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r8152: change some definitions
[deliverable/linux.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
2 * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/init.h>
11#include <linux/signal.h>
12#include <linux/slab.h>
13#include <linux/module.h>
ac718b69 14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/mii.h>
17#include <linux/ethtool.h>
18#include <linux/usb.h>
19#include <linux/crc32.h>
20#include <linux/if_vlan.h>
21#include <linux/uaccess.h>
ebc2ec48 22#include <linux/list.h>
5bd23881 23#include <linux/ip.h>
24#include <linux/ipv6.h>
ac718b69 25
26/* Version Information */
7937f9e5 27#define DRIVER_VERSION "v1.02.0 (2013/10/28)"
ac718b69 28#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
29#define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
30#define MODULENAME "r8152"
31
32#define R8152_PHY_ID 32
33
34#define PLA_IDR 0xc000
35#define PLA_RCR 0xc010
36#define PLA_RMS 0xc016
37#define PLA_RXFIFO_CTRL0 0xc0a0
38#define PLA_RXFIFO_CTRL1 0xc0a4
39#define PLA_RXFIFO_CTRL2 0xc0a8
40#define PLA_FMC 0xc0b4
41#define PLA_CFG_WOL 0xc0b6
42#define PLA_MAR 0xcd00
43#define PAL_BDC_CR 0xd1a0
44#define PLA_LEDSEL 0xdd90
45#define PLA_LED_FEATURE 0xdd92
46#define PLA_PHYAR 0xde00
47#define PLA_GPHY_INTR_IMR 0xe022
48#define PLA_EEE_CR 0xe040
49#define PLA_EEEP_CR 0xe080
50#define PLA_MAC_PWR_CTRL 0xe0c0
51#define PLA_TCR0 0xe610
52#define PLA_TCR1 0xe612
53#define PLA_TXFIFO_CTRL 0xe618
54#define PLA_RSTTELLY 0xe800
55#define PLA_CR 0xe813
56#define PLA_CRWECR 0xe81c
57#define PLA_CONFIG5 0xe822
58#define PLA_PHY_PWR 0xe84c
59#define PLA_OOB_CTRL 0xe84f
60#define PLA_CPCR 0xe854
61#define PLA_MISC_0 0xe858
62#define PLA_MISC_1 0xe85a
63#define PLA_OCP_GPHY_BASE 0xe86c
64#define PLA_TELLYCNT 0xe890
65#define PLA_SFF_STS_7 0xe8de
66#define PLA_PHYSTATUS 0xe908
67#define PLA_BP_BA 0xfc26
68#define PLA_BP_0 0xfc28
69#define PLA_BP_1 0xfc2a
70#define PLA_BP_2 0xfc2c
71#define PLA_BP_3 0xfc2e
72#define PLA_BP_4 0xfc30
73#define PLA_BP_5 0xfc32
74#define PLA_BP_6 0xfc34
75#define PLA_BP_7 0xfc36
76
77#define USB_DEV_STAT 0xb808
78#define USB_USB_CTRL 0xd406
79#define USB_PHY_CTRL 0xd408
80#define USB_TX_AGG 0xd40a
81#define USB_RX_BUF_TH 0xd40c
82#define USB_USB_TIMER 0xd428
83#define USB_PM_CTRL_STATUS 0xd432
84#define USB_TX_DMA 0xd434
85#define USB_UPS_CTRL 0xd800
86#define USB_BP_BA 0xfc26
87#define USB_BP_0 0xfc28
88#define USB_BP_1 0xfc2a
89#define USB_BP_2 0xfc2c
90#define USB_BP_3 0xfc2e
91#define USB_BP_4 0xfc30
92#define USB_BP_5 0xfc32
93#define USB_BP_6 0xfc34
94#define USB_BP_7 0xfc36
95
96/* OCP Registers */
97#define OCP_ALDPS_CONFIG 0x2010
98#define OCP_EEE_CONFIG1 0x2080
99#define OCP_EEE_CONFIG2 0x2092
100#define OCP_EEE_CONFIG3 0x2094
ac244d3e 101#define OCP_BASE_MII 0xa400
ac718b69 102#define OCP_EEE_AR 0xa41a
103#define OCP_EEE_DATA 0xa41c
104
105/* PLA_RCR */
106#define RCR_AAP 0x00000001
107#define RCR_APM 0x00000002
108#define RCR_AM 0x00000004
109#define RCR_AB 0x00000008
110#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
111
112/* PLA_RXFIFO_CTRL0 */
113#define RXFIFO_THR1_NORMAL 0x00080002
114#define RXFIFO_THR1_OOB 0x01800003
115
116/* PLA_RXFIFO_CTRL1 */
117#define RXFIFO_THR2_FULL 0x00000060
118#define RXFIFO_THR2_HIGH 0x00000038
119#define RXFIFO_THR2_OOB 0x0000004a
120
121/* PLA_RXFIFO_CTRL2 */
122#define RXFIFO_THR3_FULL 0x00000078
123#define RXFIFO_THR3_HIGH 0x00000048
124#define RXFIFO_THR3_OOB 0x0000005a
125
126/* PLA_TXFIFO_CTRL */
127#define TXFIFO_THR_NORMAL 0x00400008
128
129/* PLA_FMC */
130#define FMC_FCR_MCU_EN 0x0001
131
132/* PLA_EEEP_CR */
133#define EEEP_CR_EEEP_TX 0x0002
134
135/* PLA_TCR0 */
136#define TCR0_TX_EMPTY 0x0800
137#define TCR0_AUTO_FIFO 0x0080
138
139/* PLA_TCR1 */
140#define VERSION_MASK 0x7cf0
141
142/* PLA_CR */
143#define CR_RST 0x10
144#define CR_RE 0x08
145#define CR_TE 0x04
146
147/* PLA_CRWECR */
148#define CRWECR_NORAML 0x00
149#define CRWECR_CONFIG 0xc0
150
151/* PLA_OOB_CTRL */
152#define NOW_IS_OOB 0x80
153#define TXFIFO_EMPTY 0x20
154#define RXFIFO_EMPTY 0x10
155#define LINK_LIST_READY 0x02
156#define DIS_MCU_CLROOB 0x01
157#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
158
159/* PLA_MISC_1 */
160#define RXDY_GATED_EN 0x0008
161
162/* PLA_SFF_STS_7 */
163#define RE_INIT_LL 0x8000
164#define MCU_BORW_EN 0x4000
165
166/* PLA_CPCR */
167#define CPCR_RX_VLAN 0x0040
168
169/* PLA_CFG_WOL */
170#define MAGIC_EN 0x0001
171
172/* PAL_BDC_CR */
173#define ALDPS_PROXY_MODE 0x0001
174
175/* PLA_CONFIG5 */
176#define LAN_WAKE_EN 0x0002
177
178/* PLA_LED_FEATURE */
179#define LED_MODE_MASK 0x0700
180
181/* PLA_PHY_PWR */
182#define TX_10M_IDLE_EN 0x0080
183#define PFM_PWM_SWITCH 0x0040
184
185/* PLA_MAC_PWR_CTRL */
186#define D3_CLK_GATED_EN 0x00004000
187#define MCU_CLK_RATIO 0x07010f07
188#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
189
190/* PLA_GPHY_INTR_IMR */
191#define GPHY_STS_MSK 0x0001
192#define SPEED_DOWN_MSK 0x0002
193#define SPDWN_RXDV_MSK 0x0004
194#define SPDWN_LINKCHG_MSK 0x0008
195
196/* PLA_PHYAR */
197#define PHYAR_FLAG 0x80000000
198
199/* PLA_EEE_CR */
200#define EEE_RX_EN 0x0001
201#define EEE_TX_EN 0x0002
202
203/* USB_DEV_STAT */
204#define STAT_SPEED_MASK 0x0006
205#define STAT_SPEED_HIGH 0x0000
206#define STAT_SPEED_FULL 0x0001
207
208/* USB_TX_AGG */
209#define TX_AGG_MAX_THRESHOLD 0x03
210
211/* USB_RX_BUF_TH */
8e1f51bd 212#define RX_THR_HIGH 0x7a120180
ac718b69 213
214/* USB_TX_DMA */
215#define TEST_MODE_DISABLE 0x00000001
216#define TX_SIZE_ADJUST1 0x00000100
217
218/* USB_UPS_CTRL */
219#define POWER_CUT 0x0100
220
221/* USB_PM_CTRL_STATUS */
8e1f51bd 222#define RESUME_INDICATE 0x0001
ac718b69 223
224/* USB_USB_CTRL */
225#define RX_AGG_DISABLE 0x0010
226
227/* OCP_ALDPS_CONFIG */
228#define ENPWRSAVE 0x8000
229#define ENPDNPS 0x0200
230#define LINKENA 0x0100
231#define DIS_SDSAVE 0x0010
232
233/* OCP_EEE_CONFIG1 */
234#define RG_TXLPI_MSK_HFDUP 0x8000
235#define RG_MATCLR_EN 0x4000
236#define EEE_10_CAP 0x2000
237#define EEE_NWAY_EN 0x1000
238#define TX_QUIET_EN 0x0200
239#define RX_QUIET_EN 0x0100
240#define SDRISETIME 0x0010 /* bit 4 ~ 6 */
241#define RG_RXLPI_MSK_HFDUP 0x0008
242#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
243
244/* OCP_EEE_CONFIG2 */
245#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
246#define RG_DACQUIET_EN 0x0400
247#define RG_LDVQUIET_EN 0x0200
248#define RG_CKRSEL 0x0020
249#define RG_EEEPRG_EN 0x0010
250
251/* OCP_EEE_CONFIG3 */
252#define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
253#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
254#define MSK_PH 0x0006 /* bit 0 ~ 3 */
255
256/* OCP_EEE_AR */
257/* bit[15:14] function */
258#define FUN_ADDR 0x0000
259#define FUN_DATA 0x4000
260/* bit[4:0] device addr */
261#define DEVICE_ADDR 0x0007
262
263/* OCP_EEE_DATA */
264#define EEE_ADDR 0x003C
265#define EEE_DATA 0x0002
266
267enum rtl_register_content {
268 _100bps = 0x08,
269 _10bps = 0x04,
270 LINK_STATUS = 0x02,
271 FULL_DUP = 0x01,
272};
273
ebc2ec48 274#define RTL8152_MAX_TX 10
275#define RTL8152_MAX_RX 10
40a82917 276#define INTBUFSIZE 2
8e1f51bd 277#define CRC_SIZE 4
278#define TX_ALIGN 4
279#define RX_ALIGN 8
40a82917 280
281#define INTR_LINK 0x0004
ebc2ec48 282
ac718b69 283#define RTL8152_REQT_READ 0xc0
284#define RTL8152_REQT_WRITE 0x40
285#define RTL8152_REQ_GET_REGS 0x05
286#define RTL8152_REQ_SET_REGS 0x05
287
288#define BYTE_EN_DWORD 0xff
289#define BYTE_EN_WORD 0x33
290#define BYTE_EN_BYTE 0x11
291#define BYTE_EN_SIX_BYTES 0x3f
292#define BYTE_EN_START_MASK 0x0f
293#define BYTE_EN_END_MASK 0xf0
294
295#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
296#define RTL8152_TX_TIMEOUT (HZ)
297
298/* rtl8152 flags */
299enum rtl8152_flags {
300 RTL8152_UNPLUG = 0,
ac718b69 301 RTL8152_SET_RX_MODE,
40a82917 302 WORK_ENABLE,
303 RTL8152_LINK_CHG,
ac718b69 304};
305
306/* Define these values to match your device */
307#define VENDOR_ID_REALTEK 0x0bda
308#define PRODUCT_ID_RTL8152 0x8152
309
310#define MCU_TYPE_PLA 0x0100
311#define MCU_TYPE_USB 0x0000
312
313struct rx_desc {
500b6d7e 314 __le32 opts1;
ac718b69 315#define RX_LEN_MASK 0x7fff
500b6d7e 316 __le32 opts2;
317 __le32 opts3;
318 __le32 opts4;
319 __le32 opts5;
320 __le32 opts6;
ac718b69 321};
322
323struct tx_desc {
500b6d7e 324 __le32 opts1;
ac718b69 325#define TX_FS (1 << 31) /* First segment of a packet */
326#define TX_LS (1 << 30) /* Final segment of a packet */
5bd23881 327#define TX_LEN_MASK 0x3ffff
328
500b6d7e 329 __le32 opts2;
5bd23881 330#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
331#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
332#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
333#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
ac718b69 334};
335
dff4e8ad 336struct r8152;
337
ebc2ec48 338struct rx_agg {
339 struct list_head list;
340 struct urb *urb;
dff4e8ad 341 struct r8152 *context;
ebc2ec48 342 void *buffer;
343 void *head;
344};
345
346struct tx_agg {
347 struct list_head list;
348 struct urb *urb;
dff4e8ad 349 struct r8152 *context;
ebc2ec48 350 void *buffer;
351 void *head;
352 u32 skb_num;
353 u32 skb_len;
354};
355
ac718b69 356struct r8152 {
357 unsigned long flags;
358 struct usb_device *udev;
359 struct tasklet_struct tl;
40a82917 360 struct usb_interface *intf;
ac718b69 361 struct net_device *netdev;
40a82917 362 struct urb *intr_urb;
ebc2ec48 363 struct tx_agg tx_info[RTL8152_MAX_TX];
364 struct rx_agg rx_info[RTL8152_MAX_RX];
365 struct list_head rx_done, tx_free;
366 struct sk_buff_head tx_queue;
367 spinlock_t rx_lock, tx_lock;
ac718b69 368 struct delayed_work schedule;
369 struct mii_if_info mii;
40a82917 370 int intr_interval;
ac718b69 371 u32 msg_enable;
dd1b119c 372 u32 tx_qlen;
ac718b69 373 u16 ocp_base;
40a82917 374 u8 *intr_buff;
ac718b69 375 u8 version;
376 u8 speed;
377};
378
379enum rtl_version {
380 RTL_VER_UNKNOWN = 0,
381 RTL_VER_01,
382 RTL_VER_02
383};
384
385/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
386 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
387 */
388static const int multicast_filter_limit = 32;
ebc2ec48 389static unsigned int rx_buf_sz = 16384;
ac718b69 390
391static
392int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
393{
31787f53 394 int ret;
395 void *tmp;
396
397 tmp = kmalloc(size, GFP_KERNEL);
398 if (!tmp)
399 return -ENOMEM;
400
401 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
ac718b69 402 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
31787f53 403 value, index, tmp, size, 500);
404
405 memcpy(data, tmp, size);
406 kfree(tmp);
407
408 return ret;
ac718b69 409}
410
411static
412int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
413{
31787f53 414 int ret;
415 void *tmp;
416
417 tmp = kmalloc(size, GFP_KERNEL);
418 if (!tmp)
419 return -ENOMEM;
420
421 memcpy(tmp, data, size);
422
423 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
ac718b69 424 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
31787f53 425 value, index, tmp, size, 500);
426
427 kfree(tmp);
428 return ret;
ac718b69 429}
430
431static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
432 void *data, u16 type)
433{
434 u16 limit = 64;
435 int ret = 0;
436
437 if (test_bit(RTL8152_UNPLUG, &tp->flags))
438 return -ENODEV;
439
440 /* both size and indix must be 4 bytes align */
441 if ((size & 3) || !size || (index & 3) || !data)
442 return -EPERM;
443
444 if ((u32)index + (u32)size > 0xffff)
445 return -EPERM;
446
447 while (size) {
448 if (size > limit) {
449 ret = get_registers(tp, index, type, limit, data);
450 if (ret < 0)
451 break;
452
453 index += limit;
454 data += limit;
455 size -= limit;
456 } else {
457 ret = get_registers(tp, index, type, size, data);
458 if (ret < 0)
459 break;
460
461 index += size;
462 data += size;
463 size = 0;
464 break;
465 }
466 }
467
468 return ret;
469}
470
471static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
472 u16 size, void *data, u16 type)
473{
474 int ret;
475 u16 byteen_start, byteen_end, byen;
476 u16 limit = 512;
477
478 if (test_bit(RTL8152_UNPLUG, &tp->flags))
479 return -ENODEV;
480
481 /* both size and indix must be 4 bytes align */
482 if ((size & 3) || !size || (index & 3) || !data)
483 return -EPERM;
484
485 if ((u32)index + (u32)size > 0xffff)
486 return -EPERM;
487
488 byteen_start = byteen & BYTE_EN_START_MASK;
489 byteen_end = byteen & BYTE_EN_END_MASK;
490
491 byen = byteen_start | (byteen_start << 4);
492 ret = set_registers(tp, index, type | byen, 4, data);
493 if (ret < 0)
494 goto error1;
495
496 index += 4;
497 data += 4;
498 size -= 4;
499
500 if (size) {
501 size -= 4;
502
503 while (size) {
504 if (size > limit) {
505 ret = set_registers(tp, index,
506 type | BYTE_EN_DWORD,
507 limit, data);
508 if (ret < 0)
509 goto error1;
510
511 index += limit;
512 data += limit;
513 size -= limit;
514 } else {
515 ret = set_registers(tp, index,
516 type | BYTE_EN_DWORD,
517 size, data);
518 if (ret < 0)
519 goto error1;
520
521 index += size;
522 data += size;
523 size = 0;
524 break;
525 }
526 }
527
528 byen = byteen_end | (byteen_end >> 4);
529 ret = set_registers(tp, index, type | byen, 4, data);
530 if (ret < 0)
531 goto error1;
532 }
533
534error1:
535 return ret;
536}
537
538static inline
539int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
540{
541 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
542}
543
544static inline
545int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
546{
547 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
548}
549
550static inline
551int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
552{
553 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
554}
555
556static inline
557int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
558{
559 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
560}
561
562static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
563{
c8826de8 564 __le32 data;
ac718b69 565
c8826de8 566 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 567
568 return __le32_to_cpu(data);
569}
570
571static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
572{
c8826de8 573 __le32 tmp = __cpu_to_le32(data);
574
575 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 576}
577
578static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
579{
580 u32 data;
c8826de8 581 __le32 tmp;
ac718b69 582 u8 shift = index & 2;
583
584 index &= ~3;
585
c8826de8 586 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 587
c8826de8 588 data = __le32_to_cpu(tmp);
ac718b69 589 data >>= (shift * 8);
590 data &= 0xffff;
591
592 return (u16)data;
593}
594
595static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
596{
c8826de8 597 u32 mask = 0xffff;
598 __le32 tmp;
ac718b69 599 u16 byen = BYTE_EN_WORD;
600 u8 shift = index & 2;
601
602 data &= mask;
603
604 if (index & 2) {
605 byen <<= shift;
606 mask <<= (shift * 8);
607 data <<= (shift * 8);
608 index &= ~3;
609 }
610
c8826de8 611 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 612
c8826de8 613 data |= __le32_to_cpu(tmp) & ~mask;
614 tmp = __cpu_to_le32(data);
ac718b69 615
c8826de8 616 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 617}
618
619static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
620{
621 u32 data;
c8826de8 622 __le32 tmp;
ac718b69 623 u8 shift = index & 3;
624
625 index &= ~3;
626
c8826de8 627 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 628
c8826de8 629 data = __le32_to_cpu(tmp);
ac718b69 630 data >>= (shift * 8);
631 data &= 0xff;
632
633 return (u8)data;
634}
635
636static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
637{
c8826de8 638 u32 mask = 0xff;
639 __le32 tmp;
ac718b69 640 u16 byen = BYTE_EN_BYTE;
641 u8 shift = index & 3;
642
643 data &= mask;
644
645 if (index & 3) {
646 byen <<= shift;
647 mask <<= (shift * 8);
648 data <<= (shift * 8);
649 index &= ~3;
650 }
651
c8826de8 652 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 653
c8826de8 654 data |= __le32_to_cpu(tmp) & ~mask;
655 tmp = __cpu_to_le32(data);
ac718b69 656
c8826de8 657 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 658}
659
ac244d3e 660static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 661{
662 u16 ocp_base, ocp_index;
663
664 ocp_base = addr & 0xf000;
665 if (ocp_base != tp->ocp_base) {
666 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
667 tp->ocp_base = ocp_base;
668 }
669
670 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 671 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 672}
673
ac244d3e 674static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 675{
ac244d3e 676 u16 ocp_base, ocp_index;
ac718b69 677
ac244d3e 678 ocp_base = addr & 0xf000;
679 if (ocp_base != tp->ocp_base) {
680 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
681 tp->ocp_base = ocp_base;
ac718b69 682 }
ac244d3e 683
684 ocp_index = (addr & 0x0fff) | 0xb000;
685 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 686}
687
ac244d3e 688static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 689{
ac244d3e 690 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
691}
ac718b69 692
ac244d3e 693static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
694{
695 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 696}
697
698static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
699{
700 struct r8152 *tp = netdev_priv(netdev);
701
702 if (phy_id != R8152_PHY_ID)
703 return -EINVAL;
704
705 return r8152_mdio_read(tp, reg);
706}
707
708static
709void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
710{
711 struct r8152 *tp = netdev_priv(netdev);
712
713 if (phy_id != R8152_PHY_ID)
714 return;
715
716 r8152_mdio_write(tp, reg, val);
717}
718
ebc2ec48 719static
720int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
721
ac718b69 722static inline void set_ethernet_addr(struct r8152 *tp)
723{
724 struct net_device *dev = tp->netdev;
31787f53 725 u8 node_id[8] = {0};
ac718b69 726
31787f53 727 if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
ac718b69 728 netif_notice(tp, probe, dev, "inet addr fail\n");
729 else {
730 memcpy(dev->dev_addr, node_id, dev->addr_len);
731 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
732 }
ac718b69 733}
734
735static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
736{
737 struct r8152 *tp = netdev_priv(netdev);
738 struct sockaddr *addr = p;
739
740 if (!is_valid_ether_addr(addr->sa_data))
741 return -EADDRNOTAVAIL;
742
743 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
744
745 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
746 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
747 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
748
749 return 0;
750}
751
ac718b69 752static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
753{
754 return &dev->stats;
755}
756
757static void read_bulk_callback(struct urb *urb)
758{
ac718b69 759 struct net_device *netdev;
a5a4f468 760 unsigned long flags;
ac718b69 761 int status = urb->status;
ebc2ec48 762 struct rx_agg *agg;
763 struct r8152 *tp;
ac718b69 764 int result;
ac718b69 765
ebc2ec48 766 agg = urb->context;
767 if (!agg)
768 return;
769
770 tp = agg->context;
ac718b69 771 if (!tp)
772 return;
ebc2ec48 773
ac718b69 774 if (test_bit(RTL8152_UNPLUG, &tp->flags))
775 return;
ebc2ec48 776
777 if (!test_bit(WORK_ENABLE, &tp->flags))
778 return;
779
ac718b69 780 netdev = tp->netdev;
7559fb2f 781
782 /* When link down, the driver would cancel all bulks. */
783 /* This avoid the re-submitting bulk */
ebc2ec48 784 if (!netif_carrier_ok(netdev))
ac718b69 785 return;
786
ac718b69 787 switch (status) {
788 case 0:
ebc2ec48 789 if (urb->actual_length < ETH_ZLEN)
790 break;
791
a5a4f468 792 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 793 list_add_tail(&agg->list, &tp->rx_done);
a5a4f468 794 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 795 tasklet_schedule(&tp->tl);
796 return;
ac718b69 797 case -ESHUTDOWN:
798 set_bit(RTL8152_UNPLUG, &tp->flags);
799 netif_device_detach(tp->netdev);
ebc2ec48 800 return;
ac718b69 801 case -ENOENT:
802 return; /* the urb is in unlink state */
803 case -ETIME:
804 pr_warn_ratelimited("may be reset is needed?..\n");
ebc2ec48 805 break;
ac718b69 806 default:
807 pr_warn_ratelimited("Rx status %d\n", status);
ebc2ec48 808 break;
ac718b69 809 }
810
ebc2ec48 811 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 812 if (result == -ENODEV) {
813 netif_device_detach(tp->netdev);
814 } else if (result) {
a5a4f468 815 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 816 list_add_tail(&agg->list, &tp->rx_done);
a5a4f468 817 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 818 tasklet_schedule(&tp->tl);
ac718b69 819 }
ac718b69 820}
821
ebc2ec48 822static void write_bulk_callback(struct urb *urb)
ac718b69 823{
ebc2ec48 824 struct net_device_stats *stats;
a5a4f468 825 unsigned long flags;
ebc2ec48 826 struct tx_agg *agg;
ac718b69 827 struct r8152 *tp;
ebc2ec48 828 int status = urb->status;
ac718b69 829
ebc2ec48 830 agg = urb->context;
831 if (!agg)
ac718b69 832 return;
833
ebc2ec48 834 tp = agg->context;
835 if (!tp)
836 return;
837
838 stats = rtl8152_get_stats(tp->netdev);
839 if (status) {
840 pr_warn_ratelimited("Tx status %d\n", status);
841 stats->tx_errors += agg->skb_num;
ac718b69 842 } else {
ebc2ec48 843 stats->tx_packets += agg->skb_num;
844 stats->tx_bytes += agg->skb_len;
ac718b69 845 }
846
a5a4f468 847 spin_lock_irqsave(&tp->tx_lock, flags);
ebc2ec48 848 list_add_tail(&agg->list, &tp->tx_free);
a5a4f468 849 spin_unlock_irqrestore(&tp->tx_lock, flags);
ebc2ec48 850
851 if (!netif_carrier_ok(tp->netdev))
852 return;
853
854 if (!test_bit(WORK_ENABLE, &tp->flags))
855 return;
856
857 if (test_bit(RTL8152_UNPLUG, &tp->flags))
858 return;
859
860 if (!skb_queue_empty(&tp->tx_queue))
861 tasklet_schedule(&tp->tl);
ac718b69 862}
863
40a82917 864static void intr_callback(struct urb *urb)
865{
866 struct r8152 *tp;
500b6d7e 867 __le16 *d;
40a82917 868 int status = urb->status;
869 int res;
870
871 tp = urb->context;
872 if (!tp)
873 return;
874
875 if (!test_bit(WORK_ENABLE, &tp->flags))
876 return;
877
878 if (test_bit(RTL8152_UNPLUG, &tp->flags))
879 return;
880
881 switch (status) {
882 case 0: /* success */
883 break;
884 case -ECONNRESET: /* unlink */
885 case -ESHUTDOWN:
886 netif_device_detach(tp->netdev);
887 case -ENOENT:
888 return;
889 case -EOVERFLOW:
890 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
891 goto resubmit;
892 /* -EPIPE: should clear the halt */
893 default:
894 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
895 goto resubmit;
896 }
897
898 d = urb->transfer_buffer;
899 if (INTR_LINK & __le16_to_cpu(d[0])) {
900 if (!(tp->speed & LINK_STATUS)) {
901 set_bit(RTL8152_LINK_CHG, &tp->flags);
902 schedule_delayed_work(&tp->schedule, 0);
903 }
904 } else {
905 if (tp->speed & LINK_STATUS) {
906 set_bit(RTL8152_LINK_CHG, &tp->flags);
907 schedule_delayed_work(&tp->schedule, 0);
908 }
909 }
910
911resubmit:
912 res = usb_submit_urb(urb, GFP_ATOMIC);
913 if (res == -ENODEV)
914 netif_device_detach(tp->netdev);
915 else if (res)
916 netif_err(tp, intr, tp->netdev,
917 "can't resubmit intr, status %d\n", res);
918}
919
ebc2ec48 920static inline void *rx_agg_align(void *data)
921{
8e1f51bd 922 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 923}
924
925static inline void *tx_agg_align(void *data)
926{
8e1f51bd 927 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 928}
929
930static void free_all_mem(struct r8152 *tp)
931{
932 int i;
933
934 for (i = 0; i < RTL8152_MAX_RX; i++) {
935 if (tp->rx_info[i].urb) {
936 usb_free_urb(tp->rx_info[i].urb);
937 tp->rx_info[i].urb = NULL;
938 }
939
940 if (tp->rx_info[i].buffer) {
941 kfree(tp->rx_info[i].buffer);
942 tp->rx_info[i].buffer = NULL;
943 tp->rx_info[i].head = NULL;
944 }
945 }
946
947 for (i = 0; i < RTL8152_MAX_TX; i++) {
948 if (tp->tx_info[i].urb) {
949 usb_free_urb(tp->tx_info[i].urb);
950 tp->tx_info[i].urb = NULL;
951 }
952
953 if (tp->tx_info[i].buffer) {
954 kfree(tp->tx_info[i].buffer);
955 tp->tx_info[i].buffer = NULL;
956 tp->tx_info[i].head = NULL;
957 }
958 }
40a82917 959
960 if (tp->intr_urb) {
961 usb_free_urb(tp->intr_urb);
962 tp->intr_urb = NULL;
963 }
964
965 if (tp->intr_buff) {
966 kfree(tp->intr_buff);
967 tp->intr_buff = NULL;
968 }
ebc2ec48 969}
970
971static int alloc_all_mem(struct r8152 *tp)
972{
973 struct net_device *netdev = tp->netdev;
40a82917 974 struct usb_interface *intf = tp->intf;
975 struct usb_host_interface *alt = intf->cur_altsetting;
976 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 977 struct urb *urb;
978 int node, i;
979 u8 *buf;
980
981 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
982
983 spin_lock_init(&tp->rx_lock);
984 spin_lock_init(&tp->tx_lock);
985 INIT_LIST_HEAD(&tp->rx_done);
986 INIT_LIST_HEAD(&tp->tx_free);
987 skb_queue_head_init(&tp->tx_queue);
988
989 for (i = 0; i < RTL8152_MAX_RX; i++) {
990 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
991 if (!buf)
992 goto err1;
993
994 if (buf != rx_agg_align(buf)) {
995 kfree(buf);
8e1f51bd 996 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
997 node);
ebc2ec48 998 if (!buf)
999 goto err1;
1000 }
1001
1002 urb = usb_alloc_urb(0, GFP_KERNEL);
1003 if (!urb) {
1004 kfree(buf);
1005 goto err1;
1006 }
1007
1008 INIT_LIST_HEAD(&tp->rx_info[i].list);
1009 tp->rx_info[i].context = tp;
1010 tp->rx_info[i].urb = urb;
1011 tp->rx_info[i].buffer = buf;
1012 tp->rx_info[i].head = rx_agg_align(buf);
1013 }
1014
1015 for (i = 0; i < RTL8152_MAX_TX; i++) {
1016 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1017 if (!buf)
1018 goto err1;
1019
1020 if (buf != tx_agg_align(buf)) {
1021 kfree(buf);
8e1f51bd 1022 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1023 node);
ebc2ec48 1024 if (!buf)
1025 goto err1;
1026 }
1027
1028 urb = usb_alloc_urb(0, GFP_KERNEL);
1029 if (!urb) {
1030 kfree(buf);
1031 goto err1;
1032 }
1033
1034 INIT_LIST_HEAD(&tp->tx_info[i].list);
1035 tp->tx_info[i].context = tp;
1036 tp->tx_info[i].urb = urb;
1037 tp->tx_info[i].buffer = buf;
1038 tp->tx_info[i].head = tx_agg_align(buf);
1039
1040 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1041 }
1042
40a82917 1043 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1044 if (!tp->intr_urb)
1045 goto err1;
1046
1047 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1048 if (!tp->intr_buff)
1049 goto err1;
1050
1051 tp->intr_interval = (int)ep_intr->desc.bInterval;
1052 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1053 tp->intr_buff, INTBUFSIZE, intr_callback,
1054 tp, tp->intr_interval);
1055
ebc2ec48 1056 return 0;
1057
1058err1:
1059 free_all_mem(tp);
1060 return -ENOMEM;
1061}
1062
0de98f6c 1063static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1064{
1065 struct tx_agg *agg = NULL;
1066 unsigned long flags;
1067
1068 spin_lock_irqsave(&tp->tx_lock, flags);
1069 if (!list_empty(&tp->tx_free)) {
1070 struct list_head *cursor;
1071
1072 cursor = tp->tx_free.next;
1073 list_del_init(cursor);
1074 agg = list_entry(cursor, struct tx_agg, list);
1075 }
1076 spin_unlock_irqrestore(&tp->tx_lock, flags);
1077
1078 return agg;
1079}
1080
5bd23881 1081static void
1082r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1083{
1084 memset(desc, 0, sizeof(*desc));
1085
1086 desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1087
1088 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1089 __be16 protocol;
1090 u8 ip_protocol;
1091 u32 opts2 = 0;
1092
1093 if (skb->protocol == htons(ETH_P_8021Q))
1094 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1095 else
1096 protocol = skb->protocol;
1097
1098 switch (protocol) {
1099 case htons(ETH_P_IP):
1100 opts2 |= IPV4_CS;
1101 ip_protocol = ip_hdr(skb)->protocol;
1102 break;
1103
1104 case htons(ETH_P_IPV6):
1105 opts2 |= IPV6_CS;
1106 ip_protocol = ipv6_hdr(skb)->nexthdr;
1107 break;
1108
1109 default:
1110 ip_protocol = IPPROTO_RAW;
1111 break;
1112 }
1113
1114 if (ip_protocol == IPPROTO_TCP) {
1115 opts2 |= TCP_CS;
1116 opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1117 } else if (ip_protocol == IPPROTO_UDP) {
1118 opts2 |= UDP_CS;
1119 } else {
1120 WARN_ON_ONCE(1);
1121 }
1122
1123 desc->opts2 = cpu_to_le32(opts2);
1124 }
1125}
1126
b1379d9a 1127static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1128{
7937f9e5 1129 int remain;
b1379d9a 1130 u8 *tx_data;
1131
1132 tx_data = agg->head;
1133 agg->skb_num = agg->skb_len = 0;
7937f9e5 1134 remain = rx_buf_sz;
b1379d9a 1135
7937f9e5 1136 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1137 struct tx_desc *tx_desc;
1138 struct sk_buff *skb;
1139 unsigned int len;
1140
1141 skb = skb_dequeue(&tp->tx_queue);
1142 if (!skb)
1143 break;
1144
7937f9e5 1145 remain -= sizeof(*tx_desc);
b1379d9a 1146 len = skb->len;
1147 if (remain < len) {
1148 skb_queue_head(&tp->tx_queue, skb);
1149 break;
1150 }
1151
7937f9e5 1152 tx_data = tx_agg_align(tx_data);
b1379d9a 1153 tx_desc = (struct tx_desc *)tx_data;
1154 tx_data += sizeof(*tx_desc);
1155
1156 r8152_tx_csum(tp, tx_desc, skb);
1157 memcpy(tx_data, skb->data, len);
1158 agg->skb_num++;
1159 agg->skb_len += len;
1160 dev_kfree_skb_any(skb);
1161
7937f9e5 1162 tx_data += len;
1163 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1164 }
1165
dd1b119c 1166 netif_tx_lock(tp->netdev);
1167
1168 if (netif_queue_stopped(tp->netdev) &&
1169 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1170 netif_wake_queue(tp->netdev);
1171
1172 netif_tx_unlock(tp->netdev);
1173
b1379d9a 1174 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1175 agg->head, (int)(tx_data - (u8 *)agg->head),
1176 (usb_complete_t)write_bulk_callback, agg);
1177
1178 return usb_submit_urb(agg->urb, GFP_ATOMIC);
1179}
1180
ebc2ec48 1181static void rx_bottom(struct r8152 *tp)
1182{
a5a4f468 1183 unsigned long flags;
ebc2ec48 1184 struct list_head *cursor, *next;
ebc2ec48 1185
a5a4f468 1186 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 1187 list_for_each_safe(cursor, next, &tp->rx_done) {
43a4478d 1188 struct rx_desc *rx_desc;
1189 struct rx_agg *agg;
43a4478d 1190 int len_used = 0;
1191 struct urb *urb;
1192 u8 *rx_data;
1193 int ret;
1194
ebc2ec48 1195 list_del_init(cursor);
a5a4f468 1196 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1197
1198 agg = list_entry(cursor, struct rx_agg, list);
1199 urb = agg->urb;
0de98f6c 1200 if (urb->actual_length < ETH_ZLEN)
1201 goto submit;
ebc2ec48 1202
ebc2ec48 1203 rx_desc = agg->head;
1204 rx_data = agg->head;
7937f9e5 1205 len_used += sizeof(struct rx_desc);
ebc2ec48 1206
7937f9e5 1207 while (urb->actual_length > len_used) {
43a4478d 1208 struct net_device *netdev = tp->netdev;
1209 struct net_device_stats *stats;
7937f9e5 1210 unsigned int pkt_len;
43a4478d 1211 struct sk_buff *skb;
1212
7937f9e5 1213 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1214 if (pkt_len < ETH_ZLEN)
1215 break;
1216
7937f9e5 1217 len_used += pkt_len;
1218 if (urb->actual_length < len_used)
1219 break;
1220
43a4478d 1221 stats = rtl8152_get_stats(netdev);
1222
8e1f51bd 1223 pkt_len -= CRC_SIZE;
ebc2ec48 1224 rx_data += sizeof(struct rx_desc);
1225
1226 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1227 if (!skb) {
1228 stats->rx_dropped++;
1229 break;
1230 }
1231 memcpy(skb->data, rx_data, pkt_len);
1232 skb_put(skb, pkt_len);
1233 skb->protocol = eth_type_trans(skb, netdev);
1234 netif_rx(skb);
1235 stats->rx_packets++;
1236 stats->rx_bytes += pkt_len;
1237
8e1f51bd 1238 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1239 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1240 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1241 len_used += sizeof(struct rx_desc);
ebc2ec48 1242 }
1243
0de98f6c 1244submit:
ebc2ec48 1245 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
a5a4f468 1246 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 1247 if (ret && ret != -ENODEV) {
1248 list_add_tail(&agg->list, next);
1249 tasklet_schedule(&tp->tl);
1250 }
1251 }
a5a4f468 1252 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1253}
1254
1255static void tx_bottom(struct r8152 *tp)
1256{
ebc2ec48 1257 int res;
1258
b1379d9a 1259 do {
1260 struct tx_agg *agg;
ebc2ec48 1261
b1379d9a 1262 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1263 break;
1264
b1379d9a 1265 agg = r8152_get_tx_agg(tp);
1266 if (!agg)
ebc2ec48 1267 break;
ebc2ec48 1268
b1379d9a 1269 res = r8152_tx_agg_fill(tp, agg);
1270 if (res) {
1271 struct net_device_stats *stats;
1272 struct net_device *netdev;
1273 unsigned long flags;
ebc2ec48 1274
b1379d9a 1275 netdev = tp->netdev;
1276 stats = rtl8152_get_stats(netdev);
ebc2ec48 1277
b1379d9a 1278 if (res == -ENODEV) {
1279 netif_device_detach(netdev);
1280 } else {
1281 netif_warn(tp, tx_err, netdev,
1282 "failed tx_urb %d\n", res);
1283 stats->tx_dropped += agg->skb_num;
1284 spin_lock_irqsave(&tp->tx_lock, flags);
1285 list_add_tail(&agg->list, &tp->tx_free);
1286 spin_unlock_irqrestore(&tp->tx_lock, flags);
1287 }
ebc2ec48 1288 }
b1379d9a 1289 } while (res == 0);
ebc2ec48 1290}
1291
1292static void bottom_half(unsigned long data)
ac718b69 1293{
1294 struct r8152 *tp;
ac718b69 1295
ebc2ec48 1296 tp = (struct r8152 *)data;
1297
1298 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1299 return;
1300
1301 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1302 return;
ebc2ec48 1303
7559fb2f 1304 /* When link down, the driver would cancel all bulks. */
1305 /* This avoid the re-submitting bulk */
ebc2ec48 1306 if (!netif_carrier_ok(tp->netdev))
ac718b69 1307 return;
ebc2ec48 1308
1309 rx_bottom(tp);
1310 tx_bottom(tp);
1311}
1312
1313static
1314int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1315{
1316 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1317 agg->head, rx_buf_sz,
1318 (usb_complete_t)read_bulk_callback, agg);
1319
1320 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1321}
1322
1323static void rtl8152_tx_timeout(struct net_device *netdev)
1324{
1325 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1326 int i;
1327
ac718b69 1328 netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
ebc2ec48 1329 for (i = 0; i < RTL8152_MAX_TX; i++)
1330 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1331}
1332
1333static void rtl8152_set_rx_mode(struct net_device *netdev)
1334{
1335 struct r8152 *tp = netdev_priv(netdev);
1336
40a82917 1337 if (tp->speed & LINK_STATUS) {
ac718b69 1338 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1339 schedule_delayed_work(&tp->schedule, 0);
1340 }
ac718b69 1341}
1342
1343static void _rtl8152_set_rx_mode(struct net_device *netdev)
1344{
1345 struct r8152 *tp = netdev_priv(netdev);
31787f53 1346 u32 mc_filter[2]; /* Multicast hash filter */
1347 __le32 tmp[2];
ac718b69 1348 u32 ocp_data;
1349
ac718b69 1350 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1351 netif_stop_queue(netdev);
1352 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1353 ocp_data &= ~RCR_ACPT_ALL;
1354 ocp_data |= RCR_AB | RCR_APM;
1355
1356 if (netdev->flags & IFF_PROMISC) {
1357 /* Unconditionally log net taps. */
1358 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1359 ocp_data |= RCR_AM | RCR_AAP;
1360 mc_filter[1] = mc_filter[0] = 0xffffffff;
1361 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1362 (netdev->flags & IFF_ALLMULTI)) {
1363 /* Too many to filter perfectly -- accept all multicasts. */
1364 ocp_data |= RCR_AM;
1365 mc_filter[1] = mc_filter[0] = 0xffffffff;
1366 } else {
1367 struct netdev_hw_addr *ha;
1368
1369 mc_filter[1] = mc_filter[0] = 0;
1370 netdev_for_each_mc_addr(ha, netdev) {
1371 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1372 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1373 ocp_data |= RCR_AM;
1374 }
1375 }
1376
31787f53 1377 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1378 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1379
31787f53 1380 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1381 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1382 netif_wake_queue(netdev);
ac718b69 1383}
1384
1385static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1386 struct net_device *netdev)
1387{
1388 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1389
ebc2ec48 1390 skb_tx_timestamp(skb);
ac718b69 1391
61598788 1392 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1393
dd1b119c 1394 if (list_empty(&tp->tx_free) &&
1395 skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1396 netif_stop_queue(netdev);
1397
61598788 1398 if (!list_empty(&tp->tx_free))
1399 tasklet_schedule(&tp->tl);
ac718b69 1400
1401 return NETDEV_TX_OK;
1402}
1403
1404static void r8152b_reset_packet_filter(struct r8152 *tp)
1405{
1406 u32 ocp_data;
1407
1408 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1409 ocp_data &= ~FMC_FCR_MCU_EN;
1410 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1411 ocp_data |= FMC_FCR_MCU_EN;
1412 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1413}
1414
1415static void rtl8152_nic_reset(struct r8152 *tp)
1416{
1417 int i;
1418
1419 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1420
1421 for (i = 0; i < 1000; i++) {
1422 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1423 break;
1424 udelay(100);
1425 }
1426}
1427
dd1b119c 1428static void set_tx_qlen(struct r8152 *tp)
1429{
1430 struct net_device *netdev = tp->netdev;
1431
1432 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1433 sizeof(struct tx_desc));
1434}
1435
ac718b69 1436static inline u8 rtl8152_get_speed(struct r8152 *tp)
1437{
1438 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1439}
1440
1441static int rtl8152_enable(struct r8152 *tp)
1442{
ebc2ec48 1443 u32 ocp_data;
1444 int i, ret;
ac718b69 1445 u8 speed;
1446
dd1b119c 1447 set_tx_qlen(tp);
ac718b69 1448 speed = rtl8152_get_speed(tp);
ebc2ec48 1449 if (speed & _10bps) {
ac718b69 1450 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1451 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1452 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1453 } else {
1454 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1455 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1457 }
1458
1459 r8152b_reset_packet_filter(tp);
1460
1461 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1462 ocp_data |= CR_RE | CR_TE;
1463 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1464
1465 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1466 ocp_data &= ~RXDY_GATED_EN;
1467 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1468
ebc2ec48 1469 INIT_LIST_HEAD(&tp->rx_done);
1470 ret = 0;
1471 for (i = 0; i < RTL8152_MAX_RX; i++) {
1472 INIT_LIST_HEAD(&tp->rx_info[i].list);
1473 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1474 }
ac718b69 1475
ebc2ec48 1476 return ret;
ac718b69 1477}
1478
1479static void rtl8152_disable(struct r8152 *tp)
1480{
ebc2ec48 1481 struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
1482 struct sk_buff *skb;
1483 u32 ocp_data;
1484 int i;
ac718b69 1485
1486 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1487 ocp_data &= ~RCR_ACPT_ALL;
1488 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1489
ebc2ec48 1490 while ((skb = skb_dequeue(&tp->tx_queue))) {
1491 dev_kfree_skb(skb);
1492 stats->tx_dropped++;
1493 }
1494
1495 for (i = 0; i < RTL8152_MAX_TX; i++)
1496 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 1497
1498 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1499 ocp_data |= RXDY_GATED_EN;
1500 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1501
1502 for (i = 0; i < 1000; i++) {
1503 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1504 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1505 break;
1506 mdelay(1);
1507 }
1508
1509 for (i = 0; i < 1000; i++) {
1510 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1511 break;
1512 mdelay(1);
1513 }
1514
ebc2ec48 1515 for (i = 0; i < RTL8152_MAX_RX; i++)
1516 usb_kill_urb(tp->rx_info[i].urb);
ac718b69 1517
1518 rtl8152_nic_reset(tp);
1519}
1520
1521static void r8152b_exit_oob(struct r8152 *tp)
1522{
1523 u32 ocp_data;
1524 int i;
1525
1526 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1527 ocp_data &= ~RCR_ACPT_ALL;
1528 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1529
1530 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1531 ocp_data |= RXDY_GATED_EN;
1532 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1533
1534 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1535 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
1536
1537 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1538 ocp_data &= ~NOW_IS_OOB;
1539 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1540
1541 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1542 ocp_data &= ~MCU_BORW_EN;
1543 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1544
1545 for (i = 0; i < 1000; i++) {
1546 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1547 if (ocp_data & LINK_LIST_READY)
1548 break;
1549 mdelay(1);
1550 }
1551
1552 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1553 ocp_data |= RE_INIT_LL;
1554 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1555
1556 for (i = 0; i < 1000; i++) {
1557 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1558 if (ocp_data & LINK_LIST_READY)
1559 break;
1560 mdelay(1);
1561 }
1562
1563 rtl8152_nic_reset(tp);
1564
1565 /* rx share fifo credit full threshold */
1566 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
1567
1568 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
1569 ocp_data &= STAT_SPEED_MASK;
1570 if (ocp_data == STAT_SPEED_FULL) {
1571 /* rx share fifo credit near full threshold */
1572 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1573 RXFIFO_THR2_FULL);
1574 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1575 RXFIFO_THR3_FULL);
1576 } else {
1577 /* rx share fifo credit near full threshold */
1578 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1579 RXFIFO_THR2_HIGH);
1580 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1581 RXFIFO_THR3_HIGH);
1582 }
1583
1584 /* TX share fifo free credit full threshold */
1585 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1586
1587 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 1588 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 1589 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
1590 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
1591
1592 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1593 ocp_data &= ~CPCR_RX_VLAN;
1594 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1595
1596 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1597
1598 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
1599 ocp_data |= TCR0_AUTO_FIFO;
1600 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
1601}
1602
1603static void r8152b_enter_oob(struct r8152 *tp)
1604{
1605 u32 ocp_data;
1606 int i;
1607
1608 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1609 ocp_data &= ~NOW_IS_OOB;
1610 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1611
1612 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
1613 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
1614 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
1615
1616 rtl8152_disable(tp);
1617
1618 for (i = 0; i < 1000; i++) {
1619 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1620 if (ocp_data & LINK_LIST_READY)
1621 break;
1622 mdelay(1);
1623 }
1624
1625 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1626 ocp_data |= RE_INIT_LL;
1627 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1628
1629 for (i = 0; i < 1000; i++) {
1630 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1631 if (ocp_data & LINK_LIST_READY)
1632 break;
1633 mdelay(1);
1634 }
1635
1636 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1637
1638 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1639 ocp_data |= MAGIC_EN;
1640 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1641
1642 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1643 ocp_data |= CPCR_RX_VLAN;
1644 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1645
1646 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
1647 ocp_data |= ALDPS_PROXY_MODE;
1648 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
1649
1650 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1651 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
1652 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1653
1654 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
1655
1656 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1657 ocp_data &= ~RXDY_GATED_EN;
1658 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1659
1660 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1661 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1662 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1663}
1664
1665static void r8152b_disable_aldps(struct r8152 *tp)
1666{
1667 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1668 msleep(20);
1669}
1670
1671static inline void r8152b_enable_aldps(struct r8152 *tp)
1672{
1673 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1674 LINKENA | DIS_SDSAVE);
1675}
1676
1677static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
1678{
1679 u16 bmcr, anar;
1680 int ret = 0;
1681
1682 cancel_delayed_work_sync(&tp->schedule);
1683 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1684 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1685 ADVERTISE_100HALF | ADVERTISE_100FULL);
1686
1687 if (autoneg == AUTONEG_DISABLE) {
1688 if (speed == SPEED_10) {
1689 bmcr = 0;
1690 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1691 } else if (speed == SPEED_100) {
1692 bmcr = BMCR_SPEED100;
1693 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1694 } else {
1695 ret = -EINVAL;
1696 goto out;
1697 }
1698
1699 if (duplex == DUPLEX_FULL)
1700 bmcr |= BMCR_FULLDPLX;
1701 } else {
1702 if (speed == SPEED_10) {
1703 if (duplex == DUPLEX_FULL)
1704 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1705 else
1706 anar |= ADVERTISE_10HALF;
1707 } else if (speed == SPEED_100) {
1708 if (duplex == DUPLEX_FULL) {
1709 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1710 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1711 } else {
1712 anar |= ADVERTISE_10HALF;
1713 anar |= ADVERTISE_100HALF;
1714 }
1715 } else {
1716 ret = -EINVAL;
1717 goto out;
1718 }
1719
1720 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1721 }
1722
1723 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1724 r8152_mdio_write(tp, MII_BMCR, bmcr);
1725
1726out:
ac718b69 1727
1728 return ret;
1729}
1730
1731static void rtl8152_down(struct r8152 *tp)
1732{
1733 u32 ocp_data;
1734
1735 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1736 ocp_data &= ~POWER_CUT;
1737 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1738
1739 r8152b_disable_aldps(tp);
1740 r8152b_enter_oob(tp);
1741 r8152b_enable_aldps(tp);
1742}
1743
1744static void set_carrier(struct r8152 *tp)
1745{
1746 struct net_device *netdev = tp->netdev;
1747 u8 speed;
1748
40a82917 1749 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 1750 speed = rtl8152_get_speed(tp);
1751
1752 if (speed & LINK_STATUS) {
1753 if (!(tp->speed & LINK_STATUS)) {
1754 rtl8152_enable(tp);
1755 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1756 netif_carrier_on(netdev);
1757 }
1758 } else {
1759 if (tp->speed & LINK_STATUS) {
1760 netif_carrier_off(netdev);
ebc2ec48 1761 tasklet_disable(&tp->tl);
ac718b69 1762 rtl8152_disable(tp);
ebc2ec48 1763 tasklet_enable(&tp->tl);
ac718b69 1764 }
1765 }
1766 tp->speed = speed;
1767}
1768
1769static void rtl_work_func_t(struct work_struct *work)
1770{
1771 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
1772
1773 if (!test_bit(WORK_ENABLE, &tp->flags))
1774 goto out1;
1775
1776 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1777 goto out1;
1778
40a82917 1779 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
1780 set_carrier(tp);
ac718b69 1781
1782 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
1783 _rtl8152_set_rx_mode(tp->netdev);
1784
ac718b69 1785out1:
1786 return;
1787}
1788
1789static int rtl8152_open(struct net_device *netdev)
1790{
1791 struct r8152 *tp = netdev_priv(netdev);
1792 int res = 0;
1793
40a82917 1794 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
1795 if (res) {
1796 if (res == -ENODEV)
1797 netif_device_detach(tp->netdev);
1798 netif_warn(tp, ifup, netdev,
1799 "intr_urb submit failed: %d\n", res);
1800 return res;
ac718b69 1801 }
1802
1803 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
40a82917 1804 tp->speed = 0;
1805 netif_carrier_off(netdev);
ac718b69 1806 netif_start_queue(netdev);
1807 set_bit(WORK_ENABLE, &tp->flags);
ac718b69 1808
1809 return res;
1810}
1811
1812static int rtl8152_close(struct net_device *netdev)
1813{
1814 struct r8152 *tp = netdev_priv(netdev);
1815 int res = 0;
1816
40a82917 1817 usb_kill_urb(tp->intr_urb);
ac718b69 1818 clear_bit(WORK_ENABLE, &tp->flags);
1819 cancel_delayed_work_sync(&tp->schedule);
1820 netif_stop_queue(netdev);
ebc2ec48 1821 tasklet_disable(&tp->tl);
ac718b69 1822 rtl8152_disable(tp);
ebc2ec48 1823 tasklet_enable(&tp->tl);
ac718b69 1824
1825 return res;
1826}
1827
1828static void rtl_clear_bp(struct r8152 *tp)
1829{
1830 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
1831 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
1832 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
1833 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
1834 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
1835 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
1836 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
1837 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
1838 mdelay(3);
1839 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
1840 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
1841}
1842
1843static void r8152b_enable_eee(struct r8152 *tp)
1844{
1845 u32 ocp_data;
1846
1847 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
1848 ocp_data |= EEE_RX_EN | EEE_TX_EN;
1849 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
1850 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
1851 EEE_10_CAP | EEE_NWAY_EN |
1852 TX_QUIET_EN | RX_QUIET_EN |
1853 SDRISETIME | RG_RXLPI_MSK_HFDUP |
1854 SDFALLTIME);
1855 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
1856 RG_LDVQUIET_EN | RG_CKRSEL |
1857 RG_EEEPRG_EN);
1858 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
1859 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
1860 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
1861 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
1862 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
1863 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
1864}
1865
1866static void r8152b_enable_fc(struct r8152 *tp)
1867{
1868 u16 anar;
1869
1870 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1871 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1872 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1873}
1874
1875static void r8152b_hw_phy_cfg(struct r8152 *tp)
1876{
1877 r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
1878 r8152b_disable_aldps(tp);
1879}
1880
1881static void r8152b_init(struct r8152 *tp)
1882{
ebc2ec48 1883 u32 ocp_data;
1884 int i;
ac718b69 1885
1886 rtl_clear_bp(tp);
1887
1888 if (tp->version == RTL_VER_01) {
1889 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1890 ocp_data &= ~LED_MODE_MASK;
1891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1892 }
1893
1894 r8152b_hw_phy_cfg(tp);
1895
1896 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1897 ocp_data &= ~POWER_CUT;
1898 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1899
1900 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
8e1f51bd 1901 ocp_data &= ~RESUME_INDICATE;
ac718b69 1902 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
1903
1904 r8152b_exit_oob(tp);
1905
1906 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1907 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1908 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1909 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1910 ocp_data &= ~MCU_CLK_RATIO_MASK;
1911 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1912 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1913 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1914 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1915 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1916
1917 r8152b_enable_eee(tp);
1918 r8152b_enable_aldps(tp);
1919 r8152b_enable_fc(tp);
1920
1921 r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
1922 BMCR_ANRESTART);
1923 for (i = 0; i < 100; i++) {
1924 udelay(100);
1925 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
1926 break;
1927 }
1928
ebc2ec48 1929 /* enable rx aggregation */
ac718b69 1930 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 1931 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 1932 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1933}
1934
1935static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
1936{
1937 struct r8152 *tp = usb_get_intfdata(intf);
1938
1939 netif_device_detach(tp->netdev);
1940
1941 if (netif_running(tp->netdev)) {
1942 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 1943 usb_kill_urb(tp->intr_urb);
ac718b69 1944 cancel_delayed_work_sync(&tp->schedule);
ebc2ec48 1945 tasklet_disable(&tp->tl);
ac718b69 1946 }
1947
1948 rtl8152_down(tp);
1949
1950 return 0;
1951}
1952
1953static int rtl8152_resume(struct usb_interface *intf)
1954{
1955 struct r8152 *tp = usb_get_intfdata(intf);
1956
1957 r8152b_init(tp);
1958 netif_device_attach(tp->netdev);
1959 if (netif_running(tp->netdev)) {
40a82917 1960 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
1961 tp->speed = 0;
1962 netif_carrier_off(tp->netdev);
ac718b69 1963 set_bit(WORK_ENABLE, &tp->flags);
40a82917 1964 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
ebc2ec48 1965 tasklet_enable(&tp->tl);
ac718b69 1966 }
1967
1968 return 0;
1969}
1970
1971static void rtl8152_get_drvinfo(struct net_device *netdev,
1972 struct ethtool_drvinfo *info)
1973{
1974 struct r8152 *tp = netdev_priv(netdev);
1975
1976 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
1977 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
1978 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
1979}
1980
1981static
1982int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1983{
1984 struct r8152 *tp = netdev_priv(netdev);
1985
1986 if (!tp->mii.mdio_read)
1987 return -EOPNOTSUPP;
1988
1989 return mii_ethtool_gset(&tp->mii, cmd);
1990}
1991
1992static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1993{
1994 struct r8152 *tp = netdev_priv(dev);
1995
1996 return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
1997}
1998
1999static struct ethtool_ops ops = {
2000 .get_drvinfo = rtl8152_get_drvinfo,
2001 .get_settings = rtl8152_get_settings,
2002 .set_settings = rtl8152_set_settings,
2003 .get_link = ethtool_op_get_link,
2004};
2005
2006static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2007{
2008 struct r8152 *tp = netdev_priv(netdev);
2009 struct mii_ioctl_data *data = if_mii(rq);
2010 int res = 0;
2011
2012 switch (cmd) {
2013 case SIOCGMIIPHY:
2014 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2015 break;
2016
2017 case SIOCGMIIREG:
2018 data->val_out = r8152_mdio_read(tp, data->reg_num);
2019 break;
2020
2021 case SIOCSMIIREG:
2022 if (!capable(CAP_NET_ADMIN)) {
2023 res = -EPERM;
2024 break;
2025 }
2026 r8152_mdio_write(tp, data->reg_num, data->val_in);
2027 break;
2028
2029 default:
2030 res = -EOPNOTSUPP;
2031 }
2032
2033 return res;
2034}
2035
2036static const struct net_device_ops rtl8152_netdev_ops = {
2037 .ndo_open = rtl8152_open,
2038 .ndo_stop = rtl8152_close,
2039 .ndo_do_ioctl = rtl8152_ioctl,
2040 .ndo_start_xmit = rtl8152_start_xmit,
2041 .ndo_tx_timeout = rtl8152_tx_timeout,
2042 .ndo_set_rx_mode = rtl8152_set_rx_mode,
2043 .ndo_set_mac_address = rtl8152_set_mac_address,
2044
2045 .ndo_change_mtu = eth_change_mtu,
2046 .ndo_validate_addr = eth_validate_addr,
2047};
2048
2049static void r8152b_get_version(struct r8152 *tp)
2050{
2051 u32 ocp_data;
2052 u16 version;
2053
2054 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2055 version = (u16)(ocp_data & VERSION_MASK);
2056
2057 switch (version) {
2058 case 0x4c00:
2059 tp->version = RTL_VER_01;
2060 break;
2061 case 0x4c10:
2062 tp->version = RTL_VER_02;
2063 break;
2064 default:
2065 netif_info(tp, probe, tp->netdev,
2066 "Unknown version 0x%04x\n", version);
2067 break;
2068 }
2069}
2070
e3fe0b1a 2071static void rtl8152_unload(struct r8152 *tp)
2072{
2073 u32 ocp_data;
2074
2075 if (tp->version != RTL_VER_01) {
2076 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2077 ocp_data |= POWER_CUT;
2078 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2079 }
2080
2081 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
8e1f51bd 2082 ocp_data &= ~RESUME_INDICATE;
e3fe0b1a 2083 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2084}
2085
ac718b69 2086static int rtl8152_probe(struct usb_interface *intf,
2087 const struct usb_device_id *id)
2088{
2089 struct usb_device *udev = interface_to_usbdev(intf);
2090 struct r8152 *tp;
2091 struct net_device *netdev;
ebc2ec48 2092 int ret;
ac718b69 2093
2094 if (udev->actconfig->desc.bConfigurationValue != 1) {
2095 usb_driver_set_configuration(udev, 1);
2096 return -ENODEV;
2097 }
2098
2099 netdev = alloc_etherdev(sizeof(struct r8152));
2100 if (!netdev) {
2101 dev_err(&intf->dev, "Out of memory");
2102 return -ENOMEM;
2103 }
2104
ebc2ec48 2105 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 2106 tp = netdev_priv(netdev);
2107 tp->msg_enable = 0x7FFF;
2108
ebc2ec48 2109 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
ac718b69 2110 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
2111
2112 tp->udev = udev;
2113 tp->netdev = netdev;
40a82917 2114 tp->intf = intf;
ac718b69 2115 netdev->netdev_ops = &rtl8152_netdev_ops;
2116 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 2117
2118 netdev->features |= NETIF_F_IP_CSUM;
2119 netdev->hw_features = NETIF_F_IP_CSUM;
ac718b69 2120 SET_ETHTOOL_OPS(netdev, &ops);
ac718b69 2121
2122 tp->mii.dev = netdev;
2123 tp->mii.mdio_read = read_mii_word;
2124 tp->mii.mdio_write = write_mii_word;
2125 tp->mii.phy_id_mask = 0x3f;
2126 tp->mii.reg_num_mask = 0x1f;
2127 tp->mii.phy_id = R8152_PHY_ID;
2128 tp->mii.supports_gmii = 0;
2129
2130 r8152b_get_version(tp);
2131 r8152b_init(tp);
2132 set_ethernet_addr(tp);
2133
ebc2ec48 2134 ret = alloc_all_mem(tp);
2135 if (ret)
ac718b69 2136 goto out;
ac718b69 2137
2138 usb_set_intfdata(intf, tp);
ac718b69 2139
ebc2ec48 2140 ret = register_netdev(netdev);
2141 if (ret != 0) {
ac718b69 2142 netif_err(tp, probe, netdev, "couldn't register the device");
ebc2ec48 2143 goto out1;
ac718b69 2144 }
2145
2146 netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
2147
2148 return 0;
2149
ac718b69 2150out1:
ebc2ec48 2151 usb_set_intfdata(intf, NULL);
ac718b69 2152out:
2153 free_netdev(netdev);
ebc2ec48 2154 return ret;
ac718b69 2155}
2156
ac718b69 2157static void rtl8152_disconnect(struct usb_interface *intf)
2158{
2159 struct r8152 *tp = usb_get_intfdata(intf);
2160
2161 usb_set_intfdata(intf, NULL);
2162 if (tp) {
2163 set_bit(RTL8152_UNPLUG, &tp->flags);
2164 tasklet_kill(&tp->tl);
2165 unregister_netdev(tp->netdev);
2166 rtl8152_unload(tp);
ebc2ec48 2167 free_all_mem(tp);
ac718b69 2168 free_netdev(tp->netdev);
2169 }
2170}
2171
2172/* table of devices that work with this driver */
2173static struct usb_device_id rtl8152_table[] = {
2174 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
2175 {}
2176};
2177
2178MODULE_DEVICE_TABLE(usb, rtl8152_table);
2179
2180static struct usb_driver rtl8152_driver = {
2181 .name = MODULENAME,
ebc2ec48 2182 .id_table = rtl8152_table,
ac718b69 2183 .probe = rtl8152_probe,
2184 .disconnect = rtl8152_disconnect,
ac718b69 2185 .suspend = rtl8152_suspend,
ebc2ec48 2186 .resume = rtl8152_resume,
2187 .reset_resume = rtl8152_resume,
ac718b69 2188};
2189
b4236daa 2190module_usb_driver(rtl8152_driver);
ac718b69 2191
2192MODULE_AUTHOR(DRIVER_AUTHOR);
2193MODULE_DESCRIPTION(DRIVER_DESC);
2194MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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