r8152: support get_msglevel and set_msglevel
[deliverable/linux.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
ac718b69 24
25/* Version Information */
21ff2e89 26#define DRIVER_VERSION "v1.05.0 (2014/02/18)"
ac718b69 27#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 28#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 29#define MODULENAME "r8152"
30
31#define R8152_PHY_ID 32
32
33#define PLA_IDR 0xc000
34#define PLA_RCR 0xc010
35#define PLA_RMS 0xc016
36#define PLA_RXFIFO_CTRL0 0xc0a0
37#define PLA_RXFIFO_CTRL1 0xc0a4
38#define PLA_RXFIFO_CTRL2 0xc0a8
39#define PLA_FMC 0xc0b4
40#define PLA_CFG_WOL 0xc0b6
43779f8d 41#define PLA_TEREDO_CFG 0xc0bc
ac718b69 42#define PLA_MAR 0xcd00
43779f8d 43#define PLA_BACKUP 0xd000
ac718b69 44#define PAL_BDC_CR 0xd1a0
43779f8d 45#define PLA_TEREDO_TIMER 0xd2cc
46#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 47#define PLA_LEDSEL 0xdd90
48#define PLA_LED_FEATURE 0xdd92
49#define PLA_PHYAR 0xde00
43779f8d 50#define PLA_BOOT_CTRL 0xe004
ac718b69 51#define PLA_GPHY_INTR_IMR 0xe022
52#define PLA_EEE_CR 0xe040
53#define PLA_EEEP_CR 0xe080
54#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 55#define PLA_MAC_PWR_CTRL2 0xe0ca
56#define PLA_MAC_PWR_CTRL3 0xe0cc
57#define PLA_MAC_PWR_CTRL4 0xe0ce
58#define PLA_WDT6_CTRL 0xe428
ac718b69 59#define PLA_TCR0 0xe610
60#define PLA_TCR1 0xe612
61#define PLA_TXFIFO_CTRL 0xe618
62#define PLA_RSTTELLY 0xe800
63#define PLA_CR 0xe813
64#define PLA_CRWECR 0xe81c
21ff2e89 65#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
66#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 67#define PLA_CONFIG5 0xe822
68#define PLA_PHY_PWR 0xe84c
69#define PLA_OOB_CTRL 0xe84f
70#define PLA_CPCR 0xe854
71#define PLA_MISC_0 0xe858
72#define PLA_MISC_1 0xe85a
73#define PLA_OCP_GPHY_BASE 0xe86c
74#define PLA_TELLYCNT 0xe890
75#define PLA_SFF_STS_7 0xe8de
76#define PLA_PHYSTATUS 0xe908
77#define PLA_BP_BA 0xfc26
78#define PLA_BP_0 0xfc28
79#define PLA_BP_1 0xfc2a
80#define PLA_BP_2 0xfc2c
81#define PLA_BP_3 0xfc2e
82#define PLA_BP_4 0xfc30
83#define PLA_BP_5 0xfc32
84#define PLA_BP_6 0xfc34
85#define PLA_BP_7 0xfc36
43779f8d 86#define PLA_BP_EN 0xfc38
ac718b69 87
43779f8d 88#define USB_U2P3_CTRL 0xb460
ac718b69 89#define USB_DEV_STAT 0xb808
90#define USB_USB_CTRL 0xd406
91#define USB_PHY_CTRL 0xd408
92#define USB_TX_AGG 0xd40a
93#define USB_RX_BUF_TH 0xd40c
94#define USB_USB_TIMER 0xd428
43779f8d 95#define USB_RX_EARLY_AGG 0xd42c
ac718b69 96#define USB_PM_CTRL_STATUS 0xd432
97#define USB_TX_DMA 0xd434
43779f8d 98#define USB_TOLERANCE 0xd490
99#define USB_LPM_CTRL 0xd41a
ac718b69 100#define USB_UPS_CTRL 0xd800
43779f8d 101#define USB_MISC_0 0xd81a
102#define USB_POWER_CUT 0xd80a
103#define USB_AFE_CTRL2 0xd824
104#define USB_WDT11_CTRL 0xe43c
ac718b69 105#define USB_BP_BA 0xfc26
106#define USB_BP_0 0xfc28
107#define USB_BP_1 0xfc2a
108#define USB_BP_2 0xfc2c
109#define USB_BP_3 0xfc2e
110#define USB_BP_4 0xfc30
111#define USB_BP_5 0xfc32
112#define USB_BP_6 0xfc34
113#define USB_BP_7 0xfc36
43779f8d 114#define USB_BP_EN 0xfc38
ac718b69 115
116/* OCP Registers */
117#define OCP_ALDPS_CONFIG 0x2010
118#define OCP_EEE_CONFIG1 0x2080
119#define OCP_EEE_CONFIG2 0x2092
120#define OCP_EEE_CONFIG3 0x2094
ac244d3e 121#define OCP_BASE_MII 0xa400
ac718b69 122#define OCP_EEE_AR 0xa41a
123#define OCP_EEE_DATA 0xa41c
43779f8d 124#define OCP_PHY_STATUS 0xa420
125#define OCP_POWER_CFG 0xa430
126#define OCP_EEE_CFG 0xa432
127#define OCP_SRAM_ADDR 0xa436
128#define OCP_SRAM_DATA 0xa438
129#define OCP_DOWN_SPEED 0xa442
130#define OCP_EEE_CFG2 0xa5d0
131#define OCP_ADC_CFG 0xbc06
132
133/* SRAM Register */
134#define SRAM_LPF_CFG 0x8012
135#define SRAM_10M_AMP1 0x8080
136#define SRAM_10M_AMP2 0x8082
137#define SRAM_IMPEDANCE 0x8084
ac718b69 138
139/* PLA_RCR */
140#define RCR_AAP 0x00000001
141#define RCR_APM 0x00000002
142#define RCR_AM 0x00000004
143#define RCR_AB 0x00000008
144#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
145
146/* PLA_RXFIFO_CTRL0 */
147#define RXFIFO_THR1_NORMAL 0x00080002
148#define RXFIFO_THR1_OOB 0x01800003
149
150/* PLA_RXFIFO_CTRL1 */
151#define RXFIFO_THR2_FULL 0x00000060
152#define RXFIFO_THR2_HIGH 0x00000038
153#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 154#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 155
156/* PLA_RXFIFO_CTRL2 */
157#define RXFIFO_THR3_FULL 0x00000078
158#define RXFIFO_THR3_HIGH 0x00000048
159#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 160#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 161
162/* PLA_TXFIFO_CTRL */
163#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 164#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 165
166/* PLA_FMC */
167#define FMC_FCR_MCU_EN 0x0001
168
169/* PLA_EEEP_CR */
170#define EEEP_CR_EEEP_TX 0x0002
171
43779f8d 172/* PLA_WDT6_CTRL */
173#define WDT6_SET_MODE 0x0010
174
ac718b69 175/* PLA_TCR0 */
176#define TCR0_TX_EMPTY 0x0800
177#define TCR0_AUTO_FIFO 0x0080
178
179/* PLA_TCR1 */
180#define VERSION_MASK 0x7cf0
181
182/* PLA_CR */
183#define CR_RST 0x10
184#define CR_RE 0x08
185#define CR_TE 0x04
186
187/* PLA_CRWECR */
188#define CRWECR_NORAML 0x00
189#define CRWECR_CONFIG 0xc0
190
191/* PLA_OOB_CTRL */
192#define NOW_IS_OOB 0x80
193#define TXFIFO_EMPTY 0x20
194#define RXFIFO_EMPTY 0x10
195#define LINK_LIST_READY 0x02
196#define DIS_MCU_CLROOB 0x01
197#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
198
199/* PLA_MISC_1 */
200#define RXDY_GATED_EN 0x0008
201
202/* PLA_SFF_STS_7 */
203#define RE_INIT_LL 0x8000
204#define MCU_BORW_EN 0x4000
205
206/* PLA_CPCR */
207#define CPCR_RX_VLAN 0x0040
208
209/* PLA_CFG_WOL */
210#define MAGIC_EN 0x0001
211
43779f8d 212/* PLA_TEREDO_CFG */
213#define TEREDO_SEL 0x8000
214#define TEREDO_WAKE_MASK 0x7f00
215#define TEREDO_RS_EVENT_MASK 0x00fe
216#define OOB_TEREDO_EN 0x0001
217
ac718b69 218/* PAL_BDC_CR */
219#define ALDPS_PROXY_MODE 0x0001
220
21ff2e89 221/* PLA_CONFIG34 */
222#define LINK_ON_WAKE_EN 0x0010
223#define LINK_OFF_WAKE_EN 0x0008
224
ac718b69 225/* PLA_CONFIG5 */
21ff2e89 226#define BWF_EN 0x0040
227#define MWF_EN 0x0020
228#define UWF_EN 0x0010
ac718b69 229#define LAN_WAKE_EN 0x0002
230
231/* PLA_LED_FEATURE */
232#define LED_MODE_MASK 0x0700
233
234/* PLA_PHY_PWR */
235#define TX_10M_IDLE_EN 0x0080
236#define PFM_PWM_SWITCH 0x0040
237
238/* PLA_MAC_PWR_CTRL */
239#define D3_CLK_GATED_EN 0x00004000
240#define MCU_CLK_RATIO 0x07010f07
241#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 242#define ALDPS_SPDWN_RATIO 0x0f87
243
244/* PLA_MAC_PWR_CTRL2 */
245#define EEE_SPDWN_RATIO 0x8007
246
247/* PLA_MAC_PWR_CTRL3 */
248#define PKT_AVAIL_SPDWN_EN 0x0100
249#define SUSPEND_SPDWN_EN 0x0004
250#define U1U2_SPDWN_EN 0x0002
251#define L1_SPDWN_EN 0x0001
252
253/* PLA_MAC_PWR_CTRL4 */
254#define PWRSAVE_SPDWN_EN 0x1000
255#define RXDV_SPDWN_EN 0x0800
256#define TX10MIDLE_EN 0x0100
257#define TP100_SPDWN_EN 0x0020
258#define TP500_SPDWN_EN 0x0010
259#define TP1000_SPDWN_EN 0x0008
260#define EEE_SPDWN_EN 0x0001
ac718b69 261
262/* PLA_GPHY_INTR_IMR */
263#define GPHY_STS_MSK 0x0001
264#define SPEED_DOWN_MSK 0x0002
265#define SPDWN_RXDV_MSK 0x0004
266#define SPDWN_LINKCHG_MSK 0x0008
267
268/* PLA_PHYAR */
269#define PHYAR_FLAG 0x80000000
270
271/* PLA_EEE_CR */
272#define EEE_RX_EN 0x0001
273#define EEE_TX_EN 0x0002
274
43779f8d 275/* PLA_BOOT_CTRL */
276#define AUTOLOAD_DONE 0x0002
277
ac718b69 278/* USB_DEV_STAT */
279#define STAT_SPEED_MASK 0x0006
280#define STAT_SPEED_HIGH 0x0000
281#define STAT_SPEED_FULL 0x0001
282
283/* USB_TX_AGG */
284#define TX_AGG_MAX_THRESHOLD 0x03
285
286/* USB_RX_BUF_TH */
43779f8d 287#define RX_THR_SUPPER 0x0c350180
8e1f51bd 288#define RX_THR_HIGH 0x7a120180
43779f8d 289#define RX_THR_SLOW 0xffff0180
ac718b69 290
291/* USB_TX_DMA */
292#define TEST_MODE_DISABLE 0x00000001
293#define TX_SIZE_ADJUST1 0x00000100
294
295/* USB_UPS_CTRL */
296#define POWER_CUT 0x0100
297
298/* USB_PM_CTRL_STATUS */
8e1f51bd 299#define RESUME_INDICATE 0x0001
ac718b69 300
301/* USB_USB_CTRL */
302#define RX_AGG_DISABLE 0x0010
303
43779f8d 304/* USB_U2P3_CTRL */
305#define U2P3_ENABLE 0x0001
306
307/* USB_POWER_CUT */
308#define PWR_EN 0x0001
309#define PHASE2_EN 0x0008
310
311/* USB_MISC_0 */
312#define PCUT_STATUS 0x0001
313
314/* USB_RX_EARLY_AGG */
315#define EARLY_AGG_SUPPER 0x0e832981
316#define EARLY_AGG_HIGH 0x0e837a12
317#define EARLY_AGG_SLOW 0x0e83ffff
318
319/* USB_WDT11_CTRL */
320#define TIMER11_EN 0x0001
321
322/* USB_LPM_CTRL */
323#define LPM_TIMER_MASK 0x0c
324#define LPM_TIMER_500MS 0x04 /* 500 ms */
325#define LPM_TIMER_500US 0x0c /* 500 us */
326
327/* USB_AFE_CTRL2 */
328#define SEN_VAL_MASK 0xf800
329#define SEN_VAL_NORMAL 0xa000
330#define SEL_RXIDLE 0x0100
331
ac718b69 332/* OCP_ALDPS_CONFIG */
333#define ENPWRSAVE 0x8000
334#define ENPDNPS 0x0200
335#define LINKENA 0x0100
336#define DIS_SDSAVE 0x0010
337
43779f8d 338/* OCP_PHY_STATUS */
339#define PHY_STAT_MASK 0x0007
340#define PHY_STAT_LAN_ON 3
341#define PHY_STAT_PWRDN 5
342
343/* OCP_POWER_CFG */
344#define EEE_CLKDIV_EN 0x8000
345#define EN_ALDPS 0x0004
346#define EN_10M_PLLOFF 0x0001
347
ac718b69 348/* OCP_EEE_CONFIG1 */
349#define RG_TXLPI_MSK_HFDUP 0x8000
350#define RG_MATCLR_EN 0x4000
351#define EEE_10_CAP 0x2000
352#define EEE_NWAY_EN 0x1000
353#define TX_QUIET_EN 0x0200
354#define RX_QUIET_EN 0x0100
355#define SDRISETIME 0x0010 /* bit 4 ~ 6 */
356#define RG_RXLPI_MSK_HFDUP 0x0008
357#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
358
359/* OCP_EEE_CONFIG2 */
360#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
361#define RG_DACQUIET_EN 0x0400
362#define RG_LDVQUIET_EN 0x0200
363#define RG_CKRSEL 0x0020
364#define RG_EEEPRG_EN 0x0010
365
366/* OCP_EEE_CONFIG3 */
367#define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
368#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
369#define MSK_PH 0x0006 /* bit 0 ~ 3 */
370
371/* OCP_EEE_AR */
372/* bit[15:14] function */
373#define FUN_ADDR 0x0000
374#define FUN_DATA 0x4000
375/* bit[4:0] device addr */
376#define DEVICE_ADDR 0x0007
377
378/* OCP_EEE_DATA */
379#define EEE_ADDR 0x003C
380#define EEE_DATA 0x0002
381
43779f8d 382/* OCP_EEE_CFG */
383#define CTAP_SHORT_EN 0x0040
384#define EEE10_EN 0x0010
385
386/* OCP_DOWN_SPEED */
387#define EN_10M_BGOFF 0x0080
388
389/* OCP_EEE_CFG2 */
390#define MY1000_EEE 0x0004
391#define MY100_EEE 0x0002
392
393/* OCP_ADC_CFG */
394#define CKADSEL_L 0x0100
395#define ADC_EN 0x0080
396#define EN_EMI_L 0x0040
397
398/* SRAM_LPF_CFG */
399#define LPF_AUTO_TUNE 0x8000
400
401/* SRAM_10M_AMP1 */
402#define GDAC_IB_UPALL 0x0008
403
404/* SRAM_10M_AMP2 */
405#define AMP_DN 0x0200
406
407/* SRAM_IMPEDANCE */
408#define RX_DRIVING_MASK 0x6000
409
ac718b69 410enum rtl_register_content {
43779f8d 411 _1000bps = 0x10,
ac718b69 412 _100bps = 0x08,
413 _10bps = 0x04,
414 LINK_STATUS = 0x02,
415 FULL_DUP = 0x01,
416};
417
ebc2ec48 418#define RTL8152_MAX_TX 10
419#define RTL8152_MAX_RX 10
40a82917 420#define INTBUFSIZE 2
8e1f51bd 421#define CRC_SIZE 4
422#define TX_ALIGN 4
423#define RX_ALIGN 8
40a82917 424
425#define INTR_LINK 0x0004
ebc2ec48 426
ac718b69 427#define RTL8152_REQT_READ 0xc0
428#define RTL8152_REQT_WRITE 0x40
429#define RTL8152_REQ_GET_REGS 0x05
430#define RTL8152_REQ_SET_REGS 0x05
431
432#define BYTE_EN_DWORD 0xff
433#define BYTE_EN_WORD 0x33
434#define BYTE_EN_BYTE 0x11
435#define BYTE_EN_SIX_BYTES 0x3f
436#define BYTE_EN_START_MASK 0x0f
437#define BYTE_EN_END_MASK 0xf0
438
439#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
440#define RTL8152_TX_TIMEOUT (HZ)
441
442/* rtl8152 flags */
443enum rtl8152_flags {
444 RTL8152_UNPLUG = 0,
ac718b69 445 RTL8152_SET_RX_MODE,
40a82917 446 WORK_ENABLE,
447 RTL8152_LINK_CHG,
9a4be1bd 448 SELECTIVE_SUSPEND,
aa66a5f1 449 PHY_RESET,
ac718b69 450};
451
452/* Define these values to match your device */
453#define VENDOR_ID_REALTEK 0x0bda
454#define PRODUCT_ID_RTL8152 0x8152
43779f8d 455#define PRODUCT_ID_RTL8153 0x8153
456
457#define VENDOR_ID_SAMSUNG 0x04e8
458#define PRODUCT_ID_SAMSUNG 0xa101
ac718b69 459
460#define MCU_TYPE_PLA 0x0100
461#define MCU_TYPE_USB 0x0000
462
c7de7dec 463#define REALTEK_USB_DEVICE(vend, prod) \
464 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
465
ac718b69 466struct rx_desc {
500b6d7e 467 __le32 opts1;
ac718b69 468#define RX_LEN_MASK 0x7fff
500b6d7e 469 __le32 opts2;
470 __le32 opts3;
471 __le32 opts4;
472 __le32 opts5;
473 __le32 opts6;
ac718b69 474};
475
476struct tx_desc {
500b6d7e 477 __le32 opts1;
ac718b69 478#define TX_FS (1 << 31) /* First segment of a packet */
479#define TX_LS (1 << 30) /* Final segment of a packet */
5bd23881 480#define TX_LEN_MASK 0x3ffff
481
500b6d7e 482 __le32 opts2;
5bd23881 483#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
484#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
485#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
486#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
ac718b69 487};
488
dff4e8ad 489struct r8152;
490
ebc2ec48 491struct rx_agg {
492 struct list_head list;
493 struct urb *urb;
dff4e8ad 494 struct r8152 *context;
ebc2ec48 495 void *buffer;
496 void *head;
497};
498
499struct tx_agg {
500 struct list_head list;
501 struct urb *urb;
dff4e8ad 502 struct r8152 *context;
ebc2ec48 503 void *buffer;
504 void *head;
505 u32 skb_num;
506 u32 skb_len;
507};
508
ac718b69 509struct r8152 {
510 unsigned long flags;
511 struct usb_device *udev;
512 struct tasklet_struct tl;
40a82917 513 struct usb_interface *intf;
ac718b69 514 struct net_device *netdev;
40a82917 515 struct urb *intr_urb;
ebc2ec48 516 struct tx_agg tx_info[RTL8152_MAX_TX];
517 struct rx_agg rx_info[RTL8152_MAX_RX];
518 struct list_head rx_done, tx_free;
519 struct sk_buff_head tx_queue;
520 spinlock_t rx_lock, tx_lock;
ac718b69 521 struct delayed_work schedule;
522 struct mii_if_info mii;
c81229c9 523
524 struct rtl_ops {
525 void (*init)(struct r8152 *);
526 int (*enable)(struct r8152 *);
527 void (*disable)(struct r8152 *);
7e9da481 528 void (*up)(struct r8152 *);
c81229c9 529 void (*down)(struct r8152 *);
530 void (*unload)(struct r8152 *);
531 } rtl_ops;
532
40a82917 533 int intr_interval;
21ff2e89 534 u32 saved_wolopts;
ac718b69 535 u32 msg_enable;
dd1b119c 536 u32 tx_qlen;
ac718b69 537 u16 ocp_base;
40a82917 538 u8 *intr_buff;
ac718b69 539 u8 version;
540 u8 speed;
541};
542
543enum rtl_version {
544 RTL_VER_UNKNOWN = 0,
545 RTL_VER_01,
43779f8d 546 RTL_VER_02,
547 RTL_VER_03,
548 RTL_VER_04,
549 RTL_VER_05,
550 RTL_VER_MAX
ac718b69 551};
552
553/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
554 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
555 */
556static const int multicast_filter_limit = 32;
ebc2ec48 557static unsigned int rx_buf_sz = 16384;
ac718b69 558
559static
560int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
561{
31787f53 562 int ret;
563 void *tmp;
564
565 tmp = kmalloc(size, GFP_KERNEL);
566 if (!tmp)
567 return -ENOMEM;
568
569 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
ac718b69 570 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
31787f53 571 value, index, tmp, size, 500);
572
573 memcpy(data, tmp, size);
574 kfree(tmp);
575
576 return ret;
ac718b69 577}
578
579static
580int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
581{
31787f53 582 int ret;
583 void *tmp;
584
585 tmp = kmalloc(size, GFP_KERNEL);
586 if (!tmp)
587 return -ENOMEM;
588
589 memcpy(tmp, data, size);
590
591 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
ac718b69 592 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
31787f53 593 value, index, tmp, size, 500);
594
595 kfree(tmp);
596 return ret;
ac718b69 597}
598
599static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
600 void *data, u16 type)
601{
45f4a19f 602 u16 limit = 64;
603 int ret = 0;
ac718b69 604
605 if (test_bit(RTL8152_UNPLUG, &tp->flags))
606 return -ENODEV;
607
608 /* both size and indix must be 4 bytes align */
609 if ((size & 3) || !size || (index & 3) || !data)
610 return -EPERM;
611
612 if ((u32)index + (u32)size > 0xffff)
613 return -EPERM;
614
615 while (size) {
616 if (size > limit) {
617 ret = get_registers(tp, index, type, limit, data);
618 if (ret < 0)
619 break;
620
621 index += limit;
622 data += limit;
623 size -= limit;
624 } else {
625 ret = get_registers(tp, index, type, size, data);
626 if (ret < 0)
627 break;
628
629 index += size;
630 data += size;
631 size = 0;
632 break;
633 }
634 }
635
636 return ret;
637}
638
639static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
640 u16 size, void *data, u16 type)
641{
45f4a19f 642 int ret;
643 u16 byteen_start, byteen_end, byen;
644 u16 limit = 512;
ac718b69 645
646 if (test_bit(RTL8152_UNPLUG, &tp->flags))
647 return -ENODEV;
648
649 /* both size and indix must be 4 bytes align */
650 if ((size & 3) || !size || (index & 3) || !data)
651 return -EPERM;
652
653 if ((u32)index + (u32)size > 0xffff)
654 return -EPERM;
655
656 byteen_start = byteen & BYTE_EN_START_MASK;
657 byteen_end = byteen & BYTE_EN_END_MASK;
658
659 byen = byteen_start | (byteen_start << 4);
660 ret = set_registers(tp, index, type | byen, 4, data);
661 if (ret < 0)
662 goto error1;
663
664 index += 4;
665 data += 4;
666 size -= 4;
667
668 if (size) {
669 size -= 4;
670
671 while (size) {
672 if (size > limit) {
673 ret = set_registers(tp, index,
674 type | BYTE_EN_DWORD,
675 limit, data);
676 if (ret < 0)
677 goto error1;
678
679 index += limit;
680 data += limit;
681 size -= limit;
682 } else {
683 ret = set_registers(tp, index,
684 type | BYTE_EN_DWORD,
685 size, data);
686 if (ret < 0)
687 goto error1;
688
689 index += size;
690 data += size;
691 size = 0;
692 break;
693 }
694 }
695
696 byen = byteen_end | (byteen_end >> 4);
697 ret = set_registers(tp, index, type | byen, 4, data);
698 if (ret < 0)
699 goto error1;
700 }
701
702error1:
703 return ret;
704}
705
706static inline
707int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
708{
709 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
710}
711
712static inline
713int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
714{
715 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
716}
717
718static inline
719int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
720{
721 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
722}
723
724static inline
725int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
726{
727 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
728}
729
730static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
731{
c8826de8 732 __le32 data;
ac718b69 733
c8826de8 734 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 735
736 return __le32_to_cpu(data);
737}
738
739static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
740{
c8826de8 741 __le32 tmp = __cpu_to_le32(data);
742
743 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 744}
745
746static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
747{
748 u32 data;
c8826de8 749 __le32 tmp;
ac718b69 750 u8 shift = index & 2;
751
752 index &= ~3;
753
c8826de8 754 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 755
c8826de8 756 data = __le32_to_cpu(tmp);
ac718b69 757 data >>= (shift * 8);
758 data &= 0xffff;
759
760 return (u16)data;
761}
762
763static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
764{
c8826de8 765 u32 mask = 0xffff;
766 __le32 tmp;
ac718b69 767 u16 byen = BYTE_EN_WORD;
768 u8 shift = index & 2;
769
770 data &= mask;
771
772 if (index & 2) {
773 byen <<= shift;
774 mask <<= (shift * 8);
775 data <<= (shift * 8);
776 index &= ~3;
777 }
778
c8826de8 779 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 780
c8826de8 781 data |= __le32_to_cpu(tmp) & ~mask;
782 tmp = __cpu_to_le32(data);
ac718b69 783
c8826de8 784 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 785}
786
787static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
788{
789 u32 data;
c8826de8 790 __le32 tmp;
ac718b69 791 u8 shift = index & 3;
792
793 index &= ~3;
794
c8826de8 795 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 796
c8826de8 797 data = __le32_to_cpu(tmp);
ac718b69 798 data >>= (shift * 8);
799 data &= 0xff;
800
801 return (u8)data;
802}
803
804static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
805{
c8826de8 806 u32 mask = 0xff;
807 __le32 tmp;
ac718b69 808 u16 byen = BYTE_EN_BYTE;
809 u8 shift = index & 3;
810
811 data &= mask;
812
813 if (index & 3) {
814 byen <<= shift;
815 mask <<= (shift * 8);
816 data <<= (shift * 8);
817 index &= ~3;
818 }
819
c8826de8 820 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 821
c8826de8 822 data |= __le32_to_cpu(tmp) & ~mask;
823 tmp = __cpu_to_le32(data);
ac718b69 824
c8826de8 825 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 826}
827
ac244d3e 828static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 829{
830 u16 ocp_base, ocp_index;
831
832 ocp_base = addr & 0xf000;
833 if (ocp_base != tp->ocp_base) {
834 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
835 tp->ocp_base = ocp_base;
836 }
837
838 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 839 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 840}
841
ac244d3e 842static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 843{
ac244d3e 844 u16 ocp_base, ocp_index;
ac718b69 845
ac244d3e 846 ocp_base = addr & 0xf000;
847 if (ocp_base != tp->ocp_base) {
848 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
849 tp->ocp_base = ocp_base;
ac718b69 850 }
ac244d3e 851
852 ocp_index = (addr & 0x0fff) | 0xb000;
853 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 854}
855
ac244d3e 856static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 857{
ac244d3e 858 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
859}
ac718b69 860
ac244d3e 861static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
862{
863 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 864}
865
43779f8d 866static void sram_write(struct r8152 *tp, u16 addr, u16 data)
867{
868 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
869 ocp_reg_write(tp, OCP_SRAM_DATA, data);
870}
871
872static u16 sram_read(struct r8152 *tp, u16 addr)
873{
874 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
875 return ocp_reg_read(tp, OCP_SRAM_DATA);
876}
877
ac718b69 878static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
879{
880 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 881 int ret;
ac718b69 882
883 if (phy_id != R8152_PHY_ID)
884 return -EINVAL;
885
9a4be1bd 886 ret = usb_autopm_get_interface(tp->intf);
887 if (ret < 0)
888 goto out;
889
890 ret = r8152_mdio_read(tp, reg);
891
892 usb_autopm_put_interface(tp->intf);
893
894out:
895 return ret;
ac718b69 896}
897
898static
899void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
900{
901 struct r8152 *tp = netdev_priv(netdev);
902
903 if (phy_id != R8152_PHY_ID)
904 return;
905
9a4be1bd 906 if (usb_autopm_get_interface(tp->intf) < 0)
907 return;
908
ac718b69 909 r8152_mdio_write(tp, reg, val);
9a4be1bd 910
911 usb_autopm_put_interface(tp->intf);
ac718b69 912}
913
ebc2ec48 914static
915int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
916
ac718b69 917static inline void set_ethernet_addr(struct r8152 *tp)
918{
919 struct net_device *dev = tp->netdev;
8a91c824 920 int ret;
31787f53 921 u8 node_id[8] = {0};
ac718b69 922
8a91c824 923 if (tp->version == RTL_VER_01)
924 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id);
925 else
926 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id);
927
928 if (ret < 0) {
ac718b69 929 netif_notice(tp, probe, dev, "inet addr fail\n");
8a91c824 930 } else {
931 if (tp->version != RTL_VER_01) {
932 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
933 CRWECR_CONFIG);
934 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES,
935 sizeof(node_id), node_id);
936 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
937 CRWECR_NORAML);
938 }
939
ac718b69 940 memcpy(dev->dev_addr, node_id, dev->addr_len);
941 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
942 }
ac718b69 943}
944
945static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
946{
947 struct r8152 *tp = netdev_priv(netdev);
948 struct sockaddr *addr = p;
949
950 if (!is_valid_ether_addr(addr->sa_data))
951 return -EADDRNOTAVAIL;
952
953 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
954
955 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
956 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
957 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
958
959 return 0;
960}
961
ac718b69 962static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
963{
964 return &dev->stats;
965}
966
967static void read_bulk_callback(struct urb *urb)
968{
ac718b69 969 struct net_device *netdev;
a5a4f468 970 unsigned long flags;
ac718b69 971 int status = urb->status;
ebc2ec48 972 struct rx_agg *agg;
973 struct r8152 *tp;
ac718b69 974 int result;
ac718b69 975
ebc2ec48 976 agg = urb->context;
977 if (!agg)
978 return;
979
980 tp = agg->context;
ac718b69 981 if (!tp)
982 return;
ebc2ec48 983
ac718b69 984 if (test_bit(RTL8152_UNPLUG, &tp->flags))
985 return;
ebc2ec48 986
987 if (!test_bit(WORK_ENABLE, &tp->flags))
988 return;
989
ac718b69 990 netdev = tp->netdev;
7559fb2f 991
992 /* When link down, the driver would cancel all bulks. */
993 /* This avoid the re-submitting bulk */
ebc2ec48 994 if (!netif_carrier_ok(netdev))
ac718b69 995 return;
996
9a4be1bd 997 usb_mark_last_busy(tp->udev);
998
ac718b69 999 switch (status) {
1000 case 0:
ebc2ec48 1001 if (urb->actual_length < ETH_ZLEN)
1002 break;
1003
a5a4f468 1004 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 1005 list_add_tail(&agg->list, &tp->rx_done);
a5a4f468 1006 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1007 tasklet_schedule(&tp->tl);
1008 return;
ac718b69 1009 case -ESHUTDOWN:
1010 set_bit(RTL8152_UNPLUG, &tp->flags);
1011 netif_device_detach(tp->netdev);
ebc2ec48 1012 return;
ac718b69 1013 case -ENOENT:
1014 return; /* the urb is in unlink state */
1015 case -ETIME:
4a8deae2
HW
1016 if (net_ratelimit())
1017 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1018 break;
ac718b69 1019 default:
4a8deae2
HW
1020 if (net_ratelimit())
1021 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1022 break;
ac718b69 1023 }
1024
ebc2ec48 1025 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1026 if (result == -ENODEV) {
1027 netif_device_detach(tp->netdev);
1028 } else if (result) {
a5a4f468 1029 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 1030 list_add_tail(&agg->list, &tp->rx_done);
a5a4f468 1031 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1032 tasklet_schedule(&tp->tl);
ac718b69 1033 }
ac718b69 1034}
1035
ebc2ec48 1036static void write_bulk_callback(struct urb *urb)
ac718b69 1037{
ebc2ec48 1038 struct net_device_stats *stats;
a5a4f468 1039 unsigned long flags;
ebc2ec48 1040 struct tx_agg *agg;
ac718b69 1041 struct r8152 *tp;
ebc2ec48 1042 int status = urb->status;
ac718b69 1043
ebc2ec48 1044 agg = urb->context;
1045 if (!agg)
ac718b69 1046 return;
1047
ebc2ec48 1048 tp = agg->context;
1049 if (!tp)
1050 return;
1051
1052 stats = rtl8152_get_stats(tp->netdev);
1053 if (status) {
4a8deae2
HW
1054 if (net_ratelimit())
1055 netdev_warn(tp->netdev, "Tx status %d\n", status);
ebc2ec48 1056 stats->tx_errors += agg->skb_num;
ac718b69 1057 } else {
ebc2ec48 1058 stats->tx_packets += agg->skb_num;
1059 stats->tx_bytes += agg->skb_len;
ac718b69 1060 }
1061
a5a4f468 1062 spin_lock_irqsave(&tp->tx_lock, flags);
ebc2ec48 1063 list_add_tail(&agg->list, &tp->tx_free);
a5a4f468 1064 spin_unlock_irqrestore(&tp->tx_lock, flags);
ebc2ec48 1065
9a4be1bd 1066 usb_autopm_put_interface_async(tp->intf);
1067
ebc2ec48 1068 if (!netif_carrier_ok(tp->netdev))
1069 return;
1070
1071 if (!test_bit(WORK_ENABLE, &tp->flags))
1072 return;
1073
1074 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1075 return;
1076
1077 if (!skb_queue_empty(&tp->tx_queue))
9a4be1bd 1078 schedule_delayed_work(&tp->schedule, 0);
ac718b69 1079}
1080
40a82917 1081static void intr_callback(struct urb *urb)
1082{
1083 struct r8152 *tp;
500b6d7e 1084 __le16 *d;
40a82917 1085 int status = urb->status;
1086 int res;
1087
1088 tp = urb->context;
1089 if (!tp)
1090 return;
1091
1092 if (!test_bit(WORK_ENABLE, &tp->flags))
1093 return;
1094
1095 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1096 return;
1097
1098 switch (status) {
1099 case 0: /* success */
1100 break;
1101 case -ECONNRESET: /* unlink */
1102 case -ESHUTDOWN:
1103 netif_device_detach(tp->netdev);
1104 case -ENOENT:
1105 return;
1106 case -EOVERFLOW:
1107 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1108 goto resubmit;
1109 /* -EPIPE: should clear the halt */
1110 default:
1111 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1112 goto resubmit;
1113 }
1114
1115 d = urb->transfer_buffer;
1116 if (INTR_LINK & __le16_to_cpu(d[0])) {
1117 if (!(tp->speed & LINK_STATUS)) {
1118 set_bit(RTL8152_LINK_CHG, &tp->flags);
1119 schedule_delayed_work(&tp->schedule, 0);
1120 }
1121 } else {
1122 if (tp->speed & LINK_STATUS) {
1123 set_bit(RTL8152_LINK_CHG, &tp->flags);
1124 schedule_delayed_work(&tp->schedule, 0);
1125 }
1126 }
1127
1128resubmit:
1129 res = usb_submit_urb(urb, GFP_ATOMIC);
1130 if (res == -ENODEV)
1131 netif_device_detach(tp->netdev);
1132 else if (res)
1133 netif_err(tp, intr, tp->netdev,
4a8deae2 1134 "can't resubmit intr, status %d\n", res);
40a82917 1135}
1136
ebc2ec48 1137static inline void *rx_agg_align(void *data)
1138{
8e1f51bd 1139 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1140}
1141
1142static inline void *tx_agg_align(void *data)
1143{
8e1f51bd 1144 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1145}
1146
1147static void free_all_mem(struct r8152 *tp)
1148{
1149 int i;
1150
1151 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1152 usb_free_urb(tp->rx_info[i].urb);
1153 tp->rx_info[i].urb = NULL;
ebc2ec48 1154
9629e3c0 1155 kfree(tp->rx_info[i].buffer);
1156 tp->rx_info[i].buffer = NULL;
1157 tp->rx_info[i].head = NULL;
ebc2ec48 1158 }
1159
1160 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1161 usb_free_urb(tp->tx_info[i].urb);
1162 tp->tx_info[i].urb = NULL;
ebc2ec48 1163
9629e3c0 1164 kfree(tp->tx_info[i].buffer);
1165 tp->tx_info[i].buffer = NULL;
1166 tp->tx_info[i].head = NULL;
ebc2ec48 1167 }
40a82917 1168
9629e3c0 1169 usb_free_urb(tp->intr_urb);
1170 tp->intr_urb = NULL;
40a82917 1171
9629e3c0 1172 kfree(tp->intr_buff);
1173 tp->intr_buff = NULL;
ebc2ec48 1174}
1175
1176static int alloc_all_mem(struct r8152 *tp)
1177{
1178 struct net_device *netdev = tp->netdev;
40a82917 1179 struct usb_interface *intf = tp->intf;
1180 struct usb_host_interface *alt = intf->cur_altsetting;
1181 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1182 struct urb *urb;
1183 int node, i;
1184 u8 *buf;
1185
1186 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1187
1188 spin_lock_init(&tp->rx_lock);
1189 spin_lock_init(&tp->tx_lock);
1190 INIT_LIST_HEAD(&tp->rx_done);
1191 INIT_LIST_HEAD(&tp->tx_free);
1192 skb_queue_head_init(&tp->tx_queue);
1193
1194 for (i = 0; i < RTL8152_MAX_RX; i++) {
1195 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1196 if (!buf)
1197 goto err1;
1198
1199 if (buf != rx_agg_align(buf)) {
1200 kfree(buf);
8e1f51bd 1201 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1202 node);
ebc2ec48 1203 if (!buf)
1204 goto err1;
1205 }
1206
1207 urb = usb_alloc_urb(0, GFP_KERNEL);
1208 if (!urb) {
1209 kfree(buf);
1210 goto err1;
1211 }
1212
1213 INIT_LIST_HEAD(&tp->rx_info[i].list);
1214 tp->rx_info[i].context = tp;
1215 tp->rx_info[i].urb = urb;
1216 tp->rx_info[i].buffer = buf;
1217 tp->rx_info[i].head = rx_agg_align(buf);
1218 }
1219
1220 for (i = 0; i < RTL8152_MAX_TX; i++) {
1221 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1222 if (!buf)
1223 goto err1;
1224
1225 if (buf != tx_agg_align(buf)) {
1226 kfree(buf);
8e1f51bd 1227 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1228 node);
ebc2ec48 1229 if (!buf)
1230 goto err1;
1231 }
1232
1233 urb = usb_alloc_urb(0, GFP_KERNEL);
1234 if (!urb) {
1235 kfree(buf);
1236 goto err1;
1237 }
1238
1239 INIT_LIST_HEAD(&tp->tx_info[i].list);
1240 tp->tx_info[i].context = tp;
1241 tp->tx_info[i].urb = urb;
1242 tp->tx_info[i].buffer = buf;
1243 tp->tx_info[i].head = tx_agg_align(buf);
1244
1245 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1246 }
1247
40a82917 1248 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1249 if (!tp->intr_urb)
1250 goto err1;
1251
1252 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1253 if (!tp->intr_buff)
1254 goto err1;
1255
1256 tp->intr_interval = (int)ep_intr->desc.bInterval;
1257 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1258 tp->intr_buff, INTBUFSIZE, intr_callback,
1259 tp, tp->intr_interval);
1260
ebc2ec48 1261 return 0;
1262
1263err1:
1264 free_all_mem(tp);
1265 return -ENOMEM;
1266}
1267
0de98f6c 1268static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1269{
1270 struct tx_agg *agg = NULL;
1271 unsigned long flags;
1272
1273 spin_lock_irqsave(&tp->tx_lock, flags);
1274 if (!list_empty(&tp->tx_free)) {
1275 struct list_head *cursor;
1276
1277 cursor = tp->tx_free.next;
1278 list_del_init(cursor);
1279 agg = list_entry(cursor, struct tx_agg, list);
1280 }
1281 spin_unlock_irqrestore(&tp->tx_lock, flags);
1282
1283 return agg;
1284}
1285
5bd23881 1286static void
1287r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1288{
1289 memset(desc, 0, sizeof(*desc));
1290
1291 desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1292
1293 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1294 __be16 protocol;
1295 u8 ip_protocol;
1296 u32 opts2 = 0;
1297
1298 if (skb->protocol == htons(ETH_P_8021Q))
1299 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1300 else
1301 protocol = skb->protocol;
1302
1303 switch (protocol) {
1304 case htons(ETH_P_IP):
1305 opts2 |= IPV4_CS;
1306 ip_protocol = ip_hdr(skb)->protocol;
1307 break;
1308
1309 case htons(ETH_P_IPV6):
1310 opts2 |= IPV6_CS;
1311 ip_protocol = ipv6_hdr(skb)->nexthdr;
1312 break;
1313
1314 default:
1315 ip_protocol = IPPROTO_RAW;
1316 break;
1317 }
1318
1319 if (ip_protocol == IPPROTO_TCP) {
1320 opts2 |= TCP_CS;
1321 opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1322 } else if (ip_protocol == IPPROTO_UDP) {
1323 opts2 |= UDP_CS;
1324 } else {
1325 WARN_ON_ONCE(1);
1326 }
1327
1328 desc->opts2 = cpu_to_le32(opts2);
1329 }
1330}
1331
b1379d9a 1332static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1333{
d84130a1 1334 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1335 unsigned long flags;
9a4be1bd 1336 int remain, ret;
b1379d9a 1337 u8 *tx_data;
1338
d84130a1 1339 __skb_queue_head_init(&skb_head);
1340 spin_lock_irqsave(&tx_queue->lock, flags);
1341 skb_queue_splice_init(tx_queue, &skb_head);
1342 spin_unlock_irqrestore(&tx_queue->lock, flags);
1343
b1379d9a 1344 tx_data = agg->head;
1345 agg->skb_num = agg->skb_len = 0;
7937f9e5 1346 remain = rx_buf_sz;
b1379d9a 1347
7937f9e5 1348 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1349 struct tx_desc *tx_desc;
1350 struct sk_buff *skb;
1351 unsigned int len;
1352
d84130a1 1353 skb = __skb_dequeue(&skb_head);
b1379d9a 1354 if (!skb)
1355 break;
1356
7937f9e5 1357 remain -= sizeof(*tx_desc);
b1379d9a 1358 len = skb->len;
1359 if (remain < len) {
d84130a1 1360 __skb_queue_head(&skb_head, skb);
b1379d9a 1361 break;
1362 }
1363
7937f9e5 1364 tx_data = tx_agg_align(tx_data);
b1379d9a 1365 tx_desc = (struct tx_desc *)tx_data;
1366 tx_data += sizeof(*tx_desc);
1367
1368 r8152_tx_csum(tp, tx_desc, skb);
1369 memcpy(tx_data, skb->data, len);
1370 agg->skb_num++;
1371 agg->skb_len += len;
1372 dev_kfree_skb_any(skb);
1373
7937f9e5 1374 tx_data += len;
1375 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1376 }
1377
d84130a1 1378 if (!skb_queue_empty(&skb_head)) {
1379 spin_lock_irqsave(&tx_queue->lock, flags);
1380 skb_queue_splice(&skb_head, tx_queue);
1381 spin_unlock_irqrestore(&tx_queue->lock, flags);
1382 }
1383
9a4be1bd 1384 netif_tx_lock_bh(tp->netdev);
dd1b119c 1385
1386 if (netif_queue_stopped(tp->netdev) &&
1387 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1388 netif_wake_queue(tp->netdev);
1389
9a4be1bd 1390 netif_tx_unlock_bh(tp->netdev);
1391
1392 ret = usb_autopm_get_interface(tp->intf);
1393 if (ret < 0)
1394 goto out_tx_fill;
dd1b119c 1395
b1379d9a 1396 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1397 agg->head, (int)(tx_data - (u8 *)agg->head),
1398 (usb_complete_t)write_bulk_callback, agg);
1399
9a4be1bd 1400 ret = usb_submit_urb(agg->urb, GFP_KERNEL);
1401 if (ret < 0)
1402 usb_autopm_put_interface(tp->intf);
1403
1404out_tx_fill:
1405 return ret;
b1379d9a 1406}
1407
ebc2ec48 1408static void rx_bottom(struct r8152 *tp)
1409{
a5a4f468 1410 unsigned long flags;
d84130a1 1411 struct list_head *cursor, *next, rx_queue;
ebc2ec48 1412
d84130a1 1413 if (list_empty(&tp->rx_done))
1414 return;
1415
1416 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1417 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1418 list_splice_init(&tp->rx_done, &rx_queue);
1419 spin_unlock_irqrestore(&tp->rx_lock, flags);
1420
1421 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1422 struct rx_desc *rx_desc;
1423 struct rx_agg *agg;
43a4478d 1424 int len_used = 0;
1425 struct urb *urb;
1426 u8 *rx_data;
1427 int ret;
1428
ebc2ec48 1429 list_del_init(cursor);
ebc2ec48 1430
1431 agg = list_entry(cursor, struct rx_agg, list);
1432 urb = agg->urb;
0de98f6c 1433 if (urb->actual_length < ETH_ZLEN)
1434 goto submit;
ebc2ec48 1435
ebc2ec48 1436 rx_desc = agg->head;
1437 rx_data = agg->head;
7937f9e5 1438 len_used += sizeof(struct rx_desc);
ebc2ec48 1439
7937f9e5 1440 while (urb->actual_length > len_used) {
43a4478d 1441 struct net_device *netdev = tp->netdev;
1442 struct net_device_stats *stats;
7937f9e5 1443 unsigned int pkt_len;
43a4478d 1444 struct sk_buff *skb;
1445
7937f9e5 1446 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1447 if (pkt_len < ETH_ZLEN)
1448 break;
1449
7937f9e5 1450 len_used += pkt_len;
1451 if (urb->actual_length < len_used)
1452 break;
1453
43a4478d 1454 stats = rtl8152_get_stats(netdev);
1455
8e1f51bd 1456 pkt_len -= CRC_SIZE;
ebc2ec48 1457 rx_data += sizeof(struct rx_desc);
1458
1459 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1460 if (!skb) {
1461 stats->rx_dropped++;
1462 break;
1463 }
1464 memcpy(skb->data, rx_data, pkt_len);
1465 skb_put(skb, pkt_len);
1466 skb->protocol = eth_type_trans(skb, netdev);
9d9aafa1 1467 netif_receive_skb(skb);
ebc2ec48 1468 stats->rx_packets++;
1469 stats->rx_bytes += pkt_len;
1470
8e1f51bd 1471 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1472 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1473 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1474 len_used += sizeof(struct rx_desc);
ebc2ec48 1475 }
1476
0de98f6c 1477submit:
ebc2ec48 1478 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ebc2ec48 1479 if (ret && ret != -ENODEV) {
d84130a1 1480 spin_lock_irqsave(&tp->rx_lock, flags);
1481 list_add_tail(&agg->list, &tp->rx_done);
1482 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1483 tasklet_schedule(&tp->tl);
1484 }
1485 }
ebc2ec48 1486}
1487
1488static void tx_bottom(struct r8152 *tp)
1489{
ebc2ec48 1490 int res;
1491
b1379d9a 1492 do {
1493 struct tx_agg *agg;
ebc2ec48 1494
b1379d9a 1495 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1496 break;
1497
b1379d9a 1498 agg = r8152_get_tx_agg(tp);
1499 if (!agg)
ebc2ec48 1500 break;
ebc2ec48 1501
b1379d9a 1502 res = r8152_tx_agg_fill(tp, agg);
1503 if (res) {
1504 struct net_device_stats *stats;
1505 struct net_device *netdev;
1506 unsigned long flags;
ebc2ec48 1507
b1379d9a 1508 netdev = tp->netdev;
1509 stats = rtl8152_get_stats(netdev);
ebc2ec48 1510
b1379d9a 1511 if (res == -ENODEV) {
1512 netif_device_detach(netdev);
1513 } else {
1514 netif_warn(tp, tx_err, netdev,
1515 "failed tx_urb %d\n", res);
1516 stats->tx_dropped += agg->skb_num;
1517 spin_lock_irqsave(&tp->tx_lock, flags);
1518 list_add_tail(&agg->list, &tp->tx_free);
1519 spin_unlock_irqrestore(&tp->tx_lock, flags);
1520 }
ebc2ec48 1521 }
b1379d9a 1522 } while (res == 0);
ebc2ec48 1523}
1524
1525static void bottom_half(unsigned long data)
ac718b69 1526{
1527 struct r8152 *tp;
ac718b69 1528
ebc2ec48 1529 tp = (struct r8152 *)data;
1530
1531 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1532 return;
1533
1534 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1535 return;
ebc2ec48 1536
7559fb2f 1537 /* When link down, the driver would cancel all bulks. */
1538 /* This avoid the re-submitting bulk */
ebc2ec48 1539 if (!netif_carrier_ok(tp->netdev))
ac718b69 1540 return;
ebc2ec48 1541
1542 rx_bottom(tp);
ebc2ec48 1543}
1544
1545static
1546int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1547{
1548 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1549 agg->head, rx_buf_sz,
1550 (usb_complete_t)read_bulk_callback, agg);
1551
1552 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1553}
1554
00a5e360 1555static void rtl_drop_queued_tx(struct r8152 *tp)
1556{
1557 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1558 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1559 unsigned long flags;
00a5e360 1560 struct sk_buff *skb;
1561
d84130a1 1562 if (skb_queue_empty(tx_queue))
1563 return;
1564
1565 __skb_queue_head_init(&skb_head);
1566 spin_lock_irqsave(&tx_queue->lock, flags);
1567 skb_queue_splice_init(tx_queue, &skb_head);
1568 spin_unlock_irqrestore(&tx_queue->lock, flags);
1569
1570 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1571 dev_kfree_skb(skb);
1572 stats->tx_dropped++;
1573 }
1574}
1575
ac718b69 1576static void rtl8152_tx_timeout(struct net_device *netdev)
1577{
1578 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1579 int i;
1580
4a8deae2 1581 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
ebc2ec48 1582 for (i = 0; i < RTL8152_MAX_TX; i++)
1583 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1584}
1585
1586static void rtl8152_set_rx_mode(struct net_device *netdev)
1587{
1588 struct r8152 *tp = netdev_priv(netdev);
1589
40a82917 1590 if (tp->speed & LINK_STATUS) {
ac718b69 1591 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1592 schedule_delayed_work(&tp->schedule, 0);
1593 }
ac718b69 1594}
1595
1596static void _rtl8152_set_rx_mode(struct net_device *netdev)
1597{
1598 struct r8152 *tp = netdev_priv(netdev);
31787f53 1599 u32 mc_filter[2]; /* Multicast hash filter */
1600 __le32 tmp[2];
ac718b69 1601 u32 ocp_data;
1602
ac718b69 1603 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1604 netif_stop_queue(netdev);
1605 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1606 ocp_data &= ~RCR_ACPT_ALL;
1607 ocp_data |= RCR_AB | RCR_APM;
1608
1609 if (netdev->flags & IFF_PROMISC) {
1610 /* Unconditionally log net taps. */
1611 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1612 ocp_data |= RCR_AM | RCR_AAP;
1613 mc_filter[1] = mc_filter[0] = 0xffffffff;
1614 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1615 (netdev->flags & IFF_ALLMULTI)) {
1616 /* Too many to filter perfectly -- accept all multicasts. */
1617 ocp_data |= RCR_AM;
1618 mc_filter[1] = mc_filter[0] = 0xffffffff;
1619 } else {
1620 struct netdev_hw_addr *ha;
1621
1622 mc_filter[1] = mc_filter[0] = 0;
1623 netdev_for_each_mc_addr(ha, netdev) {
1624 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1625 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1626 ocp_data |= RCR_AM;
1627 }
1628 }
1629
31787f53 1630 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1631 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1632
31787f53 1633 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1634 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1635 netif_wake_queue(netdev);
ac718b69 1636}
1637
1638static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1639 struct net_device *netdev)
1640{
1641 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1642
ebc2ec48 1643 skb_tx_timestamp(skb);
ac718b69 1644
61598788 1645 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1646
dd1b119c 1647 if (list_empty(&tp->tx_free) &&
1648 skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1649 netif_stop_queue(netdev);
1650
61598788 1651 if (!list_empty(&tp->tx_free))
9a4be1bd 1652 schedule_delayed_work(&tp->schedule, 0);
ac718b69 1653
1654 return NETDEV_TX_OK;
1655}
1656
1657static void r8152b_reset_packet_filter(struct r8152 *tp)
1658{
1659 u32 ocp_data;
1660
1661 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1662 ocp_data &= ~FMC_FCR_MCU_EN;
1663 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1664 ocp_data |= FMC_FCR_MCU_EN;
1665 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1666}
1667
1668static void rtl8152_nic_reset(struct r8152 *tp)
1669{
1670 int i;
1671
1672 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1673
1674 for (i = 0; i < 1000; i++) {
1675 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1676 break;
1677 udelay(100);
1678 }
1679}
1680
dd1b119c 1681static void set_tx_qlen(struct r8152 *tp)
1682{
1683 struct net_device *netdev = tp->netdev;
1684
1685 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1686 sizeof(struct tx_desc));
1687}
1688
ac718b69 1689static inline u8 rtl8152_get_speed(struct r8152 *tp)
1690{
1691 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1692}
1693
507605a8 1694static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 1695{
ebc2ec48 1696 u32 ocp_data;
ac718b69 1697 u8 speed;
1698
1699 speed = rtl8152_get_speed(tp);
ebc2ec48 1700 if (speed & _10bps) {
ac718b69 1701 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1702 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1703 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1704 } else {
1705 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1706 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1707 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1708 }
507605a8 1709}
1710
00a5e360 1711static void rxdy_gated_en(struct r8152 *tp, bool enable)
1712{
1713 u32 ocp_data;
1714
1715 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1716 if (enable)
1717 ocp_data |= RXDY_GATED_EN;
1718 else
1719 ocp_data &= ~RXDY_GATED_EN;
1720 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1721}
1722
507605a8 1723static int rtl_enable(struct r8152 *tp)
1724{
1725 u32 ocp_data;
1726 int i, ret;
ac718b69 1727
1728 r8152b_reset_packet_filter(tp);
1729
1730 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1731 ocp_data |= CR_RE | CR_TE;
1732 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1733
00a5e360 1734 rxdy_gated_en(tp, false);
ac718b69 1735
ebc2ec48 1736 INIT_LIST_HEAD(&tp->rx_done);
1737 ret = 0;
1738 for (i = 0; i < RTL8152_MAX_RX; i++) {
1739 INIT_LIST_HEAD(&tp->rx_info[i].list);
1740 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1741 }
ac718b69 1742
ebc2ec48 1743 return ret;
ac718b69 1744}
1745
507605a8 1746static int rtl8152_enable(struct r8152 *tp)
1747{
1748 set_tx_qlen(tp);
1749 rtl_set_eee_plus(tp);
1750
1751 return rtl_enable(tp);
1752}
1753
43779f8d 1754static void r8153_set_rx_agg(struct r8152 *tp)
1755{
1756 u8 speed;
1757
1758 speed = rtl8152_get_speed(tp);
1759 if (speed & _1000bps) {
1760 if (tp->udev->speed == USB_SPEED_SUPER) {
1761 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1762 RX_THR_SUPPER);
1763 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1764 EARLY_AGG_SUPPER);
1765 } else {
1766 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1767 RX_THR_HIGH);
1768 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1769 EARLY_AGG_HIGH);
1770 }
1771 } else {
1772 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
1773 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1774 EARLY_AGG_SLOW);
1775 }
1776}
1777
1778static int rtl8153_enable(struct r8152 *tp)
1779{
1780 set_tx_qlen(tp);
1781 rtl_set_eee_plus(tp);
1782 r8153_set_rx_agg(tp);
1783
1784 return rtl_enable(tp);
1785}
1786
ac718b69 1787static void rtl8152_disable(struct r8152 *tp)
1788{
ebc2ec48 1789 u32 ocp_data;
1790 int i;
ac718b69 1791
1792 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1793 ocp_data &= ~RCR_ACPT_ALL;
1794 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1795
00a5e360 1796 rtl_drop_queued_tx(tp);
ebc2ec48 1797
1798 for (i = 0; i < RTL8152_MAX_TX; i++)
1799 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 1800
00a5e360 1801 rxdy_gated_en(tp, true);
ac718b69 1802
1803 for (i = 0; i < 1000; i++) {
1804 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1805 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1806 break;
1807 mdelay(1);
1808 }
1809
1810 for (i = 0; i < 1000; i++) {
1811 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1812 break;
1813 mdelay(1);
1814 }
1815
ebc2ec48 1816 for (i = 0; i < RTL8152_MAX_RX; i++)
1817 usb_kill_urb(tp->rx_info[i].urb);
ac718b69 1818
1819 rtl8152_nic_reset(tp);
1820}
1821
00a5e360 1822static void r8152_power_cut_en(struct r8152 *tp, bool enable)
1823{
1824 u32 ocp_data;
1825
1826 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1827 if (enable)
1828 ocp_data |= POWER_CUT;
1829 else
1830 ocp_data &= ~POWER_CUT;
1831 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1832
1833 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
1834 ocp_data &= ~RESUME_INDICATE;
1835 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
1836
1837}
1838
21ff2e89 1839#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1840
1841static u32 __rtl_get_wol(struct r8152 *tp)
1842{
1843 u32 ocp_data;
1844 u32 wolopts = 0;
1845
1846 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
1847 if (!(ocp_data & LAN_WAKE_EN))
1848 return 0;
1849
1850 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
1851 if (ocp_data & LINK_ON_WAKE_EN)
1852 wolopts |= WAKE_PHY;
1853
1854 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
1855 if (ocp_data & UWF_EN)
1856 wolopts |= WAKE_UCAST;
1857 if (ocp_data & BWF_EN)
1858 wolopts |= WAKE_BCAST;
1859 if (ocp_data & MWF_EN)
1860 wolopts |= WAKE_MCAST;
1861
1862 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1863 if (ocp_data & MAGIC_EN)
1864 wolopts |= WAKE_MAGIC;
1865
1866 return wolopts;
1867}
1868
1869static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
1870{
1871 u32 ocp_data;
1872
1873 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1874
1875 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
1876 ocp_data &= ~LINK_ON_WAKE_EN;
1877 if (wolopts & WAKE_PHY)
1878 ocp_data |= LINK_ON_WAKE_EN;
1879 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
1880
1881 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
1882 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
1883 if (wolopts & WAKE_UCAST)
1884 ocp_data |= UWF_EN;
1885 if (wolopts & WAKE_BCAST)
1886 ocp_data |= BWF_EN;
1887 if (wolopts & WAKE_MCAST)
1888 ocp_data |= MWF_EN;
1889 if (wolopts & WAKE_ANY)
1890 ocp_data |= LAN_WAKE_EN;
1891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
1892
1893 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1894
1895 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1896 ocp_data &= ~MAGIC_EN;
1897 if (wolopts & WAKE_MAGIC)
1898 ocp_data |= MAGIC_EN;
1899 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1900
1901 if (wolopts & WAKE_ANY)
1902 device_set_wakeup_enable(&tp->udev->dev, true);
1903 else
1904 device_set_wakeup_enable(&tp->udev->dev, false);
1905}
1906
9a4be1bd 1907static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
1908{
1909 if (enable) {
1910 u32 ocp_data;
1911
1912 __rtl_set_wol(tp, WAKE_ANY);
1913
1914 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1915
1916 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
1917 ocp_data |= LINK_OFF_WAKE_EN;
1918 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
1919
1920 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1921 } else {
1922 __rtl_set_wol(tp, tp->saved_wolopts);
1923 }
1924}
1925
aa66a5f1 1926static void rtl_phy_reset(struct r8152 *tp)
1927{
1928 u16 data;
1929 int i;
1930
1931 clear_bit(PHY_RESET, &tp->flags);
1932
1933 data = r8152_mdio_read(tp, MII_BMCR);
1934
1935 /* don't reset again before the previous one complete */
1936 if (data & BMCR_RESET)
1937 return;
1938
1939 data |= BMCR_RESET;
1940 r8152_mdio_write(tp, MII_BMCR, data);
1941
1942 for (i = 0; i < 50; i++) {
1943 msleep(20);
1944 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
1945 break;
1946 }
1947}
1948
4349968a 1949static void rtl_clear_bp(struct r8152 *tp)
1950{
1951 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
1952 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
1953 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
1954 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
1955 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
1956 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
1957 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
1958 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
1959 mdelay(3);
1960 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
1961 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
1962}
1963
1964static void r8153_clear_bp(struct r8152 *tp)
1965{
1966 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
1967 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
1968 rtl_clear_bp(tp);
1969}
1970
1971static void r8153_teredo_off(struct r8152 *tp)
1972{
1973 u32 ocp_data;
1974
1975 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
1976 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
1977 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
1978
1979 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
1980 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
1981 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
1982}
1983
1984static void r8152b_disable_aldps(struct r8152 *tp)
1985{
1986 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1987 msleep(20);
1988}
1989
1990static inline void r8152b_enable_aldps(struct r8152 *tp)
1991{
1992 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1993 LINKENA | DIS_SDSAVE);
1994}
1995
1996static void r8152b_hw_phy_cfg(struct r8152 *tp)
1997{
f0cbe0ac 1998 u16 data;
1999
2000 data = r8152_mdio_read(tp, MII_BMCR);
2001 if (data & BMCR_PDOWN) {
2002 data &= ~BMCR_PDOWN;
2003 r8152_mdio_write(tp, MII_BMCR, data);
2004 }
2005
4349968a 2006 r8152b_disable_aldps(tp);
7e9da481 2007
2008 rtl_clear_bp(tp);
2009
2010 r8152b_enable_aldps(tp);
aa66a5f1 2011 set_bit(PHY_RESET, &tp->flags);
4349968a 2012}
2013
ac718b69 2014static void r8152b_exit_oob(struct r8152 *tp)
2015{
2016 u32 ocp_data;
2017 int i;
2018
2019 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2020 ocp_data &= ~RCR_ACPT_ALL;
2021 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2022
00a5e360 2023 rxdy_gated_en(tp, true);
da9bd117 2024 r8153_teredo_off(tp);
7e9da481 2025 r8152b_hw_phy_cfg(tp);
ac718b69 2026
2027 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2028 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2029
2030 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2031 ocp_data &= ~NOW_IS_OOB;
2032 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2033
2034 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2035 ocp_data &= ~MCU_BORW_EN;
2036 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2037
2038 for (i = 0; i < 1000; i++) {
2039 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2040 if (ocp_data & LINK_LIST_READY)
2041 break;
2042 mdelay(1);
2043 }
2044
2045 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2046 ocp_data |= RE_INIT_LL;
2047 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2048
2049 for (i = 0; i < 1000; i++) {
2050 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2051 if (ocp_data & LINK_LIST_READY)
2052 break;
2053 mdelay(1);
2054 }
2055
2056 rtl8152_nic_reset(tp);
2057
2058 /* rx share fifo credit full threshold */
2059 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2060
2061 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
2062 ocp_data &= STAT_SPEED_MASK;
2063 if (ocp_data == STAT_SPEED_FULL) {
2064 /* rx share fifo credit near full threshold */
2065 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2066 RXFIFO_THR2_FULL);
2067 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2068 RXFIFO_THR3_FULL);
2069 } else {
2070 /* rx share fifo credit near full threshold */
2071 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2072 RXFIFO_THR2_HIGH);
2073 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2074 RXFIFO_THR3_HIGH);
2075 }
2076
2077 /* TX share fifo free credit full threshold */
2078 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2079
2080 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2081 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2082 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2083 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2084
2085 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2086 ocp_data &= ~CPCR_RX_VLAN;
2087 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2088
2089 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2090
2091 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2092 ocp_data |= TCR0_AUTO_FIFO;
2093 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2094}
2095
2096static void r8152b_enter_oob(struct r8152 *tp)
2097{
45f4a19f 2098 u32 ocp_data;
2099 int i;
ac718b69 2100
2101 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2102 ocp_data &= ~NOW_IS_OOB;
2103 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2104
2105 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2106 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2107 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2108
2109 rtl8152_disable(tp);
2110
2111 for (i = 0; i < 1000; i++) {
2112 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2113 if (ocp_data & LINK_LIST_READY)
2114 break;
2115 mdelay(1);
2116 }
2117
2118 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2119 ocp_data |= RE_INIT_LL;
2120 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2121
2122 for (i = 0; i < 1000; i++) {
2123 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2124 if (ocp_data & LINK_LIST_READY)
2125 break;
2126 mdelay(1);
2127 }
2128
2129 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2130
ac718b69 2131 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2132 ocp_data |= CPCR_RX_VLAN;
2133 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2134
2135 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2136 ocp_data |= ALDPS_PROXY_MODE;
2137 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2138
2139 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2140 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2141 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2142
00a5e360 2143 rxdy_gated_en(tp, false);
ac718b69 2144
2145 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2146 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2147 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2148}
2149
43779f8d 2150static void r8153_hw_phy_cfg(struct r8152 *tp)
2151{
2152 u32 ocp_data;
2153 u16 data;
2154
2155 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
f0cbe0ac 2156 data = r8152_mdio_read(tp, MII_BMCR);
2157 if (data & BMCR_PDOWN) {
2158 data &= ~BMCR_PDOWN;
2159 r8152_mdio_write(tp, MII_BMCR, data);
2160 }
43779f8d 2161
7e9da481 2162 r8153_clear_bp(tp);
2163
43779f8d 2164 if (tp->version == RTL_VER_03) {
2165 data = ocp_reg_read(tp, OCP_EEE_CFG);
2166 data &= ~CTAP_SHORT_EN;
2167 ocp_reg_write(tp, OCP_EEE_CFG, data);
2168 }
2169
2170 data = ocp_reg_read(tp, OCP_POWER_CFG);
2171 data |= EEE_CLKDIV_EN;
2172 ocp_reg_write(tp, OCP_POWER_CFG, data);
2173
2174 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2175 data |= EN_10M_BGOFF;
2176 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2177 data = ocp_reg_read(tp, OCP_POWER_CFG);
2178 data |= EN_10M_PLLOFF;
2179 ocp_reg_write(tp, OCP_POWER_CFG, data);
2180 data = sram_read(tp, SRAM_IMPEDANCE);
2181 data &= ~RX_DRIVING_MASK;
2182 sram_write(tp, SRAM_IMPEDANCE, data);
2183
2184 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2185 ocp_data |= PFM_PWM_SWITCH;
2186 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2187
2188 data = sram_read(tp, SRAM_LPF_CFG);
2189 data |= LPF_AUTO_TUNE;
2190 sram_write(tp, SRAM_LPF_CFG, data);
2191
2192 data = sram_read(tp, SRAM_10M_AMP1);
2193 data |= GDAC_IB_UPALL;
2194 sram_write(tp, SRAM_10M_AMP1, data);
2195 data = sram_read(tp, SRAM_10M_AMP2);
2196 data |= AMP_DN;
2197 sram_write(tp, SRAM_10M_AMP2, data);
aa66a5f1 2198
2199 set_bit(PHY_RESET, &tp->flags);
43779f8d 2200}
2201
b9702723 2202static void r8153_u1u2en(struct r8152 *tp, bool enable)
43779f8d 2203{
2204 u8 u1u2[8];
2205
2206 if (enable)
2207 memset(u1u2, 0xff, sizeof(u1u2));
2208 else
2209 memset(u1u2, 0x00, sizeof(u1u2));
2210
2211 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2212}
2213
b9702723 2214static void r8153_u2p3en(struct r8152 *tp, bool enable)
43779f8d 2215{
2216 u32 ocp_data;
2217
2218 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2219 if (enable)
2220 ocp_data |= U2P3_ENABLE;
2221 else
2222 ocp_data &= ~U2P3_ENABLE;
2223 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2224}
2225
b9702723 2226static void r8153_power_cut_en(struct r8152 *tp, bool enable)
43779f8d 2227{
2228 u32 ocp_data;
2229
2230 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2231 if (enable)
2232 ocp_data |= PWR_EN | PHASE2_EN;
2233 else
2234 ocp_data &= ~(PWR_EN | PHASE2_EN);
2235 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2236
2237 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2238 ocp_data &= ~PCUT_STATUS;
2239 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2240}
2241
43779f8d 2242static void r8153_first_init(struct r8152 *tp)
2243{
2244 u32 ocp_data;
2245 int i;
2246
00a5e360 2247 rxdy_gated_en(tp, true);
43779f8d 2248 r8153_teredo_off(tp);
2249
2250 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2251 ocp_data &= ~RCR_ACPT_ALL;
2252 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2253
2254 r8153_hw_phy_cfg(tp);
2255
2256 rtl8152_nic_reset(tp);
2257
2258 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2259 ocp_data &= ~NOW_IS_OOB;
2260 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2261
2262 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2263 ocp_data &= ~MCU_BORW_EN;
2264 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2265
2266 for (i = 0; i < 1000; i++) {
2267 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2268 if (ocp_data & LINK_LIST_READY)
2269 break;
2270 mdelay(1);
2271 }
2272
2273 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2274 ocp_data |= RE_INIT_LL;
2275 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2276
2277 for (i = 0; i < 1000; i++) {
2278 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2279 if (ocp_data & LINK_LIST_READY)
2280 break;
2281 mdelay(1);
2282 }
2283
2284 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2285 ocp_data &= ~CPCR_RX_VLAN;
2286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2287
2288 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2289
2290 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2291 ocp_data |= TCR0_AUTO_FIFO;
2292 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2293
2294 rtl8152_nic_reset(tp);
2295
2296 /* rx share fifo credit full threshold */
2297 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2298 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2299 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2300 /* TX share fifo free credit full threshold */
2301 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2302
9629e3c0 2303 /* rx aggregation */
43779f8d 2304 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2305 ocp_data &= ~RX_AGG_DISABLE;
2306 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2307}
2308
2309static void r8153_enter_oob(struct r8152 *tp)
2310{
2311 u32 ocp_data;
2312 int i;
2313
2314 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2315 ocp_data &= ~NOW_IS_OOB;
2316 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2317
2318 rtl8152_disable(tp);
2319
2320 for (i = 0; i < 1000; i++) {
2321 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2322 if (ocp_data & LINK_LIST_READY)
2323 break;
2324 mdelay(1);
2325 }
2326
2327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2328 ocp_data |= RE_INIT_LL;
2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2330
2331 for (i = 0; i < 1000; i++) {
2332 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2333 if (ocp_data & LINK_LIST_READY)
2334 break;
2335 mdelay(1);
2336 }
2337
2338 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2339
43779f8d 2340 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2341 ocp_data &= ~TEREDO_WAKE_MASK;
2342 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2343
2344 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2345 ocp_data |= CPCR_RX_VLAN;
2346 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2347
2348 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2349 ocp_data |= ALDPS_PROXY_MODE;
2350 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2351
2352 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2353 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2354 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2355
00a5e360 2356 rxdy_gated_en(tp, false);
43779f8d 2357
2358 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2359 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2360 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2361}
2362
2363static void r8153_disable_aldps(struct r8152 *tp)
2364{
2365 u16 data;
2366
2367 data = ocp_reg_read(tp, OCP_POWER_CFG);
2368 data &= ~EN_ALDPS;
2369 ocp_reg_write(tp, OCP_POWER_CFG, data);
2370 msleep(20);
2371}
2372
2373static void r8153_enable_aldps(struct r8152 *tp)
2374{
2375 u16 data;
2376
2377 data = ocp_reg_read(tp, OCP_POWER_CFG);
2378 data |= EN_ALDPS;
2379 ocp_reg_write(tp, OCP_POWER_CFG, data);
2380}
2381
ac718b69 2382static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2383{
43779f8d 2384 u16 bmcr, anar, gbcr;
ac718b69 2385 int ret = 0;
2386
2387 cancel_delayed_work_sync(&tp->schedule);
2388 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2389 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2390 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2391 if (tp->mii.supports_gmii) {
2392 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2393 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2394 } else {
2395 gbcr = 0;
2396 }
ac718b69 2397
2398 if (autoneg == AUTONEG_DISABLE) {
2399 if (speed == SPEED_10) {
2400 bmcr = 0;
2401 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2402 } else if (speed == SPEED_100) {
2403 bmcr = BMCR_SPEED100;
2404 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2405 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2406 bmcr = BMCR_SPEED1000;
2407 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2408 } else {
2409 ret = -EINVAL;
2410 goto out;
2411 }
2412
2413 if (duplex == DUPLEX_FULL)
2414 bmcr |= BMCR_FULLDPLX;
2415 } else {
2416 if (speed == SPEED_10) {
2417 if (duplex == DUPLEX_FULL)
2418 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2419 else
2420 anar |= ADVERTISE_10HALF;
2421 } else if (speed == SPEED_100) {
2422 if (duplex == DUPLEX_FULL) {
2423 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2424 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2425 } else {
2426 anar |= ADVERTISE_10HALF;
2427 anar |= ADVERTISE_100HALF;
2428 }
43779f8d 2429 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2430 if (duplex == DUPLEX_FULL) {
2431 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2432 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2433 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2434 } else {
2435 anar |= ADVERTISE_10HALF;
2436 anar |= ADVERTISE_100HALF;
2437 gbcr |= ADVERTISE_1000HALF;
2438 }
ac718b69 2439 } else {
2440 ret = -EINVAL;
2441 goto out;
2442 }
2443
2444 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2445 }
2446
aa66a5f1 2447 if (test_bit(PHY_RESET, &tp->flags))
2448 bmcr |= BMCR_RESET;
2449
43779f8d 2450 if (tp->mii.supports_gmii)
2451 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2452
ac718b69 2453 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2454 r8152_mdio_write(tp, MII_BMCR, bmcr);
2455
aa66a5f1 2456 if (test_bit(PHY_RESET, &tp->flags)) {
2457 int i;
2458
2459 clear_bit(PHY_RESET, &tp->flags);
2460 for (i = 0; i < 50; i++) {
2461 msleep(20);
2462 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2463 break;
2464 }
2465 }
2466
ac718b69 2467out:
ac718b69 2468
2469 return ret;
2470}
2471
2472static void rtl8152_down(struct r8152 *tp)
2473{
00a5e360 2474 r8152_power_cut_en(tp, false);
ac718b69 2475 r8152b_disable_aldps(tp);
2476 r8152b_enter_oob(tp);
2477 r8152b_enable_aldps(tp);
2478}
2479
43779f8d 2480static void rtl8153_down(struct r8152 *tp)
2481{
b9702723 2482 r8153_u1u2en(tp, false);
2483 r8153_power_cut_en(tp, false);
43779f8d 2484 r8153_disable_aldps(tp);
2485 r8153_enter_oob(tp);
2486 r8153_enable_aldps(tp);
2487}
2488
ac718b69 2489static void set_carrier(struct r8152 *tp)
2490{
2491 struct net_device *netdev = tp->netdev;
2492 u8 speed;
2493
40a82917 2494 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 2495 speed = rtl8152_get_speed(tp);
2496
2497 if (speed & LINK_STATUS) {
2498 if (!(tp->speed & LINK_STATUS)) {
c81229c9 2499 tp->rtl_ops.enable(tp);
ac718b69 2500 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2501 netif_carrier_on(netdev);
2502 }
2503 } else {
2504 if (tp->speed & LINK_STATUS) {
2505 netif_carrier_off(netdev);
ebc2ec48 2506 tasklet_disable(&tp->tl);
c81229c9 2507 tp->rtl_ops.disable(tp);
ebc2ec48 2508 tasklet_enable(&tp->tl);
ac718b69 2509 }
2510 }
2511 tp->speed = speed;
2512}
2513
2514static void rtl_work_func_t(struct work_struct *work)
2515{
2516 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2517
9a4be1bd 2518 if (usb_autopm_get_interface(tp->intf) < 0)
2519 return;
2520
ac718b69 2521 if (!test_bit(WORK_ENABLE, &tp->flags))
2522 goto out1;
2523
2524 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2525 goto out1;
2526
40a82917 2527 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2528 set_carrier(tp);
ac718b69 2529
2530 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2531 _rtl8152_set_rx_mode(tp->netdev);
2532
9a4be1bd 2533 if (tp->speed & LINK_STATUS)
2534 tx_bottom(tp);
aa66a5f1 2535
2536 if (test_bit(PHY_RESET, &tp->flags))
2537 rtl_phy_reset(tp);
2538
ac718b69 2539out1:
9a4be1bd 2540 usb_autopm_put_interface(tp->intf);
ac718b69 2541}
2542
2543static int rtl8152_open(struct net_device *netdev)
2544{
2545 struct r8152 *tp = netdev_priv(netdev);
2546 int res = 0;
2547
7e9da481 2548 res = alloc_all_mem(tp);
2549 if (res)
2550 goto out;
2551
9a4be1bd 2552 res = usb_autopm_get_interface(tp->intf);
2553 if (res < 0) {
2554 free_all_mem(tp);
2555 goto out;
2556 }
2557
2558 /* The WORK_ENABLE may be set when autoresume occurs */
2559 if (test_bit(WORK_ENABLE, &tp->flags)) {
2560 clear_bit(WORK_ENABLE, &tp->flags);
2561 usb_kill_urb(tp->intr_urb);
2562 cancel_delayed_work_sync(&tp->schedule);
2563 if (tp->speed & LINK_STATUS)
2564 tp->rtl_ops.disable(tp);
2565 }
2566
7e9da481 2567 tp->rtl_ops.up(tp);
2568
3d55f44f 2569 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2570 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2571 DUPLEX_FULL);
2572 tp->speed = 0;
2573 netif_carrier_off(netdev);
2574 netif_start_queue(netdev);
2575 set_bit(WORK_ENABLE, &tp->flags);
40a82917 2576 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2577 if (res) {
2578 if (res == -ENODEV)
2579 netif_device_detach(tp->netdev);
4a8deae2
HW
2580 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2581 res);
7e9da481 2582 free_all_mem(tp);
ac718b69 2583 }
2584
9a4be1bd 2585 usb_autopm_put_interface(tp->intf);
ac718b69 2586
7e9da481 2587out:
ac718b69 2588 return res;
2589}
2590
2591static int rtl8152_close(struct net_device *netdev)
2592{
2593 struct r8152 *tp = netdev_priv(netdev);
2594 int res = 0;
2595
2596 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 2597 usb_kill_urb(tp->intr_urb);
ac718b69 2598 cancel_delayed_work_sync(&tp->schedule);
2599 netif_stop_queue(netdev);
9a4be1bd 2600
2601 res = usb_autopm_get_interface(tp->intf);
2602 if (res < 0) {
2603 rtl_drop_queued_tx(tp);
2604 } else {
2605 /*
2606 * The autosuspend may have been enabled and wouldn't
2607 * be disable when autoresume occurs, because the
2608 * netif_running() would be false.
2609 */
2610 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2611 rtl_runtime_suspend_enable(tp, false);
2612 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2613 }
2614
2615 tasklet_disable(&tp->tl);
2616 tp->rtl_ops.down(tp);
2617 tasklet_enable(&tp->tl);
2618 usb_autopm_put_interface(tp->intf);
2619 }
ac718b69 2620
7e9da481 2621 free_all_mem(tp);
2622
ac718b69 2623 return res;
2624}
2625
ac718b69 2626static void r8152b_enable_eee(struct r8152 *tp)
2627{
45f4a19f 2628 u32 ocp_data;
ac718b69 2629
2630 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2631 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2632 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2633 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2634 EEE_10_CAP | EEE_NWAY_EN |
2635 TX_QUIET_EN | RX_QUIET_EN |
2636 SDRISETIME | RG_RXLPI_MSK_HFDUP |
2637 SDFALLTIME);
2638 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2639 RG_LDVQUIET_EN | RG_CKRSEL |
2640 RG_EEEPRG_EN);
2641 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2642 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2643 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2644 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2645 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2646 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2647}
2648
43779f8d 2649static void r8153_enable_eee(struct r8152 *tp)
2650{
2651 u32 ocp_data;
2652 u16 data;
2653
2654 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2655 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2656 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2657 data = ocp_reg_read(tp, OCP_EEE_CFG);
2658 data |= EEE10_EN;
2659 ocp_reg_write(tp, OCP_EEE_CFG, data);
2660 data = ocp_reg_read(tp, OCP_EEE_CFG2);
2661 data |= MY1000_EEE | MY100_EEE;
2662 ocp_reg_write(tp, OCP_EEE_CFG2, data);
2663}
2664
ac718b69 2665static void r8152b_enable_fc(struct r8152 *tp)
2666{
2667 u16 anar;
2668
2669 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2670 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2671 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2672}
2673
ac718b69 2674static void r8152b_init(struct r8152 *tp)
2675{
ebc2ec48 2676 u32 ocp_data;
ac718b69 2677
ac718b69 2678 if (tp->version == RTL_VER_01) {
2679 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2680 ocp_data &= ~LED_MODE_MASK;
2681 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2682 }
2683
00a5e360 2684 r8152_power_cut_en(tp, false);
ac718b69 2685
ac718b69 2686 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2687 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
2688 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2689 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
2690 ocp_data &= ~MCU_CLK_RATIO_MASK;
2691 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
2692 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
2693 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
2694 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
2695 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
2696
2697 r8152b_enable_eee(tp);
2698 r8152b_enable_aldps(tp);
2699 r8152b_enable_fc(tp);
2700
ebc2ec48 2701 /* enable rx aggregation */
ac718b69 2702 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 2703 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 2704 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2705}
2706
43779f8d 2707static void r8153_init(struct r8152 *tp)
2708{
2709 u32 ocp_data;
2710 int i;
2711
b9702723 2712 r8153_u1u2en(tp, false);
43779f8d 2713
2714 for (i = 0; i < 500; i++) {
2715 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2716 AUTOLOAD_DONE)
2717 break;
2718 msleep(20);
2719 }
2720
2721 for (i = 0; i < 500; i++) {
2722 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
2723 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
2724 break;
2725 msleep(20);
2726 }
2727
b9702723 2728 r8153_u2p3en(tp, false);
43779f8d 2729
2730 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
2731 ocp_data &= ~TIMER11_EN;
2732 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
2733
43779f8d 2734 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2735 ocp_data &= ~LED_MODE_MASK;
2736 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2737
2738 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
2739 ocp_data &= ~LPM_TIMER_MASK;
2740 if (tp->udev->speed == USB_SPEED_SUPER)
2741 ocp_data |= LPM_TIMER_500US;
2742 else
2743 ocp_data |= LPM_TIMER_500MS;
2744 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
2745
2746 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
2747 ocp_data &= ~SEN_VAL_MASK;
2748 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
2749 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
2750
b9702723 2751 r8153_power_cut_en(tp, false);
2752 r8153_u1u2en(tp, true);
43779f8d 2753
43779f8d 2754 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
2755 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
2756 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2757 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2758 U1U2_SPDWN_EN | L1_SPDWN_EN);
2759 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2760 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2761 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
2762 EEE_SPDWN_EN);
2763
2764 r8153_enable_eee(tp);
2765 r8153_enable_aldps(tp);
2766 r8152b_enable_fc(tp);
43779f8d 2767}
2768
ac718b69 2769static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
2770{
2771 struct r8152 *tp = usb_get_intfdata(intf);
2772
9a4be1bd 2773 if (PMSG_IS_AUTO(message))
2774 set_bit(SELECTIVE_SUSPEND, &tp->flags);
2775 else
2776 netif_device_detach(tp->netdev);
ac718b69 2777
2778 if (netif_running(tp->netdev)) {
2779 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 2780 usb_kill_urb(tp->intr_urb);
ac718b69 2781 cancel_delayed_work_sync(&tp->schedule);
9a4be1bd 2782 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2783 rtl_runtime_suspend_enable(tp, true);
2784 } else {
2785 tasklet_disable(&tp->tl);
2786 tp->rtl_ops.down(tp);
2787 tasklet_enable(&tp->tl);
2788 }
ac718b69 2789 }
2790
ac718b69 2791 return 0;
2792}
2793
2794static int rtl8152_resume(struct usb_interface *intf)
2795{
2796 struct r8152 *tp = usb_get_intfdata(intf);
2797
9a4be1bd 2798 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2799 tp->rtl_ops.init(tp);
2800 netif_device_attach(tp->netdev);
2801 }
2802
ac718b69 2803 if (netif_running(tp->netdev)) {
9a4be1bd 2804 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2805 rtl_runtime_suspend_enable(tp, false);
2806 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2807 if (tp->speed & LINK_STATUS)
2808 tp->rtl_ops.disable(tp);
2809 } else {
2810 tp->rtl_ops.up(tp);
2811 rtl8152_set_speed(tp, AUTONEG_ENABLE,
43779f8d 2812 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2813 DUPLEX_FULL);
9a4be1bd 2814 }
40a82917 2815 tp->speed = 0;
2816 netif_carrier_off(tp->netdev);
ac718b69 2817 set_bit(WORK_ENABLE, &tp->flags);
40a82917 2818 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
ac718b69 2819 }
2820
2821 return 0;
2822}
2823
21ff2e89 2824static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2825{
2826 struct r8152 *tp = netdev_priv(dev);
2827
9a4be1bd 2828 if (usb_autopm_get_interface(tp->intf) < 0)
2829 return;
2830
21ff2e89 2831 wol->supported = WAKE_ANY;
2832 wol->wolopts = __rtl_get_wol(tp);
9a4be1bd 2833
2834 usb_autopm_put_interface(tp->intf);
21ff2e89 2835}
2836
2837static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2838{
2839 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 2840 int ret;
2841
2842 ret = usb_autopm_get_interface(tp->intf);
2843 if (ret < 0)
2844 goto out_set_wol;
21ff2e89 2845
2846 __rtl_set_wol(tp, wol->wolopts);
2847 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
2848
9a4be1bd 2849 usb_autopm_put_interface(tp->intf);
2850
2851out_set_wol:
2852 return ret;
21ff2e89 2853}
2854
a5ec27c1 2855static u32 rtl8152_get_msglevel(struct net_device *dev)
2856{
2857 struct r8152 *tp = netdev_priv(dev);
2858
2859 return tp->msg_enable;
2860}
2861
2862static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
2863{
2864 struct r8152 *tp = netdev_priv(dev);
2865
2866 tp->msg_enable = value;
2867}
2868
ac718b69 2869static void rtl8152_get_drvinfo(struct net_device *netdev,
2870 struct ethtool_drvinfo *info)
2871{
2872 struct r8152 *tp = netdev_priv(netdev);
2873
2874 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
2875 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
2876 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
2877}
2878
2879static
2880int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2881{
2882 struct r8152 *tp = netdev_priv(netdev);
2883
2884 if (!tp->mii.mdio_read)
2885 return -EOPNOTSUPP;
2886
2887 return mii_ethtool_gset(&tp->mii, cmd);
2888}
2889
2890static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2891{
2892 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 2893 int ret;
2894
2895 ret = usb_autopm_get_interface(tp->intf);
2896 if (ret < 0)
2897 goto out;
ac718b69 2898
9a4be1bd 2899 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
2900
2901 usb_autopm_put_interface(tp->intf);
2902
2903out:
2904 return ret;
ac718b69 2905}
2906
2907static struct ethtool_ops ops = {
2908 .get_drvinfo = rtl8152_get_drvinfo,
2909 .get_settings = rtl8152_get_settings,
2910 .set_settings = rtl8152_set_settings,
2911 .get_link = ethtool_op_get_link,
a5ec27c1 2912 .get_msglevel = rtl8152_get_msglevel,
2913 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 2914 .get_wol = rtl8152_get_wol,
2915 .set_wol = rtl8152_set_wol,
ac718b69 2916};
2917
2918static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2919{
2920 struct r8152 *tp = netdev_priv(netdev);
2921 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 2922 int res;
2923
2924 res = usb_autopm_get_interface(tp->intf);
2925 if (res < 0)
2926 goto out;
ac718b69 2927
2928 switch (cmd) {
2929 case SIOCGMIIPHY:
2930 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2931 break;
2932
2933 case SIOCGMIIREG:
2934 data->val_out = r8152_mdio_read(tp, data->reg_num);
2935 break;
2936
2937 case SIOCSMIIREG:
2938 if (!capable(CAP_NET_ADMIN)) {
2939 res = -EPERM;
2940 break;
2941 }
2942 r8152_mdio_write(tp, data->reg_num, data->val_in);
2943 break;
2944
2945 default:
2946 res = -EOPNOTSUPP;
2947 }
2948
9a4be1bd 2949 usb_autopm_put_interface(tp->intf);
2950
2951out:
ac718b69 2952 return res;
2953}
2954
2955static const struct net_device_ops rtl8152_netdev_ops = {
2956 .ndo_open = rtl8152_open,
2957 .ndo_stop = rtl8152_close,
2958 .ndo_do_ioctl = rtl8152_ioctl,
2959 .ndo_start_xmit = rtl8152_start_xmit,
2960 .ndo_tx_timeout = rtl8152_tx_timeout,
2961 .ndo_set_rx_mode = rtl8152_set_rx_mode,
2962 .ndo_set_mac_address = rtl8152_set_mac_address,
2963
2964 .ndo_change_mtu = eth_change_mtu,
2965 .ndo_validate_addr = eth_validate_addr,
2966};
2967
2968static void r8152b_get_version(struct r8152 *tp)
2969{
2970 u32 ocp_data;
2971 u16 version;
2972
2973 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2974 version = (u16)(ocp_data & VERSION_MASK);
2975
2976 switch (version) {
2977 case 0x4c00:
2978 tp->version = RTL_VER_01;
2979 break;
2980 case 0x4c10:
2981 tp->version = RTL_VER_02;
2982 break;
43779f8d 2983 case 0x5c00:
2984 tp->version = RTL_VER_03;
2985 tp->mii.supports_gmii = 1;
2986 break;
2987 case 0x5c10:
2988 tp->version = RTL_VER_04;
2989 tp->mii.supports_gmii = 1;
2990 break;
2991 case 0x5c20:
2992 tp->version = RTL_VER_05;
2993 tp->mii.supports_gmii = 1;
2994 break;
ac718b69 2995 default:
2996 netif_info(tp, probe, tp->netdev,
2997 "Unknown version 0x%04x\n", version);
2998 break;
2999 }
3000}
3001
e3fe0b1a 3002static void rtl8152_unload(struct r8152 *tp)
3003{
00a5e360 3004 if (tp->version != RTL_VER_01)
3005 r8152_power_cut_en(tp, true);
e3fe0b1a 3006}
3007
43779f8d 3008static void rtl8153_unload(struct r8152 *tp)
3009{
b9702723 3010 r8153_power_cut_en(tp, true);
43779f8d 3011}
3012
31ca1dec 3013static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
c81229c9 3014{
3015 struct rtl_ops *ops = &tp->rtl_ops;
31ca1dec 3016 int ret = -ENODEV;
c81229c9 3017
3018 switch (id->idVendor) {
3019 case VENDOR_ID_REALTEK:
3020 switch (id->idProduct) {
3021 case PRODUCT_ID_RTL8152:
3022 ops->init = r8152b_init;
3023 ops->enable = rtl8152_enable;
3024 ops->disable = rtl8152_disable;
7e9da481 3025 ops->up = r8152b_exit_oob;
c81229c9 3026 ops->down = rtl8152_down;
3027 ops->unload = rtl8152_unload;
31ca1dec 3028 ret = 0;
c81229c9 3029 break;
43779f8d 3030 case PRODUCT_ID_RTL8153:
3031 ops->init = r8153_init;
3032 ops->enable = rtl8153_enable;
3033 ops->disable = rtl8152_disable;
7e9da481 3034 ops->up = r8153_first_init;
43779f8d 3035 ops->down = rtl8153_down;
3036 ops->unload = rtl8153_unload;
31ca1dec 3037 ret = 0;
43779f8d 3038 break;
3039 default:
43779f8d 3040 break;
3041 }
3042 break;
3043
3044 case VENDOR_ID_SAMSUNG:
3045 switch (id->idProduct) {
3046 case PRODUCT_ID_SAMSUNG:
3047 ops->init = r8153_init;
3048 ops->enable = rtl8153_enable;
3049 ops->disable = rtl8152_disable;
7e9da481 3050 ops->up = r8153_first_init;
43779f8d 3051 ops->down = rtl8153_down;
3052 ops->unload = rtl8153_unload;
31ca1dec 3053 ret = 0;
43779f8d 3054 break;
c81229c9 3055 default:
c81229c9 3056 break;
3057 }
3058 break;
3059
3060 default:
c81229c9 3061 break;
3062 }
3063
31ca1dec 3064 if (ret)
3065 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3066
c81229c9 3067 return ret;
3068}
3069
ac718b69 3070static int rtl8152_probe(struct usb_interface *intf,
3071 const struct usb_device_id *id)
3072{
3073 struct usb_device *udev = interface_to_usbdev(intf);
3074 struct r8152 *tp;
3075 struct net_device *netdev;
ebc2ec48 3076 int ret;
ac718b69 3077
ac718b69 3078 netdev = alloc_etherdev(sizeof(struct r8152));
3079 if (!netdev) {
4a8deae2 3080 dev_err(&intf->dev, "Out of memory\n");
ac718b69 3081 return -ENOMEM;
3082 }
3083
ebc2ec48 3084 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 3085 tp = netdev_priv(netdev);
3086 tp->msg_enable = 0x7FFF;
3087
e3ad412a 3088 tp->udev = udev;
3089 tp->netdev = netdev;
3090 tp->intf = intf;
3091
31ca1dec 3092 ret = rtl_ops_init(tp, id);
3093 if (ret)
3094 goto out;
c81229c9 3095
ebc2ec48 3096 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
ac718b69 3097 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3098
ac718b69 3099 netdev->netdev_ops = &rtl8152_netdev_ops;
3100 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 3101
3102 netdev->features |= NETIF_F_IP_CSUM;
3103 netdev->hw_features = NETIF_F_IP_CSUM;
ac718b69 3104 SET_ETHTOOL_OPS(netdev, &ops);
ac718b69 3105
3106 tp->mii.dev = netdev;
3107 tp->mii.mdio_read = read_mii_word;
3108 tp->mii.mdio_write = write_mii_word;
3109 tp->mii.phy_id_mask = 0x3f;
3110 tp->mii.reg_num_mask = 0x1f;
3111 tp->mii.phy_id = R8152_PHY_ID;
3112 tp->mii.supports_gmii = 0;
3113
9a4be1bd 3114 intf->needs_remote_wakeup = 1;
3115
ac718b69 3116 r8152b_get_version(tp);
c81229c9 3117 tp->rtl_ops.init(tp);
ac718b69 3118 set_ethernet_addr(tp);
3119
ac718b69 3120 usb_set_intfdata(intf, tp);
ac718b69 3121
ebc2ec48 3122 ret = register_netdev(netdev);
3123 if (ret != 0) {
4a8deae2 3124 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 3125 goto out1;
ac718b69 3126 }
3127
21ff2e89 3128 tp->saved_wolopts = __rtl_get_wol(tp);
3129 if (tp->saved_wolopts)
3130 device_set_wakeup_enable(&udev->dev, true);
3131 else
3132 device_set_wakeup_enable(&udev->dev, false);
3133
4a8deae2 3134 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 3135
3136 return 0;
3137
ac718b69 3138out1:
ebc2ec48 3139 usb_set_intfdata(intf, NULL);
ac718b69 3140out:
3141 free_netdev(netdev);
ebc2ec48 3142 return ret;
ac718b69 3143}
3144
ac718b69 3145static void rtl8152_disconnect(struct usb_interface *intf)
3146{
3147 struct r8152 *tp = usb_get_intfdata(intf);
3148
3149 usb_set_intfdata(intf, NULL);
3150 if (tp) {
3151 set_bit(RTL8152_UNPLUG, &tp->flags);
3152 tasklet_kill(&tp->tl);
3153 unregister_netdev(tp->netdev);
c81229c9 3154 tp->rtl_ops.unload(tp);
ac718b69 3155 free_netdev(tp->netdev);
3156 }
3157}
3158
3159/* table of devices that work with this driver */
3160static struct usb_device_id rtl8152_table[] = {
c7de7dec 3161 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3162 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3163 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
ac718b69 3164 {}
3165};
3166
3167MODULE_DEVICE_TABLE(usb, rtl8152_table);
3168
3169static struct usb_driver rtl8152_driver = {
3170 .name = MODULENAME,
ebc2ec48 3171 .id_table = rtl8152_table,
ac718b69 3172 .probe = rtl8152_probe,
3173 .disconnect = rtl8152_disconnect,
ac718b69 3174 .suspend = rtl8152_suspend,
ebc2ec48 3175 .resume = rtl8152_resume,
3176 .reset_resume = rtl8152_resume,
9a4be1bd 3177 .supports_autosuspend = 1,
a634782f 3178 .disable_hub_initiated_lpm = 1,
ac718b69 3179};
3180
b4236daa 3181module_usb_driver(rtl8152_driver);
ac718b69 3182
3183MODULE_AUTHOR(DRIVER_AUTHOR);
3184MODULE_DESCRIPTION(DRIVER_DESC);
3185MODULE_LICENSE("GPL");
This page took 0.417788 seconds and 5 git commands to generate.