r8152: split DRIVER_VERSION
[deliverable/linux.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
d9a28c5b 27#include <linux/usb/cdc.h>
ac718b69 28
d0942473 29/* Information for net-next */
30#define NETNEXT_VERSION "08"
31
32/* Information for net */
33#define NET_VERSION "1"
34
35#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
ac718b69 36#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 37#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 38#define MODULENAME "r8152"
39
40#define R8152_PHY_ID 32
41
42#define PLA_IDR 0xc000
43#define PLA_RCR 0xc010
44#define PLA_RMS 0xc016
45#define PLA_RXFIFO_CTRL0 0xc0a0
46#define PLA_RXFIFO_CTRL1 0xc0a4
47#define PLA_RXFIFO_CTRL2 0xc0a8
65bab84c 48#define PLA_DMY_REG0 0xc0b0
ac718b69 49#define PLA_FMC 0xc0b4
50#define PLA_CFG_WOL 0xc0b6
43779f8d 51#define PLA_TEREDO_CFG 0xc0bc
ac718b69 52#define PLA_MAR 0xcd00
43779f8d 53#define PLA_BACKUP 0xd000
ac718b69 54#define PAL_BDC_CR 0xd1a0
43779f8d 55#define PLA_TEREDO_TIMER 0xd2cc
56#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 57#define PLA_LEDSEL 0xdd90
58#define PLA_LED_FEATURE 0xdd92
59#define PLA_PHYAR 0xde00
43779f8d 60#define PLA_BOOT_CTRL 0xe004
ac718b69 61#define PLA_GPHY_INTR_IMR 0xe022
62#define PLA_EEE_CR 0xe040
63#define PLA_EEEP_CR 0xe080
64#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 65#define PLA_MAC_PWR_CTRL2 0xe0ca
66#define PLA_MAC_PWR_CTRL3 0xe0cc
67#define PLA_MAC_PWR_CTRL4 0xe0ce
68#define PLA_WDT6_CTRL 0xe428
ac718b69 69#define PLA_TCR0 0xe610
70#define PLA_TCR1 0xe612
69b4b7a4 71#define PLA_MTPS 0xe615
ac718b69 72#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 73#define PLA_RSTTALLY 0xe800
ac718b69 74#define PLA_CR 0xe813
75#define PLA_CRWECR 0xe81c
21ff2e89 76#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
77#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 78#define PLA_CONFIG5 0xe822
79#define PLA_PHY_PWR 0xe84c
80#define PLA_OOB_CTRL 0xe84f
81#define PLA_CPCR 0xe854
82#define PLA_MISC_0 0xe858
83#define PLA_MISC_1 0xe85a
84#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 85#define PLA_TALLYCNT 0xe890
ac718b69 86#define PLA_SFF_STS_7 0xe8de
87#define PLA_PHYSTATUS 0xe908
88#define PLA_BP_BA 0xfc26
89#define PLA_BP_0 0xfc28
90#define PLA_BP_1 0xfc2a
91#define PLA_BP_2 0xfc2c
92#define PLA_BP_3 0xfc2e
93#define PLA_BP_4 0xfc30
94#define PLA_BP_5 0xfc32
95#define PLA_BP_6 0xfc34
96#define PLA_BP_7 0xfc36
43779f8d 97#define PLA_BP_EN 0xfc38
ac718b69 98
65bab84c 99#define USB_USB2PHY 0xb41e
100#define USB_SSPHYLINK2 0xb428
43779f8d 101#define USB_U2P3_CTRL 0xb460
65bab84c 102#define USB_CSR_DUMMY1 0xb464
103#define USB_CSR_DUMMY2 0xb466
ac718b69 104#define USB_DEV_STAT 0xb808
65bab84c 105#define USB_CONNECT_TIMER 0xcbf8
106#define USB_BURST_SIZE 0xcfc0
ac718b69 107#define USB_USB_CTRL 0xd406
108#define USB_PHY_CTRL 0xd408
109#define USB_TX_AGG 0xd40a
110#define USB_RX_BUF_TH 0xd40c
111#define USB_USB_TIMER 0xd428
464ec10a 112#define USB_RX_EARLY_TIMEOUT 0xd42c
113#define USB_RX_EARLY_SIZE 0xd42e
ac718b69 114#define USB_PM_CTRL_STATUS 0xd432
115#define USB_TX_DMA 0xd434
43779f8d 116#define USB_TOLERANCE 0xd490
117#define USB_LPM_CTRL 0xd41a
ac718b69 118#define USB_UPS_CTRL 0xd800
43779f8d 119#define USB_MISC_0 0xd81a
120#define USB_POWER_CUT 0xd80a
121#define USB_AFE_CTRL2 0xd824
122#define USB_WDT11_CTRL 0xe43c
ac718b69 123#define USB_BP_BA 0xfc26
124#define USB_BP_0 0xfc28
125#define USB_BP_1 0xfc2a
126#define USB_BP_2 0xfc2c
127#define USB_BP_3 0xfc2e
128#define USB_BP_4 0xfc30
129#define USB_BP_5 0xfc32
130#define USB_BP_6 0xfc34
131#define USB_BP_7 0xfc36
43779f8d 132#define USB_BP_EN 0xfc38
ac718b69 133
134/* OCP Registers */
135#define OCP_ALDPS_CONFIG 0x2010
136#define OCP_EEE_CONFIG1 0x2080
137#define OCP_EEE_CONFIG2 0x2092
138#define OCP_EEE_CONFIG3 0x2094
ac244d3e 139#define OCP_BASE_MII 0xa400
ac718b69 140#define OCP_EEE_AR 0xa41a
141#define OCP_EEE_DATA 0xa41c
43779f8d 142#define OCP_PHY_STATUS 0xa420
143#define OCP_POWER_CFG 0xa430
144#define OCP_EEE_CFG 0xa432
145#define OCP_SRAM_ADDR 0xa436
146#define OCP_SRAM_DATA 0xa438
147#define OCP_DOWN_SPEED 0xa442
df35d283 148#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 149#define OCP_EEE_ADV 0xa5d0
df35d283 150#define OCP_EEE_LPABLE 0xa5d2
43779f8d 151#define OCP_ADC_CFG 0xbc06
152
153/* SRAM Register */
154#define SRAM_LPF_CFG 0x8012
155#define SRAM_10M_AMP1 0x8080
156#define SRAM_10M_AMP2 0x8082
157#define SRAM_IMPEDANCE 0x8084
ac718b69 158
159/* PLA_RCR */
160#define RCR_AAP 0x00000001
161#define RCR_APM 0x00000002
162#define RCR_AM 0x00000004
163#define RCR_AB 0x00000008
164#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
165
166/* PLA_RXFIFO_CTRL0 */
167#define RXFIFO_THR1_NORMAL 0x00080002
168#define RXFIFO_THR1_OOB 0x01800003
169
170/* PLA_RXFIFO_CTRL1 */
171#define RXFIFO_THR2_FULL 0x00000060
172#define RXFIFO_THR2_HIGH 0x00000038
173#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 174#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 175
176/* PLA_RXFIFO_CTRL2 */
177#define RXFIFO_THR3_FULL 0x00000078
178#define RXFIFO_THR3_HIGH 0x00000048
179#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 180#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 181
182/* PLA_TXFIFO_CTRL */
183#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 184#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 185
65bab84c 186/* PLA_DMY_REG0 */
187#define ECM_ALDPS 0x0002
188
ac718b69 189/* PLA_FMC */
190#define FMC_FCR_MCU_EN 0x0001
191
192/* PLA_EEEP_CR */
193#define EEEP_CR_EEEP_TX 0x0002
194
43779f8d 195/* PLA_WDT6_CTRL */
196#define WDT6_SET_MODE 0x0010
197
ac718b69 198/* PLA_TCR0 */
199#define TCR0_TX_EMPTY 0x0800
200#define TCR0_AUTO_FIFO 0x0080
201
202/* PLA_TCR1 */
203#define VERSION_MASK 0x7cf0
204
69b4b7a4 205/* PLA_MTPS */
206#define MTPS_JUMBO (12 * 1024 / 64)
207#define MTPS_DEFAULT (6 * 1024 / 64)
208
4f1d4d54 209/* PLA_RSTTALLY */
210#define TALLY_RESET 0x0001
211
ac718b69 212/* PLA_CR */
213#define CR_RST 0x10
214#define CR_RE 0x08
215#define CR_TE 0x04
216
217/* PLA_CRWECR */
218#define CRWECR_NORAML 0x00
219#define CRWECR_CONFIG 0xc0
220
221/* PLA_OOB_CTRL */
222#define NOW_IS_OOB 0x80
223#define TXFIFO_EMPTY 0x20
224#define RXFIFO_EMPTY 0x10
225#define LINK_LIST_READY 0x02
226#define DIS_MCU_CLROOB 0x01
227#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
228
229/* PLA_MISC_1 */
230#define RXDY_GATED_EN 0x0008
231
232/* PLA_SFF_STS_7 */
233#define RE_INIT_LL 0x8000
234#define MCU_BORW_EN 0x4000
235
236/* PLA_CPCR */
237#define CPCR_RX_VLAN 0x0040
238
239/* PLA_CFG_WOL */
240#define MAGIC_EN 0x0001
241
43779f8d 242/* PLA_TEREDO_CFG */
243#define TEREDO_SEL 0x8000
244#define TEREDO_WAKE_MASK 0x7f00
245#define TEREDO_RS_EVENT_MASK 0x00fe
246#define OOB_TEREDO_EN 0x0001
247
ac718b69 248/* PAL_BDC_CR */
249#define ALDPS_PROXY_MODE 0x0001
250
21ff2e89 251/* PLA_CONFIG34 */
252#define LINK_ON_WAKE_EN 0x0010
253#define LINK_OFF_WAKE_EN 0x0008
254
ac718b69 255/* PLA_CONFIG5 */
21ff2e89 256#define BWF_EN 0x0040
257#define MWF_EN 0x0020
258#define UWF_EN 0x0010
ac718b69 259#define LAN_WAKE_EN 0x0002
260
261/* PLA_LED_FEATURE */
262#define LED_MODE_MASK 0x0700
263
264/* PLA_PHY_PWR */
265#define TX_10M_IDLE_EN 0x0080
266#define PFM_PWM_SWITCH 0x0040
267
268/* PLA_MAC_PWR_CTRL */
269#define D3_CLK_GATED_EN 0x00004000
270#define MCU_CLK_RATIO 0x07010f07
271#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 272#define ALDPS_SPDWN_RATIO 0x0f87
273
274/* PLA_MAC_PWR_CTRL2 */
275#define EEE_SPDWN_RATIO 0x8007
276
277/* PLA_MAC_PWR_CTRL3 */
278#define PKT_AVAIL_SPDWN_EN 0x0100
279#define SUSPEND_SPDWN_EN 0x0004
280#define U1U2_SPDWN_EN 0x0002
281#define L1_SPDWN_EN 0x0001
282
283/* PLA_MAC_PWR_CTRL4 */
284#define PWRSAVE_SPDWN_EN 0x1000
285#define RXDV_SPDWN_EN 0x0800
286#define TX10MIDLE_EN 0x0100
287#define TP100_SPDWN_EN 0x0020
288#define TP500_SPDWN_EN 0x0010
289#define TP1000_SPDWN_EN 0x0008
290#define EEE_SPDWN_EN 0x0001
ac718b69 291
292/* PLA_GPHY_INTR_IMR */
293#define GPHY_STS_MSK 0x0001
294#define SPEED_DOWN_MSK 0x0002
295#define SPDWN_RXDV_MSK 0x0004
296#define SPDWN_LINKCHG_MSK 0x0008
297
298/* PLA_PHYAR */
299#define PHYAR_FLAG 0x80000000
300
301/* PLA_EEE_CR */
302#define EEE_RX_EN 0x0001
303#define EEE_TX_EN 0x0002
304
43779f8d 305/* PLA_BOOT_CTRL */
306#define AUTOLOAD_DONE 0x0002
307
65bab84c 308/* USB_USB2PHY */
309#define USB2PHY_SUSPEND 0x0001
310#define USB2PHY_L1 0x0002
311
312/* USB_SSPHYLINK2 */
313#define pwd_dn_scale_mask 0x3ffe
314#define pwd_dn_scale(x) ((x) << 1)
315
316/* USB_CSR_DUMMY1 */
317#define DYNAMIC_BURST 0x0001
318
319/* USB_CSR_DUMMY2 */
320#define EP4_FULL_FC 0x0001
321
ac718b69 322/* USB_DEV_STAT */
323#define STAT_SPEED_MASK 0x0006
324#define STAT_SPEED_HIGH 0x0000
a3cc465d 325#define STAT_SPEED_FULL 0x0002
ac718b69 326
327/* USB_TX_AGG */
328#define TX_AGG_MAX_THRESHOLD 0x03
329
330/* USB_RX_BUF_TH */
43779f8d 331#define RX_THR_SUPPER 0x0c350180
8e1f51bd 332#define RX_THR_HIGH 0x7a120180
43779f8d 333#define RX_THR_SLOW 0xffff0180
ac718b69 334
335/* USB_TX_DMA */
336#define TEST_MODE_DISABLE 0x00000001
337#define TX_SIZE_ADJUST1 0x00000100
338
339/* USB_UPS_CTRL */
340#define POWER_CUT 0x0100
341
342/* USB_PM_CTRL_STATUS */
8e1f51bd 343#define RESUME_INDICATE 0x0001
ac718b69 344
345/* USB_USB_CTRL */
346#define RX_AGG_DISABLE 0x0010
e90fba8d 347#define RX_ZERO_EN 0x0080
ac718b69 348
43779f8d 349/* USB_U2P3_CTRL */
350#define U2P3_ENABLE 0x0001
351
352/* USB_POWER_CUT */
353#define PWR_EN 0x0001
354#define PHASE2_EN 0x0008
355
356/* USB_MISC_0 */
357#define PCUT_STATUS 0x0001
358
464ec10a 359/* USB_RX_EARLY_TIMEOUT */
360#define COALESCE_SUPER 85000U
361#define COALESCE_HIGH 250000U
362#define COALESCE_SLOW 524280U
43779f8d 363
364/* USB_WDT11_CTRL */
365#define TIMER11_EN 0x0001
366
367/* USB_LPM_CTRL */
65bab84c 368/* bit 4 ~ 5: fifo empty boundary */
369#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
370/* bit 2 ~ 3: LMP timer */
43779f8d 371#define LPM_TIMER_MASK 0x0c
372#define LPM_TIMER_500MS 0x04 /* 500 ms */
373#define LPM_TIMER_500US 0x0c /* 500 us */
65bab84c 374#define ROK_EXIT_LPM 0x02
43779f8d 375
376/* USB_AFE_CTRL2 */
377#define SEN_VAL_MASK 0xf800
378#define SEN_VAL_NORMAL 0xa000
379#define SEL_RXIDLE 0x0100
380
ac718b69 381/* OCP_ALDPS_CONFIG */
382#define ENPWRSAVE 0x8000
383#define ENPDNPS 0x0200
384#define LINKENA 0x0100
385#define DIS_SDSAVE 0x0010
386
43779f8d 387/* OCP_PHY_STATUS */
388#define PHY_STAT_MASK 0x0007
389#define PHY_STAT_LAN_ON 3
390#define PHY_STAT_PWRDN 5
391
392/* OCP_POWER_CFG */
393#define EEE_CLKDIV_EN 0x8000
394#define EN_ALDPS 0x0004
395#define EN_10M_PLLOFF 0x0001
396
ac718b69 397/* OCP_EEE_CONFIG1 */
398#define RG_TXLPI_MSK_HFDUP 0x8000
399#define RG_MATCLR_EN 0x4000
400#define EEE_10_CAP 0x2000
401#define EEE_NWAY_EN 0x1000
402#define TX_QUIET_EN 0x0200
403#define RX_QUIET_EN 0x0100
d24f6134 404#define sd_rise_time_mask 0x0070
4c4a6b1b 405#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 406#define RG_RXLPI_MSK_HFDUP 0x0008
407#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
408
409/* OCP_EEE_CONFIG2 */
410#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
411#define RG_DACQUIET_EN 0x0400
412#define RG_LDVQUIET_EN 0x0200
413#define RG_CKRSEL 0x0020
414#define RG_EEEPRG_EN 0x0010
415
416/* OCP_EEE_CONFIG3 */
d24f6134 417#define fast_snr_mask 0xff80
4c4a6b1b 418#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 419#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
420#define MSK_PH 0x0006 /* bit 0 ~ 3 */
421
422/* OCP_EEE_AR */
423/* bit[15:14] function */
424#define FUN_ADDR 0x0000
425#define FUN_DATA 0x4000
426/* bit[4:0] device addr */
ac718b69 427
43779f8d 428/* OCP_EEE_CFG */
429#define CTAP_SHORT_EN 0x0040
430#define EEE10_EN 0x0010
431
432/* OCP_DOWN_SPEED */
433#define EN_10M_BGOFF 0x0080
434
43779f8d 435/* OCP_ADC_CFG */
436#define CKADSEL_L 0x0100
437#define ADC_EN 0x0080
438#define EN_EMI_L 0x0040
439
440/* SRAM_LPF_CFG */
441#define LPF_AUTO_TUNE 0x8000
442
443/* SRAM_10M_AMP1 */
444#define GDAC_IB_UPALL 0x0008
445
446/* SRAM_10M_AMP2 */
447#define AMP_DN 0x0200
448
449/* SRAM_IMPEDANCE */
450#define RX_DRIVING_MASK 0x6000
451
ac718b69 452enum rtl_register_content {
43779f8d 453 _1000bps = 0x10,
ac718b69 454 _100bps = 0x08,
455 _10bps = 0x04,
456 LINK_STATUS = 0x02,
457 FULL_DUP = 0x01,
458};
459
1764bcd9 460#define RTL8152_MAX_TX 4
ebc2ec48 461#define RTL8152_MAX_RX 10
40a82917 462#define INTBUFSIZE 2
8e1f51bd 463#define CRC_SIZE 4
464#define TX_ALIGN 4
465#define RX_ALIGN 8
40a82917 466
467#define INTR_LINK 0x0004
ebc2ec48 468
ac718b69 469#define RTL8152_REQT_READ 0xc0
470#define RTL8152_REQT_WRITE 0x40
471#define RTL8152_REQ_GET_REGS 0x05
472#define RTL8152_REQ_SET_REGS 0x05
473
474#define BYTE_EN_DWORD 0xff
475#define BYTE_EN_WORD 0x33
476#define BYTE_EN_BYTE 0x11
477#define BYTE_EN_SIX_BYTES 0x3f
478#define BYTE_EN_START_MASK 0x0f
479#define BYTE_EN_END_MASK 0xf0
480
69b4b7a4 481#define RTL8153_MAX_PACKET 9216 /* 9K */
482#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 483#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 484#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 485#define RTL8152_TX_TIMEOUT (5 * HZ)
d823ab68 486#define RTL8152_NAPI_WEIGHT 64
ac718b69 487
488/* rtl8152 flags */
489enum rtl8152_flags {
490 RTL8152_UNPLUG = 0,
ac718b69 491 RTL8152_SET_RX_MODE,
40a82917 492 WORK_ENABLE,
493 RTL8152_LINK_CHG,
9a4be1bd 494 SELECTIVE_SUSPEND,
aa66a5f1 495 PHY_RESET,
d823ab68 496 SCHEDULE_NAPI,
ac718b69 497};
498
499/* Define these values to match your device */
500#define VENDOR_ID_REALTEK 0x0bda
43779f8d 501#define VENDOR_ID_SAMSUNG 0x04e8
347eec34 502#define VENDOR_ID_LENOVO 0x17ef
d065c3c1 503#define VENDOR_ID_NVIDIA 0x0955
ac718b69 504
505#define MCU_TYPE_PLA 0x0100
506#define MCU_TYPE_USB 0x0000
507
4f1d4d54 508struct tally_counter {
509 __le64 tx_packets;
510 __le64 rx_packets;
511 __le64 tx_errors;
512 __le32 rx_errors;
513 __le16 rx_missed;
514 __le16 align_errors;
515 __le32 tx_one_collision;
516 __le32 tx_multi_collision;
517 __le64 rx_unicast;
518 __le64 rx_broadcast;
519 __le32 rx_multicast;
520 __le16 tx_aborted;
f37119c5 521 __le16 tx_underrun;
4f1d4d54 522};
523
ac718b69 524struct rx_desc {
500b6d7e 525 __le32 opts1;
ac718b69 526#define RX_LEN_MASK 0x7fff
565cab0a 527
500b6d7e 528 __le32 opts2;
f5aaaa6d 529#define RD_UDP_CS BIT(23)
530#define RD_TCP_CS BIT(22)
531#define RD_IPV6_CS BIT(20)
532#define RD_IPV4_CS BIT(19)
565cab0a 533
500b6d7e 534 __le32 opts3;
f5aaaa6d 535#define IPF BIT(23) /* IP checksum fail */
536#define UDPF BIT(22) /* UDP checksum fail */
537#define TCPF BIT(21) /* TCP checksum fail */
538#define RX_VLAN_TAG BIT(16)
565cab0a 539
500b6d7e 540 __le32 opts4;
541 __le32 opts5;
542 __le32 opts6;
ac718b69 543};
544
545struct tx_desc {
500b6d7e 546 __le32 opts1;
f5aaaa6d 547#define TX_FS BIT(31) /* First segment of a packet */
548#define TX_LS BIT(30) /* Final segment of a packet */
549#define GTSENDV4 BIT(28)
550#define GTSENDV6 BIT(27)
60c89071 551#define GTTCPHO_SHIFT 18
6128d1bb 552#define GTTCPHO_MAX 0x7fU
60c89071 553#define TX_LEN_MAX 0x3ffffU
5bd23881 554
500b6d7e 555 __le32 opts2;
f5aaaa6d 556#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
557#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
558#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
559#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
60c89071 560#define MSS_SHIFT 17
561#define MSS_MAX 0x7ffU
562#define TCPHO_SHIFT 17
6128d1bb 563#define TCPHO_MAX 0x7ffU
f5aaaa6d 564#define TX_VLAN_TAG BIT(16)
ac718b69 565};
566
dff4e8ad 567struct r8152;
568
ebc2ec48 569struct rx_agg {
570 struct list_head list;
571 struct urb *urb;
dff4e8ad 572 struct r8152 *context;
ebc2ec48 573 void *buffer;
574 void *head;
575};
576
577struct tx_agg {
578 struct list_head list;
579 struct urb *urb;
dff4e8ad 580 struct r8152 *context;
ebc2ec48 581 void *buffer;
582 void *head;
583 u32 skb_num;
584 u32 skb_len;
585};
586
ac718b69 587struct r8152 {
588 unsigned long flags;
589 struct usb_device *udev;
d823ab68 590 struct napi_struct napi;
40a82917 591 struct usb_interface *intf;
ac718b69 592 struct net_device *netdev;
40a82917 593 struct urb *intr_urb;
ebc2ec48 594 struct tx_agg tx_info[RTL8152_MAX_TX];
595 struct rx_agg rx_info[RTL8152_MAX_RX];
596 struct list_head rx_done, tx_free;
d823ab68 597 struct sk_buff_head tx_queue, rx_queue;
ebc2ec48 598 spinlock_t rx_lock, tx_lock;
ac718b69 599 struct delayed_work schedule;
600 struct mii_if_info mii;
b5403273 601 struct mutex control; /* use for hw setting */
c81229c9 602
603 struct rtl_ops {
604 void (*init)(struct r8152 *);
605 int (*enable)(struct r8152 *);
606 void (*disable)(struct r8152 *);
7e9da481 607 void (*up)(struct r8152 *);
c81229c9 608 void (*down)(struct r8152 *);
609 void (*unload)(struct r8152 *);
df35d283 610 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
611 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
c81229c9 612 } rtl_ops;
613
40a82917 614 int intr_interval;
21ff2e89 615 u32 saved_wolopts;
ac718b69 616 u32 msg_enable;
dd1b119c 617 u32 tx_qlen;
464ec10a 618 u32 coalesce;
ac718b69 619 u16 ocp_base;
40a82917 620 u8 *intr_buff;
ac718b69 621 u8 version;
ac718b69 622};
623
624enum rtl_version {
625 RTL_VER_UNKNOWN = 0,
626 RTL_VER_01,
43779f8d 627 RTL_VER_02,
628 RTL_VER_03,
629 RTL_VER_04,
630 RTL_VER_05,
fb02eb4a 631 RTL_VER_06,
43779f8d 632 RTL_VER_MAX
ac718b69 633};
634
60c89071 635enum tx_csum_stat {
636 TX_CSUM_SUCCESS = 0,
637 TX_CSUM_TSO,
638 TX_CSUM_NONE
639};
640
ac718b69 641/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
642 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
643 */
644static const int multicast_filter_limit = 32;
52aec126 645static unsigned int agg_buf_sz = 16384;
ac718b69 646
52aec126 647#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 648 VLAN_ETH_HLEN - VLAN_HLEN)
649
ac718b69 650static
651int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
652{
31787f53 653 int ret;
654 void *tmp;
655
656 tmp = kmalloc(size, GFP_KERNEL);
657 if (!tmp)
658 return -ENOMEM;
659
660 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 661 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
662 value, index, tmp, size, 500);
31787f53 663
664 memcpy(data, tmp, size);
665 kfree(tmp);
666
667 return ret;
ac718b69 668}
669
670static
671int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
672{
31787f53 673 int ret;
674 void *tmp;
675
c4438f03 676 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 677 if (!tmp)
678 return -ENOMEM;
679
31787f53 680 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 681 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
682 value, index, tmp, size, 500);
31787f53 683
684 kfree(tmp);
db8515ef 685
31787f53 686 return ret;
ac718b69 687}
688
689static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 690 void *data, u16 type)
ac718b69 691{
45f4a19f 692 u16 limit = 64;
693 int ret = 0;
ac718b69 694
695 if (test_bit(RTL8152_UNPLUG, &tp->flags))
696 return -ENODEV;
697
698 /* both size and indix must be 4 bytes align */
699 if ((size & 3) || !size || (index & 3) || !data)
700 return -EPERM;
701
702 if ((u32)index + (u32)size > 0xffff)
703 return -EPERM;
704
705 while (size) {
706 if (size > limit) {
707 ret = get_registers(tp, index, type, limit, data);
708 if (ret < 0)
709 break;
710
711 index += limit;
712 data += limit;
713 size -= limit;
714 } else {
715 ret = get_registers(tp, index, type, size, data);
716 if (ret < 0)
717 break;
718
719 index += size;
720 data += size;
721 size = 0;
722 break;
723 }
724 }
725
67610496 726 if (ret == -ENODEV)
727 set_bit(RTL8152_UNPLUG, &tp->flags);
728
ac718b69 729 return ret;
730}
731
732static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 733 u16 size, void *data, u16 type)
ac718b69 734{
45f4a19f 735 int ret;
736 u16 byteen_start, byteen_end, byen;
737 u16 limit = 512;
ac718b69 738
739 if (test_bit(RTL8152_UNPLUG, &tp->flags))
740 return -ENODEV;
741
742 /* both size and indix must be 4 bytes align */
743 if ((size & 3) || !size || (index & 3) || !data)
744 return -EPERM;
745
746 if ((u32)index + (u32)size > 0xffff)
747 return -EPERM;
748
749 byteen_start = byteen & BYTE_EN_START_MASK;
750 byteen_end = byteen & BYTE_EN_END_MASK;
751
752 byen = byteen_start | (byteen_start << 4);
753 ret = set_registers(tp, index, type | byen, 4, data);
754 if (ret < 0)
755 goto error1;
756
757 index += 4;
758 data += 4;
759 size -= 4;
760
761 if (size) {
762 size -= 4;
763
764 while (size) {
765 if (size > limit) {
766 ret = set_registers(tp, index,
b209af99 767 type | BYTE_EN_DWORD,
768 limit, data);
ac718b69 769 if (ret < 0)
770 goto error1;
771
772 index += limit;
773 data += limit;
774 size -= limit;
775 } else {
776 ret = set_registers(tp, index,
b209af99 777 type | BYTE_EN_DWORD,
778 size, data);
ac718b69 779 if (ret < 0)
780 goto error1;
781
782 index += size;
783 data += size;
784 size = 0;
785 break;
786 }
787 }
788
789 byen = byteen_end | (byteen_end >> 4);
790 ret = set_registers(tp, index, type | byen, 4, data);
791 if (ret < 0)
792 goto error1;
793 }
794
795error1:
67610496 796 if (ret == -ENODEV)
797 set_bit(RTL8152_UNPLUG, &tp->flags);
798
ac718b69 799 return ret;
800}
801
802static inline
803int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
804{
805 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
806}
807
808static inline
809int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
810{
811 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
812}
813
814static inline
815int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
816{
817 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
818}
819
820static inline
821int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
822{
823 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
824}
825
826static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
827{
c8826de8 828 __le32 data;
ac718b69 829
c8826de8 830 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 831
832 return __le32_to_cpu(data);
833}
834
835static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
836{
c8826de8 837 __le32 tmp = __cpu_to_le32(data);
838
839 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 840}
841
842static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
843{
844 u32 data;
c8826de8 845 __le32 tmp;
ac718b69 846 u8 shift = index & 2;
847
848 index &= ~3;
849
c8826de8 850 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 851
c8826de8 852 data = __le32_to_cpu(tmp);
ac718b69 853 data >>= (shift * 8);
854 data &= 0xffff;
855
856 return (u16)data;
857}
858
859static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
860{
c8826de8 861 u32 mask = 0xffff;
862 __le32 tmp;
ac718b69 863 u16 byen = BYTE_EN_WORD;
864 u8 shift = index & 2;
865
866 data &= mask;
867
868 if (index & 2) {
869 byen <<= shift;
870 mask <<= (shift * 8);
871 data <<= (shift * 8);
872 index &= ~3;
873 }
874
c8826de8 875 tmp = __cpu_to_le32(data);
ac718b69 876
c8826de8 877 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 878}
879
880static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
881{
882 u32 data;
c8826de8 883 __le32 tmp;
ac718b69 884 u8 shift = index & 3;
885
886 index &= ~3;
887
c8826de8 888 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 889
c8826de8 890 data = __le32_to_cpu(tmp);
ac718b69 891 data >>= (shift * 8);
892 data &= 0xff;
893
894 return (u8)data;
895}
896
897static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
898{
c8826de8 899 u32 mask = 0xff;
900 __le32 tmp;
ac718b69 901 u16 byen = BYTE_EN_BYTE;
902 u8 shift = index & 3;
903
904 data &= mask;
905
906 if (index & 3) {
907 byen <<= shift;
908 mask <<= (shift * 8);
909 data <<= (shift * 8);
910 index &= ~3;
911 }
912
c8826de8 913 tmp = __cpu_to_le32(data);
ac718b69 914
c8826de8 915 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 916}
917
ac244d3e 918static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 919{
920 u16 ocp_base, ocp_index;
921
922 ocp_base = addr & 0xf000;
923 if (ocp_base != tp->ocp_base) {
924 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
925 tp->ocp_base = ocp_base;
926 }
927
928 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 929 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 930}
931
ac244d3e 932static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 933{
ac244d3e 934 u16 ocp_base, ocp_index;
ac718b69 935
ac244d3e 936 ocp_base = addr & 0xf000;
937 if (ocp_base != tp->ocp_base) {
938 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
939 tp->ocp_base = ocp_base;
ac718b69 940 }
ac244d3e 941
942 ocp_index = (addr & 0x0fff) | 0xb000;
943 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 944}
945
ac244d3e 946static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 947{
ac244d3e 948 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
949}
ac718b69 950
ac244d3e 951static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
952{
953 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 954}
955
43779f8d 956static void sram_write(struct r8152 *tp, u16 addr, u16 data)
957{
958 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
959 ocp_reg_write(tp, OCP_SRAM_DATA, data);
960}
961
ac718b69 962static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
963{
964 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 965 int ret;
ac718b69 966
6871438c 967 if (test_bit(RTL8152_UNPLUG, &tp->flags))
968 return -ENODEV;
969
ac718b69 970 if (phy_id != R8152_PHY_ID)
971 return -EINVAL;
972
9a4be1bd 973 ret = r8152_mdio_read(tp, reg);
974
9a4be1bd 975 return ret;
ac718b69 976}
977
978static
979void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
980{
981 struct r8152 *tp = netdev_priv(netdev);
982
6871438c 983 if (test_bit(RTL8152_UNPLUG, &tp->flags))
984 return;
985
ac718b69 986 if (phy_id != R8152_PHY_ID)
987 return;
988
989 r8152_mdio_write(tp, reg, val);
990}
991
b209af99 992static int
993r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 994
8ba789ab 995static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
996{
997 struct r8152 *tp = netdev_priv(netdev);
998 struct sockaddr *addr = p;
ea6a7112 999 int ret = -EADDRNOTAVAIL;
8ba789ab 1000
1001 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 1002 goto out1;
1003
1004 ret = usb_autopm_get_interface(tp->intf);
1005 if (ret < 0)
1006 goto out1;
8ba789ab 1007
b5403273 1008 mutex_lock(&tp->control);
1009
8ba789ab 1010 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1011
1012 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1013 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1014 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1015
b5403273 1016 mutex_unlock(&tp->control);
1017
ea6a7112 1018 usb_autopm_put_interface(tp->intf);
1019out1:
1020 return ret;
8ba789ab 1021}
1022
179bb6d7 1023static int set_ethernet_addr(struct r8152 *tp)
ac718b69 1024{
1025 struct net_device *dev = tp->netdev;
179bb6d7 1026 struct sockaddr sa;
8a91c824 1027 int ret;
ac718b69 1028
8a91c824 1029 if (tp->version == RTL_VER_01)
179bb6d7 1030 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
8a91c824 1031 else
179bb6d7 1032 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
8a91c824 1033
1034 if (ret < 0) {
179bb6d7 1035 netif_err(tp, probe, dev, "Get ether addr fail\n");
1036 } else if (!is_valid_ether_addr(sa.sa_data)) {
1037 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1038 sa.sa_data);
1039 eth_hw_addr_random(dev);
1040 ether_addr_copy(sa.sa_data, dev->dev_addr);
1041 ret = rtl8152_set_mac_address(dev, &sa);
1042 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1043 sa.sa_data);
8a91c824 1044 } else {
179bb6d7 1045 if (tp->version == RTL_VER_01)
1046 ether_addr_copy(dev->dev_addr, sa.sa_data);
1047 else
1048 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1049 }
179bb6d7 1050
1051 return ret;
ac718b69 1052}
1053
ac718b69 1054static void read_bulk_callback(struct urb *urb)
1055{
ac718b69 1056 struct net_device *netdev;
ac718b69 1057 int status = urb->status;
ebc2ec48 1058 struct rx_agg *agg;
1059 struct r8152 *tp;
ac718b69 1060
ebc2ec48 1061 agg = urb->context;
1062 if (!agg)
1063 return;
1064
1065 tp = agg->context;
ac718b69 1066 if (!tp)
1067 return;
ebc2ec48 1068
ac718b69 1069 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1070 return;
ebc2ec48 1071
1072 if (!test_bit(WORK_ENABLE, &tp->flags))
1073 return;
1074
ac718b69 1075 netdev = tp->netdev;
7559fb2f 1076
1077 /* When link down, the driver would cancel all bulks. */
1078 /* This avoid the re-submitting bulk */
ebc2ec48 1079 if (!netif_carrier_ok(netdev))
ac718b69 1080 return;
1081
9a4be1bd 1082 usb_mark_last_busy(tp->udev);
1083
ac718b69 1084 switch (status) {
1085 case 0:
ebc2ec48 1086 if (urb->actual_length < ETH_ZLEN)
1087 break;
1088
2685d410 1089 spin_lock(&tp->rx_lock);
ebc2ec48 1090 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1091 spin_unlock(&tp->rx_lock);
d823ab68 1092 napi_schedule(&tp->napi);
ebc2ec48 1093 return;
ac718b69 1094 case -ESHUTDOWN:
1095 set_bit(RTL8152_UNPLUG, &tp->flags);
1096 netif_device_detach(tp->netdev);
ebc2ec48 1097 return;
ac718b69 1098 case -ENOENT:
1099 return; /* the urb is in unlink state */
1100 case -ETIME:
4a8deae2
HW
1101 if (net_ratelimit())
1102 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1103 break;
ac718b69 1104 default:
4a8deae2
HW
1105 if (net_ratelimit())
1106 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1107 break;
ac718b69 1108 }
1109
a0fccd48 1110 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1111}
1112
ebc2ec48 1113static void write_bulk_callback(struct urb *urb)
ac718b69 1114{
ebc2ec48 1115 struct net_device_stats *stats;
d104eafa 1116 struct net_device *netdev;
ebc2ec48 1117 struct tx_agg *agg;
ac718b69 1118 struct r8152 *tp;
ebc2ec48 1119 int status = urb->status;
ac718b69 1120
ebc2ec48 1121 agg = urb->context;
1122 if (!agg)
ac718b69 1123 return;
1124
ebc2ec48 1125 tp = agg->context;
1126 if (!tp)
1127 return;
1128
d104eafa 1129 netdev = tp->netdev;
05e0f1aa 1130 stats = &netdev->stats;
ebc2ec48 1131 if (status) {
4a8deae2 1132 if (net_ratelimit())
d104eafa 1133 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1134 stats->tx_errors += agg->skb_num;
ac718b69 1135 } else {
ebc2ec48 1136 stats->tx_packets += agg->skb_num;
1137 stats->tx_bytes += agg->skb_len;
ac718b69 1138 }
1139
2685d410 1140 spin_lock(&tp->tx_lock);
ebc2ec48 1141 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1142 spin_unlock(&tp->tx_lock);
ebc2ec48 1143
9a4be1bd 1144 usb_autopm_put_interface_async(tp->intf);
1145
d104eafa 1146 if (!netif_carrier_ok(netdev))
ebc2ec48 1147 return;
1148
1149 if (!test_bit(WORK_ENABLE, &tp->flags))
1150 return;
1151
1152 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1153 return;
1154
1155 if (!skb_queue_empty(&tp->tx_queue))
d823ab68 1156 napi_schedule(&tp->napi);
ac718b69 1157}
1158
40a82917 1159static void intr_callback(struct urb *urb)
1160{
1161 struct r8152 *tp;
500b6d7e 1162 __le16 *d;
40a82917 1163 int status = urb->status;
1164 int res;
1165
1166 tp = urb->context;
1167 if (!tp)
1168 return;
1169
1170 if (!test_bit(WORK_ENABLE, &tp->flags))
1171 return;
1172
1173 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1174 return;
1175
1176 switch (status) {
1177 case 0: /* success */
1178 break;
1179 case -ECONNRESET: /* unlink */
1180 case -ESHUTDOWN:
1181 netif_device_detach(tp->netdev);
1182 case -ENOENT:
d59c876d 1183 case -EPROTO:
1184 netif_info(tp, intr, tp->netdev,
1185 "Stop submitting intr, status %d\n", status);
40a82917 1186 return;
1187 case -EOVERFLOW:
1188 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1189 goto resubmit;
1190 /* -EPIPE: should clear the halt */
1191 default:
1192 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1193 goto resubmit;
1194 }
1195
1196 d = urb->transfer_buffer;
1197 if (INTR_LINK & __le16_to_cpu(d[0])) {
51d979fa 1198 if (!netif_carrier_ok(tp->netdev)) {
40a82917 1199 set_bit(RTL8152_LINK_CHG, &tp->flags);
1200 schedule_delayed_work(&tp->schedule, 0);
1201 }
1202 } else {
51d979fa 1203 if (netif_carrier_ok(tp->netdev)) {
40a82917 1204 set_bit(RTL8152_LINK_CHG, &tp->flags);
1205 schedule_delayed_work(&tp->schedule, 0);
1206 }
1207 }
1208
1209resubmit:
1210 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1211 if (res == -ENODEV) {
1212 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1213 netif_device_detach(tp->netdev);
67610496 1214 } else if (res) {
40a82917 1215 netif_err(tp, intr, tp->netdev,
4a8deae2 1216 "can't resubmit intr, status %d\n", res);
67610496 1217 }
40a82917 1218}
1219
ebc2ec48 1220static inline void *rx_agg_align(void *data)
1221{
8e1f51bd 1222 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1223}
1224
1225static inline void *tx_agg_align(void *data)
1226{
8e1f51bd 1227 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1228}
1229
1230static void free_all_mem(struct r8152 *tp)
1231{
1232 int i;
1233
1234 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1235 usb_free_urb(tp->rx_info[i].urb);
1236 tp->rx_info[i].urb = NULL;
ebc2ec48 1237
9629e3c0 1238 kfree(tp->rx_info[i].buffer);
1239 tp->rx_info[i].buffer = NULL;
1240 tp->rx_info[i].head = NULL;
ebc2ec48 1241 }
1242
1243 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1244 usb_free_urb(tp->tx_info[i].urb);
1245 tp->tx_info[i].urb = NULL;
ebc2ec48 1246
9629e3c0 1247 kfree(tp->tx_info[i].buffer);
1248 tp->tx_info[i].buffer = NULL;
1249 tp->tx_info[i].head = NULL;
ebc2ec48 1250 }
40a82917 1251
9629e3c0 1252 usb_free_urb(tp->intr_urb);
1253 tp->intr_urb = NULL;
40a82917 1254
9629e3c0 1255 kfree(tp->intr_buff);
1256 tp->intr_buff = NULL;
ebc2ec48 1257}
1258
1259static int alloc_all_mem(struct r8152 *tp)
1260{
1261 struct net_device *netdev = tp->netdev;
40a82917 1262 struct usb_interface *intf = tp->intf;
1263 struct usb_host_interface *alt = intf->cur_altsetting;
1264 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1265 struct urb *urb;
1266 int node, i;
1267 u8 *buf;
1268
1269 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1270
1271 spin_lock_init(&tp->rx_lock);
1272 spin_lock_init(&tp->tx_lock);
ebc2ec48 1273 INIT_LIST_HEAD(&tp->tx_free);
1274 skb_queue_head_init(&tp->tx_queue);
d823ab68 1275 skb_queue_head_init(&tp->rx_queue);
ebc2ec48 1276
1277 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1278 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1279 if (!buf)
1280 goto err1;
1281
1282 if (buf != rx_agg_align(buf)) {
1283 kfree(buf);
52aec126 1284 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1285 node);
ebc2ec48 1286 if (!buf)
1287 goto err1;
1288 }
1289
1290 urb = usb_alloc_urb(0, GFP_KERNEL);
1291 if (!urb) {
1292 kfree(buf);
1293 goto err1;
1294 }
1295
1296 INIT_LIST_HEAD(&tp->rx_info[i].list);
1297 tp->rx_info[i].context = tp;
1298 tp->rx_info[i].urb = urb;
1299 tp->rx_info[i].buffer = buf;
1300 tp->rx_info[i].head = rx_agg_align(buf);
1301 }
1302
1303 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1304 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1305 if (!buf)
1306 goto err1;
1307
1308 if (buf != tx_agg_align(buf)) {
1309 kfree(buf);
52aec126 1310 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1311 node);
ebc2ec48 1312 if (!buf)
1313 goto err1;
1314 }
1315
1316 urb = usb_alloc_urb(0, GFP_KERNEL);
1317 if (!urb) {
1318 kfree(buf);
1319 goto err1;
1320 }
1321
1322 INIT_LIST_HEAD(&tp->tx_info[i].list);
1323 tp->tx_info[i].context = tp;
1324 tp->tx_info[i].urb = urb;
1325 tp->tx_info[i].buffer = buf;
1326 tp->tx_info[i].head = tx_agg_align(buf);
1327
1328 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1329 }
1330
40a82917 1331 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1332 if (!tp->intr_urb)
1333 goto err1;
1334
1335 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1336 if (!tp->intr_buff)
1337 goto err1;
1338
1339 tp->intr_interval = (int)ep_intr->desc.bInterval;
1340 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1341 tp->intr_buff, INTBUFSIZE, intr_callback,
1342 tp, tp->intr_interval);
40a82917 1343
ebc2ec48 1344 return 0;
1345
1346err1:
1347 free_all_mem(tp);
1348 return -ENOMEM;
1349}
1350
0de98f6c 1351static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1352{
1353 struct tx_agg *agg = NULL;
1354 unsigned long flags;
1355
21949ab7 1356 if (list_empty(&tp->tx_free))
1357 return NULL;
1358
0de98f6c 1359 spin_lock_irqsave(&tp->tx_lock, flags);
1360 if (!list_empty(&tp->tx_free)) {
1361 struct list_head *cursor;
1362
1363 cursor = tp->tx_free.next;
1364 list_del_init(cursor);
1365 agg = list_entry(cursor, struct tx_agg, list);
1366 }
1367 spin_unlock_irqrestore(&tp->tx_lock, flags);
1368
1369 return agg;
1370}
1371
b209af99 1372/* r8152_csum_workaround()
6128d1bb 1373 * The hw limites the value the transport offset. When the offset is out of the
1374 * range, calculate the checksum by sw.
1375 */
1376static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1377 struct sk_buff_head *list)
1378{
1379 if (skb_shinfo(skb)->gso_size) {
1380 netdev_features_t features = tp->netdev->features;
1381 struct sk_buff_head seg_list;
1382 struct sk_buff *segs, *nskb;
1383
a91d45f1 1384 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1385 segs = skb_gso_segment(skb, features);
1386 if (IS_ERR(segs) || !segs)
1387 goto drop;
1388
1389 __skb_queue_head_init(&seg_list);
1390
1391 do {
1392 nskb = segs;
1393 segs = segs->next;
1394 nskb->next = NULL;
1395 __skb_queue_tail(&seg_list, nskb);
1396 } while (segs);
1397
1398 skb_queue_splice(&seg_list, list);
1399 dev_kfree_skb(skb);
1400 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1401 if (skb_checksum_help(skb) < 0)
1402 goto drop;
1403
1404 __skb_queue_head(list, skb);
1405 } else {
1406 struct net_device_stats *stats;
1407
1408drop:
1409 stats = &tp->netdev->stats;
1410 stats->tx_dropped++;
1411 dev_kfree_skb(skb);
1412 }
1413}
1414
b209af99 1415/* msdn_giant_send_check()
6128d1bb 1416 * According to the document of microsoft, the TCP Pseudo Header excludes the
1417 * packet length for IPv6 TCP large packets.
1418 */
1419static int msdn_giant_send_check(struct sk_buff *skb)
1420{
1421 const struct ipv6hdr *ipv6h;
1422 struct tcphdr *th;
fcb308d5 1423 int ret;
1424
1425 ret = skb_cow_head(skb, 0);
1426 if (ret)
1427 return ret;
6128d1bb 1428
1429 ipv6h = ipv6_hdr(skb);
1430 th = tcp_hdr(skb);
1431
1432 th->check = 0;
1433 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1434
fcb308d5 1435 return ret;
6128d1bb 1436}
1437
c5554298 1438static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1439{
df8a39de 1440 if (skb_vlan_tag_present(skb)) {
c5554298 1441 u32 opts2;
1442
df8a39de 1443 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
c5554298 1444 desc->opts2 |= cpu_to_le32(opts2);
1445 }
1446}
1447
1448static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1449{
1450 u32 opts2 = le32_to_cpu(desc->opts2);
1451
1452 if (opts2 & RX_VLAN_TAG)
1453 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1454 swab16(opts2 & 0xffff));
1455}
1456
60c89071 1457static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1458 struct sk_buff *skb, u32 len, u32 transport_offset)
1459{
1460 u32 mss = skb_shinfo(skb)->gso_size;
1461 u32 opts1, opts2 = 0;
1462 int ret = TX_CSUM_SUCCESS;
1463
1464 WARN_ON_ONCE(len > TX_LEN_MAX);
1465
1466 opts1 = len | TX_FS | TX_LS;
1467
1468 if (mss) {
6128d1bb 1469 if (transport_offset > GTTCPHO_MAX) {
1470 netif_warn(tp, tx_err, tp->netdev,
1471 "Invalid transport offset 0x%x for TSO\n",
1472 transport_offset);
1473 ret = TX_CSUM_TSO;
1474 goto unavailable;
1475 }
1476
6e74d174 1477 switch (vlan_get_protocol(skb)) {
60c89071 1478 case htons(ETH_P_IP):
1479 opts1 |= GTSENDV4;
1480 break;
1481
6128d1bb 1482 case htons(ETH_P_IPV6):
fcb308d5 1483 if (msdn_giant_send_check(skb)) {
1484 ret = TX_CSUM_TSO;
1485 goto unavailable;
1486 }
6128d1bb 1487 opts1 |= GTSENDV6;
6128d1bb 1488 break;
1489
60c89071 1490 default:
1491 WARN_ON_ONCE(1);
1492 break;
1493 }
1494
1495 opts1 |= transport_offset << GTTCPHO_SHIFT;
1496 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1497 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1498 u8 ip_protocol;
5bd23881 1499
6128d1bb 1500 if (transport_offset > TCPHO_MAX) {
1501 netif_warn(tp, tx_err, tp->netdev,
1502 "Invalid transport offset 0x%x\n",
1503 transport_offset);
1504 ret = TX_CSUM_NONE;
1505 goto unavailable;
1506 }
1507
6e74d174 1508 switch (vlan_get_protocol(skb)) {
5bd23881 1509 case htons(ETH_P_IP):
1510 opts2 |= IPV4_CS;
1511 ip_protocol = ip_hdr(skb)->protocol;
1512 break;
1513
1514 case htons(ETH_P_IPV6):
1515 opts2 |= IPV6_CS;
1516 ip_protocol = ipv6_hdr(skb)->nexthdr;
1517 break;
1518
1519 default:
1520 ip_protocol = IPPROTO_RAW;
1521 break;
1522 }
1523
60c89071 1524 if (ip_protocol == IPPROTO_TCP)
5bd23881 1525 opts2 |= TCP_CS;
60c89071 1526 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1527 opts2 |= UDP_CS;
60c89071 1528 else
5bd23881 1529 WARN_ON_ONCE(1);
5bd23881 1530
60c89071 1531 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1532 }
60c89071 1533
1534 desc->opts2 = cpu_to_le32(opts2);
1535 desc->opts1 = cpu_to_le32(opts1);
1536
6128d1bb 1537unavailable:
60c89071 1538 return ret;
5bd23881 1539}
1540
b1379d9a 1541static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1542{
d84130a1 1543 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1544 int remain, ret;
b1379d9a 1545 u8 *tx_data;
1546
d84130a1 1547 __skb_queue_head_init(&skb_head);
0c3121fc 1548 spin_lock(&tx_queue->lock);
d84130a1 1549 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1550 spin_unlock(&tx_queue->lock);
d84130a1 1551
b1379d9a 1552 tx_data = agg->head;
b209af99 1553 agg->skb_num = 0;
1554 agg->skb_len = 0;
52aec126 1555 remain = agg_buf_sz;
b1379d9a 1556
7937f9e5 1557 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1558 struct tx_desc *tx_desc;
1559 struct sk_buff *skb;
1560 unsigned int len;
60c89071 1561 u32 offset;
b1379d9a 1562
d84130a1 1563 skb = __skb_dequeue(&skb_head);
b1379d9a 1564 if (!skb)
1565 break;
1566
60c89071 1567 len = skb->len + sizeof(*tx_desc);
1568
1569 if (len > remain) {
d84130a1 1570 __skb_queue_head(&skb_head, skb);
b1379d9a 1571 break;
1572 }
1573
7937f9e5 1574 tx_data = tx_agg_align(tx_data);
b1379d9a 1575 tx_desc = (struct tx_desc *)tx_data;
60c89071 1576
1577 offset = (u32)skb_transport_offset(skb);
1578
6128d1bb 1579 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1580 r8152_csum_workaround(tp, skb, &skb_head);
1581 continue;
1582 }
60c89071 1583
c5554298 1584 rtl_tx_vlan_tag(tx_desc, skb);
1585
b1379d9a 1586 tx_data += sizeof(*tx_desc);
1587
60c89071 1588 len = skb->len;
1589 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1590 struct net_device_stats *stats = &tp->netdev->stats;
1591
1592 stats->tx_dropped++;
1593 dev_kfree_skb_any(skb);
1594 tx_data -= sizeof(*tx_desc);
1595 continue;
1596 }
1597
1598 tx_data += len;
b1379d9a 1599 agg->skb_len += len;
60c89071 1600 agg->skb_num++;
1601
b1379d9a 1602 dev_kfree_skb_any(skb);
1603
52aec126 1604 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1605 }
1606
d84130a1 1607 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1608 spin_lock(&tx_queue->lock);
d84130a1 1609 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1610 spin_unlock(&tx_queue->lock);
d84130a1 1611 }
1612
0c3121fc 1613 netif_tx_lock(tp->netdev);
dd1b119c 1614
1615 if (netif_queue_stopped(tp->netdev) &&
1616 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1617 netif_wake_queue(tp->netdev);
1618
0c3121fc 1619 netif_tx_unlock(tp->netdev);
9a4be1bd 1620
0c3121fc 1621 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1622 if (ret < 0)
1623 goto out_tx_fill;
dd1b119c 1624
b1379d9a 1625 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1626 agg->head, (int)(tx_data - (u8 *)agg->head),
1627 (usb_complete_t)write_bulk_callback, agg);
1628
0c3121fc 1629 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1630 if (ret < 0)
0c3121fc 1631 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1632
1633out_tx_fill:
1634 return ret;
b1379d9a 1635}
1636
565cab0a 1637static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1638{
1639 u8 checksum = CHECKSUM_NONE;
1640 u32 opts2, opts3;
1641
1642 if (tp->version == RTL_VER_01)
1643 goto return_result;
1644
1645 opts2 = le32_to_cpu(rx_desc->opts2);
1646 opts3 = le32_to_cpu(rx_desc->opts3);
1647
1648 if (opts2 & RD_IPV4_CS) {
1649 if (opts3 & IPF)
1650 checksum = CHECKSUM_NONE;
1651 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1652 checksum = CHECKSUM_NONE;
1653 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1654 checksum = CHECKSUM_NONE;
1655 else
1656 checksum = CHECKSUM_UNNECESSARY;
6128d1bb 1657 } else if (RD_IPV6_CS) {
1658 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1659 checksum = CHECKSUM_UNNECESSARY;
1660 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1661 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1662 }
1663
1664return_result:
1665 return checksum;
1666}
1667
d823ab68 1668static int rx_bottom(struct r8152 *tp, int budget)
ebc2ec48 1669{
a5a4f468 1670 unsigned long flags;
d84130a1 1671 struct list_head *cursor, *next, rx_queue;
e1a2ca92 1672 int ret = 0, work_done = 0;
d823ab68 1673
1674 if (!skb_queue_empty(&tp->rx_queue)) {
1675 while (work_done < budget) {
1676 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1677 struct net_device *netdev = tp->netdev;
1678 struct net_device_stats *stats = &netdev->stats;
1679 unsigned int pkt_len;
1680
1681 if (!skb)
1682 break;
1683
1684 pkt_len = skb->len;
1685 napi_gro_receive(&tp->napi, skb);
1686 work_done++;
1687 stats->rx_packets++;
1688 stats->rx_bytes += pkt_len;
1689 }
1690 }
ebc2ec48 1691
d84130a1 1692 if (list_empty(&tp->rx_done))
d823ab68 1693 goto out1;
d84130a1 1694
1695 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1696 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1697 list_splice_init(&tp->rx_done, &rx_queue);
1698 spin_unlock_irqrestore(&tp->rx_lock, flags);
1699
1700 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1701 struct rx_desc *rx_desc;
1702 struct rx_agg *agg;
43a4478d 1703 int len_used = 0;
1704 struct urb *urb;
1705 u8 *rx_data;
43a4478d 1706
ebc2ec48 1707 list_del_init(cursor);
ebc2ec48 1708
1709 agg = list_entry(cursor, struct rx_agg, list);
1710 urb = agg->urb;
0de98f6c 1711 if (urb->actual_length < ETH_ZLEN)
1712 goto submit;
ebc2ec48 1713
ebc2ec48 1714 rx_desc = agg->head;
1715 rx_data = agg->head;
7937f9e5 1716 len_used += sizeof(struct rx_desc);
ebc2ec48 1717
7937f9e5 1718 while (urb->actual_length > len_used) {
43a4478d 1719 struct net_device *netdev = tp->netdev;
05e0f1aa 1720 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1721 unsigned int pkt_len;
43a4478d 1722 struct sk_buff *skb;
1723
7937f9e5 1724 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1725 if (pkt_len < ETH_ZLEN)
1726 break;
1727
7937f9e5 1728 len_used += pkt_len;
1729 if (urb->actual_length < len_used)
1730 break;
1731
8e1f51bd 1732 pkt_len -= CRC_SIZE;
ebc2ec48 1733 rx_data += sizeof(struct rx_desc);
1734
1735 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1736 if (!skb) {
1737 stats->rx_dropped++;
5e2f7485 1738 goto find_next_rx;
ebc2ec48 1739 }
565cab0a 1740
1741 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1742 memcpy(skb->data, rx_data, pkt_len);
1743 skb_put(skb, pkt_len);
1744 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1745 rtl_rx_vlan_tag(rx_desc, skb);
d823ab68 1746 if (work_done < budget) {
1747 napi_gro_receive(&tp->napi, skb);
1748 work_done++;
1749 stats->rx_packets++;
1750 stats->rx_bytes += pkt_len;
1751 } else {
1752 __skb_queue_tail(&tp->rx_queue, skb);
1753 }
ebc2ec48 1754
5e2f7485 1755find_next_rx:
8e1f51bd 1756 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1757 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1758 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1759 len_used += sizeof(struct rx_desc);
ebc2ec48 1760 }
1761
0de98f6c 1762submit:
e1a2ca92 1763 if (!ret) {
1764 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1765 } else {
1766 urb->actual_length = 0;
1767 list_add_tail(&agg->list, next);
1768 }
1769 }
1770
1771 if (!list_empty(&rx_queue)) {
1772 spin_lock_irqsave(&tp->rx_lock, flags);
1773 list_splice_tail(&rx_queue, &tp->rx_done);
1774 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1775 }
d823ab68 1776
1777out1:
1778 return work_done;
ebc2ec48 1779}
1780
1781static void tx_bottom(struct r8152 *tp)
1782{
ebc2ec48 1783 int res;
1784
b1379d9a 1785 do {
1786 struct tx_agg *agg;
ebc2ec48 1787
b1379d9a 1788 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1789 break;
1790
b1379d9a 1791 agg = r8152_get_tx_agg(tp);
1792 if (!agg)
ebc2ec48 1793 break;
ebc2ec48 1794
b1379d9a 1795 res = r8152_tx_agg_fill(tp, agg);
1796 if (res) {
05e0f1aa 1797 struct net_device *netdev = tp->netdev;
ebc2ec48 1798
b1379d9a 1799 if (res == -ENODEV) {
67610496 1800 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1801 netif_device_detach(netdev);
1802 } else {
05e0f1aa 1803 struct net_device_stats *stats = &netdev->stats;
1804 unsigned long flags;
1805
b1379d9a 1806 netif_warn(tp, tx_err, netdev,
1807 "failed tx_urb %d\n", res);
1808 stats->tx_dropped += agg->skb_num;
db8515ef 1809
b1379d9a 1810 spin_lock_irqsave(&tp->tx_lock, flags);
1811 list_add_tail(&agg->list, &tp->tx_free);
1812 spin_unlock_irqrestore(&tp->tx_lock, flags);
1813 }
ebc2ec48 1814 }
b1379d9a 1815 } while (res == 0);
ebc2ec48 1816}
1817
d823ab68 1818static void bottom_half(struct r8152 *tp)
ac718b69 1819{
ebc2ec48 1820 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1821 return;
1822
1823 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1824 return;
ebc2ec48 1825
7559fb2f 1826 /* When link down, the driver would cancel all bulks. */
1827 /* This avoid the re-submitting bulk */
ebc2ec48 1828 if (!netif_carrier_ok(tp->netdev))
ac718b69 1829 return;
ebc2ec48 1830
d823ab68 1831 clear_bit(SCHEDULE_NAPI, &tp->flags);
9451a11c 1832
0c3121fc 1833 tx_bottom(tp);
ebc2ec48 1834}
1835
d823ab68 1836static int r8152_poll(struct napi_struct *napi, int budget)
1837{
1838 struct r8152 *tp = container_of(napi, struct r8152, napi);
1839 int work_done;
1840
1841 work_done = rx_bottom(tp, budget);
1842 bottom_half(tp);
1843
1844 if (work_done < budget) {
1845 napi_complete(napi);
1846 if (!list_empty(&tp->rx_done))
1847 napi_schedule(napi);
1848 }
1849
1850 return work_done;
1851}
1852
ebc2ec48 1853static
1854int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1855{
a0fccd48 1856 int ret;
1857
ef827a5b 1858 /* The rx would be stopped, so skip submitting */
1859 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1860 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1861 return 0;
1862
ebc2ec48 1863 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1864 agg->head, agg_buf_sz,
b209af99 1865 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1866
a0fccd48 1867 ret = usb_submit_urb(agg->urb, mem_flags);
1868 if (ret == -ENODEV) {
1869 set_bit(RTL8152_UNPLUG, &tp->flags);
1870 netif_device_detach(tp->netdev);
1871 } else if (ret) {
1872 struct urb *urb = agg->urb;
1873 unsigned long flags;
1874
1875 urb->actual_length = 0;
1876 spin_lock_irqsave(&tp->rx_lock, flags);
1877 list_add_tail(&agg->list, &tp->rx_done);
1878 spin_unlock_irqrestore(&tp->rx_lock, flags);
d823ab68 1879
1880 netif_err(tp, rx_err, tp->netdev,
1881 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1882
1883 napi_schedule(&tp->napi);
a0fccd48 1884 }
1885
1886 return ret;
ac718b69 1887}
1888
00a5e360 1889static void rtl_drop_queued_tx(struct r8152 *tp)
1890{
1891 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1892 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1893 struct sk_buff *skb;
1894
d84130a1 1895 if (skb_queue_empty(tx_queue))
1896 return;
1897
1898 __skb_queue_head_init(&skb_head);
2685d410 1899 spin_lock_bh(&tx_queue->lock);
d84130a1 1900 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1901 spin_unlock_bh(&tx_queue->lock);
d84130a1 1902
1903 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1904 dev_kfree_skb(skb);
1905 stats->tx_dropped++;
1906 }
1907}
1908
ac718b69 1909static void rtl8152_tx_timeout(struct net_device *netdev)
1910{
1911 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1912
4a8deae2 1913 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
37608f3e 1914
1915 usb_queue_reset_device(tp->intf);
ac718b69 1916}
1917
1918static void rtl8152_set_rx_mode(struct net_device *netdev)
1919{
1920 struct r8152 *tp = netdev_priv(netdev);
1921
51d979fa 1922 if (netif_carrier_ok(netdev)) {
ac718b69 1923 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1924 schedule_delayed_work(&tp->schedule, 0);
1925 }
ac718b69 1926}
1927
1928static void _rtl8152_set_rx_mode(struct net_device *netdev)
1929{
1930 struct r8152 *tp = netdev_priv(netdev);
31787f53 1931 u32 mc_filter[2]; /* Multicast hash filter */
1932 __le32 tmp[2];
ac718b69 1933 u32 ocp_data;
1934
ac718b69 1935 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1936 netif_stop_queue(netdev);
1937 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1938 ocp_data &= ~RCR_ACPT_ALL;
1939 ocp_data |= RCR_AB | RCR_APM;
1940
1941 if (netdev->flags & IFF_PROMISC) {
1942 /* Unconditionally log net taps. */
1943 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1944 ocp_data |= RCR_AM | RCR_AAP;
b209af99 1945 mc_filter[1] = 0xffffffff;
1946 mc_filter[0] = 0xffffffff;
ac718b69 1947 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1948 (netdev->flags & IFF_ALLMULTI)) {
1949 /* Too many to filter perfectly -- accept all multicasts. */
1950 ocp_data |= RCR_AM;
b209af99 1951 mc_filter[1] = 0xffffffff;
1952 mc_filter[0] = 0xffffffff;
ac718b69 1953 } else {
1954 struct netdev_hw_addr *ha;
1955
b209af99 1956 mc_filter[1] = 0;
1957 mc_filter[0] = 0;
ac718b69 1958 netdev_for_each_mc_addr(ha, netdev) {
1959 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 1960
ac718b69 1961 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1962 ocp_data |= RCR_AM;
1963 }
1964 }
1965
31787f53 1966 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1967 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1968
31787f53 1969 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1970 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1971 netif_wake_queue(netdev);
ac718b69 1972}
1973
a5e31255 1974static netdev_features_t
1975rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1976 netdev_features_t features)
1977{
1978 u32 mss = skb_shinfo(skb)->gso_size;
1979 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1980 int offset = skb_transport_offset(skb);
1981
1982 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1983 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1984 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1985 features &= ~NETIF_F_GSO_MASK;
1986
1987 return features;
1988}
1989
ac718b69 1990static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 1991 struct net_device *netdev)
ac718b69 1992{
1993 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1994
ebc2ec48 1995 skb_tx_timestamp(skb);
ac718b69 1996
61598788 1997 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1998
0c3121fc 1999 if (!list_empty(&tp->tx_free)) {
2000 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
d823ab68 2001 set_bit(SCHEDULE_NAPI, &tp->flags);
0c3121fc 2002 schedule_delayed_work(&tp->schedule, 0);
2003 } else {
2004 usb_mark_last_busy(tp->udev);
d823ab68 2005 napi_schedule(&tp->napi);
0c3121fc 2006 }
b209af99 2007 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 2008 netif_stop_queue(netdev);
b209af99 2009 }
dd1b119c 2010
ac718b69 2011 return NETDEV_TX_OK;
2012}
2013
2014static void r8152b_reset_packet_filter(struct r8152 *tp)
2015{
2016 u32 ocp_data;
2017
2018 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2019 ocp_data &= ~FMC_FCR_MCU_EN;
2020 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2021 ocp_data |= FMC_FCR_MCU_EN;
2022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2023}
2024
2025static void rtl8152_nic_reset(struct r8152 *tp)
2026{
2027 int i;
2028
2029 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2030
2031 for (i = 0; i < 1000; i++) {
2032 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2033 break;
b209af99 2034 usleep_range(100, 400);
ac718b69 2035 }
2036}
2037
dd1b119c 2038static void set_tx_qlen(struct r8152 *tp)
2039{
2040 struct net_device *netdev = tp->netdev;
2041
52aec126 2042 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2043 sizeof(struct tx_desc));
dd1b119c 2044}
2045
ac718b69 2046static inline u8 rtl8152_get_speed(struct r8152 *tp)
2047{
2048 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2049}
2050
507605a8 2051static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 2052{
ebc2ec48 2053 u32 ocp_data;
ac718b69 2054 u8 speed;
2055
2056 speed = rtl8152_get_speed(tp);
ebc2ec48 2057 if (speed & _10bps) {
ac718b69 2058 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2059 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 2060 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2061 } else {
2062 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2063 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 2064 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2065 }
507605a8 2066}
2067
00a5e360 2068static void rxdy_gated_en(struct r8152 *tp, bool enable)
2069{
2070 u32 ocp_data;
2071
2072 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2073 if (enable)
2074 ocp_data |= RXDY_GATED_EN;
2075 else
2076 ocp_data &= ~RXDY_GATED_EN;
2077 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2078}
2079
445f7f4d 2080static int rtl_start_rx(struct r8152 *tp)
2081{
2082 int i, ret = 0;
2083
2084 INIT_LIST_HEAD(&tp->rx_done);
2085 for (i = 0; i < RTL8152_MAX_RX; i++) {
2086 INIT_LIST_HEAD(&tp->rx_info[i].list);
2087 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2088 if (ret)
2089 break;
2090 }
2091
7bcf4f60 2092 if (ret && ++i < RTL8152_MAX_RX) {
2093 struct list_head rx_queue;
2094 unsigned long flags;
2095
2096 INIT_LIST_HEAD(&rx_queue);
2097
2098 do {
2099 struct rx_agg *agg = &tp->rx_info[i++];
2100 struct urb *urb = agg->urb;
2101
2102 urb->actual_length = 0;
2103 list_add_tail(&agg->list, &rx_queue);
2104 } while (i < RTL8152_MAX_RX);
2105
2106 spin_lock_irqsave(&tp->rx_lock, flags);
2107 list_splice_tail(&rx_queue, &tp->rx_done);
2108 spin_unlock_irqrestore(&tp->rx_lock, flags);
2109 }
2110
445f7f4d 2111 return ret;
2112}
2113
2114static int rtl_stop_rx(struct r8152 *tp)
2115{
2116 int i;
2117
2118 for (i = 0; i < RTL8152_MAX_RX; i++)
2119 usb_kill_urb(tp->rx_info[i].urb);
2120
d823ab68 2121 while (!skb_queue_empty(&tp->rx_queue))
2122 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2123
445f7f4d 2124 return 0;
2125}
2126
507605a8 2127static int rtl_enable(struct r8152 *tp)
2128{
2129 u32 ocp_data;
ac718b69 2130
2131 r8152b_reset_packet_filter(tp);
2132
2133 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2134 ocp_data |= CR_RE | CR_TE;
2135 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2136
00a5e360 2137 rxdy_gated_en(tp, false);
ac718b69 2138
aa2e0926 2139 return 0;
ac718b69 2140}
2141
507605a8 2142static int rtl8152_enable(struct r8152 *tp)
2143{
6871438c 2144 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2145 return -ENODEV;
2146
507605a8 2147 set_tx_qlen(tp);
2148 rtl_set_eee_plus(tp);
2149
2150 return rtl_enable(tp);
2151}
2152
464ec10a 2153static void r8153_set_rx_early_timeout(struct r8152 *tp)
43779f8d 2154{
464ec10a 2155 u32 ocp_data = tp->coalesce / 8;
43779f8d 2156
464ec10a 2157 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2158}
2159
2160static void r8153_set_rx_early_size(struct r8152 *tp)
2161{
2162 u32 mtu = tp->netdev->mtu;
2163 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
2164
2165 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
43779f8d 2166}
2167
2168static int rtl8153_enable(struct r8152 *tp)
2169{
6871438c 2170 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2171 return -ENODEV;
2172
b214396f 2173 usb_disable_lpm(tp->udev);
43779f8d 2174 set_tx_qlen(tp);
2175 rtl_set_eee_plus(tp);
464ec10a 2176 r8153_set_rx_early_timeout(tp);
2177 r8153_set_rx_early_size(tp);
43779f8d 2178
2179 return rtl_enable(tp);
2180}
2181
d70b1137 2182static void rtl_disable(struct r8152 *tp)
ac718b69 2183{
ebc2ec48 2184 u32 ocp_data;
2185 int i;
ac718b69 2186
6871438c 2187 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2188 rtl_drop_queued_tx(tp);
2189 return;
2190 }
2191
ac718b69 2192 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2193 ocp_data &= ~RCR_ACPT_ALL;
2194 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2195
00a5e360 2196 rtl_drop_queued_tx(tp);
ebc2ec48 2197
2198 for (i = 0; i < RTL8152_MAX_TX; i++)
2199 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2200
00a5e360 2201 rxdy_gated_en(tp, true);
ac718b69 2202
2203 for (i = 0; i < 1000; i++) {
2204 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2205 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2206 break;
8ddfa077 2207 usleep_range(1000, 2000);
ac718b69 2208 }
2209
2210 for (i = 0; i < 1000; i++) {
2211 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2212 break;
8ddfa077 2213 usleep_range(1000, 2000);
ac718b69 2214 }
2215
445f7f4d 2216 rtl_stop_rx(tp);
ac718b69 2217
2218 rtl8152_nic_reset(tp);
2219}
2220
00a5e360 2221static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2222{
2223 u32 ocp_data;
2224
2225 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2226 if (enable)
2227 ocp_data |= POWER_CUT;
2228 else
2229 ocp_data &= ~POWER_CUT;
2230 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2231
2232 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2233 ocp_data &= ~RESUME_INDICATE;
2234 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2235}
2236
c5554298 2237static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2238{
2239 u32 ocp_data;
2240
2241 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2242 if (enable)
2243 ocp_data |= CPCR_RX_VLAN;
2244 else
2245 ocp_data &= ~CPCR_RX_VLAN;
2246 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2247}
2248
2249static int rtl8152_set_features(struct net_device *dev,
2250 netdev_features_t features)
2251{
2252 netdev_features_t changed = features ^ dev->features;
2253 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2254 int ret;
2255
2256 ret = usb_autopm_get_interface(tp->intf);
2257 if (ret < 0)
2258 goto out;
c5554298 2259
b5403273 2260 mutex_lock(&tp->control);
2261
c5554298 2262 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2263 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2264 rtl_rx_vlan_en(tp, true);
2265 else
2266 rtl_rx_vlan_en(tp, false);
2267 }
2268
b5403273 2269 mutex_unlock(&tp->control);
2270
405f8a0e 2271 usb_autopm_put_interface(tp->intf);
2272
2273out:
2274 return ret;
c5554298 2275}
2276
21ff2e89 2277#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2278
2279static u32 __rtl_get_wol(struct r8152 *tp)
2280{
2281 u32 ocp_data;
2282 u32 wolopts = 0;
2283
2284 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2285 if (!(ocp_data & LAN_WAKE_EN))
2286 return 0;
2287
2288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2289 if (ocp_data & LINK_ON_WAKE_EN)
2290 wolopts |= WAKE_PHY;
2291
2292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2293 if (ocp_data & UWF_EN)
2294 wolopts |= WAKE_UCAST;
2295 if (ocp_data & BWF_EN)
2296 wolopts |= WAKE_BCAST;
2297 if (ocp_data & MWF_EN)
2298 wolopts |= WAKE_MCAST;
2299
2300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2301 if (ocp_data & MAGIC_EN)
2302 wolopts |= WAKE_MAGIC;
2303
2304 return wolopts;
2305}
2306
2307static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2308{
2309 u32 ocp_data;
2310
2311 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2312
2313 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2314 ocp_data &= ~LINK_ON_WAKE_EN;
2315 if (wolopts & WAKE_PHY)
2316 ocp_data |= LINK_ON_WAKE_EN;
2317 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2318
2319 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2320 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2321 if (wolopts & WAKE_UCAST)
2322 ocp_data |= UWF_EN;
2323 if (wolopts & WAKE_BCAST)
2324 ocp_data |= BWF_EN;
2325 if (wolopts & WAKE_MCAST)
2326 ocp_data |= MWF_EN;
2327 if (wolopts & WAKE_ANY)
2328 ocp_data |= LAN_WAKE_EN;
2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2330
2331 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2332
2333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2334 ocp_data &= ~MAGIC_EN;
2335 if (wolopts & WAKE_MAGIC)
2336 ocp_data |= MAGIC_EN;
2337 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2338
2339 if (wolopts & WAKE_ANY)
2340 device_set_wakeup_enable(&tp->udev->dev, true);
2341 else
2342 device_set_wakeup_enable(&tp->udev->dev, false);
2343}
2344
b214396f 2345static void r8153_u1u2en(struct r8152 *tp, bool enable)
2346{
2347 u8 u1u2[8];
2348
2349 if (enable)
2350 memset(u1u2, 0xff, sizeof(u1u2));
2351 else
2352 memset(u1u2, 0x00, sizeof(u1u2));
2353
2354 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2355}
2356
2357static void r8153_u2p3en(struct r8152 *tp, bool enable)
2358{
2359 u32 ocp_data;
2360
2361 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2362 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
2363 ocp_data |= U2P3_ENABLE;
2364 else
2365 ocp_data &= ~U2P3_ENABLE;
2366 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2367}
2368
2369static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2370{
2371 u32 ocp_data;
2372
2373 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2374 if (enable)
2375 ocp_data |= PWR_EN | PHASE2_EN;
2376 else
2377 ocp_data &= ~(PWR_EN | PHASE2_EN);
2378 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2379
2380 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2381 ocp_data &= ~PCUT_STATUS;
2382 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2383}
2384
7daed8dc 2385static bool rtl_can_wakeup(struct r8152 *tp)
2386{
2387 struct usb_device *udev = tp->udev;
2388
2389 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2390}
2391
9a4be1bd 2392static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2393{
2394 if (enable) {
2395 u32 ocp_data;
2396
b214396f 2397 r8153_u1u2en(tp, false);
2398 r8153_u2p3en(tp, false);
2399
9a4be1bd 2400 __rtl_set_wol(tp, WAKE_ANY);
2401
2402 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2403
2404 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2405 ocp_data |= LINK_OFF_WAKE_EN;
2406 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2407
2408 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2409 } else {
2410 __rtl_set_wol(tp, tp->saved_wolopts);
b214396f 2411 r8153_u2p3en(tp, true);
2412 r8153_u1u2en(tp, true);
9a4be1bd 2413 }
2414}
2415
aa66a5f1 2416static void rtl_phy_reset(struct r8152 *tp)
2417{
2418 u16 data;
2419 int i;
2420
2421 clear_bit(PHY_RESET, &tp->flags);
2422
2423 data = r8152_mdio_read(tp, MII_BMCR);
2424
2425 /* don't reset again before the previous one complete */
2426 if (data & BMCR_RESET)
2427 return;
2428
2429 data |= BMCR_RESET;
2430 r8152_mdio_write(tp, MII_BMCR, data);
2431
2432 for (i = 0; i < 50; i++) {
2433 msleep(20);
2434 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2435 break;
2436 }
2437}
2438
4349968a 2439static void r8153_teredo_off(struct r8152 *tp)
2440{
2441 u32 ocp_data;
2442
2443 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2444 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2445 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2446
2447 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2449 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2450}
2451
2452static void r8152b_disable_aldps(struct r8152 *tp)
2453{
2454 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2455 msleep(20);
2456}
2457
2458static inline void r8152b_enable_aldps(struct r8152 *tp)
2459{
2460 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2461 LINKENA | DIS_SDSAVE);
2462}
2463
d70b1137 2464static void rtl8152_disable(struct r8152 *tp)
2465{
2466 r8152b_disable_aldps(tp);
2467 rtl_disable(tp);
2468 r8152b_enable_aldps(tp);
2469}
2470
4349968a 2471static void r8152b_hw_phy_cfg(struct r8152 *tp)
2472{
f0cbe0ac 2473 u16 data;
2474
2475 data = r8152_mdio_read(tp, MII_BMCR);
2476 if (data & BMCR_PDOWN) {
2477 data &= ~BMCR_PDOWN;
2478 r8152_mdio_write(tp, MII_BMCR, data);
2479 }
2480
aa66a5f1 2481 set_bit(PHY_RESET, &tp->flags);
4349968a 2482}
2483
ac718b69 2484static void r8152b_exit_oob(struct r8152 *tp)
2485{
db8515ef 2486 u32 ocp_data;
2487 int i;
ac718b69 2488
2489 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2490 ocp_data &= ~RCR_ACPT_ALL;
2491 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2492
00a5e360 2493 rxdy_gated_en(tp, true);
da9bd117 2494 r8153_teredo_off(tp);
7e9da481 2495 r8152b_hw_phy_cfg(tp);
ac718b69 2496
2497 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2498 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2499
2500 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2501 ocp_data &= ~NOW_IS_OOB;
2502 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2503
2504 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2505 ocp_data &= ~MCU_BORW_EN;
2506 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2507
2508 for (i = 0; i < 1000; i++) {
2509 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2510 if (ocp_data & LINK_LIST_READY)
2511 break;
8ddfa077 2512 usleep_range(1000, 2000);
ac718b69 2513 }
2514
2515 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2516 ocp_data |= RE_INIT_LL;
2517 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2518
2519 for (i = 0; i < 1000; i++) {
2520 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2521 if (ocp_data & LINK_LIST_READY)
2522 break;
8ddfa077 2523 usleep_range(1000, 2000);
ac718b69 2524 }
2525
2526 rtl8152_nic_reset(tp);
2527
2528 /* rx share fifo credit full threshold */
2529 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2530
a3cc465d 2531 if (tp->udev->speed == USB_SPEED_FULL ||
2532 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2533 /* rx share fifo credit near full threshold */
2534 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2535 RXFIFO_THR2_FULL);
2536 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2537 RXFIFO_THR3_FULL);
2538 } else {
2539 /* rx share fifo credit near full threshold */
2540 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2541 RXFIFO_THR2_HIGH);
2542 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2543 RXFIFO_THR3_HIGH);
2544 }
2545
2546 /* TX share fifo free credit full threshold */
2547 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2548
2549 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2550 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2551 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2552 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2553
c5554298 2554 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2555
2556 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2557
2558 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2559 ocp_data |= TCR0_AUTO_FIFO;
2560 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2561}
2562
2563static void r8152b_enter_oob(struct r8152 *tp)
2564{
45f4a19f 2565 u32 ocp_data;
2566 int i;
ac718b69 2567
2568 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2569 ocp_data &= ~NOW_IS_OOB;
2570 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2571
2572 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2573 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2574 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2575
d70b1137 2576 rtl_disable(tp);
ac718b69 2577
2578 for (i = 0; i < 1000; i++) {
2579 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2580 if (ocp_data & LINK_LIST_READY)
2581 break;
8ddfa077 2582 usleep_range(1000, 2000);
ac718b69 2583 }
2584
2585 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2586 ocp_data |= RE_INIT_LL;
2587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2588
2589 for (i = 0; i < 1000; i++) {
2590 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2591 if (ocp_data & LINK_LIST_READY)
2592 break;
8ddfa077 2593 usleep_range(1000, 2000);
ac718b69 2594 }
2595
2596 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2597
c5554298 2598 rtl_rx_vlan_en(tp, true);
ac718b69 2599
2600 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2601 ocp_data |= ALDPS_PROXY_MODE;
2602 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2603
2604 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2605 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2606 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2607
00a5e360 2608 rxdy_gated_en(tp, false);
ac718b69 2609
2610 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2611 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2612 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2613}
2614
43779f8d 2615static void r8153_hw_phy_cfg(struct r8152 *tp)
2616{
2617 u32 ocp_data;
2618 u16 data;
2619
fb02eb4a 2620 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
2621 tp->version == RTL_VER_05)
2622 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2623
f0cbe0ac 2624 data = r8152_mdio_read(tp, MII_BMCR);
2625 if (data & BMCR_PDOWN) {
2626 data &= ~BMCR_PDOWN;
2627 r8152_mdio_write(tp, MII_BMCR, data);
2628 }
43779f8d 2629
2630 if (tp->version == RTL_VER_03) {
2631 data = ocp_reg_read(tp, OCP_EEE_CFG);
2632 data &= ~CTAP_SHORT_EN;
2633 ocp_reg_write(tp, OCP_EEE_CFG, data);
2634 }
2635
2636 data = ocp_reg_read(tp, OCP_POWER_CFG);
2637 data |= EEE_CLKDIV_EN;
2638 ocp_reg_write(tp, OCP_POWER_CFG, data);
2639
2640 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2641 data |= EN_10M_BGOFF;
2642 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2643 data = ocp_reg_read(tp, OCP_POWER_CFG);
2644 data |= EN_10M_PLLOFF;
2645 ocp_reg_write(tp, OCP_POWER_CFG, data);
b4d99def 2646 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
43779f8d 2647
2648 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2649 ocp_data |= PFM_PWM_SWITCH;
2650 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2651
b4d99def 2652 /* Enable LPF corner auto tune */
2653 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
43779f8d 2654
b4d99def 2655 /* Adjust 10M Amplitude */
2656 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2657 sram_write(tp, SRAM_10M_AMP2, 0x0208);
aa66a5f1 2658
2659 set_bit(PHY_RESET, &tp->flags);
43779f8d 2660}
2661
43779f8d 2662static void r8153_first_init(struct r8152 *tp)
2663{
2664 u32 ocp_data;
2665 int i;
2666
00a5e360 2667 rxdy_gated_en(tp, true);
43779f8d 2668 r8153_teredo_off(tp);
2669
2670 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2671 ocp_data &= ~RCR_ACPT_ALL;
2672 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2673
2674 r8153_hw_phy_cfg(tp);
2675
2676 rtl8152_nic_reset(tp);
2677
2678 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2679 ocp_data &= ~NOW_IS_OOB;
2680 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2681
2682 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2683 ocp_data &= ~MCU_BORW_EN;
2684 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2685
2686 for (i = 0; i < 1000; i++) {
2687 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2688 if (ocp_data & LINK_LIST_READY)
2689 break;
8ddfa077 2690 usleep_range(1000, 2000);
43779f8d 2691 }
2692
2693 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2694 ocp_data |= RE_INIT_LL;
2695 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2696
2697 for (i = 0; i < 1000; i++) {
2698 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2699 if (ocp_data & LINK_LIST_READY)
2700 break;
8ddfa077 2701 usleep_range(1000, 2000);
43779f8d 2702 }
2703
c5554298 2704 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2705
69b4b7a4 2706 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2707 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2708
2709 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2710 ocp_data |= TCR0_AUTO_FIFO;
2711 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2712
2713 rtl8152_nic_reset(tp);
2714
2715 /* rx share fifo credit full threshold */
2716 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2717 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2718 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2719 /* TX share fifo free credit full threshold */
2720 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2721
9629e3c0 2722 /* rx aggregation */
43779f8d 2723 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 2724 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
43779f8d 2725 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2726}
2727
2728static void r8153_enter_oob(struct r8152 *tp)
2729{
2730 u32 ocp_data;
2731 int i;
2732
2733 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2734 ocp_data &= ~NOW_IS_OOB;
2735 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2736
d70b1137 2737 rtl_disable(tp);
43779f8d 2738
2739 for (i = 0; i < 1000; i++) {
2740 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2741 if (ocp_data & LINK_LIST_READY)
2742 break;
8ddfa077 2743 usleep_range(1000, 2000);
43779f8d 2744 }
2745
2746 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2747 ocp_data |= RE_INIT_LL;
2748 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2749
2750 for (i = 0; i < 1000; i++) {
2751 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2752 if (ocp_data & LINK_LIST_READY)
2753 break;
8ddfa077 2754 usleep_range(1000, 2000);
43779f8d 2755 }
2756
69b4b7a4 2757 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2758
43779f8d 2759 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2760 ocp_data &= ~TEREDO_WAKE_MASK;
2761 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2762
c5554298 2763 rtl_rx_vlan_en(tp, true);
43779f8d 2764
2765 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2766 ocp_data |= ALDPS_PROXY_MODE;
2767 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2768
2769 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2770 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2771 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2772
00a5e360 2773 rxdy_gated_en(tp, false);
43779f8d 2774
2775 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2776 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2777 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2778}
2779
2780static void r8153_disable_aldps(struct r8152 *tp)
2781{
2782 u16 data;
2783
2784 data = ocp_reg_read(tp, OCP_POWER_CFG);
2785 data &= ~EN_ALDPS;
2786 ocp_reg_write(tp, OCP_POWER_CFG, data);
2787 msleep(20);
2788}
2789
2790static void r8153_enable_aldps(struct r8152 *tp)
2791{
2792 u16 data;
2793
2794 data = ocp_reg_read(tp, OCP_POWER_CFG);
2795 data |= EN_ALDPS;
2796 ocp_reg_write(tp, OCP_POWER_CFG, data);
2797}
2798
d70b1137 2799static void rtl8153_disable(struct r8152 *tp)
2800{
2801 r8153_disable_aldps(tp);
2802 rtl_disable(tp);
2803 r8153_enable_aldps(tp);
b214396f 2804 usb_enable_lpm(tp->udev);
d70b1137 2805}
2806
ac718b69 2807static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2808{
43779f8d 2809 u16 bmcr, anar, gbcr;
ac718b69 2810 int ret = 0;
2811
2812 cancel_delayed_work_sync(&tp->schedule);
2813 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2814 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2815 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2816 if (tp->mii.supports_gmii) {
2817 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2818 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2819 } else {
2820 gbcr = 0;
2821 }
ac718b69 2822
2823 if (autoneg == AUTONEG_DISABLE) {
2824 if (speed == SPEED_10) {
2825 bmcr = 0;
2826 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2827 } else if (speed == SPEED_100) {
2828 bmcr = BMCR_SPEED100;
2829 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2830 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2831 bmcr = BMCR_SPEED1000;
2832 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2833 } else {
2834 ret = -EINVAL;
2835 goto out;
2836 }
2837
2838 if (duplex == DUPLEX_FULL)
2839 bmcr |= BMCR_FULLDPLX;
2840 } else {
2841 if (speed == SPEED_10) {
2842 if (duplex == DUPLEX_FULL)
2843 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2844 else
2845 anar |= ADVERTISE_10HALF;
2846 } else if (speed == SPEED_100) {
2847 if (duplex == DUPLEX_FULL) {
2848 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2849 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2850 } else {
2851 anar |= ADVERTISE_10HALF;
2852 anar |= ADVERTISE_100HALF;
2853 }
43779f8d 2854 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2855 if (duplex == DUPLEX_FULL) {
2856 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2857 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2858 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2859 } else {
2860 anar |= ADVERTISE_10HALF;
2861 anar |= ADVERTISE_100HALF;
2862 gbcr |= ADVERTISE_1000HALF;
2863 }
ac718b69 2864 } else {
2865 ret = -EINVAL;
2866 goto out;
2867 }
2868
2869 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2870 }
2871
aa66a5f1 2872 if (test_bit(PHY_RESET, &tp->flags))
2873 bmcr |= BMCR_RESET;
2874
43779f8d 2875 if (tp->mii.supports_gmii)
2876 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2877
ac718b69 2878 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2879 r8152_mdio_write(tp, MII_BMCR, bmcr);
2880
aa66a5f1 2881 if (test_bit(PHY_RESET, &tp->flags)) {
2882 int i;
2883
2884 clear_bit(PHY_RESET, &tp->flags);
2885 for (i = 0; i < 50; i++) {
2886 msleep(20);
2887 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2888 break;
2889 }
2890 }
2891
ac718b69 2892out:
ac718b69 2893
2894 return ret;
2895}
2896
d70b1137 2897static void rtl8152_up(struct r8152 *tp)
2898{
2899 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2900 return;
2901
2902 r8152b_disable_aldps(tp);
2903 r8152b_exit_oob(tp);
2904 r8152b_enable_aldps(tp);
2905}
2906
ac718b69 2907static void rtl8152_down(struct r8152 *tp)
2908{
6871438c 2909 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2910 rtl_drop_queued_tx(tp);
2911 return;
2912 }
2913
00a5e360 2914 r8152_power_cut_en(tp, false);
ac718b69 2915 r8152b_disable_aldps(tp);
2916 r8152b_enter_oob(tp);
2917 r8152b_enable_aldps(tp);
2918}
2919
d70b1137 2920static void rtl8153_up(struct r8152 *tp)
2921{
2922 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2923 return;
2924
b214396f 2925 r8153_u1u2en(tp, false);
d70b1137 2926 r8153_disable_aldps(tp);
2927 r8153_first_init(tp);
2928 r8153_enable_aldps(tp);
b214396f 2929 r8153_u2p3en(tp, true);
2930 r8153_u1u2en(tp, true);
2931 usb_enable_lpm(tp->udev);
d70b1137 2932}
2933
43779f8d 2934static void rtl8153_down(struct r8152 *tp)
2935{
6871438c 2936 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2937 rtl_drop_queued_tx(tp);
2938 return;
2939 }
2940
b9702723 2941 r8153_u1u2en(tp, false);
b214396f 2942 r8153_u2p3en(tp, false);
b9702723 2943 r8153_power_cut_en(tp, false);
43779f8d 2944 r8153_disable_aldps(tp);
2945 r8153_enter_oob(tp);
2946 r8153_enable_aldps(tp);
2947}
2948
ac718b69 2949static void set_carrier(struct r8152 *tp)
2950{
2951 struct net_device *netdev = tp->netdev;
2952 u8 speed;
2953
40a82917 2954 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 2955 speed = rtl8152_get_speed(tp);
2956
2957 if (speed & LINK_STATUS) {
51d979fa 2958 if (!netif_carrier_ok(netdev)) {
c81229c9 2959 tp->rtl_ops.enable(tp);
ac718b69 2960 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
41cec84c 2961 napi_disable(&tp->napi);
ac718b69 2962 netif_carrier_on(netdev);
aa2e0926 2963 rtl_start_rx(tp);
41cec84c 2964 napi_enable(&tp->napi);
ac718b69 2965 }
2966 } else {
51d979fa 2967 if (netif_carrier_ok(netdev)) {
ac718b69 2968 netif_carrier_off(netdev);
d823ab68 2969 napi_disable(&tp->napi);
c81229c9 2970 tp->rtl_ops.disable(tp);
d823ab68 2971 napi_enable(&tp->napi);
ac718b69 2972 }
2973 }
ac718b69 2974}
2975
2976static void rtl_work_func_t(struct work_struct *work)
2977{
2978 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2979
a1f83fee 2980 /* If the device is unplugged or !netif_running(), the workqueue
2981 * doesn't need to wake the device, and could return directly.
2982 */
2983 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2984 return;
2985
9a4be1bd 2986 if (usb_autopm_get_interface(tp->intf) < 0)
2987 return;
2988
ac718b69 2989 if (!test_bit(WORK_ENABLE, &tp->flags))
2990 goto out1;
2991
b5403273 2992 if (!mutex_trylock(&tp->control)) {
2993 schedule_delayed_work(&tp->schedule, 0);
2994 goto out1;
2995 }
2996
40a82917 2997 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2998 set_carrier(tp);
ac718b69 2999
3000 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
3001 _rtl8152_set_rx_mode(tp->netdev);
3002
d823ab68 3003 /* don't schedule napi before linking */
3004 if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
51d979fa 3005 netif_carrier_ok(tp->netdev)) {
d823ab68 3006 clear_bit(SCHEDULE_NAPI, &tp->flags);
3007 napi_schedule(&tp->napi);
0c3121fc 3008 }
aa66a5f1 3009
3010 if (test_bit(PHY_RESET, &tp->flags))
3011 rtl_phy_reset(tp);
3012
b5403273 3013 mutex_unlock(&tp->control);
3014
ac718b69 3015out1:
9a4be1bd 3016 usb_autopm_put_interface(tp->intf);
ac718b69 3017}
3018
3019static int rtl8152_open(struct net_device *netdev)
3020{
3021 struct r8152 *tp = netdev_priv(netdev);
3022 int res = 0;
3023
7e9da481 3024 res = alloc_all_mem(tp);
3025 if (res)
3026 goto out;
3027
51d979fa 3028 netif_carrier_off(netdev);
f4c7476b 3029
9a4be1bd 3030 res = usb_autopm_get_interface(tp->intf);
3031 if (res < 0) {
3032 free_all_mem(tp);
3033 goto out;
3034 }
3035
b5403273 3036 mutex_lock(&tp->control);
3037
9a4be1bd 3038 /* The WORK_ENABLE may be set when autoresume occurs */
3039 if (test_bit(WORK_ENABLE, &tp->flags)) {
3040 clear_bit(WORK_ENABLE, &tp->flags);
3041 usb_kill_urb(tp->intr_urb);
3042 cancel_delayed_work_sync(&tp->schedule);
f4c7476b 3043
3044 /* disable the tx/rx, if the workqueue has enabled them. */
51d979fa 3045 if (netif_carrier_ok(netdev))
9a4be1bd 3046 tp->rtl_ops.disable(tp);
3047 }
3048
7e9da481 3049 tp->rtl_ops.up(tp);
3050
3d55f44f 3051 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3052 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3053 DUPLEX_FULL);
3d55f44f 3054 netif_carrier_off(netdev);
3055 netif_start_queue(netdev);
3056 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 3057
40a82917 3058 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3059 if (res) {
3060 if (res == -ENODEV)
3061 netif_device_detach(tp->netdev);
4a8deae2
HW
3062 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3063 res);
7e9da481 3064 free_all_mem(tp);
93ffbeab 3065 } else {
d823ab68 3066 napi_enable(&tp->napi);
ac718b69 3067 }
3068
b5403273 3069 mutex_unlock(&tp->control);
3070
9a4be1bd 3071 usb_autopm_put_interface(tp->intf);
ac718b69 3072
7e9da481 3073out:
ac718b69 3074 return res;
3075}
3076
3077static int rtl8152_close(struct net_device *netdev)
3078{
3079 struct r8152 *tp = netdev_priv(netdev);
3080 int res = 0;
3081
d823ab68 3082 napi_disable(&tp->napi);
ac718b69 3083 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 3084 usb_kill_urb(tp->intr_urb);
ac718b69 3085 cancel_delayed_work_sync(&tp->schedule);
3086 netif_stop_queue(netdev);
9a4be1bd 3087
3088 res = usb_autopm_get_interface(tp->intf);
53543db5 3089 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
9a4be1bd 3090 rtl_drop_queued_tx(tp);
d823ab68 3091 rtl_stop_rx(tp);
9a4be1bd 3092 } else {
b5403273 3093 mutex_lock(&tp->control);
3094
b209af99 3095 /* The autosuspend may have been enabled and wouldn't
9a4be1bd 3096 * be disable when autoresume occurs, because the
3097 * netif_running() would be false.
3098 */
923e1ee3 3099 rtl_runtime_suspend_enable(tp, false);
9a4be1bd 3100
9a4be1bd 3101 tp->rtl_ops.down(tp);
b5403273 3102
3103 mutex_unlock(&tp->control);
3104
9a4be1bd 3105 usb_autopm_put_interface(tp->intf);
3106 }
ac718b69 3107
7e9da481 3108 free_all_mem(tp);
3109
ac718b69 3110 return res;
3111}
3112
d24f6134 3113static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3114{
3115 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3116 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3117 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3118}
3119
3120static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3121{
3122 u16 data;
3123
3124 r8152_mmd_indirect(tp, dev, reg);
3125 data = ocp_reg_read(tp, OCP_EEE_DATA);
3126 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3127
3128 return data;
3129}
3130
3131static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
ac718b69 3132{
d24f6134 3133 r8152_mmd_indirect(tp, dev, reg);
3134 ocp_reg_write(tp, OCP_EEE_DATA, data);
3135 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3136}
3137
3138static void r8152_eee_en(struct r8152 *tp, bool enable)
3139{
3140 u16 config1, config2, config3;
45f4a19f 3141 u32 ocp_data;
ac718b69 3142
3143 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3144 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3145 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3146 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3147
3148 if (enable) {
3149 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3150 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3151 config1 |= sd_rise_time(1);
3152 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3153 config3 |= fast_snr(42);
3154 } else {
3155 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3156 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3157 RX_QUIET_EN);
3158 config1 |= sd_rise_time(7);
3159 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3160 config3 |= fast_snr(511);
3161 }
3162
ac718b69 3163 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3164 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3165 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3166 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
ac718b69 3167}
3168
d24f6134 3169static void r8152b_enable_eee(struct r8152 *tp)
3170{
3171 r8152_eee_en(tp, true);
3172 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3173}
3174
3175static void r8153_eee_en(struct r8152 *tp, bool enable)
43779f8d 3176{
3177 u32 ocp_data;
d24f6134 3178 u16 config;
43779f8d 3179
3180 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3181 config = ocp_reg_read(tp, OCP_EEE_CFG);
3182
3183 if (enable) {
3184 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3185 config |= EEE10_EN;
3186 } else {
3187 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3188 config &= ~EEE10_EN;
3189 }
3190
43779f8d 3191 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3192 ocp_reg_write(tp, OCP_EEE_CFG, config);
3193}
3194
3195static void r8153_enable_eee(struct r8152 *tp)
3196{
3197 r8153_eee_en(tp, true);
3198 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
43779f8d 3199}
3200
ac718b69 3201static void r8152b_enable_fc(struct r8152 *tp)
3202{
3203 u16 anar;
3204
3205 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3206 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3207 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3208}
3209
4f1d4d54 3210static void rtl_tally_reset(struct r8152 *tp)
3211{
3212 u32 ocp_data;
3213
3214 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3215 ocp_data |= TALLY_RESET;
3216 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3217}
3218
ac718b69 3219static void r8152b_init(struct r8152 *tp)
3220{
ebc2ec48 3221 u32 ocp_data;
ac718b69 3222
6871438c 3223 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3224 return;
3225
d70b1137 3226 r8152b_disable_aldps(tp);
3227
ac718b69 3228 if (tp->version == RTL_VER_01) {
3229 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3230 ocp_data &= ~LED_MODE_MASK;
3231 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3232 }
3233
00a5e360 3234 r8152_power_cut_en(tp, false);
ac718b69 3235
ac718b69 3236 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3237 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3238 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3239 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3240 ocp_data &= ~MCU_CLK_RATIO_MASK;
3241 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3242 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3243 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3244 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3245 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3246
3247 r8152b_enable_eee(tp);
3248 r8152b_enable_aldps(tp);
3249 r8152b_enable_fc(tp);
4f1d4d54 3250 rtl_tally_reset(tp);
ac718b69 3251
ebc2ec48 3252 /* enable rx aggregation */
ac718b69 3253 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 3254 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ac718b69 3255 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3256}
3257
43779f8d 3258static void r8153_init(struct r8152 *tp)
3259{
3260 u32 ocp_data;
3261 int i;
3262
6871438c 3263 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3264 return;
3265
d70b1137 3266 r8153_disable_aldps(tp);
b9702723 3267 r8153_u1u2en(tp, false);
43779f8d 3268
3269 for (i = 0; i < 500; i++) {
3270 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3271 AUTOLOAD_DONE)
3272 break;
3273 msleep(20);
3274 }
3275
3276 for (i = 0; i < 500; i++) {
3277 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3278 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3279 break;
3280 msleep(20);
3281 }
3282
b214396f 3283 usb_disable_lpm(tp->udev);
b9702723 3284 r8153_u2p3en(tp, false);
43779f8d 3285
65bab84c 3286 if (tp->version == RTL_VER_04) {
3287 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3288 ocp_data &= ~pwd_dn_scale_mask;
3289 ocp_data |= pwd_dn_scale(96);
3290 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3291
3292 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3293 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3294 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3295 } else if (tp->version == RTL_VER_05) {
3296 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3297 ocp_data &= ~ECM_ALDPS;
3298 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3299
fb02eb4a 3300 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3301 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3302 ocp_data &= ~DYNAMIC_BURST;
3303 else
3304 ocp_data |= DYNAMIC_BURST;
3305 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3306 } else if (tp->version == RTL_VER_06) {
65bab84c 3307 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3308 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3309 ocp_data &= ~DYNAMIC_BURST;
3310 else
3311 ocp_data |= DYNAMIC_BURST;
3312 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3313 }
3314
3315 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3316 ocp_data |= EP4_FULL_FC;
3317 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3318
43779f8d 3319 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3320 ocp_data &= ~TIMER11_EN;
3321 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3322
43779f8d 3323 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3324 ocp_data &= ~LED_MODE_MASK;
3325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3326
65bab84c 3327 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
34203e25 3328 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
43779f8d 3329 ocp_data |= LPM_TIMER_500MS;
34203e25 3330 else
3331 ocp_data |= LPM_TIMER_500US;
43779f8d 3332 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3333
3334 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3335 ocp_data &= ~SEN_VAL_MASK;
3336 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3337 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3338
65bab84c 3339 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3340
b9702723 3341 r8153_power_cut_en(tp, false);
3342 r8153_u1u2en(tp, true);
43779f8d 3343
43779f8d 3344 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3345 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3346 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3347 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3348 U1U2_SPDWN_EN | L1_SPDWN_EN);
3349 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3350 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3351 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3352 EEE_SPDWN_EN);
3353
3354 r8153_enable_eee(tp);
3355 r8153_enable_aldps(tp);
3356 r8152b_enable_fc(tp);
4f1d4d54 3357 rtl_tally_reset(tp);
b214396f 3358 r8153_u2p3en(tp, true);
43779f8d 3359}
3360
e501139a 3361static int rtl8152_pre_reset(struct usb_interface *intf)
3362{
3363 struct r8152 *tp = usb_get_intfdata(intf);
3364 struct net_device *netdev;
3365
3366 if (!tp)
3367 return 0;
3368
3369 netdev = tp->netdev;
3370 if (!netif_running(netdev))
3371 return 0;
3372
3373 napi_disable(&tp->napi);
3374 clear_bit(WORK_ENABLE, &tp->flags);
3375 usb_kill_urb(tp->intr_urb);
3376 cancel_delayed_work_sync(&tp->schedule);
3377 if (netif_carrier_ok(netdev)) {
3378 netif_stop_queue(netdev);
3379 mutex_lock(&tp->control);
3380 tp->rtl_ops.disable(tp);
3381 mutex_unlock(&tp->control);
3382 }
3383
3384 return 0;
3385}
3386
3387static int rtl8152_post_reset(struct usb_interface *intf)
3388{
3389 struct r8152 *tp = usb_get_intfdata(intf);
3390 struct net_device *netdev;
3391
3392 if (!tp)
3393 return 0;
3394
3395 netdev = tp->netdev;
3396 if (!netif_running(netdev))
3397 return 0;
3398
3399 set_bit(WORK_ENABLE, &tp->flags);
3400 if (netif_carrier_ok(netdev)) {
3401 mutex_lock(&tp->control);
3402 tp->rtl_ops.enable(tp);
3403 rtl8152_set_rx_mode(netdev);
3404 mutex_unlock(&tp->control);
3405 netif_wake_queue(netdev);
3406 }
3407
3408 napi_enable(&tp->napi);
3409
3410 return 0;
43779f8d 3411}
3412
ac718b69 3413static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3414{
3415 struct r8152 *tp = usb_get_intfdata(intf);
6cc69f2a 3416 struct net_device *netdev = tp->netdev;
3417 int ret = 0;
ac718b69 3418
b5403273 3419 mutex_lock(&tp->control);
3420
6cc69f2a 3421 if (PMSG_IS_AUTO(message)) {
3422 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3423 ret = -EBUSY;
3424 goto out1;
3425 }
3426
9a4be1bd 3427 set_bit(SELECTIVE_SUSPEND, &tp->flags);
6cc69f2a 3428 } else {
3429 netif_device_detach(netdev);
3430 }
ac718b69 3431
e3bd1a81 3432 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ac718b69 3433 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3434 usb_kill_urb(tp->intr_urb);
d823ab68 3435 napi_disable(&tp->napi);
9a4be1bd 3436 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
445f7f4d 3437 rtl_stop_rx(tp);
9a4be1bd 3438 rtl_runtime_suspend_enable(tp, true);
3439 } else {
6cc69f2a 3440 cancel_delayed_work_sync(&tp->schedule);
9a4be1bd 3441 tp->rtl_ops.down(tp);
9a4be1bd 3442 }
d823ab68 3443 napi_enable(&tp->napi);
ac718b69 3444 }
6cc69f2a 3445out1:
b5403273 3446 mutex_unlock(&tp->control);
3447
6cc69f2a 3448 return ret;
ac718b69 3449}
3450
3451static int rtl8152_resume(struct usb_interface *intf)
3452{
3453 struct r8152 *tp = usb_get_intfdata(intf);
3454
b5403273 3455 mutex_lock(&tp->control);
3456
9a4be1bd 3457 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3458 tp->rtl_ops.init(tp);
3459 netif_device_attach(tp->netdev);
3460 }
3461
ac718b69 3462 if (netif_running(tp->netdev)) {
9a4be1bd 3463 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3464 rtl_runtime_suspend_enable(tp, false);
3465 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
41cec84c 3466 napi_disable(&tp->napi);
445f7f4d 3467 set_bit(WORK_ENABLE, &tp->flags);
51d979fa 3468 if (netif_carrier_ok(tp->netdev))
445f7f4d 3469 rtl_start_rx(tp);
41cec84c 3470 napi_enable(&tp->napi);
9a4be1bd 3471 } else {
3472 tp->rtl_ops.up(tp);
3473 rtl8152_set_speed(tp, AUTONEG_ENABLE,
b209af99 3474 tp->mii.supports_gmii ?
3475 SPEED_1000 : SPEED_100,
3476 DUPLEX_FULL);
445f7f4d 3477 netif_carrier_off(tp->netdev);
3478 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3479 }
40a82917 3480 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3481 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3482 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3483 }
3484
b5403273 3485 mutex_unlock(&tp->control);
3486
ac718b69 3487 return 0;
3488}
3489
21ff2e89 3490static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3491{
3492 struct r8152 *tp = netdev_priv(dev);
3493
9a4be1bd 3494 if (usb_autopm_get_interface(tp->intf) < 0)
3495 return;
3496
7daed8dc 3497 if (!rtl_can_wakeup(tp)) {
3498 wol->supported = 0;
3499 wol->wolopts = 0;
3500 } else {
3501 mutex_lock(&tp->control);
3502 wol->supported = WAKE_ANY;
3503 wol->wolopts = __rtl_get_wol(tp);
3504 mutex_unlock(&tp->control);
3505 }
b5403273 3506
9a4be1bd 3507 usb_autopm_put_interface(tp->intf);
21ff2e89 3508}
3509
3510static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3511{
3512 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3513 int ret;
3514
7daed8dc 3515 if (!rtl_can_wakeup(tp))
3516 return -EOPNOTSUPP;
3517
9a4be1bd 3518 ret = usb_autopm_get_interface(tp->intf);
3519 if (ret < 0)
3520 goto out_set_wol;
21ff2e89 3521
b5403273 3522 mutex_lock(&tp->control);
3523
21ff2e89 3524 __rtl_set_wol(tp, wol->wolopts);
3525 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3526
b5403273 3527 mutex_unlock(&tp->control);
3528
9a4be1bd 3529 usb_autopm_put_interface(tp->intf);
3530
3531out_set_wol:
3532 return ret;
21ff2e89 3533}
3534
a5ec27c1 3535static u32 rtl8152_get_msglevel(struct net_device *dev)
3536{
3537 struct r8152 *tp = netdev_priv(dev);
3538
3539 return tp->msg_enable;
3540}
3541
3542static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3543{
3544 struct r8152 *tp = netdev_priv(dev);
3545
3546 tp->msg_enable = value;
3547}
3548
ac718b69 3549static void rtl8152_get_drvinfo(struct net_device *netdev,
3550 struct ethtool_drvinfo *info)
3551{
3552 struct r8152 *tp = netdev_priv(netdev);
3553
b0b46c77 3554 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3555 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3556 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3557}
3558
3559static
3560int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3561{
3562 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3563 int ret;
ac718b69 3564
3565 if (!tp->mii.mdio_read)
3566 return -EOPNOTSUPP;
3567
8d4a4d72 3568 ret = usb_autopm_get_interface(tp->intf);
3569 if (ret < 0)
3570 goto out;
3571
b5403273 3572 mutex_lock(&tp->control);
3573
8d4a4d72 3574 ret = mii_ethtool_gset(&tp->mii, cmd);
3575
b5403273 3576 mutex_unlock(&tp->control);
3577
8d4a4d72 3578 usb_autopm_put_interface(tp->intf);
3579
3580out:
3581 return ret;
ac718b69 3582}
3583
3584static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3585{
3586 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3587 int ret;
3588
3589 ret = usb_autopm_get_interface(tp->intf);
3590 if (ret < 0)
3591 goto out;
ac718b69 3592
b5403273 3593 mutex_lock(&tp->control);
3594
9a4be1bd 3595 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3596
b5403273 3597 mutex_unlock(&tp->control);
3598
9a4be1bd 3599 usb_autopm_put_interface(tp->intf);
3600
3601out:
3602 return ret;
ac718b69 3603}
3604
4f1d4d54 3605static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3606 "tx_packets",
3607 "rx_packets",
3608 "tx_errors",
3609 "rx_errors",
3610 "rx_missed",
3611 "align_errors",
3612 "tx_single_collisions",
3613 "tx_multi_collisions",
3614 "rx_unicast",
3615 "rx_broadcast",
3616 "rx_multicast",
3617 "tx_aborted",
3618 "tx_underrun",
3619};
3620
3621static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3622{
3623 switch (sset) {
3624 case ETH_SS_STATS:
3625 return ARRAY_SIZE(rtl8152_gstrings);
3626 default:
3627 return -EOPNOTSUPP;
3628 }
3629}
3630
3631static void rtl8152_get_ethtool_stats(struct net_device *dev,
3632 struct ethtool_stats *stats, u64 *data)
3633{
3634 struct r8152 *tp = netdev_priv(dev);
3635 struct tally_counter tally;
3636
0b030244 3637 if (usb_autopm_get_interface(tp->intf) < 0)
3638 return;
3639
4f1d4d54 3640 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3641
0b030244 3642 usb_autopm_put_interface(tp->intf);
3643
4f1d4d54 3644 data[0] = le64_to_cpu(tally.tx_packets);
3645 data[1] = le64_to_cpu(tally.rx_packets);
3646 data[2] = le64_to_cpu(tally.tx_errors);
3647 data[3] = le32_to_cpu(tally.rx_errors);
3648 data[4] = le16_to_cpu(tally.rx_missed);
3649 data[5] = le16_to_cpu(tally.align_errors);
3650 data[6] = le32_to_cpu(tally.tx_one_collision);
3651 data[7] = le32_to_cpu(tally.tx_multi_collision);
3652 data[8] = le64_to_cpu(tally.rx_unicast);
3653 data[9] = le64_to_cpu(tally.rx_broadcast);
3654 data[10] = le32_to_cpu(tally.rx_multicast);
3655 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3656 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3657}
3658
3659static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3660{
3661 switch (stringset) {
3662 case ETH_SS_STATS:
3663 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3664 break;
3665 }
3666}
3667
df35d283 3668static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3669{
3670 u32 ocp_data, lp, adv, supported = 0;
3671 u16 val;
3672
3673 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3674 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3675
3676 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3677 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3678
3679 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3680 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3681
3682 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3683 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3684
3685 eee->eee_enabled = !!ocp_data;
3686 eee->eee_active = !!(supported & adv & lp);
3687 eee->supported = supported;
3688 eee->advertised = adv;
3689 eee->lp_advertised = lp;
3690
3691 return 0;
3692}
3693
3694static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3695{
3696 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3697
3698 r8152_eee_en(tp, eee->eee_enabled);
3699
3700 if (!eee->eee_enabled)
3701 val = 0;
3702
3703 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3704
3705 return 0;
3706}
3707
3708static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3709{
3710 u32 ocp_data, lp, adv, supported = 0;
3711 u16 val;
3712
3713 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3714 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3715
3716 val = ocp_reg_read(tp, OCP_EEE_ADV);
3717 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3718
3719 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3720 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3721
3722 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3723 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3724
3725 eee->eee_enabled = !!ocp_data;
3726 eee->eee_active = !!(supported & adv & lp);
3727 eee->supported = supported;
3728 eee->advertised = adv;
3729 eee->lp_advertised = lp;
3730
3731 return 0;
3732}
3733
3734static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3735{
3736 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3737
3738 r8153_eee_en(tp, eee->eee_enabled);
3739
3740 if (!eee->eee_enabled)
3741 val = 0;
3742
3743 ocp_reg_write(tp, OCP_EEE_ADV, val);
3744
3745 return 0;
3746}
3747
3748static int
3749rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3750{
3751 struct r8152 *tp = netdev_priv(net);
3752 int ret;
3753
3754 ret = usb_autopm_get_interface(tp->intf);
3755 if (ret < 0)
3756 goto out;
3757
b5403273 3758 mutex_lock(&tp->control);
3759
df35d283 3760 ret = tp->rtl_ops.eee_get(tp, edata);
3761
b5403273 3762 mutex_unlock(&tp->control);
3763
df35d283 3764 usb_autopm_put_interface(tp->intf);
3765
3766out:
3767 return ret;
3768}
3769
3770static int
3771rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3772{
3773 struct r8152 *tp = netdev_priv(net);
3774 int ret;
3775
3776 ret = usb_autopm_get_interface(tp->intf);
3777 if (ret < 0)
3778 goto out;
3779
b5403273 3780 mutex_lock(&tp->control);
3781
df35d283 3782 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 3783 if (!ret)
3784 ret = mii_nway_restart(&tp->mii);
df35d283 3785
b5403273 3786 mutex_unlock(&tp->control);
3787
df35d283 3788 usb_autopm_put_interface(tp->intf);
3789
3790out:
3791 return ret;
3792}
3793
8884f507 3794static int rtl8152_nway_reset(struct net_device *dev)
3795{
3796 struct r8152 *tp = netdev_priv(dev);
3797 int ret;
3798
3799 ret = usb_autopm_get_interface(tp->intf);
3800 if (ret < 0)
3801 goto out;
3802
3803 mutex_lock(&tp->control);
3804
3805 ret = mii_nway_restart(&tp->mii);
3806
3807 mutex_unlock(&tp->control);
3808
3809 usb_autopm_put_interface(tp->intf);
3810
3811out:
3812 return ret;
3813}
3814
efb3dd88 3815static int rtl8152_get_coalesce(struct net_device *netdev,
3816 struct ethtool_coalesce *coalesce)
3817{
3818 struct r8152 *tp = netdev_priv(netdev);
3819
3820 switch (tp->version) {
3821 case RTL_VER_01:
3822 case RTL_VER_02:
3823 return -EOPNOTSUPP;
3824 default:
3825 break;
3826 }
3827
3828 coalesce->rx_coalesce_usecs = tp->coalesce;
3829
3830 return 0;
3831}
3832
3833static int rtl8152_set_coalesce(struct net_device *netdev,
3834 struct ethtool_coalesce *coalesce)
3835{
3836 struct r8152 *tp = netdev_priv(netdev);
3837 int ret;
3838
3839 switch (tp->version) {
3840 case RTL_VER_01:
3841 case RTL_VER_02:
3842 return -EOPNOTSUPP;
3843 default:
3844 break;
3845 }
3846
3847 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
3848 return -EINVAL;
3849
3850 ret = usb_autopm_get_interface(tp->intf);
3851 if (ret < 0)
3852 return ret;
3853
3854 mutex_lock(&tp->control);
3855
3856 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
3857 tp->coalesce = coalesce->rx_coalesce_usecs;
3858
3859 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
3860 r8153_set_rx_early_timeout(tp);
3861 }
3862
3863 mutex_unlock(&tp->control);
3864
3865 usb_autopm_put_interface(tp->intf);
3866
3867 return ret;
3868}
3869
ac718b69 3870static struct ethtool_ops ops = {
3871 .get_drvinfo = rtl8152_get_drvinfo,
3872 .get_settings = rtl8152_get_settings,
3873 .set_settings = rtl8152_set_settings,
3874 .get_link = ethtool_op_get_link,
8884f507 3875 .nway_reset = rtl8152_nway_reset,
a5ec27c1 3876 .get_msglevel = rtl8152_get_msglevel,
3877 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 3878 .get_wol = rtl8152_get_wol,
3879 .set_wol = rtl8152_set_wol,
4f1d4d54 3880 .get_strings = rtl8152_get_strings,
3881 .get_sset_count = rtl8152_get_sset_count,
3882 .get_ethtool_stats = rtl8152_get_ethtool_stats,
efb3dd88 3883 .get_coalesce = rtl8152_get_coalesce,
3884 .set_coalesce = rtl8152_set_coalesce,
df35d283 3885 .get_eee = rtl_ethtool_get_eee,
3886 .set_eee = rtl_ethtool_set_eee,
ac718b69 3887};
3888
3889static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3890{
3891 struct r8152 *tp = netdev_priv(netdev);
3892 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 3893 int res;
3894
6871438c 3895 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3896 return -ENODEV;
3897
9a4be1bd 3898 res = usb_autopm_get_interface(tp->intf);
3899 if (res < 0)
3900 goto out;
ac718b69 3901
3902 switch (cmd) {
3903 case SIOCGMIIPHY:
3904 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3905 break;
3906
3907 case SIOCGMIIREG:
b5403273 3908 mutex_lock(&tp->control);
ac718b69 3909 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 3910 mutex_unlock(&tp->control);
ac718b69 3911 break;
3912
3913 case SIOCSMIIREG:
3914 if (!capable(CAP_NET_ADMIN)) {
3915 res = -EPERM;
3916 break;
3917 }
b5403273 3918 mutex_lock(&tp->control);
ac718b69 3919 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 3920 mutex_unlock(&tp->control);
ac718b69 3921 break;
3922
3923 default:
3924 res = -EOPNOTSUPP;
3925 }
3926
9a4be1bd 3927 usb_autopm_put_interface(tp->intf);
3928
3929out:
ac718b69 3930 return res;
3931}
3932
69b4b7a4 3933static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3934{
3935 struct r8152 *tp = netdev_priv(dev);
396e2e23 3936 int ret;
69b4b7a4 3937
3938 switch (tp->version) {
3939 case RTL_VER_01:
3940 case RTL_VER_02:
3941 return eth_change_mtu(dev, new_mtu);
3942 default:
3943 break;
3944 }
3945
3946 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3947 return -EINVAL;
3948
396e2e23 3949 ret = usb_autopm_get_interface(tp->intf);
3950 if (ret < 0)
3951 return ret;
3952
3953 mutex_lock(&tp->control);
3954
69b4b7a4 3955 dev->mtu = new_mtu;
3956
396e2e23 3957 if (netif_running(dev) && netif_carrier_ok(dev))
3958 r8153_set_rx_early_size(tp);
3959
3960 mutex_unlock(&tp->control);
3961
3962 usb_autopm_put_interface(tp->intf);
3963
3964 return ret;
69b4b7a4 3965}
3966
ac718b69 3967static const struct net_device_ops rtl8152_netdev_ops = {
3968 .ndo_open = rtl8152_open,
3969 .ndo_stop = rtl8152_close,
3970 .ndo_do_ioctl = rtl8152_ioctl,
3971 .ndo_start_xmit = rtl8152_start_xmit,
3972 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 3973 .ndo_set_features = rtl8152_set_features,
ac718b69 3974 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3975 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 3976 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 3977 .ndo_validate_addr = eth_validate_addr,
a5e31255 3978 .ndo_features_check = rtl8152_features_check,
ac718b69 3979};
3980
3981static void r8152b_get_version(struct r8152 *tp)
3982{
3983 u32 ocp_data;
3984 u16 version;
3985
3986 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3987 version = (u16)(ocp_data & VERSION_MASK);
3988
3989 switch (version) {
3990 case 0x4c00:
3991 tp->version = RTL_VER_01;
3992 break;
3993 case 0x4c10:
3994 tp->version = RTL_VER_02;
3995 break;
43779f8d 3996 case 0x5c00:
3997 tp->version = RTL_VER_03;
3998 tp->mii.supports_gmii = 1;
3999 break;
4000 case 0x5c10:
4001 tp->version = RTL_VER_04;
4002 tp->mii.supports_gmii = 1;
4003 break;
4004 case 0x5c20:
4005 tp->version = RTL_VER_05;
4006 tp->mii.supports_gmii = 1;
4007 break;
fb02eb4a 4008 case 0x5c30:
4009 tp->version = RTL_VER_06;
4010 tp->mii.supports_gmii = 1;
4011 break;
ac718b69 4012 default:
4013 netif_info(tp, probe, tp->netdev,
4014 "Unknown version 0x%04x\n", version);
4015 break;
4016 }
4017}
4018
e3fe0b1a 4019static void rtl8152_unload(struct r8152 *tp)
4020{
6871438c 4021 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4022 return;
4023
00a5e360 4024 if (tp->version != RTL_VER_01)
4025 r8152_power_cut_en(tp, true);
e3fe0b1a 4026}
4027
43779f8d 4028static void rtl8153_unload(struct r8152 *tp)
4029{
6871438c 4030 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4031 return;
4032
49be1723 4033 r8153_power_cut_en(tp, false);
43779f8d 4034}
4035
55b65475 4036static int rtl_ops_init(struct r8152 *tp)
c81229c9 4037{
4038 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 4039 int ret = 0;
4040
4041 switch (tp->version) {
4042 case RTL_VER_01:
4043 case RTL_VER_02:
4044 ops->init = r8152b_init;
4045 ops->enable = rtl8152_enable;
4046 ops->disable = rtl8152_disable;
4047 ops->up = rtl8152_up;
4048 ops->down = rtl8152_down;
4049 ops->unload = rtl8152_unload;
4050 ops->eee_get = r8152_get_eee;
4051 ops->eee_set = r8152_set_eee;
43779f8d 4052 break;
4053
55b65475 4054 case RTL_VER_03:
4055 case RTL_VER_04:
4056 case RTL_VER_05:
fb02eb4a 4057 case RTL_VER_06:
55b65475 4058 ops->init = r8153_init;
4059 ops->enable = rtl8153_enable;
4060 ops->disable = rtl8153_disable;
4061 ops->up = rtl8153_up;
4062 ops->down = rtl8153_down;
4063 ops->unload = rtl8153_unload;
4064 ops->eee_get = r8153_get_eee;
4065 ops->eee_set = r8153_set_eee;
c81229c9 4066 break;
4067
4068 default:
55b65475 4069 ret = -ENODEV;
4070 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 4071 break;
4072 }
4073
4074 return ret;
4075}
4076
ac718b69 4077static int rtl8152_probe(struct usb_interface *intf,
4078 const struct usb_device_id *id)
4079{
4080 struct usb_device *udev = interface_to_usbdev(intf);
4081 struct r8152 *tp;
4082 struct net_device *netdev;
ebc2ec48 4083 int ret;
ac718b69 4084
10c32717 4085 if (udev->actconfig->desc.bConfigurationValue != 1) {
4086 usb_driver_set_configuration(udev, 1);
4087 return -ENODEV;
4088 }
4089
4090 usb_reset_device(udev);
ac718b69 4091 netdev = alloc_etherdev(sizeof(struct r8152));
4092 if (!netdev) {
4a8deae2 4093 dev_err(&intf->dev, "Out of memory\n");
ac718b69 4094 return -ENOMEM;
4095 }
4096
ebc2ec48 4097 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 4098 tp = netdev_priv(netdev);
4099 tp->msg_enable = 0x7FFF;
4100
e3ad412a 4101 tp->udev = udev;
4102 tp->netdev = netdev;
4103 tp->intf = intf;
4104
82cf94cb 4105 r8152b_get_version(tp);
55b65475 4106 ret = rtl_ops_init(tp);
31ca1dec 4107 if (ret)
4108 goto out;
c81229c9 4109
b5403273 4110 mutex_init(&tp->control);
ac718b69 4111 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
4112
ac718b69 4113 netdev->netdev_ops = &rtl8152_netdev_ops;
4114 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 4115
60c89071 4116 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4117 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 4118 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4119 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 4120 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4121 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 4122 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
ccc39faf 4123 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
c5554298 4124 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4125 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4126 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 4127
7ad24ea4 4128 netdev->ethtool_ops = &ops;
60c89071 4129 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 4130
4131 tp->mii.dev = netdev;
4132 tp->mii.mdio_read = read_mii_word;
4133 tp->mii.mdio_write = write_mii_word;
4134 tp->mii.phy_id_mask = 0x3f;
4135 tp->mii.reg_num_mask = 0x1f;
4136 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 4137
464ec10a 4138 switch (udev->speed) {
4139 case USB_SPEED_SUPER:
4140 tp->coalesce = COALESCE_SUPER;
4141 break;
4142 case USB_SPEED_HIGH:
4143 tp->coalesce = COALESCE_HIGH;
4144 break;
4145 default:
4146 tp->coalesce = COALESCE_SLOW;
4147 break;
4148 }
4149
9a4be1bd 4150 intf->needs_remote_wakeup = 1;
4151
c81229c9 4152 tp->rtl_ops.init(tp);
ac718b69 4153 set_ethernet_addr(tp);
4154
ac718b69 4155 usb_set_intfdata(intf, tp);
d823ab68 4156 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
ac718b69 4157
ebc2ec48 4158 ret = register_netdev(netdev);
4159 if (ret != 0) {
4a8deae2 4160 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 4161 goto out1;
ac718b69 4162 }
4163
7daed8dc 4164 if (!rtl_can_wakeup(tp))
4165 __rtl_set_wol(tp, 0);
4166
21ff2e89 4167 tp->saved_wolopts = __rtl_get_wol(tp);
4168 if (tp->saved_wolopts)
4169 device_set_wakeup_enable(&udev->dev, true);
4170 else
4171 device_set_wakeup_enable(&udev->dev, false);
4172
4a8deae2 4173 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 4174
4175 return 0;
4176
ac718b69 4177out1:
d823ab68 4178 netif_napi_del(&tp->napi);
ebc2ec48 4179 usb_set_intfdata(intf, NULL);
ac718b69 4180out:
4181 free_netdev(netdev);
ebc2ec48 4182 return ret;
ac718b69 4183}
4184
ac718b69 4185static void rtl8152_disconnect(struct usb_interface *intf)
4186{
4187 struct r8152 *tp = usb_get_intfdata(intf);
4188
4189 usb_set_intfdata(intf, NULL);
4190 if (tp) {
f561de33 4191 struct usb_device *udev = tp->udev;
4192
4193 if (udev->state == USB_STATE_NOTATTACHED)
4194 set_bit(RTL8152_UNPLUG, &tp->flags);
4195
d823ab68 4196 netif_napi_del(&tp->napi);
ac718b69 4197 unregister_netdev(tp->netdev);
c81229c9 4198 tp->rtl_ops.unload(tp);
ac718b69 4199 free_netdev(tp->netdev);
4200 }
4201}
4202
d9a28c5b 4203#define REALTEK_USB_DEVICE(vend, prod) \
4204 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4205 USB_DEVICE_ID_MATCH_INT_CLASS, \
4206 .idVendor = (vend), \
4207 .idProduct = (prod), \
4208 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4209}, \
4210{ \
4211 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4212 USB_DEVICE_ID_MATCH_DEVICE, \
4213 .idVendor = (vend), \
4214 .idProduct = (prod), \
4215 .bInterfaceClass = USB_CLASS_COMM, \
4216 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4217 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4218
ac718b69 4219/* table of devices that work with this driver */
4220static struct usb_device_id rtl8152_table[] = {
d9a28c5b 4221 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4222 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4223 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
347eec34 4224 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
1006da19 4225 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
d065c3c1 4226 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
ac718b69 4227 {}
4228};
4229
4230MODULE_DEVICE_TABLE(usb, rtl8152_table);
4231
4232static struct usb_driver rtl8152_driver = {
4233 .name = MODULENAME,
ebc2ec48 4234 .id_table = rtl8152_table,
ac718b69 4235 .probe = rtl8152_probe,
4236 .disconnect = rtl8152_disconnect,
ac718b69 4237 .suspend = rtl8152_suspend,
ebc2ec48 4238 .resume = rtl8152_resume,
4239 .reset_resume = rtl8152_resume,
e501139a 4240 .pre_reset = rtl8152_pre_reset,
4241 .post_reset = rtl8152_post_reset,
9a4be1bd 4242 .supports_autosuspend = 1,
a634782f 4243 .disable_hub_initiated_lpm = 1,
ac718b69 4244};
4245
b4236daa 4246module_usb_driver(rtl8152_driver);
ac718b69 4247
4248MODULE_AUTHOR(DRIVER_AUTHOR);
4249MODULE_DESCRIPTION(DRIVER_DESC);
4250MODULE_LICENSE("GPL");
This page took 0.642301 seconds and 5 git commands to generate.