rds: Make rds_message_copy_from_user() return 0 on success.
[deliverable/linux.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
d9a28c5b 27#include <linux/usb/cdc.h>
ac718b69 28
29/* Version Information */
d823ab68 30#define DRIVER_VERSION "v1.08.0 (2015/01/13)"
ac718b69 31#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 32#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 33#define MODULENAME "r8152"
34
35#define R8152_PHY_ID 32
36
37#define PLA_IDR 0xc000
38#define PLA_RCR 0xc010
39#define PLA_RMS 0xc016
40#define PLA_RXFIFO_CTRL0 0xc0a0
41#define PLA_RXFIFO_CTRL1 0xc0a4
42#define PLA_RXFIFO_CTRL2 0xc0a8
43#define PLA_FMC 0xc0b4
44#define PLA_CFG_WOL 0xc0b6
43779f8d 45#define PLA_TEREDO_CFG 0xc0bc
ac718b69 46#define PLA_MAR 0xcd00
43779f8d 47#define PLA_BACKUP 0xd000
ac718b69 48#define PAL_BDC_CR 0xd1a0
43779f8d 49#define PLA_TEREDO_TIMER 0xd2cc
50#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 51#define PLA_LEDSEL 0xdd90
52#define PLA_LED_FEATURE 0xdd92
53#define PLA_PHYAR 0xde00
43779f8d 54#define PLA_BOOT_CTRL 0xe004
ac718b69 55#define PLA_GPHY_INTR_IMR 0xe022
56#define PLA_EEE_CR 0xe040
57#define PLA_EEEP_CR 0xe080
58#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 59#define PLA_MAC_PWR_CTRL2 0xe0ca
60#define PLA_MAC_PWR_CTRL3 0xe0cc
61#define PLA_MAC_PWR_CTRL4 0xe0ce
62#define PLA_WDT6_CTRL 0xe428
ac718b69 63#define PLA_TCR0 0xe610
64#define PLA_TCR1 0xe612
69b4b7a4 65#define PLA_MTPS 0xe615
ac718b69 66#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 67#define PLA_RSTTALLY 0xe800
ac718b69 68#define PLA_CR 0xe813
69#define PLA_CRWECR 0xe81c
21ff2e89 70#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
71#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 72#define PLA_CONFIG5 0xe822
73#define PLA_PHY_PWR 0xe84c
74#define PLA_OOB_CTRL 0xe84f
75#define PLA_CPCR 0xe854
76#define PLA_MISC_0 0xe858
77#define PLA_MISC_1 0xe85a
78#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 79#define PLA_TALLYCNT 0xe890
ac718b69 80#define PLA_SFF_STS_7 0xe8de
81#define PLA_PHYSTATUS 0xe908
82#define PLA_BP_BA 0xfc26
83#define PLA_BP_0 0xfc28
84#define PLA_BP_1 0xfc2a
85#define PLA_BP_2 0xfc2c
86#define PLA_BP_3 0xfc2e
87#define PLA_BP_4 0xfc30
88#define PLA_BP_5 0xfc32
89#define PLA_BP_6 0xfc34
90#define PLA_BP_7 0xfc36
43779f8d 91#define PLA_BP_EN 0xfc38
ac718b69 92
43779f8d 93#define USB_U2P3_CTRL 0xb460
ac718b69 94#define USB_DEV_STAT 0xb808
95#define USB_USB_CTRL 0xd406
96#define USB_PHY_CTRL 0xd408
97#define USB_TX_AGG 0xd40a
98#define USB_RX_BUF_TH 0xd40c
99#define USB_USB_TIMER 0xd428
43779f8d 100#define USB_RX_EARLY_AGG 0xd42c
ac718b69 101#define USB_PM_CTRL_STATUS 0xd432
102#define USB_TX_DMA 0xd434
43779f8d 103#define USB_TOLERANCE 0xd490
104#define USB_LPM_CTRL 0xd41a
ac718b69 105#define USB_UPS_CTRL 0xd800
43779f8d 106#define USB_MISC_0 0xd81a
107#define USB_POWER_CUT 0xd80a
108#define USB_AFE_CTRL2 0xd824
109#define USB_WDT11_CTRL 0xe43c
ac718b69 110#define USB_BP_BA 0xfc26
111#define USB_BP_0 0xfc28
112#define USB_BP_1 0xfc2a
113#define USB_BP_2 0xfc2c
114#define USB_BP_3 0xfc2e
115#define USB_BP_4 0xfc30
116#define USB_BP_5 0xfc32
117#define USB_BP_6 0xfc34
118#define USB_BP_7 0xfc36
43779f8d 119#define USB_BP_EN 0xfc38
ac718b69 120
121/* OCP Registers */
122#define OCP_ALDPS_CONFIG 0x2010
123#define OCP_EEE_CONFIG1 0x2080
124#define OCP_EEE_CONFIG2 0x2092
125#define OCP_EEE_CONFIG3 0x2094
ac244d3e 126#define OCP_BASE_MII 0xa400
ac718b69 127#define OCP_EEE_AR 0xa41a
128#define OCP_EEE_DATA 0xa41c
43779f8d 129#define OCP_PHY_STATUS 0xa420
130#define OCP_POWER_CFG 0xa430
131#define OCP_EEE_CFG 0xa432
132#define OCP_SRAM_ADDR 0xa436
133#define OCP_SRAM_DATA 0xa438
134#define OCP_DOWN_SPEED 0xa442
df35d283 135#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 136#define OCP_EEE_ADV 0xa5d0
df35d283 137#define OCP_EEE_LPABLE 0xa5d2
43779f8d 138#define OCP_ADC_CFG 0xbc06
139
140/* SRAM Register */
141#define SRAM_LPF_CFG 0x8012
142#define SRAM_10M_AMP1 0x8080
143#define SRAM_10M_AMP2 0x8082
144#define SRAM_IMPEDANCE 0x8084
ac718b69 145
146/* PLA_RCR */
147#define RCR_AAP 0x00000001
148#define RCR_APM 0x00000002
149#define RCR_AM 0x00000004
150#define RCR_AB 0x00000008
151#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
152
153/* PLA_RXFIFO_CTRL0 */
154#define RXFIFO_THR1_NORMAL 0x00080002
155#define RXFIFO_THR1_OOB 0x01800003
156
157/* PLA_RXFIFO_CTRL1 */
158#define RXFIFO_THR2_FULL 0x00000060
159#define RXFIFO_THR2_HIGH 0x00000038
160#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 161#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 162
163/* PLA_RXFIFO_CTRL2 */
164#define RXFIFO_THR3_FULL 0x00000078
165#define RXFIFO_THR3_HIGH 0x00000048
166#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 167#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 168
169/* PLA_TXFIFO_CTRL */
170#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 171#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 172
173/* PLA_FMC */
174#define FMC_FCR_MCU_EN 0x0001
175
176/* PLA_EEEP_CR */
177#define EEEP_CR_EEEP_TX 0x0002
178
43779f8d 179/* PLA_WDT6_CTRL */
180#define WDT6_SET_MODE 0x0010
181
ac718b69 182/* PLA_TCR0 */
183#define TCR0_TX_EMPTY 0x0800
184#define TCR0_AUTO_FIFO 0x0080
185
186/* PLA_TCR1 */
187#define VERSION_MASK 0x7cf0
188
69b4b7a4 189/* PLA_MTPS */
190#define MTPS_JUMBO (12 * 1024 / 64)
191#define MTPS_DEFAULT (6 * 1024 / 64)
192
4f1d4d54 193/* PLA_RSTTALLY */
194#define TALLY_RESET 0x0001
195
ac718b69 196/* PLA_CR */
197#define CR_RST 0x10
198#define CR_RE 0x08
199#define CR_TE 0x04
200
201/* PLA_CRWECR */
202#define CRWECR_NORAML 0x00
203#define CRWECR_CONFIG 0xc0
204
205/* PLA_OOB_CTRL */
206#define NOW_IS_OOB 0x80
207#define TXFIFO_EMPTY 0x20
208#define RXFIFO_EMPTY 0x10
209#define LINK_LIST_READY 0x02
210#define DIS_MCU_CLROOB 0x01
211#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
212
213/* PLA_MISC_1 */
214#define RXDY_GATED_EN 0x0008
215
216/* PLA_SFF_STS_7 */
217#define RE_INIT_LL 0x8000
218#define MCU_BORW_EN 0x4000
219
220/* PLA_CPCR */
221#define CPCR_RX_VLAN 0x0040
222
223/* PLA_CFG_WOL */
224#define MAGIC_EN 0x0001
225
43779f8d 226/* PLA_TEREDO_CFG */
227#define TEREDO_SEL 0x8000
228#define TEREDO_WAKE_MASK 0x7f00
229#define TEREDO_RS_EVENT_MASK 0x00fe
230#define OOB_TEREDO_EN 0x0001
231
ac718b69 232/* PAL_BDC_CR */
233#define ALDPS_PROXY_MODE 0x0001
234
21ff2e89 235/* PLA_CONFIG34 */
236#define LINK_ON_WAKE_EN 0x0010
237#define LINK_OFF_WAKE_EN 0x0008
238
ac718b69 239/* PLA_CONFIG5 */
21ff2e89 240#define BWF_EN 0x0040
241#define MWF_EN 0x0020
242#define UWF_EN 0x0010
ac718b69 243#define LAN_WAKE_EN 0x0002
244
245/* PLA_LED_FEATURE */
246#define LED_MODE_MASK 0x0700
247
248/* PLA_PHY_PWR */
249#define TX_10M_IDLE_EN 0x0080
250#define PFM_PWM_SWITCH 0x0040
251
252/* PLA_MAC_PWR_CTRL */
253#define D3_CLK_GATED_EN 0x00004000
254#define MCU_CLK_RATIO 0x07010f07
255#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 256#define ALDPS_SPDWN_RATIO 0x0f87
257
258/* PLA_MAC_PWR_CTRL2 */
259#define EEE_SPDWN_RATIO 0x8007
260
261/* PLA_MAC_PWR_CTRL3 */
262#define PKT_AVAIL_SPDWN_EN 0x0100
263#define SUSPEND_SPDWN_EN 0x0004
264#define U1U2_SPDWN_EN 0x0002
265#define L1_SPDWN_EN 0x0001
266
267/* PLA_MAC_PWR_CTRL4 */
268#define PWRSAVE_SPDWN_EN 0x1000
269#define RXDV_SPDWN_EN 0x0800
270#define TX10MIDLE_EN 0x0100
271#define TP100_SPDWN_EN 0x0020
272#define TP500_SPDWN_EN 0x0010
273#define TP1000_SPDWN_EN 0x0008
274#define EEE_SPDWN_EN 0x0001
ac718b69 275
276/* PLA_GPHY_INTR_IMR */
277#define GPHY_STS_MSK 0x0001
278#define SPEED_DOWN_MSK 0x0002
279#define SPDWN_RXDV_MSK 0x0004
280#define SPDWN_LINKCHG_MSK 0x0008
281
282/* PLA_PHYAR */
283#define PHYAR_FLAG 0x80000000
284
285/* PLA_EEE_CR */
286#define EEE_RX_EN 0x0001
287#define EEE_TX_EN 0x0002
288
43779f8d 289/* PLA_BOOT_CTRL */
290#define AUTOLOAD_DONE 0x0002
291
ac718b69 292/* USB_DEV_STAT */
293#define STAT_SPEED_MASK 0x0006
294#define STAT_SPEED_HIGH 0x0000
a3cc465d 295#define STAT_SPEED_FULL 0x0002
ac718b69 296
297/* USB_TX_AGG */
298#define TX_AGG_MAX_THRESHOLD 0x03
299
300/* USB_RX_BUF_TH */
43779f8d 301#define RX_THR_SUPPER 0x0c350180
8e1f51bd 302#define RX_THR_HIGH 0x7a120180
43779f8d 303#define RX_THR_SLOW 0xffff0180
ac718b69 304
305/* USB_TX_DMA */
306#define TEST_MODE_DISABLE 0x00000001
307#define TX_SIZE_ADJUST1 0x00000100
308
309/* USB_UPS_CTRL */
310#define POWER_CUT 0x0100
311
312/* USB_PM_CTRL_STATUS */
8e1f51bd 313#define RESUME_INDICATE 0x0001
ac718b69 314
315/* USB_USB_CTRL */
316#define RX_AGG_DISABLE 0x0010
317
43779f8d 318/* USB_U2P3_CTRL */
319#define U2P3_ENABLE 0x0001
320
321/* USB_POWER_CUT */
322#define PWR_EN 0x0001
323#define PHASE2_EN 0x0008
324
325/* USB_MISC_0 */
326#define PCUT_STATUS 0x0001
327
328/* USB_RX_EARLY_AGG */
329#define EARLY_AGG_SUPPER 0x0e832981
330#define EARLY_AGG_HIGH 0x0e837a12
331#define EARLY_AGG_SLOW 0x0e83ffff
332
333/* USB_WDT11_CTRL */
334#define TIMER11_EN 0x0001
335
336/* USB_LPM_CTRL */
337#define LPM_TIMER_MASK 0x0c
338#define LPM_TIMER_500MS 0x04 /* 500 ms */
339#define LPM_TIMER_500US 0x0c /* 500 us */
340
341/* USB_AFE_CTRL2 */
342#define SEN_VAL_MASK 0xf800
343#define SEN_VAL_NORMAL 0xa000
344#define SEL_RXIDLE 0x0100
345
ac718b69 346/* OCP_ALDPS_CONFIG */
347#define ENPWRSAVE 0x8000
348#define ENPDNPS 0x0200
349#define LINKENA 0x0100
350#define DIS_SDSAVE 0x0010
351
43779f8d 352/* OCP_PHY_STATUS */
353#define PHY_STAT_MASK 0x0007
354#define PHY_STAT_LAN_ON 3
355#define PHY_STAT_PWRDN 5
356
357/* OCP_POWER_CFG */
358#define EEE_CLKDIV_EN 0x8000
359#define EN_ALDPS 0x0004
360#define EN_10M_PLLOFF 0x0001
361
ac718b69 362/* OCP_EEE_CONFIG1 */
363#define RG_TXLPI_MSK_HFDUP 0x8000
364#define RG_MATCLR_EN 0x4000
365#define EEE_10_CAP 0x2000
366#define EEE_NWAY_EN 0x1000
367#define TX_QUIET_EN 0x0200
368#define RX_QUIET_EN 0x0100
d24f6134 369#define sd_rise_time_mask 0x0070
4c4a6b1b 370#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 371#define RG_RXLPI_MSK_HFDUP 0x0008
372#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
373
374/* OCP_EEE_CONFIG2 */
375#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
376#define RG_DACQUIET_EN 0x0400
377#define RG_LDVQUIET_EN 0x0200
378#define RG_CKRSEL 0x0020
379#define RG_EEEPRG_EN 0x0010
380
381/* OCP_EEE_CONFIG3 */
d24f6134 382#define fast_snr_mask 0xff80
4c4a6b1b 383#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 384#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
385#define MSK_PH 0x0006 /* bit 0 ~ 3 */
386
387/* OCP_EEE_AR */
388/* bit[15:14] function */
389#define FUN_ADDR 0x0000
390#define FUN_DATA 0x4000
391/* bit[4:0] device addr */
ac718b69 392
43779f8d 393/* OCP_EEE_CFG */
394#define CTAP_SHORT_EN 0x0040
395#define EEE10_EN 0x0010
396
397/* OCP_DOWN_SPEED */
398#define EN_10M_BGOFF 0x0080
399
43779f8d 400/* OCP_ADC_CFG */
401#define CKADSEL_L 0x0100
402#define ADC_EN 0x0080
403#define EN_EMI_L 0x0040
404
405/* SRAM_LPF_CFG */
406#define LPF_AUTO_TUNE 0x8000
407
408/* SRAM_10M_AMP1 */
409#define GDAC_IB_UPALL 0x0008
410
411/* SRAM_10M_AMP2 */
412#define AMP_DN 0x0200
413
414/* SRAM_IMPEDANCE */
415#define RX_DRIVING_MASK 0x6000
416
ac718b69 417enum rtl_register_content {
43779f8d 418 _1000bps = 0x10,
ac718b69 419 _100bps = 0x08,
420 _10bps = 0x04,
421 LINK_STATUS = 0x02,
422 FULL_DUP = 0x01,
423};
424
1764bcd9 425#define RTL8152_MAX_TX 4
ebc2ec48 426#define RTL8152_MAX_RX 10
40a82917 427#define INTBUFSIZE 2
8e1f51bd 428#define CRC_SIZE 4
429#define TX_ALIGN 4
430#define RX_ALIGN 8
40a82917 431
432#define INTR_LINK 0x0004
ebc2ec48 433
ac718b69 434#define RTL8152_REQT_READ 0xc0
435#define RTL8152_REQT_WRITE 0x40
436#define RTL8152_REQ_GET_REGS 0x05
437#define RTL8152_REQ_SET_REGS 0x05
438
439#define BYTE_EN_DWORD 0xff
440#define BYTE_EN_WORD 0x33
441#define BYTE_EN_BYTE 0x11
442#define BYTE_EN_SIX_BYTES 0x3f
443#define BYTE_EN_START_MASK 0x0f
444#define BYTE_EN_END_MASK 0xf0
445
69b4b7a4 446#define RTL8153_MAX_PACKET 9216 /* 9K */
447#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 448#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 449#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 450#define RTL8152_TX_TIMEOUT (5 * HZ)
d823ab68 451#define RTL8152_NAPI_WEIGHT 64
ac718b69 452
453/* rtl8152 flags */
454enum rtl8152_flags {
455 RTL8152_UNPLUG = 0,
ac718b69 456 RTL8152_SET_RX_MODE,
40a82917 457 WORK_ENABLE,
458 RTL8152_LINK_CHG,
9a4be1bd 459 SELECTIVE_SUSPEND,
aa66a5f1 460 PHY_RESET,
d823ab68 461 SCHEDULE_NAPI,
ac718b69 462};
463
464/* Define these values to match your device */
465#define VENDOR_ID_REALTEK 0x0bda
43779f8d 466#define VENDOR_ID_SAMSUNG 0x04e8
ac718b69 467
468#define MCU_TYPE_PLA 0x0100
469#define MCU_TYPE_USB 0x0000
470
4f1d4d54 471struct tally_counter {
472 __le64 tx_packets;
473 __le64 rx_packets;
474 __le64 tx_errors;
475 __le32 rx_errors;
476 __le16 rx_missed;
477 __le16 align_errors;
478 __le32 tx_one_collision;
479 __le32 tx_multi_collision;
480 __le64 rx_unicast;
481 __le64 rx_broadcast;
482 __le32 rx_multicast;
483 __le16 tx_aborted;
f37119c5 484 __le16 tx_underrun;
4f1d4d54 485};
486
ac718b69 487struct rx_desc {
500b6d7e 488 __le32 opts1;
ac718b69 489#define RX_LEN_MASK 0x7fff
565cab0a 490
500b6d7e 491 __le32 opts2;
565cab0a 492#define RD_UDP_CS (1 << 23)
493#define RD_TCP_CS (1 << 22)
6128d1bb 494#define RD_IPV6_CS (1 << 20)
565cab0a 495#define RD_IPV4_CS (1 << 19)
496
500b6d7e 497 __le32 opts3;
565cab0a 498#define IPF (1 << 23) /* IP checksum fail */
499#define UDPF (1 << 22) /* UDP checksum fail */
500#define TCPF (1 << 21) /* TCP checksum fail */
c5554298 501#define RX_VLAN_TAG (1 << 16)
565cab0a 502
500b6d7e 503 __le32 opts4;
504 __le32 opts5;
505 __le32 opts6;
ac718b69 506};
507
508struct tx_desc {
500b6d7e 509 __le32 opts1;
ac718b69 510#define TX_FS (1 << 31) /* First segment of a packet */
511#define TX_LS (1 << 30) /* Final segment of a packet */
60c89071 512#define GTSENDV4 (1 << 28)
6128d1bb 513#define GTSENDV6 (1 << 27)
60c89071 514#define GTTCPHO_SHIFT 18
6128d1bb 515#define GTTCPHO_MAX 0x7fU
60c89071 516#define TX_LEN_MAX 0x3ffffU
5bd23881 517
500b6d7e 518 __le32 opts2;
5bd23881 519#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
520#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
521#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
522#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
60c89071 523#define MSS_SHIFT 17
524#define MSS_MAX 0x7ffU
525#define TCPHO_SHIFT 17
6128d1bb 526#define TCPHO_MAX 0x7ffU
c5554298 527#define TX_VLAN_TAG (1 << 16)
ac718b69 528};
529
dff4e8ad 530struct r8152;
531
ebc2ec48 532struct rx_agg {
533 struct list_head list;
534 struct urb *urb;
dff4e8ad 535 struct r8152 *context;
ebc2ec48 536 void *buffer;
537 void *head;
538};
539
540struct tx_agg {
541 struct list_head list;
542 struct urb *urb;
dff4e8ad 543 struct r8152 *context;
ebc2ec48 544 void *buffer;
545 void *head;
546 u32 skb_num;
547 u32 skb_len;
548};
549
ac718b69 550struct r8152 {
551 unsigned long flags;
552 struct usb_device *udev;
d823ab68 553 struct napi_struct napi;
40a82917 554 struct usb_interface *intf;
ac718b69 555 struct net_device *netdev;
40a82917 556 struct urb *intr_urb;
ebc2ec48 557 struct tx_agg tx_info[RTL8152_MAX_TX];
558 struct rx_agg rx_info[RTL8152_MAX_RX];
559 struct list_head rx_done, tx_free;
d823ab68 560 struct sk_buff_head tx_queue, rx_queue;
ebc2ec48 561 spinlock_t rx_lock, tx_lock;
ac718b69 562 struct delayed_work schedule;
563 struct mii_if_info mii;
b5403273 564 struct mutex control; /* use for hw setting */
c81229c9 565
566 struct rtl_ops {
567 void (*init)(struct r8152 *);
568 int (*enable)(struct r8152 *);
569 void (*disable)(struct r8152 *);
7e9da481 570 void (*up)(struct r8152 *);
c81229c9 571 void (*down)(struct r8152 *);
572 void (*unload)(struct r8152 *);
df35d283 573 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
574 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
c81229c9 575 } rtl_ops;
576
40a82917 577 int intr_interval;
21ff2e89 578 u32 saved_wolopts;
ac718b69 579 u32 msg_enable;
dd1b119c 580 u32 tx_qlen;
ac718b69 581 u16 ocp_base;
40a82917 582 u8 *intr_buff;
ac718b69 583 u8 version;
584 u8 speed;
585};
586
587enum rtl_version {
588 RTL_VER_UNKNOWN = 0,
589 RTL_VER_01,
43779f8d 590 RTL_VER_02,
591 RTL_VER_03,
592 RTL_VER_04,
593 RTL_VER_05,
594 RTL_VER_MAX
ac718b69 595};
596
60c89071 597enum tx_csum_stat {
598 TX_CSUM_SUCCESS = 0,
599 TX_CSUM_TSO,
600 TX_CSUM_NONE
601};
602
ac718b69 603/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
604 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
605 */
606static const int multicast_filter_limit = 32;
52aec126 607static unsigned int agg_buf_sz = 16384;
ac718b69 608
52aec126 609#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 610 VLAN_ETH_HLEN - VLAN_HLEN)
611
ac718b69 612static
613int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
614{
31787f53 615 int ret;
616 void *tmp;
617
618 tmp = kmalloc(size, GFP_KERNEL);
619 if (!tmp)
620 return -ENOMEM;
621
622 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 623 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
624 value, index, tmp, size, 500);
31787f53 625
626 memcpy(data, tmp, size);
627 kfree(tmp);
628
629 return ret;
ac718b69 630}
631
632static
633int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
634{
31787f53 635 int ret;
636 void *tmp;
637
c4438f03 638 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 639 if (!tmp)
640 return -ENOMEM;
641
31787f53 642 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 643 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
644 value, index, tmp, size, 500);
31787f53 645
646 kfree(tmp);
db8515ef 647
31787f53 648 return ret;
ac718b69 649}
650
651static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 652 void *data, u16 type)
ac718b69 653{
45f4a19f 654 u16 limit = 64;
655 int ret = 0;
ac718b69 656
657 if (test_bit(RTL8152_UNPLUG, &tp->flags))
658 return -ENODEV;
659
660 /* both size and indix must be 4 bytes align */
661 if ((size & 3) || !size || (index & 3) || !data)
662 return -EPERM;
663
664 if ((u32)index + (u32)size > 0xffff)
665 return -EPERM;
666
667 while (size) {
668 if (size > limit) {
669 ret = get_registers(tp, index, type, limit, data);
670 if (ret < 0)
671 break;
672
673 index += limit;
674 data += limit;
675 size -= limit;
676 } else {
677 ret = get_registers(tp, index, type, size, data);
678 if (ret < 0)
679 break;
680
681 index += size;
682 data += size;
683 size = 0;
684 break;
685 }
686 }
687
67610496 688 if (ret == -ENODEV)
689 set_bit(RTL8152_UNPLUG, &tp->flags);
690
ac718b69 691 return ret;
692}
693
694static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 695 u16 size, void *data, u16 type)
ac718b69 696{
45f4a19f 697 int ret;
698 u16 byteen_start, byteen_end, byen;
699 u16 limit = 512;
ac718b69 700
701 if (test_bit(RTL8152_UNPLUG, &tp->flags))
702 return -ENODEV;
703
704 /* both size and indix must be 4 bytes align */
705 if ((size & 3) || !size || (index & 3) || !data)
706 return -EPERM;
707
708 if ((u32)index + (u32)size > 0xffff)
709 return -EPERM;
710
711 byteen_start = byteen & BYTE_EN_START_MASK;
712 byteen_end = byteen & BYTE_EN_END_MASK;
713
714 byen = byteen_start | (byteen_start << 4);
715 ret = set_registers(tp, index, type | byen, 4, data);
716 if (ret < 0)
717 goto error1;
718
719 index += 4;
720 data += 4;
721 size -= 4;
722
723 if (size) {
724 size -= 4;
725
726 while (size) {
727 if (size > limit) {
728 ret = set_registers(tp, index,
b209af99 729 type | BYTE_EN_DWORD,
730 limit, data);
ac718b69 731 if (ret < 0)
732 goto error1;
733
734 index += limit;
735 data += limit;
736 size -= limit;
737 } else {
738 ret = set_registers(tp, index,
b209af99 739 type | BYTE_EN_DWORD,
740 size, data);
ac718b69 741 if (ret < 0)
742 goto error1;
743
744 index += size;
745 data += size;
746 size = 0;
747 break;
748 }
749 }
750
751 byen = byteen_end | (byteen_end >> 4);
752 ret = set_registers(tp, index, type | byen, 4, data);
753 if (ret < 0)
754 goto error1;
755 }
756
757error1:
67610496 758 if (ret == -ENODEV)
759 set_bit(RTL8152_UNPLUG, &tp->flags);
760
ac718b69 761 return ret;
762}
763
764static inline
765int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
766{
767 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
768}
769
770static inline
771int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
772{
773 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
774}
775
776static inline
777int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
778{
779 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
780}
781
782static inline
783int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
784{
785 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
786}
787
788static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
789{
c8826de8 790 __le32 data;
ac718b69 791
c8826de8 792 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 793
794 return __le32_to_cpu(data);
795}
796
797static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
798{
c8826de8 799 __le32 tmp = __cpu_to_le32(data);
800
801 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 802}
803
804static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
805{
806 u32 data;
c8826de8 807 __le32 tmp;
ac718b69 808 u8 shift = index & 2;
809
810 index &= ~3;
811
c8826de8 812 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 813
c8826de8 814 data = __le32_to_cpu(tmp);
ac718b69 815 data >>= (shift * 8);
816 data &= 0xffff;
817
818 return (u16)data;
819}
820
821static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
822{
c8826de8 823 u32 mask = 0xffff;
824 __le32 tmp;
ac718b69 825 u16 byen = BYTE_EN_WORD;
826 u8 shift = index & 2;
827
828 data &= mask;
829
830 if (index & 2) {
831 byen <<= shift;
832 mask <<= (shift * 8);
833 data <<= (shift * 8);
834 index &= ~3;
835 }
836
c8826de8 837 tmp = __cpu_to_le32(data);
ac718b69 838
c8826de8 839 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 840}
841
842static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
843{
844 u32 data;
c8826de8 845 __le32 tmp;
ac718b69 846 u8 shift = index & 3;
847
848 index &= ~3;
849
c8826de8 850 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 851
c8826de8 852 data = __le32_to_cpu(tmp);
ac718b69 853 data >>= (shift * 8);
854 data &= 0xff;
855
856 return (u8)data;
857}
858
859static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
860{
c8826de8 861 u32 mask = 0xff;
862 __le32 tmp;
ac718b69 863 u16 byen = BYTE_EN_BYTE;
864 u8 shift = index & 3;
865
866 data &= mask;
867
868 if (index & 3) {
869 byen <<= shift;
870 mask <<= (shift * 8);
871 data <<= (shift * 8);
872 index &= ~3;
873 }
874
c8826de8 875 tmp = __cpu_to_le32(data);
ac718b69 876
c8826de8 877 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 878}
879
ac244d3e 880static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 881{
882 u16 ocp_base, ocp_index;
883
884 ocp_base = addr & 0xf000;
885 if (ocp_base != tp->ocp_base) {
886 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
887 tp->ocp_base = ocp_base;
888 }
889
890 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 891 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 892}
893
ac244d3e 894static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 895{
ac244d3e 896 u16 ocp_base, ocp_index;
ac718b69 897
ac244d3e 898 ocp_base = addr & 0xf000;
899 if (ocp_base != tp->ocp_base) {
900 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
901 tp->ocp_base = ocp_base;
ac718b69 902 }
ac244d3e 903
904 ocp_index = (addr & 0x0fff) | 0xb000;
905 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 906}
907
ac244d3e 908static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 909{
ac244d3e 910 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
911}
ac718b69 912
ac244d3e 913static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
914{
915 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 916}
917
43779f8d 918static void sram_write(struct r8152 *tp, u16 addr, u16 data)
919{
920 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
921 ocp_reg_write(tp, OCP_SRAM_DATA, data);
922}
923
ac718b69 924static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
925{
926 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 927 int ret;
ac718b69 928
6871438c 929 if (test_bit(RTL8152_UNPLUG, &tp->flags))
930 return -ENODEV;
931
ac718b69 932 if (phy_id != R8152_PHY_ID)
933 return -EINVAL;
934
9a4be1bd 935 ret = r8152_mdio_read(tp, reg);
936
9a4be1bd 937 return ret;
ac718b69 938}
939
940static
941void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
942{
943 struct r8152 *tp = netdev_priv(netdev);
944
6871438c 945 if (test_bit(RTL8152_UNPLUG, &tp->flags))
946 return;
947
ac718b69 948 if (phy_id != R8152_PHY_ID)
949 return;
950
951 r8152_mdio_write(tp, reg, val);
952}
953
b209af99 954static int
955r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 956
8ba789ab 957static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
958{
959 struct r8152 *tp = netdev_priv(netdev);
960 struct sockaddr *addr = p;
ea6a7112 961 int ret = -EADDRNOTAVAIL;
8ba789ab 962
963 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 964 goto out1;
965
966 ret = usb_autopm_get_interface(tp->intf);
967 if (ret < 0)
968 goto out1;
8ba789ab 969
b5403273 970 mutex_lock(&tp->control);
971
8ba789ab 972 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
973
974 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
975 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
976 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
977
b5403273 978 mutex_unlock(&tp->control);
979
ea6a7112 980 usb_autopm_put_interface(tp->intf);
981out1:
982 return ret;
8ba789ab 983}
984
179bb6d7 985static int set_ethernet_addr(struct r8152 *tp)
ac718b69 986{
987 struct net_device *dev = tp->netdev;
179bb6d7 988 struct sockaddr sa;
8a91c824 989 int ret;
ac718b69 990
8a91c824 991 if (tp->version == RTL_VER_01)
179bb6d7 992 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
8a91c824 993 else
179bb6d7 994 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
8a91c824 995
996 if (ret < 0) {
179bb6d7 997 netif_err(tp, probe, dev, "Get ether addr fail\n");
998 } else if (!is_valid_ether_addr(sa.sa_data)) {
999 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1000 sa.sa_data);
1001 eth_hw_addr_random(dev);
1002 ether_addr_copy(sa.sa_data, dev->dev_addr);
1003 ret = rtl8152_set_mac_address(dev, &sa);
1004 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1005 sa.sa_data);
8a91c824 1006 } else {
179bb6d7 1007 if (tp->version == RTL_VER_01)
1008 ether_addr_copy(dev->dev_addr, sa.sa_data);
1009 else
1010 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1011 }
179bb6d7 1012
1013 return ret;
ac718b69 1014}
1015
ac718b69 1016static void read_bulk_callback(struct urb *urb)
1017{
ac718b69 1018 struct net_device *netdev;
ac718b69 1019 int status = urb->status;
ebc2ec48 1020 struct rx_agg *agg;
1021 struct r8152 *tp;
ac718b69 1022
ebc2ec48 1023 agg = urb->context;
1024 if (!agg)
1025 return;
1026
1027 tp = agg->context;
ac718b69 1028 if (!tp)
1029 return;
ebc2ec48 1030
ac718b69 1031 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1032 return;
ebc2ec48 1033
1034 if (!test_bit(WORK_ENABLE, &tp->flags))
1035 return;
1036
ac718b69 1037 netdev = tp->netdev;
7559fb2f 1038
1039 /* When link down, the driver would cancel all bulks. */
1040 /* This avoid the re-submitting bulk */
ebc2ec48 1041 if (!netif_carrier_ok(netdev))
ac718b69 1042 return;
1043
9a4be1bd 1044 usb_mark_last_busy(tp->udev);
1045
ac718b69 1046 switch (status) {
1047 case 0:
ebc2ec48 1048 if (urb->actual_length < ETH_ZLEN)
1049 break;
1050
2685d410 1051 spin_lock(&tp->rx_lock);
ebc2ec48 1052 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1053 spin_unlock(&tp->rx_lock);
d823ab68 1054 napi_schedule(&tp->napi);
ebc2ec48 1055 return;
ac718b69 1056 case -ESHUTDOWN:
1057 set_bit(RTL8152_UNPLUG, &tp->flags);
1058 netif_device_detach(tp->netdev);
ebc2ec48 1059 return;
ac718b69 1060 case -ENOENT:
1061 return; /* the urb is in unlink state */
1062 case -ETIME:
4a8deae2
HW
1063 if (net_ratelimit())
1064 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1065 break;
ac718b69 1066 default:
4a8deae2
HW
1067 if (net_ratelimit())
1068 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1069 break;
ac718b69 1070 }
1071
a0fccd48 1072 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1073}
1074
ebc2ec48 1075static void write_bulk_callback(struct urb *urb)
ac718b69 1076{
ebc2ec48 1077 struct net_device_stats *stats;
d104eafa 1078 struct net_device *netdev;
ebc2ec48 1079 struct tx_agg *agg;
ac718b69 1080 struct r8152 *tp;
ebc2ec48 1081 int status = urb->status;
ac718b69 1082
ebc2ec48 1083 agg = urb->context;
1084 if (!agg)
ac718b69 1085 return;
1086
ebc2ec48 1087 tp = agg->context;
1088 if (!tp)
1089 return;
1090
d104eafa 1091 netdev = tp->netdev;
05e0f1aa 1092 stats = &netdev->stats;
ebc2ec48 1093 if (status) {
4a8deae2 1094 if (net_ratelimit())
d104eafa 1095 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1096 stats->tx_errors += agg->skb_num;
ac718b69 1097 } else {
ebc2ec48 1098 stats->tx_packets += agg->skb_num;
1099 stats->tx_bytes += agg->skb_len;
ac718b69 1100 }
1101
2685d410 1102 spin_lock(&tp->tx_lock);
ebc2ec48 1103 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1104 spin_unlock(&tp->tx_lock);
ebc2ec48 1105
9a4be1bd 1106 usb_autopm_put_interface_async(tp->intf);
1107
d104eafa 1108 if (!netif_carrier_ok(netdev))
ebc2ec48 1109 return;
1110
1111 if (!test_bit(WORK_ENABLE, &tp->flags))
1112 return;
1113
1114 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1115 return;
1116
1117 if (!skb_queue_empty(&tp->tx_queue))
d823ab68 1118 napi_schedule(&tp->napi);
ac718b69 1119}
1120
40a82917 1121static void intr_callback(struct urb *urb)
1122{
1123 struct r8152 *tp;
500b6d7e 1124 __le16 *d;
40a82917 1125 int status = urb->status;
1126 int res;
1127
1128 tp = urb->context;
1129 if (!tp)
1130 return;
1131
1132 if (!test_bit(WORK_ENABLE, &tp->flags))
1133 return;
1134
1135 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1136 return;
1137
1138 switch (status) {
1139 case 0: /* success */
1140 break;
1141 case -ECONNRESET: /* unlink */
1142 case -ESHUTDOWN:
1143 netif_device_detach(tp->netdev);
1144 case -ENOENT:
d59c876d 1145 case -EPROTO:
1146 netif_info(tp, intr, tp->netdev,
1147 "Stop submitting intr, status %d\n", status);
40a82917 1148 return;
1149 case -EOVERFLOW:
1150 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1151 goto resubmit;
1152 /* -EPIPE: should clear the halt */
1153 default:
1154 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1155 goto resubmit;
1156 }
1157
1158 d = urb->transfer_buffer;
1159 if (INTR_LINK & __le16_to_cpu(d[0])) {
1160 if (!(tp->speed & LINK_STATUS)) {
1161 set_bit(RTL8152_LINK_CHG, &tp->flags);
1162 schedule_delayed_work(&tp->schedule, 0);
1163 }
1164 } else {
1165 if (tp->speed & LINK_STATUS) {
1166 set_bit(RTL8152_LINK_CHG, &tp->flags);
1167 schedule_delayed_work(&tp->schedule, 0);
1168 }
1169 }
1170
1171resubmit:
1172 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1173 if (res == -ENODEV) {
1174 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1175 netif_device_detach(tp->netdev);
67610496 1176 } else if (res) {
40a82917 1177 netif_err(tp, intr, tp->netdev,
4a8deae2 1178 "can't resubmit intr, status %d\n", res);
67610496 1179 }
40a82917 1180}
1181
ebc2ec48 1182static inline void *rx_agg_align(void *data)
1183{
8e1f51bd 1184 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1185}
1186
1187static inline void *tx_agg_align(void *data)
1188{
8e1f51bd 1189 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1190}
1191
1192static void free_all_mem(struct r8152 *tp)
1193{
1194 int i;
1195
1196 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1197 usb_free_urb(tp->rx_info[i].urb);
1198 tp->rx_info[i].urb = NULL;
ebc2ec48 1199
9629e3c0 1200 kfree(tp->rx_info[i].buffer);
1201 tp->rx_info[i].buffer = NULL;
1202 tp->rx_info[i].head = NULL;
ebc2ec48 1203 }
1204
1205 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1206 usb_free_urb(tp->tx_info[i].urb);
1207 tp->tx_info[i].urb = NULL;
ebc2ec48 1208
9629e3c0 1209 kfree(tp->tx_info[i].buffer);
1210 tp->tx_info[i].buffer = NULL;
1211 tp->tx_info[i].head = NULL;
ebc2ec48 1212 }
40a82917 1213
9629e3c0 1214 usb_free_urb(tp->intr_urb);
1215 tp->intr_urb = NULL;
40a82917 1216
9629e3c0 1217 kfree(tp->intr_buff);
1218 tp->intr_buff = NULL;
ebc2ec48 1219}
1220
1221static int alloc_all_mem(struct r8152 *tp)
1222{
1223 struct net_device *netdev = tp->netdev;
40a82917 1224 struct usb_interface *intf = tp->intf;
1225 struct usb_host_interface *alt = intf->cur_altsetting;
1226 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1227 struct urb *urb;
1228 int node, i;
1229 u8 *buf;
1230
1231 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1232
1233 spin_lock_init(&tp->rx_lock);
1234 spin_lock_init(&tp->tx_lock);
ebc2ec48 1235 INIT_LIST_HEAD(&tp->tx_free);
1236 skb_queue_head_init(&tp->tx_queue);
d823ab68 1237 skb_queue_head_init(&tp->rx_queue);
ebc2ec48 1238
1239 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1240 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1241 if (!buf)
1242 goto err1;
1243
1244 if (buf != rx_agg_align(buf)) {
1245 kfree(buf);
52aec126 1246 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1247 node);
ebc2ec48 1248 if (!buf)
1249 goto err1;
1250 }
1251
1252 urb = usb_alloc_urb(0, GFP_KERNEL);
1253 if (!urb) {
1254 kfree(buf);
1255 goto err1;
1256 }
1257
1258 INIT_LIST_HEAD(&tp->rx_info[i].list);
1259 tp->rx_info[i].context = tp;
1260 tp->rx_info[i].urb = urb;
1261 tp->rx_info[i].buffer = buf;
1262 tp->rx_info[i].head = rx_agg_align(buf);
1263 }
1264
1265 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1266 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1267 if (!buf)
1268 goto err1;
1269
1270 if (buf != tx_agg_align(buf)) {
1271 kfree(buf);
52aec126 1272 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1273 node);
ebc2ec48 1274 if (!buf)
1275 goto err1;
1276 }
1277
1278 urb = usb_alloc_urb(0, GFP_KERNEL);
1279 if (!urb) {
1280 kfree(buf);
1281 goto err1;
1282 }
1283
1284 INIT_LIST_HEAD(&tp->tx_info[i].list);
1285 tp->tx_info[i].context = tp;
1286 tp->tx_info[i].urb = urb;
1287 tp->tx_info[i].buffer = buf;
1288 tp->tx_info[i].head = tx_agg_align(buf);
1289
1290 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1291 }
1292
40a82917 1293 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1294 if (!tp->intr_urb)
1295 goto err1;
1296
1297 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1298 if (!tp->intr_buff)
1299 goto err1;
1300
1301 tp->intr_interval = (int)ep_intr->desc.bInterval;
1302 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1303 tp->intr_buff, INTBUFSIZE, intr_callback,
1304 tp, tp->intr_interval);
40a82917 1305
ebc2ec48 1306 return 0;
1307
1308err1:
1309 free_all_mem(tp);
1310 return -ENOMEM;
1311}
1312
0de98f6c 1313static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1314{
1315 struct tx_agg *agg = NULL;
1316 unsigned long flags;
1317
21949ab7 1318 if (list_empty(&tp->tx_free))
1319 return NULL;
1320
0de98f6c 1321 spin_lock_irqsave(&tp->tx_lock, flags);
1322 if (!list_empty(&tp->tx_free)) {
1323 struct list_head *cursor;
1324
1325 cursor = tp->tx_free.next;
1326 list_del_init(cursor);
1327 agg = list_entry(cursor, struct tx_agg, list);
1328 }
1329 spin_unlock_irqrestore(&tp->tx_lock, flags);
1330
1331 return agg;
1332}
1333
60c89071 1334static inline __be16 get_protocol(struct sk_buff *skb)
5bd23881 1335{
60c89071 1336 __be16 protocol;
5bd23881 1337
60c89071 1338 if (skb->protocol == htons(ETH_P_8021Q))
1339 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1340 else
1341 protocol = skb->protocol;
5bd23881 1342
60c89071 1343 return protocol;
1344}
5bd23881 1345
b209af99 1346/* r8152_csum_workaround()
6128d1bb 1347 * The hw limites the value the transport offset. When the offset is out of the
1348 * range, calculate the checksum by sw.
1349 */
1350static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1351 struct sk_buff_head *list)
1352{
1353 if (skb_shinfo(skb)->gso_size) {
1354 netdev_features_t features = tp->netdev->features;
1355 struct sk_buff_head seg_list;
1356 struct sk_buff *segs, *nskb;
1357
a91d45f1 1358 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1359 segs = skb_gso_segment(skb, features);
1360 if (IS_ERR(segs) || !segs)
1361 goto drop;
1362
1363 __skb_queue_head_init(&seg_list);
1364
1365 do {
1366 nskb = segs;
1367 segs = segs->next;
1368 nskb->next = NULL;
1369 __skb_queue_tail(&seg_list, nskb);
1370 } while (segs);
1371
1372 skb_queue_splice(&seg_list, list);
1373 dev_kfree_skb(skb);
1374 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1375 if (skb_checksum_help(skb) < 0)
1376 goto drop;
1377
1378 __skb_queue_head(list, skb);
1379 } else {
1380 struct net_device_stats *stats;
1381
1382drop:
1383 stats = &tp->netdev->stats;
1384 stats->tx_dropped++;
1385 dev_kfree_skb(skb);
1386 }
1387}
1388
b209af99 1389/* msdn_giant_send_check()
6128d1bb 1390 * According to the document of microsoft, the TCP Pseudo Header excludes the
1391 * packet length for IPv6 TCP large packets.
1392 */
1393static int msdn_giant_send_check(struct sk_buff *skb)
1394{
1395 const struct ipv6hdr *ipv6h;
1396 struct tcphdr *th;
fcb308d5 1397 int ret;
1398
1399 ret = skb_cow_head(skb, 0);
1400 if (ret)
1401 return ret;
6128d1bb 1402
1403 ipv6h = ipv6_hdr(skb);
1404 th = tcp_hdr(skb);
1405
1406 th->check = 0;
1407 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1408
fcb308d5 1409 return ret;
6128d1bb 1410}
1411
c5554298 1412static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1413{
df8a39de 1414 if (skb_vlan_tag_present(skb)) {
c5554298 1415 u32 opts2;
1416
df8a39de 1417 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
c5554298 1418 desc->opts2 |= cpu_to_le32(opts2);
1419 }
1420}
1421
1422static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1423{
1424 u32 opts2 = le32_to_cpu(desc->opts2);
1425
1426 if (opts2 & RX_VLAN_TAG)
1427 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1428 swab16(opts2 & 0xffff));
1429}
1430
60c89071 1431static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1432 struct sk_buff *skb, u32 len, u32 transport_offset)
1433{
1434 u32 mss = skb_shinfo(skb)->gso_size;
1435 u32 opts1, opts2 = 0;
1436 int ret = TX_CSUM_SUCCESS;
1437
1438 WARN_ON_ONCE(len > TX_LEN_MAX);
1439
1440 opts1 = len | TX_FS | TX_LS;
1441
1442 if (mss) {
6128d1bb 1443 if (transport_offset > GTTCPHO_MAX) {
1444 netif_warn(tp, tx_err, tp->netdev,
1445 "Invalid transport offset 0x%x for TSO\n",
1446 transport_offset);
1447 ret = TX_CSUM_TSO;
1448 goto unavailable;
1449 }
1450
60c89071 1451 switch (get_protocol(skb)) {
1452 case htons(ETH_P_IP):
1453 opts1 |= GTSENDV4;
1454 break;
1455
6128d1bb 1456 case htons(ETH_P_IPV6):
fcb308d5 1457 if (msdn_giant_send_check(skb)) {
1458 ret = TX_CSUM_TSO;
1459 goto unavailable;
1460 }
6128d1bb 1461 opts1 |= GTSENDV6;
6128d1bb 1462 break;
1463
60c89071 1464 default:
1465 WARN_ON_ONCE(1);
1466 break;
1467 }
1468
1469 opts1 |= transport_offset << GTTCPHO_SHIFT;
1470 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1471 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1472 u8 ip_protocol;
5bd23881 1473
6128d1bb 1474 if (transport_offset > TCPHO_MAX) {
1475 netif_warn(tp, tx_err, tp->netdev,
1476 "Invalid transport offset 0x%x\n",
1477 transport_offset);
1478 ret = TX_CSUM_NONE;
1479 goto unavailable;
1480 }
1481
60c89071 1482 switch (get_protocol(skb)) {
5bd23881 1483 case htons(ETH_P_IP):
1484 opts2 |= IPV4_CS;
1485 ip_protocol = ip_hdr(skb)->protocol;
1486 break;
1487
1488 case htons(ETH_P_IPV6):
1489 opts2 |= IPV6_CS;
1490 ip_protocol = ipv6_hdr(skb)->nexthdr;
1491 break;
1492
1493 default:
1494 ip_protocol = IPPROTO_RAW;
1495 break;
1496 }
1497
60c89071 1498 if (ip_protocol == IPPROTO_TCP)
5bd23881 1499 opts2 |= TCP_CS;
60c89071 1500 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1501 opts2 |= UDP_CS;
60c89071 1502 else
5bd23881 1503 WARN_ON_ONCE(1);
5bd23881 1504
60c89071 1505 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1506 }
60c89071 1507
1508 desc->opts2 = cpu_to_le32(opts2);
1509 desc->opts1 = cpu_to_le32(opts1);
1510
6128d1bb 1511unavailable:
60c89071 1512 return ret;
5bd23881 1513}
1514
b1379d9a 1515static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1516{
d84130a1 1517 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1518 int remain, ret;
b1379d9a 1519 u8 *tx_data;
1520
d84130a1 1521 __skb_queue_head_init(&skb_head);
0c3121fc 1522 spin_lock(&tx_queue->lock);
d84130a1 1523 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1524 spin_unlock(&tx_queue->lock);
d84130a1 1525
b1379d9a 1526 tx_data = agg->head;
b209af99 1527 agg->skb_num = 0;
1528 agg->skb_len = 0;
52aec126 1529 remain = agg_buf_sz;
b1379d9a 1530
7937f9e5 1531 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1532 struct tx_desc *tx_desc;
1533 struct sk_buff *skb;
1534 unsigned int len;
60c89071 1535 u32 offset;
b1379d9a 1536
d84130a1 1537 skb = __skb_dequeue(&skb_head);
b1379d9a 1538 if (!skb)
1539 break;
1540
60c89071 1541 len = skb->len + sizeof(*tx_desc);
1542
1543 if (len > remain) {
d84130a1 1544 __skb_queue_head(&skb_head, skb);
b1379d9a 1545 break;
1546 }
1547
7937f9e5 1548 tx_data = tx_agg_align(tx_data);
b1379d9a 1549 tx_desc = (struct tx_desc *)tx_data;
60c89071 1550
1551 offset = (u32)skb_transport_offset(skb);
1552
6128d1bb 1553 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1554 r8152_csum_workaround(tp, skb, &skb_head);
1555 continue;
1556 }
60c89071 1557
c5554298 1558 rtl_tx_vlan_tag(tx_desc, skb);
1559
b1379d9a 1560 tx_data += sizeof(*tx_desc);
1561
60c89071 1562 len = skb->len;
1563 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1564 struct net_device_stats *stats = &tp->netdev->stats;
1565
1566 stats->tx_dropped++;
1567 dev_kfree_skb_any(skb);
1568 tx_data -= sizeof(*tx_desc);
1569 continue;
1570 }
1571
1572 tx_data += len;
b1379d9a 1573 agg->skb_len += len;
60c89071 1574 agg->skb_num++;
1575
b1379d9a 1576 dev_kfree_skb_any(skb);
1577
52aec126 1578 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1579 }
1580
d84130a1 1581 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1582 spin_lock(&tx_queue->lock);
d84130a1 1583 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1584 spin_unlock(&tx_queue->lock);
d84130a1 1585 }
1586
0c3121fc 1587 netif_tx_lock(tp->netdev);
dd1b119c 1588
1589 if (netif_queue_stopped(tp->netdev) &&
1590 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1591 netif_wake_queue(tp->netdev);
1592
0c3121fc 1593 netif_tx_unlock(tp->netdev);
9a4be1bd 1594
0c3121fc 1595 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1596 if (ret < 0)
1597 goto out_tx_fill;
dd1b119c 1598
b1379d9a 1599 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1600 agg->head, (int)(tx_data - (u8 *)agg->head),
1601 (usb_complete_t)write_bulk_callback, agg);
1602
0c3121fc 1603 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1604 if (ret < 0)
0c3121fc 1605 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1606
1607out_tx_fill:
1608 return ret;
b1379d9a 1609}
1610
565cab0a 1611static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1612{
1613 u8 checksum = CHECKSUM_NONE;
1614 u32 opts2, opts3;
1615
1616 if (tp->version == RTL_VER_01)
1617 goto return_result;
1618
1619 opts2 = le32_to_cpu(rx_desc->opts2);
1620 opts3 = le32_to_cpu(rx_desc->opts3);
1621
1622 if (opts2 & RD_IPV4_CS) {
1623 if (opts3 & IPF)
1624 checksum = CHECKSUM_NONE;
1625 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1626 checksum = CHECKSUM_NONE;
1627 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1628 checksum = CHECKSUM_NONE;
1629 else
1630 checksum = CHECKSUM_UNNECESSARY;
6128d1bb 1631 } else if (RD_IPV6_CS) {
1632 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1633 checksum = CHECKSUM_UNNECESSARY;
1634 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1635 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1636 }
1637
1638return_result:
1639 return checksum;
1640}
1641
d823ab68 1642static int rx_bottom(struct r8152 *tp, int budget)
ebc2ec48 1643{
a5a4f468 1644 unsigned long flags;
d84130a1 1645 struct list_head *cursor, *next, rx_queue;
d823ab68 1646 int work_done = 0;
1647
1648 if (!skb_queue_empty(&tp->rx_queue)) {
1649 while (work_done < budget) {
1650 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1651 struct net_device *netdev = tp->netdev;
1652 struct net_device_stats *stats = &netdev->stats;
1653 unsigned int pkt_len;
1654
1655 if (!skb)
1656 break;
1657
1658 pkt_len = skb->len;
1659 napi_gro_receive(&tp->napi, skb);
1660 work_done++;
1661 stats->rx_packets++;
1662 stats->rx_bytes += pkt_len;
1663 }
1664 }
ebc2ec48 1665
d84130a1 1666 if (list_empty(&tp->rx_done))
d823ab68 1667 goto out1;
d84130a1 1668
1669 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1670 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1671 list_splice_init(&tp->rx_done, &rx_queue);
1672 spin_unlock_irqrestore(&tp->rx_lock, flags);
1673
1674 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1675 struct rx_desc *rx_desc;
1676 struct rx_agg *agg;
43a4478d 1677 int len_used = 0;
1678 struct urb *urb;
1679 u8 *rx_data;
43a4478d 1680
ebc2ec48 1681 list_del_init(cursor);
ebc2ec48 1682
1683 agg = list_entry(cursor, struct rx_agg, list);
1684 urb = agg->urb;
0de98f6c 1685 if (urb->actual_length < ETH_ZLEN)
1686 goto submit;
ebc2ec48 1687
ebc2ec48 1688 rx_desc = agg->head;
1689 rx_data = agg->head;
7937f9e5 1690 len_used += sizeof(struct rx_desc);
ebc2ec48 1691
7937f9e5 1692 while (urb->actual_length > len_used) {
43a4478d 1693 struct net_device *netdev = tp->netdev;
05e0f1aa 1694 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1695 unsigned int pkt_len;
43a4478d 1696 struct sk_buff *skb;
1697
7937f9e5 1698 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1699 if (pkt_len < ETH_ZLEN)
1700 break;
1701
7937f9e5 1702 len_used += pkt_len;
1703 if (urb->actual_length < len_used)
1704 break;
1705
8e1f51bd 1706 pkt_len -= CRC_SIZE;
ebc2ec48 1707 rx_data += sizeof(struct rx_desc);
1708
1709 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1710 if (!skb) {
1711 stats->rx_dropped++;
5e2f7485 1712 goto find_next_rx;
ebc2ec48 1713 }
565cab0a 1714
1715 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1716 memcpy(skb->data, rx_data, pkt_len);
1717 skb_put(skb, pkt_len);
1718 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1719 rtl_rx_vlan_tag(rx_desc, skb);
d823ab68 1720 if (work_done < budget) {
1721 napi_gro_receive(&tp->napi, skb);
1722 work_done++;
1723 stats->rx_packets++;
1724 stats->rx_bytes += pkt_len;
1725 } else {
1726 __skb_queue_tail(&tp->rx_queue, skb);
1727 }
ebc2ec48 1728
5e2f7485 1729find_next_rx:
8e1f51bd 1730 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1731 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1732 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1733 len_used += sizeof(struct rx_desc);
ebc2ec48 1734 }
1735
0de98f6c 1736submit:
a0fccd48 1737 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ebc2ec48 1738 }
d823ab68 1739
1740out1:
1741 return work_done;
ebc2ec48 1742}
1743
1744static void tx_bottom(struct r8152 *tp)
1745{
ebc2ec48 1746 int res;
1747
b1379d9a 1748 do {
1749 struct tx_agg *agg;
ebc2ec48 1750
b1379d9a 1751 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1752 break;
1753
b1379d9a 1754 agg = r8152_get_tx_agg(tp);
1755 if (!agg)
ebc2ec48 1756 break;
ebc2ec48 1757
b1379d9a 1758 res = r8152_tx_agg_fill(tp, agg);
1759 if (res) {
05e0f1aa 1760 struct net_device *netdev = tp->netdev;
ebc2ec48 1761
b1379d9a 1762 if (res == -ENODEV) {
67610496 1763 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1764 netif_device_detach(netdev);
1765 } else {
05e0f1aa 1766 struct net_device_stats *stats = &netdev->stats;
1767 unsigned long flags;
1768
b1379d9a 1769 netif_warn(tp, tx_err, netdev,
1770 "failed tx_urb %d\n", res);
1771 stats->tx_dropped += agg->skb_num;
db8515ef 1772
b1379d9a 1773 spin_lock_irqsave(&tp->tx_lock, flags);
1774 list_add_tail(&agg->list, &tp->tx_free);
1775 spin_unlock_irqrestore(&tp->tx_lock, flags);
1776 }
ebc2ec48 1777 }
b1379d9a 1778 } while (res == 0);
ebc2ec48 1779}
1780
d823ab68 1781static void bottom_half(struct r8152 *tp)
ac718b69 1782{
ebc2ec48 1783 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1784 return;
1785
1786 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1787 return;
ebc2ec48 1788
7559fb2f 1789 /* When link down, the driver would cancel all bulks. */
1790 /* This avoid the re-submitting bulk */
ebc2ec48 1791 if (!netif_carrier_ok(tp->netdev))
ac718b69 1792 return;
ebc2ec48 1793
d823ab68 1794 clear_bit(SCHEDULE_NAPI, &tp->flags);
9451a11c 1795
0c3121fc 1796 tx_bottom(tp);
ebc2ec48 1797}
1798
d823ab68 1799static int r8152_poll(struct napi_struct *napi, int budget)
1800{
1801 struct r8152 *tp = container_of(napi, struct r8152, napi);
1802 int work_done;
1803
1804 work_done = rx_bottom(tp, budget);
1805 bottom_half(tp);
1806
1807 if (work_done < budget) {
1808 napi_complete(napi);
1809 if (!list_empty(&tp->rx_done))
1810 napi_schedule(napi);
1811 }
1812
1813 return work_done;
1814}
1815
ebc2ec48 1816static
1817int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1818{
a0fccd48 1819 int ret;
1820
ef827a5b 1821 /* The rx would be stopped, so skip submitting */
1822 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1823 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1824 return 0;
1825
ebc2ec48 1826 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1827 agg->head, agg_buf_sz,
b209af99 1828 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1829
a0fccd48 1830 ret = usb_submit_urb(agg->urb, mem_flags);
1831 if (ret == -ENODEV) {
1832 set_bit(RTL8152_UNPLUG, &tp->flags);
1833 netif_device_detach(tp->netdev);
1834 } else if (ret) {
1835 struct urb *urb = agg->urb;
1836 unsigned long flags;
1837
1838 urb->actual_length = 0;
1839 spin_lock_irqsave(&tp->rx_lock, flags);
1840 list_add_tail(&agg->list, &tp->rx_done);
1841 spin_unlock_irqrestore(&tp->rx_lock, flags);
d823ab68 1842
1843 netif_err(tp, rx_err, tp->netdev,
1844 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1845
1846 napi_schedule(&tp->napi);
a0fccd48 1847 }
1848
1849 return ret;
ac718b69 1850}
1851
00a5e360 1852static void rtl_drop_queued_tx(struct r8152 *tp)
1853{
1854 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1855 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1856 struct sk_buff *skb;
1857
d84130a1 1858 if (skb_queue_empty(tx_queue))
1859 return;
1860
1861 __skb_queue_head_init(&skb_head);
2685d410 1862 spin_lock_bh(&tx_queue->lock);
d84130a1 1863 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1864 spin_unlock_bh(&tx_queue->lock);
d84130a1 1865
1866 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1867 dev_kfree_skb(skb);
1868 stats->tx_dropped++;
1869 }
1870}
1871
ac718b69 1872static void rtl8152_tx_timeout(struct net_device *netdev)
1873{
1874 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1875 int i;
1876
4a8deae2 1877 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
ebc2ec48 1878 for (i = 0; i < RTL8152_MAX_TX; i++)
1879 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1880}
1881
1882static void rtl8152_set_rx_mode(struct net_device *netdev)
1883{
1884 struct r8152 *tp = netdev_priv(netdev);
1885
40a82917 1886 if (tp->speed & LINK_STATUS) {
ac718b69 1887 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1888 schedule_delayed_work(&tp->schedule, 0);
1889 }
ac718b69 1890}
1891
1892static void _rtl8152_set_rx_mode(struct net_device *netdev)
1893{
1894 struct r8152 *tp = netdev_priv(netdev);
31787f53 1895 u32 mc_filter[2]; /* Multicast hash filter */
1896 __le32 tmp[2];
ac718b69 1897 u32 ocp_data;
1898
ac718b69 1899 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1900 netif_stop_queue(netdev);
1901 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1902 ocp_data &= ~RCR_ACPT_ALL;
1903 ocp_data |= RCR_AB | RCR_APM;
1904
1905 if (netdev->flags & IFF_PROMISC) {
1906 /* Unconditionally log net taps. */
1907 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1908 ocp_data |= RCR_AM | RCR_AAP;
b209af99 1909 mc_filter[1] = 0xffffffff;
1910 mc_filter[0] = 0xffffffff;
ac718b69 1911 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1912 (netdev->flags & IFF_ALLMULTI)) {
1913 /* Too many to filter perfectly -- accept all multicasts. */
1914 ocp_data |= RCR_AM;
b209af99 1915 mc_filter[1] = 0xffffffff;
1916 mc_filter[0] = 0xffffffff;
ac718b69 1917 } else {
1918 struct netdev_hw_addr *ha;
1919
b209af99 1920 mc_filter[1] = 0;
1921 mc_filter[0] = 0;
ac718b69 1922 netdev_for_each_mc_addr(ha, netdev) {
1923 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 1924
ac718b69 1925 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1926 ocp_data |= RCR_AM;
1927 }
1928 }
1929
31787f53 1930 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1931 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1932
31787f53 1933 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1934 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1935 netif_wake_queue(netdev);
ac718b69 1936}
1937
a5e31255 1938static netdev_features_t
1939rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1940 netdev_features_t features)
1941{
1942 u32 mss = skb_shinfo(skb)->gso_size;
1943 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1944 int offset = skb_transport_offset(skb);
1945
1946 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1947 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1948 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1949 features &= ~NETIF_F_GSO_MASK;
1950
1951 return features;
1952}
1953
ac718b69 1954static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 1955 struct net_device *netdev)
ac718b69 1956{
1957 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1958
ebc2ec48 1959 skb_tx_timestamp(skb);
ac718b69 1960
61598788 1961 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1962
0c3121fc 1963 if (!list_empty(&tp->tx_free)) {
1964 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
d823ab68 1965 set_bit(SCHEDULE_NAPI, &tp->flags);
0c3121fc 1966 schedule_delayed_work(&tp->schedule, 0);
1967 } else {
1968 usb_mark_last_busy(tp->udev);
d823ab68 1969 napi_schedule(&tp->napi);
0c3121fc 1970 }
b209af99 1971 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 1972 netif_stop_queue(netdev);
b209af99 1973 }
dd1b119c 1974
ac718b69 1975 return NETDEV_TX_OK;
1976}
1977
1978static void r8152b_reset_packet_filter(struct r8152 *tp)
1979{
1980 u32 ocp_data;
1981
1982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1983 ocp_data &= ~FMC_FCR_MCU_EN;
1984 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1985 ocp_data |= FMC_FCR_MCU_EN;
1986 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1987}
1988
1989static void rtl8152_nic_reset(struct r8152 *tp)
1990{
1991 int i;
1992
1993 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1994
1995 for (i = 0; i < 1000; i++) {
1996 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1997 break;
b209af99 1998 usleep_range(100, 400);
ac718b69 1999 }
2000}
2001
dd1b119c 2002static void set_tx_qlen(struct r8152 *tp)
2003{
2004 struct net_device *netdev = tp->netdev;
2005
52aec126 2006 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2007 sizeof(struct tx_desc));
dd1b119c 2008}
2009
ac718b69 2010static inline u8 rtl8152_get_speed(struct r8152 *tp)
2011{
2012 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2013}
2014
507605a8 2015static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 2016{
ebc2ec48 2017 u32 ocp_data;
ac718b69 2018 u8 speed;
2019
2020 speed = rtl8152_get_speed(tp);
ebc2ec48 2021 if (speed & _10bps) {
ac718b69 2022 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2023 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 2024 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2025 } else {
2026 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2027 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 2028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2029 }
507605a8 2030}
2031
00a5e360 2032static void rxdy_gated_en(struct r8152 *tp, bool enable)
2033{
2034 u32 ocp_data;
2035
2036 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2037 if (enable)
2038 ocp_data |= RXDY_GATED_EN;
2039 else
2040 ocp_data &= ~RXDY_GATED_EN;
2041 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2042}
2043
445f7f4d 2044static int rtl_start_rx(struct r8152 *tp)
2045{
2046 int i, ret = 0;
2047
d823ab68 2048 napi_disable(&tp->napi);
445f7f4d 2049 INIT_LIST_HEAD(&tp->rx_done);
2050 for (i = 0; i < RTL8152_MAX_RX; i++) {
2051 INIT_LIST_HEAD(&tp->rx_info[i].list);
2052 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2053 if (ret)
2054 break;
2055 }
d823ab68 2056 napi_enable(&tp->napi);
445f7f4d 2057
7bcf4f60 2058 if (ret && ++i < RTL8152_MAX_RX) {
2059 struct list_head rx_queue;
2060 unsigned long flags;
2061
2062 INIT_LIST_HEAD(&rx_queue);
2063
2064 do {
2065 struct rx_agg *agg = &tp->rx_info[i++];
2066 struct urb *urb = agg->urb;
2067
2068 urb->actual_length = 0;
2069 list_add_tail(&agg->list, &rx_queue);
2070 } while (i < RTL8152_MAX_RX);
2071
2072 spin_lock_irqsave(&tp->rx_lock, flags);
2073 list_splice_tail(&rx_queue, &tp->rx_done);
2074 spin_unlock_irqrestore(&tp->rx_lock, flags);
2075 }
2076
445f7f4d 2077 return ret;
2078}
2079
2080static int rtl_stop_rx(struct r8152 *tp)
2081{
2082 int i;
2083
2084 for (i = 0; i < RTL8152_MAX_RX; i++)
2085 usb_kill_urb(tp->rx_info[i].urb);
2086
d823ab68 2087 while (!skb_queue_empty(&tp->rx_queue))
2088 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2089
445f7f4d 2090 return 0;
2091}
2092
507605a8 2093static int rtl_enable(struct r8152 *tp)
2094{
2095 u32 ocp_data;
ac718b69 2096
2097 r8152b_reset_packet_filter(tp);
2098
2099 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2100 ocp_data |= CR_RE | CR_TE;
2101 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2102
00a5e360 2103 rxdy_gated_en(tp, false);
ac718b69 2104
aa2e0926 2105 return 0;
ac718b69 2106}
2107
507605a8 2108static int rtl8152_enable(struct r8152 *tp)
2109{
6871438c 2110 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2111 return -ENODEV;
2112
507605a8 2113 set_tx_qlen(tp);
2114 rtl_set_eee_plus(tp);
2115
2116 return rtl_enable(tp);
2117}
2118
43779f8d 2119static void r8153_set_rx_agg(struct r8152 *tp)
2120{
2121 u8 speed;
2122
2123 speed = rtl8152_get_speed(tp);
2124 if (speed & _1000bps) {
2125 if (tp->udev->speed == USB_SPEED_SUPER) {
2126 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2127 RX_THR_SUPPER);
2128 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2129 EARLY_AGG_SUPPER);
2130 } else {
2131 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2132 RX_THR_HIGH);
2133 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2134 EARLY_AGG_HIGH);
2135 }
2136 } else {
2137 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2138 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2139 EARLY_AGG_SLOW);
2140 }
2141}
2142
2143static int rtl8153_enable(struct r8152 *tp)
2144{
6871438c 2145 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2146 return -ENODEV;
2147
43779f8d 2148 set_tx_qlen(tp);
2149 rtl_set_eee_plus(tp);
2150 r8153_set_rx_agg(tp);
2151
2152 return rtl_enable(tp);
2153}
2154
d70b1137 2155static void rtl_disable(struct r8152 *tp)
ac718b69 2156{
ebc2ec48 2157 u32 ocp_data;
2158 int i;
ac718b69 2159
6871438c 2160 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2161 rtl_drop_queued_tx(tp);
2162 return;
2163 }
2164
ac718b69 2165 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2166 ocp_data &= ~RCR_ACPT_ALL;
2167 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2168
00a5e360 2169 rtl_drop_queued_tx(tp);
ebc2ec48 2170
2171 for (i = 0; i < RTL8152_MAX_TX; i++)
2172 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2173
00a5e360 2174 rxdy_gated_en(tp, true);
ac718b69 2175
2176 for (i = 0; i < 1000; i++) {
2177 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2178 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2179 break;
8ddfa077 2180 usleep_range(1000, 2000);
ac718b69 2181 }
2182
2183 for (i = 0; i < 1000; i++) {
2184 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2185 break;
8ddfa077 2186 usleep_range(1000, 2000);
ac718b69 2187 }
2188
445f7f4d 2189 rtl_stop_rx(tp);
ac718b69 2190
2191 rtl8152_nic_reset(tp);
2192}
2193
00a5e360 2194static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2195{
2196 u32 ocp_data;
2197
2198 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2199 if (enable)
2200 ocp_data |= POWER_CUT;
2201 else
2202 ocp_data &= ~POWER_CUT;
2203 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2204
2205 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2206 ocp_data &= ~RESUME_INDICATE;
2207 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2208}
2209
c5554298 2210static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2211{
2212 u32 ocp_data;
2213
2214 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2215 if (enable)
2216 ocp_data |= CPCR_RX_VLAN;
2217 else
2218 ocp_data &= ~CPCR_RX_VLAN;
2219 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2220}
2221
2222static int rtl8152_set_features(struct net_device *dev,
2223 netdev_features_t features)
2224{
2225 netdev_features_t changed = features ^ dev->features;
2226 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2227 int ret;
2228
2229 ret = usb_autopm_get_interface(tp->intf);
2230 if (ret < 0)
2231 goto out;
c5554298 2232
b5403273 2233 mutex_lock(&tp->control);
2234
c5554298 2235 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2236 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2237 rtl_rx_vlan_en(tp, true);
2238 else
2239 rtl_rx_vlan_en(tp, false);
2240 }
2241
b5403273 2242 mutex_unlock(&tp->control);
2243
405f8a0e 2244 usb_autopm_put_interface(tp->intf);
2245
2246out:
2247 return ret;
c5554298 2248}
2249
21ff2e89 2250#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2251
2252static u32 __rtl_get_wol(struct r8152 *tp)
2253{
2254 u32 ocp_data;
2255 u32 wolopts = 0;
2256
2257 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2258 if (!(ocp_data & LAN_WAKE_EN))
2259 return 0;
2260
2261 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2262 if (ocp_data & LINK_ON_WAKE_EN)
2263 wolopts |= WAKE_PHY;
2264
2265 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2266 if (ocp_data & UWF_EN)
2267 wolopts |= WAKE_UCAST;
2268 if (ocp_data & BWF_EN)
2269 wolopts |= WAKE_BCAST;
2270 if (ocp_data & MWF_EN)
2271 wolopts |= WAKE_MCAST;
2272
2273 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2274 if (ocp_data & MAGIC_EN)
2275 wolopts |= WAKE_MAGIC;
2276
2277 return wolopts;
2278}
2279
2280static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2281{
2282 u32 ocp_data;
2283
2284 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2285
2286 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2287 ocp_data &= ~LINK_ON_WAKE_EN;
2288 if (wolopts & WAKE_PHY)
2289 ocp_data |= LINK_ON_WAKE_EN;
2290 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2291
2292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2293 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2294 if (wolopts & WAKE_UCAST)
2295 ocp_data |= UWF_EN;
2296 if (wolopts & WAKE_BCAST)
2297 ocp_data |= BWF_EN;
2298 if (wolopts & WAKE_MCAST)
2299 ocp_data |= MWF_EN;
2300 if (wolopts & WAKE_ANY)
2301 ocp_data |= LAN_WAKE_EN;
2302 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2303
2304 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2305
2306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2307 ocp_data &= ~MAGIC_EN;
2308 if (wolopts & WAKE_MAGIC)
2309 ocp_data |= MAGIC_EN;
2310 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2311
2312 if (wolopts & WAKE_ANY)
2313 device_set_wakeup_enable(&tp->udev->dev, true);
2314 else
2315 device_set_wakeup_enable(&tp->udev->dev, false);
2316}
2317
9a4be1bd 2318static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2319{
2320 if (enable) {
2321 u32 ocp_data;
2322
2323 __rtl_set_wol(tp, WAKE_ANY);
2324
2325 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2326
2327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2328 ocp_data |= LINK_OFF_WAKE_EN;
2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2330
2331 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2332 } else {
2333 __rtl_set_wol(tp, tp->saved_wolopts);
2334 }
2335}
2336
aa66a5f1 2337static void rtl_phy_reset(struct r8152 *tp)
2338{
2339 u16 data;
2340 int i;
2341
2342 clear_bit(PHY_RESET, &tp->flags);
2343
2344 data = r8152_mdio_read(tp, MII_BMCR);
2345
2346 /* don't reset again before the previous one complete */
2347 if (data & BMCR_RESET)
2348 return;
2349
2350 data |= BMCR_RESET;
2351 r8152_mdio_write(tp, MII_BMCR, data);
2352
2353 for (i = 0; i < 50; i++) {
2354 msleep(20);
2355 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2356 break;
2357 }
2358}
2359
4349968a 2360static void r8153_teredo_off(struct r8152 *tp)
2361{
2362 u32 ocp_data;
2363
2364 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2365 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2366 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2367
2368 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2369 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2370 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2371}
2372
2373static void r8152b_disable_aldps(struct r8152 *tp)
2374{
2375 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2376 msleep(20);
2377}
2378
2379static inline void r8152b_enable_aldps(struct r8152 *tp)
2380{
2381 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2382 LINKENA | DIS_SDSAVE);
2383}
2384
d70b1137 2385static void rtl8152_disable(struct r8152 *tp)
2386{
2387 r8152b_disable_aldps(tp);
2388 rtl_disable(tp);
2389 r8152b_enable_aldps(tp);
2390}
2391
4349968a 2392static void r8152b_hw_phy_cfg(struct r8152 *tp)
2393{
f0cbe0ac 2394 u16 data;
2395
2396 data = r8152_mdio_read(tp, MII_BMCR);
2397 if (data & BMCR_PDOWN) {
2398 data &= ~BMCR_PDOWN;
2399 r8152_mdio_write(tp, MII_BMCR, data);
2400 }
2401
aa66a5f1 2402 set_bit(PHY_RESET, &tp->flags);
4349968a 2403}
2404
ac718b69 2405static void r8152b_exit_oob(struct r8152 *tp)
2406{
db8515ef 2407 u32 ocp_data;
2408 int i;
ac718b69 2409
2410 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2411 ocp_data &= ~RCR_ACPT_ALL;
2412 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2413
00a5e360 2414 rxdy_gated_en(tp, true);
da9bd117 2415 r8153_teredo_off(tp);
7e9da481 2416 r8152b_hw_phy_cfg(tp);
ac718b69 2417
2418 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2419 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2420
2421 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2422 ocp_data &= ~NOW_IS_OOB;
2423 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2424
2425 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2426 ocp_data &= ~MCU_BORW_EN;
2427 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2428
2429 for (i = 0; i < 1000; i++) {
2430 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2431 if (ocp_data & LINK_LIST_READY)
2432 break;
8ddfa077 2433 usleep_range(1000, 2000);
ac718b69 2434 }
2435
2436 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2437 ocp_data |= RE_INIT_LL;
2438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2439
2440 for (i = 0; i < 1000; i++) {
2441 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2442 if (ocp_data & LINK_LIST_READY)
2443 break;
8ddfa077 2444 usleep_range(1000, 2000);
ac718b69 2445 }
2446
2447 rtl8152_nic_reset(tp);
2448
2449 /* rx share fifo credit full threshold */
2450 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2451
a3cc465d 2452 if (tp->udev->speed == USB_SPEED_FULL ||
2453 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2454 /* rx share fifo credit near full threshold */
2455 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2456 RXFIFO_THR2_FULL);
2457 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2458 RXFIFO_THR3_FULL);
2459 } else {
2460 /* rx share fifo credit near full threshold */
2461 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2462 RXFIFO_THR2_HIGH);
2463 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2464 RXFIFO_THR3_HIGH);
2465 }
2466
2467 /* TX share fifo free credit full threshold */
2468 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2469
2470 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2471 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2472 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2473 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2474
c5554298 2475 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2476
2477 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2478
2479 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2480 ocp_data |= TCR0_AUTO_FIFO;
2481 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2482}
2483
2484static void r8152b_enter_oob(struct r8152 *tp)
2485{
45f4a19f 2486 u32 ocp_data;
2487 int i;
ac718b69 2488
2489 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2490 ocp_data &= ~NOW_IS_OOB;
2491 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2492
2493 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2494 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2495 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2496
d70b1137 2497 rtl_disable(tp);
ac718b69 2498
2499 for (i = 0; i < 1000; i++) {
2500 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2501 if (ocp_data & LINK_LIST_READY)
2502 break;
8ddfa077 2503 usleep_range(1000, 2000);
ac718b69 2504 }
2505
2506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2507 ocp_data |= RE_INIT_LL;
2508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2509
2510 for (i = 0; i < 1000; i++) {
2511 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2512 if (ocp_data & LINK_LIST_READY)
2513 break;
8ddfa077 2514 usleep_range(1000, 2000);
ac718b69 2515 }
2516
2517 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2518
c5554298 2519 rtl_rx_vlan_en(tp, true);
ac718b69 2520
2521 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2522 ocp_data |= ALDPS_PROXY_MODE;
2523 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2524
2525 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2526 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2527 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2528
00a5e360 2529 rxdy_gated_en(tp, false);
ac718b69 2530
2531 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2532 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2533 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2534}
2535
43779f8d 2536static void r8153_hw_phy_cfg(struct r8152 *tp)
2537{
2538 u32 ocp_data;
2539 u16 data;
2540
2541 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
f0cbe0ac 2542 data = r8152_mdio_read(tp, MII_BMCR);
2543 if (data & BMCR_PDOWN) {
2544 data &= ~BMCR_PDOWN;
2545 r8152_mdio_write(tp, MII_BMCR, data);
2546 }
43779f8d 2547
2548 if (tp->version == RTL_VER_03) {
2549 data = ocp_reg_read(tp, OCP_EEE_CFG);
2550 data &= ~CTAP_SHORT_EN;
2551 ocp_reg_write(tp, OCP_EEE_CFG, data);
2552 }
2553
2554 data = ocp_reg_read(tp, OCP_POWER_CFG);
2555 data |= EEE_CLKDIV_EN;
2556 ocp_reg_write(tp, OCP_POWER_CFG, data);
2557
2558 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2559 data |= EN_10M_BGOFF;
2560 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2561 data = ocp_reg_read(tp, OCP_POWER_CFG);
2562 data |= EN_10M_PLLOFF;
2563 ocp_reg_write(tp, OCP_POWER_CFG, data);
b4d99def 2564 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
43779f8d 2565
2566 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2567 ocp_data |= PFM_PWM_SWITCH;
2568 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2569
b4d99def 2570 /* Enable LPF corner auto tune */
2571 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
43779f8d 2572
b4d99def 2573 /* Adjust 10M Amplitude */
2574 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2575 sram_write(tp, SRAM_10M_AMP2, 0x0208);
aa66a5f1 2576
2577 set_bit(PHY_RESET, &tp->flags);
43779f8d 2578}
2579
b9702723 2580static void r8153_u1u2en(struct r8152 *tp, bool enable)
43779f8d 2581{
2582 u8 u1u2[8];
2583
2584 if (enable)
2585 memset(u1u2, 0xff, sizeof(u1u2));
2586 else
2587 memset(u1u2, 0x00, sizeof(u1u2));
2588
2589 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2590}
2591
b9702723 2592static void r8153_u2p3en(struct r8152 *tp, bool enable)
43779f8d 2593{
2594 u32 ocp_data;
2595
2596 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2597 if (enable)
2598 ocp_data |= U2P3_ENABLE;
2599 else
2600 ocp_data &= ~U2P3_ENABLE;
2601 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2602}
2603
b9702723 2604static void r8153_power_cut_en(struct r8152 *tp, bool enable)
43779f8d 2605{
2606 u32 ocp_data;
2607
2608 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2609 if (enable)
2610 ocp_data |= PWR_EN | PHASE2_EN;
2611 else
2612 ocp_data &= ~(PWR_EN | PHASE2_EN);
2613 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2614
2615 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2616 ocp_data &= ~PCUT_STATUS;
2617 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2618}
2619
43779f8d 2620static void r8153_first_init(struct r8152 *tp)
2621{
2622 u32 ocp_data;
2623 int i;
2624
00a5e360 2625 rxdy_gated_en(tp, true);
43779f8d 2626 r8153_teredo_off(tp);
2627
2628 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2629 ocp_data &= ~RCR_ACPT_ALL;
2630 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2631
2632 r8153_hw_phy_cfg(tp);
2633
2634 rtl8152_nic_reset(tp);
2635
2636 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2637 ocp_data &= ~NOW_IS_OOB;
2638 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2639
2640 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2641 ocp_data &= ~MCU_BORW_EN;
2642 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2643
2644 for (i = 0; i < 1000; i++) {
2645 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2646 if (ocp_data & LINK_LIST_READY)
2647 break;
8ddfa077 2648 usleep_range(1000, 2000);
43779f8d 2649 }
2650
2651 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2652 ocp_data |= RE_INIT_LL;
2653 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2654
2655 for (i = 0; i < 1000; i++) {
2656 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2657 if (ocp_data & LINK_LIST_READY)
2658 break;
8ddfa077 2659 usleep_range(1000, 2000);
43779f8d 2660 }
2661
c5554298 2662 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2663
69b4b7a4 2664 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2665 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2666
2667 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2668 ocp_data |= TCR0_AUTO_FIFO;
2669 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2670
2671 rtl8152_nic_reset(tp);
2672
2673 /* rx share fifo credit full threshold */
2674 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2675 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2676 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2677 /* TX share fifo free credit full threshold */
2678 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2679
9629e3c0 2680 /* rx aggregation */
43779f8d 2681 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2682 ocp_data &= ~RX_AGG_DISABLE;
2683 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2684}
2685
2686static void r8153_enter_oob(struct r8152 *tp)
2687{
2688 u32 ocp_data;
2689 int i;
2690
2691 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2692 ocp_data &= ~NOW_IS_OOB;
2693 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2694
d70b1137 2695 rtl_disable(tp);
43779f8d 2696
2697 for (i = 0; i < 1000; i++) {
2698 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2699 if (ocp_data & LINK_LIST_READY)
2700 break;
8ddfa077 2701 usleep_range(1000, 2000);
43779f8d 2702 }
2703
2704 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2705 ocp_data |= RE_INIT_LL;
2706 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2707
2708 for (i = 0; i < 1000; i++) {
2709 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2710 if (ocp_data & LINK_LIST_READY)
2711 break;
8ddfa077 2712 usleep_range(1000, 2000);
43779f8d 2713 }
2714
69b4b7a4 2715 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2716
43779f8d 2717 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2718 ocp_data &= ~TEREDO_WAKE_MASK;
2719 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2720
c5554298 2721 rtl_rx_vlan_en(tp, true);
43779f8d 2722
2723 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2724 ocp_data |= ALDPS_PROXY_MODE;
2725 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2726
2727 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2728 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2729 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2730
00a5e360 2731 rxdy_gated_en(tp, false);
43779f8d 2732
2733 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2734 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2735 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2736}
2737
2738static void r8153_disable_aldps(struct r8152 *tp)
2739{
2740 u16 data;
2741
2742 data = ocp_reg_read(tp, OCP_POWER_CFG);
2743 data &= ~EN_ALDPS;
2744 ocp_reg_write(tp, OCP_POWER_CFG, data);
2745 msleep(20);
2746}
2747
2748static void r8153_enable_aldps(struct r8152 *tp)
2749{
2750 u16 data;
2751
2752 data = ocp_reg_read(tp, OCP_POWER_CFG);
2753 data |= EN_ALDPS;
2754 ocp_reg_write(tp, OCP_POWER_CFG, data);
2755}
2756
d70b1137 2757static void rtl8153_disable(struct r8152 *tp)
2758{
2759 r8153_disable_aldps(tp);
2760 rtl_disable(tp);
2761 r8153_enable_aldps(tp);
2762}
2763
ac718b69 2764static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2765{
43779f8d 2766 u16 bmcr, anar, gbcr;
ac718b69 2767 int ret = 0;
2768
2769 cancel_delayed_work_sync(&tp->schedule);
2770 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2771 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2772 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2773 if (tp->mii.supports_gmii) {
2774 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2775 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2776 } else {
2777 gbcr = 0;
2778 }
ac718b69 2779
2780 if (autoneg == AUTONEG_DISABLE) {
2781 if (speed == SPEED_10) {
2782 bmcr = 0;
2783 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2784 } else if (speed == SPEED_100) {
2785 bmcr = BMCR_SPEED100;
2786 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2787 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2788 bmcr = BMCR_SPEED1000;
2789 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2790 } else {
2791 ret = -EINVAL;
2792 goto out;
2793 }
2794
2795 if (duplex == DUPLEX_FULL)
2796 bmcr |= BMCR_FULLDPLX;
2797 } else {
2798 if (speed == SPEED_10) {
2799 if (duplex == DUPLEX_FULL)
2800 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2801 else
2802 anar |= ADVERTISE_10HALF;
2803 } else if (speed == SPEED_100) {
2804 if (duplex == DUPLEX_FULL) {
2805 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2806 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2807 } else {
2808 anar |= ADVERTISE_10HALF;
2809 anar |= ADVERTISE_100HALF;
2810 }
43779f8d 2811 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2812 if (duplex == DUPLEX_FULL) {
2813 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2814 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2815 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2816 } else {
2817 anar |= ADVERTISE_10HALF;
2818 anar |= ADVERTISE_100HALF;
2819 gbcr |= ADVERTISE_1000HALF;
2820 }
ac718b69 2821 } else {
2822 ret = -EINVAL;
2823 goto out;
2824 }
2825
2826 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2827 }
2828
aa66a5f1 2829 if (test_bit(PHY_RESET, &tp->flags))
2830 bmcr |= BMCR_RESET;
2831
43779f8d 2832 if (tp->mii.supports_gmii)
2833 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2834
ac718b69 2835 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2836 r8152_mdio_write(tp, MII_BMCR, bmcr);
2837
aa66a5f1 2838 if (test_bit(PHY_RESET, &tp->flags)) {
2839 int i;
2840
2841 clear_bit(PHY_RESET, &tp->flags);
2842 for (i = 0; i < 50; i++) {
2843 msleep(20);
2844 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2845 break;
2846 }
2847 }
2848
ac718b69 2849out:
ac718b69 2850
2851 return ret;
2852}
2853
d70b1137 2854static void rtl8152_up(struct r8152 *tp)
2855{
2856 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2857 return;
2858
2859 r8152b_disable_aldps(tp);
2860 r8152b_exit_oob(tp);
2861 r8152b_enable_aldps(tp);
2862}
2863
ac718b69 2864static void rtl8152_down(struct r8152 *tp)
2865{
6871438c 2866 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2867 rtl_drop_queued_tx(tp);
2868 return;
2869 }
2870
00a5e360 2871 r8152_power_cut_en(tp, false);
ac718b69 2872 r8152b_disable_aldps(tp);
2873 r8152b_enter_oob(tp);
2874 r8152b_enable_aldps(tp);
2875}
2876
d70b1137 2877static void rtl8153_up(struct r8152 *tp)
2878{
2879 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2880 return;
2881
2882 r8153_disable_aldps(tp);
2883 r8153_first_init(tp);
2884 r8153_enable_aldps(tp);
2885}
2886
43779f8d 2887static void rtl8153_down(struct r8152 *tp)
2888{
6871438c 2889 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2890 rtl_drop_queued_tx(tp);
2891 return;
2892 }
2893
b9702723 2894 r8153_u1u2en(tp, false);
2895 r8153_power_cut_en(tp, false);
43779f8d 2896 r8153_disable_aldps(tp);
2897 r8153_enter_oob(tp);
2898 r8153_enable_aldps(tp);
2899}
2900
ac718b69 2901static void set_carrier(struct r8152 *tp)
2902{
2903 struct net_device *netdev = tp->netdev;
2904 u8 speed;
2905
40a82917 2906 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 2907 speed = rtl8152_get_speed(tp);
2908
2909 if (speed & LINK_STATUS) {
2910 if (!(tp->speed & LINK_STATUS)) {
c81229c9 2911 tp->rtl_ops.enable(tp);
ac718b69 2912 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2913 netif_carrier_on(netdev);
aa2e0926 2914 rtl_start_rx(tp);
ac718b69 2915 }
2916 } else {
2917 if (tp->speed & LINK_STATUS) {
2918 netif_carrier_off(netdev);
d823ab68 2919 napi_disable(&tp->napi);
c81229c9 2920 tp->rtl_ops.disable(tp);
d823ab68 2921 napi_enable(&tp->napi);
ac718b69 2922 }
2923 }
2924 tp->speed = speed;
2925}
2926
2927static void rtl_work_func_t(struct work_struct *work)
2928{
2929 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2930
a1f83fee 2931 /* If the device is unplugged or !netif_running(), the workqueue
2932 * doesn't need to wake the device, and could return directly.
2933 */
2934 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2935 return;
2936
9a4be1bd 2937 if (usb_autopm_get_interface(tp->intf) < 0)
2938 return;
2939
ac718b69 2940 if (!test_bit(WORK_ENABLE, &tp->flags))
2941 goto out1;
2942
b5403273 2943 if (!mutex_trylock(&tp->control)) {
2944 schedule_delayed_work(&tp->schedule, 0);
2945 goto out1;
2946 }
2947
40a82917 2948 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2949 set_carrier(tp);
ac718b69 2950
2951 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2952 _rtl8152_set_rx_mode(tp->netdev);
2953
d823ab68 2954 /* don't schedule napi before linking */
2955 if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
0c3121fc 2956 (tp->speed & LINK_STATUS)) {
d823ab68 2957 clear_bit(SCHEDULE_NAPI, &tp->flags);
2958 napi_schedule(&tp->napi);
0c3121fc 2959 }
aa66a5f1 2960
2961 if (test_bit(PHY_RESET, &tp->flags))
2962 rtl_phy_reset(tp);
2963
b5403273 2964 mutex_unlock(&tp->control);
2965
ac718b69 2966out1:
9a4be1bd 2967 usb_autopm_put_interface(tp->intf);
ac718b69 2968}
2969
2970static int rtl8152_open(struct net_device *netdev)
2971{
2972 struct r8152 *tp = netdev_priv(netdev);
2973 int res = 0;
2974
7e9da481 2975 res = alloc_all_mem(tp);
2976 if (res)
2977 goto out;
2978
f4c7476b 2979 /* set speed to 0 to avoid autoresume try to submit rx */
2980 tp->speed = 0;
2981
9a4be1bd 2982 res = usb_autopm_get_interface(tp->intf);
2983 if (res < 0) {
2984 free_all_mem(tp);
2985 goto out;
2986 }
2987
b5403273 2988 mutex_lock(&tp->control);
2989
9a4be1bd 2990 /* The WORK_ENABLE may be set when autoresume occurs */
2991 if (test_bit(WORK_ENABLE, &tp->flags)) {
2992 clear_bit(WORK_ENABLE, &tp->flags);
2993 usb_kill_urb(tp->intr_urb);
2994 cancel_delayed_work_sync(&tp->schedule);
f4c7476b 2995
2996 /* disable the tx/rx, if the workqueue has enabled them. */
9a4be1bd 2997 if (tp->speed & LINK_STATUS)
2998 tp->rtl_ops.disable(tp);
2999 }
3000
7e9da481 3001 tp->rtl_ops.up(tp);
3002
3d55f44f 3003 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3004 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3005 DUPLEX_FULL);
3006 tp->speed = 0;
3007 netif_carrier_off(netdev);
3008 netif_start_queue(netdev);
3009 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 3010
40a82917 3011 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3012 if (res) {
3013 if (res == -ENODEV)
3014 netif_device_detach(tp->netdev);
4a8deae2
HW
3015 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3016 res);
7e9da481 3017 free_all_mem(tp);
93ffbeab 3018 } else {
d823ab68 3019 napi_enable(&tp->napi);
ac718b69 3020 }
3021
b5403273 3022 mutex_unlock(&tp->control);
3023
9a4be1bd 3024 usb_autopm_put_interface(tp->intf);
ac718b69 3025
7e9da481 3026out:
ac718b69 3027 return res;
3028}
3029
3030static int rtl8152_close(struct net_device *netdev)
3031{
3032 struct r8152 *tp = netdev_priv(netdev);
3033 int res = 0;
3034
d823ab68 3035 napi_disable(&tp->napi);
ac718b69 3036 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 3037 usb_kill_urb(tp->intr_urb);
ac718b69 3038 cancel_delayed_work_sync(&tp->schedule);
3039 netif_stop_queue(netdev);
9a4be1bd 3040
3041 res = usb_autopm_get_interface(tp->intf);
3042 if (res < 0) {
3043 rtl_drop_queued_tx(tp);
d823ab68 3044 rtl_stop_rx(tp);
9a4be1bd 3045 } else {
b5403273 3046 mutex_lock(&tp->control);
3047
b209af99 3048 /* The autosuspend may have been enabled and wouldn't
9a4be1bd 3049 * be disable when autoresume occurs, because the
3050 * netif_running() would be false.
3051 */
923e1ee3 3052 rtl_runtime_suspend_enable(tp, false);
9a4be1bd 3053
9a4be1bd 3054 tp->rtl_ops.down(tp);
b5403273 3055
3056 mutex_unlock(&tp->control);
3057
9a4be1bd 3058 usb_autopm_put_interface(tp->intf);
3059 }
ac718b69 3060
7e9da481 3061 free_all_mem(tp);
3062
ac718b69 3063 return res;
3064}
3065
d24f6134 3066static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3067{
3068 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3069 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3070 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3071}
3072
3073static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3074{
3075 u16 data;
3076
3077 r8152_mmd_indirect(tp, dev, reg);
3078 data = ocp_reg_read(tp, OCP_EEE_DATA);
3079 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3080
3081 return data;
3082}
3083
3084static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
ac718b69 3085{
d24f6134 3086 r8152_mmd_indirect(tp, dev, reg);
3087 ocp_reg_write(tp, OCP_EEE_DATA, data);
3088 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3089}
3090
3091static void r8152_eee_en(struct r8152 *tp, bool enable)
3092{
3093 u16 config1, config2, config3;
45f4a19f 3094 u32 ocp_data;
ac718b69 3095
3096 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3097 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3098 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3099 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3100
3101 if (enable) {
3102 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3103 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3104 config1 |= sd_rise_time(1);
3105 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3106 config3 |= fast_snr(42);
3107 } else {
3108 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3109 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3110 RX_QUIET_EN);
3111 config1 |= sd_rise_time(7);
3112 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3113 config3 |= fast_snr(511);
3114 }
3115
ac718b69 3116 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3117 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3118 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3119 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
ac718b69 3120}
3121
d24f6134 3122static void r8152b_enable_eee(struct r8152 *tp)
3123{
3124 r8152_eee_en(tp, true);
3125 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3126}
3127
3128static void r8153_eee_en(struct r8152 *tp, bool enable)
43779f8d 3129{
3130 u32 ocp_data;
d24f6134 3131 u16 config;
43779f8d 3132
3133 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3134 config = ocp_reg_read(tp, OCP_EEE_CFG);
3135
3136 if (enable) {
3137 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3138 config |= EEE10_EN;
3139 } else {
3140 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3141 config &= ~EEE10_EN;
3142 }
3143
43779f8d 3144 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3145 ocp_reg_write(tp, OCP_EEE_CFG, config);
3146}
3147
3148static void r8153_enable_eee(struct r8152 *tp)
3149{
3150 r8153_eee_en(tp, true);
3151 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
43779f8d 3152}
3153
ac718b69 3154static void r8152b_enable_fc(struct r8152 *tp)
3155{
3156 u16 anar;
3157
3158 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3159 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3160 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3161}
3162
4f1d4d54 3163static void rtl_tally_reset(struct r8152 *tp)
3164{
3165 u32 ocp_data;
3166
3167 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3168 ocp_data |= TALLY_RESET;
3169 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3170}
3171
ac718b69 3172static void r8152b_init(struct r8152 *tp)
3173{
ebc2ec48 3174 u32 ocp_data;
ac718b69 3175
6871438c 3176 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3177 return;
3178
d70b1137 3179 r8152b_disable_aldps(tp);
3180
ac718b69 3181 if (tp->version == RTL_VER_01) {
3182 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3183 ocp_data &= ~LED_MODE_MASK;
3184 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3185 }
3186
00a5e360 3187 r8152_power_cut_en(tp, false);
ac718b69 3188
ac718b69 3189 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3190 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3191 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3192 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3193 ocp_data &= ~MCU_CLK_RATIO_MASK;
3194 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3195 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3196 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3197 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3198 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3199
3200 r8152b_enable_eee(tp);
3201 r8152b_enable_aldps(tp);
3202 r8152b_enable_fc(tp);
4f1d4d54 3203 rtl_tally_reset(tp);
ac718b69 3204
ebc2ec48 3205 /* enable rx aggregation */
ac718b69 3206 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 3207 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 3208 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3209}
3210
43779f8d 3211static void r8153_init(struct r8152 *tp)
3212{
3213 u32 ocp_data;
3214 int i;
3215
6871438c 3216 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3217 return;
3218
d70b1137 3219 r8153_disable_aldps(tp);
b9702723 3220 r8153_u1u2en(tp, false);
43779f8d 3221
3222 for (i = 0; i < 500; i++) {
3223 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3224 AUTOLOAD_DONE)
3225 break;
3226 msleep(20);
3227 }
3228
3229 for (i = 0; i < 500; i++) {
3230 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3231 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3232 break;
3233 msleep(20);
3234 }
3235
b9702723 3236 r8153_u2p3en(tp, false);
43779f8d 3237
3238 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3239 ocp_data &= ~TIMER11_EN;
3240 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3241
43779f8d 3242 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3243 ocp_data &= ~LED_MODE_MASK;
3244 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3245
3246 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3247 ocp_data &= ~LPM_TIMER_MASK;
3248 if (tp->udev->speed == USB_SPEED_SUPER)
3249 ocp_data |= LPM_TIMER_500US;
3250 else
3251 ocp_data |= LPM_TIMER_500MS;
3252 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3253
3254 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3255 ocp_data &= ~SEN_VAL_MASK;
3256 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3257 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3258
b9702723 3259 r8153_power_cut_en(tp, false);
3260 r8153_u1u2en(tp, true);
43779f8d 3261
43779f8d 3262 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3263 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3264 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3265 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3266 U1U2_SPDWN_EN | L1_SPDWN_EN);
3267 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3268 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3269 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3270 EEE_SPDWN_EN);
3271
3272 r8153_enable_eee(tp);
3273 r8153_enable_aldps(tp);
3274 r8152b_enable_fc(tp);
4f1d4d54 3275 rtl_tally_reset(tp);
43779f8d 3276}
3277
ac718b69 3278static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3279{
3280 struct r8152 *tp = usb_get_intfdata(intf);
6cc69f2a 3281 struct net_device *netdev = tp->netdev;
3282 int ret = 0;
ac718b69 3283
b5403273 3284 mutex_lock(&tp->control);
3285
6cc69f2a 3286 if (PMSG_IS_AUTO(message)) {
3287 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3288 ret = -EBUSY;
3289 goto out1;
3290 }
3291
9a4be1bd 3292 set_bit(SELECTIVE_SUSPEND, &tp->flags);
6cc69f2a 3293 } else {
3294 netif_device_detach(netdev);
3295 }
ac718b69 3296
e3bd1a81 3297 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ac718b69 3298 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3299 usb_kill_urb(tp->intr_urb);
d823ab68 3300 napi_disable(&tp->napi);
9a4be1bd 3301 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
445f7f4d 3302 rtl_stop_rx(tp);
9a4be1bd 3303 rtl_runtime_suspend_enable(tp, true);
3304 } else {
6cc69f2a 3305 cancel_delayed_work_sync(&tp->schedule);
9a4be1bd 3306 tp->rtl_ops.down(tp);
9a4be1bd 3307 }
d823ab68 3308 napi_enable(&tp->napi);
ac718b69 3309 }
6cc69f2a 3310out1:
b5403273 3311 mutex_unlock(&tp->control);
3312
6cc69f2a 3313 return ret;
ac718b69 3314}
3315
3316static int rtl8152_resume(struct usb_interface *intf)
3317{
3318 struct r8152 *tp = usb_get_intfdata(intf);
3319
b5403273 3320 mutex_lock(&tp->control);
3321
9a4be1bd 3322 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3323 tp->rtl_ops.init(tp);
3324 netif_device_attach(tp->netdev);
3325 }
3326
ac718b69 3327 if (netif_running(tp->netdev)) {
9a4be1bd 3328 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3329 rtl_runtime_suspend_enable(tp, false);
3330 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
445f7f4d 3331 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3332 if (tp->speed & LINK_STATUS)
445f7f4d 3333 rtl_start_rx(tp);
9a4be1bd 3334 } else {
3335 tp->rtl_ops.up(tp);
3336 rtl8152_set_speed(tp, AUTONEG_ENABLE,
b209af99 3337 tp->mii.supports_gmii ?
3338 SPEED_1000 : SPEED_100,
3339 DUPLEX_FULL);
445f7f4d 3340 tp->speed = 0;
3341 netif_carrier_off(tp->netdev);
3342 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3343 }
40a82917 3344 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3345 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3346 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3347 }
3348
b5403273 3349 mutex_unlock(&tp->control);
3350
ac718b69 3351 return 0;
3352}
3353
21ff2e89 3354static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3355{
3356 struct r8152 *tp = netdev_priv(dev);
3357
9a4be1bd 3358 if (usb_autopm_get_interface(tp->intf) < 0)
3359 return;
3360
b5403273 3361 mutex_lock(&tp->control);
3362
21ff2e89 3363 wol->supported = WAKE_ANY;
3364 wol->wolopts = __rtl_get_wol(tp);
9a4be1bd 3365
b5403273 3366 mutex_unlock(&tp->control);
3367
9a4be1bd 3368 usb_autopm_put_interface(tp->intf);
21ff2e89 3369}
3370
3371static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3372{
3373 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3374 int ret;
3375
3376 ret = usb_autopm_get_interface(tp->intf);
3377 if (ret < 0)
3378 goto out_set_wol;
21ff2e89 3379
b5403273 3380 mutex_lock(&tp->control);
3381
21ff2e89 3382 __rtl_set_wol(tp, wol->wolopts);
3383 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3384
b5403273 3385 mutex_unlock(&tp->control);
3386
9a4be1bd 3387 usb_autopm_put_interface(tp->intf);
3388
3389out_set_wol:
3390 return ret;
21ff2e89 3391}
3392
a5ec27c1 3393static u32 rtl8152_get_msglevel(struct net_device *dev)
3394{
3395 struct r8152 *tp = netdev_priv(dev);
3396
3397 return tp->msg_enable;
3398}
3399
3400static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3401{
3402 struct r8152 *tp = netdev_priv(dev);
3403
3404 tp->msg_enable = value;
3405}
3406
ac718b69 3407static void rtl8152_get_drvinfo(struct net_device *netdev,
3408 struct ethtool_drvinfo *info)
3409{
3410 struct r8152 *tp = netdev_priv(netdev);
3411
b0b46c77 3412 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3413 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3414 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3415}
3416
3417static
3418int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3419{
3420 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3421 int ret;
ac718b69 3422
3423 if (!tp->mii.mdio_read)
3424 return -EOPNOTSUPP;
3425
8d4a4d72 3426 ret = usb_autopm_get_interface(tp->intf);
3427 if (ret < 0)
3428 goto out;
3429
b5403273 3430 mutex_lock(&tp->control);
3431
8d4a4d72 3432 ret = mii_ethtool_gset(&tp->mii, cmd);
3433
b5403273 3434 mutex_unlock(&tp->control);
3435
8d4a4d72 3436 usb_autopm_put_interface(tp->intf);
3437
3438out:
3439 return ret;
ac718b69 3440}
3441
3442static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3443{
3444 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3445 int ret;
3446
3447 ret = usb_autopm_get_interface(tp->intf);
3448 if (ret < 0)
3449 goto out;
ac718b69 3450
b5403273 3451 mutex_lock(&tp->control);
3452
9a4be1bd 3453 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3454
b5403273 3455 mutex_unlock(&tp->control);
3456
9a4be1bd 3457 usb_autopm_put_interface(tp->intf);
3458
3459out:
3460 return ret;
ac718b69 3461}
3462
4f1d4d54 3463static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3464 "tx_packets",
3465 "rx_packets",
3466 "tx_errors",
3467 "rx_errors",
3468 "rx_missed",
3469 "align_errors",
3470 "tx_single_collisions",
3471 "tx_multi_collisions",
3472 "rx_unicast",
3473 "rx_broadcast",
3474 "rx_multicast",
3475 "tx_aborted",
3476 "tx_underrun",
3477};
3478
3479static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3480{
3481 switch (sset) {
3482 case ETH_SS_STATS:
3483 return ARRAY_SIZE(rtl8152_gstrings);
3484 default:
3485 return -EOPNOTSUPP;
3486 }
3487}
3488
3489static void rtl8152_get_ethtool_stats(struct net_device *dev,
3490 struct ethtool_stats *stats, u64 *data)
3491{
3492 struct r8152 *tp = netdev_priv(dev);
3493 struct tally_counter tally;
3494
0b030244 3495 if (usb_autopm_get_interface(tp->intf) < 0)
3496 return;
3497
4f1d4d54 3498 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3499
0b030244 3500 usb_autopm_put_interface(tp->intf);
3501
4f1d4d54 3502 data[0] = le64_to_cpu(tally.tx_packets);
3503 data[1] = le64_to_cpu(tally.rx_packets);
3504 data[2] = le64_to_cpu(tally.tx_errors);
3505 data[3] = le32_to_cpu(tally.rx_errors);
3506 data[4] = le16_to_cpu(tally.rx_missed);
3507 data[5] = le16_to_cpu(tally.align_errors);
3508 data[6] = le32_to_cpu(tally.tx_one_collision);
3509 data[7] = le32_to_cpu(tally.tx_multi_collision);
3510 data[8] = le64_to_cpu(tally.rx_unicast);
3511 data[9] = le64_to_cpu(tally.rx_broadcast);
3512 data[10] = le32_to_cpu(tally.rx_multicast);
3513 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3514 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3515}
3516
3517static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3518{
3519 switch (stringset) {
3520 case ETH_SS_STATS:
3521 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3522 break;
3523 }
3524}
3525
df35d283 3526static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3527{
3528 u32 ocp_data, lp, adv, supported = 0;
3529 u16 val;
3530
3531 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3532 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3533
3534 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3535 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3536
3537 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3538 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3539
3540 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3541 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3542
3543 eee->eee_enabled = !!ocp_data;
3544 eee->eee_active = !!(supported & adv & lp);
3545 eee->supported = supported;
3546 eee->advertised = adv;
3547 eee->lp_advertised = lp;
3548
3549 return 0;
3550}
3551
3552static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3553{
3554 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3555
3556 r8152_eee_en(tp, eee->eee_enabled);
3557
3558 if (!eee->eee_enabled)
3559 val = 0;
3560
3561 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3562
3563 return 0;
3564}
3565
3566static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3567{
3568 u32 ocp_data, lp, adv, supported = 0;
3569 u16 val;
3570
3571 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3572 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3573
3574 val = ocp_reg_read(tp, OCP_EEE_ADV);
3575 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3576
3577 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3578 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3579
3580 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3581 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3582
3583 eee->eee_enabled = !!ocp_data;
3584 eee->eee_active = !!(supported & adv & lp);
3585 eee->supported = supported;
3586 eee->advertised = adv;
3587 eee->lp_advertised = lp;
3588
3589 return 0;
3590}
3591
3592static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3593{
3594 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3595
3596 r8153_eee_en(tp, eee->eee_enabled);
3597
3598 if (!eee->eee_enabled)
3599 val = 0;
3600
3601 ocp_reg_write(tp, OCP_EEE_ADV, val);
3602
3603 return 0;
3604}
3605
3606static int
3607rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3608{
3609 struct r8152 *tp = netdev_priv(net);
3610 int ret;
3611
3612 ret = usb_autopm_get_interface(tp->intf);
3613 if (ret < 0)
3614 goto out;
3615
b5403273 3616 mutex_lock(&tp->control);
3617
df35d283 3618 ret = tp->rtl_ops.eee_get(tp, edata);
3619
b5403273 3620 mutex_unlock(&tp->control);
3621
df35d283 3622 usb_autopm_put_interface(tp->intf);
3623
3624out:
3625 return ret;
3626}
3627
3628static int
3629rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3630{
3631 struct r8152 *tp = netdev_priv(net);
3632 int ret;
3633
3634 ret = usb_autopm_get_interface(tp->intf);
3635 if (ret < 0)
3636 goto out;
3637
b5403273 3638 mutex_lock(&tp->control);
3639
df35d283 3640 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 3641 if (!ret)
3642 ret = mii_nway_restart(&tp->mii);
df35d283 3643
b5403273 3644 mutex_unlock(&tp->control);
3645
df35d283 3646 usb_autopm_put_interface(tp->intf);
3647
3648out:
3649 return ret;
3650}
3651
8884f507 3652static int rtl8152_nway_reset(struct net_device *dev)
3653{
3654 struct r8152 *tp = netdev_priv(dev);
3655 int ret;
3656
3657 ret = usb_autopm_get_interface(tp->intf);
3658 if (ret < 0)
3659 goto out;
3660
3661 mutex_lock(&tp->control);
3662
3663 ret = mii_nway_restart(&tp->mii);
3664
3665 mutex_unlock(&tp->control);
3666
3667 usb_autopm_put_interface(tp->intf);
3668
3669out:
3670 return ret;
3671}
3672
ac718b69 3673static struct ethtool_ops ops = {
3674 .get_drvinfo = rtl8152_get_drvinfo,
3675 .get_settings = rtl8152_get_settings,
3676 .set_settings = rtl8152_set_settings,
3677 .get_link = ethtool_op_get_link,
8884f507 3678 .nway_reset = rtl8152_nway_reset,
a5ec27c1 3679 .get_msglevel = rtl8152_get_msglevel,
3680 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 3681 .get_wol = rtl8152_get_wol,
3682 .set_wol = rtl8152_set_wol,
4f1d4d54 3683 .get_strings = rtl8152_get_strings,
3684 .get_sset_count = rtl8152_get_sset_count,
3685 .get_ethtool_stats = rtl8152_get_ethtool_stats,
df35d283 3686 .get_eee = rtl_ethtool_get_eee,
3687 .set_eee = rtl_ethtool_set_eee,
ac718b69 3688};
3689
3690static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3691{
3692 struct r8152 *tp = netdev_priv(netdev);
3693 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 3694 int res;
3695
6871438c 3696 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3697 return -ENODEV;
3698
9a4be1bd 3699 res = usb_autopm_get_interface(tp->intf);
3700 if (res < 0)
3701 goto out;
ac718b69 3702
3703 switch (cmd) {
3704 case SIOCGMIIPHY:
3705 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3706 break;
3707
3708 case SIOCGMIIREG:
b5403273 3709 mutex_lock(&tp->control);
ac718b69 3710 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 3711 mutex_unlock(&tp->control);
ac718b69 3712 break;
3713
3714 case SIOCSMIIREG:
3715 if (!capable(CAP_NET_ADMIN)) {
3716 res = -EPERM;
3717 break;
3718 }
b5403273 3719 mutex_lock(&tp->control);
ac718b69 3720 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 3721 mutex_unlock(&tp->control);
ac718b69 3722 break;
3723
3724 default:
3725 res = -EOPNOTSUPP;
3726 }
3727
9a4be1bd 3728 usb_autopm_put_interface(tp->intf);
3729
3730out:
ac718b69 3731 return res;
3732}
3733
69b4b7a4 3734static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3735{
3736 struct r8152 *tp = netdev_priv(dev);
3737
3738 switch (tp->version) {
3739 case RTL_VER_01:
3740 case RTL_VER_02:
3741 return eth_change_mtu(dev, new_mtu);
3742 default:
3743 break;
3744 }
3745
3746 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3747 return -EINVAL;
3748
3749 dev->mtu = new_mtu;
3750
3751 return 0;
3752}
3753
ac718b69 3754static const struct net_device_ops rtl8152_netdev_ops = {
3755 .ndo_open = rtl8152_open,
3756 .ndo_stop = rtl8152_close,
3757 .ndo_do_ioctl = rtl8152_ioctl,
3758 .ndo_start_xmit = rtl8152_start_xmit,
3759 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 3760 .ndo_set_features = rtl8152_set_features,
ac718b69 3761 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3762 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 3763 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 3764 .ndo_validate_addr = eth_validate_addr,
a5e31255 3765 .ndo_features_check = rtl8152_features_check,
ac718b69 3766};
3767
3768static void r8152b_get_version(struct r8152 *tp)
3769{
3770 u32 ocp_data;
3771 u16 version;
3772
3773 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3774 version = (u16)(ocp_data & VERSION_MASK);
3775
3776 switch (version) {
3777 case 0x4c00:
3778 tp->version = RTL_VER_01;
3779 break;
3780 case 0x4c10:
3781 tp->version = RTL_VER_02;
3782 break;
43779f8d 3783 case 0x5c00:
3784 tp->version = RTL_VER_03;
3785 tp->mii.supports_gmii = 1;
3786 break;
3787 case 0x5c10:
3788 tp->version = RTL_VER_04;
3789 tp->mii.supports_gmii = 1;
3790 break;
3791 case 0x5c20:
3792 tp->version = RTL_VER_05;
3793 tp->mii.supports_gmii = 1;
3794 break;
ac718b69 3795 default:
3796 netif_info(tp, probe, tp->netdev,
3797 "Unknown version 0x%04x\n", version);
3798 break;
3799 }
3800}
3801
e3fe0b1a 3802static void rtl8152_unload(struct r8152 *tp)
3803{
6871438c 3804 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3805 return;
3806
00a5e360 3807 if (tp->version != RTL_VER_01)
3808 r8152_power_cut_en(tp, true);
e3fe0b1a 3809}
3810
43779f8d 3811static void rtl8153_unload(struct r8152 *tp)
3812{
6871438c 3813 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3814 return;
3815
49be1723 3816 r8153_power_cut_en(tp, false);
43779f8d 3817}
3818
55b65475 3819static int rtl_ops_init(struct r8152 *tp)
c81229c9 3820{
3821 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 3822 int ret = 0;
3823
3824 switch (tp->version) {
3825 case RTL_VER_01:
3826 case RTL_VER_02:
3827 ops->init = r8152b_init;
3828 ops->enable = rtl8152_enable;
3829 ops->disable = rtl8152_disable;
3830 ops->up = rtl8152_up;
3831 ops->down = rtl8152_down;
3832 ops->unload = rtl8152_unload;
3833 ops->eee_get = r8152_get_eee;
3834 ops->eee_set = r8152_set_eee;
43779f8d 3835 break;
3836
55b65475 3837 case RTL_VER_03:
3838 case RTL_VER_04:
3839 case RTL_VER_05:
3840 ops->init = r8153_init;
3841 ops->enable = rtl8153_enable;
3842 ops->disable = rtl8153_disable;
3843 ops->up = rtl8153_up;
3844 ops->down = rtl8153_down;
3845 ops->unload = rtl8153_unload;
3846 ops->eee_get = r8153_get_eee;
3847 ops->eee_set = r8153_set_eee;
c81229c9 3848 break;
3849
3850 default:
55b65475 3851 ret = -ENODEV;
3852 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 3853 break;
3854 }
3855
3856 return ret;
3857}
3858
ac718b69 3859static int rtl8152_probe(struct usb_interface *intf,
3860 const struct usb_device_id *id)
3861{
3862 struct usb_device *udev = interface_to_usbdev(intf);
3863 struct r8152 *tp;
3864 struct net_device *netdev;
ebc2ec48 3865 int ret;
ac718b69 3866
10c32717 3867 if (udev->actconfig->desc.bConfigurationValue != 1) {
3868 usb_driver_set_configuration(udev, 1);
3869 return -ENODEV;
3870 }
3871
3872 usb_reset_device(udev);
ac718b69 3873 netdev = alloc_etherdev(sizeof(struct r8152));
3874 if (!netdev) {
4a8deae2 3875 dev_err(&intf->dev, "Out of memory\n");
ac718b69 3876 return -ENOMEM;
3877 }
3878
ebc2ec48 3879 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 3880 tp = netdev_priv(netdev);
3881 tp->msg_enable = 0x7FFF;
3882
e3ad412a 3883 tp->udev = udev;
3884 tp->netdev = netdev;
3885 tp->intf = intf;
3886
82cf94cb 3887 r8152b_get_version(tp);
55b65475 3888 ret = rtl_ops_init(tp);
31ca1dec 3889 if (ret)
3890 goto out;
c81229c9 3891
b5403273 3892 mutex_init(&tp->control);
ac718b69 3893 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3894
ac718b69 3895 netdev->netdev_ops = &rtl8152_netdev_ops;
3896 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 3897
60c89071 3898 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3899 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 3900 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3901 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 3902 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3903 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 3904 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3905 NETIF_F_HW_VLAN_CTAG_RX |
3906 NETIF_F_HW_VLAN_CTAG_TX;
3907 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3908 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3909 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 3910
7ad24ea4 3911 netdev->ethtool_ops = &ops;
60c89071 3912 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 3913
3914 tp->mii.dev = netdev;
3915 tp->mii.mdio_read = read_mii_word;
3916 tp->mii.mdio_write = write_mii_word;
3917 tp->mii.phy_id_mask = 0x3f;
3918 tp->mii.reg_num_mask = 0x1f;
3919 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 3920
9a4be1bd 3921 intf->needs_remote_wakeup = 1;
3922
c81229c9 3923 tp->rtl_ops.init(tp);
ac718b69 3924 set_ethernet_addr(tp);
3925
ac718b69 3926 usb_set_intfdata(intf, tp);
d823ab68 3927 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
ac718b69 3928
ebc2ec48 3929 ret = register_netdev(netdev);
3930 if (ret != 0) {
4a8deae2 3931 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 3932 goto out1;
ac718b69 3933 }
3934
21ff2e89 3935 tp->saved_wolopts = __rtl_get_wol(tp);
3936 if (tp->saved_wolopts)
3937 device_set_wakeup_enable(&udev->dev, true);
3938 else
3939 device_set_wakeup_enable(&udev->dev, false);
3940
4a8deae2 3941 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 3942
3943 return 0;
3944
ac718b69 3945out1:
d823ab68 3946 netif_napi_del(&tp->napi);
ebc2ec48 3947 usb_set_intfdata(intf, NULL);
ac718b69 3948out:
3949 free_netdev(netdev);
ebc2ec48 3950 return ret;
ac718b69 3951}
3952
ac718b69 3953static void rtl8152_disconnect(struct usb_interface *intf)
3954{
3955 struct r8152 *tp = usb_get_intfdata(intf);
3956
3957 usb_set_intfdata(intf, NULL);
3958 if (tp) {
f561de33 3959 struct usb_device *udev = tp->udev;
3960
3961 if (udev->state == USB_STATE_NOTATTACHED)
3962 set_bit(RTL8152_UNPLUG, &tp->flags);
3963
d823ab68 3964 netif_napi_del(&tp->napi);
ac718b69 3965 unregister_netdev(tp->netdev);
c81229c9 3966 tp->rtl_ops.unload(tp);
ac718b69 3967 free_netdev(tp->netdev);
3968 }
3969}
3970
d9a28c5b 3971#define REALTEK_USB_DEVICE(vend, prod) \
3972 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
3973 USB_DEVICE_ID_MATCH_INT_CLASS, \
3974 .idVendor = (vend), \
3975 .idProduct = (prod), \
3976 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
3977}, \
3978{ \
3979 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
3980 USB_DEVICE_ID_MATCH_DEVICE, \
3981 .idVendor = (vend), \
3982 .idProduct = (prod), \
3983 .bInterfaceClass = USB_CLASS_COMM, \
3984 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
3985 .bInterfaceProtocol = USB_CDC_PROTO_NONE
3986
ac718b69 3987/* table of devices that work with this driver */
3988static struct usb_device_id rtl8152_table[] = {
d9a28c5b 3989 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
3990 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
3991 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
ac718b69 3992 {}
3993};
3994
3995MODULE_DEVICE_TABLE(usb, rtl8152_table);
3996
3997static struct usb_driver rtl8152_driver = {
3998 .name = MODULENAME,
ebc2ec48 3999 .id_table = rtl8152_table,
ac718b69 4000 .probe = rtl8152_probe,
4001 .disconnect = rtl8152_disconnect,
ac718b69 4002 .suspend = rtl8152_suspend,
ebc2ec48 4003 .resume = rtl8152_resume,
4004 .reset_resume = rtl8152_resume,
9a4be1bd 4005 .supports_autosuspend = 1,
a634782f 4006 .disable_hub_initiated_lpm = 1,
ac718b69 4007};
4008
b4236daa 4009module_usb_driver(rtl8152_driver);
ac718b69 4010
4011MODULE_AUTHOR(DRIVER_AUTHOR);
4012MODULE_DESCRIPTION(DRIVER_DESC);
4013MODULE_LICENSE("GPL");
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