ac718b69 |
1 | /* |
2 | * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved. |
3 | * |
4 | * This program is free software; you can redistribute it and/or |
5 | * modify it under the terms of the GNU General Public License |
6 | * version 2 as published by the Free Software Foundation. |
7 | * |
8 | */ |
9 | |
10 | #include <linux/init.h> |
11 | #include <linux/signal.h> |
12 | #include <linux/slab.h> |
13 | #include <linux/module.h> |
ac718b69 |
14 | #include <linux/netdevice.h> |
15 | #include <linux/etherdevice.h> |
16 | #include <linux/mii.h> |
17 | #include <linux/ethtool.h> |
18 | #include <linux/usb.h> |
19 | #include <linux/crc32.h> |
20 | #include <linux/if_vlan.h> |
21 | #include <linux/uaccess.h> |
ebc2ec48 |
22 | #include <linux/list.h> |
5bd23881 |
23 | #include <linux/ip.h> |
24 | #include <linux/ipv6.h> |
ac718b69 |
25 | |
26 | /* Version Information */ |
43779f8d |
27 | #define DRIVER_VERSION "v1.03.0 (2013/12/26)" |
ac718b69 |
28 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
29 | #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters" |
30 | #define MODULENAME "r8152" |
31 | |
32 | #define R8152_PHY_ID 32 |
33 | |
34 | #define PLA_IDR 0xc000 |
35 | #define PLA_RCR 0xc010 |
36 | #define PLA_RMS 0xc016 |
37 | #define PLA_RXFIFO_CTRL0 0xc0a0 |
38 | #define PLA_RXFIFO_CTRL1 0xc0a4 |
39 | #define PLA_RXFIFO_CTRL2 0xc0a8 |
40 | #define PLA_FMC 0xc0b4 |
41 | #define PLA_CFG_WOL 0xc0b6 |
43779f8d |
42 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 |
43 | #define PLA_MAR 0xcd00 |
43779f8d |
44 | #define PLA_BACKUP 0xd000 |
ac718b69 |
45 | #define PAL_BDC_CR 0xd1a0 |
43779f8d |
46 | #define PLA_TEREDO_TIMER 0xd2cc |
47 | #define PLA_REALWOW_TIMER 0xd2e8 |
ac718b69 |
48 | #define PLA_LEDSEL 0xdd90 |
49 | #define PLA_LED_FEATURE 0xdd92 |
50 | #define PLA_PHYAR 0xde00 |
43779f8d |
51 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 |
52 | #define PLA_GPHY_INTR_IMR 0xe022 |
53 | #define PLA_EEE_CR 0xe040 |
54 | #define PLA_EEEP_CR 0xe080 |
55 | #define PLA_MAC_PWR_CTRL 0xe0c0 |
43779f8d |
56 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
57 | #define PLA_MAC_PWR_CTRL3 0xe0cc |
58 | #define PLA_MAC_PWR_CTRL4 0xe0ce |
59 | #define PLA_WDT6_CTRL 0xe428 |
ac718b69 |
60 | #define PLA_TCR0 0xe610 |
61 | #define PLA_TCR1 0xe612 |
62 | #define PLA_TXFIFO_CTRL 0xe618 |
63 | #define PLA_RSTTELLY 0xe800 |
64 | #define PLA_CR 0xe813 |
65 | #define PLA_CRWECR 0xe81c |
66 | #define PLA_CONFIG5 0xe822 |
67 | #define PLA_PHY_PWR 0xe84c |
68 | #define PLA_OOB_CTRL 0xe84f |
69 | #define PLA_CPCR 0xe854 |
70 | #define PLA_MISC_0 0xe858 |
71 | #define PLA_MISC_1 0xe85a |
72 | #define PLA_OCP_GPHY_BASE 0xe86c |
73 | #define PLA_TELLYCNT 0xe890 |
74 | #define PLA_SFF_STS_7 0xe8de |
75 | #define PLA_PHYSTATUS 0xe908 |
76 | #define PLA_BP_BA 0xfc26 |
77 | #define PLA_BP_0 0xfc28 |
78 | #define PLA_BP_1 0xfc2a |
79 | #define PLA_BP_2 0xfc2c |
80 | #define PLA_BP_3 0xfc2e |
81 | #define PLA_BP_4 0xfc30 |
82 | #define PLA_BP_5 0xfc32 |
83 | #define PLA_BP_6 0xfc34 |
84 | #define PLA_BP_7 0xfc36 |
43779f8d |
85 | #define PLA_BP_EN 0xfc38 |
ac718b69 |
86 | |
43779f8d |
87 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 |
88 | #define USB_DEV_STAT 0xb808 |
89 | #define USB_USB_CTRL 0xd406 |
90 | #define USB_PHY_CTRL 0xd408 |
91 | #define USB_TX_AGG 0xd40a |
92 | #define USB_RX_BUF_TH 0xd40c |
93 | #define USB_USB_TIMER 0xd428 |
43779f8d |
94 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 |
95 | #define USB_PM_CTRL_STATUS 0xd432 |
96 | #define USB_TX_DMA 0xd434 |
43779f8d |
97 | #define USB_TOLERANCE 0xd490 |
98 | #define USB_LPM_CTRL 0xd41a |
ac718b69 |
99 | #define USB_UPS_CTRL 0xd800 |
43779f8d |
100 | #define USB_MISC_0 0xd81a |
101 | #define USB_POWER_CUT 0xd80a |
102 | #define USB_AFE_CTRL2 0xd824 |
103 | #define USB_WDT11_CTRL 0xe43c |
ac718b69 |
104 | #define USB_BP_BA 0xfc26 |
105 | #define USB_BP_0 0xfc28 |
106 | #define USB_BP_1 0xfc2a |
107 | #define USB_BP_2 0xfc2c |
108 | #define USB_BP_3 0xfc2e |
109 | #define USB_BP_4 0xfc30 |
110 | #define USB_BP_5 0xfc32 |
111 | #define USB_BP_6 0xfc34 |
112 | #define USB_BP_7 0xfc36 |
43779f8d |
113 | #define USB_BP_EN 0xfc38 |
ac718b69 |
114 | |
115 | /* OCP Registers */ |
116 | #define OCP_ALDPS_CONFIG 0x2010 |
117 | #define OCP_EEE_CONFIG1 0x2080 |
118 | #define OCP_EEE_CONFIG2 0x2092 |
119 | #define OCP_EEE_CONFIG3 0x2094 |
ac244d3e |
120 | #define OCP_BASE_MII 0xa400 |
ac718b69 |
121 | #define OCP_EEE_AR 0xa41a |
122 | #define OCP_EEE_DATA 0xa41c |
43779f8d |
123 | #define OCP_PHY_STATUS 0xa420 |
124 | #define OCP_POWER_CFG 0xa430 |
125 | #define OCP_EEE_CFG 0xa432 |
126 | #define OCP_SRAM_ADDR 0xa436 |
127 | #define OCP_SRAM_DATA 0xa438 |
128 | #define OCP_DOWN_SPEED 0xa442 |
129 | #define OCP_EEE_CFG2 0xa5d0 |
130 | #define OCP_ADC_CFG 0xbc06 |
131 | |
132 | /* SRAM Register */ |
133 | #define SRAM_LPF_CFG 0x8012 |
134 | #define SRAM_10M_AMP1 0x8080 |
135 | #define SRAM_10M_AMP2 0x8082 |
136 | #define SRAM_IMPEDANCE 0x8084 |
ac718b69 |
137 | |
138 | /* PLA_RCR */ |
139 | #define RCR_AAP 0x00000001 |
140 | #define RCR_APM 0x00000002 |
141 | #define RCR_AM 0x00000004 |
142 | #define RCR_AB 0x00000008 |
143 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) |
144 | |
145 | /* PLA_RXFIFO_CTRL0 */ |
146 | #define RXFIFO_THR1_NORMAL 0x00080002 |
147 | #define RXFIFO_THR1_OOB 0x01800003 |
148 | |
149 | /* PLA_RXFIFO_CTRL1 */ |
150 | #define RXFIFO_THR2_FULL 0x00000060 |
151 | #define RXFIFO_THR2_HIGH 0x00000038 |
152 | #define RXFIFO_THR2_OOB 0x0000004a |
43779f8d |
153 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 |
154 | |
155 | /* PLA_RXFIFO_CTRL2 */ |
156 | #define RXFIFO_THR3_FULL 0x00000078 |
157 | #define RXFIFO_THR3_HIGH 0x00000048 |
158 | #define RXFIFO_THR3_OOB 0x0000005a |
43779f8d |
159 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 |
160 | |
161 | /* PLA_TXFIFO_CTRL */ |
162 | #define TXFIFO_THR_NORMAL 0x00400008 |
43779f8d |
163 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 |
164 | |
165 | /* PLA_FMC */ |
166 | #define FMC_FCR_MCU_EN 0x0001 |
167 | |
168 | /* PLA_EEEP_CR */ |
169 | #define EEEP_CR_EEEP_TX 0x0002 |
170 | |
43779f8d |
171 | /* PLA_WDT6_CTRL */ |
172 | #define WDT6_SET_MODE 0x0010 |
173 | |
ac718b69 |
174 | /* PLA_TCR0 */ |
175 | #define TCR0_TX_EMPTY 0x0800 |
176 | #define TCR0_AUTO_FIFO 0x0080 |
177 | |
178 | /* PLA_TCR1 */ |
179 | #define VERSION_MASK 0x7cf0 |
180 | |
181 | /* PLA_CR */ |
182 | #define CR_RST 0x10 |
183 | #define CR_RE 0x08 |
184 | #define CR_TE 0x04 |
185 | |
186 | /* PLA_CRWECR */ |
187 | #define CRWECR_NORAML 0x00 |
188 | #define CRWECR_CONFIG 0xc0 |
189 | |
190 | /* PLA_OOB_CTRL */ |
191 | #define NOW_IS_OOB 0x80 |
192 | #define TXFIFO_EMPTY 0x20 |
193 | #define RXFIFO_EMPTY 0x10 |
194 | #define LINK_LIST_READY 0x02 |
195 | #define DIS_MCU_CLROOB 0x01 |
196 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) |
197 | |
198 | /* PLA_MISC_1 */ |
199 | #define RXDY_GATED_EN 0x0008 |
200 | |
201 | /* PLA_SFF_STS_7 */ |
202 | #define RE_INIT_LL 0x8000 |
203 | #define MCU_BORW_EN 0x4000 |
204 | |
205 | /* PLA_CPCR */ |
206 | #define CPCR_RX_VLAN 0x0040 |
207 | |
208 | /* PLA_CFG_WOL */ |
209 | #define MAGIC_EN 0x0001 |
210 | |
43779f8d |
211 | /* PLA_TEREDO_CFG */ |
212 | #define TEREDO_SEL 0x8000 |
213 | #define TEREDO_WAKE_MASK 0x7f00 |
214 | #define TEREDO_RS_EVENT_MASK 0x00fe |
215 | #define OOB_TEREDO_EN 0x0001 |
216 | |
ac718b69 |
217 | /* PAL_BDC_CR */ |
218 | #define ALDPS_PROXY_MODE 0x0001 |
219 | |
220 | /* PLA_CONFIG5 */ |
221 | #define LAN_WAKE_EN 0x0002 |
222 | |
223 | /* PLA_LED_FEATURE */ |
224 | #define LED_MODE_MASK 0x0700 |
225 | |
226 | /* PLA_PHY_PWR */ |
227 | #define TX_10M_IDLE_EN 0x0080 |
228 | #define PFM_PWM_SWITCH 0x0040 |
229 | |
230 | /* PLA_MAC_PWR_CTRL */ |
231 | #define D3_CLK_GATED_EN 0x00004000 |
232 | #define MCU_CLK_RATIO 0x07010f07 |
233 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f |
43779f8d |
234 | #define ALDPS_SPDWN_RATIO 0x0f87 |
235 | |
236 | /* PLA_MAC_PWR_CTRL2 */ |
237 | #define EEE_SPDWN_RATIO 0x8007 |
238 | |
239 | /* PLA_MAC_PWR_CTRL3 */ |
240 | #define PKT_AVAIL_SPDWN_EN 0x0100 |
241 | #define SUSPEND_SPDWN_EN 0x0004 |
242 | #define U1U2_SPDWN_EN 0x0002 |
243 | #define L1_SPDWN_EN 0x0001 |
244 | |
245 | /* PLA_MAC_PWR_CTRL4 */ |
246 | #define PWRSAVE_SPDWN_EN 0x1000 |
247 | #define RXDV_SPDWN_EN 0x0800 |
248 | #define TX10MIDLE_EN 0x0100 |
249 | #define TP100_SPDWN_EN 0x0020 |
250 | #define TP500_SPDWN_EN 0x0010 |
251 | #define TP1000_SPDWN_EN 0x0008 |
252 | #define EEE_SPDWN_EN 0x0001 |
ac718b69 |
253 | |
254 | /* PLA_GPHY_INTR_IMR */ |
255 | #define GPHY_STS_MSK 0x0001 |
256 | #define SPEED_DOWN_MSK 0x0002 |
257 | #define SPDWN_RXDV_MSK 0x0004 |
258 | #define SPDWN_LINKCHG_MSK 0x0008 |
259 | |
260 | /* PLA_PHYAR */ |
261 | #define PHYAR_FLAG 0x80000000 |
262 | |
263 | /* PLA_EEE_CR */ |
264 | #define EEE_RX_EN 0x0001 |
265 | #define EEE_TX_EN 0x0002 |
266 | |
43779f8d |
267 | /* PLA_BOOT_CTRL */ |
268 | #define AUTOLOAD_DONE 0x0002 |
269 | |
ac718b69 |
270 | /* USB_DEV_STAT */ |
271 | #define STAT_SPEED_MASK 0x0006 |
272 | #define STAT_SPEED_HIGH 0x0000 |
273 | #define STAT_SPEED_FULL 0x0001 |
274 | |
275 | /* USB_TX_AGG */ |
276 | #define TX_AGG_MAX_THRESHOLD 0x03 |
277 | |
278 | /* USB_RX_BUF_TH */ |
43779f8d |
279 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd |
280 | #define RX_THR_HIGH 0x7a120180 |
43779f8d |
281 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 |
282 | |
283 | /* USB_TX_DMA */ |
284 | #define TEST_MODE_DISABLE 0x00000001 |
285 | #define TX_SIZE_ADJUST1 0x00000100 |
286 | |
287 | /* USB_UPS_CTRL */ |
288 | #define POWER_CUT 0x0100 |
289 | |
290 | /* USB_PM_CTRL_STATUS */ |
8e1f51bd |
291 | #define RESUME_INDICATE 0x0001 |
ac718b69 |
292 | |
293 | /* USB_USB_CTRL */ |
294 | #define RX_AGG_DISABLE 0x0010 |
295 | |
43779f8d |
296 | /* USB_U2P3_CTRL */ |
297 | #define U2P3_ENABLE 0x0001 |
298 | |
299 | /* USB_POWER_CUT */ |
300 | #define PWR_EN 0x0001 |
301 | #define PHASE2_EN 0x0008 |
302 | |
303 | /* USB_MISC_0 */ |
304 | #define PCUT_STATUS 0x0001 |
305 | |
306 | /* USB_RX_EARLY_AGG */ |
307 | #define EARLY_AGG_SUPPER 0x0e832981 |
308 | #define EARLY_AGG_HIGH 0x0e837a12 |
309 | #define EARLY_AGG_SLOW 0x0e83ffff |
310 | |
311 | /* USB_WDT11_CTRL */ |
312 | #define TIMER11_EN 0x0001 |
313 | |
314 | /* USB_LPM_CTRL */ |
315 | #define LPM_TIMER_MASK 0x0c |
316 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ |
317 | #define LPM_TIMER_500US 0x0c /* 500 us */ |
318 | |
319 | /* USB_AFE_CTRL2 */ |
320 | #define SEN_VAL_MASK 0xf800 |
321 | #define SEN_VAL_NORMAL 0xa000 |
322 | #define SEL_RXIDLE 0x0100 |
323 | |
ac718b69 |
324 | /* OCP_ALDPS_CONFIG */ |
325 | #define ENPWRSAVE 0x8000 |
326 | #define ENPDNPS 0x0200 |
327 | #define LINKENA 0x0100 |
328 | #define DIS_SDSAVE 0x0010 |
329 | |
43779f8d |
330 | /* OCP_PHY_STATUS */ |
331 | #define PHY_STAT_MASK 0x0007 |
332 | #define PHY_STAT_LAN_ON 3 |
333 | #define PHY_STAT_PWRDN 5 |
334 | |
335 | /* OCP_POWER_CFG */ |
336 | #define EEE_CLKDIV_EN 0x8000 |
337 | #define EN_ALDPS 0x0004 |
338 | #define EN_10M_PLLOFF 0x0001 |
339 | |
ac718b69 |
340 | /* OCP_EEE_CONFIG1 */ |
341 | #define RG_TXLPI_MSK_HFDUP 0x8000 |
342 | #define RG_MATCLR_EN 0x4000 |
343 | #define EEE_10_CAP 0x2000 |
344 | #define EEE_NWAY_EN 0x1000 |
345 | #define TX_QUIET_EN 0x0200 |
346 | #define RX_QUIET_EN 0x0100 |
347 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ |
348 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
349 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ |
350 | |
351 | /* OCP_EEE_CONFIG2 */ |
352 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ |
353 | #define RG_DACQUIET_EN 0x0400 |
354 | #define RG_LDVQUIET_EN 0x0200 |
355 | #define RG_CKRSEL 0x0020 |
356 | #define RG_EEEPRG_EN 0x0010 |
357 | |
358 | /* OCP_EEE_CONFIG3 */ |
359 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ |
360 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
361 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ |
362 | |
363 | /* OCP_EEE_AR */ |
364 | /* bit[15:14] function */ |
365 | #define FUN_ADDR 0x0000 |
366 | #define FUN_DATA 0x4000 |
367 | /* bit[4:0] device addr */ |
368 | #define DEVICE_ADDR 0x0007 |
369 | |
370 | /* OCP_EEE_DATA */ |
371 | #define EEE_ADDR 0x003C |
372 | #define EEE_DATA 0x0002 |
373 | |
43779f8d |
374 | /* OCP_EEE_CFG */ |
375 | #define CTAP_SHORT_EN 0x0040 |
376 | #define EEE10_EN 0x0010 |
377 | |
378 | /* OCP_DOWN_SPEED */ |
379 | #define EN_10M_BGOFF 0x0080 |
380 | |
381 | /* OCP_EEE_CFG2 */ |
382 | #define MY1000_EEE 0x0004 |
383 | #define MY100_EEE 0x0002 |
384 | |
385 | /* OCP_ADC_CFG */ |
386 | #define CKADSEL_L 0x0100 |
387 | #define ADC_EN 0x0080 |
388 | #define EN_EMI_L 0x0040 |
389 | |
390 | /* SRAM_LPF_CFG */ |
391 | #define LPF_AUTO_TUNE 0x8000 |
392 | |
393 | /* SRAM_10M_AMP1 */ |
394 | #define GDAC_IB_UPALL 0x0008 |
395 | |
396 | /* SRAM_10M_AMP2 */ |
397 | #define AMP_DN 0x0200 |
398 | |
399 | /* SRAM_IMPEDANCE */ |
400 | #define RX_DRIVING_MASK 0x6000 |
401 | |
ac718b69 |
402 | enum rtl_register_content { |
43779f8d |
403 | _1000bps = 0x10, |
ac718b69 |
404 | _100bps = 0x08, |
405 | _10bps = 0x04, |
406 | LINK_STATUS = 0x02, |
407 | FULL_DUP = 0x01, |
408 | }; |
409 | |
ebc2ec48 |
410 | #define RTL8152_MAX_TX 10 |
411 | #define RTL8152_MAX_RX 10 |
40a82917 |
412 | #define INTBUFSIZE 2 |
8e1f51bd |
413 | #define CRC_SIZE 4 |
414 | #define TX_ALIGN 4 |
415 | #define RX_ALIGN 8 |
40a82917 |
416 | |
417 | #define INTR_LINK 0x0004 |
ebc2ec48 |
418 | |
ac718b69 |
419 | #define RTL8152_REQT_READ 0xc0 |
420 | #define RTL8152_REQT_WRITE 0x40 |
421 | #define RTL8152_REQ_GET_REGS 0x05 |
422 | #define RTL8152_REQ_SET_REGS 0x05 |
423 | |
424 | #define BYTE_EN_DWORD 0xff |
425 | #define BYTE_EN_WORD 0x33 |
426 | #define BYTE_EN_BYTE 0x11 |
427 | #define BYTE_EN_SIX_BYTES 0x3f |
428 | #define BYTE_EN_START_MASK 0x0f |
429 | #define BYTE_EN_END_MASK 0xf0 |
430 | |
431 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
432 | #define RTL8152_TX_TIMEOUT (HZ) |
433 | |
434 | /* rtl8152 flags */ |
435 | enum rtl8152_flags { |
436 | RTL8152_UNPLUG = 0, |
ac718b69 |
437 | RTL8152_SET_RX_MODE, |
40a82917 |
438 | WORK_ENABLE, |
439 | RTL8152_LINK_CHG, |
ac718b69 |
440 | }; |
441 | |
442 | /* Define these values to match your device */ |
443 | #define VENDOR_ID_REALTEK 0x0bda |
444 | #define PRODUCT_ID_RTL8152 0x8152 |
43779f8d |
445 | #define PRODUCT_ID_RTL8153 0x8153 |
446 | |
447 | #define VENDOR_ID_SAMSUNG 0x04e8 |
448 | #define PRODUCT_ID_SAMSUNG 0xa101 |
ac718b69 |
449 | |
450 | #define MCU_TYPE_PLA 0x0100 |
451 | #define MCU_TYPE_USB 0x0000 |
452 | |
453 | struct rx_desc { |
500b6d7e |
454 | __le32 opts1; |
ac718b69 |
455 | #define RX_LEN_MASK 0x7fff |
500b6d7e |
456 | __le32 opts2; |
457 | __le32 opts3; |
458 | __le32 opts4; |
459 | __le32 opts5; |
460 | __le32 opts6; |
ac718b69 |
461 | }; |
462 | |
463 | struct tx_desc { |
500b6d7e |
464 | __le32 opts1; |
ac718b69 |
465 | #define TX_FS (1 << 31) /* First segment of a packet */ |
466 | #define TX_LS (1 << 30) /* Final segment of a packet */ |
5bd23881 |
467 | #define TX_LEN_MASK 0x3ffff |
468 | |
500b6d7e |
469 | __le32 opts2; |
5bd23881 |
470 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
471 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ |
472 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ |
473 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ |
ac718b69 |
474 | }; |
475 | |
dff4e8ad |
476 | struct r8152; |
477 | |
ebc2ec48 |
478 | struct rx_agg { |
479 | struct list_head list; |
480 | struct urb *urb; |
dff4e8ad |
481 | struct r8152 *context; |
ebc2ec48 |
482 | void *buffer; |
483 | void *head; |
484 | }; |
485 | |
486 | struct tx_agg { |
487 | struct list_head list; |
488 | struct urb *urb; |
dff4e8ad |
489 | struct r8152 *context; |
ebc2ec48 |
490 | void *buffer; |
491 | void *head; |
492 | u32 skb_num; |
493 | u32 skb_len; |
494 | }; |
495 | |
ac718b69 |
496 | struct r8152 { |
497 | unsigned long flags; |
498 | struct usb_device *udev; |
499 | struct tasklet_struct tl; |
40a82917 |
500 | struct usb_interface *intf; |
ac718b69 |
501 | struct net_device *netdev; |
40a82917 |
502 | struct urb *intr_urb; |
ebc2ec48 |
503 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
504 | struct rx_agg rx_info[RTL8152_MAX_RX]; |
505 | struct list_head rx_done, tx_free; |
506 | struct sk_buff_head tx_queue; |
507 | spinlock_t rx_lock, tx_lock; |
ac718b69 |
508 | struct delayed_work schedule; |
509 | struct mii_if_info mii; |
c81229c9 |
510 | |
511 | struct rtl_ops { |
512 | void (*init)(struct r8152 *); |
513 | int (*enable)(struct r8152 *); |
514 | void (*disable)(struct r8152 *); |
515 | void (*down)(struct r8152 *); |
516 | void (*unload)(struct r8152 *); |
517 | } rtl_ops; |
518 | |
40a82917 |
519 | int intr_interval; |
ac718b69 |
520 | u32 msg_enable; |
dd1b119c |
521 | u32 tx_qlen; |
ac718b69 |
522 | u16 ocp_base; |
40a82917 |
523 | u8 *intr_buff; |
ac718b69 |
524 | u8 version; |
525 | u8 speed; |
526 | }; |
527 | |
528 | enum rtl_version { |
529 | RTL_VER_UNKNOWN = 0, |
530 | RTL_VER_01, |
43779f8d |
531 | RTL_VER_02, |
532 | RTL_VER_03, |
533 | RTL_VER_04, |
534 | RTL_VER_05, |
535 | RTL_VER_MAX |
ac718b69 |
536 | }; |
537 | |
538 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
539 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. |
540 | */ |
541 | static const int multicast_filter_limit = 32; |
ebc2ec48 |
542 | static unsigned int rx_buf_sz = 16384; |
ac718b69 |
543 | |
544 | static |
545 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) |
546 | { |
31787f53 |
547 | int ret; |
548 | void *tmp; |
549 | |
550 | tmp = kmalloc(size, GFP_KERNEL); |
551 | if (!tmp) |
552 | return -ENOMEM; |
553 | |
554 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), |
ac718b69 |
555 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
31787f53 |
556 | value, index, tmp, size, 500); |
557 | |
558 | memcpy(data, tmp, size); |
559 | kfree(tmp); |
560 | |
561 | return ret; |
ac718b69 |
562 | } |
563 | |
564 | static |
565 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) |
566 | { |
31787f53 |
567 | int ret; |
568 | void *tmp; |
569 | |
570 | tmp = kmalloc(size, GFP_KERNEL); |
571 | if (!tmp) |
572 | return -ENOMEM; |
573 | |
574 | memcpy(tmp, data, size); |
575 | |
576 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
ac718b69 |
577 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
31787f53 |
578 | value, index, tmp, size, 500); |
579 | |
580 | kfree(tmp); |
581 | return ret; |
ac718b69 |
582 | } |
583 | |
584 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, |
585 | void *data, u16 type) |
586 | { |
45f4a19f |
587 | u16 limit = 64; |
588 | int ret = 0; |
ac718b69 |
589 | |
590 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
591 | return -ENODEV; |
592 | |
593 | /* both size and indix must be 4 bytes align */ |
594 | if ((size & 3) || !size || (index & 3) || !data) |
595 | return -EPERM; |
596 | |
597 | if ((u32)index + (u32)size > 0xffff) |
598 | return -EPERM; |
599 | |
600 | while (size) { |
601 | if (size > limit) { |
602 | ret = get_registers(tp, index, type, limit, data); |
603 | if (ret < 0) |
604 | break; |
605 | |
606 | index += limit; |
607 | data += limit; |
608 | size -= limit; |
609 | } else { |
610 | ret = get_registers(tp, index, type, size, data); |
611 | if (ret < 0) |
612 | break; |
613 | |
614 | index += size; |
615 | data += size; |
616 | size = 0; |
617 | break; |
618 | } |
619 | } |
620 | |
621 | return ret; |
622 | } |
623 | |
624 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, |
625 | u16 size, void *data, u16 type) |
626 | { |
45f4a19f |
627 | int ret; |
628 | u16 byteen_start, byteen_end, byen; |
629 | u16 limit = 512; |
ac718b69 |
630 | |
631 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
632 | return -ENODEV; |
633 | |
634 | /* both size and indix must be 4 bytes align */ |
635 | if ((size & 3) || !size || (index & 3) || !data) |
636 | return -EPERM; |
637 | |
638 | if ((u32)index + (u32)size > 0xffff) |
639 | return -EPERM; |
640 | |
641 | byteen_start = byteen & BYTE_EN_START_MASK; |
642 | byteen_end = byteen & BYTE_EN_END_MASK; |
643 | |
644 | byen = byteen_start | (byteen_start << 4); |
645 | ret = set_registers(tp, index, type | byen, 4, data); |
646 | if (ret < 0) |
647 | goto error1; |
648 | |
649 | index += 4; |
650 | data += 4; |
651 | size -= 4; |
652 | |
653 | if (size) { |
654 | size -= 4; |
655 | |
656 | while (size) { |
657 | if (size > limit) { |
658 | ret = set_registers(tp, index, |
659 | type | BYTE_EN_DWORD, |
660 | limit, data); |
661 | if (ret < 0) |
662 | goto error1; |
663 | |
664 | index += limit; |
665 | data += limit; |
666 | size -= limit; |
667 | } else { |
668 | ret = set_registers(tp, index, |
669 | type | BYTE_EN_DWORD, |
670 | size, data); |
671 | if (ret < 0) |
672 | goto error1; |
673 | |
674 | index += size; |
675 | data += size; |
676 | size = 0; |
677 | break; |
678 | } |
679 | } |
680 | |
681 | byen = byteen_end | (byteen_end >> 4); |
682 | ret = set_registers(tp, index, type | byen, 4, data); |
683 | if (ret < 0) |
684 | goto error1; |
685 | } |
686 | |
687 | error1: |
688 | return ret; |
689 | } |
690 | |
691 | static inline |
692 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) |
693 | { |
694 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); |
695 | } |
696 | |
697 | static inline |
698 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) |
699 | { |
700 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); |
701 | } |
702 | |
703 | static inline |
704 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) |
705 | { |
706 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); |
707 | } |
708 | |
709 | static inline |
710 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) |
711 | { |
712 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); |
713 | } |
714 | |
715 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) |
716 | { |
c8826de8 |
717 | __le32 data; |
ac718b69 |
718 | |
c8826de8 |
719 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 |
720 | |
721 | return __le32_to_cpu(data); |
722 | } |
723 | |
724 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) |
725 | { |
c8826de8 |
726 | __le32 tmp = __cpu_to_le32(data); |
727 | |
728 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); |
ac718b69 |
729 | } |
730 | |
731 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) |
732 | { |
733 | u32 data; |
c8826de8 |
734 | __le32 tmp; |
ac718b69 |
735 | u8 shift = index & 2; |
736 | |
737 | index &= ~3; |
738 | |
c8826de8 |
739 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 |
740 | |
c8826de8 |
741 | data = __le32_to_cpu(tmp); |
ac718b69 |
742 | data >>= (shift * 8); |
743 | data &= 0xffff; |
744 | |
745 | return (u16)data; |
746 | } |
747 | |
748 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) |
749 | { |
c8826de8 |
750 | u32 mask = 0xffff; |
751 | __le32 tmp; |
ac718b69 |
752 | u16 byen = BYTE_EN_WORD; |
753 | u8 shift = index & 2; |
754 | |
755 | data &= mask; |
756 | |
757 | if (index & 2) { |
758 | byen <<= shift; |
759 | mask <<= (shift * 8); |
760 | data <<= (shift * 8); |
761 | index &= ~3; |
762 | } |
763 | |
c8826de8 |
764 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 |
765 | |
c8826de8 |
766 | data |= __le32_to_cpu(tmp) & ~mask; |
767 | tmp = __cpu_to_le32(data); |
ac718b69 |
768 | |
c8826de8 |
769 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 |
770 | } |
771 | |
772 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) |
773 | { |
774 | u32 data; |
c8826de8 |
775 | __le32 tmp; |
ac718b69 |
776 | u8 shift = index & 3; |
777 | |
778 | index &= ~3; |
779 | |
c8826de8 |
780 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 |
781 | |
c8826de8 |
782 | data = __le32_to_cpu(tmp); |
ac718b69 |
783 | data >>= (shift * 8); |
784 | data &= 0xff; |
785 | |
786 | return (u8)data; |
787 | } |
788 | |
789 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) |
790 | { |
c8826de8 |
791 | u32 mask = 0xff; |
792 | __le32 tmp; |
ac718b69 |
793 | u16 byen = BYTE_EN_BYTE; |
794 | u8 shift = index & 3; |
795 | |
796 | data &= mask; |
797 | |
798 | if (index & 3) { |
799 | byen <<= shift; |
800 | mask <<= (shift * 8); |
801 | data <<= (shift * 8); |
802 | index &= ~3; |
803 | } |
804 | |
c8826de8 |
805 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 |
806 | |
c8826de8 |
807 | data |= __le32_to_cpu(tmp) & ~mask; |
808 | tmp = __cpu_to_le32(data); |
ac718b69 |
809 | |
c8826de8 |
810 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 |
811 | } |
812 | |
ac244d3e |
813 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a |
814 | { |
815 | u16 ocp_base, ocp_index; |
816 | |
817 | ocp_base = addr & 0xf000; |
818 | if (ocp_base != tp->ocp_base) { |
819 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); |
820 | tp->ocp_base = ocp_base; |
821 | } |
822 | |
823 | ocp_index = (addr & 0x0fff) | 0xb000; |
ac244d3e |
824 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a |
825 | } |
826 | |
ac244d3e |
827 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 |
828 | { |
ac244d3e |
829 | u16 ocp_base, ocp_index; |
ac718b69 |
830 | |
ac244d3e |
831 | ocp_base = addr & 0xf000; |
832 | if (ocp_base != tp->ocp_base) { |
833 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); |
834 | tp->ocp_base = ocp_base; |
ac718b69 |
835 | } |
ac244d3e |
836 | |
837 | ocp_index = (addr & 0x0fff) | 0xb000; |
838 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); |
ac718b69 |
839 | } |
840 | |
ac244d3e |
841 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 |
842 | { |
ac244d3e |
843 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
844 | } |
ac718b69 |
845 | |
ac244d3e |
846 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
847 | { |
848 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); |
ac718b69 |
849 | } |
850 | |
43779f8d |
851 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
852 | { |
853 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); |
854 | ocp_reg_write(tp, OCP_SRAM_DATA, data); |
855 | } |
856 | |
857 | static u16 sram_read(struct r8152 *tp, u16 addr) |
858 | { |
859 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); |
860 | return ocp_reg_read(tp, OCP_SRAM_DATA); |
861 | } |
862 | |
ac718b69 |
863 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
864 | { |
865 | struct r8152 *tp = netdev_priv(netdev); |
866 | |
867 | if (phy_id != R8152_PHY_ID) |
868 | return -EINVAL; |
869 | |
870 | return r8152_mdio_read(tp, reg); |
871 | } |
872 | |
873 | static |
874 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) |
875 | { |
876 | struct r8152 *tp = netdev_priv(netdev); |
877 | |
878 | if (phy_id != R8152_PHY_ID) |
879 | return; |
880 | |
881 | r8152_mdio_write(tp, reg, val); |
882 | } |
883 | |
ebc2ec48 |
884 | static |
885 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); |
886 | |
ac718b69 |
887 | static inline void set_ethernet_addr(struct r8152 *tp) |
888 | { |
889 | struct net_device *dev = tp->netdev; |
31787f53 |
890 | u8 node_id[8] = {0}; |
ac718b69 |
891 | |
31787f53 |
892 | if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0) |
ac718b69 |
893 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
894 | else { |
895 | memcpy(dev->dev_addr, node_id, dev->addr_len); |
896 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
897 | } |
ac718b69 |
898 | } |
899 | |
900 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
901 | { |
902 | struct r8152 *tp = netdev_priv(netdev); |
903 | struct sockaddr *addr = p; |
904 | |
905 | if (!is_valid_ether_addr(addr->sa_data)) |
906 | return -EADDRNOTAVAIL; |
907 | |
908 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
909 | |
910 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); |
911 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); |
912 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
913 | |
914 | return 0; |
915 | } |
916 | |
ac718b69 |
917 | static struct net_device_stats *rtl8152_get_stats(struct net_device *dev) |
918 | { |
919 | return &dev->stats; |
920 | } |
921 | |
922 | static void read_bulk_callback(struct urb *urb) |
923 | { |
ac718b69 |
924 | struct net_device *netdev; |
a5a4f468 |
925 | unsigned long flags; |
ac718b69 |
926 | int status = urb->status; |
ebc2ec48 |
927 | struct rx_agg *agg; |
928 | struct r8152 *tp; |
ac718b69 |
929 | int result; |
ac718b69 |
930 | |
ebc2ec48 |
931 | agg = urb->context; |
932 | if (!agg) |
933 | return; |
934 | |
935 | tp = agg->context; |
ac718b69 |
936 | if (!tp) |
937 | return; |
ebc2ec48 |
938 | |
ac718b69 |
939 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
940 | return; |
ebc2ec48 |
941 | |
942 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
943 | return; |
944 | |
ac718b69 |
945 | netdev = tp->netdev; |
7559fb2f |
946 | |
947 | /* When link down, the driver would cancel all bulks. */ |
948 | /* This avoid the re-submitting bulk */ |
ebc2ec48 |
949 | if (!netif_carrier_ok(netdev)) |
ac718b69 |
950 | return; |
951 | |
ac718b69 |
952 | switch (status) { |
953 | case 0: |
ebc2ec48 |
954 | if (urb->actual_length < ETH_ZLEN) |
955 | break; |
956 | |
a5a4f468 |
957 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 |
958 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 |
959 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 |
960 | tasklet_schedule(&tp->tl); |
961 | return; |
ac718b69 |
962 | case -ESHUTDOWN: |
963 | set_bit(RTL8152_UNPLUG, &tp->flags); |
964 | netif_device_detach(tp->netdev); |
ebc2ec48 |
965 | return; |
ac718b69 |
966 | case -ENOENT: |
967 | return; /* the urb is in unlink state */ |
968 | case -ETIME: |
969 | pr_warn_ratelimited("may be reset is needed?..\n"); |
ebc2ec48 |
970 | break; |
ac718b69 |
971 | default: |
972 | pr_warn_ratelimited("Rx status %d\n", status); |
ebc2ec48 |
973 | break; |
ac718b69 |
974 | } |
975 | |
ebc2ec48 |
976 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 |
977 | if (result == -ENODEV) { |
978 | netif_device_detach(tp->netdev); |
979 | } else if (result) { |
a5a4f468 |
980 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 |
981 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 |
982 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 |
983 | tasklet_schedule(&tp->tl); |
ac718b69 |
984 | } |
ac718b69 |
985 | } |
986 | |
ebc2ec48 |
987 | static void write_bulk_callback(struct urb *urb) |
ac718b69 |
988 | { |
ebc2ec48 |
989 | struct net_device_stats *stats; |
a5a4f468 |
990 | unsigned long flags; |
ebc2ec48 |
991 | struct tx_agg *agg; |
ac718b69 |
992 | struct r8152 *tp; |
ebc2ec48 |
993 | int status = urb->status; |
ac718b69 |
994 | |
ebc2ec48 |
995 | agg = urb->context; |
996 | if (!agg) |
ac718b69 |
997 | return; |
998 | |
ebc2ec48 |
999 | tp = agg->context; |
1000 | if (!tp) |
1001 | return; |
1002 | |
1003 | stats = rtl8152_get_stats(tp->netdev); |
1004 | if (status) { |
1005 | pr_warn_ratelimited("Tx status %d\n", status); |
1006 | stats->tx_errors += agg->skb_num; |
ac718b69 |
1007 | } else { |
ebc2ec48 |
1008 | stats->tx_packets += agg->skb_num; |
1009 | stats->tx_bytes += agg->skb_len; |
ac718b69 |
1010 | } |
1011 | |
a5a4f468 |
1012 | spin_lock_irqsave(&tp->tx_lock, flags); |
ebc2ec48 |
1013 | list_add_tail(&agg->list, &tp->tx_free); |
a5a4f468 |
1014 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
ebc2ec48 |
1015 | |
1016 | if (!netif_carrier_ok(tp->netdev)) |
1017 | return; |
1018 | |
1019 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
1020 | return; |
1021 | |
1022 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1023 | return; |
1024 | |
1025 | if (!skb_queue_empty(&tp->tx_queue)) |
1026 | tasklet_schedule(&tp->tl); |
ac718b69 |
1027 | } |
1028 | |
40a82917 |
1029 | static void intr_callback(struct urb *urb) |
1030 | { |
1031 | struct r8152 *tp; |
500b6d7e |
1032 | __le16 *d; |
40a82917 |
1033 | int status = urb->status; |
1034 | int res; |
1035 | |
1036 | tp = urb->context; |
1037 | if (!tp) |
1038 | return; |
1039 | |
1040 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
1041 | return; |
1042 | |
1043 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1044 | return; |
1045 | |
1046 | switch (status) { |
1047 | case 0: /* success */ |
1048 | break; |
1049 | case -ECONNRESET: /* unlink */ |
1050 | case -ESHUTDOWN: |
1051 | netif_device_detach(tp->netdev); |
1052 | case -ENOENT: |
1053 | return; |
1054 | case -EOVERFLOW: |
1055 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); |
1056 | goto resubmit; |
1057 | /* -EPIPE: should clear the halt */ |
1058 | default: |
1059 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); |
1060 | goto resubmit; |
1061 | } |
1062 | |
1063 | d = urb->transfer_buffer; |
1064 | if (INTR_LINK & __le16_to_cpu(d[0])) { |
1065 | if (!(tp->speed & LINK_STATUS)) { |
1066 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1067 | schedule_delayed_work(&tp->schedule, 0); |
1068 | } |
1069 | } else { |
1070 | if (tp->speed & LINK_STATUS) { |
1071 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1072 | schedule_delayed_work(&tp->schedule, 0); |
1073 | } |
1074 | } |
1075 | |
1076 | resubmit: |
1077 | res = usb_submit_urb(urb, GFP_ATOMIC); |
1078 | if (res == -ENODEV) |
1079 | netif_device_detach(tp->netdev); |
1080 | else if (res) |
1081 | netif_err(tp, intr, tp->netdev, |
1082 | "can't resubmit intr, status %d\n", res); |
1083 | } |
1084 | |
ebc2ec48 |
1085 | static inline void *rx_agg_align(void *data) |
1086 | { |
8e1f51bd |
1087 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 |
1088 | } |
1089 | |
1090 | static inline void *tx_agg_align(void *data) |
1091 | { |
8e1f51bd |
1092 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 |
1093 | } |
1094 | |
1095 | static void free_all_mem(struct r8152 *tp) |
1096 | { |
1097 | int i; |
1098 | |
1099 | for (i = 0; i < RTL8152_MAX_RX; i++) { |
1100 | if (tp->rx_info[i].urb) { |
1101 | usb_free_urb(tp->rx_info[i].urb); |
1102 | tp->rx_info[i].urb = NULL; |
1103 | } |
1104 | |
1105 | if (tp->rx_info[i].buffer) { |
1106 | kfree(tp->rx_info[i].buffer); |
1107 | tp->rx_info[i].buffer = NULL; |
1108 | tp->rx_info[i].head = NULL; |
1109 | } |
1110 | } |
1111 | |
1112 | for (i = 0; i < RTL8152_MAX_TX; i++) { |
1113 | if (tp->tx_info[i].urb) { |
1114 | usb_free_urb(tp->tx_info[i].urb); |
1115 | tp->tx_info[i].urb = NULL; |
1116 | } |
1117 | |
1118 | if (tp->tx_info[i].buffer) { |
1119 | kfree(tp->tx_info[i].buffer); |
1120 | tp->tx_info[i].buffer = NULL; |
1121 | tp->tx_info[i].head = NULL; |
1122 | } |
1123 | } |
40a82917 |
1124 | |
1125 | if (tp->intr_urb) { |
1126 | usb_free_urb(tp->intr_urb); |
1127 | tp->intr_urb = NULL; |
1128 | } |
1129 | |
1130 | if (tp->intr_buff) { |
1131 | kfree(tp->intr_buff); |
1132 | tp->intr_buff = NULL; |
1133 | } |
ebc2ec48 |
1134 | } |
1135 | |
1136 | static int alloc_all_mem(struct r8152 *tp) |
1137 | { |
1138 | struct net_device *netdev = tp->netdev; |
40a82917 |
1139 | struct usb_interface *intf = tp->intf; |
1140 | struct usb_host_interface *alt = intf->cur_altsetting; |
1141 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; |
ebc2ec48 |
1142 | struct urb *urb; |
1143 | int node, i; |
1144 | u8 *buf; |
1145 | |
1146 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; |
1147 | |
1148 | spin_lock_init(&tp->rx_lock); |
1149 | spin_lock_init(&tp->tx_lock); |
1150 | INIT_LIST_HEAD(&tp->rx_done); |
1151 | INIT_LIST_HEAD(&tp->tx_free); |
1152 | skb_queue_head_init(&tp->tx_queue); |
1153 | |
1154 | for (i = 0; i < RTL8152_MAX_RX; i++) { |
1155 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
1156 | if (!buf) |
1157 | goto err1; |
1158 | |
1159 | if (buf != rx_agg_align(buf)) { |
1160 | kfree(buf); |
8e1f51bd |
1161 | buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, |
1162 | node); |
ebc2ec48 |
1163 | if (!buf) |
1164 | goto err1; |
1165 | } |
1166 | |
1167 | urb = usb_alloc_urb(0, GFP_KERNEL); |
1168 | if (!urb) { |
1169 | kfree(buf); |
1170 | goto err1; |
1171 | } |
1172 | |
1173 | INIT_LIST_HEAD(&tp->rx_info[i].list); |
1174 | tp->rx_info[i].context = tp; |
1175 | tp->rx_info[i].urb = urb; |
1176 | tp->rx_info[i].buffer = buf; |
1177 | tp->rx_info[i].head = rx_agg_align(buf); |
1178 | } |
1179 | |
1180 | for (i = 0; i < RTL8152_MAX_TX; i++) { |
1181 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
1182 | if (!buf) |
1183 | goto err1; |
1184 | |
1185 | if (buf != tx_agg_align(buf)) { |
1186 | kfree(buf); |
8e1f51bd |
1187 | buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, |
1188 | node); |
ebc2ec48 |
1189 | if (!buf) |
1190 | goto err1; |
1191 | } |
1192 | |
1193 | urb = usb_alloc_urb(0, GFP_KERNEL); |
1194 | if (!urb) { |
1195 | kfree(buf); |
1196 | goto err1; |
1197 | } |
1198 | |
1199 | INIT_LIST_HEAD(&tp->tx_info[i].list); |
1200 | tp->tx_info[i].context = tp; |
1201 | tp->tx_info[i].urb = urb; |
1202 | tp->tx_info[i].buffer = buf; |
1203 | tp->tx_info[i].head = tx_agg_align(buf); |
1204 | |
1205 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); |
1206 | } |
1207 | |
40a82917 |
1208 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1209 | if (!tp->intr_urb) |
1210 | goto err1; |
1211 | |
1212 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); |
1213 | if (!tp->intr_buff) |
1214 | goto err1; |
1215 | |
1216 | tp->intr_interval = (int)ep_intr->desc.bInterval; |
1217 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), |
1218 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1219 | tp, tp->intr_interval); |
1220 | |
ebc2ec48 |
1221 | return 0; |
1222 | |
1223 | err1: |
1224 | free_all_mem(tp); |
1225 | return -ENOMEM; |
1226 | } |
1227 | |
0de98f6c |
1228 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1229 | { |
1230 | struct tx_agg *agg = NULL; |
1231 | unsigned long flags; |
1232 | |
1233 | spin_lock_irqsave(&tp->tx_lock, flags); |
1234 | if (!list_empty(&tp->tx_free)) { |
1235 | struct list_head *cursor; |
1236 | |
1237 | cursor = tp->tx_free.next; |
1238 | list_del_init(cursor); |
1239 | agg = list_entry(cursor, struct tx_agg, list); |
1240 | } |
1241 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
1242 | |
1243 | return agg; |
1244 | } |
1245 | |
5bd23881 |
1246 | static void |
1247 | r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) |
1248 | { |
1249 | memset(desc, 0, sizeof(*desc)); |
1250 | |
1251 | desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); |
1252 | |
1253 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
1254 | __be16 protocol; |
1255 | u8 ip_protocol; |
1256 | u32 opts2 = 0; |
1257 | |
1258 | if (skb->protocol == htons(ETH_P_8021Q)) |
1259 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; |
1260 | else |
1261 | protocol = skb->protocol; |
1262 | |
1263 | switch (protocol) { |
1264 | case htons(ETH_P_IP): |
1265 | opts2 |= IPV4_CS; |
1266 | ip_protocol = ip_hdr(skb)->protocol; |
1267 | break; |
1268 | |
1269 | case htons(ETH_P_IPV6): |
1270 | opts2 |= IPV6_CS; |
1271 | ip_protocol = ipv6_hdr(skb)->nexthdr; |
1272 | break; |
1273 | |
1274 | default: |
1275 | ip_protocol = IPPROTO_RAW; |
1276 | break; |
1277 | } |
1278 | |
1279 | if (ip_protocol == IPPROTO_TCP) { |
1280 | opts2 |= TCP_CS; |
1281 | opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; |
1282 | } else if (ip_protocol == IPPROTO_UDP) { |
1283 | opts2 |= UDP_CS; |
1284 | } else { |
1285 | WARN_ON_ONCE(1); |
1286 | } |
1287 | |
1288 | desc->opts2 = cpu_to_le32(opts2); |
1289 | } |
1290 | } |
1291 | |
b1379d9a |
1292 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1293 | { |
7937f9e5 |
1294 | int remain; |
b1379d9a |
1295 | u8 *tx_data; |
1296 | |
1297 | tx_data = agg->head; |
1298 | agg->skb_num = agg->skb_len = 0; |
7937f9e5 |
1299 | remain = rx_buf_sz; |
b1379d9a |
1300 | |
7937f9e5 |
1301 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a |
1302 | struct tx_desc *tx_desc; |
1303 | struct sk_buff *skb; |
1304 | unsigned int len; |
1305 | |
1306 | skb = skb_dequeue(&tp->tx_queue); |
1307 | if (!skb) |
1308 | break; |
1309 | |
7937f9e5 |
1310 | remain -= sizeof(*tx_desc); |
b1379d9a |
1311 | len = skb->len; |
1312 | if (remain < len) { |
1313 | skb_queue_head(&tp->tx_queue, skb); |
1314 | break; |
1315 | } |
1316 | |
7937f9e5 |
1317 | tx_data = tx_agg_align(tx_data); |
b1379d9a |
1318 | tx_desc = (struct tx_desc *)tx_data; |
1319 | tx_data += sizeof(*tx_desc); |
1320 | |
1321 | r8152_tx_csum(tp, tx_desc, skb); |
1322 | memcpy(tx_data, skb->data, len); |
1323 | agg->skb_num++; |
1324 | agg->skb_len += len; |
1325 | dev_kfree_skb_any(skb); |
1326 | |
7937f9e5 |
1327 | tx_data += len; |
1328 | remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a |
1329 | } |
1330 | |
dd1b119c |
1331 | netif_tx_lock(tp->netdev); |
1332 | |
1333 | if (netif_queue_stopped(tp->netdev) && |
1334 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) |
1335 | netif_wake_queue(tp->netdev); |
1336 | |
1337 | netif_tx_unlock(tp->netdev); |
1338 | |
b1379d9a |
1339 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1340 | agg->head, (int)(tx_data - (u8 *)agg->head), |
1341 | (usb_complete_t)write_bulk_callback, agg); |
1342 | |
1343 | return usb_submit_urb(agg->urb, GFP_ATOMIC); |
1344 | } |
1345 | |
ebc2ec48 |
1346 | static void rx_bottom(struct r8152 *tp) |
1347 | { |
a5a4f468 |
1348 | unsigned long flags; |
ebc2ec48 |
1349 | struct list_head *cursor, *next; |
ebc2ec48 |
1350 | |
a5a4f468 |
1351 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 |
1352 | list_for_each_safe(cursor, next, &tp->rx_done) { |
43a4478d |
1353 | struct rx_desc *rx_desc; |
1354 | struct rx_agg *agg; |
43a4478d |
1355 | int len_used = 0; |
1356 | struct urb *urb; |
1357 | u8 *rx_data; |
1358 | int ret; |
1359 | |
ebc2ec48 |
1360 | list_del_init(cursor); |
a5a4f468 |
1361 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 |
1362 | |
1363 | agg = list_entry(cursor, struct rx_agg, list); |
1364 | urb = agg->urb; |
0de98f6c |
1365 | if (urb->actual_length < ETH_ZLEN) |
1366 | goto submit; |
ebc2ec48 |
1367 | |
ebc2ec48 |
1368 | rx_desc = agg->head; |
1369 | rx_data = agg->head; |
7937f9e5 |
1370 | len_used += sizeof(struct rx_desc); |
ebc2ec48 |
1371 | |
7937f9e5 |
1372 | while (urb->actual_length > len_used) { |
43a4478d |
1373 | struct net_device *netdev = tp->netdev; |
1374 | struct net_device_stats *stats; |
7937f9e5 |
1375 | unsigned int pkt_len; |
43a4478d |
1376 | struct sk_buff *skb; |
1377 | |
7937f9e5 |
1378 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 |
1379 | if (pkt_len < ETH_ZLEN) |
1380 | break; |
1381 | |
7937f9e5 |
1382 | len_used += pkt_len; |
1383 | if (urb->actual_length < len_used) |
1384 | break; |
1385 | |
43a4478d |
1386 | stats = rtl8152_get_stats(netdev); |
1387 | |
8e1f51bd |
1388 | pkt_len -= CRC_SIZE; |
ebc2ec48 |
1389 | rx_data += sizeof(struct rx_desc); |
1390 | |
1391 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); |
1392 | if (!skb) { |
1393 | stats->rx_dropped++; |
1394 | break; |
1395 | } |
1396 | memcpy(skb->data, rx_data, pkt_len); |
1397 | skb_put(skb, pkt_len); |
1398 | skb->protocol = eth_type_trans(skb, netdev); |
1399 | netif_rx(skb); |
1400 | stats->rx_packets++; |
1401 | stats->rx_bytes += pkt_len; |
1402 | |
8e1f51bd |
1403 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 |
1404 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 |
1405 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 |
1406 | len_used += sizeof(struct rx_desc); |
ebc2ec48 |
1407 | } |
1408 | |
0de98f6c |
1409 | submit: |
ebc2ec48 |
1410 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
a5a4f468 |
1411 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 |
1412 | if (ret && ret != -ENODEV) { |
1413 | list_add_tail(&agg->list, next); |
1414 | tasklet_schedule(&tp->tl); |
1415 | } |
1416 | } |
a5a4f468 |
1417 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 |
1418 | } |
1419 | |
1420 | static void tx_bottom(struct r8152 *tp) |
1421 | { |
ebc2ec48 |
1422 | int res; |
1423 | |
b1379d9a |
1424 | do { |
1425 | struct tx_agg *agg; |
ebc2ec48 |
1426 | |
b1379d9a |
1427 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 |
1428 | break; |
1429 | |
b1379d9a |
1430 | agg = r8152_get_tx_agg(tp); |
1431 | if (!agg) |
ebc2ec48 |
1432 | break; |
ebc2ec48 |
1433 | |
b1379d9a |
1434 | res = r8152_tx_agg_fill(tp, agg); |
1435 | if (res) { |
1436 | struct net_device_stats *stats; |
1437 | struct net_device *netdev; |
1438 | unsigned long flags; |
ebc2ec48 |
1439 | |
b1379d9a |
1440 | netdev = tp->netdev; |
1441 | stats = rtl8152_get_stats(netdev); |
ebc2ec48 |
1442 | |
b1379d9a |
1443 | if (res == -ENODEV) { |
1444 | netif_device_detach(netdev); |
1445 | } else { |
1446 | netif_warn(tp, tx_err, netdev, |
1447 | "failed tx_urb %d\n", res); |
1448 | stats->tx_dropped += agg->skb_num; |
1449 | spin_lock_irqsave(&tp->tx_lock, flags); |
1450 | list_add_tail(&agg->list, &tp->tx_free); |
1451 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
1452 | } |
ebc2ec48 |
1453 | } |
b1379d9a |
1454 | } while (res == 0); |
ebc2ec48 |
1455 | } |
1456 | |
1457 | static void bottom_half(unsigned long data) |
ac718b69 |
1458 | { |
1459 | struct r8152 *tp; |
ac718b69 |
1460 | |
ebc2ec48 |
1461 | tp = (struct r8152 *)data; |
1462 | |
1463 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1464 | return; |
1465 | |
1466 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
ac718b69 |
1467 | return; |
ebc2ec48 |
1468 | |
7559fb2f |
1469 | /* When link down, the driver would cancel all bulks. */ |
1470 | /* This avoid the re-submitting bulk */ |
ebc2ec48 |
1471 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 |
1472 | return; |
ebc2ec48 |
1473 | |
1474 | rx_bottom(tp); |
1475 | tx_bottom(tp); |
1476 | } |
1477 | |
1478 | static |
1479 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) |
1480 | { |
1481 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
1482 | agg->head, rx_buf_sz, |
1483 | (usb_complete_t)read_bulk_callback, agg); |
1484 | |
1485 | return usb_submit_urb(agg->urb, mem_flags); |
ac718b69 |
1486 | } |
1487 | |
1488 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1489 | { |
1490 | struct r8152 *tp = netdev_priv(netdev); |
ebc2ec48 |
1491 | int i; |
1492 | |
ac718b69 |
1493 | netif_warn(tp, tx_err, netdev, "Tx timeout.\n"); |
ebc2ec48 |
1494 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1495 | usb_unlink_urb(tp->tx_info[i].urb); |
ac718b69 |
1496 | } |
1497 | |
1498 | static void rtl8152_set_rx_mode(struct net_device *netdev) |
1499 | { |
1500 | struct r8152 *tp = netdev_priv(netdev); |
1501 | |
40a82917 |
1502 | if (tp->speed & LINK_STATUS) { |
ac718b69 |
1503 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 |
1504 | schedule_delayed_work(&tp->schedule, 0); |
1505 | } |
ac718b69 |
1506 | } |
1507 | |
1508 | static void _rtl8152_set_rx_mode(struct net_device *netdev) |
1509 | { |
1510 | struct r8152 *tp = netdev_priv(netdev); |
31787f53 |
1511 | u32 mc_filter[2]; /* Multicast hash filter */ |
1512 | __le32 tmp[2]; |
ac718b69 |
1513 | u32 ocp_data; |
1514 | |
ac718b69 |
1515 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1516 | netif_stop_queue(netdev); |
1517 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
1518 | ocp_data &= ~RCR_ACPT_ALL; |
1519 | ocp_data |= RCR_AB | RCR_APM; |
1520 | |
1521 | if (netdev->flags & IFF_PROMISC) { |
1522 | /* Unconditionally log net taps. */ |
1523 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); |
1524 | ocp_data |= RCR_AM | RCR_AAP; |
1525 | mc_filter[1] = mc_filter[0] = 0xffffffff; |
1526 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
1527 | (netdev->flags & IFF_ALLMULTI)) { |
1528 | /* Too many to filter perfectly -- accept all multicasts. */ |
1529 | ocp_data |= RCR_AM; |
1530 | mc_filter[1] = mc_filter[0] = 0xffffffff; |
1531 | } else { |
1532 | struct netdev_hw_addr *ha; |
1533 | |
1534 | mc_filter[1] = mc_filter[0] = 0; |
1535 | netdev_for_each_mc_addr(ha, netdev) { |
1536 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; |
1537 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
1538 | ocp_data |= RCR_AM; |
1539 | } |
1540 | } |
1541 | |
31787f53 |
1542 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1543 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); |
ac718b69 |
1544 | |
31787f53 |
1545 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 |
1546 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1547 | netif_wake_queue(netdev); |
ac718b69 |
1548 | } |
1549 | |
1550 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
1551 | struct net_device *netdev) |
1552 | { |
1553 | struct r8152 *tp = netdev_priv(netdev); |
ac718b69 |
1554 | |
ebc2ec48 |
1555 | skb_tx_timestamp(skb); |
ac718b69 |
1556 | |
61598788 |
1557 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 |
1558 | |
dd1b119c |
1559 | if (list_empty(&tp->tx_free) && |
1560 | skb_queue_len(&tp->tx_queue) > tp->tx_qlen) |
1561 | netif_stop_queue(netdev); |
1562 | |
61598788 |
1563 | if (!list_empty(&tp->tx_free)) |
1564 | tasklet_schedule(&tp->tl); |
ac718b69 |
1565 | |
1566 | return NETDEV_TX_OK; |
1567 | } |
1568 | |
1569 | static void r8152b_reset_packet_filter(struct r8152 *tp) |
1570 | { |
1571 | u32 ocp_data; |
1572 | |
1573 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); |
1574 | ocp_data &= ~FMC_FCR_MCU_EN; |
1575 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); |
1576 | ocp_data |= FMC_FCR_MCU_EN; |
1577 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); |
1578 | } |
1579 | |
1580 | static void rtl8152_nic_reset(struct r8152 *tp) |
1581 | { |
1582 | int i; |
1583 | |
1584 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); |
1585 | |
1586 | for (i = 0; i < 1000; i++) { |
1587 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) |
1588 | break; |
1589 | udelay(100); |
1590 | } |
1591 | } |
1592 | |
dd1b119c |
1593 | static void set_tx_qlen(struct r8152 *tp) |
1594 | { |
1595 | struct net_device *netdev = tp->netdev; |
1596 | |
1597 | tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
1598 | sizeof(struct tx_desc)); |
1599 | } |
1600 | |
ac718b69 |
1601 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1602 | { |
1603 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); |
1604 | } |
1605 | |
507605a8 |
1606 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 |
1607 | { |
ebc2ec48 |
1608 | u32 ocp_data; |
ac718b69 |
1609 | u8 speed; |
1610 | |
1611 | speed = rtl8152_get_speed(tp); |
ebc2ec48 |
1612 | if (speed & _10bps) { |
ac718b69 |
1613 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 |
1614 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 |
1615 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1616 | } else { |
1617 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 |
1618 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 |
1619 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1620 | } |
507605a8 |
1621 | } |
1622 | |
1623 | static int rtl_enable(struct r8152 *tp) |
1624 | { |
1625 | u32 ocp_data; |
1626 | int i, ret; |
ac718b69 |
1627 | |
1628 | r8152b_reset_packet_filter(tp); |
1629 | |
1630 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); |
1631 | ocp_data |= CR_RE | CR_TE; |
1632 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); |
1633 | |
1634 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1635 | ocp_data &= ~RXDY_GATED_EN; |
1636 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1637 | |
ebc2ec48 |
1638 | INIT_LIST_HEAD(&tp->rx_done); |
1639 | ret = 0; |
1640 | for (i = 0; i < RTL8152_MAX_RX; i++) { |
1641 | INIT_LIST_HEAD(&tp->rx_info[i].list); |
1642 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); |
1643 | } |
ac718b69 |
1644 | |
ebc2ec48 |
1645 | return ret; |
ac718b69 |
1646 | } |
1647 | |
507605a8 |
1648 | static int rtl8152_enable(struct r8152 *tp) |
1649 | { |
1650 | set_tx_qlen(tp); |
1651 | rtl_set_eee_plus(tp); |
1652 | |
1653 | return rtl_enable(tp); |
1654 | } |
1655 | |
43779f8d |
1656 | static void r8153_set_rx_agg(struct r8152 *tp) |
1657 | { |
1658 | u8 speed; |
1659 | |
1660 | speed = rtl8152_get_speed(tp); |
1661 | if (speed & _1000bps) { |
1662 | if (tp->udev->speed == USB_SPEED_SUPER) { |
1663 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, |
1664 | RX_THR_SUPPER); |
1665 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, |
1666 | EARLY_AGG_SUPPER); |
1667 | } else { |
1668 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, |
1669 | RX_THR_HIGH); |
1670 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, |
1671 | EARLY_AGG_HIGH); |
1672 | } |
1673 | } else { |
1674 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); |
1675 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, |
1676 | EARLY_AGG_SLOW); |
1677 | } |
1678 | } |
1679 | |
1680 | static int rtl8153_enable(struct r8152 *tp) |
1681 | { |
1682 | set_tx_qlen(tp); |
1683 | rtl_set_eee_plus(tp); |
1684 | r8153_set_rx_agg(tp); |
1685 | |
1686 | return rtl_enable(tp); |
1687 | } |
1688 | |
ac718b69 |
1689 | static void rtl8152_disable(struct r8152 *tp) |
1690 | { |
ebc2ec48 |
1691 | struct net_device_stats *stats = rtl8152_get_stats(tp->netdev); |
1692 | struct sk_buff *skb; |
1693 | u32 ocp_data; |
1694 | int i; |
ac718b69 |
1695 | |
1696 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
1697 | ocp_data &= ~RCR_ACPT_ALL; |
1698 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1699 | |
ebc2ec48 |
1700 | while ((skb = skb_dequeue(&tp->tx_queue))) { |
1701 | dev_kfree_skb(skb); |
1702 | stats->tx_dropped++; |
1703 | } |
1704 | |
1705 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1706 | usb_kill_urb(tp->tx_info[i].urb); |
ac718b69 |
1707 | |
1708 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1709 | ocp_data |= RXDY_GATED_EN; |
1710 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1711 | |
1712 | for (i = 0; i < 1000; i++) { |
1713 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1714 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) |
1715 | break; |
1716 | mdelay(1); |
1717 | } |
1718 | |
1719 | for (i = 0; i < 1000; i++) { |
1720 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) |
1721 | break; |
1722 | mdelay(1); |
1723 | } |
1724 | |
ebc2ec48 |
1725 | for (i = 0; i < RTL8152_MAX_RX; i++) |
1726 | usb_kill_urb(tp->rx_info[i].urb); |
ac718b69 |
1727 | |
1728 | rtl8152_nic_reset(tp); |
1729 | } |
1730 | |
1731 | static void r8152b_exit_oob(struct r8152 *tp) |
1732 | { |
1733 | u32 ocp_data; |
1734 | int i; |
1735 | |
1736 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
1737 | ocp_data &= ~RCR_ACPT_ALL; |
1738 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1739 | |
1740 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1741 | ocp_data |= RXDY_GATED_EN; |
1742 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1743 | |
1744 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
1745 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); |
1746 | |
1747 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1748 | ocp_data &= ~NOW_IS_OOB; |
1749 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
1750 | |
1751 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
1752 | ocp_data &= ~MCU_BORW_EN; |
1753 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
1754 | |
1755 | for (i = 0; i < 1000; i++) { |
1756 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1757 | if (ocp_data & LINK_LIST_READY) |
1758 | break; |
1759 | mdelay(1); |
1760 | } |
1761 | |
1762 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
1763 | ocp_data |= RE_INIT_LL; |
1764 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
1765 | |
1766 | for (i = 0; i < 1000; i++) { |
1767 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1768 | if (ocp_data & LINK_LIST_READY) |
1769 | break; |
1770 | mdelay(1); |
1771 | } |
1772 | |
1773 | rtl8152_nic_reset(tp); |
1774 | |
1775 | /* rx share fifo credit full threshold */ |
1776 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); |
1777 | |
1778 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); |
1779 | ocp_data &= STAT_SPEED_MASK; |
1780 | if (ocp_data == STAT_SPEED_FULL) { |
1781 | /* rx share fifo credit near full threshold */ |
1782 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, |
1783 | RXFIFO_THR2_FULL); |
1784 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, |
1785 | RXFIFO_THR3_FULL); |
1786 | } else { |
1787 | /* rx share fifo credit near full threshold */ |
1788 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, |
1789 | RXFIFO_THR2_HIGH); |
1790 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, |
1791 | RXFIFO_THR3_HIGH); |
1792 | } |
1793 | |
1794 | /* TX share fifo free credit full threshold */ |
1795 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); |
1796 | |
1797 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); |
8e1f51bd |
1798 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 |
1799 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
1800 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); |
1801 | |
1802 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
1803 | ocp_data &= ~CPCR_RX_VLAN; |
1804 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); |
1805 | |
1806 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); |
1807 | |
1808 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); |
1809 | ocp_data |= TCR0_AUTO_FIFO; |
1810 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); |
1811 | } |
1812 | |
1813 | static void r8152b_enter_oob(struct r8152 *tp) |
1814 | { |
45f4a19f |
1815 | u32 ocp_data; |
1816 | int i; |
ac718b69 |
1817 | |
1818 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1819 | ocp_data &= ~NOW_IS_OOB; |
1820 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
1821 | |
1822 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); |
1823 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); |
1824 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); |
1825 | |
1826 | rtl8152_disable(tp); |
1827 | |
1828 | for (i = 0; i < 1000; i++) { |
1829 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1830 | if (ocp_data & LINK_LIST_READY) |
1831 | break; |
1832 | mdelay(1); |
1833 | } |
1834 | |
1835 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
1836 | ocp_data |= RE_INIT_LL; |
1837 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
1838 | |
1839 | for (i = 0; i < 1000; i++) { |
1840 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1841 | if (ocp_data & LINK_LIST_READY) |
1842 | break; |
1843 | mdelay(1); |
1844 | } |
1845 | |
1846 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); |
1847 | |
1848 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); |
1849 | ocp_data |= MAGIC_EN; |
1850 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); |
1851 | |
1852 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
1853 | ocp_data |= CPCR_RX_VLAN; |
1854 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); |
1855 | |
1856 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); |
1857 | ocp_data |= ALDPS_PROXY_MODE; |
1858 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); |
1859 | |
1860 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1861 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; |
1862 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
1863 | |
1864 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); |
1865 | |
1866 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1867 | ocp_data &= ~RXDY_GATED_EN; |
1868 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1869 | |
1870 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
1871 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; |
1872 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1873 | } |
1874 | |
1875 | static void r8152b_disable_aldps(struct r8152 *tp) |
1876 | { |
1877 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); |
1878 | msleep(20); |
1879 | } |
1880 | |
1881 | static inline void r8152b_enable_aldps(struct r8152 *tp) |
1882 | { |
1883 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | |
1884 | LINKENA | DIS_SDSAVE); |
1885 | } |
1886 | |
43779f8d |
1887 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
1888 | { |
1889 | u32 ocp_data; |
1890 | u16 data; |
1891 | |
1892 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); |
1893 | r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); |
1894 | |
1895 | if (tp->version == RTL_VER_03) { |
1896 | data = ocp_reg_read(tp, OCP_EEE_CFG); |
1897 | data &= ~CTAP_SHORT_EN; |
1898 | ocp_reg_write(tp, OCP_EEE_CFG, data); |
1899 | } |
1900 | |
1901 | data = ocp_reg_read(tp, OCP_POWER_CFG); |
1902 | data |= EEE_CLKDIV_EN; |
1903 | ocp_reg_write(tp, OCP_POWER_CFG, data); |
1904 | |
1905 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); |
1906 | data |= EN_10M_BGOFF; |
1907 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); |
1908 | data = ocp_reg_read(tp, OCP_POWER_CFG); |
1909 | data |= EN_10M_PLLOFF; |
1910 | ocp_reg_write(tp, OCP_POWER_CFG, data); |
1911 | data = sram_read(tp, SRAM_IMPEDANCE); |
1912 | data &= ~RX_DRIVING_MASK; |
1913 | sram_write(tp, SRAM_IMPEDANCE, data); |
1914 | |
1915 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
1916 | ocp_data |= PFM_PWM_SWITCH; |
1917 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); |
1918 | |
1919 | data = sram_read(tp, SRAM_LPF_CFG); |
1920 | data |= LPF_AUTO_TUNE; |
1921 | sram_write(tp, SRAM_LPF_CFG, data); |
1922 | |
1923 | data = sram_read(tp, SRAM_10M_AMP1); |
1924 | data |= GDAC_IB_UPALL; |
1925 | sram_write(tp, SRAM_10M_AMP1, data); |
1926 | data = sram_read(tp, SRAM_10M_AMP2); |
1927 | data |= AMP_DN; |
1928 | sram_write(tp, SRAM_10M_AMP2, data); |
1929 | } |
1930 | |
1931 | static void r8153_u1u2en(struct r8152 *tp, int enable) |
1932 | { |
1933 | u8 u1u2[8]; |
1934 | |
1935 | if (enable) |
1936 | memset(u1u2, 0xff, sizeof(u1u2)); |
1937 | else |
1938 | memset(u1u2, 0x00, sizeof(u1u2)); |
1939 | |
1940 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); |
1941 | } |
1942 | |
1943 | static void r8153_u2p3en(struct r8152 *tp, int enable) |
1944 | { |
1945 | u32 ocp_data; |
1946 | |
1947 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); |
1948 | if (enable) |
1949 | ocp_data |= U2P3_ENABLE; |
1950 | else |
1951 | ocp_data &= ~U2P3_ENABLE; |
1952 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); |
1953 | } |
1954 | |
1955 | static void r8153_power_cut_en(struct r8152 *tp, int enable) |
1956 | { |
1957 | u32 ocp_data; |
1958 | |
1959 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); |
1960 | if (enable) |
1961 | ocp_data |= PWR_EN | PHASE2_EN; |
1962 | else |
1963 | ocp_data &= ~(PWR_EN | PHASE2_EN); |
1964 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); |
1965 | |
1966 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); |
1967 | ocp_data &= ~PCUT_STATUS; |
1968 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); |
1969 | } |
1970 | |
1971 | static void r8153_teredo_off(struct r8152 *tp) |
1972 | { |
1973 | u32 ocp_data; |
1974 | |
1975 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
1976 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); |
1977 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); |
1978 | |
1979 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); |
1980 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); |
1981 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); |
1982 | } |
1983 | |
1984 | static void r8153_first_init(struct r8152 *tp) |
1985 | { |
1986 | u32 ocp_data; |
1987 | int i; |
1988 | |
1989 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1990 | ocp_data |= RXDY_GATED_EN; |
1991 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1992 | |
1993 | r8153_teredo_off(tp); |
1994 | |
1995 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
1996 | ocp_data &= ~RCR_ACPT_ALL; |
1997 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1998 | |
1999 | r8153_hw_phy_cfg(tp); |
2000 | |
2001 | rtl8152_nic_reset(tp); |
2002 | |
2003 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
2004 | ocp_data &= ~NOW_IS_OOB; |
2005 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
2006 | |
2007 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
2008 | ocp_data &= ~MCU_BORW_EN; |
2009 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
2010 | |
2011 | for (i = 0; i < 1000; i++) { |
2012 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
2013 | if (ocp_data & LINK_LIST_READY) |
2014 | break; |
2015 | mdelay(1); |
2016 | } |
2017 | |
2018 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
2019 | ocp_data |= RE_INIT_LL; |
2020 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
2021 | |
2022 | for (i = 0; i < 1000; i++) { |
2023 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
2024 | if (ocp_data & LINK_LIST_READY) |
2025 | break; |
2026 | mdelay(1); |
2027 | } |
2028 | |
2029 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
2030 | ocp_data &= ~CPCR_RX_VLAN; |
2031 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); |
2032 | |
2033 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); |
2034 | |
2035 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); |
2036 | ocp_data |= TCR0_AUTO_FIFO; |
2037 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); |
2038 | |
2039 | rtl8152_nic_reset(tp); |
2040 | |
2041 | /* rx share fifo credit full threshold */ |
2042 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); |
2043 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); |
2044 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); |
2045 | /* TX share fifo free credit full threshold */ |
2046 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); |
2047 | |
2048 | // rx aggregation |
2049 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2050 | ocp_data &= ~RX_AGG_DISABLE; |
2051 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2052 | } |
2053 | |
2054 | static void r8153_enter_oob(struct r8152 *tp) |
2055 | { |
2056 | u32 ocp_data; |
2057 | int i; |
2058 | |
2059 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
2060 | ocp_data &= ~NOW_IS_OOB; |
2061 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
2062 | |
2063 | rtl8152_disable(tp); |
2064 | |
2065 | for (i = 0; i < 1000; i++) { |
2066 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
2067 | if (ocp_data & LINK_LIST_READY) |
2068 | break; |
2069 | mdelay(1); |
2070 | } |
2071 | |
2072 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
2073 | ocp_data |= RE_INIT_LL; |
2074 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
2075 | |
2076 | for (i = 0; i < 1000; i++) { |
2077 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
2078 | if (ocp_data & LINK_LIST_READY) |
2079 | break; |
2080 | mdelay(1); |
2081 | } |
2082 | |
2083 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); |
2084 | |
2085 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); |
2086 | ocp_data |= MAGIC_EN; |
2087 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); |
2088 | |
2089 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2090 | ocp_data &= ~TEREDO_WAKE_MASK; |
2091 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); |
2092 | |
2093 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
2094 | ocp_data |= CPCR_RX_VLAN; |
2095 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); |
2096 | |
2097 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); |
2098 | ocp_data |= ALDPS_PROXY_MODE; |
2099 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); |
2100 | |
2101 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
2102 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; |
2103 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
2104 | |
2105 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); |
2106 | |
2107 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
2108 | ocp_data &= ~RXDY_GATED_EN; |
2109 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
2110 | |
2111 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2112 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; |
2113 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
2114 | } |
2115 | |
2116 | static void r8153_disable_aldps(struct r8152 *tp) |
2117 | { |
2118 | u16 data; |
2119 | |
2120 | data = ocp_reg_read(tp, OCP_POWER_CFG); |
2121 | data &= ~EN_ALDPS; |
2122 | ocp_reg_write(tp, OCP_POWER_CFG, data); |
2123 | msleep(20); |
2124 | } |
2125 | |
2126 | static void r8153_enable_aldps(struct r8152 *tp) |
2127 | { |
2128 | u16 data; |
2129 | |
2130 | data = ocp_reg_read(tp, OCP_POWER_CFG); |
2131 | data |= EN_ALDPS; |
2132 | ocp_reg_write(tp, OCP_POWER_CFG, data); |
2133 | } |
2134 | |
ac718b69 |
2135 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2136 | { |
43779f8d |
2137 | u16 bmcr, anar, gbcr; |
ac718b69 |
2138 | int ret = 0; |
2139 | |
2140 | cancel_delayed_work_sync(&tp->schedule); |
2141 | anar = r8152_mdio_read(tp, MII_ADVERTISE); |
2142 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
2143 | ADVERTISE_100HALF | ADVERTISE_100FULL); |
43779f8d |
2144 | if (tp->mii.supports_gmii) { |
2145 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); |
2146 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
2147 | } else { |
2148 | gbcr = 0; |
2149 | } |
ac718b69 |
2150 | |
2151 | if (autoneg == AUTONEG_DISABLE) { |
2152 | if (speed == SPEED_10) { |
2153 | bmcr = 0; |
2154 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
2155 | } else if (speed == SPEED_100) { |
2156 | bmcr = BMCR_SPEED100; |
2157 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
43779f8d |
2158 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2159 | bmcr = BMCR_SPEED1000; |
2160 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
ac718b69 |
2161 | } else { |
2162 | ret = -EINVAL; |
2163 | goto out; |
2164 | } |
2165 | |
2166 | if (duplex == DUPLEX_FULL) |
2167 | bmcr |= BMCR_FULLDPLX; |
2168 | } else { |
2169 | if (speed == SPEED_10) { |
2170 | if (duplex == DUPLEX_FULL) |
2171 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
2172 | else |
2173 | anar |= ADVERTISE_10HALF; |
2174 | } else if (speed == SPEED_100) { |
2175 | if (duplex == DUPLEX_FULL) { |
2176 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
2177 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
2178 | } else { |
2179 | anar |= ADVERTISE_10HALF; |
2180 | anar |= ADVERTISE_100HALF; |
2181 | } |
43779f8d |
2182 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2183 | if (duplex == DUPLEX_FULL) { |
2184 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
2185 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
2186 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
2187 | } else { |
2188 | anar |= ADVERTISE_10HALF; |
2189 | anar |= ADVERTISE_100HALF; |
2190 | gbcr |= ADVERTISE_1000HALF; |
2191 | } |
ac718b69 |
2192 | } else { |
2193 | ret = -EINVAL; |
2194 | goto out; |
2195 | } |
2196 | |
2197 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
2198 | } |
2199 | |
43779f8d |
2200 | if (tp->mii.supports_gmii) |
2201 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); |
2202 | |
ac718b69 |
2203 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2204 | r8152_mdio_write(tp, MII_BMCR, bmcr); |
2205 | |
2206 | out: |
ac718b69 |
2207 | |
2208 | return ret; |
2209 | } |
2210 | |
2211 | static void rtl8152_down(struct r8152 *tp) |
2212 | { |
2213 | u32 ocp_data; |
2214 | |
2215 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); |
2216 | ocp_data &= ~POWER_CUT; |
2217 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); |
2218 | |
2219 | r8152b_disable_aldps(tp); |
2220 | r8152b_enter_oob(tp); |
2221 | r8152b_enable_aldps(tp); |
2222 | } |
2223 | |
43779f8d |
2224 | static void rtl8153_down(struct r8152 *tp) |
2225 | { |
2226 | r8153_u1u2en(tp, 0); |
2227 | r8153_power_cut_en(tp, 0); |
2228 | r8153_disable_aldps(tp); |
2229 | r8153_enter_oob(tp); |
2230 | r8153_enable_aldps(tp); |
2231 | } |
2232 | |
ac718b69 |
2233 | static void set_carrier(struct r8152 *tp) |
2234 | { |
2235 | struct net_device *netdev = tp->netdev; |
2236 | u8 speed; |
2237 | |
40a82917 |
2238 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 |
2239 | speed = rtl8152_get_speed(tp); |
2240 | |
2241 | if (speed & LINK_STATUS) { |
2242 | if (!(tp->speed & LINK_STATUS)) { |
c81229c9 |
2243 | tp->rtl_ops.enable(tp); |
ac718b69 |
2244 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2245 | netif_carrier_on(netdev); |
2246 | } |
2247 | } else { |
2248 | if (tp->speed & LINK_STATUS) { |
2249 | netif_carrier_off(netdev); |
ebc2ec48 |
2250 | tasklet_disable(&tp->tl); |
c81229c9 |
2251 | tp->rtl_ops.disable(tp); |
ebc2ec48 |
2252 | tasklet_enable(&tp->tl); |
ac718b69 |
2253 | } |
2254 | } |
2255 | tp->speed = speed; |
2256 | } |
2257 | |
2258 | static void rtl_work_func_t(struct work_struct *work) |
2259 | { |
2260 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); |
2261 | |
2262 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2263 | goto out1; |
2264 | |
2265 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2266 | goto out1; |
2267 | |
40a82917 |
2268 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2269 | set_carrier(tp); |
ac718b69 |
2270 | |
2271 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) |
2272 | _rtl8152_set_rx_mode(tp->netdev); |
2273 | |
ac718b69 |
2274 | out1: |
2275 | return; |
2276 | } |
2277 | |
2278 | static int rtl8152_open(struct net_device *netdev) |
2279 | { |
2280 | struct r8152 *tp = netdev_priv(netdev); |
2281 | int res = 0; |
2282 | |
40a82917 |
2283 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2284 | if (res) { |
2285 | if (res == -ENODEV) |
2286 | netif_device_detach(tp->netdev); |
2287 | netif_warn(tp, ifup, netdev, |
2288 | "intr_urb submit failed: %d\n", res); |
2289 | return res; |
ac718b69 |
2290 | } |
2291 | |
43779f8d |
2292 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2293 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, |
2294 | DUPLEX_FULL); |
40a82917 |
2295 | tp->speed = 0; |
2296 | netif_carrier_off(netdev); |
ac718b69 |
2297 | netif_start_queue(netdev); |
2298 | set_bit(WORK_ENABLE, &tp->flags); |
ac718b69 |
2299 | |
2300 | return res; |
2301 | } |
2302 | |
2303 | static int rtl8152_close(struct net_device *netdev) |
2304 | { |
2305 | struct r8152 *tp = netdev_priv(netdev); |
2306 | int res = 0; |
2307 | |
40a82917 |
2308 | usb_kill_urb(tp->intr_urb); |
ac718b69 |
2309 | clear_bit(WORK_ENABLE, &tp->flags); |
2310 | cancel_delayed_work_sync(&tp->schedule); |
2311 | netif_stop_queue(netdev); |
ebc2ec48 |
2312 | tasklet_disable(&tp->tl); |
c81229c9 |
2313 | tp->rtl_ops.disable(tp); |
ebc2ec48 |
2314 | tasklet_enable(&tp->tl); |
ac718b69 |
2315 | |
2316 | return res; |
2317 | } |
2318 | |
2319 | static void rtl_clear_bp(struct r8152 *tp) |
2320 | { |
2321 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); |
2322 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); |
2323 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); |
2324 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); |
2325 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); |
2326 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); |
2327 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); |
2328 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); |
2329 | mdelay(3); |
2330 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); |
2331 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); |
2332 | } |
2333 | |
43779f8d |
2334 | static void r8153_clear_bp(struct r8152 *tp) |
2335 | { |
2336 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); |
2337 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); |
2338 | rtl_clear_bp(tp); |
2339 | } |
2340 | |
ac718b69 |
2341 | static void r8152b_enable_eee(struct r8152 *tp) |
2342 | { |
45f4a19f |
2343 | u32 ocp_data; |
ac718b69 |
2344 | |
2345 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); |
2346 | ocp_data |= EEE_RX_EN | EEE_TX_EN; |
2347 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
2348 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | |
2349 | EEE_10_CAP | EEE_NWAY_EN | |
2350 | TX_QUIET_EN | RX_QUIET_EN | |
2351 | SDRISETIME | RG_RXLPI_MSK_HFDUP | |
2352 | SDFALLTIME); |
2353 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | |
2354 | RG_LDVQUIET_EN | RG_CKRSEL | |
2355 | RG_EEEPRG_EN); |
2356 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); |
2357 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); |
2358 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); |
2359 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); |
2360 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); |
2361 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); |
2362 | } |
2363 | |
43779f8d |
2364 | static void r8153_enable_eee(struct r8152 *tp) |
2365 | { |
2366 | u32 ocp_data; |
2367 | u16 data; |
2368 | |
2369 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); |
2370 | ocp_data |= EEE_RX_EN | EEE_TX_EN; |
2371 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
2372 | data = ocp_reg_read(tp, OCP_EEE_CFG); |
2373 | data |= EEE10_EN; |
2374 | ocp_reg_write(tp, OCP_EEE_CFG, data); |
2375 | data = ocp_reg_read(tp, OCP_EEE_CFG2); |
2376 | data |= MY1000_EEE | MY100_EEE; |
2377 | ocp_reg_write(tp, OCP_EEE_CFG2, data); |
2378 | } |
2379 | |
ac718b69 |
2380 | static void r8152b_enable_fc(struct r8152 *tp) |
2381 | { |
2382 | u16 anar; |
2383 | |
2384 | anar = r8152_mdio_read(tp, MII_ADVERTISE); |
2385 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
2386 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2387 | } |
2388 | |
2389 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2390 | { |
2391 | r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); |
2392 | r8152b_disable_aldps(tp); |
2393 | } |
2394 | |
2395 | static void r8152b_init(struct r8152 *tp) |
2396 | { |
ebc2ec48 |
2397 | u32 ocp_data; |
2398 | int i; |
ac718b69 |
2399 | |
2400 | rtl_clear_bp(tp); |
2401 | |
2402 | if (tp->version == RTL_VER_01) { |
2403 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
2404 | ocp_data &= ~LED_MODE_MASK; |
2405 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); |
2406 | } |
2407 | |
2408 | r8152b_hw_phy_cfg(tp); |
2409 | |
2410 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); |
2411 | ocp_data &= ~POWER_CUT; |
2412 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); |
2413 | |
2414 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); |
8e1f51bd |
2415 | ocp_data &= ~RESUME_INDICATE; |
ac718b69 |
2416 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); |
2417 | |
2418 | r8152b_exit_oob(tp); |
2419 | |
2420 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
2421 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; |
2422 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); |
2423 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); |
2424 | ocp_data &= ~MCU_CLK_RATIO_MASK; |
2425 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; |
2426 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); |
2427 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | |
2428 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; |
2429 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); |
2430 | |
2431 | r8152b_enable_eee(tp); |
2432 | r8152b_enable_aldps(tp); |
2433 | r8152b_enable_fc(tp); |
2434 | |
2435 | r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | |
2436 | BMCR_ANRESTART); |
2437 | for (i = 0; i < 100; i++) { |
2438 | udelay(100); |
2439 | if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET)) |
2440 | break; |
2441 | } |
2442 | |
ebc2ec48 |
2443 | /* enable rx aggregation */ |
ac718b69 |
2444 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 |
2445 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 |
2446 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2447 | } |
2448 | |
43779f8d |
2449 | static void r8153_init(struct r8152 *tp) |
2450 | { |
2451 | u32 ocp_data; |
2452 | int i; |
2453 | |
2454 | r8153_u1u2en(tp, 0); |
2455 | |
2456 | for (i = 0; i < 500; i++) { |
2457 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & |
2458 | AUTOLOAD_DONE) |
2459 | break; |
2460 | msleep(20); |
2461 | } |
2462 | |
2463 | for (i = 0; i < 500; i++) { |
2464 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; |
2465 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) |
2466 | break; |
2467 | msleep(20); |
2468 | } |
2469 | |
2470 | r8153_u2p3en(tp, 0); |
2471 | |
2472 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); |
2473 | ocp_data &= ~TIMER11_EN; |
2474 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); |
2475 | |
2476 | r8153_clear_bp(tp); |
2477 | |
2478 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
2479 | ocp_data &= ~LED_MODE_MASK; |
2480 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); |
2481 | |
2482 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); |
2483 | ocp_data &= ~LPM_TIMER_MASK; |
2484 | if (tp->udev->speed == USB_SPEED_SUPER) |
2485 | ocp_data |= LPM_TIMER_500US; |
2486 | else |
2487 | ocp_data |= LPM_TIMER_500MS; |
2488 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); |
2489 | |
2490 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); |
2491 | ocp_data &= ~SEN_VAL_MASK; |
2492 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; |
2493 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); |
2494 | |
2495 | r8153_power_cut_en(tp, 0); |
2496 | r8153_u1u2en(tp, 1); |
2497 | |
2498 | r8153_first_init(tp); |
2499 | |
2500 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
2501 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); |
2502 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, |
2503 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | |
2504 | U1U2_SPDWN_EN | L1_SPDWN_EN); |
2505 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, |
2506 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | |
2507 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | |
2508 | EEE_SPDWN_EN); |
2509 | |
2510 | r8153_enable_eee(tp); |
2511 | r8153_enable_aldps(tp); |
2512 | r8152b_enable_fc(tp); |
2513 | |
2514 | r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | |
2515 | BMCR_ANRESTART); |
2516 | } |
2517 | |
ac718b69 |
2518 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
2519 | { |
2520 | struct r8152 *tp = usb_get_intfdata(intf); |
2521 | |
2522 | netif_device_detach(tp->netdev); |
2523 | |
2524 | if (netif_running(tp->netdev)) { |
2525 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 |
2526 | usb_kill_urb(tp->intr_urb); |
ac718b69 |
2527 | cancel_delayed_work_sync(&tp->schedule); |
ebc2ec48 |
2528 | tasklet_disable(&tp->tl); |
ac718b69 |
2529 | } |
2530 | |
c81229c9 |
2531 | tp->rtl_ops.down(tp); |
ac718b69 |
2532 | |
2533 | return 0; |
2534 | } |
2535 | |
2536 | static int rtl8152_resume(struct usb_interface *intf) |
2537 | { |
2538 | struct r8152 *tp = usb_get_intfdata(intf); |
2539 | |
c81229c9 |
2540 | tp->rtl_ops.init(tp); |
ac718b69 |
2541 | netif_device_attach(tp->netdev); |
2542 | if (netif_running(tp->netdev)) { |
43779f8d |
2543 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2544 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, |
2545 | DUPLEX_FULL); |
40a82917 |
2546 | tp->speed = 0; |
2547 | netif_carrier_off(tp->netdev); |
ac718b69 |
2548 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 |
2549 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ebc2ec48 |
2550 | tasklet_enable(&tp->tl); |
ac718b69 |
2551 | } |
2552 | |
2553 | return 0; |
2554 | } |
2555 | |
2556 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
2557 | struct ethtool_drvinfo *info) |
2558 | { |
2559 | struct r8152 *tp = netdev_priv(netdev); |
2560 | |
2561 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); |
2562 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); |
2563 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
2564 | } |
2565 | |
2566 | static |
2567 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) |
2568 | { |
2569 | struct r8152 *tp = netdev_priv(netdev); |
2570 | |
2571 | if (!tp->mii.mdio_read) |
2572 | return -EOPNOTSUPP; |
2573 | |
2574 | return mii_ethtool_gset(&tp->mii, cmd); |
2575 | } |
2576 | |
2577 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
2578 | { |
2579 | struct r8152 *tp = netdev_priv(dev); |
2580 | |
2581 | return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
2582 | } |
2583 | |
2584 | static struct ethtool_ops ops = { |
2585 | .get_drvinfo = rtl8152_get_drvinfo, |
2586 | .get_settings = rtl8152_get_settings, |
2587 | .set_settings = rtl8152_set_settings, |
2588 | .get_link = ethtool_op_get_link, |
2589 | }; |
2590 | |
2591 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) |
2592 | { |
2593 | struct r8152 *tp = netdev_priv(netdev); |
2594 | struct mii_ioctl_data *data = if_mii(rq); |
2595 | int res = 0; |
2596 | |
2597 | switch (cmd) { |
2598 | case SIOCGMIIPHY: |
2599 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ |
2600 | break; |
2601 | |
2602 | case SIOCGMIIREG: |
2603 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
2604 | break; |
2605 | |
2606 | case SIOCSMIIREG: |
2607 | if (!capable(CAP_NET_ADMIN)) { |
2608 | res = -EPERM; |
2609 | break; |
2610 | } |
2611 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
2612 | break; |
2613 | |
2614 | default: |
2615 | res = -EOPNOTSUPP; |
2616 | } |
2617 | |
2618 | return res; |
2619 | } |
2620 | |
2621 | static const struct net_device_ops rtl8152_netdev_ops = { |
2622 | .ndo_open = rtl8152_open, |
2623 | .ndo_stop = rtl8152_close, |
2624 | .ndo_do_ioctl = rtl8152_ioctl, |
2625 | .ndo_start_xmit = rtl8152_start_xmit, |
2626 | .ndo_tx_timeout = rtl8152_tx_timeout, |
2627 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
2628 | .ndo_set_mac_address = rtl8152_set_mac_address, |
2629 | |
2630 | .ndo_change_mtu = eth_change_mtu, |
2631 | .ndo_validate_addr = eth_validate_addr, |
2632 | }; |
2633 | |
2634 | static void r8152b_get_version(struct r8152 *tp) |
2635 | { |
2636 | u32 ocp_data; |
2637 | u16 version; |
2638 | |
2639 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); |
2640 | version = (u16)(ocp_data & VERSION_MASK); |
2641 | |
2642 | switch (version) { |
2643 | case 0x4c00: |
2644 | tp->version = RTL_VER_01; |
2645 | break; |
2646 | case 0x4c10: |
2647 | tp->version = RTL_VER_02; |
2648 | break; |
43779f8d |
2649 | case 0x5c00: |
2650 | tp->version = RTL_VER_03; |
2651 | tp->mii.supports_gmii = 1; |
2652 | break; |
2653 | case 0x5c10: |
2654 | tp->version = RTL_VER_04; |
2655 | tp->mii.supports_gmii = 1; |
2656 | break; |
2657 | case 0x5c20: |
2658 | tp->version = RTL_VER_05; |
2659 | tp->mii.supports_gmii = 1; |
2660 | break; |
ac718b69 |
2661 | default: |
2662 | netif_info(tp, probe, tp->netdev, |
2663 | "Unknown version 0x%04x\n", version); |
2664 | break; |
2665 | } |
2666 | } |
2667 | |
e3fe0b1a |
2668 | static void rtl8152_unload(struct r8152 *tp) |
2669 | { |
2670 | u32 ocp_data; |
2671 | |
2672 | if (tp->version != RTL_VER_01) { |
2673 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); |
2674 | ocp_data |= POWER_CUT; |
2675 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); |
2676 | } |
2677 | |
2678 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); |
8e1f51bd |
2679 | ocp_data &= ~RESUME_INDICATE; |
e3fe0b1a |
2680 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); |
2681 | } |
2682 | |
43779f8d |
2683 | static void rtl8153_unload(struct r8152 *tp) |
2684 | { |
2685 | r8153_power_cut_en(tp, 1); |
2686 | } |
2687 | |
31ca1dec |
2688 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 |
2689 | { |
2690 | struct rtl_ops *ops = &tp->rtl_ops; |
31ca1dec |
2691 | int ret = -ENODEV; |
c81229c9 |
2692 | |
2693 | switch (id->idVendor) { |
2694 | case VENDOR_ID_REALTEK: |
2695 | switch (id->idProduct) { |
2696 | case PRODUCT_ID_RTL8152: |
2697 | ops->init = r8152b_init; |
2698 | ops->enable = rtl8152_enable; |
2699 | ops->disable = rtl8152_disable; |
2700 | ops->down = rtl8152_down; |
2701 | ops->unload = rtl8152_unload; |
31ca1dec |
2702 | ret = 0; |
c81229c9 |
2703 | break; |
43779f8d |
2704 | case PRODUCT_ID_RTL8153: |
2705 | ops->init = r8153_init; |
2706 | ops->enable = rtl8153_enable; |
2707 | ops->disable = rtl8152_disable; |
2708 | ops->down = rtl8153_down; |
2709 | ops->unload = rtl8153_unload; |
31ca1dec |
2710 | ret = 0; |
43779f8d |
2711 | break; |
2712 | default: |
43779f8d |
2713 | break; |
2714 | } |
2715 | break; |
2716 | |
2717 | case VENDOR_ID_SAMSUNG: |
2718 | switch (id->idProduct) { |
2719 | case PRODUCT_ID_SAMSUNG: |
2720 | ops->init = r8153_init; |
2721 | ops->enable = rtl8153_enable; |
2722 | ops->disable = rtl8152_disable; |
2723 | ops->down = rtl8153_down; |
2724 | ops->unload = rtl8153_unload; |
31ca1dec |
2725 | ret = 0; |
43779f8d |
2726 | break; |
c81229c9 |
2727 | default: |
c81229c9 |
2728 | break; |
2729 | } |
2730 | break; |
2731 | |
2732 | default: |
c81229c9 |
2733 | break; |
2734 | } |
2735 | |
31ca1dec |
2736 | if (ret) |
2737 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); |
2738 | |
c81229c9 |
2739 | return ret; |
2740 | } |
2741 | |
ac718b69 |
2742 | static int rtl8152_probe(struct usb_interface *intf, |
2743 | const struct usb_device_id *id) |
2744 | { |
2745 | struct usb_device *udev = interface_to_usbdev(intf); |
2746 | struct r8152 *tp; |
2747 | struct net_device *netdev; |
ebc2ec48 |
2748 | int ret; |
ac718b69 |
2749 | |
2750 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
2751 | usb_driver_set_configuration(udev, 1); |
2752 | return -ENODEV; |
2753 | } |
2754 | |
2755 | netdev = alloc_etherdev(sizeof(struct r8152)); |
2756 | if (!netdev) { |
2757 | dev_err(&intf->dev, "Out of memory"); |
2758 | return -ENOMEM; |
2759 | } |
2760 | |
ebc2ec48 |
2761 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 |
2762 | tp = netdev_priv(netdev); |
2763 | tp->msg_enable = 0x7FFF; |
2764 | |
e3ad412a |
2765 | tp->udev = udev; |
2766 | tp->netdev = netdev; |
2767 | tp->intf = intf; |
2768 | |
31ca1dec |
2769 | ret = rtl_ops_init(tp, id); |
2770 | if (ret) |
2771 | goto out; |
c81229c9 |
2772 | |
ebc2ec48 |
2773 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 |
2774 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
2775 | |
ac718b69 |
2776 | netdev->netdev_ops = &rtl8152_netdev_ops; |
2777 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; |
5bd23881 |
2778 | |
2779 | netdev->features |= NETIF_F_IP_CSUM; |
2780 | netdev->hw_features = NETIF_F_IP_CSUM; |
ac718b69 |
2781 | SET_ETHTOOL_OPS(netdev, &ops); |
ac718b69 |
2782 | |
2783 | tp->mii.dev = netdev; |
2784 | tp->mii.mdio_read = read_mii_word; |
2785 | tp->mii.mdio_write = write_mii_word; |
2786 | tp->mii.phy_id_mask = 0x3f; |
2787 | tp->mii.reg_num_mask = 0x1f; |
2788 | tp->mii.phy_id = R8152_PHY_ID; |
2789 | tp->mii.supports_gmii = 0; |
2790 | |
2791 | r8152b_get_version(tp); |
c81229c9 |
2792 | tp->rtl_ops.init(tp); |
ac718b69 |
2793 | set_ethernet_addr(tp); |
2794 | |
ebc2ec48 |
2795 | ret = alloc_all_mem(tp); |
2796 | if (ret) |
ac718b69 |
2797 | goto out; |
ac718b69 |
2798 | |
2799 | usb_set_intfdata(intf, tp); |
ac718b69 |
2800 | |
ebc2ec48 |
2801 | ret = register_netdev(netdev); |
2802 | if (ret != 0) { |
ac718b69 |
2803 | netif_err(tp, probe, netdev, "couldn't register the device"); |
ebc2ec48 |
2804 | goto out1; |
ac718b69 |
2805 | } |
2806 | |
2807 | netif_info(tp, probe, netdev, "%s", DRIVER_VERSION); |
2808 | |
2809 | return 0; |
2810 | |
ac718b69 |
2811 | out1: |
ebc2ec48 |
2812 | usb_set_intfdata(intf, NULL); |
ac718b69 |
2813 | out: |
2814 | free_netdev(netdev); |
ebc2ec48 |
2815 | return ret; |
ac718b69 |
2816 | } |
2817 | |
ac718b69 |
2818 | static void rtl8152_disconnect(struct usb_interface *intf) |
2819 | { |
2820 | struct r8152 *tp = usb_get_intfdata(intf); |
2821 | |
2822 | usb_set_intfdata(intf, NULL); |
2823 | if (tp) { |
2824 | set_bit(RTL8152_UNPLUG, &tp->flags); |
2825 | tasklet_kill(&tp->tl); |
2826 | unregister_netdev(tp->netdev); |
c81229c9 |
2827 | tp->rtl_ops.unload(tp); |
ebc2ec48 |
2828 | free_all_mem(tp); |
ac718b69 |
2829 | free_netdev(tp->netdev); |
2830 | } |
2831 | } |
2832 | |
2833 | /* table of devices that work with this driver */ |
2834 | static struct usb_device_id rtl8152_table[] = { |
2835 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
43779f8d |
2836 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, |
2837 | {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, |
ac718b69 |
2838 | {} |
2839 | }; |
2840 | |
2841 | MODULE_DEVICE_TABLE(usb, rtl8152_table); |
2842 | |
2843 | static struct usb_driver rtl8152_driver = { |
2844 | .name = MODULENAME, |
ebc2ec48 |
2845 | .id_table = rtl8152_table, |
ac718b69 |
2846 | .probe = rtl8152_probe, |
2847 | .disconnect = rtl8152_disconnect, |
ac718b69 |
2848 | .suspend = rtl8152_suspend, |
ebc2ec48 |
2849 | .resume = rtl8152_resume, |
2850 | .reset_resume = rtl8152_resume, |
ac718b69 |
2851 | }; |
2852 | |
b4236daa |
2853 | module_usb_driver(rtl8152_driver); |
ac718b69 |
2854 | |
2855 | MODULE_AUTHOR(DRIVER_AUTHOR); |
2856 | MODULE_DESCRIPTION(DRIVER_DESC); |
2857 | MODULE_LICENSE("GPL"); |