regulator: tps65023: Use [set|get]_voltage_sel_regmap instead of open coded
[deliverable/linux.git] / drivers / net / usb / smsc75xx.c
CommitLineData
d0cad871
SG
1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2010 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 *****************************************************************************/
20
21#include <linux/module.h>
22#include <linux/kmod.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/mii.h>
28#include <linux/usb.h>
899a391b
SG
29#include <linux/bitrev.h>
30#include <linux/crc16.h>
d0cad871
SG
31#include <linux/crc32.h>
32#include <linux/usb/usbnet.h>
5a0e3ad6 33#include <linux/slab.h>
d0cad871
SG
34#include "smsc75xx.h"
35
36#define SMSC_CHIPNAME "smsc75xx"
37#define SMSC_DRIVER_VERSION "1.0.0"
38#define HS_USB_PKT_SIZE (512)
39#define FS_USB_PKT_SIZE (64)
40#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
41#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
42#define DEFAULT_BULK_IN_DELAY (0x00002000)
43#define MAX_SINGLE_PACKET_SIZE (9000)
44#define LAN75XX_EEPROM_MAGIC (0x7500)
45#define EEPROM_MAC_OFFSET (0x01)
46#define DEFAULT_TX_CSUM_ENABLE (true)
47#define DEFAULT_RX_CSUM_ENABLE (true)
48#define DEFAULT_TSO_ENABLE (true)
49#define SMSC75XX_INTERNAL_PHY_ID (1)
50#define SMSC75XX_TX_OVERHEAD (8)
51#define MAX_RX_FIFO_SIZE (20 * 1024)
52#define MAX_TX_FIFO_SIZE (12 * 1024)
53#define USB_VENDOR_ID_SMSC (0x0424)
54#define USB_PRODUCT_ID_LAN7500 (0x7500)
55#define USB_PRODUCT_ID_LAN7505 (0x7505)
ea1649de 56#define RXW_PADDING 2
f329ccdc 57#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
899a391b 58 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
d0cad871 59
b4cdea9c
SG
60#define SUSPEND_SUSPEND0 (0x01)
61#define SUSPEND_SUSPEND1 (0x02)
62#define SUSPEND_SUSPEND2 (0x04)
63#define SUSPEND_SUSPEND3 (0x08)
b4cdea9c
SG
64#define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
65 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
66
d0cad871
SG
67struct smsc75xx_priv {
68 struct usbnet *dev;
69 u32 rfe_ctl;
6c636503 70 u32 wolopts;
d0cad871 71 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
d0cad871
SG
72 struct mutex dataport_mutex;
73 spinlock_t rfe_ctl_lock;
74 struct work_struct set_multicast;
b4cdea9c 75 u8 suspend_flags;
d0cad871
SG
76};
77
78struct usb_context {
79 struct usb_ctrlrequest req;
80 struct usbnet *dev;
81};
82
eb939922 83static bool turbo_mode = true;
d0cad871
SG
84module_param(turbo_mode, bool, 0644);
85MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
86
47bbea41
ML
87static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
88 u32 *data, int in_pm)
d0cad871 89{
2b2e41e3 90 u32 buf;
d0cad871 91 int ret;
47bbea41 92 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
d0cad871
SG
93
94 BUG_ON(!dev);
95
47bbea41
ML
96 if (!in_pm)
97 fn = usbnet_read_cmd;
98 else
99 fn = usbnet_read_cmd_nopm;
100
101 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
102 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
103 0, index, &buf, 4);
d0cad871 104 if (unlikely(ret < 0))
1e1d7412
JP
105 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
106 index, ret);
d0cad871 107
2b2e41e3
ML
108 le32_to_cpus(&buf);
109 *data = buf;
d0cad871
SG
110
111 return ret;
112}
113
47bbea41
ML
114static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
115 u32 data, int in_pm)
d0cad871 116{
2b2e41e3 117 u32 buf;
d0cad871 118 int ret;
47bbea41 119 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
d0cad871
SG
120
121 BUG_ON(!dev);
122
47bbea41
ML
123 if (!in_pm)
124 fn = usbnet_write_cmd;
125 else
126 fn = usbnet_write_cmd_nopm;
127
2b2e41e3
ML
128 buf = data;
129 cpu_to_le32s(&buf);
d0cad871 130
47bbea41
ML
131 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
132 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
133 0, index, &buf, 4);
d0cad871 134 if (unlikely(ret < 0))
1e1d7412
JP
135 netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
136 index, ret);
d0cad871 137
d0cad871
SG
138 return ret;
139}
140
47bbea41
ML
141static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
142 u32 *data)
143{
144 return __smsc75xx_read_reg(dev, index, data, 1);
145}
146
147static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
148 u32 data)
149{
150 return __smsc75xx_write_reg(dev, index, data, 1);
151}
152
153static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
154 u32 *data)
155{
156 return __smsc75xx_read_reg(dev, index, data, 0);
157}
158
159static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
160 u32 data)
161{
162 return __smsc75xx_write_reg(dev, index, data, 0);
163}
164
d0cad871
SG
165/* Loop until the read is completed with timeout
166 * called with phy_mutex held */
f329ccdc
SG
167static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
168 int in_pm)
d0cad871
SG
169{
170 unsigned long start_time = jiffies;
171 u32 val;
172 int ret;
173
174 do {
f329ccdc 175 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
e3c678e6
SG
176 if (ret < 0) {
177 netdev_warn(dev->net, "Error reading MII_ACCESS\n");
178 return ret;
179 }
d0cad871
SG
180
181 if (!(val & MII_ACCESS_BUSY))
182 return 0;
183 } while (!time_after(jiffies, start_time + HZ));
184
185 return -EIO;
186}
187
f329ccdc
SG
188static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
189 int in_pm)
d0cad871
SG
190{
191 struct usbnet *dev = netdev_priv(netdev);
192 u32 val, addr;
193 int ret;
194
195 mutex_lock(&dev->phy_mutex);
196
197 /* confirm MII not busy */
f329ccdc 198 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
199 if (ret < 0) {
200 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
201 goto done;
202 }
d0cad871
SG
203
204 /* set the address, index & direction (read from PHY) */
205 phy_id &= dev->mii.phy_id_mask;
206 idx &= dev->mii.reg_num_mask;
207 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
208 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 209 | MII_ACCESS_READ | MII_ACCESS_BUSY;
f329ccdc 210 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
211 if (ret < 0) {
212 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
213 goto done;
214 }
d0cad871 215
f329ccdc 216 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
217 if (ret < 0) {
218 netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
219 goto done;
220 }
d0cad871 221
f329ccdc 222 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
e3c678e6
SG
223 if (ret < 0) {
224 netdev_warn(dev->net, "Error reading MII_DATA\n");
225 goto done;
226 }
d0cad871
SG
227
228 ret = (u16)(val & 0xFFFF);
229
230done:
231 mutex_unlock(&dev->phy_mutex);
232 return ret;
233}
234
f329ccdc
SG
235static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
236 int idx, int regval, int in_pm)
d0cad871
SG
237{
238 struct usbnet *dev = netdev_priv(netdev);
239 u32 val, addr;
240 int ret;
241
242 mutex_lock(&dev->phy_mutex);
243
244 /* confirm MII not busy */
f329ccdc 245 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
246 if (ret < 0) {
247 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
248 goto done;
249 }
d0cad871
SG
250
251 val = regval;
f329ccdc 252 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
e3c678e6
SG
253 if (ret < 0) {
254 netdev_warn(dev->net, "Error writing MII_DATA\n");
255 goto done;
256 }
d0cad871
SG
257
258 /* set the address, index & direction (write to PHY) */
259 phy_id &= dev->mii.phy_id_mask;
260 idx &= dev->mii.reg_num_mask;
261 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
262 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 263 | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
f329ccdc 264 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
265 if (ret < 0) {
266 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
267 goto done;
268 }
d0cad871 269
f329ccdc 270 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
271 if (ret < 0) {
272 netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
273 goto done;
274 }
d0cad871
SG
275
276done:
277 mutex_unlock(&dev->phy_mutex);
278}
279
f329ccdc
SG
280static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
281 int idx)
282{
283 return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
284}
285
286static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
287 int idx, int regval)
288{
289 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
290}
291
292static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
293{
294 return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
295}
296
297static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
298 int regval)
299{
300 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
301}
302
d0cad871
SG
303static int smsc75xx_wait_eeprom(struct usbnet *dev)
304{
305 unsigned long start_time = jiffies;
306 u32 val;
307 int ret;
308
309 do {
310 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
311 if (ret < 0) {
312 netdev_warn(dev->net, "Error reading E2P_CMD\n");
313 return ret;
314 }
d0cad871
SG
315
316 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
317 break;
318 udelay(40);
319 } while (!time_after(jiffies, start_time + HZ));
320
321 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
1e1d7412 322 netdev_warn(dev->net, "EEPROM read operation timeout\n");
d0cad871
SG
323 return -EIO;
324 }
325
326 return 0;
327}
328
329static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
330{
331 unsigned long start_time = jiffies;
332 u32 val;
333 int ret;
334
335 do {
336 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
337 if (ret < 0) {
338 netdev_warn(dev->net, "Error reading E2P_CMD\n");
339 return ret;
340 }
d0cad871
SG
341
342 if (!(val & E2P_CMD_BUSY))
343 return 0;
344
345 udelay(40);
346 } while (!time_after(jiffies, start_time + HZ));
347
1e1d7412 348 netdev_warn(dev->net, "EEPROM is busy\n");
d0cad871
SG
349 return -EIO;
350}
351
352static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
353 u8 *data)
354{
355 u32 val;
356 int i, ret;
357
358 BUG_ON(!dev);
359 BUG_ON(!data);
360
361 ret = smsc75xx_eeprom_confirm_not_busy(dev);
362 if (ret)
363 return ret;
364
365 for (i = 0; i < length; i++) {
366 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
367 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
368 if (ret < 0) {
369 netdev_warn(dev->net, "Error writing E2P_CMD\n");
370 return ret;
371 }
d0cad871
SG
372
373 ret = smsc75xx_wait_eeprom(dev);
374 if (ret < 0)
375 return ret;
376
377 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
e3c678e6
SG
378 if (ret < 0) {
379 netdev_warn(dev->net, "Error reading E2P_DATA\n");
380 return ret;
381 }
d0cad871
SG
382
383 data[i] = val & 0xFF;
384 offset++;
385 }
386
387 return 0;
388}
389
390static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
391 u8 *data)
392{
393 u32 val;
394 int i, ret;
395
396 BUG_ON(!dev);
397 BUG_ON(!data);
398
399 ret = smsc75xx_eeprom_confirm_not_busy(dev);
400 if (ret)
401 return ret;
402
403 /* Issue write/erase enable command */
404 val = E2P_CMD_BUSY | E2P_CMD_EWEN;
405 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
406 if (ret < 0) {
407 netdev_warn(dev->net, "Error writing E2P_CMD\n");
408 return ret;
409 }
d0cad871
SG
410
411 ret = smsc75xx_wait_eeprom(dev);
412 if (ret < 0)
413 return ret;
414
415 for (i = 0; i < length; i++) {
416
417 /* Fill data register */
418 val = data[i];
419 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
e3c678e6
SG
420 if (ret < 0) {
421 netdev_warn(dev->net, "Error writing E2P_DATA\n");
422 return ret;
423 }
d0cad871
SG
424
425 /* Send "write" command */
426 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
427 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
428 if (ret < 0) {
429 netdev_warn(dev->net, "Error writing E2P_CMD\n");
430 return ret;
431 }
d0cad871
SG
432
433 ret = smsc75xx_wait_eeprom(dev);
434 if (ret < 0)
435 return ret;
436
437 offset++;
438 }
439
440 return 0;
441}
442
443static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
444{
445 int i, ret;
446
447 for (i = 0; i < 100; i++) {
448 u32 dp_sel;
449 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
450 if (ret < 0) {
451 netdev_warn(dev->net, "Error reading DP_SEL\n");
452 return ret;
453 }
d0cad871
SG
454
455 if (dp_sel & DP_SEL_DPRDY)
456 return 0;
457
458 udelay(40);
459 }
460
1e1d7412 461 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
d0cad871
SG
462
463 return -EIO;
464}
465
466static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
467 u32 length, u32 *buf)
468{
469 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
470 u32 dp_sel;
471 int i, ret;
472
473 mutex_lock(&pdata->dataport_mutex);
474
475 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
476 if (ret < 0) {
477 netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
478 goto done;
479 }
d0cad871
SG
480
481 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
482 if (ret < 0) {
483 netdev_warn(dev->net, "Error reading DP_SEL\n");
484 goto done;
485 }
d0cad871
SG
486
487 dp_sel &= ~DP_SEL_RSEL;
488 dp_sel |= ram_select;
489 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
e3c678e6
SG
490 if (ret < 0) {
491 netdev_warn(dev->net, "Error writing DP_SEL\n");
492 goto done;
493 }
d0cad871
SG
494
495 for (i = 0; i < length; i++) {
496 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
e3c678e6
SG
497 if (ret < 0) {
498 netdev_warn(dev->net, "Error writing DP_ADDR\n");
499 goto done;
500 }
d0cad871
SG
501
502 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
e3c678e6
SG
503 if (ret < 0) {
504 netdev_warn(dev->net, "Error writing DP_DATA\n");
505 goto done;
506 }
d0cad871
SG
507
508 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
e3c678e6
SG
509 if (ret < 0) {
510 netdev_warn(dev->net, "Error writing DP_CMD\n");
511 goto done;
512 }
d0cad871
SG
513
514 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
515 if (ret < 0) {
516 netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
517 goto done;
518 }
d0cad871
SG
519 }
520
521done:
522 mutex_unlock(&pdata->dataport_mutex);
523 return ret;
524}
525
526/* returns hash bit number for given MAC address */
527static u32 smsc75xx_hash(char addr[ETH_ALEN])
528{
529 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
530}
531
532static void smsc75xx_deferred_multicast_write(struct work_struct *param)
533{
534 struct smsc75xx_priv *pdata =
535 container_of(param, struct smsc75xx_priv, set_multicast);
536 struct usbnet *dev = pdata->dev;
537 int ret;
538
1e1d7412
JP
539 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
540 pdata->rfe_ctl);
d0cad871
SG
541
542 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
543 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
544
545 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
546 if (ret < 0)
547 netdev_warn(dev->net, "Error writing RFE_CRL\n");
d0cad871
SG
548}
549
550static void smsc75xx_set_multicast(struct net_device *netdev)
551{
552 struct usbnet *dev = netdev_priv(netdev);
553 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
554 unsigned long flags;
555 int i;
556
557 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
558
559 pdata->rfe_ctl &=
560 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
561 pdata->rfe_ctl |= RFE_CTL_AB;
562
563 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
564 pdata->multicast_hash_table[i] = 0;
565
566 if (dev->net->flags & IFF_PROMISC) {
1e1d7412 567 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
d0cad871
SG
568 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
569 } else if (dev->net->flags & IFF_ALLMULTI) {
1e1d7412 570 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
d0cad871
SG
571 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
572 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 573 struct netdev_hw_addr *ha;
d0cad871 574
1e1d7412 575 netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
d0cad871
SG
576
577 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
578
22bedad3
JP
579 netdev_for_each_mc_addr(ha, netdev) {
580 u32 bitnum = smsc75xx_hash(ha->addr);
d0cad871
SG
581 pdata->multicast_hash_table[bitnum / 32] |=
582 (1 << (bitnum % 32));
583 }
584 } else {
1e1d7412 585 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
d0cad871
SG
586 pdata->rfe_ctl |= RFE_CTL_DPF;
587 }
588
589 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
590
591 /* defer register writes to a sleepable context */
592 schedule_work(&pdata->set_multicast);
593}
594
595static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
596 u16 lcladv, u16 rmtadv)
597{
598 u32 flow = 0, fct_flow = 0;
599 int ret;
600
601 if (duplex == DUPLEX_FULL) {
602 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
603
604 if (cap & FLOW_CTRL_TX) {
605 flow = (FLOW_TX_FCEN | 0xFFFF);
606 /* set fct_flow thresholds to 20% and 80% */
607 fct_flow = (8 << 8) | 32;
608 }
609
610 if (cap & FLOW_CTRL_RX)
611 flow |= FLOW_RX_FCEN;
612
1e1d7412
JP
613 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
614 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
615 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
d0cad871 616 } else {
1e1d7412 617 netif_dbg(dev, link, dev->net, "half duplex\n");
d0cad871
SG
618 }
619
620 ret = smsc75xx_write_reg(dev, FLOW, flow);
e3c678e6
SG
621 if (ret < 0) {
622 netdev_warn(dev->net, "Error writing FLOW\n");
623 return ret;
624 }
d0cad871
SG
625
626 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
e3c678e6
SG
627 if (ret < 0) {
628 netdev_warn(dev->net, "Error writing FCT_FLOW\n");
629 return ret;
630 }
d0cad871
SG
631
632 return 0;
633}
634
635static int smsc75xx_link_reset(struct usbnet *dev)
636{
637 struct mii_if_info *mii = &dev->mii;
8ae6daca 638 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
d0cad871
SG
639 u16 lcladv, rmtadv;
640 int ret;
641
4f94a929 642 /* write to clear phy interrupt status */
7749622d
SG
643 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
644 PHY_INT_SRC_CLEAR_ALL);
d0cad871
SG
645
646 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
647 if (ret < 0) {
648 netdev_warn(dev->net, "Error writing INT_STS\n");
649 return ret;
650 }
d0cad871
SG
651
652 mii_check_media(mii, 1, 1);
653 mii_ethtool_gset(&dev->mii, &ecmd);
654 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
655 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
656
1e1d7412
JP
657 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
658 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
d0cad871
SG
659
660 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
661}
662
663static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
664{
665 u32 intdata;
666
667 if (urb->actual_length != 4) {
1e1d7412
JP
668 netdev_warn(dev->net, "unexpected urb length %d\n",
669 urb->actual_length);
d0cad871
SG
670 return;
671 }
672
673 memcpy(&intdata, urb->transfer_buffer, 4);
674 le32_to_cpus(&intdata);
675
1e1d7412 676 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
d0cad871
SG
677
678 if (intdata & INT_ENP_PHY_INT)
679 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
680 else
1e1d7412
JP
681 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
682 intdata);
d0cad871
SG
683}
684
d0cad871
SG
685static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
686{
687 return MAX_EEPROM_SIZE;
688}
689
690static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
691 struct ethtool_eeprom *ee, u8 *data)
692{
693 struct usbnet *dev = netdev_priv(netdev);
694
695 ee->magic = LAN75XX_EEPROM_MAGIC;
696
697 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
698}
699
700static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
701 struct ethtool_eeprom *ee, u8 *data)
702{
703 struct usbnet *dev = netdev_priv(netdev);
704
705 if (ee->magic != LAN75XX_EEPROM_MAGIC) {
1e1d7412
JP
706 netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
707 ee->magic);
d0cad871
SG
708 return -EINVAL;
709 }
710
711 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
712}
713
6c636503
SG
714static void smsc75xx_ethtool_get_wol(struct net_device *net,
715 struct ethtool_wolinfo *wolinfo)
716{
717 struct usbnet *dev = netdev_priv(net);
718 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
719
720 wolinfo->supported = SUPPORTED_WAKE;
721 wolinfo->wolopts = pdata->wolopts;
722}
723
724static int smsc75xx_ethtool_set_wol(struct net_device *net,
725 struct ethtool_wolinfo *wolinfo)
726{
727 struct usbnet *dev = netdev_priv(net);
728 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
351f33d9 729 int ret;
6c636503
SG
730
731 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
351f33d9
SG
732
733 ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
e3c678e6
SG
734 if (ret < 0)
735 netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
351f33d9 736
e3c678e6 737 return ret;
6c636503
SG
738}
739
d0cad871
SG
740static const struct ethtool_ops smsc75xx_ethtool_ops = {
741 .get_link = usbnet_get_link,
742 .nway_reset = usbnet_nway_reset,
743 .get_drvinfo = usbnet_get_drvinfo,
744 .get_msglevel = usbnet_get_msglevel,
745 .set_msglevel = usbnet_set_msglevel,
746 .get_settings = usbnet_get_settings,
747 .set_settings = usbnet_set_settings,
748 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
749 .get_eeprom = smsc75xx_ethtool_get_eeprom,
750 .set_eeprom = smsc75xx_ethtool_set_eeprom,
6c636503
SG
751 .get_wol = smsc75xx_ethtool_get_wol,
752 .set_wol = smsc75xx_ethtool_set_wol,
d0cad871
SG
753};
754
755static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
756{
757 struct usbnet *dev = netdev_priv(netdev);
758
759 if (!netif_running(netdev))
760 return -EINVAL;
761
762 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
763}
764
765static void smsc75xx_init_mac_address(struct usbnet *dev)
766{
767 /* try reading mac address from EEPROM */
768 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
769 dev->net->dev_addr) == 0) {
770 if (is_valid_ether_addr(dev->net->dev_addr)) {
771 /* eeprom values are valid so use them */
772 netif_dbg(dev, ifup, dev->net,
1e1d7412 773 "MAC address read from EEPROM\n");
d0cad871
SG
774 return;
775 }
776 }
777
778 /* no eeprom, or eeprom values are invalid. generate random MAC */
f2cedb63 779 eth_hw_addr_random(dev->net);
1e1d7412 780 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
d0cad871
SG
781}
782
783static int smsc75xx_set_mac_address(struct usbnet *dev)
784{
785 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
786 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
787 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
788
789 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
e3c678e6
SG
790 if (ret < 0) {
791 netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
792 return ret;
793 }
d0cad871
SG
794
795 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
e3c678e6
SG
796 if (ret < 0) {
797 netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
798 return ret;
799 }
d0cad871
SG
800
801 addr_hi |= ADDR_FILTX_FB_VALID;
802 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
e3c678e6
SG
803 if (ret < 0) {
804 netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
805 return ret;
806 }
d0cad871
SG
807
808 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
e3c678e6
SG
809 if (ret < 0)
810 netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
d0cad871 811
e3c678e6 812 return ret;
d0cad871
SG
813}
814
815static int smsc75xx_phy_initialize(struct usbnet *dev)
816{
b140504a 817 int bmcr, ret, timeout = 0;
d0cad871
SG
818
819 /* Initialize MII structure */
820 dev->mii.dev = dev->net;
821 dev->mii.mdio_read = smsc75xx_mdio_read;
822 dev->mii.mdio_write = smsc75xx_mdio_write;
823 dev->mii.phy_id_mask = 0x1f;
824 dev->mii.reg_num_mask = 0x1f;
c0b92e4d 825 dev->mii.supports_gmii = 1;
d0cad871
SG
826 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
827
828 /* reset phy and wait for reset to complete */
829 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
830
831 do {
832 msleep(10);
833 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
e3c678e6
SG
834 if (bmcr < 0) {
835 netdev_warn(dev->net, "Error reading MII_BMCR\n");
836 return bmcr;
837 }
d0cad871 838 timeout++;
8a1d59d7 839 } while ((bmcr & BMCR_RESET) && (timeout < 100));
d0cad871
SG
840
841 if (timeout >= 100) {
1e1d7412 842 netdev_warn(dev->net, "timeout on PHY Reset\n");
d0cad871
SG
843 return -EIO;
844 }
845
846 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
847 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
848 ADVERTISE_PAUSE_ASYM);
c0b92e4d
SG
849 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
850 ADVERTISE_1000FULL);
d0cad871 851
b140504a
SG
852 /* read and write to clear phy interrupt status */
853 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
e3c678e6
SG
854 if (ret < 0) {
855 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
856 return ret;
857 }
858
b140504a 859 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
d0cad871
SG
860
861 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
862 PHY_INT_MASK_DEFAULT);
863 mii_nway_restart(&dev->mii);
864
1e1d7412 865 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
d0cad871
SG
866 return 0;
867}
868
869static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
870{
871 int ret = 0;
872 u32 buf;
873 bool rxenabled;
874
875 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
876 if (ret < 0) {
877 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
878 return ret;
879 }
d0cad871
SG
880
881 rxenabled = ((buf & MAC_RX_RXEN) != 0);
882
883 if (rxenabled) {
884 buf &= ~MAC_RX_RXEN;
885 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
886 if (ret < 0) {
887 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
888 return ret;
889 }
d0cad871
SG
890 }
891
892 /* add 4 to size for FCS */
893 buf &= ~MAC_RX_MAX_SIZE;
894 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
895
896 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
897 if (ret < 0) {
898 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
899 return ret;
900 }
d0cad871
SG
901
902 if (rxenabled) {
903 buf |= MAC_RX_RXEN;
904 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
905 if (ret < 0) {
906 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
907 return ret;
908 }
d0cad871
SG
909 }
910
911 return 0;
912}
913
914static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
915{
916 struct usbnet *dev = netdev_priv(netdev);
4c51e536
SG
917 int ret;
918
919 if (new_mtu > MAX_SINGLE_PACKET_SIZE)
920 return -EINVAL;
d0cad871 921
4c51e536 922 ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
e3c678e6
SG
923 if (ret < 0) {
924 netdev_warn(dev->net, "Failed to set mac rx frame length\n");
925 return ret;
926 }
d0cad871
SG
927
928 return usbnet_change_mtu(netdev, new_mtu);
929}
930
78e47fe4 931/* Enable or disable Rx checksum offload engine */
c8f44aff
MM
932static int smsc75xx_set_features(struct net_device *netdev,
933 netdev_features_t features)
78e47fe4
MM
934{
935 struct usbnet *dev = netdev_priv(netdev);
936 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
937 unsigned long flags;
938 int ret;
939
940 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
941
942 if (features & NETIF_F_RXCSUM)
943 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
944 else
945 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
946
947 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
948 /* it's racing here! */
949
950 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
951 if (ret < 0)
952 netdev_warn(dev->net, "Error writing RFE_CTL\n");
78e47fe4 953
e3c678e6 954 return ret;
78e47fe4
MM
955}
956
47bbea41 957static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
8762cec8
SG
958{
959 int timeout = 0;
960
961 do {
962 u32 buf;
47bbea41
ML
963 int ret;
964
965 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
966
e3c678e6
SG
967 if (ret < 0) {
968 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
969 return ret;
970 }
8762cec8
SG
971
972 if (buf & PMT_CTL_DEV_RDY)
973 return 0;
974
975 msleep(10);
976 timeout++;
977 } while (timeout < 100);
978
1e1d7412 979 netdev_warn(dev->net, "timeout waiting for device ready\n");
8762cec8
SG
980 return -EIO;
981}
982
d0cad871
SG
983static int smsc75xx_reset(struct usbnet *dev)
984{
985 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
986 u32 buf;
987 int ret = 0, timeout;
988
1e1d7412 989 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
d0cad871 990
47bbea41 991 ret = smsc75xx_wait_ready(dev, 0);
e3c678e6
SG
992 if (ret < 0) {
993 netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
994 return ret;
995 }
8762cec8 996
d0cad871 997 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
998 if (ret < 0) {
999 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1000 return ret;
1001 }
d0cad871
SG
1002
1003 buf |= HW_CFG_LRST;
1004
1005 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1006 if (ret < 0) {
1007 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1008 return ret;
1009 }
d0cad871
SG
1010
1011 timeout = 0;
1012 do {
1013 msleep(10);
1014 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1015 if (ret < 0) {
1016 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1017 return ret;
1018 }
d0cad871
SG
1019 timeout++;
1020 } while ((buf & HW_CFG_LRST) && (timeout < 100));
1021
1022 if (timeout >= 100) {
1e1d7412 1023 netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
d0cad871
SG
1024 return -EIO;
1025 }
1026
1e1d7412 1027 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
d0cad871
SG
1028
1029 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1030 if (ret < 0) {
1031 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1032 return ret;
1033 }
d0cad871
SG
1034
1035 buf |= PMT_CTL_PHY_RST;
1036
1037 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
e3c678e6
SG
1038 if (ret < 0) {
1039 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1040 return ret;
1041 }
d0cad871
SG
1042
1043 timeout = 0;
1044 do {
1045 msleep(10);
1046 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1047 if (ret < 0) {
1048 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1049 return ret;
1050 }
d0cad871
SG
1051 timeout++;
1052 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
1053
1054 if (timeout >= 100) {
1e1d7412 1055 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
d0cad871
SG
1056 return -EIO;
1057 }
1058
1e1d7412 1059 netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
d0cad871 1060
d0cad871 1061 ret = smsc75xx_set_mac_address(dev);
e3c678e6
SG
1062 if (ret < 0) {
1063 netdev_warn(dev->net, "Failed to set mac address\n");
1064 return ret;
1065 }
d0cad871 1066
1e1d7412
JP
1067 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
1068 dev->net->dev_addr);
d0cad871
SG
1069
1070 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1071 if (ret < 0) {
1072 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1073 return ret;
1074 }
d0cad871 1075
1e1d7412
JP
1076 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
1077 buf);
d0cad871
SG
1078
1079 buf |= HW_CFG_BIR;
1080
1081 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1082 if (ret < 0) {
1083 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1084 return ret;
1085 }
d0cad871
SG
1086
1087 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1088 if (ret < 0) {
1089 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1090 return ret;
1091 }
d0cad871 1092
1e1d7412
JP
1093 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
1094 buf);
d0cad871
SG
1095
1096 if (!turbo_mode) {
1097 buf = 0;
1098 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
1099 } else if (dev->udev->speed == USB_SPEED_HIGH) {
1100 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
1101 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
1102 } else {
1103 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
1104 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
1105 }
1106
1e1d7412
JP
1107 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
1108 (ulong)dev->rx_urb_size);
d0cad871
SG
1109
1110 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
e3c678e6
SG
1111 if (ret < 0) {
1112 netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
1113 return ret;
1114 }
d0cad871
SG
1115
1116 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
e3c678e6
SG
1117 if (ret < 0) {
1118 netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
1119 return ret;
1120 }
d0cad871
SG
1121
1122 netif_dbg(dev, ifup, dev->net,
1e1d7412 1123 "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
d0cad871
SG
1124
1125 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
e3c678e6
SG
1126 if (ret < 0) {
1127 netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
1128 return ret;
1129 }
d0cad871
SG
1130
1131 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
e3c678e6
SG
1132 if (ret < 0) {
1133 netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
1134 return ret;
1135 }
d0cad871
SG
1136
1137 netif_dbg(dev, ifup, dev->net,
1e1d7412 1138 "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
d0cad871
SG
1139
1140 if (turbo_mode) {
1141 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1142 if (ret < 0) {
1143 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1144 return ret;
1145 }
d0cad871 1146
1e1d7412 1147 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1148
1149 buf |= (HW_CFG_MEF | HW_CFG_BCE);
1150
1151 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1152 if (ret < 0) {
1153 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1154 return ret;
1155 }
d0cad871
SG
1156
1157 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1158 if (ret < 0) {
1159 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1160 return ret;
1161 }
d0cad871 1162
1e1d7412 1163 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1164 }
1165
1166 /* set FIFO sizes */
1167 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
1168 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
e3c678e6
SG
1169 if (ret < 0) {
1170 netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
1171 return ret;
1172 }
d0cad871 1173
1e1d7412 1174 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1175
1176 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
1177 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
e3c678e6
SG
1178 if (ret < 0) {
1179 netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
1180 return ret;
1181 }
d0cad871 1182
1e1d7412 1183 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1184
1185 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
1186 if (ret < 0) {
1187 netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
1188 return ret;
1189 }
d0cad871
SG
1190
1191 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
e3c678e6
SG
1192 if (ret < 0) {
1193 netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
1194 return ret;
1195 }
d0cad871 1196
1e1d7412 1197 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
d0cad871 1198
97138a1c 1199 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
e3c678e6
SG
1200 if (ret < 0) {
1201 netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
1202 return ret;
1203 }
d0cad871 1204
97138a1c
SG
1205 /* only set default GPIO/LED settings if no EEPROM is detected */
1206 if (!(buf & E2P_CMD_LOADED)) {
1207 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
e3c678e6
SG
1208 if (ret < 0) {
1209 netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
1210 return ret;
1211 }
d0cad871 1212
97138a1c
SG
1213 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
1214 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
1215
1216 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
e3c678e6
SG
1217 if (ret < 0) {
1218 netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
1219 return ret;
1220 }
97138a1c 1221 }
d0cad871
SG
1222
1223 ret = smsc75xx_write_reg(dev, FLOW, 0);
e3c678e6
SG
1224 if (ret < 0) {
1225 netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
1226 return ret;
1227 }
d0cad871
SG
1228
1229 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
e3c678e6
SG
1230 if (ret < 0) {
1231 netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
1232 return ret;
1233 }
d0cad871
SG
1234
1235 /* Don't need rfe_ctl_lock during initialisation */
1236 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1237 if (ret < 0) {
1238 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1239 return ret;
1240 }
d0cad871
SG
1241
1242 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
1243
1244 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
1245 if (ret < 0) {
1246 netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
1247 return ret;
1248 }
d0cad871
SG
1249
1250 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1251 if (ret < 0) {
1252 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1253 return ret;
1254 }
d0cad871 1255
1e1d7412
JP
1256 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
1257 pdata->rfe_ctl);
d0cad871
SG
1258
1259 /* Enable or disable checksum offload engines */
78e47fe4 1260 smsc75xx_set_features(dev->net, dev->net->features);
d0cad871
SG
1261
1262 smsc75xx_set_multicast(dev->net);
1263
1264 ret = smsc75xx_phy_initialize(dev);
e3c678e6
SG
1265 if (ret < 0) {
1266 netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
1267 return ret;
1268 }
d0cad871
SG
1269
1270 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
e3c678e6
SG
1271 if (ret < 0) {
1272 netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
1273 return ret;
1274 }
d0cad871
SG
1275
1276 /* enable PHY interrupts */
1277 buf |= INT_ENP_PHY_INT;
1278
1279 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
e3c678e6
SG
1280 if (ret < 0) {
1281 netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
1282 return ret;
1283 }
d0cad871 1284
2f3a081e
SG
1285 /* allow mac to detect speed and duplex from phy */
1286 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
e3c678e6
SG
1287 if (ret < 0) {
1288 netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
1289 return ret;
1290 }
2f3a081e
SG
1291
1292 buf |= (MAC_CR_ADD | MAC_CR_ASD);
1293 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
e3c678e6
SG
1294 if (ret < 0) {
1295 netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
1296 return ret;
1297 }
2f3a081e 1298
d0cad871 1299 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
e3c678e6
SG
1300 if (ret < 0) {
1301 netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
1302 return ret;
1303 }
d0cad871
SG
1304
1305 buf |= MAC_TX_TXEN;
1306
1307 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
e3c678e6
SG
1308 if (ret < 0) {
1309 netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
1310 return ret;
1311 }
d0cad871 1312
1e1d7412 1313 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
d0cad871
SG
1314
1315 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
e3c678e6
SG
1316 if (ret < 0) {
1317 netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
1318 return ret;
1319 }
d0cad871
SG
1320
1321 buf |= FCT_TX_CTL_EN;
1322
1323 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
e3c678e6
SG
1324 if (ret < 0) {
1325 netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
1326 return ret;
1327 }
d0cad871 1328
1e1d7412 1329 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
d0cad871 1330
4c51e536 1331 ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
e3c678e6
SG
1332 if (ret < 0) {
1333 netdev_warn(dev->net, "Failed to set max rx frame length\n");
1334 return ret;
1335 }
d0cad871
SG
1336
1337 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
1338 if (ret < 0) {
1339 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
1340 return ret;
1341 }
d0cad871
SG
1342
1343 buf |= MAC_RX_RXEN;
1344
1345 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
1346 if (ret < 0) {
1347 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
1348 return ret;
1349 }
d0cad871 1350
1e1d7412 1351 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
d0cad871
SG
1352
1353 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
e3c678e6
SG
1354 if (ret < 0) {
1355 netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
1356 return ret;
1357 }
d0cad871
SG
1358
1359 buf |= FCT_RX_CTL_EN;
1360
1361 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
e3c678e6
SG
1362 if (ret < 0) {
1363 netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
1364 return ret;
1365 }
d0cad871 1366
1e1d7412 1367 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
d0cad871 1368
1e1d7412 1369 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
d0cad871
SG
1370 return 0;
1371}
1372
1373static const struct net_device_ops smsc75xx_netdev_ops = {
1374 .ndo_open = usbnet_open,
1375 .ndo_stop = usbnet_stop,
1376 .ndo_start_xmit = usbnet_start_xmit,
1377 .ndo_tx_timeout = usbnet_tx_timeout,
1378 .ndo_change_mtu = smsc75xx_change_mtu,
1379 .ndo_set_mac_address = eth_mac_addr,
1380 .ndo_validate_addr = eth_validate_addr,
1381 .ndo_do_ioctl = smsc75xx_ioctl,
afc4b13d 1382 .ndo_set_rx_mode = smsc75xx_set_multicast,
78e47fe4 1383 .ndo_set_features = smsc75xx_set_features,
d0cad871
SG
1384};
1385
1386static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
1387{
1388 struct smsc75xx_priv *pdata = NULL;
1389 int ret;
1390
1391 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1392
1393 ret = usbnet_get_endpoints(dev, intf);
e3c678e6
SG
1394 if (ret < 0) {
1395 netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
1396 return ret;
1397 }
d0cad871
SG
1398
1399 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
38673c82 1400 GFP_KERNEL);
d0cad871
SG
1401
1402 pdata = (struct smsc75xx_priv *)(dev->data[0]);
38673c82 1403 if (!pdata)
d0cad871 1404 return -ENOMEM;
d0cad871
SG
1405
1406 pdata->dev = dev;
1407
1408 spin_lock_init(&pdata->rfe_ctl_lock);
1409 mutex_init(&pdata->dataport_mutex);
1410
1411 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
1412
78e47fe4
MM
1413 if (DEFAULT_TX_CSUM_ENABLE) {
1414 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1415 if (DEFAULT_TSO_ENABLE)
1416 dev->net->features |= NETIF_F_SG |
1417 NETIF_F_TSO | NETIF_F_TSO6;
1418 }
1419 if (DEFAULT_RX_CSUM_ENABLE)
1420 dev->net->features |= NETIF_F_RXCSUM;
d0cad871 1421
78e47fe4
MM
1422 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1423 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_RXCSUM;
d0cad871 1424
481705a1
SG
1425 ret = smsc75xx_wait_ready(dev, 0);
1426 if (ret < 0) {
1427 netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
1428 return ret;
1429 }
1430
1431 smsc75xx_init_mac_address(dev);
1432
d0cad871
SG
1433 /* Init all registers */
1434 ret = smsc75xx_reset(dev);
e3c678e6
SG
1435 if (ret < 0) {
1436 netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
1437 return ret;
1438 }
d0cad871
SG
1439
1440 dev->net->netdev_ops = &smsc75xx_netdev_ops;
1441 dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
1442 dev->net->flags |= IFF_MULTICAST;
1443 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
a99ff7d0 1444 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
d0cad871
SG
1445 return 0;
1446}
1447
1448static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1449{
1450 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1451 if (pdata) {
1e1d7412 1452 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
d0cad871
SG
1453 kfree(pdata);
1454 pdata = NULL;
1455 dev->data[0] = 0;
1456 }
1457}
1458
899a391b
SG
1459static u16 smsc_crc(const u8 *buffer, size_t len)
1460{
1461 return bitrev16(crc16(0xFFFF, buffer, len));
1462}
1463
1464static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
1465 u32 wuf_mask1)
1466{
1467 int cfg_base = WUF_CFGX + filter * 4;
1468 int mask_base = WUF_MASKX + filter * 16;
1469 int ret;
1470
1471 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
e3c678e6
SG
1472 if (ret < 0) {
1473 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1474 return ret;
1475 }
899a391b
SG
1476
1477 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
e3c678e6
SG
1478 if (ret < 0) {
1479 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1480 return ret;
1481 }
899a391b
SG
1482
1483 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
e3c678e6
SG
1484 if (ret < 0) {
1485 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1486 return ret;
1487 }
899a391b
SG
1488
1489 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
e3c678e6
SG
1490 if (ret < 0) {
1491 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1492 return ret;
1493 }
899a391b
SG
1494
1495 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
e3c678e6
SG
1496 if (ret < 0) {
1497 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1498 return ret;
1499 }
899a391b
SG
1500
1501 return 0;
1502}
1503
9deb2757
SG
1504static int smsc75xx_enter_suspend0(struct usbnet *dev)
1505{
b4cdea9c 1506 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1507 u32 val;
1508 int ret;
1509
1510 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1511 if (ret < 0) {
1512 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1513 return ret;
1514 }
9deb2757
SG
1515
1516 val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
1517 val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
1518
1519 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1520 if (ret < 0) {
1521 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1522 return ret;
1523 }
9deb2757 1524
351f33d9 1525 pdata->suspend_flags |= SUSPEND_SUSPEND0;
b4cdea9c 1526
9deb2757
SG
1527 return 0;
1528}
1529
f329ccdc
SG
1530static int smsc75xx_enter_suspend1(struct usbnet *dev)
1531{
b4cdea9c 1532 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc
SG
1533 u32 val;
1534 int ret;
1535
1536 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1537 if (ret < 0) {
1538 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1539 return ret;
1540 }
f329ccdc
SG
1541
1542 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1543 val |= PMT_CTL_SUS_MODE_1;
1544
1545 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1546 if (ret < 0) {
1547 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1548 return ret;
1549 }
f329ccdc
SG
1550
1551 /* clear wol status, enable energy detection */
1552 val &= ~PMT_CTL_WUPS;
1553 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1554
1555 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1556 if (ret < 0) {
1557 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1558 return ret;
1559 }
f329ccdc 1560
351f33d9 1561 pdata->suspend_flags |= SUSPEND_SUSPEND1;
b4cdea9c 1562
f329ccdc
SG
1563 return 0;
1564}
1565
9deb2757
SG
1566static int smsc75xx_enter_suspend2(struct usbnet *dev)
1567{
b4cdea9c 1568 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1569 u32 val;
1570 int ret;
1571
1572 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1573 if (ret < 0) {
1574 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1575 return ret;
1576 }
9deb2757
SG
1577
1578 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1579 val |= PMT_CTL_SUS_MODE_2;
1580
1581 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1582 if (ret < 0) {
1583 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1584 return ret;
1585 }
9deb2757 1586
b4cdea9c
SG
1587 pdata->suspend_flags |= SUSPEND_SUSPEND2;
1588
1589 return 0;
1590}
1591
1592static int smsc75xx_enter_suspend3(struct usbnet *dev)
1593{
1594 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1595 u32 val;
1596 int ret;
1597
1598 ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
e3c678e6
SG
1599 if (ret < 0) {
1600 netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
1601 return ret;
1602 }
b4cdea9c
SG
1603
1604 if (val & FCT_RX_CTL_RXUSED) {
1605 netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
1606 return -EBUSY;
1607 }
1608
1609 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1610 if (ret < 0) {
1611 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1612 return ret;
1613 }
b4cdea9c
SG
1614
1615 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1616 val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
1617
1618 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1619 if (ret < 0) {
1620 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1621 return ret;
1622 }
b4cdea9c
SG
1623
1624 /* clear wol status */
1625 val &= ~PMT_CTL_WUPS;
1626 val |= PMT_CTL_WUPS_WOL;
1627
1628 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1629 if (ret < 0) {
1630 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1631 return ret;
1632 }
b4cdea9c 1633
351f33d9 1634 pdata->suspend_flags |= SUSPEND_SUSPEND3;
b4cdea9c 1635
9deb2757
SG
1636 return 0;
1637}
1638
f329ccdc
SG
1639static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
1640{
1641 struct mii_if_info *mii = &dev->mii;
1642 int ret;
1643
1644 netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
1645
1646 /* read to clear */
1647 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
e3c678e6
SG
1648 if (ret < 0) {
1649 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
1650 return ret;
1651 }
f329ccdc
SG
1652
1653 /* enable interrupt source */
1654 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
e3c678e6
SG
1655 if (ret < 0) {
1656 netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
1657 return ret;
1658 }
f329ccdc
SG
1659
1660 ret |= mask;
1661
1662 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1663
1664 return 0;
1665}
1666
1667static int smsc75xx_link_ok_nopm(struct usbnet *dev)
1668{
1669 struct mii_if_info *mii = &dev->mii;
1670 int ret;
1671
1672 /* first, a dummy read, needed to latch some MII phys */
1673 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1674 if (ret < 0) {
1675 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1676 return ret;
1677 }
f329ccdc
SG
1678
1679 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1680 if (ret < 0) {
1681 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1682 return ret;
1683 }
f329ccdc
SG
1684
1685 return !!(ret & BMSR_LSTATUS);
1686}
1687
b4cdea9c
SG
1688static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
1689{
1690 int ret;
1691
1692 if (!netif_running(dev->net)) {
1693 /* interface is ifconfig down so fully power down hw */
1694 netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
1695 return smsc75xx_enter_suspend2(dev);
1696 }
1697
1698 if (!link_up) {
1699 /* link is down so enter EDPD mode */
1700 netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
1701
1702 /* enable PHY wakeup events for if cable is attached */
1703 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1704 PHY_INT_MASK_ANEG_COMP);
e3c678e6
SG
1705 if (ret < 0) {
1706 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1707 return ret;
1708 }
b4cdea9c
SG
1709
1710 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1711 return smsc75xx_enter_suspend1(dev);
1712 }
1713
1714 /* enable PHY wakeup events so we remote wakeup if cable is pulled */
1715 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1716 PHY_INT_MASK_LINK_DOWN);
e3c678e6
SG
1717 if (ret < 0) {
1718 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1719 return ret;
1720 }
b4cdea9c
SG
1721
1722 netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
1723 return smsc75xx_enter_suspend3(dev);
1724}
1725
16c79a04
SG
1726static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
1727{
1728 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1729 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc 1730 u32 val, link_up;
16c79a04 1731 int ret;
16c79a04 1732
16c79a04 1733 ret = usbnet_suspend(intf, message);
e3c678e6
SG
1734 if (ret < 0) {
1735 netdev_warn(dev->net, "usbnet_suspend error\n");
1736 return ret;
1737 }
16c79a04 1738
b4cdea9c
SG
1739 if (pdata->suspend_flags) {
1740 netdev_warn(dev->net, "error during last resume\n");
1741 pdata->suspend_flags = 0;
1742 }
1743
f329ccdc
SG
1744 /* determine if link is up using only _nopm functions */
1745 link_up = smsc75xx_link_ok_nopm(dev);
1746
b4cdea9c
SG
1747 if (message.event == PM_EVENT_AUTO_SUSPEND) {
1748 ret = smsc75xx_autosuspend(dev, link_up);
1749 goto done;
1750 }
1751
1752 /* if we get this far we're not autosuspending */
f329ccdc
SG
1753 /* if no wol options set, or if link is down and we're not waking on
1754 * PHY activity, enter lowest power SUSPEND2 mode
1755 */
1756 if (!(pdata->wolopts & SUPPORTED_WAKE) ||
1757 !(link_up || (pdata->wolopts & WAKE_PHY))) {
1e1d7412 1758 netdev_info(dev->net, "entering SUSPEND2 mode\n");
6c636503
SG
1759
1760 /* disable energy detect (link up) & wake up events */
47bbea41 1761 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1762 if (ret < 0) {
1763 netdev_warn(dev->net, "Error reading WUCSR\n");
1764 goto done;
1765 }
6c636503
SG
1766
1767 val &= ~(WUCSR_MPEN | WUCSR_WUEN);
1768
47bbea41 1769 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1770 if (ret < 0) {
1771 netdev_warn(dev->net, "Error writing WUCSR\n");
1772 goto done;
1773 }
6c636503 1774
47bbea41 1775 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1776 if (ret < 0) {
1777 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1778 goto done;
1779 }
6c636503
SG
1780
1781 val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
1782
47bbea41 1783 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1784 if (ret < 0) {
1785 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1786 goto done;
1787 }
6c636503 1788
eacdd6c2
SG
1789 ret = smsc75xx_enter_suspend2(dev);
1790 goto done;
6c636503
SG
1791 }
1792
f329ccdc
SG
1793 if (pdata->wolopts & WAKE_PHY) {
1794 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1795 (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
e3c678e6
SG
1796 if (ret < 0) {
1797 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1798 goto done;
1799 }
f329ccdc
SG
1800
1801 /* if link is down then configure EDPD and enter SUSPEND1,
1802 * otherwise enter SUSPEND0 below
1803 */
1804 if (!link_up) {
1805 struct mii_if_info *mii = &dev->mii;
1806 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1807
1808 /* enable energy detect power-down mode */
1809 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1810 PHY_MODE_CTRL_STS);
e3c678e6
SG
1811 if (ret < 0) {
1812 netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
1813 goto done;
1814 }
f329ccdc
SG
1815
1816 ret |= MODE_CTRL_STS_EDPWRDOWN;
1817
1818 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
1819 PHY_MODE_CTRL_STS, ret);
1820
1821 /* enter SUSPEND1 mode */
eacdd6c2
SG
1822 ret = smsc75xx_enter_suspend1(dev);
1823 goto done;
f329ccdc
SG
1824 }
1825 }
1826
899a391b
SG
1827 if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
1828 int i, filter = 0;
1829
1830 /* disable all filters */
1831 for (i = 0; i < WUF_NUM; i++) {
47bbea41 1832 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
e3c678e6
SG
1833 if (ret < 0) {
1834 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1835 goto done;
1836 }
899a391b
SG
1837 }
1838
1839 if (pdata->wolopts & WAKE_MCAST) {
1840 const u8 mcast[] = {0x01, 0x00, 0x5E};
1e1d7412 1841 netdev_info(dev->net, "enabling multicast detection\n");
899a391b
SG
1842
1843 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
1844 | smsc_crc(mcast, 3);
1845 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
e3c678e6
SG
1846 if (ret < 0) {
1847 netdev_warn(dev->net, "Error writing wakeup filter\n");
1848 goto done;
1849 }
899a391b
SG
1850 }
1851
1852 if (pdata->wolopts & WAKE_ARP) {
1853 const u8 arp[] = {0x08, 0x06};
1e1d7412 1854 netdev_info(dev->net, "enabling ARP detection\n");
899a391b
SG
1855
1856 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
1857 | smsc_crc(arp, 2);
1858 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
e3c678e6
SG
1859 if (ret < 0) {
1860 netdev_warn(dev->net, "Error writing wakeup filter\n");
1861 goto done;
1862 }
899a391b
SG
1863 }
1864
1865 /* clear any pending pattern match packet status */
47bbea41 1866 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1867 if (ret < 0) {
1868 netdev_warn(dev->net, "Error reading WUCSR\n");
1869 goto done;
1870 }
899a391b
SG
1871
1872 val |= WUCSR_WUFR;
1873
47bbea41 1874 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1875 if (ret < 0) {
1876 netdev_warn(dev->net, "Error writing WUCSR\n");
1877 goto done;
1878 }
899a391b 1879
1e1d7412 1880 netdev_info(dev->net, "enabling packet match detection\n");
47bbea41 1881 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1882 if (ret < 0) {
1883 netdev_warn(dev->net, "Error reading WUCSR\n");
1884 goto done;
1885 }
899a391b
SG
1886
1887 val |= WUCSR_WUEN;
1888
47bbea41 1889 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1890 if (ret < 0) {
1891 netdev_warn(dev->net, "Error writing WUCSR\n");
1892 goto done;
1893 }
899a391b 1894 } else {
1e1d7412 1895 netdev_info(dev->net, "disabling packet match detection\n");
47bbea41 1896 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1897 if (ret < 0) {
1898 netdev_warn(dev->net, "Error reading WUCSR\n");
1899 goto done;
1900 }
6c636503 1901
899a391b 1902 val &= ~WUCSR_WUEN;
16c79a04 1903
47bbea41 1904 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1905 if (ret < 0) {
1906 netdev_warn(dev->net, "Error writing WUCSR\n");
1907 goto done;
1908 }
6c636503
SG
1909 }
1910
899a391b 1911 /* disable magic, bcast & unicast wakeup sources */
47bbea41 1912 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1913 if (ret < 0) {
1914 netdev_warn(dev->net, "Error reading WUCSR\n");
1915 goto done;
1916 }
6c636503 1917
899a391b
SG
1918 val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
1919
47bbea41 1920 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1921 if (ret < 0) {
1922 netdev_warn(dev->net, "Error writing WUCSR\n");
1923 goto done;
1924 }
899a391b 1925
f329ccdc
SG
1926 if (pdata->wolopts & WAKE_PHY) {
1927 netdev_info(dev->net, "enabling PHY wakeup\n");
1928
1929 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1930 if (ret < 0) {
1931 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1932 goto done;
1933 }
f329ccdc
SG
1934
1935 /* clear wol status, enable energy detection */
1936 val &= ~PMT_CTL_WUPS;
1937 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1938
1939 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1940 if (ret < 0) {
1941 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1942 goto done;
1943 }
f329ccdc
SG
1944 }
1945
6c636503 1946 if (pdata->wolopts & WAKE_MAGIC) {
1e1d7412 1947 netdev_info(dev->net, "enabling magic packet wakeup\n");
47bbea41 1948 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1949 if (ret < 0) {
1950 netdev_warn(dev->net, "Error reading WUCSR\n");
1951 goto done;
1952 }
899a391b
SG
1953
1954 /* clear any pending magic packet status */
1955 val |= WUCSR_MPR | WUCSR_MPEN;
1956
47bbea41 1957 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1958 if (ret < 0) {
1959 netdev_warn(dev->net, "Error writing WUCSR\n");
1960 goto done;
1961 }
6c636503
SG
1962 }
1963
899a391b 1964 if (pdata->wolopts & WAKE_BCAST) {
1e1d7412 1965 netdev_info(dev->net, "enabling broadcast detection\n");
47bbea41 1966 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1967 if (ret < 0) {
1968 netdev_warn(dev->net, "Error reading WUCSR\n");
1969 goto done;
1970 }
6c636503 1971
899a391b 1972 val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
16c79a04 1973
47bbea41 1974 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1975 if (ret < 0) {
1976 netdev_warn(dev->net, "Error writing WUCSR\n");
1977 goto done;
1978 }
899a391b 1979 }
6c636503 1980
899a391b 1981 if (pdata->wolopts & WAKE_UCAST) {
1e1d7412 1982 netdev_info(dev->net, "enabling unicast detection\n");
47bbea41 1983 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1984 if (ret < 0) {
1985 netdev_warn(dev->net, "Error reading WUCSR\n");
1986 goto done;
1987 }
899a391b
SG
1988
1989 val |= WUCSR_WUFR | WUCSR_PFDA_EN;
6c636503 1990
47bbea41 1991 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1992 if (ret < 0) {
1993 netdev_warn(dev->net, "Error writing WUCSR\n");
1994 goto done;
1995 }
899a391b
SG
1996 }
1997
1998 /* enable receiver to enable frame reception */
47bbea41 1999 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
e3c678e6
SG
2000 if (ret < 0) {
2001 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
2002 goto done;
2003 }
6c636503
SG
2004
2005 val |= MAC_RX_RXEN;
2006
47bbea41 2007 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
e3c678e6
SG
2008 if (ret < 0) {
2009 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
2010 goto done;
2011 }
6c636503
SG
2012
2013 /* some wol options are enabled, so enter SUSPEND0 */
1e1d7412 2014 netdev_info(dev->net, "entering SUSPEND0 mode\n");
eacdd6c2
SG
2015 ret = smsc75xx_enter_suspend0(dev);
2016
2017done:
2018 if (ret)
2019 usbnet_resume(intf);
2020 return ret;
16c79a04
SG
2021}
2022
2023static int smsc75xx_resume(struct usb_interface *intf)
2024{
2025 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 2026 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
b4cdea9c 2027 u8 suspend_flags = pdata->suspend_flags;
16c79a04
SG
2028 int ret;
2029 u32 val;
2030
b4cdea9c 2031 netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
16c79a04 2032
b4cdea9c
SG
2033 /* do this first to ensure it's cleared even in error case */
2034 pdata->suspend_flags = 0;
2035
b4cdea9c 2036 if (suspend_flags & SUSPEND_ALLMODES) {
899a391b 2037 /* Disable wakeup sources */
47bbea41 2038 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
2039 if (ret < 0) {
2040 netdev_warn(dev->net, "Error reading WUCSR\n");
2041 return ret;
2042 }
16c79a04 2043
899a391b
SG
2044 val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
2045 | WUCSR_BCST_EN);
16c79a04 2046
47bbea41 2047 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
2048 if (ret < 0) {
2049 netdev_warn(dev->net, "Error writing WUCSR\n");
2050 return ret;
2051 }
6c636503
SG
2052
2053 /* clear wake-up status */
47bbea41 2054 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2055 if (ret < 0) {
2056 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2057 return ret;
2058 }
6c636503
SG
2059
2060 val &= ~PMT_CTL_WOL_EN;
2061 val |= PMT_CTL_WUPS;
2062
47bbea41 2063 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2064 if (ret < 0) {
2065 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2066 return ret;
2067 }
b4cdea9c
SG
2068 }
2069
2070 if (suspend_flags & SUSPEND_SUSPEND2) {
1e1d7412 2071 netdev_info(dev->net, "resuming from SUSPEND2\n");
6c636503 2072
47bbea41 2073 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2074 if (ret < 0) {
2075 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2076 return ret;
2077 }
6c636503
SG
2078
2079 val |= PMT_CTL_PHY_PWRUP;
2080
47bbea41 2081 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2082 if (ret < 0) {
2083 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2084 return ret;
2085 }
6c636503 2086 }
16c79a04 2087
47bbea41 2088 ret = smsc75xx_wait_ready(dev, 1);
e3c678e6
SG
2089 if (ret < 0) {
2090 netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
2091 return ret;
2092 }
16c79a04
SG
2093
2094 return usbnet_resume(intf);
2095}
2096
78e47fe4
MM
2097static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
2098 u32 rx_cmd_a, u32 rx_cmd_b)
d0cad871 2099{
78e47fe4
MM
2100 if (!(dev->net->features & NETIF_F_RXCSUM) ||
2101 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
d0cad871
SG
2102 skb->ip_summed = CHECKSUM_NONE;
2103 } else {
2104 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
2105 skb->ip_summed = CHECKSUM_COMPLETE;
2106 }
2107}
2108
2109static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
2110{
d0cad871
SG
2111 while (skb->len > 0) {
2112 u32 rx_cmd_a, rx_cmd_b, align_count, size;
2113 struct sk_buff *ax_skb;
2114 unsigned char *packet;
2115
2116 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
2117 le32_to_cpus(&rx_cmd_a);
2118 skb_pull(skb, 4);
2119
2120 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
2121 le32_to_cpus(&rx_cmd_b);
ea1649de 2122 skb_pull(skb, 4 + RXW_PADDING);
d0cad871
SG
2123
2124 packet = skb->data;
2125
2126 /* get the packet length */
ea1649de
NE
2127 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
2128 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
d0cad871
SG
2129
2130 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
2131 netif_dbg(dev, rx_err, dev->net,
1e1d7412 2132 "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
d0cad871
SG
2133 dev->net->stats.rx_errors++;
2134 dev->net->stats.rx_dropped++;
2135
2136 if (rx_cmd_a & RX_CMD_A_FCS)
2137 dev->net->stats.rx_crc_errors++;
2138 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
2139 dev->net->stats.rx_frame_errors++;
2140 } else {
4c51e536
SG
2141 /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
2142 if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
d0cad871 2143 netif_dbg(dev, rx_err, dev->net,
1e1d7412
JP
2144 "size err rx_cmd_a=0x%08x\n",
2145 rx_cmd_a);
d0cad871
SG
2146 return 0;
2147 }
2148
2149 /* last frame in this batch */
2150 if (skb->len == size) {
78e47fe4
MM
2151 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
2152 rx_cmd_b);
d0cad871
SG
2153
2154 skb_trim(skb, skb->len - 4); /* remove fcs */
2155 skb->truesize = size + sizeof(struct sk_buff);
2156
2157 return 1;
2158 }
2159
2160 ax_skb = skb_clone(skb, GFP_ATOMIC);
2161 if (unlikely(!ax_skb)) {
1e1d7412 2162 netdev_warn(dev->net, "Error allocating skb\n");
d0cad871
SG
2163 return 0;
2164 }
2165
2166 ax_skb->len = size;
2167 ax_skb->data = packet;
2168 skb_set_tail_pointer(ax_skb, size);
2169
78e47fe4
MM
2170 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
2171 rx_cmd_b);
d0cad871
SG
2172
2173 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
2174 ax_skb->truesize = size + sizeof(struct sk_buff);
2175
2176 usbnet_skb_return(dev, ax_skb);
2177 }
2178
2179 skb_pull(skb, size);
2180
2181 /* padding bytes before the next frame starts */
2182 if (skb->len)
2183 skb_pull(skb, align_count);
2184 }
2185
2186 if (unlikely(skb->len < 0)) {
1e1d7412 2187 netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
d0cad871
SG
2188 return 0;
2189 }
2190
2191 return 1;
2192}
2193
2194static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
2195 struct sk_buff *skb, gfp_t flags)
2196{
2197 u32 tx_cmd_a, tx_cmd_b;
2198
2199 skb_linearize(skb);
2200
2201 if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
2202 struct sk_buff *skb2 =
2203 skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
2204 dev_kfree_skb_any(skb);
2205 skb = skb2;
2206 if (!skb)
2207 return NULL;
2208 }
2209
2210 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
2211
2212 if (skb->ip_summed == CHECKSUM_PARTIAL)
2213 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
2214
2215 if (skb_is_gso(skb)) {
2216 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
2217 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
2218
2219 tx_cmd_a |= TX_CMD_A_LSO;
2220 } else {
2221 tx_cmd_b = 0;
2222 }
2223
2224 skb_push(skb, 4);
2225 cpu_to_le32s(&tx_cmd_b);
2226 memcpy(skb->data, &tx_cmd_b, 4);
2227
2228 skb_push(skb, 4);
2229 cpu_to_le32s(&tx_cmd_a);
2230 memcpy(skb->data, &tx_cmd_a, 4);
2231
2232 return skb;
2233}
2234
b4cdea9c
SG
2235static int smsc75xx_manage_power(struct usbnet *dev, int on)
2236{
2237 dev->intf->needs_remote_wakeup = on;
2238 return 0;
2239}
2240
d0cad871
SG
2241static const struct driver_info smsc75xx_info = {
2242 .description = "smsc75xx USB 2.0 Gigabit Ethernet",
2243 .bind = smsc75xx_bind,
2244 .unbind = smsc75xx_unbind,
2245 .link_reset = smsc75xx_link_reset,
2246 .reset = smsc75xx_reset,
2247 .rx_fixup = smsc75xx_rx_fixup,
2248 .tx_fixup = smsc75xx_tx_fixup,
2249 .status = smsc75xx_status,
b4cdea9c 2250 .manage_power = smsc75xx_manage_power,
7bdd305e 2251 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
d0cad871
SG
2252};
2253
2254static const struct usb_device_id products[] = {
2255 {
2256 /* SMSC7500 USB Gigabit Ethernet Device */
2257 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
2258 .driver_info = (unsigned long) &smsc75xx_info,
2259 },
2260 {
2261 /* SMSC7500 USB Gigabit Ethernet Device */
2262 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
2263 .driver_info = (unsigned long) &smsc75xx_info,
2264 },
2265 { }, /* END */
2266};
2267MODULE_DEVICE_TABLE(usb, products);
2268
2269static struct usb_driver smsc75xx_driver = {
2270 .name = SMSC_CHIPNAME,
2271 .id_table = products,
2272 .probe = usbnet_probe,
16c79a04
SG
2273 .suspend = smsc75xx_suspend,
2274 .resume = smsc75xx_resume,
2275 .reset_resume = smsc75xx_resume,
d0cad871 2276 .disconnect = usbnet_disconnect,
e1f12eb6 2277 .disable_hub_initiated_lpm = 1,
b4cdea9c 2278 .supports_autosuspend = 1,
d0cad871
SG
2279};
2280
d632eb1b 2281module_usb_driver(smsc75xx_driver);
d0cad871
SG
2282
2283MODULE_AUTHOR("Nancy Lin");
90b24cfb 2284MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
d0cad871
SG
2285MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
2286MODULE_LICENSE("GPL");
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