Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / drivers / net / usb / smsc75xx.c
CommitLineData
d0cad871
SG
1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2010 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
9cb00073 16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
d0cad871
SG
17 *
18 *****************************************************************************/
19
20#include <linux/module.h>
21#include <linux/kmod.h>
d0cad871
SG
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/usb.h>
899a391b
SG
27#include <linux/bitrev.h>
28#include <linux/crc16.h>
d0cad871
SG
29#include <linux/crc32.h>
30#include <linux/usb/usbnet.h>
5a0e3ad6 31#include <linux/slab.h>
c489565b 32#include <linux/of_net.h>
d0cad871
SG
33#include "smsc75xx.h"
34
35#define SMSC_CHIPNAME "smsc75xx"
36#define SMSC_DRIVER_VERSION "1.0.0"
37#define HS_USB_PKT_SIZE (512)
38#define FS_USB_PKT_SIZE (64)
39#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
40#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
41#define DEFAULT_BULK_IN_DELAY (0x00002000)
42#define MAX_SINGLE_PACKET_SIZE (9000)
43#define LAN75XX_EEPROM_MAGIC (0x7500)
44#define EEPROM_MAC_OFFSET (0x01)
45#define DEFAULT_TX_CSUM_ENABLE (true)
46#define DEFAULT_RX_CSUM_ENABLE (true)
d0cad871
SG
47#define SMSC75XX_INTERNAL_PHY_ID (1)
48#define SMSC75XX_TX_OVERHEAD (8)
49#define MAX_RX_FIFO_SIZE (20 * 1024)
50#define MAX_TX_FIFO_SIZE (12 * 1024)
51#define USB_VENDOR_ID_SMSC (0x0424)
52#define USB_PRODUCT_ID_LAN7500 (0x7500)
53#define USB_PRODUCT_ID_LAN7505 (0x7505)
ea1649de 54#define RXW_PADDING 2
f329ccdc 55#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
899a391b 56 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
d0cad871 57
b4cdea9c
SG
58#define SUSPEND_SUSPEND0 (0x01)
59#define SUSPEND_SUSPEND1 (0x02)
60#define SUSPEND_SUSPEND2 (0x04)
61#define SUSPEND_SUSPEND3 (0x08)
b4cdea9c
SG
62#define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
63 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
64
d0cad871
SG
65struct smsc75xx_priv {
66 struct usbnet *dev;
67 u32 rfe_ctl;
6c636503 68 u32 wolopts;
d0cad871 69 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
d0cad871
SG
70 struct mutex dataport_mutex;
71 spinlock_t rfe_ctl_lock;
72 struct work_struct set_multicast;
b4cdea9c 73 u8 suspend_flags;
d0cad871
SG
74};
75
76struct usb_context {
77 struct usb_ctrlrequest req;
78 struct usbnet *dev;
79};
80
eb939922 81static bool turbo_mode = true;
d0cad871
SG
82module_param(turbo_mode, bool, 0644);
83MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
84
47bbea41
ML
85static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
86 u32 *data, int in_pm)
d0cad871 87{
2b2e41e3 88 u32 buf;
d0cad871 89 int ret;
47bbea41 90 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
d0cad871
SG
91
92 BUG_ON(!dev);
93
47bbea41
ML
94 if (!in_pm)
95 fn = usbnet_read_cmd;
96 else
97 fn = usbnet_read_cmd_nopm;
98
99 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
100 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
101 0, index, &buf, 4);
58ef6a3f 102 if (unlikely(ret < 0)) {
1e1d7412
JP
103 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
104 index, ret);
58ef6a3f
DC
105 return ret;
106 }
d0cad871 107
2b2e41e3
ML
108 le32_to_cpus(&buf);
109 *data = buf;
d0cad871
SG
110
111 return ret;
112}
113
47bbea41
ML
114static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
115 u32 data, int in_pm)
d0cad871 116{
2b2e41e3 117 u32 buf;
d0cad871 118 int ret;
47bbea41 119 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
d0cad871
SG
120
121 BUG_ON(!dev);
122
47bbea41
ML
123 if (!in_pm)
124 fn = usbnet_write_cmd;
125 else
126 fn = usbnet_write_cmd_nopm;
127
2b2e41e3
ML
128 buf = data;
129 cpu_to_le32s(&buf);
d0cad871 130
47bbea41
ML
131 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
132 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
133 0, index, &buf, 4);
d0cad871 134 if (unlikely(ret < 0))
1e1d7412
JP
135 netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
136 index, ret);
d0cad871 137
d0cad871
SG
138 return ret;
139}
140
47bbea41
ML
141static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
142 u32 *data)
143{
144 return __smsc75xx_read_reg(dev, index, data, 1);
145}
146
147static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
148 u32 data)
149{
150 return __smsc75xx_write_reg(dev, index, data, 1);
151}
152
153static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
154 u32 *data)
155{
156 return __smsc75xx_read_reg(dev, index, data, 0);
157}
158
159static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
160 u32 data)
161{
162 return __smsc75xx_write_reg(dev, index, data, 0);
163}
164
d0cad871
SG
165/* Loop until the read is completed with timeout
166 * called with phy_mutex held */
f329ccdc
SG
167static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
168 int in_pm)
d0cad871
SG
169{
170 unsigned long start_time = jiffies;
171 u32 val;
172 int ret;
173
174 do {
f329ccdc 175 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
e3c678e6
SG
176 if (ret < 0) {
177 netdev_warn(dev->net, "Error reading MII_ACCESS\n");
178 return ret;
179 }
d0cad871
SG
180
181 if (!(val & MII_ACCESS_BUSY))
182 return 0;
183 } while (!time_after(jiffies, start_time + HZ));
184
185 return -EIO;
186}
187
f329ccdc
SG
188static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
189 int in_pm)
d0cad871
SG
190{
191 struct usbnet *dev = netdev_priv(netdev);
192 u32 val, addr;
193 int ret;
194
195 mutex_lock(&dev->phy_mutex);
196
197 /* confirm MII not busy */
f329ccdc 198 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
199 if (ret < 0) {
200 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
201 goto done;
202 }
d0cad871
SG
203
204 /* set the address, index & direction (read from PHY) */
205 phy_id &= dev->mii.phy_id_mask;
206 idx &= dev->mii.reg_num_mask;
207 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
208 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 209 | MII_ACCESS_READ | MII_ACCESS_BUSY;
f329ccdc 210 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
211 if (ret < 0) {
212 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
213 goto done;
214 }
d0cad871 215
f329ccdc 216 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
217 if (ret < 0) {
218 netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
219 goto done;
220 }
d0cad871 221
f329ccdc 222 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
e3c678e6
SG
223 if (ret < 0) {
224 netdev_warn(dev->net, "Error reading MII_DATA\n");
225 goto done;
226 }
d0cad871
SG
227
228 ret = (u16)(val & 0xFFFF);
229
230done:
231 mutex_unlock(&dev->phy_mutex);
232 return ret;
233}
234
f329ccdc
SG
235static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
236 int idx, int regval, int in_pm)
d0cad871
SG
237{
238 struct usbnet *dev = netdev_priv(netdev);
239 u32 val, addr;
240 int ret;
241
242 mutex_lock(&dev->phy_mutex);
243
244 /* confirm MII not busy */
f329ccdc 245 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
246 if (ret < 0) {
247 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
248 goto done;
249 }
d0cad871
SG
250
251 val = regval;
f329ccdc 252 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
e3c678e6
SG
253 if (ret < 0) {
254 netdev_warn(dev->net, "Error writing MII_DATA\n");
255 goto done;
256 }
d0cad871
SG
257
258 /* set the address, index & direction (write to PHY) */
259 phy_id &= dev->mii.phy_id_mask;
260 idx &= dev->mii.reg_num_mask;
261 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
262 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 263 | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
f329ccdc 264 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
265 if (ret < 0) {
266 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
267 goto done;
268 }
d0cad871 269
f329ccdc 270 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
271 if (ret < 0) {
272 netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
273 goto done;
274 }
d0cad871
SG
275
276done:
277 mutex_unlock(&dev->phy_mutex);
278}
279
f329ccdc
SG
280static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
281 int idx)
282{
283 return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
284}
285
286static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
287 int idx, int regval)
288{
289 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
290}
291
292static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
293{
294 return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
295}
296
297static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
298 int regval)
299{
300 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
301}
302
d0cad871
SG
303static int smsc75xx_wait_eeprom(struct usbnet *dev)
304{
305 unsigned long start_time = jiffies;
306 u32 val;
307 int ret;
308
309 do {
310 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
311 if (ret < 0) {
312 netdev_warn(dev->net, "Error reading E2P_CMD\n");
313 return ret;
314 }
d0cad871
SG
315
316 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
317 break;
318 udelay(40);
319 } while (!time_after(jiffies, start_time + HZ));
320
321 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
1e1d7412 322 netdev_warn(dev->net, "EEPROM read operation timeout\n");
d0cad871
SG
323 return -EIO;
324 }
325
326 return 0;
327}
328
329static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
330{
331 unsigned long start_time = jiffies;
332 u32 val;
333 int ret;
334
335 do {
336 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
337 if (ret < 0) {
338 netdev_warn(dev->net, "Error reading E2P_CMD\n");
339 return ret;
340 }
d0cad871
SG
341
342 if (!(val & E2P_CMD_BUSY))
343 return 0;
344
345 udelay(40);
346 } while (!time_after(jiffies, start_time + HZ));
347
1e1d7412 348 netdev_warn(dev->net, "EEPROM is busy\n");
d0cad871
SG
349 return -EIO;
350}
351
352static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
353 u8 *data)
354{
355 u32 val;
356 int i, ret;
357
358 BUG_ON(!dev);
359 BUG_ON(!data);
360
361 ret = smsc75xx_eeprom_confirm_not_busy(dev);
362 if (ret)
363 return ret;
364
365 for (i = 0; i < length; i++) {
366 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
367 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
368 if (ret < 0) {
369 netdev_warn(dev->net, "Error writing E2P_CMD\n");
370 return ret;
371 }
d0cad871
SG
372
373 ret = smsc75xx_wait_eeprom(dev);
374 if (ret < 0)
375 return ret;
376
377 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
e3c678e6
SG
378 if (ret < 0) {
379 netdev_warn(dev->net, "Error reading E2P_DATA\n");
380 return ret;
381 }
d0cad871
SG
382
383 data[i] = val & 0xFF;
384 offset++;
385 }
386
387 return 0;
388}
389
390static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
391 u8 *data)
392{
393 u32 val;
394 int i, ret;
395
396 BUG_ON(!dev);
397 BUG_ON(!data);
398
399 ret = smsc75xx_eeprom_confirm_not_busy(dev);
400 if (ret)
401 return ret;
402
403 /* Issue write/erase enable command */
404 val = E2P_CMD_BUSY | E2P_CMD_EWEN;
405 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
406 if (ret < 0) {
407 netdev_warn(dev->net, "Error writing E2P_CMD\n");
408 return ret;
409 }
d0cad871
SG
410
411 ret = smsc75xx_wait_eeprom(dev);
412 if (ret < 0)
413 return ret;
414
415 for (i = 0; i < length; i++) {
416
417 /* Fill data register */
418 val = data[i];
419 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
e3c678e6
SG
420 if (ret < 0) {
421 netdev_warn(dev->net, "Error writing E2P_DATA\n");
422 return ret;
423 }
d0cad871
SG
424
425 /* Send "write" command */
426 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
427 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
428 if (ret < 0) {
429 netdev_warn(dev->net, "Error writing E2P_CMD\n");
430 return ret;
431 }
d0cad871
SG
432
433 ret = smsc75xx_wait_eeprom(dev);
434 if (ret < 0)
435 return ret;
436
437 offset++;
438 }
439
440 return 0;
441}
442
443static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
444{
445 int i, ret;
446
447 for (i = 0; i < 100; i++) {
448 u32 dp_sel;
449 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
450 if (ret < 0) {
451 netdev_warn(dev->net, "Error reading DP_SEL\n");
452 return ret;
453 }
d0cad871
SG
454
455 if (dp_sel & DP_SEL_DPRDY)
456 return 0;
457
458 udelay(40);
459 }
460
1e1d7412 461 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
d0cad871
SG
462
463 return -EIO;
464}
465
466static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
467 u32 length, u32 *buf)
468{
469 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
470 u32 dp_sel;
471 int i, ret;
472
473 mutex_lock(&pdata->dataport_mutex);
474
475 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
476 if (ret < 0) {
477 netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
478 goto done;
479 }
d0cad871
SG
480
481 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
482 if (ret < 0) {
483 netdev_warn(dev->net, "Error reading DP_SEL\n");
484 goto done;
485 }
d0cad871
SG
486
487 dp_sel &= ~DP_SEL_RSEL;
488 dp_sel |= ram_select;
489 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
e3c678e6
SG
490 if (ret < 0) {
491 netdev_warn(dev->net, "Error writing DP_SEL\n");
492 goto done;
493 }
d0cad871
SG
494
495 for (i = 0; i < length; i++) {
496 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
e3c678e6
SG
497 if (ret < 0) {
498 netdev_warn(dev->net, "Error writing DP_ADDR\n");
499 goto done;
500 }
d0cad871
SG
501
502 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
e3c678e6
SG
503 if (ret < 0) {
504 netdev_warn(dev->net, "Error writing DP_DATA\n");
505 goto done;
506 }
d0cad871
SG
507
508 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
e3c678e6
SG
509 if (ret < 0) {
510 netdev_warn(dev->net, "Error writing DP_CMD\n");
511 goto done;
512 }
d0cad871
SG
513
514 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
515 if (ret < 0) {
516 netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
517 goto done;
518 }
d0cad871
SG
519 }
520
521done:
522 mutex_unlock(&pdata->dataport_mutex);
523 return ret;
524}
525
526/* returns hash bit number for given MAC address */
527static u32 smsc75xx_hash(char addr[ETH_ALEN])
528{
529 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
530}
531
532static void smsc75xx_deferred_multicast_write(struct work_struct *param)
533{
534 struct smsc75xx_priv *pdata =
535 container_of(param, struct smsc75xx_priv, set_multicast);
536 struct usbnet *dev = pdata->dev;
537 int ret;
538
1e1d7412
JP
539 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
540 pdata->rfe_ctl);
d0cad871
SG
541
542 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
543 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
544
545 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
546 if (ret < 0)
547 netdev_warn(dev->net, "Error writing RFE_CRL\n");
d0cad871
SG
548}
549
550static void smsc75xx_set_multicast(struct net_device *netdev)
551{
552 struct usbnet *dev = netdev_priv(netdev);
553 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
554 unsigned long flags;
555 int i;
556
557 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
558
559 pdata->rfe_ctl &=
560 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
561 pdata->rfe_ctl |= RFE_CTL_AB;
562
563 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
564 pdata->multicast_hash_table[i] = 0;
565
566 if (dev->net->flags & IFF_PROMISC) {
1e1d7412 567 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
d0cad871
SG
568 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
569 } else if (dev->net->flags & IFF_ALLMULTI) {
1e1d7412 570 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
d0cad871
SG
571 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
572 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 573 struct netdev_hw_addr *ha;
d0cad871 574
1e1d7412 575 netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
d0cad871
SG
576
577 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
578
22bedad3
JP
579 netdev_for_each_mc_addr(ha, netdev) {
580 u32 bitnum = smsc75xx_hash(ha->addr);
d0cad871
SG
581 pdata->multicast_hash_table[bitnum / 32] |=
582 (1 << (bitnum % 32));
583 }
584 } else {
1e1d7412 585 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
d0cad871
SG
586 pdata->rfe_ctl |= RFE_CTL_DPF;
587 }
588
589 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
590
591 /* defer register writes to a sleepable context */
592 schedule_work(&pdata->set_multicast);
593}
594
595static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
596 u16 lcladv, u16 rmtadv)
597{
598 u32 flow = 0, fct_flow = 0;
599 int ret;
600
601 if (duplex == DUPLEX_FULL) {
602 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
603
604 if (cap & FLOW_CTRL_TX) {
605 flow = (FLOW_TX_FCEN | 0xFFFF);
606 /* set fct_flow thresholds to 20% and 80% */
607 fct_flow = (8 << 8) | 32;
608 }
609
610 if (cap & FLOW_CTRL_RX)
611 flow |= FLOW_RX_FCEN;
612
1e1d7412
JP
613 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
614 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
615 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
d0cad871 616 } else {
1e1d7412 617 netif_dbg(dev, link, dev->net, "half duplex\n");
d0cad871
SG
618 }
619
620 ret = smsc75xx_write_reg(dev, FLOW, flow);
e3c678e6
SG
621 if (ret < 0) {
622 netdev_warn(dev->net, "Error writing FLOW\n");
623 return ret;
624 }
d0cad871
SG
625
626 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
e3c678e6
SG
627 if (ret < 0) {
628 netdev_warn(dev->net, "Error writing FCT_FLOW\n");
629 return ret;
630 }
d0cad871
SG
631
632 return 0;
633}
634
635static int smsc75xx_link_reset(struct usbnet *dev)
636{
637 struct mii_if_info *mii = &dev->mii;
8ae6daca 638 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
d0cad871
SG
639 u16 lcladv, rmtadv;
640 int ret;
641
4f94a929 642 /* write to clear phy interrupt status */
7749622d
SG
643 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
644 PHY_INT_SRC_CLEAR_ALL);
d0cad871
SG
645
646 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
647 if (ret < 0) {
648 netdev_warn(dev->net, "Error writing INT_STS\n");
649 return ret;
650 }
d0cad871
SG
651
652 mii_check_media(mii, 1, 1);
653 mii_ethtool_gset(&dev->mii, &ecmd);
654 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
655 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
656
1e1d7412
JP
657 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
658 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
d0cad871
SG
659
660 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
661}
662
663static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
664{
665 u32 intdata;
666
667 if (urb->actual_length != 4) {
1e1d7412
JP
668 netdev_warn(dev->net, "unexpected urb length %d\n",
669 urb->actual_length);
d0cad871
SG
670 return;
671 }
672
673 memcpy(&intdata, urb->transfer_buffer, 4);
674 le32_to_cpus(&intdata);
675
1e1d7412 676 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
d0cad871
SG
677
678 if (intdata & INT_ENP_PHY_INT)
679 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
680 else
1e1d7412
JP
681 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
682 intdata);
d0cad871
SG
683}
684
d0cad871
SG
685static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
686{
687 return MAX_EEPROM_SIZE;
688}
689
690static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
691 struct ethtool_eeprom *ee, u8 *data)
692{
693 struct usbnet *dev = netdev_priv(netdev);
694
695 ee->magic = LAN75XX_EEPROM_MAGIC;
696
697 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
698}
699
700static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
701 struct ethtool_eeprom *ee, u8 *data)
702{
703 struct usbnet *dev = netdev_priv(netdev);
704
705 if (ee->magic != LAN75XX_EEPROM_MAGIC) {
1e1d7412
JP
706 netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
707 ee->magic);
d0cad871
SG
708 return -EINVAL;
709 }
710
711 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
712}
713
6c636503
SG
714static void smsc75xx_ethtool_get_wol(struct net_device *net,
715 struct ethtool_wolinfo *wolinfo)
716{
717 struct usbnet *dev = netdev_priv(net);
718 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
719
720 wolinfo->supported = SUPPORTED_WAKE;
721 wolinfo->wolopts = pdata->wolopts;
722}
723
724static int smsc75xx_ethtool_set_wol(struct net_device *net,
725 struct ethtool_wolinfo *wolinfo)
726{
727 struct usbnet *dev = netdev_priv(net);
728 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
351f33d9 729 int ret;
6c636503
SG
730
731 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
351f33d9
SG
732
733 ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
e3c678e6
SG
734 if (ret < 0)
735 netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
351f33d9 736
e3c678e6 737 return ret;
6c636503
SG
738}
739
d0cad871
SG
740static const struct ethtool_ops smsc75xx_ethtool_ops = {
741 .get_link = usbnet_get_link,
742 .nway_reset = usbnet_nway_reset,
743 .get_drvinfo = usbnet_get_drvinfo,
744 .get_msglevel = usbnet_get_msglevel,
745 .set_msglevel = usbnet_set_msglevel,
746 .get_settings = usbnet_get_settings,
747 .set_settings = usbnet_set_settings,
748 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
749 .get_eeprom = smsc75xx_ethtool_get_eeprom,
750 .set_eeprom = smsc75xx_ethtool_set_eeprom,
6c636503
SG
751 .get_wol = smsc75xx_ethtool_get_wol,
752 .set_wol = smsc75xx_ethtool_set_wol,
d0cad871
SG
753};
754
755static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
756{
757 struct usbnet *dev = netdev_priv(netdev);
758
759 if (!netif_running(netdev))
760 return -EINVAL;
761
762 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
763}
764
765static void smsc75xx_init_mac_address(struct usbnet *dev)
766{
c489565b
AB
767 const u8 *mac_addr;
768
769 /* maybe the boot loader passed the MAC address in devicetree */
770 mac_addr = of_get_mac_address(dev->udev->dev.of_node);
771 if (mac_addr) {
772 memcpy(dev->net->dev_addr, mac_addr, ETH_ALEN);
773 return;
774 }
775
d0cad871
SG
776 /* try reading mac address from EEPROM */
777 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
778 dev->net->dev_addr) == 0) {
779 if (is_valid_ether_addr(dev->net->dev_addr)) {
780 /* eeprom values are valid so use them */
781 netif_dbg(dev, ifup, dev->net,
1e1d7412 782 "MAC address read from EEPROM\n");
d0cad871
SG
783 return;
784 }
785 }
786
c489565b 787 /* no useful static MAC address found. generate a random one */
f2cedb63 788 eth_hw_addr_random(dev->net);
1e1d7412 789 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
d0cad871
SG
790}
791
792static int smsc75xx_set_mac_address(struct usbnet *dev)
793{
794 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
795 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
796 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
797
798 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
e3c678e6
SG
799 if (ret < 0) {
800 netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
801 return ret;
802 }
d0cad871
SG
803
804 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
e3c678e6
SG
805 if (ret < 0) {
806 netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
807 return ret;
808 }
d0cad871
SG
809
810 addr_hi |= ADDR_FILTX_FB_VALID;
811 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
e3c678e6
SG
812 if (ret < 0) {
813 netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
814 return ret;
815 }
d0cad871
SG
816
817 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
e3c678e6
SG
818 if (ret < 0)
819 netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
d0cad871 820
e3c678e6 821 return ret;
d0cad871
SG
822}
823
824static int smsc75xx_phy_initialize(struct usbnet *dev)
825{
b140504a 826 int bmcr, ret, timeout = 0;
d0cad871
SG
827
828 /* Initialize MII structure */
829 dev->mii.dev = dev->net;
830 dev->mii.mdio_read = smsc75xx_mdio_read;
831 dev->mii.mdio_write = smsc75xx_mdio_write;
832 dev->mii.phy_id_mask = 0x1f;
833 dev->mii.reg_num_mask = 0x1f;
c0b92e4d 834 dev->mii.supports_gmii = 1;
d0cad871
SG
835 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
836
837 /* reset phy and wait for reset to complete */
838 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
839
840 do {
841 msleep(10);
842 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
e3c678e6
SG
843 if (bmcr < 0) {
844 netdev_warn(dev->net, "Error reading MII_BMCR\n");
845 return bmcr;
846 }
d0cad871 847 timeout++;
8a1d59d7 848 } while ((bmcr & BMCR_RESET) && (timeout < 100));
d0cad871
SG
849
850 if (timeout >= 100) {
1e1d7412 851 netdev_warn(dev->net, "timeout on PHY Reset\n");
d0cad871
SG
852 return -EIO;
853 }
854
855 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
856 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
857 ADVERTISE_PAUSE_ASYM);
c0b92e4d
SG
858 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
859 ADVERTISE_1000FULL);
d0cad871 860
b140504a
SG
861 /* read and write to clear phy interrupt status */
862 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
e3c678e6
SG
863 if (ret < 0) {
864 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
865 return ret;
866 }
867
b140504a 868 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
d0cad871
SG
869
870 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
871 PHY_INT_MASK_DEFAULT);
872 mii_nway_restart(&dev->mii);
873
1e1d7412 874 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
d0cad871
SG
875 return 0;
876}
877
878static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
879{
880 int ret = 0;
881 u32 buf;
882 bool rxenabled;
883
884 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
885 if (ret < 0) {
886 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
887 return ret;
888 }
d0cad871
SG
889
890 rxenabled = ((buf & MAC_RX_RXEN) != 0);
891
892 if (rxenabled) {
893 buf &= ~MAC_RX_RXEN;
894 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
895 if (ret < 0) {
896 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
897 return ret;
898 }
d0cad871
SG
899 }
900
901 /* add 4 to size for FCS */
902 buf &= ~MAC_RX_MAX_SIZE;
903 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
904
905 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
906 if (ret < 0) {
907 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
908 return ret;
909 }
d0cad871
SG
910
911 if (rxenabled) {
912 buf |= MAC_RX_RXEN;
913 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
914 if (ret < 0) {
915 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
916 return ret;
917 }
d0cad871
SG
918 }
919
920 return 0;
921}
922
923static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
924{
925 struct usbnet *dev = netdev_priv(netdev);
4c51e536
SG
926 int ret;
927
928 if (new_mtu > MAX_SINGLE_PACKET_SIZE)
929 return -EINVAL;
d0cad871 930
4c51e536 931 ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
e3c678e6
SG
932 if (ret < 0) {
933 netdev_warn(dev->net, "Failed to set mac rx frame length\n");
934 return ret;
935 }
d0cad871
SG
936
937 return usbnet_change_mtu(netdev, new_mtu);
938}
939
78e47fe4 940/* Enable or disable Rx checksum offload engine */
c8f44aff
MM
941static int smsc75xx_set_features(struct net_device *netdev,
942 netdev_features_t features)
78e47fe4
MM
943{
944 struct usbnet *dev = netdev_priv(netdev);
945 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
946 unsigned long flags;
947 int ret;
948
949 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
950
951 if (features & NETIF_F_RXCSUM)
952 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
953 else
954 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
955
956 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
957 /* it's racing here! */
958
959 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
960 if (ret < 0)
961 netdev_warn(dev->net, "Error writing RFE_CTL\n");
78e47fe4 962
e3c678e6 963 return ret;
78e47fe4
MM
964}
965
47bbea41 966static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
8762cec8
SG
967{
968 int timeout = 0;
969
970 do {
971 u32 buf;
47bbea41
ML
972 int ret;
973
974 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
975
e3c678e6
SG
976 if (ret < 0) {
977 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
978 return ret;
979 }
8762cec8
SG
980
981 if (buf & PMT_CTL_DEV_RDY)
982 return 0;
983
984 msleep(10);
985 timeout++;
986 } while (timeout < 100);
987
1e1d7412 988 netdev_warn(dev->net, "timeout waiting for device ready\n");
8762cec8
SG
989 return -EIO;
990}
991
d0cad871
SG
992static int smsc75xx_reset(struct usbnet *dev)
993{
994 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
995 u32 buf;
996 int ret = 0, timeout;
997
1e1d7412 998 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
d0cad871 999
47bbea41 1000 ret = smsc75xx_wait_ready(dev, 0);
e3c678e6
SG
1001 if (ret < 0) {
1002 netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
1003 return ret;
1004 }
8762cec8 1005
d0cad871 1006 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1007 if (ret < 0) {
1008 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1009 return ret;
1010 }
d0cad871
SG
1011
1012 buf |= HW_CFG_LRST;
1013
1014 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1015 if (ret < 0) {
1016 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1017 return ret;
1018 }
d0cad871
SG
1019
1020 timeout = 0;
1021 do {
1022 msleep(10);
1023 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1024 if (ret < 0) {
1025 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1026 return ret;
1027 }
d0cad871
SG
1028 timeout++;
1029 } while ((buf & HW_CFG_LRST) && (timeout < 100));
1030
1031 if (timeout >= 100) {
1e1d7412 1032 netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
d0cad871
SG
1033 return -EIO;
1034 }
1035
1e1d7412 1036 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
d0cad871
SG
1037
1038 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1039 if (ret < 0) {
1040 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1041 return ret;
1042 }
d0cad871
SG
1043
1044 buf |= PMT_CTL_PHY_RST;
1045
1046 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
e3c678e6
SG
1047 if (ret < 0) {
1048 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1049 return ret;
1050 }
d0cad871
SG
1051
1052 timeout = 0;
1053 do {
1054 msleep(10);
1055 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1056 if (ret < 0) {
1057 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1058 return ret;
1059 }
d0cad871
SG
1060 timeout++;
1061 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
1062
1063 if (timeout >= 100) {
1e1d7412 1064 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
d0cad871
SG
1065 return -EIO;
1066 }
1067
1e1d7412 1068 netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
d0cad871 1069
d0cad871 1070 ret = smsc75xx_set_mac_address(dev);
e3c678e6
SG
1071 if (ret < 0) {
1072 netdev_warn(dev->net, "Failed to set mac address\n");
1073 return ret;
1074 }
d0cad871 1075
1e1d7412
JP
1076 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
1077 dev->net->dev_addr);
d0cad871
SG
1078
1079 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1080 if (ret < 0) {
1081 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1082 return ret;
1083 }
d0cad871 1084
1e1d7412
JP
1085 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
1086 buf);
d0cad871
SG
1087
1088 buf |= HW_CFG_BIR;
1089
1090 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1091 if (ret < 0) {
1092 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1093 return ret;
1094 }
d0cad871
SG
1095
1096 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1097 if (ret < 0) {
1098 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1099 return ret;
1100 }
d0cad871 1101
1e1d7412
JP
1102 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
1103 buf);
d0cad871
SG
1104
1105 if (!turbo_mode) {
1106 buf = 0;
1107 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
1108 } else if (dev->udev->speed == USB_SPEED_HIGH) {
1109 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
1110 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
1111 } else {
1112 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
1113 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
1114 }
1115
1e1d7412
JP
1116 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
1117 (ulong)dev->rx_urb_size);
d0cad871
SG
1118
1119 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
e3c678e6
SG
1120 if (ret < 0) {
1121 netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
1122 return ret;
1123 }
d0cad871
SG
1124
1125 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
e3c678e6
SG
1126 if (ret < 0) {
1127 netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
1128 return ret;
1129 }
d0cad871
SG
1130
1131 netif_dbg(dev, ifup, dev->net,
1e1d7412 1132 "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
d0cad871
SG
1133
1134 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
e3c678e6
SG
1135 if (ret < 0) {
1136 netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
1137 return ret;
1138 }
d0cad871
SG
1139
1140 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
e3c678e6
SG
1141 if (ret < 0) {
1142 netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
1143 return ret;
1144 }
d0cad871
SG
1145
1146 netif_dbg(dev, ifup, dev->net,
1e1d7412 1147 "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
d0cad871
SG
1148
1149 if (turbo_mode) {
1150 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1151 if (ret < 0) {
1152 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1153 return ret;
1154 }
d0cad871 1155
1e1d7412 1156 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1157
1158 buf |= (HW_CFG_MEF | HW_CFG_BCE);
1159
1160 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1161 if (ret < 0) {
1162 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1163 return ret;
1164 }
d0cad871
SG
1165
1166 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1167 if (ret < 0) {
1168 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1169 return ret;
1170 }
d0cad871 1171
1e1d7412 1172 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1173 }
1174
1175 /* set FIFO sizes */
1176 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
1177 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
e3c678e6
SG
1178 if (ret < 0) {
1179 netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
1180 return ret;
1181 }
d0cad871 1182
1e1d7412 1183 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1184
1185 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
1186 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
e3c678e6
SG
1187 if (ret < 0) {
1188 netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
1189 return ret;
1190 }
d0cad871 1191
1e1d7412 1192 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1193
1194 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
1195 if (ret < 0) {
1196 netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
1197 return ret;
1198 }
d0cad871
SG
1199
1200 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
e3c678e6
SG
1201 if (ret < 0) {
1202 netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
1203 return ret;
1204 }
d0cad871 1205
1e1d7412 1206 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
d0cad871 1207
97138a1c 1208 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
e3c678e6
SG
1209 if (ret < 0) {
1210 netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
1211 return ret;
1212 }
d0cad871 1213
97138a1c
SG
1214 /* only set default GPIO/LED settings if no EEPROM is detected */
1215 if (!(buf & E2P_CMD_LOADED)) {
1216 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
e3c678e6
SG
1217 if (ret < 0) {
1218 netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
1219 return ret;
1220 }
d0cad871 1221
97138a1c
SG
1222 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
1223 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
1224
1225 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
e3c678e6
SG
1226 if (ret < 0) {
1227 netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
1228 return ret;
1229 }
97138a1c 1230 }
d0cad871
SG
1231
1232 ret = smsc75xx_write_reg(dev, FLOW, 0);
e3c678e6
SG
1233 if (ret < 0) {
1234 netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
1235 return ret;
1236 }
d0cad871
SG
1237
1238 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
e3c678e6
SG
1239 if (ret < 0) {
1240 netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
1241 return ret;
1242 }
d0cad871
SG
1243
1244 /* Don't need rfe_ctl_lock during initialisation */
1245 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1246 if (ret < 0) {
1247 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1248 return ret;
1249 }
d0cad871
SG
1250
1251 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
1252
1253 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
1254 if (ret < 0) {
1255 netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
1256 return ret;
1257 }
d0cad871
SG
1258
1259 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1260 if (ret < 0) {
1261 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1262 return ret;
1263 }
d0cad871 1264
1e1d7412
JP
1265 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
1266 pdata->rfe_ctl);
d0cad871
SG
1267
1268 /* Enable or disable checksum offload engines */
78e47fe4 1269 smsc75xx_set_features(dev->net, dev->net->features);
d0cad871
SG
1270
1271 smsc75xx_set_multicast(dev->net);
1272
1273 ret = smsc75xx_phy_initialize(dev);
e3c678e6
SG
1274 if (ret < 0) {
1275 netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
1276 return ret;
1277 }
d0cad871
SG
1278
1279 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
e3c678e6
SG
1280 if (ret < 0) {
1281 netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
1282 return ret;
1283 }
d0cad871
SG
1284
1285 /* enable PHY interrupts */
1286 buf |= INT_ENP_PHY_INT;
1287
1288 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
e3c678e6
SG
1289 if (ret < 0) {
1290 netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
1291 return ret;
1292 }
d0cad871 1293
2f3a081e
SG
1294 /* allow mac to detect speed and duplex from phy */
1295 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
e3c678e6
SG
1296 if (ret < 0) {
1297 netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
1298 return ret;
1299 }
2f3a081e
SG
1300
1301 buf |= (MAC_CR_ADD | MAC_CR_ASD);
1302 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
e3c678e6
SG
1303 if (ret < 0) {
1304 netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
1305 return ret;
1306 }
2f3a081e 1307
d0cad871 1308 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
e3c678e6
SG
1309 if (ret < 0) {
1310 netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
1311 return ret;
1312 }
d0cad871
SG
1313
1314 buf |= MAC_TX_TXEN;
1315
1316 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
e3c678e6
SG
1317 if (ret < 0) {
1318 netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
1319 return ret;
1320 }
d0cad871 1321
1e1d7412 1322 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
d0cad871
SG
1323
1324 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
e3c678e6
SG
1325 if (ret < 0) {
1326 netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
1327 return ret;
1328 }
d0cad871
SG
1329
1330 buf |= FCT_TX_CTL_EN;
1331
1332 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
e3c678e6
SG
1333 if (ret < 0) {
1334 netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
1335 return ret;
1336 }
d0cad871 1337
1e1d7412 1338 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
d0cad871 1339
4c51e536 1340 ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
e3c678e6
SG
1341 if (ret < 0) {
1342 netdev_warn(dev->net, "Failed to set max rx frame length\n");
1343 return ret;
1344 }
d0cad871
SG
1345
1346 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
1347 if (ret < 0) {
1348 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
1349 return ret;
1350 }
d0cad871
SG
1351
1352 buf |= MAC_RX_RXEN;
1353
1354 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
1355 if (ret < 0) {
1356 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
1357 return ret;
1358 }
d0cad871 1359
1e1d7412 1360 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
d0cad871
SG
1361
1362 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
e3c678e6
SG
1363 if (ret < 0) {
1364 netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
1365 return ret;
1366 }
d0cad871
SG
1367
1368 buf |= FCT_RX_CTL_EN;
1369
1370 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
e3c678e6
SG
1371 if (ret < 0) {
1372 netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
1373 return ret;
1374 }
d0cad871 1375
1e1d7412 1376 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
d0cad871 1377
1e1d7412 1378 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
d0cad871
SG
1379 return 0;
1380}
1381
1382static const struct net_device_ops smsc75xx_netdev_ops = {
1383 .ndo_open = usbnet_open,
1384 .ndo_stop = usbnet_stop,
1385 .ndo_start_xmit = usbnet_start_xmit,
1386 .ndo_tx_timeout = usbnet_tx_timeout,
1387 .ndo_change_mtu = smsc75xx_change_mtu,
1388 .ndo_set_mac_address = eth_mac_addr,
1389 .ndo_validate_addr = eth_validate_addr,
1390 .ndo_do_ioctl = smsc75xx_ioctl,
afc4b13d 1391 .ndo_set_rx_mode = smsc75xx_set_multicast,
78e47fe4 1392 .ndo_set_features = smsc75xx_set_features,
d0cad871
SG
1393};
1394
1395static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
1396{
1397 struct smsc75xx_priv *pdata = NULL;
1398 int ret;
1399
1400 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1401
1402 ret = usbnet_get_endpoints(dev, intf);
e3c678e6
SG
1403 if (ret < 0) {
1404 netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
1405 return ret;
1406 }
d0cad871
SG
1407
1408 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
38673c82 1409 GFP_KERNEL);
d0cad871
SG
1410
1411 pdata = (struct smsc75xx_priv *)(dev->data[0]);
38673c82 1412 if (!pdata)
d0cad871 1413 return -ENOMEM;
d0cad871
SG
1414
1415 pdata->dev = dev;
1416
1417 spin_lock_init(&pdata->rfe_ctl_lock);
1418 mutex_init(&pdata->dataport_mutex);
1419
1420 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
1421
20f01703 1422 if (DEFAULT_TX_CSUM_ENABLE)
78e47fe4 1423 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
20f01703 1424
78e47fe4
MM
1425 if (DEFAULT_RX_CSUM_ENABLE)
1426 dev->net->features |= NETIF_F_RXCSUM;
d0cad871 1427
78e47fe4 1428 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
20f01703 1429 NETIF_F_RXCSUM;
d0cad871 1430
481705a1
SG
1431 ret = smsc75xx_wait_ready(dev, 0);
1432 if (ret < 0) {
1433 netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
1434 return ret;
1435 }
1436
1437 smsc75xx_init_mac_address(dev);
1438
d0cad871
SG
1439 /* Init all registers */
1440 ret = smsc75xx_reset(dev);
e3c678e6
SG
1441 if (ret < 0) {
1442 netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
1443 return ret;
1444 }
d0cad871
SG
1445
1446 dev->net->netdev_ops = &smsc75xx_netdev_ops;
1447 dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
1448 dev->net->flags |= IFF_MULTICAST;
1449 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
a99ff7d0 1450 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
d0cad871
SG
1451 return 0;
1452}
1453
1454static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1455{
1456 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1457 if (pdata) {
1e1d7412 1458 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
d0cad871
SG
1459 kfree(pdata);
1460 pdata = NULL;
1461 dev->data[0] = 0;
1462 }
1463}
1464
899a391b
SG
1465static u16 smsc_crc(const u8 *buffer, size_t len)
1466{
1467 return bitrev16(crc16(0xFFFF, buffer, len));
1468}
1469
1470static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
1471 u32 wuf_mask1)
1472{
1473 int cfg_base = WUF_CFGX + filter * 4;
1474 int mask_base = WUF_MASKX + filter * 16;
1475 int ret;
1476
1477 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
e3c678e6
SG
1478 if (ret < 0) {
1479 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1480 return ret;
1481 }
899a391b
SG
1482
1483 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
e3c678e6
SG
1484 if (ret < 0) {
1485 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1486 return ret;
1487 }
899a391b
SG
1488
1489 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
e3c678e6
SG
1490 if (ret < 0) {
1491 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1492 return ret;
1493 }
899a391b
SG
1494
1495 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
e3c678e6
SG
1496 if (ret < 0) {
1497 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1498 return ret;
1499 }
899a391b
SG
1500
1501 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
e3c678e6
SG
1502 if (ret < 0) {
1503 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1504 return ret;
1505 }
899a391b
SG
1506
1507 return 0;
1508}
1509
9deb2757
SG
1510static int smsc75xx_enter_suspend0(struct usbnet *dev)
1511{
b4cdea9c 1512 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1513 u32 val;
1514 int ret;
1515
1516 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1517 if (ret < 0) {
1518 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1519 return ret;
1520 }
9deb2757
SG
1521
1522 val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
1523 val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
1524
1525 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1526 if (ret < 0) {
1527 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1528 return ret;
1529 }
9deb2757 1530
351f33d9 1531 pdata->suspend_flags |= SUSPEND_SUSPEND0;
b4cdea9c 1532
9deb2757
SG
1533 return 0;
1534}
1535
f329ccdc
SG
1536static int smsc75xx_enter_suspend1(struct usbnet *dev)
1537{
b4cdea9c 1538 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc
SG
1539 u32 val;
1540 int ret;
1541
1542 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1543 if (ret < 0) {
1544 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1545 return ret;
1546 }
f329ccdc
SG
1547
1548 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1549 val |= PMT_CTL_SUS_MODE_1;
1550
1551 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1552 if (ret < 0) {
1553 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1554 return ret;
1555 }
f329ccdc
SG
1556
1557 /* clear wol status, enable energy detection */
1558 val &= ~PMT_CTL_WUPS;
1559 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1560
1561 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1562 if (ret < 0) {
1563 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1564 return ret;
1565 }
f329ccdc 1566
351f33d9 1567 pdata->suspend_flags |= SUSPEND_SUSPEND1;
b4cdea9c 1568
f329ccdc
SG
1569 return 0;
1570}
1571
9deb2757
SG
1572static int smsc75xx_enter_suspend2(struct usbnet *dev)
1573{
b4cdea9c 1574 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1575 u32 val;
1576 int ret;
1577
1578 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1579 if (ret < 0) {
1580 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1581 return ret;
1582 }
9deb2757
SG
1583
1584 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1585 val |= PMT_CTL_SUS_MODE_2;
1586
1587 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1588 if (ret < 0) {
1589 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1590 return ret;
1591 }
9deb2757 1592
b4cdea9c
SG
1593 pdata->suspend_flags |= SUSPEND_SUSPEND2;
1594
1595 return 0;
1596}
1597
1598static int smsc75xx_enter_suspend3(struct usbnet *dev)
1599{
1600 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1601 u32 val;
1602 int ret;
1603
1604 ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
e3c678e6
SG
1605 if (ret < 0) {
1606 netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
1607 return ret;
1608 }
b4cdea9c
SG
1609
1610 if (val & FCT_RX_CTL_RXUSED) {
1611 netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
1612 return -EBUSY;
1613 }
1614
1615 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1616 if (ret < 0) {
1617 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1618 return ret;
1619 }
b4cdea9c
SG
1620
1621 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1622 val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
1623
1624 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1625 if (ret < 0) {
1626 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1627 return ret;
1628 }
b4cdea9c
SG
1629
1630 /* clear wol status */
1631 val &= ~PMT_CTL_WUPS;
1632 val |= PMT_CTL_WUPS_WOL;
1633
1634 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1635 if (ret < 0) {
1636 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1637 return ret;
1638 }
b4cdea9c 1639
351f33d9 1640 pdata->suspend_flags |= SUSPEND_SUSPEND3;
b4cdea9c 1641
9deb2757
SG
1642 return 0;
1643}
1644
f329ccdc
SG
1645static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
1646{
1647 struct mii_if_info *mii = &dev->mii;
1648 int ret;
1649
1650 netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
1651
1652 /* read to clear */
1653 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
e3c678e6
SG
1654 if (ret < 0) {
1655 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
1656 return ret;
1657 }
f329ccdc
SG
1658
1659 /* enable interrupt source */
1660 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
e3c678e6
SG
1661 if (ret < 0) {
1662 netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
1663 return ret;
1664 }
f329ccdc
SG
1665
1666 ret |= mask;
1667
1668 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1669
1670 return 0;
1671}
1672
1673static int smsc75xx_link_ok_nopm(struct usbnet *dev)
1674{
1675 struct mii_if_info *mii = &dev->mii;
1676 int ret;
1677
1678 /* first, a dummy read, needed to latch some MII phys */
1679 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1680 if (ret < 0) {
1681 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1682 return ret;
1683 }
f329ccdc
SG
1684
1685 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1686 if (ret < 0) {
1687 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1688 return ret;
1689 }
f329ccdc
SG
1690
1691 return !!(ret & BMSR_LSTATUS);
1692}
1693
b4cdea9c
SG
1694static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
1695{
1696 int ret;
1697
1698 if (!netif_running(dev->net)) {
1699 /* interface is ifconfig down so fully power down hw */
1700 netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
1701 return smsc75xx_enter_suspend2(dev);
1702 }
1703
1704 if (!link_up) {
1705 /* link is down so enter EDPD mode */
1706 netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
1707
1708 /* enable PHY wakeup events for if cable is attached */
1709 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1710 PHY_INT_MASK_ANEG_COMP);
e3c678e6
SG
1711 if (ret < 0) {
1712 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1713 return ret;
1714 }
b4cdea9c
SG
1715
1716 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1717 return smsc75xx_enter_suspend1(dev);
1718 }
1719
1720 /* enable PHY wakeup events so we remote wakeup if cable is pulled */
1721 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1722 PHY_INT_MASK_LINK_DOWN);
e3c678e6
SG
1723 if (ret < 0) {
1724 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1725 return ret;
1726 }
b4cdea9c
SG
1727
1728 netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
1729 return smsc75xx_enter_suspend3(dev);
1730}
1731
16c79a04
SG
1732static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
1733{
1734 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1735 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc 1736 u32 val, link_up;
16c79a04 1737 int ret;
16c79a04 1738
16c79a04 1739 ret = usbnet_suspend(intf, message);
e3c678e6
SG
1740 if (ret < 0) {
1741 netdev_warn(dev->net, "usbnet_suspend error\n");
1742 return ret;
1743 }
16c79a04 1744
b4cdea9c
SG
1745 if (pdata->suspend_flags) {
1746 netdev_warn(dev->net, "error during last resume\n");
1747 pdata->suspend_flags = 0;
1748 }
1749
f329ccdc
SG
1750 /* determine if link is up using only _nopm functions */
1751 link_up = smsc75xx_link_ok_nopm(dev);
1752
b4cdea9c
SG
1753 if (message.event == PM_EVENT_AUTO_SUSPEND) {
1754 ret = smsc75xx_autosuspend(dev, link_up);
1755 goto done;
1756 }
1757
1758 /* if we get this far we're not autosuspending */
f329ccdc
SG
1759 /* if no wol options set, or if link is down and we're not waking on
1760 * PHY activity, enter lowest power SUSPEND2 mode
1761 */
1762 if (!(pdata->wolopts & SUPPORTED_WAKE) ||
1763 !(link_up || (pdata->wolopts & WAKE_PHY))) {
1e1d7412 1764 netdev_info(dev->net, "entering SUSPEND2 mode\n");
6c636503
SG
1765
1766 /* disable energy detect (link up) & wake up events */
47bbea41 1767 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1768 if (ret < 0) {
1769 netdev_warn(dev->net, "Error reading WUCSR\n");
1770 goto done;
1771 }
6c636503
SG
1772
1773 val &= ~(WUCSR_MPEN | WUCSR_WUEN);
1774
47bbea41 1775 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1776 if (ret < 0) {
1777 netdev_warn(dev->net, "Error writing WUCSR\n");
1778 goto done;
1779 }
6c636503 1780
47bbea41 1781 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1782 if (ret < 0) {
1783 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1784 goto done;
1785 }
6c636503
SG
1786
1787 val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
1788
47bbea41 1789 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1790 if (ret < 0) {
1791 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1792 goto done;
1793 }
6c636503 1794
eacdd6c2
SG
1795 ret = smsc75xx_enter_suspend2(dev);
1796 goto done;
6c636503
SG
1797 }
1798
f329ccdc
SG
1799 if (pdata->wolopts & WAKE_PHY) {
1800 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1801 (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
e3c678e6
SG
1802 if (ret < 0) {
1803 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1804 goto done;
1805 }
f329ccdc
SG
1806
1807 /* if link is down then configure EDPD and enter SUSPEND1,
1808 * otherwise enter SUSPEND0 below
1809 */
1810 if (!link_up) {
1811 struct mii_if_info *mii = &dev->mii;
1812 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1813
1814 /* enable energy detect power-down mode */
1815 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1816 PHY_MODE_CTRL_STS);
e3c678e6
SG
1817 if (ret < 0) {
1818 netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
1819 goto done;
1820 }
f329ccdc
SG
1821
1822 ret |= MODE_CTRL_STS_EDPWRDOWN;
1823
1824 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
1825 PHY_MODE_CTRL_STS, ret);
1826
1827 /* enter SUSPEND1 mode */
eacdd6c2
SG
1828 ret = smsc75xx_enter_suspend1(dev);
1829 goto done;
f329ccdc
SG
1830 }
1831 }
1832
899a391b
SG
1833 if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
1834 int i, filter = 0;
1835
1836 /* disable all filters */
1837 for (i = 0; i < WUF_NUM; i++) {
47bbea41 1838 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
e3c678e6
SG
1839 if (ret < 0) {
1840 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1841 goto done;
1842 }
899a391b
SG
1843 }
1844
1845 if (pdata->wolopts & WAKE_MCAST) {
1846 const u8 mcast[] = {0x01, 0x00, 0x5E};
1e1d7412 1847 netdev_info(dev->net, "enabling multicast detection\n");
899a391b
SG
1848
1849 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
1850 | smsc_crc(mcast, 3);
1851 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
e3c678e6
SG
1852 if (ret < 0) {
1853 netdev_warn(dev->net, "Error writing wakeup filter\n");
1854 goto done;
1855 }
899a391b
SG
1856 }
1857
1858 if (pdata->wolopts & WAKE_ARP) {
1859 const u8 arp[] = {0x08, 0x06};
1e1d7412 1860 netdev_info(dev->net, "enabling ARP detection\n");
899a391b
SG
1861
1862 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
1863 | smsc_crc(arp, 2);
1864 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
e3c678e6
SG
1865 if (ret < 0) {
1866 netdev_warn(dev->net, "Error writing wakeup filter\n");
1867 goto done;
1868 }
899a391b
SG
1869 }
1870
1871 /* clear any pending pattern match packet status */
47bbea41 1872 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1873 if (ret < 0) {
1874 netdev_warn(dev->net, "Error reading WUCSR\n");
1875 goto done;
1876 }
899a391b
SG
1877
1878 val |= WUCSR_WUFR;
1879
47bbea41 1880 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1881 if (ret < 0) {
1882 netdev_warn(dev->net, "Error writing WUCSR\n");
1883 goto done;
1884 }
899a391b 1885
1e1d7412 1886 netdev_info(dev->net, "enabling packet match detection\n");
47bbea41 1887 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1888 if (ret < 0) {
1889 netdev_warn(dev->net, "Error reading WUCSR\n");
1890 goto done;
1891 }
899a391b
SG
1892
1893 val |= WUCSR_WUEN;
1894
47bbea41 1895 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1896 if (ret < 0) {
1897 netdev_warn(dev->net, "Error writing WUCSR\n");
1898 goto done;
1899 }
899a391b 1900 } else {
1e1d7412 1901 netdev_info(dev->net, "disabling packet match detection\n");
47bbea41 1902 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1903 if (ret < 0) {
1904 netdev_warn(dev->net, "Error reading WUCSR\n");
1905 goto done;
1906 }
6c636503 1907
899a391b 1908 val &= ~WUCSR_WUEN;
16c79a04 1909
47bbea41 1910 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1911 if (ret < 0) {
1912 netdev_warn(dev->net, "Error writing WUCSR\n");
1913 goto done;
1914 }
6c636503
SG
1915 }
1916
899a391b 1917 /* disable magic, bcast & unicast wakeup sources */
47bbea41 1918 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1919 if (ret < 0) {
1920 netdev_warn(dev->net, "Error reading WUCSR\n");
1921 goto done;
1922 }
6c636503 1923
899a391b
SG
1924 val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
1925
47bbea41 1926 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1927 if (ret < 0) {
1928 netdev_warn(dev->net, "Error writing WUCSR\n");
1929 goto done;
1930 }
899a391b 1931
f329ccdc
SG
1932 if (pdata->wolopts & WAKE_PHY) {
1933 netdev_info(dev->net, "enabling PHY wakeup\n");
1934
1935 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1936 if (ret < 0) {
1937 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1938 goto done;
1939 }
f329ccdc
SG
1940
1941 /* clear wol status, enable energy detection */
1942 val &= ~PMT_CTL_WUPS;
1943 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1944
1945 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1946 if (ret < 0) {
1947 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1948 goto done;
1949 }
f329ccdc
SG
1950 }
1951
6c636503 1952 if (pdata->wolopts & WAKE_MAGIC) {
1e1d7412 1953 netdev_info(dev->net, "enabling magic packet wakeup\n");
47bbea41 1954 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1955 if (ret < 0) {
1956 netdev_warn(dev->net, "Error reading WUCSR\n");
1957 goto done;
1958 }
899a391b
SG
1959
1960 /* clear any pending magic packet status */
1961 val |= WUCSR_MPR | WUCSR_MPEN;
1962
47bbea41 1963 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1964 if (ret < 0) {
1965 netdev_warn(dev->net, "Error writing WUCSR\n");
1966 goto done;
1967 }
6c636503
SG
1968 }
1969
899a391b 1970 if (pdata->wolopts & WAKE_BCAST) {
1e1d7412 1971 netdev_info(dev->net, "enabling broadcast detection\n");
47bbea41 1972 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1973 if (ret < 0) {
1974 netdev_warn(dev->net, "Error reading WUCSR\n");
1975 goto done;
1976 }
6c636503 1977
899a391b 1978 val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
16c79a04 1979
47bbea41 1980 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1981 if (ret < 0) {
1982 netdev_warn(dev->net, "Error writing WUCSR\n");
1983 goto done;
1984 }
899a391b 1985 }
6c636503 1986
899a391b 1987 if (pdata->wolopts & WAKE_UCAST) {
1e1d7412 1988 netdev_info(dev->net, "enabling unicast detection\n");
47bbea41 1989 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1990 if (ret < 0) {
1991 netdev_warn(dev->net, "Error reading WUCSR\n");
1992 goto done;
1993 }
899a391b
SG
1994
1995 val |= WUCSR_WUFR | WUCSR_PFDA_EN;
6c636503 1996
47bbea41 1997 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1998 if (ret < 0) {
1999 netdev_warn(dev->net, "Error writing WUCSR\n");
2000 goto done;
2001 }
899a391b
SG
2002 }
2003
2004 /* enable receiver to enable frame reception */
47bbea41 2005 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
e3c678e6
SG
2006 if (ret < 0) {
2007 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
2008 goto done;
2009 }
6c636503
SG
2010
2011 val |= MAC_RX_RXEN;
2012
47bbea41 2013 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
e3c678e6
SG
2014 if (ret < 0) {
2015 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
2016 goto done;
2017 }
6c636503
SG
2018
2019 /* some wol options are enabled, so enter SUSPEND0 */
1e1d7412 2020 netdev_info(dev->net, "entering SUSPEND0 mode\n");
eacdd6c2
SG
2021 ret = smsc75xx_enter_suspend0(dev);
2022
2023done:
5410a473
ML
2024 /*
2025 * TODO: resume() might need to handle the suspend failure
2026 * in system sleep
2027 */
2028 if (ret && PMSG_IS_AUTO(message))
eacdd6c2
SG
2029 usbnet_resume(intf);
2030 return ret;
16c79a04
SG
2031}
2032
2033static int smsc75xx_resume(struct usb_interface *intf)
2034{
2035 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 2036 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
b4cdea9c 2037 u8 suspend_flags = pdata->suspend_flags;
16c79a04
SG
2038 int ret;
2039 u32 val;
2040
b4cdea9c 2041 netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
16c79a04 2042
b4cdea9c
SG
2043 /* do this first to ensure it's cleared even in error case */
2044 pdata->suspend_flags = 0;
2045
b4cdea9c 2046 if (suspend_flags & SUSPEND_ALLMODES) {
899a391b 2047 /* Disable wakeup sources */
47bbea41 2048 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
2049 if (ret < 0) {
2050 netdev_warn(dev->net, "Error reading WUCSR\n");
2051 return ret;
2052 }
16c79a04 2053
899a391b
SG
2054 val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
2055 | WUCSR_BCST_EN);
16c79a04 2056
47bbea41 2057 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
2058 if (ret < 0) {
2059 netdev_warn(dev->net, "Error writing WUCSR\n");
2060 return ret;
2061 }
6c636503
SG
2062
2063 /* clear wake-up status */
47bbea41 2064 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2065 if (ret < 0) {
2066 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2067 return ret;
2068 }
6c636503
SG
2069
2070 val &= ~PMT_CTL_WOL_EN;
2071 val |= PMT_CTL_WUPS;
2072
47bbea41 2073 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2074 if (ret < 0) {
2075 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2076 return ret;
2077 }
b4cdea9c
SG
2078 }
2079
2080 if (suspend_flags & SUSPEND_SUSPEND2) {
1e1d7412 2081 netdev_info(dev->net, "resuming from SUSPEND2\n");
6c636503 2082
47bbea41 2083 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2084 if (ret < 0) {
2085 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2086 return ret;
2087 }
6c636503
SG
2088
2089 val |= PMT_CTL_PHY_PWRUP;
2090
47bbea41 2091 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2092 if (ret < 0) {
2093 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2094 return ret;
2095 }
6c636503 2096 }
16c79a04 2097
47bbea41 2098 ret = smsc75xx_wait_ready(dev, 1);
e3c678e6
SG
2099 if (ret < 0) {
2100 netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
2101 return ret;
2102 }
16c79a04
SG
2103
2104 return usbnet_resume(intf);
2105}
2106
78e47fe4
MM
2107static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
2108 u32 rx_cmd_a, u32 rx_cmd_b)
d0cad871 2109{
78e47fe4
MM
2110 if (!(dev->net->features & NETIF_F_RXCSUM) ||
2111 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
d0cad871
SG
2112 skb->ip_summed = CHECKSUM_NONE;
2113 } else {
2114 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
2115 skb->ip_summed = CHECKSUM_COMPLETE;
2116 }
2117}
2118
2119static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
2120{
eb85569f
EG
2121 /* This check is no longer done by usbnet */
2122 if (skb->len < dev->net->hard_header_len)
2123 return 0;
2124
d0cad871
SG
2125 while (skb->len > 0) {
2126 u32 rx_cmd_a, rx_cmd_b, align_count, size;
2127 struct sk_buff *ax_skb;
2128 unsigned char *packet;
2129
2130 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
2131 le32_to_cpus(&rx_cmd_a);
2132 skb_pull(skb, 4);
2133
2134 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
2135 le32_to_cpus(&rx_cmd_b);
ea1649de 2136 skb_pull(skb, 4 + RXW_PADDING);
d0cad871
SG
2137
2138 packet = skb->data;
2139
2140 /* get the packet length */
ea1649de
NE
2141 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
2142 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
d0cad871
SG
2143
2144 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
2145 netif_dbg(dev, rx_err, dev->net,
1e1d7412 2146 "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
d0cad871
SG
2147 dev->net->stats.rx_errors++;
2148 dev->net->stats.rx_dropped++;
2149
2150 if (rx_cmd_a & RX_CMD_A_FCS)
2151 dev->net->stats.rx_crc_errors++;
2152 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
2153 dev->net->stats.rx_frame_errors++;
2154 } else {
4c51e536
SG
2155 /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
2156 if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
d0cad871 2157 netif_dbg(dev, rx_err, dev->net,
1e1d7412
JP
2158 "size err rx_cmd_a=0x%08x\n",
2159 rx_cmd_a);
d0cad871
SG
2160 return 0;
2161 }
2162
2163 /* last frame in this batch */
2164 if (skb->len == size) {
78e47fe4
MM
2165 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
2166 rx_cmd_b);
d0cad871
SG
2167
2168 skb_trim(skb, skb->len - 4); /* remove fcs */
2169 skb->truesize = size + sizeof(struct sk_buff);
2170
2171 return 1;
2172 }
2173
2174 ax_skb = skb_clone(skb, GFP_ATOMIC);
2175 if (unlikely(!ax_skb)) {
1e1d7412 2176 netdev_warn(dev->net, "Error allocating skb\n");
d0cad871
SG
2177 return 0;
2178 }
2179
2180 ax_skb->len = size;
2181 ax_skb->data = packet;
2182 skb_set_tail_pointer(ax_skb, size);
2183
78e47fe4
MM
2184 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
2185 rx_cmd_b);
d0cad871
SG
2186
2187 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
2188 ax_skb->truesize = size + sizeof(struct sk_buff);
2189
2190 usbnet_skb_return(dev, ax_skb);
2191 }
2192
2193 skb_pull(skb, size);
2194
2195 /* padding bytes before the next frame starts */
2196 if (skb->len)
2197 skb_pull(skb, align_count);
2198 }
2199
d0cad871
SG
2200 return 1;
2201}
2202
2203static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
2204 struct sk_buff *skb, gfp_t flags)
2205{
2206 u32 tx_cmd_a, tx_cmd_b;
2207
d0cad871
SG
2208 if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
2209 struct sk_buff *skb2 =
2210 skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
2211 dev_kfree_skb_any(skb);
2212 skb = skb2;
2213 if (!skb)
2214 return NULL;
2215 }
2216
2217 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
2218
2219 if (skb->ip_summed == CHECKSUM_PARTIAL)
2220 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
2221
2222 if (skb_is_gso(skb)) {
2223 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
2224 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
2225
2226 tx_cmd_a |= TX_CMD_A_LSO;
2227 } else {
2228 tx_cmd_b = 0;
2229 }
2230
2231 skb_push(skb, 4);
2232 cpu_to_le32s(&tx_cmd_b);
2233 memcpy(skb->data, &tx_cmd_b, 4);
2234
2235 skb_push(skb, 4);
2236 cpu_to_le32s(&tx_cmd_a);
2237 memcpy(skb->data, &tx_cmd_a, 4);
2238
2239 return skb;
2240}
2241
b4cdea9c
SG
2242static int smsc75xx_manage_power(struct usbnet *dev, int on)
2243{
2244 dev->intf->needs_remote_wakeup = on;
2245 return 0;
2246}
2247
d0cad871
SG
2248static const struct driver_info smsc75xx_info = {
2249 .description = "smsc75xx USB 2.0 Gigabit Ethernet",
2250 .bind = smsc75xx_bind,
2251 .unbind = smsc75xx_unbind,
2252 .link_reset = smsc75xx_link_reset,
2253 .reset = smsc75xx_reset,
2254 .rx_fixup = smsc75xx_rx_fixup,
2255 .tx_fixup = smsc75xx_tx_fixup,
2256 .status = smsc75xx_status,
b4cdea9c 2257 .manage_power = smsc75xx_manage_power,
7bdd305e 2258 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
d0cad871
SG
2259};
2260
2261static const struct usb_device_id products[] = {
2262 {
2263 /* SMSC7500 USB Gigabit Ethernet Device */
2264 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
2265 .driver_info = (unsigned long) &smsc75xx_info,
2266 },
2267 {
2268 /* SMSC7500 USB Gigabit Ethernet Device */
2269 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
2270 .driver_info = (unsigned long) &smsc75xx_info,
2271 },
2272 { }, /* END */
2273};
2274MODULE_DEVICE_TABLE(usb, products);
2275
2276static struct usb_driver smsc75xx_driver = {
2277 .name = SMSC_CHIPNAME,
2278 .id_table = products,
2279 .probe = usbnet_probe,
16c79a04
SG
2280 .suspend = smsc75xx_suspend,
2281 .resume = smsc75xx_resume,
2282 .reset_resume = smsc75xx_resume,
d0cad871 2283 .disconnect = usbnet_disconnect,
e1f12eb6 2284 .disable_hub_initiated_lpm = 1,
b4cdea9c 2285 .supports_autosuspend = 1,
d0cad871
SG
2286};
2287
d632eb1b 2288module_usb_driver(smsc75xx_driver);
d0cad871
SG
2289
2290MODULE_AUTHOR("Nancy Lin");
90b24cfb 2291MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
d0cad871
SG
2292MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
2293MODULE_LICENSE("GPL");
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