Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm...
[deliverable/linux.git] / drivers / net / usb / smsc75xx.c
CommitLineData
d0cad871
SG
1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2010 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
9cb00073 16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
d0cad871
SG
17 *
18 *****************************************************************************/
19
20#include <linux/module.h>
21#include <linux/kmod.h>
d0cad871
SG
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/usb.h>
899a391b
SG
27#include <linux/bitrev.h>
28#include <linux/crc16.h>
d0cad871
SG
29#include <linux/crc32.h>
30#include <linux/usb/usbnet.h>
5a0e3ad6 31#include <linux/slab.h>
c489565b 32#include <linux/of_net.h>
d0cad871
SG
33#include "smsc75xx.h"
34
35#define SMSC_CHIPNAME "smsc75xx"
36#define SMSC_DRIVER_VERSION "1.0.0"
37#define HS_USB_PKT_SIZE (512)
38#define FS_USB_PKT_SIZE (64)
39#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
40#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
41#define DEFAULT_BULK_IN_DELAY (0x00002000)
42#define MAX_SINGLE_PACKET_SIZE (9000)
43#define LAN75XX_EEPROM_MAGIC (0x7500)
44#define EEPROM_MAC_OFFSET (0x01)
45#define DEFAULT_TX_CSUM_ENABLE (true)
46#define DEFAULT_RX_CSUM_ENABLE (true)
d0cad871
SG
47#define SMSC75XX_INTERNAL_PHY_ID (1)
48#define SMSC75XX_TX_OVERHEAD (8)
49#define MAX_RX_FIFO_SIZE (20 * 1024)
50#define MAX_TX_FIFO_SIZE (12 * 1024)
51#define USB_VENDOR_ID_SMSC (0x0424)
52#define USB_PRODUCT_ID_LAN7500 (0x7500)
53#define USB_PRODUCT_ID_LAN7505 (0x7505)
ea1649de 54#define RXW_PADDING 2
f329ccdc 55#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
899a391b 56 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
d0cad871 57
b4cdea9c
SG
58#define SUSPEND_SUSPEND0 (0x01)
59#define SUSPEND_SUSPEND1 (0x02)
60#define SUSPEND_SUSPEND2 (0x04)
61#define SUSPEND_SUSPEND3 (0x08)
b4cdea9c
SG
62#define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
63 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
64
d0cad871
SG
65struct smsc75xx_priv {
66 struct usbnet *dev;
67 u32 rfe_ctl;
6c636503 68 u32 wolopts;
d0cad871 69 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
d0cad871
SG
70 struct mutex dataport_mutex;
71 spinlock_t rfe_ctl_lock;
72 struct work_struct set_multicast;
b4cdea9c 73 u8 suspend_flags;
d0cad871
SG
74};
75
76struct usb_context {
77 struct usb_ctrlrequest req;
78 struct usbnet *dev;
79};
80
eb939922 81static bool turbo_mode = true;
d0cad871
SG
82module_param(turbo_mode, bool, 0644);
83MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
84
47bbea41
ML
85static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
86 u32 *data, int in_pm)
d0cad871 87{
2b2e41e3 88 u32 buf;
d0cad871 89 int ret;
47bbea41 90 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
d0cad871
SG
91
92 BUG_ON(!dev);
93
47bbea41
ML
94 if (!in_pm)
95 fn = usbnet_read_cmd;
96 else
97 fn = usbnet_read_cmd_nopm;
98
99 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
100 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
101 0, index, &buf, 4);
d0cad871 102 if (unlikely(ret < 0))
1e1d7412
JP
103 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
104 index, ret);
d0cad871 105
2b2e41e3
ML
106 le32_to_cpus(&buf);
107 *data = buf;
d0cad871
SG
108
109 return ret;
110}
111
47bbea41
ML
112static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
113 u32 data, int in_pm)
d0cad871 114{
2b2e41e3 115 u32 buf;
d0cad871 116 int ret;
47bbea41 117 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
d0cad871
SG
118
119 BUG_ON(!dev);
120
47bbea41
ML
121 if (!in_pm)
122 fn = usbnet_write_cmd;
123 else
124 fn = usbnet_write_cmd_nopm;
125
2b2e41e3
ML
126 buf = data;
127 cpu_to_le32s(&buf);
d0cad871 128
47bbea41
ML
129 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
130 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
131 0, index, &buf, 4);
d0cad871 132 if (unlikely(ret < 0))
1e1d7412
JP
133 netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
134 index, ret);
d0cad871 135
d0cad871
SG
136 return ret;
137}
138
47bbea41
ML
139static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
140 u32 *data)
141{
142 return __smsc75xx_read_reg(dev, index, data, 1);
143}
144
145static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
146 u32 data)
147{
148 return __smsc75xx_write_reg(dev, index, data, 1);
149}
150
151static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
152 u32 *data)
153{
154 return __smsc75xx_read_reg(dev, index, data, 0);
155}
156
157static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
158 u32 data)
159{
160 return __smsc75xx_write_reg(dev, index, data, 0);
161}
162
d0cad871
SG
163/* Loop until the read is completed with timeout
164 * called with phy_mutex held */
f329ccdc
SG
165static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
166 int in_pm)
d0cad871
SG
167{
168 unsigned long start_time = jiffies;
169 u32 val;
170 int ret;
171
172 do {
f329ccdc 173 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
e3c678e6
SG
174 if (ret < 0) {
175 netdev_warn(dev->net, "Error reading MII_ACCESS\n");
176 return ret;
177 }
d0cad871
SG
178
179 if (!(val & MII_ACCESS_BUSY))
180 return 0;
181 } while (!time_after(jiffies, start_time + HZ));
182
183 return -EIO;
184}
185
f329ccdc
SG
186static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
187 int in_pm)
d0cad871
SG
188{
189 struct usbnet *dev = netdev_priv(netdev);
190 u32 val, addr;
191 int ret;
192
193 mutex_lock(&dev->phy_mutex);
194
195 /* confirm MII not busy */
f329ccdc 196 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
197 if (ret < 0) {
198 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
199 goto done;
200 }
d0cad871
SG
201
202 /* set the address, index & direction (read from PHY) */
203 phy_id &= dev->mii.phy_id_mask;
204 idx &= dev->mii.reg_num_mask;
205 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
206 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 207 | MII_ACCESS_READ | MII_ACCESS_BUSY;
f329ccdc 208 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
209 if (ret < 0) {
210 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
211 goto done;
212 }
d0cad871 213
f329ccdc 214 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
215 if (ret < 0) {
216 netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
217 goto done;
218 }
d0cad871 219
f329ccdc 220 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
e3c678e6
SG
221 if (ret < 0) {
222 netdev_warn(dev->net, "Error reading MII_DATA\n");
223 goto done;
224 }
d0cad871
SG
225
226 ret = (u16)(val & 0xFFFF);
227
228done:
229 mutex_unlock(&dev->phy_mutex);
230 return ret;
231}
232
f329ccdc
SG
233static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
234 int idx, int regval, int in_pm)
d0cad871
SG
235{
236 struct usbnet *dev = netdev_priv(netdev);
237 u32 val, addr;
238 int ret;
239
240 mutex_lock(&dev->phy_mutex);
241
242 /* confirm MII not busy */
f329ccdc 243 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
244 if (ret < 0) {
245 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
246 goto done;
247 }
d0cad871
SG
248
249 val = regval;
f329ccdc 250 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
e3c678e6
SG
251 if (ret < 0) {
252 netdev_warn(dev->net, "Error writing MII_DATA\n");
253 goto done;
254 }
d0cad871
SG
255
256 /* set the address, index & direction (write to PHY) */
257 phy_id &= dev->mii.phy_id_mask;
258 idx &= dev->mii.reg_num_mask;
259 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
260 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 261 | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
f329ccdc 262 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
263 if (ret < 0) {
264 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
265 goto done;
266 }
d0cad871 267
f329ccdc 268 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
269 if (ret < 0) {
270 netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
271 goto done;
272 }
d0cad871
SG
273
274done:
275 mutex_unlock(&dev->phy_mutex);
276}
277
f329ccdc
SG
278static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
279 int idx)
280{
281 return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
282}
283
284static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
285 int idx, int regval)
286{
287 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
288}
289
290static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
291{
292 return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
293}
294
295static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
296 int regval)
297{
298 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
299}
300
d0cad871
SG
301static int smsc75xx_wait_eeprom(struct usbnet *dev)
302{
303 unsigned long start_time = jiffies;
304 u32 val;
305 int ret;
306
307 do {
308 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
309 if (ret < 0) {
310 netdev_warn(dev->net, "Error reading E2P_CMD\n");
311 return ret;
312 }
d0cad871
SG
313
314 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
315 break;
316 udelay(40);
317 } while (!time_after(jiffies, start_time + HZ));
318
319 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
1e1d7412 320 netdev_warn(dev->net, "EEPROM read operation timeout\n");
d0cad871
SG
321 return -EIO;
322 }
323
324 return 0;
325}
326
327static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
328{
329 unsigned long start_time = jiffies;
330 u32 val;
331 int ret;
332
333 do {
334 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
335 if (ret < 0) {
336 netdev_warn(dev->net, "Error reading E2P_CMD\n");
337 return ret;
338 }
d0cad871
SG
339
340 if (!(val & E2P_CMD_BUSY))
341 return 0;
342
343 udelay(40);
344 } while (!time_after(jiffies, start_time + HZ));
345
1e1d7412 346 netdev_warn(dev->net, "EEPROM is busy\n");
d0cad871
SG
347 return -EIO;
348}
349
350static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
351 u8 *data)
352{
353 u32 val;
354 int i, ret;
355
356 BUG_ON(!dev);
357 BUG_ON(!data);
358
359 ret = smsc75xx_eeprom_confirm_not_busy(dev);
360 if (ret)
361 return ret;
362
363 for (i = 0; i < length; i++) {
364 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
365 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
366 if (ret < 0) {
367 netdev_warn(dev->net, "Error writing E2P_CMD\n");
368 return ret;
369 }
d0cad871
SG
370
371 ret = smsc75xx_wait_eeprom(dev);
372 if (ret < 0)
373 return ret;
374
375 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
e3c678e6
SG
376 if (ret < 0) {
377 netdev_warn(dev->net, "Error reading E2P_DATA\n");
378 return ret;
379 }
d0cad871
SG
380
381 data[i] = val & 0xFF;
382 offset++;
383 }
384
385 return 0;
386}
387
388static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
389 u8 *data)
390{
391 u32 val;
392 int i, ret;
393
394 BUG_ON(!dev);
395 BUG_ON(!data);
396
397 ret = smsc75xx_eeprom_confirm_not_busy(dev);
398 if (ret)
399 return ret;
400
401 /* Issue write/erase enable command */
402 val = E2P_CMD_BUSY | E2P_CMD_EWEN;
403 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
404 if (ret < 0) {
405 netdev_warn(dev->net, "Error writing E2P_CMD\n");
406 return ret;
407 }
d0cad871
SG
408
409 ret = smsc75xx_wait_eeprom(dev);
410 if (ret < 0)
411 return ret;
412
413 for (i = 0; i < length; i++) {
414
415 /* Fill data register */
416 val = data[i];
417 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
e3c678e6
SG
418 if (ret < 0) {
419 netdev_warn(dev->net, "Error writing E2P_DATA\n");
420 return ret;
421 }
d0cad871
SG
422
423 /* Send "write" command */
424 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
425 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
426 if (ret < 0) {
427 netdev_warn(dev->net, "Error writing E2P_CMD\n");
428 return ret;
429 }
d0cad871
SG
430
431 ret = smsc75xx_wait_eeprom(dev);
432 if (ret < 0)
433 return ret;
434
435 offset++;
436 }
437
438 return 0;
439}
440
441static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
442{
443 int i, ret;
444
445 for (i = 0; i < 100; i++) {
446 u32 dp_sel;
447 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
448 if (ret < 0) {
449 netdev_warn(dev->net, "Error reading DP_SEL\n");
450 return ret;
451 }
d0cad871
SG
452
453 if (dp_sel & DP_SEL_DPRDY)
454 return 0;
455
456 udelay(40);
457 }
458
1e1d7412 459 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
d0cad871
SG
460
461 return -EIO;
462}
463
464static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
465 u32 length, u32 *buf)
466{
467 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
468 u32 dp_sel;
469 int i, ret;
470
471 mutex_lock(&pdata->dataport_mutex);
472
473 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
474 if (ret < 0) {
475 netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
476 goto done;
477 }
d0cad871
SG
478
479 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
480 if (ret < 0) {
481 netdev_warn(dev->net, "Error reading DP_SEL\n");
482 goto done;
483 }
d0cad871
SG
484
485 dp_sel &= ~DP_SEL_RSEL;
486 dp_sel |= ram_select;
487 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
e3c678e6
SG
488 if (ret < 0) {
489 netdev_warn(dev->net, "Error writing DP_SEL\n");
490 goto done;
491 }
d0cad871
SG
492
493 for (i = 0; i < length; i++) {
494 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
e3c678e6
SG
495 if (ret < 0) {
496 netdev_warn(dev->net, "Error writing DP_ADDR\n");
497 goto done;
498 }
d0cad871
SG
499
500 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
e3c678e6
SG
501 if (ret < 0) {
502 netdev_warn(dev->net, "Error writing DP_DATA\n");
503 goto done;
504 }
d0cad871
SG
505
506 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
e3c678e6
SG
507 if (ret < 0) {
508 netdev_warn(dev->net, "Error writing DP_CMD\n");
509 goto done;
510 }
d0cad871
SG
511
512 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
513 if (ret < 0) {
514 netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
515 goto done;
516 }
d0cad871
SG
517 }
518
519done:
520 mutex_unlock(&pdata->dataport_mutex);
521 return ret;
522}
523
524/* returns hash bit number for given MAC address */
525static u32 smsc75xx_hash(char addr[ETH_ALEN])
526{
527 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
528}
529
530static void smsc75xx_deferred_multicast_write(struct work_struct *param)
531{
532 struct smsc75xx_priv *pdata =
533 container_of(param, struct smsc75xx_priv, set_multicast);
534 struct usbnet *dev = pdata->dev;
535 int ret;
536
1e1d7412
JP
537 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
538 pdata->rfe_ctl);
d0cad871
SG
539
540 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
541 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
542
543 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
544 if (ret < 0)
545 netdev_warn(dev->net, "Error writing RFE_CRL\n");
d0cad871
SG
546}
547
548static void smsc75xx_set_multicast(struct net_device *netdev)
549{
550 struct usbnet *dev = netdev_priv(netdev);
551 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
552 unsigned long flags;
553 int i;
554
555 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
556
557 pdata->rfe_ctl &=
558 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
559 pdata->rfe_ctl |= RFE_CTL_AB;
560
561 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
562 pdata->multicast_hash_table[i] = 0;
563
564 if (dev->net->flags & IFF_PROMISC) {
1e1d7412 565 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
d0cad871
SG
566 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
567 } else if (dev->net->flags & IFF_ALLMULTI) {
1e1d7412 568 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
d0cad871
SG
569 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
570 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 571 struct netdev_hw_addr *ha;
d0cad871 572
1e1d7412 573 netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
d0cad871
SG
574
575 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
576
22bedad3
JP
577 netdev_for_each_mc_addr(ha, netdev) {
578 u32 bitnum = smsc75xx_hash(ha->addr);
d0cad871
SG
579 pdata->multicast_hash_table[bitnum / 32] |=
580 (1 << (bitnum % 32));
581 }
582 } else {
1e1d7412 583 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
d0cad871
SG
584 pdata->rfe_ctl |= RFE_CTL_DPF;
585 }
586
587 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
588
589 /* defer register writes to a sleepable context */
590 schedule_work(&pdata->set_multicast);
591}
592
593static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
594 u16 lcladv, u16 rmtadv)
595{
596 u32 flow = 0, fct_flow = 0;
597 int ret;
598
599 if (duplex == DUPLEX_FULL) {
600 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
601
602 if (cap & FLOW_CTRL_TX) {
603 flow = (FLOW_TX_FCEN | 0xFFFF);
604 /* set fct_flow thresholds to 20% and 80% */
605 fct_flow = (8 << 8) | 32;
606 }
607
608 if (cap & FLOW_CTRL_RX)
609 flow |= FLOW_RX_FCEN;
610
1e1d7412
JP
611 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
612 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
613 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
d0cad871 614 } else {
1e1d7412 615 netif_dbg(dev, link, dev->net, "half duplex\n");
d0cad871
SG
616 }
617
618 ret = smsc75xx_write_reg(dev, FLOW, flow);
e3c678e6
SG
619 if (ret < 0) {
620 netdev_warn(dev->net, "Error writing FLOW\n");
621 return ret;
622 }
d0cad871
SG
623
624 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
e3c678e6
SG
625 if (ret < 0) {
626 netdev_warn(dev->net, "Error writing FCT_FLOW\n");
627 return ret;
628 }
d0cad871
SG
629
630 return 0;
631}
632
633static int smsc75xx_link_reset(struct usbnet *dev)
634{
635 struct mii_if_info *mii = &dev->mii;
8ae6daca 636 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
d0cad871
SG
637 u16 lcladv, rmtadv;
638 int ret;
639
4f94a929 640 /* write to clear phy interrupt status */
7749622d
SG
641 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
642 PHY_INT_SRC_CLEAR_ALL);
d0cad871
SG
643
644 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
645 if (ret < 0) {
646 netdev_warn(dev->net, "Error writing INT_STS\n");
647 return ret;
648 }
d0cad871
SG
649
650 mii_check_media(mii, 1, 1);
651 mii_ethtool_gset(&dev->mii, &ecmd);
652 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
653 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
654
1e1d7412
JP
655 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
656 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
d0cad871
SG
657
658 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
659}
660
661static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
662{
663 u32 intdata;
664
665 if (urb->actual_length != 4) {
1e1d7412
JP
666 netdev_warn(dev->net, "unexpected urb length %d\n",
667 urb->actual_length);
d0cad871
SG
668 return;
669 }
670
671 memcpy(&intdata, urb->transfer_buffer, 4);
672 le32_to_cpus(&intdata);
673
1e1d7412 674 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
d0cad871
SG
675
676 if (intdata & INT_ENP_PHY_INT)
677 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
678 else
1e1d7412
JP
679 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
680 intdata);
d0cad871
SG
681}
682
d0cad871
SG
683static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
684{
685 return MAX_EEPROM_SIZE;
686}
687
688static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
689 struct ethtool_eeprom *ee, u8 *data)
690{
691 struct usbnet *dev = netdev_priv(netdev);
692
693 ee->magic = LAN75XX_EEPROM_MAGIC;
694
695 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
696}
697
698static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
699 struct ethtool_eeprom *ee, u8 *data)
700{
701 struct usbnet *dev = netdev_priv(netdev);
702
703 if (ee->magic != LAN75XX_EEPROM_MAGIC) {
1e1d7412
JP
704 netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
705 ee->magic);
d0cad871
SG
706 return -EINVAL;
707 }
708
709 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
710}
711
6c636503
SG
712static void smsc75xx_ethtool_get_wol(struct net_device *net,
713 struct ethtool_wolinfo *wolinfo)
714{
715 struct usbnet *dev = netdev_priv(net);
716 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
717
718 wolinfo->supported = SUPPORTED_WAKE;
719 wolinfo->wolopts = pdata->wolopts;
720}
721
722static int smsc75xx_ethtool_set_wol(struct net_device *net,
723 struct ethtool_wolinfo *wolinfo)
724{
725 struct usbnet *dev = netdev_priv(net);
726 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
351f33d9 727 int ret;
6c636503
SG
728
729 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
351f33d9
SG
730
731 ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
e3c678e6
SG
732 if (ret < 0)
733 netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
351f33d9 734
e3c678e6 735 return ret;
6c636503
SG
736}
737
d0cad871
SG
738static const struct ethtool_ops smsc75xx_ethtool_ops = {
739 .get_link = usbnet_get_link,
740 .nway_reset = usbnet_nway_reset,
741 .get_drvinfo = usbnet_get_drvinfo,
742 .get_msglevel = usbnet_get_msglevel,
743 .set_msglevel = usbnet_set_msglevel,
744 .get_settings = usbnet_get_settings,
745 .set_settings = usbnet_set_settings,
746 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
747 .get_eeprom = smsc75xx_ethtool_get_eeprom,
748 .set_eeprom = smsc75xx_ethtool_set_eeprom,
6c636503
SG
749 .get_wol = smsc75xx_ethtool_get_wol,
750 .set_wol = smsc75xx_ethtool_set_wol,
d0cad871
SG
751};
752
753static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
754{
755 struct usbnet *dev = netdev_priv(netdev);
756
757 if (!netif_running(netdev))
758 return -EINVAL;
759
760 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
761}
762
763static void smsc75xx_init_mac_address(struct usbnet *dev)
764{
c489565b
AB
765 const u8 *mac_addr;
766
767 /* maybe the boot loader passed the MAC address in devicetree */
768 mac_addr = of_get_mac_address(dev->udev->dev.of_node);
769 if (mac_addr) {
770 memcpy(dev->net->dev_addr, mac_addr, ETH_ALEN);
771 return;
772 }
773
d0cad871
SG
774 /* try reading mac address from EEPROM */
775 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
776 dev->net->dev_addr) == 0) {
777 if (is_valid_ether_addr(dev->net->dev_addr)) {
778 /* eeprom values are valid so use them */
779 netif_dbg(dev, ifup, dev->net,
1e1d7412 780 "MAC address read from EEPROM\n");
d0cad871
SG
781 return;
782 }
783 }
784
c489565b 785 /* no useful static MAC address found. generate a random one */
f2cedb63 786 eth_hw_addr_random(dev->net);
1e1d7412 787 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
d0cad871
SG
788}
789
790static int smsc75xx_set_mac_address(struct usbnet *dev)
791{
792 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
793 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
794 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
795
796 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
e3c678e6
SG
797 if (ret < 0) {
798 netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
799 return ret;
800 }
d0cad871
SG
801
802 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
e3c678e6
SG
803 if (ret < 0) {
804 netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
805 return ret;
806 }
d0cad871
SG
807
808 addr_hi |= ADDR_FILTX_FB_VALID;
809 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
e3c678e6
SG
810 if (ret < 0) {
811 netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
812 return ret;
813 }
d0cad871
SG
814
815 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
e3c678e6
SG
816 if (ret < 0)
817 netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
d0cad871 818
e3c678e6 819 return ret;
d0cad871
SG
820}
821
822static int smsc75xx_phy_initialize(struct usbnet *dev)
823{
b140504a 824 int bmcr, ret, timeout = 0;
d0cad871
SG
825
826 /* Initialize MII structure */
827 dev->mii.dev = dev->net;
828 dev->mii.mdio_read = smsc75xx_mdio_read;
829 dev->mii.mdio_write = smsc75xx_mdio_write;
830 dev->mii.phy_id_mask = 0x1f;
831 dev->mii.reg_num_mask = 0x1f;
c0b92e4d 832 dev->mii.supports_gmii = 1;
d0cad871
SG
833 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
834
835 /* reset phy and wait for reset to complete */
836 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
837
838 do {
839 msleep(10);
840 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
e3c678e6
SG
841 if (bmcr < 0) {
842 netdev_warn(dev->net, "Error reading MII_BMCR\n");
843 return bmcr;
844 }
d0cad871 845 timeout++;
8a1d59d7 846 } while ((bmcr & BMCR_RESET) && (timeout < 100));
d0cad871
SG
847
848 if (timeout >= 100) {
1e1d7412 849 netdev_warn(dev->net, "timeout on PHY Reset\n");
d0cad871
SG
850 return -EIO;
851 }
852
853 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
854 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
855 ADVERTISE_PAUSE_ASYM);
c0b92e4d
SG
856 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
857 ADVERTISE_1000FULL);
d0cad871 858
b140504a
SG
859 /* read and write to clear phy interrupt status */
860 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
e3c678e6
SG
861 if (ret < 0) {
862 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
863 return ret;
864 }
865
b140504a 866 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
d0cad871
SG
867
868 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
869 PHY_INT_MASK_DEFAULT);
870 mii_nway_restart(&dev->mii);
871
1e1d7412 872 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
d0cad871
SG
873 return 0;
874}
875
876static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
877{
878 int ret = 0;
879 u32 buf;
880 bool rxenabled;
881
882 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
883 if (ret < 0) {
884 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
885 return ret;
886 }
d0cad871
SG
887
888 rxenabled = ((buf & MAC_RX_RXEN) != 0);
889
890 if (rxenabled) {
891 buf &= ~MAC_RX_RXEN;
892 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
893 if (ret < 0) {
894 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
895 return ret;
896 }
d0cad871
SG
897 }
898
899 /* add 4 to size for FCS */
900 buf &= ~MAC_RX_MAX_SIZE;
901 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
902
903 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
904 if (ret < 0) {
905 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
906 return ret;
907 }
d0cad871
SG
908
909 if (rxenabled) {
910 buf |= MAC_RX_RXEN;
911 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
912 if (ret < 0) {
913 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
914 return ret;
915 }
d0cad871
SG
916 }
917
918 return 0;
919}
920
921static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
922{
923 struct usbnet *dev = netdev_priv(netdev);
4c51e536
SG
924 int ret;
925
926 if (new_mtu > MAX_SINGLE_PACKET_SIZE)
927 return -EINVAL;
d0cad871 928
4c51e536 929 ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
e3c678e6
SG
930 if (ret < 0) {
931 netdev_warn(dev->net, "Failed to set mac rx frame length\n");
932 return ret;
933 }
d0cad871
SG
934
935 return usbnet_change_mtu(netdev, new_mtu);
936}
937
78e47fe4 938/* Enable or disable Rx checksum offload engine */
c8f44aff
MM
939static int smsc75xx_set_features(struct net_device *netdev,
940 netdev_features_t features)
78e47fe4
MM
941{
942 struct usbnet *dev = netdev_priv(netdev);
943 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
944 unsigned long flags;
945 int ret;
946
947 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
948
949 if (features & NETIF_F_RXCSUM)
950 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
951 else
952 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
953
954 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
955 /* it's racing here! */
956
957 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
958 if (ret < 0)
959 netdev_warn(dev->net, "Error writing RFE_CTL\n");
78e47fe4 960
e3c678e6 961 return ret;
78e47fe4
MM
962}
963
47bbea41 964static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
8762cec8
SG
965{
966 int timeout = 0;
967
968 do {
969 u32 buf;
47bbea41
ML
970 int ret;
971
972 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
973
e3c678e6
SG
974 if (ret < 0) {
975 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
976 return ret;
977 }
8762cec8
SG
978
979 if (buf & PMT_CTL_DEV_RDY)
980 return 0;
981
982 msleep(10);
983 timeout++;
984 } while (timeout < 100);
985
1e1d7412 986 netdev_warn(dev->net, "timeout waiting for device ready\n");
8762cec8
SG
987 return -EIO;
988}
989
d0cad871
SG
990static int smsc75xx_reset(struct usbnet *dev)
991{
992 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
993 u32 buf;
994 int ret = 0, timeout;
995
1e1d7412 996 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
d0cad871 997
47bbea41 998 ret = smsc75xx_wait_ready(dev, 0);
e3c678e6
SG
999 if (ret < 0) {
1000 netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
1001 return ret;
1002 }
8762cec8 1003
d0cad871 1004 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1005 if (ret < 0) {
1006 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1007 return ret;
1008 }
d0cad871
SG
1009
1010 buf |= HW_CFG_LRST;
1011
1012 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1013 if (ret < 0) {
1014 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1015 return ret;
1016 }
d0cad871
SG
1017
1018 timeout = 0;
1019 do {
1020 msleep(10);
1021 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1022 if (ret < 0) {
1023 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1024 return ret;
1025 }
d0cad871
SG
1026 timeout++;
1027 } while ((buf & HW_CFG_LRST) && (timeout < 100));
1028
1029 if (timeout >= 100) {
1e1d7412 1030 netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
d0cad871
SG
1031 return -EIO;
1032 }
1033
1e1d7412 1034 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
d0cad871
SG
1035
1036 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1037 if (ret < 0) {
1038 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1039 return ret;
1040 }
d0cad871
SG
1041
1042 buf |= PMT_CTL_PHY_RST;
1043
1044 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
e3c678e6
SG
1045 if (ret < 0) {
1046 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1047 return ret;
1048 }
d0cad871
SG
1049
1050 timeout = 0;
1051 do {
1052 msleep(10);
1053 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1054 if (ret < 0) {
1055 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1056 return ret;
1057 }
d0cad871
SG
1058 timeout++;
1059 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
1060
1061 if (timeout >= 100) {
1e1d7412 1062 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
d0cad871
SG
1063 return -EIO;
1064 }
1065
1e1d7412 1066 netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
d0cad871 1067
d0cad871 1068 ret = smsc75xx_set_mac_address(dev);
e3c678e6
SG
1069 if (ret < 0) {
1070 netdev_warn(dev->net, "Failed to set mac address\n");
1071 return ret;
1072 }
d0cad871 1073
1e1d7412
JP
1074 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
1075 dev->net->dev_addr);
d0cad871
SG
1076
1077 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1078 if (ret < 0) {
1079 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1080 return ret;
1081 }
d0cad871 1082
1e1d7412
JP
1083 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
1084 buf);
d0cad871
SG
1085
1086 buf |= HW_CFG_BIR;
1087
1088 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1089 if (ret < 0) {
1090 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1091 return ret;
1092 }
d0cad871
SG
1093
1094 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1095 if (ret < 0) {
1096 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1097 return ret;
1098 }
d0cad871 1099
1e1d7412
JP
1100 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
1101 buf);
d0cad871
SG
1102
1103 if (!turbo_mode) {
1104 buf = 0;
1105 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
1106 } else if (dev->udev->speed == USB_SPEED_HIGH) {
1107 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
1108 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
1109 } else {
1110 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
1111 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
1112 }
1113
1e1d7412
JP
1114 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
1115 (ulong)dev->rx_urb_size);
d0cad871
SG
1116
1117 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
e3c678e6
SG
1118 if (ret < 0) {
1119 netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
1120 return ret;
1121 }
d0cad871
SG
1122
1123 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
e3c678e6
SG
1124 if (ret < 0) {
1125 netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
1126 return ret;
1127 }
d0cad871
SG
1128
1129 netif_dbg(dev, ifup, dev->net,
1e1d7412 1130 "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
d0cad871
SG
1131
1132 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
e3c678e6
SG
1133 if (ret < 0) {
1134 netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
1135 return ret;
1136 }
d0cad871
SG
1137
1138 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
e3c678e6
SG
1139 if (ret < 0) {
1140 netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
1141 return ret;
1142 }
d0cad871
SG
1143
1144 netif_dbg(dev, ifup, dev->net,
1e1d7412 1145 "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
d0cad871
SG
1146
1147 if (turbo_mode) {
1148 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1149 if (ret < 0) {
1150 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1151 return ret;
1152 }
d0cad871 1153
1e1d7412 1154 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1155
1156 buf |= (HW_CFG_MEF | HW_CFG_BCE);
1157
1158 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1159 if (ret < 0) {
1160 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1161 return ret;
1162 }
d0cad871
SG
1163
1164 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1165 if (ret < 0) {
1166 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1167 return ret;
1168 }
d0cad871 1169
1e1d7412 1170 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1171 }
1172
1173 /* set FIFO sizes */
1174 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
1175 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
e3c678e6
SG
1176 if (ret < 0) {
1177 netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
1178 return ret;
1179 }
d0cad871 1180
1e1d7412 1181 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1182
1183 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
1184 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
e3c678e6
SG
1185 if (ret < 0) {
1186 netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
1187 return ret;
1188 }
d0cad871 1189
1e1d7412 1190 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1191
1192 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
1193 if (ret < 0) {
1194 netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
1195 return ret;
1196 }
d0cad871
SG
1197
1198 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
e3c678e6
SG
1199 if (ret < 0) {
1200 netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
1201 return ret;
1202 }
d0cad871 1203
1e1d7412 1204 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
d0cad871 1205
97138a1c 1206 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
e3c678e6
SG
1207 if (ret < 0) {
1208 netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
1209 return ret;
1210 }
d0cad871 1211
97138a1c
SG
1212 /* only set default GPIO/LED settings if no EEPROM is detected */
1213 if (!(buf & E2P_CMD_LOADED)) {
1214 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
e3c678e6
SG
1215 if (ret < 0) {
1216 netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
1217 return ret;
1218 }
d0cad871 1219
97138a1c
SG
1220 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
1221 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
1222
1223 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
e3c678e6
SG
1224 if (ret < 0) {
1225 netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
1226 return ret;
1227 }
97138a1c 1228 }
d0cad871
SG
1229
1230 ret = smsc75xx_write_reg(dev, FLOW, 0);
e3c678e6
SG
1231 if (ret < 0) {
1232 netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
1233 return ret;
1234 }
d0cad871
SG
1235
1236 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
e3c678e6
SG
1237 if (ret < 0) {
1238 netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
1239 return ret;
1240 }
d0cad871
SG
1241
1242 /* Don't need rfe_ctl_lock during initialisation */
1243 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1244 if (ret < 0) {
1245 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1246 return ret;
1247 }
d0cad871
SG
1248
1249 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
1250
1251 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
1252 if (ret < 0) {
1253 netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
1254 return ret;
1255 }
d0cad871
SG
1256
1257 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1258 if (ret < 0) {
1259 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1260 return ret;
1261 }
d0cad871 1262
1e1d7412
JP
1263 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
1264 pdata->rfe_ctl);
d0cad871
SG
1265
1266 /* Enable or disable checksum offload engines */
78e47fe4 1267 smsc75xx_set_features(dev->net, dev->net->features);
d0cad871
SG
1268
1269 smsc75xx_set_multicast(dev->net);
1270
1271 ret = smsc75xx_phy_initialize(dev);
e3c678e6
SG
1272 if (ret < 0) {
1273 netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
1274 return ret;
1275 }
d0cad871
SG
1276
1277 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
e3c678e6
SG
1278 if (ret < 0) {
1279 netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
1280 return ret;
1281 }
d0cad871
SG
1282
1283 /* enable PHY interrupts */
1284 buf |= INT_ENP_PHY_INT;
1285
1286 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
e3c678e6
SG
1287 if (ret < 0) {
1288 netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
1289 return ret;
1290 }
d0cad871 1291
2f3a081e
SG
1292 /* allow mac to detect speed and duplex from phy */
1293 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
e3c678e6
SG
1294 if (ret < 0) {
1295 netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
1296 return ret;
1297 }
2f3a081e
SG
1298
1299 buf |= (MAC_CR_ADD | MAC_CR_ASD);
1300 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
e3c678e6
SG
1301 if (ret < 0) {
1302 netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
1303 return ret;
1304 }
2f3a081e 1305
d0cad871 1306 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
e3c678e6
SG
1307 if (ret < 0) {
1308 netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
1309 return ret;
1310 }
d0cad871
SG
1311
1312 buf |= MAC_TX_TXEN;
1313
1314 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
e3c678e6
SG
1315 if (ret < 0) {
1316 netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
1317 return ret;
1318 }
d0cad871 1319
1e1d7412 1320 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
d0cad871
SG
1321
1322 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
e3c678e6
SG
1323 if (ret < 0) {
1324 netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
1325 return ret;
1326 }
d0cad871
SG
1327
1328 buf |= FCT_TX_CTL_EN;
1329
1330 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
e3c678e6
SG
1331 if (ret < 0) {
1332 netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
1333 return ret;
1334 }
d0cad871 1335
1e1d7412 1336 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
d0cad871 1337
4c51e536 1338 ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
e3c678e6
SG
1339 if (ret < 0) {
1340 netdev_warn(dev->net, "Failed to set max rx frame length\n");
1341 return ret;
1342 }
d0cad871
SG
1343
1344 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
1345 if (ret < 0) {
1346 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
1347 return ret;
1348 }
d0cad871
SG
1349
1350 buf |= MAC_RX_RXEN;
1351
1352 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
1353 if (ret < 0) {
1354 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
1355 return ret;
1356 }
d0cad871 1357
1e1d7412 1358 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
d0cad871
SG
1359
1360 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
e3c678e6
SG
1361 if (ret < 0) {
1362 netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
1363 return ret;
1364 }
d0cad871
SG
1365
1366 buf |= FCT_RX_CTL_EN;
1367
1368 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
e3c678e6
SG
1369 if (ret < 0) {
1370 netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
1371 return ret;
1372 }
d0cad871 1373
1e1d7412 1374 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
d0cad871 1375
1e1d7412 1376 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
d0cad871
SG
1377 return 0;
1378}
1379
1380static const struct net_device_ops smsc75xx_netdev_ops = {
1381 .ndo_open = usbnet_open,
1382 .ndo_stop = usbnet_stop,
1383 .ndo_start_xmit = usbnet_start_xmit,
1384 .ndo_tx_timeout = usbnet_tx_timeout,
1385 .ndo_change_mtu = smsc75xx_change_mtu,
1386 .ndo_set_mac_address = eth_mac_addr,
1387 .ndo_validate_addr = eth_validate_addr,
1388 .ndo_do_ioctl = smsc75xx_ioctl,
afc4b13d 1389 .ndo_set_rx_mode = smsc75xx_set_multicast,
78e47fe4 1390 .ndo_set_features = smsc75xx_set_features,
d0cad871
SG
1391};
1392
1393static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
1394{
1395 struct smsc75xx_priv *pdata = NULL;
1396 int ret;
1397
1398 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1399
1400 ret = usbnet_get_endpoints(dev, intf);
e3c678e6
SG
1401 if (ret < 0) {
1402 netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
1403 return ret;
1404 }
d0cad871
SG
1405
1406 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
38673c82 1407 GFP_KERNEL);
d0cad871
SG
1408
1409 pdata = (struct smsc75xx_priv *)(dev->data[0]);
38673c82 1410 if (!pdata)
d0cad871 1411 return -ENOMEM;
d0cad871
SG
1412
1413 pdata->dev = dev;
1414
1415 spin_lock_init(&pdata->rfe_ctl_lock);
1416 mutex_init(&pdata->dataport_mutex);
1417
1418 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
1419
20f01703 1420 if (DEFAULT_TX_CSUM_ENABLE)
78e47fe4 1421 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
20f01703 1422
78e47fe4
MM
1423 if (DEFAULT_RX_CSUM_ENABLE)
1424 dev->net->features |= NETIF_F_RXCSUM;
d0cad871 1425
78e47fe4 1426 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
20f01703 1427 NETIF_F_RXCSUM;
d0cad871 1428
481705a1
SG
1429 ret = smsc75xx_wait_ready(dev, 0);
1430 if (ret < 0) {
1431 netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
1432 return ret;
1433 }
1434
1435 smsc75xx_init_mac_address(dev);
1436
d0cad871
SG
1437 /* Init all registers */
1438 ret = smsc75xx_reset(dev);
e3c678e6
SG
1439 if (ret < 0) {
1440 netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
1441 return ret;
1442 }
d0cad871
SG
1443
1444 dev->net->netdev_ops = &smsc75xx_netdev_ops;
1445 dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
1446 dev->net->flags |= IFF_MULTICAST;
1447 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
a99ff7d0 1448 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
d0cad871
SG
1449 return 0;
1450}
1451
1452static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1453{
1454 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1455 if (pdata) {
1e1d7412 1456 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
d0cad871
SG
1457 kfree(pdata);
1458 pdata = NULL;
1459 dev->data[0] = 0;
1460 }
1461}
1462
899a391b
SG
1463static u16 smsc_crc(const u8 *buffer, size_t len)
1464{
1465 return bitrev16(crc16(0xFFFF, buffer, len));
1466}
1467
1468static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
1469 u32 wuf_mask1)
1470{
1471 int cfg_base = WUF_CFGX + filter * 4;
1472 int mask_base = WUF_MASKX + filter * 16;
1473 int ret;
1474
1475 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
e3c678e6
SG
1476 if (ret < 0) {
1477 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1478 return ret;
1479 }
899a391b
SG
1480
1481 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
e3c678e6
SG
1482 if (ret < 0) {
1483 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1484 return ret;
1485 }
899a391b
SG
1486
1487 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
e3c678e6
SG
1488 if (ret < 0) {
1489 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1490 return ret;
1491 }
899a391b
SG
1492
1493 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
e3c678e6
SG
1494 if (ret < 0) {
1495 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1496 return ret;
1497 }
899a391b
SG
1498
1499 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
e3c678e6
SG
1500 if (ret < 0) {
1501 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1502 return ret;
1503 }
899a391b
SG
1504
1505 return 0;
1506}
1507
9deb2757
SG
1508static int smsc75xx_enter_suspend0(struct usbnet *dev)
1509{
b4cdea9c 1510 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1511 u32 val;
1512 int ret;
1513
1514 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1515 if (ret < 0) {
1516 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1517 return ret;
1518 }
9deb2757
SG
1519
1520 val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
1521 val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
1522
1523 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1524 if (ret < 0) {
1525 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1526 return ret;
1527 }
9deb2757 1528
351f33d9 1529 pdata->suspend_flags |= SUSPEND_SUSPEND0;
b4cdea9c 1530
9deb2757
SG
1531 return 0;
1532}
1533
f329ccdc
SG
1534static int smsc75xx_enter_suspend1(struct usbnet *dev)
1535{
b4cdea9c 1536 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc
SG
1537 u32 val;
1538 int ret;
1539
1540 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1541 if (ret < 0) {
1542 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1543 return ret;
1544 }
f329ccdc
SG
1545
1546 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1547 val |= PMT_CTL_SUS_MODE_1;
1548
1549 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1550 if (ret < 0) {
1551 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1552 return ret;
1553 }
f329ccdc
SG
1554
1555 /* clear wol status, enable energy detection */
1556 val &= ~PMT_CTL_WUPS;
1557 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1558
1559 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1560 if (ret < 0) {
1561 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1562 return ret;
1563 }
f329ccdc 1564
351f33d9 1565 pdata->suspend_flags |= SUSPEND_SUSPEND1;
b4cdea9c 1566
f329ccdc
SG
1567 return 0;
1568}
1569
9deb2757
SG
1570static int smsc75xx_enter_suspend2(struct usbnet *dev)
1571{
b4cdea9c 1572 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1573 u32 val;
1574 int ret;
1575
1576 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1577 if (ret < 0) {
1578 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1579 return ret;
1580 }
9deb2757
SG
1581
1582 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1583 val |= PMT_CTL_SUS_MODE_2;
1584
1585 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1586 if (ret < 0) {
1587 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1588 return ret;
1589 }
9deb2757 1590
b4cdea9c
SG
1591 pdata->suspend_flags |= SUSPEND_SUSPEND2;
1592
1593 return 0;
1594}
1595
1596static int smsc75xx_enter_suspend3(struct usbnet *dev)
1597{
1598 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1599 u32 val;
1600 int ret;
1601
1602 ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
e3c678e6
SG
1603 if (ret < 0) {
1604 netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
1605 return ret;
1606 }
b4cdea9c
SG
1607
1608 if (val & FCT_RX_CTL_RXUSED) {
1609 netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
1610 return -EBUSY;
1611 }
1612
1613 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1614 if (ret < 0) {
1615 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1616 return ret;
1617 }
b4cdea9c
SG
1618
1619 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1620 val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
1621
1622 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1623 if (ret < 0) {
1624 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1625 return ret;
1626 }
b4cdea9c
SG
1627
1628 /* clear wol status */
1629 val &= ~PMT_CTL_WUPS;
1630 val |= PMT_CTL_WUPS_WOL;
1631
1632 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1633 if (ret < 0) {
1634 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1635 return ret;
1636 }
b4cdea9c 1637
351f33d9 1638 pdata->suspend_flags |= SUSPEND_SUSPEND3;
b4cdea9c 1639
9deb2757
SG
1640 return 0;
1641}
1642
f329ccdc
SG
1643static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
1644{
1645 struct mii_if_info *mii = &dev->mii;
1646 int ret;
1647
1648 netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
1649
1650 /* read to clear */
1651 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
e3c678e6
SG
1652 if (ret < 0) {
1653 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
1654 return ret;
1655 }
f329ccdc
SG
1656
1657 /* enable interrupt source */
1658 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
e3c678e6
SG
1659 if (ret < 0) {
1660 netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
1661 return ret;
1662 }
f329ccdc
SG
1663
1664 ret |= mask;
1665
1666 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1667
1668 return 0;
1669}
1670
1671static int smsc75xx_link_ok_nopm(struct usbnet *dev)
1672{
1673 struct mii_if_info *mii = &dev->mii;
1674 int ret;
1675
1676 /* first, a dummy read, needed to latch some MII phys */
1677 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1678 if (ret < 0) {
1679 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1680 return ret;
1681 }
f329ccdc
SG
1682
1683 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1684 if (ret < 0) {
1685 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1686 return ret;
1687 }
f329ccdc
SG
1688
1689 return !!(ret & BMSR_LSTATUS);
1690}
1691
b4cdea9c
SG
1692static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
1693{
1694 int ret;
1695
1696 if (!netif_running(dev->net)) {
1697 /* interface is ifconfig down so fully power down hw */
1698 netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
1699 return smsc75xx_enter_suspend2(dev);
1700 }
1701
1702 if (!link_up) {
1703 /* link is down so enter EDPD mode */
1704 netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
1705
1706 /* enable PHY wakeup events for if cable is attached */
1707 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1708 PHY_INT_MASK_ANEG_COMP);
e3c678e6
SG
1709 if (ret < 0) {
1710 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1711 return ret;
1712 }
b4cdea9c
SG
1713
1714 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1715 return smsc75xx_enter_suspend1(dev);
1716 }
1717
1718 /* enable PHY wakeup events so we remote wakeup if cable is pulled */
1719 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1720 PHY_INT_MASK_LINK_DOWN);
e3c678e6
SG
1721 if (ret < 0) {
1722 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1723 return ret;
1724 }
b4cdea9c
SG
1725
1726 netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
1727 return smsc75xx_enter_suspend3(dev);
1728}
1729
16c79a04
SG
1730static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
1731{
1732 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1733 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc 1734 u32 val, link_up;
16c79a04 1735 int ret;
16c79a04 1736
16c79a04 1737 ret = usbnet_suspend(intf, message);
e3c678e6
SG
1738 if (ret < 0) {
1739 netdev_warn(dev->net, "usbnet_suspend error\n");
1740 return ret;
1741 }
16c79a04 1742
b4cdea9c
SG
1743 if (pdata->suspend_flags) {
1744 netdev_warn(dev->net, "error during last resume\n");
1745 pdata->suspend_flags = 0;
1746 }
1747
f329ccdc
SG
1748 /* determine if link is up using only _nopm functions */
1749 link_up = smsc75xx_link_ok_nopm(dev);
1750
b4cdea9c
SG
1751 if (message.event == PM_EVENT_AUTO_SUSPEND) {
1752 ret = smsc75xx_autosuspend(dev, link_up);
1753 goto done;
1754 }
1755
1756 /* if we get this far we're not autosuspending */
f329ccdc
SG
1757 /* if no wol options set, or if link is down and we're not waking on
1758 * PHY activity, enter lowest power SUSPEND2 mode
1759 */
1760 if (!(pdata->wolopts & SUPPORTED_WAKE) ||
1761 !(link_up || (pdata->wolopts & WAKE_PHY))) {
1e1d7412 1762 netdev_info(dev->net, "entering SUSPEND2 mode\n");
6c636503
SG
1763
1764 /* disable energy detect (link up) & wake up events */
47bbea41 1765 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1766 if (ret < 0) {
1767 netdev_warn(dev->net, "Error reading WUCSR\n");
1768 goto done;
1769 }
6c636503
SG
1770
1771 val &= ~(WUCSR_MPEN | WUCSR_WUEN);
1772
47bbea41 1773 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1774 if (ret < 0) {
1775 netdev_warn(dev->net, "Error writing WUCSR\n");
1776 goto done;
1777 }
6c636503 1778
47bbea41 1779 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1780 if (ret < 0) {
1781 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1782 goto done;
1783 }
6c636503
SG
1784
1785 val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
1786
47bbea41 1787 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1788 if (ret < 0) {
1789 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1790 goto done;
1791 }
6c636503 1792
eacdd6c2
SG
1793 ret = smsc75xx_enter_suspend2(dev);
1794 goto done;
6c636503
SG
1795 }
1796
f329ccdc
SG
1797 if (pdata->wolopts & WAKE_PHY) {
1798 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1799 (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
e3c678e6
SG
1800 if (ret < 0) {
1801 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1802 goto done;
1803 }
f329ccdc
SG
1804
1805 /* if link is down then configure EDPD and enter SUSPEND1,
1806 * otherwise enter SUSPEND0 below
1807 */
1808 if (!link_up) {
1809 struct mii_if_info *mii = &dev->mii;
1810 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1811
1812 /* enable energy detect power-down mode */
1813 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1814 PHY_MODE_CTRL_STS);
e3c678e6
SG
1815 if (ret < 0) {
1816 netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
1817 goto done;
1818 }
f329ccdc
SG
1819
1820 ret |= MODE_CTRL_STS_EDPWRDOWN;
1821
1822 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
1823 PHY_MODE_CTRL_STS, ret);
1824
1825 /* enter SUSPEND1 mode */
eacdd6c2
SG
1826 ret = smsc75xx_enter_suspend1(dev);
1827 goto done;
f329ccdc
SG
1828 }
1829 }
1830
899a391b
SG
1831 if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
1832 int i, filter = 0;
1833
1834 /* disable all filters */
1835 for (i = 0; i < WUF_NUM; i++) {
47bbea41 1836 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
e3c678e6
SG
1837 if (ret < 0) {
1838 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1839 goto done;
1840 }
899a391b
SG
1841 }
1842
1843 if (pdata->wolopts & WAKE_MCAST) {
1844 const u8 mcast[] = {0x01, 0x00, 0x5E};
1e1d7412 1845 netdev_info(dev->net, "enabling multicast detection\n");
899a391b
SG
1846
1847 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
1848 | smsc_crc(mcast, 3);
1849 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
e3c678e6
SG
1850 if (ret < 0) {
1851 netdev_warn(dev->net, "Error writing wakeup filter\n");
1852 goto done;
1853 }
899a391b
SG
1854 }
1855
1856 if (pdata->wolopts & WAKE_ARP) {
1857 const u8 arp[] = {0x08, 0x06};
1e1d7412 1858 netdev_info(dev->net, "enabling ARP detection\n");
899a391b
SG
1859
1860 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
1861 | smsc_crc(arp, 2);
1862 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
e3c678e6
SG
1863 if (ret < 0) {
1864 netdev_warn(dev->net, "Error writing wakeup filter\n");
1865 goto done;
1866 }
899a391b
SG
1867 }
1868
1869 /* clear any pending pattern match packet status */
47bbea41 1870 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1871 if (ret < 0) {
1872 netdev_warn(dev->net, "Error reading WUCSR\n");
1873 goto done;
1874 }
899a391b
SG
1875
1876 val |= WUCSR_WUFR;
1877
47bbea41 1878 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1879 if (ret < 0) {
1880 netdev_warn(dev->net, "Error writing WUCSR\n");
1881 goto done;
1882 }
899a391b 1883
1e1d7412 1884 netdev_info(dev->net, "enabling packet match detection\n");
47bbea41 1885 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1886 if (ret < 0) {
1887 netdev_warn(dev->net, "Error reading WUCSR\n");
1888 goto done;
1889 }
899a391b
SG
1890
1891 val |= WUCSR_WUEN;
1892
47bbea41 1893 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1894 if (ret < 0) {
1895 netdev_warn(dev->net, "Error writing WUCSR\n");
1896 goto done;
1897 }
899a391b 1898 } else {
1e1d7412 1899 netdev_info(dev->net, "disabling packet match detection\n");
47bbea41 1900 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1901 if (ret < 0) {
1902 netdev_warn(dev->net, "Error reading WUCSR\n");
1903 goto done;
1904 }
6c636503 1905
899a391b 1906 val &= ~WUCSR_WUEN;
16c79a04 1907
47bbea41 1908 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1909 if (ret < 0) {
1910 netdev_warn(dev->net, "Error writing WUCSR\n");
1911 goto done;
1912 }
6c636503
SG
1913 }
1914
899a391b 1915 /* disable magic, bcast & unicast wakeup sources */
47bbea41 1916 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1917 if (ret < 0) {
1918 netdev_warn(dev->net, "Error reading WUCSR\n");
1919 goto done;
1920 }
6c636503 1921
899a391b
SG
1922 val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
1923
47bbea41 1924 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1925 if (ret < 0) {
1926 netdev_warn(dev->net, "Error writing WUCSR\n");
1927 goto done;
1928 }
899a391b 1929
f329ccdc
SG
1930 if (pdata->wolopts & WAKE_PHY) {
1931 netdev_info(dev->net, "enabling PHY wakeup\n");
1932
1933 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1934 if (ret < 0) {
1935 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1936 goto done;
1937 }
f329ccdc
SG
1938
1939 /* clear wol status, enable energy detection */
1940 val &= ~PMT_CTL_WUPS;
1941 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1942
1943 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1944 if (ret < 0) {
1945 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1946 goto done;
1947 }
f329ccdc
SG
1948 }
1949
6c636503 1950 if (pdata->wolopts & WAKE_MAGIC) {
1e1d7412 1951 netdev_info(dev->net, "enabling magic packet wakeup\n");
47bbea41 1952 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1953 if (ret < 0) {
1954 netdev_warn(dev->net, "Error reading WUCSR\n");
1955 goto done;
1956 }
899a391b
SG
1957
1958 /* clear any pending magic packet status */
1959 val |= WUCSR_MPR | WUCSR_MPEN;
1960
47bbea41 1961 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1962 if (ret < 0) {
1963 netdev_warn(dev->net, "Error writing WUCSR\n");
1964 goto done;
1965 }
6c636503
SG
1966 }
1967
899a391b 1968 if (pdata->wolopts & WAKE_BCAST) {
1e1d7412 1969 netdev_info(dev->net, "enabling broadcast detection\n");
47bbea41 1970 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1971 if (ret < 0) {
1972 netdev_warn(dev->net, "Error reading WUCSR\n");
1973 goto done;
1974 }
6c636503 1975
899a391b 1976 val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
16c79a04 1977
47bbea41 1978 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1979 if (ret < 0) {
1980 netdev_warn(dev->net, "Error writing WUCSR\n");
1981 goto done;
1982 }
899a391b 1983 }
6c636503 1984
899a391b 1985 if (pdata->wolopts & WAKE_UCAST) {
1e1d7412 1986 netdev_info(dev->net, "enabling unicast detection\n");
47bbea41 1987 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1988 if (ret < 0) {
1989 netdev_warn(dev->net, "Error reading WUCSR\n");
1990 goto done;
1991 }
899a391b
SG
1992
1993 val |= WUCSR_WUFR | WUCSR_PFDA_EN;
6c636503 1994
47bbea41 1995 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1996 if (ret < 0) {
1997 netdev_warn(dev->net, "Error writing WUCSR\n");
1998 goto done;
1999 }
899a391b
SG
2000 }
2001
2002 /* enable receiver to enable frame reception */
47bbea41 2003 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
e3c678e6
SG
2004 if (ret < 0) {
2005 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
2006 goto done;
2007 }
6c636503
SG
2008
2009 val |= MAC_RX_RXEN;
2010
47bbea41 2011 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
e3c678e6
SG
2012 if (ret < 0) {
2013 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
2014 goto done;
2015 }
6c636503
SG
2016
2017 /* some wol options are enabled, so enter SUSPEND0 */
1e1d7412 2018 netdev_info(dev->net, "entering SUSPEND0 mode\n");
eacdd6c2
SG
2019 ret = smsc75xx_enter_suspend0(dev);
2020
2021done:
5410a473
ML
2022 /*
2023 * TODO: resume() might need to handle the suspend failure
2024 * in system sleep
2025 */
2026 if (ret && PMSG_IS_AUTO(message))
eacdd6c2
SG
2027 usbnet_resume(intf);
2028 return ret;
16c79a04
SG
2029}
2030
2031static int smsc75xx_resume(struct usb_interface *intf)
2032{
2033 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 2034 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
b4cdea9c 2035 u8 suspend_flags = pdata->suspend_flags;
16c79a04
SG
2036 int ret;
2037 u32 val;
2038
b4cdea9c 2039 netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
16c79a04 2040
b4cdea9c
SG
2041 /* do this first to ensure it's cleared even in error case */
2042 pdata->suspend_flags = 0;
2043
b4cdea9c 2044 if (suspend_flags & SUSPEND_ALLMODES) {
899a391b 2045 /* Disable wakeup sources */
47bbea41 2046 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
2047 if (ret < 0) {
2048 netdev_warn(dev->net, "Error reading WUCSR\n");
2049 return ret;
2050 }
16c79a04 2051
899a391b
SG
2052 val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
2053 | WUCSR_BCST_EN);
16c79a04 2054
47bbea41 2055 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
2056 if (ret < 0) {
2057 netdev_warn(dev->net, "Error writing WUCSR\n");
2058 return ret;
2059 }
6c636503
SG
2060
2061 /* clear wake-up status */
47bbea41 2062 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2063 if (ret < 0) {
2064 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2065 return ret;
2066 }
6c636503
SG
2067
2068 val &= ~PMT_CTL_WOL_EN;
2069 val |= PMT_CTL_WUPS;
2070
47bbea41 2071 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2072 if (ret < 0) {
2073 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2074 return ret;
2075 }
b4cdea9c
SG
2076 }
2077
2078 if (suspend_flags & SUSPEND_SUSPEND2) {
1e1d7412 2079 netdev_info(dev->net, "resuming from SUSPEND2\n");
6c636503 2080
47bbea41 2081 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2082 if (ret < 0) {
2083 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2084 return ret;
2085 }
6c636503
SG
2086
2087 val |= PMT_CTL_PHY_PWRUP;
2088
47bbea41 2089 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2090 if (ret < 0) {
2091 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2092 return ret;
2093 }
6c636503 2094 }
16c79a04 2095
47bbea41 2096 ret = smsc75xx_wait_ready(dev, 1);
e3c678e6
SG
2097 if (ret < 0) {
2098 netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
2099 return ret;
2100 }
16c79a04
SG
2101
2102 return usbnet_resume(intf);
2103}
2104
78e47fe4
MM
2105static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
2106 u32 rx_cmd_a, u32 rx_cmd_b)
d0cad871 2107{
78e47fe4
MM
2108 if (!(dev->net->features & NETIF_F_RXCSUM) ||
2109 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
d0cad871
SG
2110 skb->ip_summed = CHECKSUM_NONE;
2111 } else {
2112 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
2113 skb->ip_summed = CHECKSUM_COMPLETE;
2114 }
2115}
2116
2117static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
2118{
eb85569f
EG
2119 /* This check is no longer done by usbnet */
2120 if (skb->len < dev->net->hard_header_len)
2121 return 0;
2122
d0cad871
SG
2123 while (skb->len > 0) {
2124 u32 rx_cmd_a, rx_cmd_b, align_count, size;
2125 struct sk_buff *ax_skb;
2126 unsigned char *packet;
2127
2128 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
2129 le32_to_cpus(&rx_cmd_a);
2130 skb_pull(skb, 4);
2131
2132 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
2133 le32_to_cpus(&rx_cmd_b);
ea1649de 2134 skb_pull(skb, 4 + RXW_PADDING);
d0cad871
SG
2135
2136 packet = skb->data;
2137
2138 /* get the packet length */
ea1649de
NE
2139 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
2140 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
d0cad871
SG
2141
2142 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
2143 netif_dbg(dev, rx_err, dev->net,
1e1d7412 2144 "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
d0cad871
SG
2145 dev->net->stats.rx_errors++;
2146 dev->net->stats.rx_dropped++;
2147
2148 if (rx_cmd_a & RX_CMD_A_FCS)
2149 dev->net->stats.rx_crc_errors++;
2150 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
2151 dev->net->stats.rx_frame_errors++;
2152 } else {
4c51e536
SG
2153 /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
2154 if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
d0cad871 2155 netif_dbg(dev, rx_err, dev->net,
1e1d7412
JP
2156 "size err rx_cmd_a=0x%08x\n",
2157 rx_cmd_a);
d0cad871
SG
2158 return 0;
2159 }
2160
2161 /* last frame in this batch */
2162 if (skb->len == size) {
78e47fe4
MM
2163 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
2164 rx_cmd_b);
d0cad871
SG
2165
2166 skb_trim(skb, skb->len - 4); /* remove fcs */
2167 skb->truesize = size + sizeof(struct sk_buff);
2168
2169 return 1;
2170 }
2171
2172 ax_skb = skb_clone(skb, GFP_ATOMIC);
2173 if (unlikely(!ax_skb)) {
1e1d7412 2174 netdev_warn(dev->net, "Error allocating skb\n");
d0cad871
SG
2175 return 0;
2176 }
2177
2178 ax_skb->len = size;
2179 ax_skb->data = packet;
2180 skb_set_tail_pointer(ax_skb, size);
2181
78e47fe4
MM
2182 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
2183 rx_cmd_b);
d0cad871
SG
2184
2185 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
2186 ax_skb->truesize = size + sizeof(struct sk_buff);
2187
2188 usbnet_skb_return(dev, ax_skb);
2189 }
2190
2191 skb_pull(skb, size);
2192
2193 /* padding bytes before the next frame starts */
2194 if (skb->len)
2195 skb_pull(skb, align_count);
2196 }
2197
d0cad871
SG
2198 return 1;
2199}
2200
2201static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
2202 struct sk_buff *skb, gfp_t flags)
2203{
2204 u32 tx_cmd_a, tx_cmd_b;
2205
d0cad871
SG
2206 if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
2207 struct sk_buff *skb2 =
2208 skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
2209 dev_kfree_skb_any(skb);
2210 skb = skb2;
2211 if (!skb)
2212 return NULL;
2213 }
2214
2215 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
2216
2217 if (skb->ip_summed == CHECKSUM_PARTIAL)
2218 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
2219
2220 if (skb_is_gso(skb)) {
2221 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
2222 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
2223
2224 tx_cmd_a |= TX_CMD_A_LSO;
2225 } else {
2226 tx_cmd_b = 0;
2227 }
2228
2229 skb_push(skb, 4);
2230 cpu_to_le32s(&tx_cmd_b);
2231 memcpy(skb->data, &tx_cmd_b, 4);
2232
2233 skb_push(skb, 4);
2234 cpu_to_le32s(&tx_cmd_a);
2235 memcpy(skb->data, &tx_cmd_a, 4);
2236
2237 return skb;
2238}
2239
b4cdea9c
SG
2240static int smsc75xx_manage_power(struct usbnet *dev, int on)
2241{
2242 dev->intf->needs_remote_wakeup = on;
2243 return 0;
2244}
2245
d0cad871
SG
2246static const struct driver_info smsc75xx_info = {
2247 .description = "smsc75xx USB 2.0 Gigabit Ethernet",
2248 .bind = smsc75xx_bind,
2249 .unbind = smsc75xx_unbind,
2250 .link_reset = smsc75xx_link_reset,
2251 .reset = smsc75xx_reset,
2252 .rx_fixup = smsc75xx_rx_fixup,
2253 .tx_fixup = smsc75xx_tx_fixup,
2254 .status = smsc75xx_status,
b4cdea9c 2255 .manage_power = smsc75xx_manage_power,
7bdd305e 2256 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
d0cad871
SG
2257};
2258
2259static const struct usb_device_id products[] = {
2260 {
2261 /* SMSC7500 USB Gigabit Ethernet Device */
2262 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
2263 .driver_info = (unsigned long) &smsc75xx_info,
2264 },
2265 {
2266 /* SMSC7500 USB Gigabit Ethernet Device */
2267 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
2268 .driver_info = (unsigned long) &smsc75xx_info,
2269 },
2270 { }, /* END */
2271};
2272MODULE_DEVICE_TABLE(usb, products);
2273
2274static struct usb_driver smsc75xx_driver = {
2275 .name = SMSC_CHIPNAME,
2276 .id_table = products,
2277 .probe = usbnet_probe,
16c79a04
SG
2278 .suspend = smsc75xx_suspend,
2279 .resume = smsc75xx_resume,
2280 .reset_resume = smsc75xx_resume,
d0cad871 2281 .disconnect = usbnet_disconnect,
e1f12eb6 2282 .disable_hub_initiated_lpm = 1,
b4cdea9c 2283 .supports_autosuspend = 1,
d0cad871
SG
2284};
2285
d632eb1b 2286module_usb_driver(smsc75xx_driver);
d0cad871
SG
2287
2288MODULE_AUTHOR("Nancy Lin");
90b24cfb 2289MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
d0cad871
SG
2290MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
2291MODULE_LICENSE("GPL");
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