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2f7ca802 SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2007-2008 SMSC | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | * | |
19 | *****************************************************************************/ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/kmod.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/ethtool.h> | |
27 | #include <linux/mii.h> | |
28 | #include <linux/usb.h> | |
29 | #include <linux/crc32.h> | |
30 | #include <linux/usb/usbnet.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2f7ca802 SG |
32 | #include "smsc95xx.h" |
33 | ||
34 | #define SMSC_CHIPNAME "smsc95xx" | |
f7b29271 | 35 | #define SMSC_DRIVER_VERSION "1.0.4" |
2f7ca802 SG |
36 | #define HS_USB_PKT_SIZE (512) |
37 | #define FS_USB_PKT_SIZE (64) | |
38 | #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) | |
39 | #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) | |
40 | #define DEFAULT_BULK_IN_DELAY (0x00002000) | |
41 | #define MAX_SINGLE_PACKET_SIZE (2048) | |
42 | #define LAN95XX_EEPROM_MAGIC (0x9500) | |
43 | #define EEPROM_MAC_OFFSET (0x01) | |
f7b29271 | 44 | #define DEFAULT_TX_CSUM_ENABLE (true) |
2f7ca802 SG |
45 | #define DEFAULT_RX_CSUM_ENABLE (true) |
46 | #define SMSC95XX_INTERNAL_PHY_ID (1) | |
47 | #define SMSC95XX_TX_OVERHEAD (8) | |
f7b29271 | 48 | #define SMSC95XX_TX_OVERHEAD_CSUM (12) |
e0e474a8 | 49 | #define SUPPORTED_WAKE (WAKE_MAGIC) |
2f7ca802 | 50 | |
769ea6d8 SG |
51 | #define check_warn(ret, fmt, args...) \ |
52 | ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); }) | |
53 | ||
54 | #define check_warn_return(ret, fmt, args...) \ | |
55 | ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } }) | |
56 | ||
57 | #define check_warn_goto_done(ret, fmt, args...) \ | |
58 | ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } }) | |
59 | ||
2f7ca802 SG |
60 | struct smsc95xx_priv { |
61 | u32 mac_cr; | |
3c0f3c60 MZ |
62 | u32 hash_hi; |
63 | u32 hash_lo; | |
e0e474a8 | 64 | u32 wolopts; |
2f7ca802 | 65 | spinlock_t mac_cr_lock; |
2f7ca802 SG |
66 | }; |
67 | ||
68 | struct usb_context { | |
69 | struct usb_ctrlrequest req; | |
2f7ca802 SG |
70 | struct usbnet *dev; |
71 | }; | |
72 | ||
eb939922 | 73 | static bool turbo_mode = true; |
2f7ca802 SG |
74 | module_param(turbo_mode, bool, 0644); |
75 | MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); | |
76 | ||
769ea6d8 SG |
77 | static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index, |
78 | u32 *data) | |
2f7ca802 SG |
79 | { |
80 | u32 *buf = kmalloc(4, GFP_KERNEL); | |
81 | int ret; | |
82 | ||
83 | BUG_ON(!dev); | |
84 | ||
85 | if (!buf) | |
86 | return -ENOMEM; | |
87 | ||
88 | ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), | |
89 | USB_VENDOR_REQUEST_READ_REGISTER, | |
90 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
91 | 00, index, buf, 4, USB_CTRL_GET_TIMEOUT); | |
92 | ||
93 | if (unlikely(ret < 0)) | |
60b86755 | 94 | netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index); |
2f7ca802 SG |
95 | |
96 | le32_to_cpus(buf); | |
97 | *data = *buf; | |
98 | kfree(buf); | |
99 | ||
100 | return ret; | |
101 | } | |
102 | ||
769ea6d8 SG |
103 | static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index, |
104 | u32 data) | |
2f7ca802 SG |
105 | { |
106 | u32 *buf = kmalloc(4, GFP_KERNEL); | |
107 | int ret; | |
108 | ||
109 | BUG_ON(!dev); | |
110 | ||
111 | if (!buf) | |
112 | return -ENOMEM; | |
113 | ||
114 | *buf = data; | |
115 | cpu_to_le32s(buf); | |
116 | ||
117 | ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), | |
118 | USB_VENDOR_REQUEST_WRITE_REGISTER, | |
119 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
120 | 00, index, buf, 4, USB_CTRL_SET_TIMEOUT); | |
121 | ||
122 | if (unlikely(ret < 0)) | |
60b86755 | 123 | netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index); |
2f7ca802 SG |
124 | |
125 | kfree(buf); | |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
e0e474a8 SG |
130 | static int smsc95xx_set_feature(struct usbnet *dev, u32 feature) |
131 | { | |
132 | if (WARN_ON_ONCE(!dev)) | |
133 | return -EINVAL; | |
134 | ||
135 | cpu_to_le32s(&feature); | |
136 | ||
137 | return usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), | |
138 | USB_REQ_SET_FEATURE, USB_RECIP_DEVICE, feature, 0, NULL, 0, | |
139 | USB_CTRL_SET_TIMEOUT); | |
140 | } | |
141 | ||
142 | static int smsc95xx_clear_feature(struct usbnet *dev, u32 feature) | |
143 | { | |
144 | if (WARN_ON_ONCE(!dev)) | |
145 | return -EINVAL; | |
146 | ||
147 | cpu_to_le32s(&feature); | |
148 | ||
149 | return usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), | |
150 | USB_REQ_CLEAR_FEATURE, USB_RECIP_DEVICE, feature, 0, NULL, 0, | |
151 | USB_CTRL_SET_TIMEOUT); | |
152 | } | |
153 | ||
2f7ca802 SG |
154 | /* Loop until the read is completed with timeout |
155 | * called with phy_mutex held */ | |
769ea6d8 | 156 | static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev) |
2f7ca802 SG |
157 | { |
158 | unsigned long start_time = jiffies; | |
159 | u32 val; | |
769ea6d8 | 160 | int ret; |
2f7ca802 SG |
161 | |
162 | do { | |
769ea6d8 SG |
163 | ret = smsc95xx_read_reg(dev, MII_ADDR, &val); |
164 | check_warn_return(ret, "Error reading MII_ACCESS"); | |
2f7ca802 SG |
165 | if (!(val & MII_BUSY_)) |
166 | return 0; | |
167 | } while (!time_after(jiffies, start_time + HZ)); | |
168 | ||
169 | return -EIO; | |
170 | } | |
171 | ||
172 | static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx) | |
173 | { | |
174 | struct usbnet *dev = netdev_priv(netdev); | |
175 | u32 val, addr; | |
769ea6d8 | 176 | int ret; |
2f7ca802 SG |
177 | |
178 | mutex_lock(&dev->phy_mutex); | |
179 | ||
180 | /* confirm MII not busy */ | |
769ea6d8 SG |
181 | ret = smsc95xx_phy_wait_not_busy(dev); |
182 | check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read"); | |
2f7ca802 SG |
183 | |
184 | /* set the address, index & direction (read from PHY) */ | |
185 | phy_id &= dev->mii.phy_id_mask; | |
186 | idx &= dev->mii.reg_num_mask; | |
187 | addr = (phy_id << 11) | (idx << 6) | MII_READ_; | |
769ea6d8 SG |
188 | ret = smsc95xx_write_reg(dev, MII_ADDR, addr); |
189 | check_warn_goto_done(ret, "Error writing MII_ADDR"); | |
2f7ca802 | 190 | |
769ea6d8 SG |
191 | ret = smsc95xx_phy_wait_not_busy(dev); |
192 | check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx); | |
2f7ca802 | 193 | |
769ea6d8 SG |
194 | ret = smsc95xx_read_reg(dev, MII_DATA, &val); |
195 | check_warn_goto_done(ret, "Error reading MII_DATA"); | |
2f7ca802 | 196 | |
769ea6d8 | 197 | ret = (u16)(val & 0xFFFF); |
2f7ca802 | 198 | |
769ea6d8 SG |
199 | done: |
200 | mutex_unlock(&dev->phy_mutex); | |
201 | return ret; | |
2f7ca802 SG |
202 | } |
203 | ||
204 | static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx, | |
205 | int regval) | |
206 | { | |
207 | struct usbnet *dev = netdev_priv(netdev); | |
208 | u32 val, addr; | |
769ea6d8 | 209 | int ret; |
2f7ca802 SG |
210 | |
211 | mutex_lock(&dev->phy_mutex); | |
212 | ||
213 | /* confirm MII not busy */ | |
769ea6d8 SG |
214 | ret = smsc95xx_phy_wait_not_busy(dev); |
215 | check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write"); | |
2f7ca802 SG |
216 | |
217 | val = regval; | |
769ea6d8 SG |
218 | ret = smsc95xx_write_reg(dev, MII_DATA, val); |
219 | check_warn_goto_done(ret, "Error writing MII_DATA"); | |
2f7ca802 SG |
220 | |
221 | /* set the address, index & direction (write to PHY) */ | |
222 | phy_id &= dev->mii.phy_id_mask; | |
223 | idx &= dev->mii.reg_num_mask; | |
224 | addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; | |
769ea6d8 SG |
225 | ret = smsc95xx_write_reg(dev, MII_ADDR, addr); |
226 | check_warn_goto_done(ret, "Error writing MII_ADDR"); | |
2f7ca802 | 227 | |
769ea6d8 SG |
228 | ret = smsc95xx_phy_wait_not_busy(dev); |
229 | check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx); | |
2f7ca802 | 230 | |
769ea6d8 | 231 | done: |
2f7ca802 SG |
232 | mutex_unlock(&dev->phy_mutex); |
233 | } | |
234 | ||
769ea6d8 | 235 | static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev) |
2f7ca802 SG |
236 | { |
237 | unsigned long start_time = jiffies; | |
238 | u32 val; | |
769ea6d8 | 239 | int ret; |
2f7ca802 SG |
240 | |
241 | do { | |
769ea6d8 SG |
242 | ret = smsc95xx_read_reg(dev, E2P_CMD, &val); |
243 | check_warn_return(ret, "Error reading E2P_CMD"); | |
2f7ca802 SG |
244 | if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) |
245 | break; | |
246 | udelay(40); | |
247 | } while (!time_after(jiffies, start_time + HZ)); | |
248 | ||
249 | if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { | |
60b86755 | 250 | netdev_warn(dev->net, "EEPROM read operation timeout\n"); |
2f7ca802 SG |
251 | return -EIO; |
252 | } | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
769ea6d8 | 257 | static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev) |
2f7ca802 SG |
258 | { |
259 | unsigned long start_time = jiffies; | |
260 | u32 val; | |
769ea6d8 | 261 | int ret; |
2f7ca802 SG |
262 | |
263 | do { | |
769ea6d8 SG |
264 | ret = smsc95xx_read_reg(dev, E2P_CMD, &val); |
265 | check_warn_return(ret, "Error reading E2P_CMD"); | |
2f7ca802 | 266 | |
2f7ca802 SG |
267 | if (!(val & E2P_CMD_BUSY_)) |
268 | return 0; | |
269 | ||
270 | udelay(40); | |
271 | } while (!time_after(jiffies, start_time + HZ)); | |
272 | ||
60b86755 | 273 | netdev_warn(dev->net, "EEPROM is busy\n"); |
2f7ca802 SG |
274 | return -EIO; |
275 | } | |
276 | ||
277 | static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length, | |
278 | u8 *data) | |
279 | { | |
280 | u32 val; | |
281 | int i, ret; | |
282 | ||
283 | BUG_ON(!dev); | |
284 | BUG_ON(!data); | |
285 | ||
286 | ret = smsc95xx_eeprom_confirm_not_busy(dev); | |
287 | if (ret) | |
288 | return ret; | |
289 | ||
290 | for (i = 0; i < length; i++) { | |
291 | val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); | |
769ea6d8 SG |
292 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
293 | check_warn_return(ret, "Error writing E2P_CMD"); | |
2f7ca802 SG |
294 | |
295 | ret = smsc95xx_wait_eeprom(dev); | |
296 | if (ret < 0) | |
297 | return ret; | |
298 | ||
769ea6d8 SG |
299 | ret = smsc95xx_read_reg(dev, E2P_DATA, &val); |
300 | check_warn_return(ret, "Error reading E2P_DATA"); | |
2f7ca802 SG |
301 | |
302 | data[i] = val & 0xFF; | |
303 | offset++; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length, | |
310 | u8 *data) | |
311 | { | |
312 | u32 val; | |
313 | int i, ret; | |
314 | ||
315 | BUG_ON(!dev); | |
316 | BUG_ON(!data); | |
317 | ||
318 | ret = smsc95xx_eeprom_confirm_not_busy(dev); | |
319 | if (ret) | |
320 | return ret; | |
321 | ||
322 | /* Issue write/erase enable command */ | |
323 | val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_; | |
769ea6d8 SG |
324 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
325 | check_warn_return(ret, "Error writing E2P_DATA"); | |
2f7ca802 SG |
326 | |
327 | ret = smsc95xx_wait_eeprom(dev); | |
328 | if (ret < 0) | |
329 | return ret; | |
330 | ||
331 | for (i = 0; i < length; i++) { | |
332 | ||
333 | /* Fill data register */ | |
334 | val = data[i]; | |
769ea6d8 SG |
335 | ret = smsc95xx_write_reg(dev, E2P_DATA, val); |
336 | check_warn_return(ret, "Error writing E2P_DATA"); | |
2f7ca802 SG |
337 | |
338 | /* Send "write" command */ | |
339 | val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_); | |
769ea6d8 SG |
340 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
341 | check_warn_return(ret, "Error writing E2P_CMD"); | |
2f7ca802 SG |
342 | |
343 | ret = smsc95xx_wait_eeprom(dev); | |
344 | if (ret < 0) | |
345 | return ret; | |
346 | ||
347 | offset++; | |
348 | } | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
150a7fcc | 353 | static void smsc95xx_async_cmd_callback(struct urb *urb) |
2f7ca802 SG |
354 | { |
355 | struct usb_context *usb_context = urb->context; | |
356 | struct usbnet *dev = usb_context->dev; | |
c94cb314 | 357 | int status = urb->status; |
2f7ca802 | 358 | |
769ea6d8 | 359 | check_warn(status, "async callback failed with %d\n", status); |
2f7ca802 | 360 | |
2f7ca802 SG |
361 | kfree(usb_context); |
362 | usb_free_urb(urb); | |
363 | } | |
364 | ||
769ea6d8 SG |
365 | static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index, |
366 | u32 *data) | |
2f7ca802 SG |
367 | { |
368 | struct usb_context *usb_context; | |
369 | int status; | |
370 | struct urb *urb; | |
1d74a6bd | 371 | const u16 size = 4; |
2f7ca802 SG |
372 | |
373 | urb = usb_alloc_urb(0, GFP_ATOMIC); | |
374 | if (!urb) { | |
60b86755 | 375 | netdev_warn(dev->net, "Error allocating URB\n"); |
2f7ca802 SG |
376 | return -ENOMEM; |
377 | } | |
378 | ||
379 | usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC); | |
380 | if (usb_context == NULL) { | |
60b86755 | 381 | netdev_warn(dev->net, "Error allocating control msg\n"); |
2f7ca802 SG |
382 | usb_free_urb(urb); |
383 | return -ENOMEM; | |
384 | } | |
385 | ||
386 | usb_context->req.bRequestType = | |
387 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE; | |
388 | usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER; | |
389 | usb_context->req.wValue = 00; | |
1d74a6bd SG |
390 | usb_context->req.wIndex = cpu_to_le16(index); |
391 | usb_context->req.wLength = cpu_to_le16(size); | |
2f7ca802 SG |
392 | |
393 | usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0), | |
394 | (void *)&usb_context->req, data, size, | |
150a7fcc | 395 | smsc95xx_async_cmd_callback, |
2f7ca802 SG |
396 | (void *)usb_context); |
397 | ||
398 | status = usb_submit_urb(urb, GFP_ATOMIC); | |
399 | if (status < 0) { | |
60b86755 JP |
400 | netdev_warn(dev->net, "Error submitting control msg, sts=%d\n", |
401 | status); | |
2f7ca802 SG |
402 | kfree(usb_context); |
403 | usb_free_urb(urb); | |
404 | } | |
405 | ||
406 | return status; | |
407 | } | |
408 | ||
409 | /* returns hash bit number for given MAC address | |
410 | * example: | |
411 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
412 | static unsigned int smsc95xx_hash(char addr[ETH_ALEN]) | |
413 | { | |
414 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
415 | } | |
416 | ||
417 | static void smsc95xx_set_multicast(struct net_device *netdev) | |
418 | { | |
419 | struct usbnet *dev = netdev_priv(netdev); | |
420 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
2f7ca802 | 421 | unsigned long flags; |
769ea6d8 | 422 | int ret; |
2f7ca802 | 423 | |
3c0f3c60 MZ |
424 | pdata->hash_hi = 0; |
425 | pdata->hash_lo = 0; | |
426 | ||
2f7ca802 SG |
427 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); |
428 | ||
429 | if (dev->net->flags & IFF_PROMISC) { | |
a475f603 | 430 | netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n"); |
2f7ca802 SG |
431 | pdata->mac_cr |= MAC_CR_PRMS_; |
432 | pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
433 | } else if (dev->net->flags & IFF_ALLMULTI) { | |
a475f603 | 434 | netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n"); |
2f7ca802 SG |
435 | pdata->mac_cr |= MAC_CR_MCPAS_; |
436 | pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
4cd24eaf | 437 | } else if (!netdev_mc_empty(dev->net)) { |
22bedad3 | 438 | struct netdev_hw_addr *ha; |
2f7ca802 SG |
439 | |
440 | pdata->mac_cr |= MAC_CR_HPFILT_; | |
441 | pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
442 | ||
22bedad3 JP |
443 | netdev_for_each_mc_addr(ha, netdev) { |
444 | u32 bitnum = smsc95xx_hash(ha->addr); | |
a92635dc JP |
445 | u32 mask = 0x01 << (bitnum & 0x1F); |
446 | if (bitnum & 0x20) | |
3c0f3c60 | 447 | pdata->hash_hi |= mask; |
a92635dc | 448 | else |
3c0f3c60 | 449 | pdata->hash_lo |= mask; |
2f7ca802 SG |
450 | } |
451 | ||
a475f603 | 452 | netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n", |
3c0f3c60 | 453 | pdata->hash_hi, pdata->hash_lo); |
2f7ca802 | 454 | } else { |
a475f603 | 455 | netif_dbg(dev, drv, dev->net, "receive own packets only\n"); |
2f7ca802 SG |
456 | pdata->mac_cr &= |
457 | ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
458 | } | |
459 | ||
460 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
461 | ||
462 | /* Initiate async writes, as we can't wait for completion here */ | |
769ea6d8 SG |
463 | ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi); |
464 | check_warn(ret, "failed to initiate async write to HASHH"); | |
465 | ||
466 | ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo); | |
467 | check_warn(ret, "failed to initiate async write to HASHL"); | |
468 | ||
469 | ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr); | |
470 | check_warn(ret, "failed to initiate async write to MAC_CR"); | |
2f7ca802 SG |
471 | } |
472 | ||
769ea6d8 SG |
473 | static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex, |
474 | u16 lcladv, u16 rmtadv) | |
2f7ca802 SG |
475 | { |
476 | u32 flow, afc_cfg = 0; | |
477 | ||
478 | int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg); | |
769ea6d8 | 479 | check_warn_return(ret, "Error reading AFC_CFG"); |
2f7ca802 SG |
480 | |
481 | if (duplex == DUPLEX_FULL) { | |
bc02ff95 | 482 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
2f7ca802 SG |
483 | |
484 | if (cap & FLOW_CTRL_RX) | |
485 | flow = 0xFFFF0002; | |
486 | else | |
487 | flow = 0; | |
488 | ||
489 | if (cap & FLOW_CTRL_TX) | |
490 | afc_cfg |= 0xF; | |
491 | else | |
492 | afc_cfg &= ~0xF; | |
493 | ||
a475f603 | 494 | netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n", |
60b86755 JP |
495 | cap & FLOW_CTRL_RX ? "enabled" : "disabled", |
496 | cap & FLOW_CTRL_TX ? "enabled" : "disabled"); | |
2f7ca802 | 497 | } else { |
a475f603 | 498 | netif_dbg(dev, link, dev->net, "half duplex\n"); |
2f7ca802 SG |
499 | flow = 0; |
500 | afc_cfg |= 0xF; | |
501 | } | |
502 | ||
769ea6d8 SG |
503 | ret = smsc95xx_write_reg(dev, FLOW, flow); |
504 | check_warn_return(ret, "Error writing FLOW"); | |
505 | ||
506 | ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg); | |
507 | check_warn_return(ret, "Error writing AFC_CFG"); | |
508 | ||
509 | return 0; | |
2f7ca802 SG |
510 | } |
511 | ||
512 | static int smsc95xx_link_reset(struct usbnet *dev) | |
513 | { | |
514 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
515 | struct mii_if_info *mii = &dev->mii; | |
8ae6daca | 516 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
2f7ca802 SG |
517 | unsigned long flags; |
518 | u16 lcladv, rmtadv; | |
769ea6d8 | 519 | int ret; |
2f7ca802 SG |
520 | |
521 | /* clear interrupt status */ | |
769ea6d8 SG |
522 | ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC); |
523 | check_warn_return(ret, "Error reading PHY_INT_SRC"); | |
524 | ||
525 | ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); | |
526 | check_warn_return(ret, "Error writing INT_STS"); | |
2f7ca802 SG |
527 | |
528 | mii_check_media(mii, 1, 1); | |
529 | mii_ethtool_gset(&dev->mii, &ecmd); | |
530 | lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE); | |
531 | rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA); | |
532 | ||
8ae6daca DD |
533 | netif_dbg(dev, link, dev->net, |
534 | "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n", | |
535 | ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv); | |
2f7ca802 SG |
536 | |
537 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
538 | if (ecmd.duplex != DUPLEX_FULL) { | |
539 | pdata->mac_cr &= ~MAC_CR_FDPX_; | |
540 | pdata->mac_cr |= MAC_CR_RCVOWN_; | |
541 | } else { | |
542 | pdata->mac_cr &= ~MAC_CR_RCVOWN_; | |
543 | pdata->mac_cr |= MAC_CR_FDPX_; | |
544 | } | |
545 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
546 | ||
769ea6d8 SG |
547 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
548 | check_warn_return(ret, "Error writing MAC_CR"); | |
2f7ca802 | 549 | |
769ea6d8 SG |
550 | ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv); |
551 | check_warn_return(ret, "Error updating PHY flow control"); | |
2f7ca802 SG |
552 | |
553 | return 0; | |
554 | } | |
555 | ||
556 | static void smsc95xx_status(struct usbnet *dev, struct urb *urb) | |
557 | { | |
558 | u32 intdata; | |
559 | ||
560 | if (urb->actual_length != 4) { | |
60b86755 JP |
561 | netdev_warn(dev->net, "unexpected urb length %d\n", |
562 | urb->actual_length); | |
2f7ca802 SG |
563 | return; |
564 | } | |
565 | ||
566 | memcpy(&intdata, urb->transfer_buffer, 4); | |
1d74a6bd | 567 | le32_to_cpus(&intdata); |
2f7ca802 | 568 | |
a475f603 | 569 | netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata); |
2f7ca802 SG |
570 | |
571 | if (intdata & INT_ENP_PHY_INT_) | |
572 | usbnet_defer_kevent(dev, EVENT_LINK_RESET); | |
573 | else | |
60b86755 JP |
574 | netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n", |
575 | intdata); | |
2f7ca802 SG |
576 | } |
577 | ||
f7b29271 | 578 | /* Enable or disable Tx & Rx checksum offload engines */ |
c8f44aff MM |
579 | static int smsc95xx_set_features(struct net_device *netdev, |
580 | netdev_features_t features) | |
2f7ca802 | 581 | { |
78e47fe4 | 582 | struct usbnet *dev = netdev_priv(netdev); |
2f7ca802 | 583 | u32 read_buf; |
78e47fe4 MM |
584 | int ret; |
585 | ||
586 | ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); | |
769ea6d8 | 587 | check_warn_return(ret, "Failed to read COE_CR: %d\n", ret); |
2f7ca802 | 588 | |
78e47fe4 | 589 | if (features & NETIF_F_HW_CSUM) |
f7b29271 SG |
590 | read_buf |= Tx_COE_EN_; |
591 | else | |
592 | read_buf &= ~Tx_COE_EN_; | |
593 | ||
78e47fe4 | 594 | if (features & NETIF_F_RXCSUM) |
2f7ca802 SG |
595 | read_buf |= Rx_COE_EN_; |
596 | else | |
597 | read_buf &= ~Rx_COE_EN_; | |
598 | ||
599 | ret = smsc95xx_write_reg(dev, COE_CR, read_buf); | |
769ea6d8 | 600 | check_warn_return(ret, "Failed to write COE_CR: %d\n", ret); |
2f7ca802 | 601 | |
a475f603 | 602 | netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf); |
2f7ca802 SG |
603 | return 0; |
604 | } | |
605 | ||
606 | static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net) | |
607 | { | |
608 | return MAX_EEPROM_SIZE; | |
609 | } | |
610 | ||
611 | static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev, | |
612 | struct ethtool_eeprom *ee, u8 *data) | |
613 | { | |
614 | struct usbnet *dev = netdev_priv(netdev); | |
615 | ||
616 | ee->magic = LAN95XX_EEPROM_MAGIC; | |
617 | ||
618 | return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data); | |
619 | } | |
620 | ||
621 | static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev, | |
622 | struct ethtool_eeprom *ee, u8 *data) | |
623 | { | |
624 | struct usbnet *dev = netdev_priv(netdev); | |
625 | ||
626 | if (ee->magic != LAN95XX_EEPROM_MAGIC) { | |
60b86755 JP |
627 | netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n", |
628 | ee->magic); | |
2f7ca802 SG |
629 | return -EINVAL; |
630 | } | |
631 | ||
632 | return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data); | |
633 | } | |
634 | ||
9fa32e94 EV |
635 | static int smsc95xx_ethtool_getregslen(struct net_device *netdev) |
636 | { | |
637 | /* all smsc95xx registers */ | |
638 | return COE_CR - ID_REV + 1; | |
639 | } | |
640 | ||
641 | static void | |
642 | smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs, | |
643 | void *buf) | |
644 | { | |
645 | struct usbnet *dev = netdev_priv(netdev); | |
d348446b DC |
646 | unsigned int i, j; |
647 | int retval; | |
9fa32e94 EV |
648 | u32 *data = buf; |
649 | ||
650 | retval = smsc95xx_read_reg(dev, ID_REV, ®s->version); | |
651 | if (retval < 0) { | |
652 | netdev_warn(netdev, "REGS: cannot read ID_REV\n"); | |
653 | return; | |
654 | } | |
655 | ||
656 | for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) { | |
657 | retval = smsc95xx_read_reg(dev, i, &data[j]); | |
658 | if (retval < 0) { | |
659 | netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i); | |
660 | return; | |
661 | } | |
662 | } | |
663 | } | |
664 | ||
e0e474a8 SG |
665 | static void smsc95xx_ethtool_get_wol(struct net_device *net, |
666 | struct ethtool_wolinfo *wolinfo) | |
667 | { | |
668 | struct usbnet *dev = netdev_priv(net); | |
669 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
670 | ||
671 | wolinfo->supported = SUPPORTED_WAKE; | |
672 | wolinfo->wolopts = pdata->wolopts; | |
673 | } | |
674 | ||
675 | static int smsc95xx_ethtool_set_wol(struct net_device *net, | |
676 | struct ethtool_wolinfo *wolinfo) | |
677 | { | |
678 | struct usbnet *dev = netdev_priv(net); | |
679 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
680 | ||
681 | pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE; | |
682 | return 0; | |
683 | } | |
684 | ||
0fc0b732 | 685 | static const struct ethtool_ops smsc95xx_ethtool_ops = { |
2f7ca802 SG |
686 | .get_link = usbnet_get_link, |
687 | .nway_reset = usbnet_nway_reset, | |
688 | .get_drvinfo = usbnet_get_drvinfo, | |
689 | .get_msglevel = usbnet_get_msglevel, | |
690 | .set_msglevel = usbnet_set_msglevel, | |
691 | .get_settings = usbnet_get_settings, | |
692 | .set_settings = usbnet_set_settings, | |
693 | .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len, | |
694 | .get_eeprom = smsc95xx_ethtool_get_eeprom, | |
695 | .set_eeprom = smsc95xx_ethtool_set_eeprom, | |
9fa32e94 EV |
696 | .get_regs_len = smsc95xx_ethtool_getregslen, |
697 | .get_regs = smsc95xx_ethtool_getregs, | |
e0e474a8 SG |
698 | .get_wol = smsc95xx_ethtool_get_wol, |
699 | .set_wol = smsc95xx_ethtool_set_wol, | |
2f7ca802 SG |
700 | }; |
701 | ||
702 | static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
703 | { | |
704 | struct usbnet *dev = netdev_priv(netdev); | |
705 | ||
706 | if (!netif_running(netdev)) | |
707 | return -EINVAL; | |
708 | ||
709 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
710 | } | |
711 | ||
712 | static void smsc95xx_init_mac_address(struct usbnet *dev) | |
713 | { | |
714 | /* try reading mac address from EEPROM */ | |
715 | if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, | |
716 | dev->net->dev_addr) == 0) { | |
717 | if (is_valid_ether_addr(dev->net->dev_addr)) { | |
718 | /* eeprom values are valid so use them */ | |
a475f603 | 719 | netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n"); |
2f7ca802 SG |
720 | return; |
721 | } | |
722 | } | |
723 | ||
724 | /* no eeprom, or eeprom values are invalid. generate random MAC */ | |
f2cedb63 | 725 | eth_hw_addr_random(dev->net); |
c7e12ead | 726 | netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n"); |
2f7ca802 SG |
727 | } |
728 | ||
729 | static int smsc95xx_set_mac_address(struct usbnet *dev) | |
730 | { | |
731 | u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 | | |
732 | dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24; | |
733 | u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8; | |
734 | int ret; | |
735 | ||
736 | ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); | |
769ea6d8 | 737 | check_warn_return(ret, "Failed to write ADDRL: %d\n", ret); |
2f7ca802 SG |
738 | |
739 | ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); | |
769ea6d8 | 740 | check_warn_return(ret, "Failed to write ADDRH: %d\n", ret); |
2f7ca802 SG |
741 | |
742 | return 0; | |
743 | } | |
744 | ||
745 | /* starts the TX path */ | |
769ea6d8 | 746 | static int smsc95xx_start_tx_path(struct usbnet *dev) |
2f7ca802 SG |
747 | { |
748 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
749 | unsigned long flags; | |
769ea6d8 | 750 | int ret; |
2f7ca802 SG |
751 | |
752 | /* Enable Tx at MAC */ | |
753 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
754 | pdata->mac_cr |= MAC_CR_TXEN_; | |
755 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
756 | ||
769ea6d8 SG |
757 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
758 | check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); | |
2f7ca802 SG |
759 | |
760 | /* Enable Tx at SCSRs */ | |
769ea6d8 SG |
761 | ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_); |
762 | check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret); | |
763 | ||
764 | return 0; | |
2f7ca802 SG |
765 | } |
766 | ||
767 | /* Starts the Receive path */ | |
769ea6d8 | 768 | static int smsc95xx_start_rx_path(struct usbnet *dev) |
2f7ca802 SG |
769 | { |
770 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
771 | unsigned long flags; | |
769ea6d8 | 772 | int ret; |
2f7ca802 SG |
773 | |
774 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
775 | pdata->mac_cr |= MAC_CR_RXEN_; | |
776 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
777 | ||
769ea6d8 SG |
778 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
779 | check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); | |
780 | ||
781 | return 0; | |
2f7ca802 SG |
782 | } |
783 | ||
784 | static int smsc95xx_phy_initialize(struct usbnet *dev) | |
785 | { | |
769ea6d8 | 786 | int bmcr, ret, timeout = 0; |
db443c44 | 787 | |
2f7ca802 SG |
788 | /* Initialize MII structure */ |
789 | dev->mii.dev = dev->net; | |
790 | dev->mii.mdio_read = smsc95xx_mdio_read; | |
791 | dev->mii.mdio_write = smsc95xx_mdio_write; | |
792 | dev->mii.phy_id_mask = 0x1f; | |
793 | dev->mii.reg_num_mask = 0x1f; | |
794 | dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID; | |
795 | ||
db443c44 | 796 | /* reset phy and wait for reset to complete */ |
2f7ca802 | 797 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
db443c44 SG |
798 | |
799 | do { | |
800 | msleep(10); | |
801 | bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR); | |
802 | timeout++; | |
d9460920 | 803 | } while ((bmcr & BMCR_RESET) && (timeout < 100)); |
db443c44 SG |
804 | |
805 | if (timeout >= 100) { | |
806 | netdev_warn(dev->net, "timeout on PHY Reset"); | |
807 | return -EIO; | |
808 | } | |
809 | ||
2f7ca802 SG |
810 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, |
811 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | | |
812 | ADVERTISE_PAUSE_ASYM); | |
813 | ||
814 | /* read to clear */ | |
769ea6d8 SG |
815 | ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC); |
816 | check_warn_return(ret, "Failed to read PHY_INT_SRC during init"); | |
2f7ca802 SG |
817 | |
818 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK, | |
819 | PHY_INT_MASK_DEFAULT_); | |
820 | mii_nway_restart(&dev->mii); | |
821 | ||
a475f603 | 822 | netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n"); |
2f7ca802 SG |
823 | return 0; |
824 | } | |
825 | ||
826 | static int smsc95xx_reset(struct usbnet *dev) | |
827 | { | |
828 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
829 | u32 read_buf, write_buf, burst_cap; | |
830 | int ret = 0, timeout; | |
2f7ca802 | 831 | |
a475f603 | 832 | netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n"); |
2f7ca802 | 833 | |
4436761b | 834 | ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_); |
769ea6d8 | 835 | check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n"); |
2f7ca802 SG |
836 | |
837 | timeout = 0; | |
838 | do { | |
cf2acec2 | 839 | msleep(10); |
2f7ca802 | 840 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); |
769ea6d8 | 841 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
2f7ca802 SG |
842 | timeout++; |
843 | } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); | |
844 | ||
845 | if (timeout >= 100) { | |
60b86755 | 846 | netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n"); |
2f7ca802 SG |
847 | return ret; |
848 | } | |
849 | ||
4436761b | 850 | ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); |
769ea6d8 | 851 | check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret); |
2f7ca802 SG |
852 | |
853 | timeout = 0; | |
854 | do { | |
cf2acec2 | 855 | msleep(10); |
2f7ca802 | 856 | ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); |
769ea6d8 | 857 | check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret); |
2f7ca802 SG |
858 | timeout++; |
859 | } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); | |
860 | ||
861 | if (timeout >= 100) { | |
60b86755 | 862 | netdev_warn(dev->net, "timeout waiting for PHY Reset\n"); |
2f7ca802 SG |
863 | return ret; |
864 | } | |
865 | ||
2f7ca802 SG |
866 | ret = smsc95xx_set_mac_address(dev); |
867 | if (ret < 0) | |
868 | return ret; | |
869 | ||
a475f603 JP |
870 | netif_dbg(dev, ifup, dev->net, |
871 | "MAC Address: %pM\n", dev->net->dev_addr); | |
2f7ca802 SG |
872 | |
873 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 | 874 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
2f7ca802 | 875 | |
a475f603 JP |
876 | netif_dbg(dev, ifup, dev->net, |
877 | "Read Value from HW_CFG : 0x%08x\n", read_buf); | |
2f7ca802 SG |
878 | |
879 | read_buf |= HW_CFG_BIR_; | |
880 | ||
881 | ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); | |
769ea6d8 | 882 | check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n"); |
2f7ca802 SG |
883 | |
884 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 | 885 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
a475f603 JP |
886 | netif_dbg(dev, ifup, dev->net, |
887 | "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n", | |
888 | read_buf); | |
2f7ca802 SG |
889 | |
890 | if (!turbo_mode) { | |
891 | burst_cap = 0; | |
892 | dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; | |
893 | } else if (dev->udev->speed == USB_SPEED_HIGH) { | |
894 | burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; | |
895 | dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; | |
896 | } else { | |
897 | burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; | |
898 | dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; | |
899 | } | |
900 | ||
a475f603 JP |
901 | netif_dbg(dev, ifup, dev->net, |
902 | "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size); | |
2f7ca802 SG |
903 | |
904 | ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); | |
769ea6d8 | 905 | check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret); |
2f7ca802 SG |
906 | |
907 | ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); | |
769ea6d8 SG |
908 | check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret); |
909 | ||
a475f603 JP |
910 | netif_dbg(dev, ifup, dev->net, |
911 | "Read Value from BURST_CAP after writing: 0x%08x\n", | |
912 | read_buf); | |
2f7ca802 | 913 | |
4436761b | 914 | ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); |
769ea6d8 | 915 | check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret); |
2f7ca802 SG |
916 | |
917 | ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); | |
769ea6d8 SG |
918 | check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret); |
919 | ||
a475f603 JP |
920 | netif_dbg(dev, ifup, dev->net, |
921 | "Read Value from BULK_IN_DLY after writing: 0x%08x\n", | |
922 | read_buf); | |
2f7ca802 SG |
923 | |
924 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 SG |
925 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
926 | ||
a475f603 JP |
927 | netif_dbg(dev, ifup, dev->net, |
928 | "Read Value from HW_CFG: 0x%08x\n", read_buf); | |
2f7ca802 SG |
929 | |
930 | if (turbo_mode) | |
931 | read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); | |
932 | ||
933 | read_buf &= ~HW_CFG_RXDOFF_; | |
934 | ||
935 | /* set Rx data offset=2, Make IP header aligns on word boundary. */ | |
936 | read_buf |= NET_IP_ALIGN << 9; | |
937 | ||
938 | ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); | |
769ea6d8 | 939 | check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret); |
2f7ca802 SG |
940 | |
941 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 SG |
942 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
943 | ||
a475f603 JP |
944 | netif_dbg(dev, ifup, dev->net, |
945 | "Read Value from HW_CFG after writing: 0x%08x\n", read_buf); | |
2f7ca802 | 946 | |
4436761b | 947 | ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); |
769ea6d8 | 948 | check_warn_return(ret, "Failed to write INT_STS: %d\n", ret); |
2f7ca802 SG |
949 | |
950 | ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); | |
769ea6d8 | 951 | check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); |
a475f603 | 952 | netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf); |
2f7ca802 | 953 | |
f293501c SG |
954 | /* Configure GPIO pins as LED outputs */ |
955 | write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | | |
956 | LED_GPIO_CFG_FDX_LED; | |
957 | ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf); | |
769ea6d8 | 958 | check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret); |
f293501c | 959 | |
2f7ca802 | 960 | /* Init Tx */ |
4436761b | 961 | ret = smsc95xx_write_reg(dev, FLOW, 0); |
769ea6d8 | 962 | check_warn_return(ret, "Failed to write FLOW: %d\n", ret); |
2f7ca802 | 963 | |
4436761b | 964 | ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT); |
769ea6d8 | 965 | check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret); |
2f7ca802 SG |
966 | |
967 | /* Don't need mac_cr_lock during initialisation */ | |
968 | ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr); | |
769ea6d8 | 969 | check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret); |
2f7ca802 SG |
970 | |
971 | /* Init Rx */ | |
972 | /* Set Vlan */ | |
4436761b | 973 | ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q); |
769ea6d8 | 974 | check_warn_return(ret, "Failed to write VLAN1: %d\n", ret); |
2f7ca802 | 975 | |
f7b29271 | 976 | /* Enable or disable checksum offload engines */ |
769ea6d8 SG |
977 | ret = smsc95xx_set_features(dev->net, dev->net->features); |
978 | check_warn_return(ret, "Failed to set checksum offload features"); | |
2f7ca802 SG |
979 | |
980 | smsc95xx_set_multicast(dev->net); | |
981 | ||
769ea6d8 SG |
982 | ret = smsc95xx_phy_initialize(dev); |
983 | check_warn_return(ret, "Failed to init PHY"); | |
2f7ca802 SG |
984 | |
985 | ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); | |
769ea6d8 | 986 | check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret); |
2f7ca802 SG |
987 | |
988 | /* enable PHY interrupts */ | |
989 | read_buf |= INT_EP_CTL_PHY_INT_; | |
990 | ||
991 | ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); | |
769ea6d8 | 992 | check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret); |
2f7ca802 | 993 | |
769ea6d8 SG |
994 | ret = smsc95xx_start_tx_path(dev); |
995 | check_warn_return(ret, "Failed to start TX path"); | |
996 | ||
997 | ret = smsc95xx_start_rx_path(dev); | |
998 | check_warn_return(ret, "Failed to start RX path"); | |
2f7ca802 | 999 | |
a475f603 | 1000 | netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n"); |
2f7ca802 SG |
1001 | return 0; |
1002 | } | |
1003 | ||
63e77b39 SH |
1004 | static const struct net_device_ops smsc95xx_netdev_ops = { |
1005 | .ndo_open = usbnet_open, | |
1006 | .ndo_stop = usbnet_stop, | |
1007 | .ndo_start_xmit = usbnet_start_xmit, | |
1008 | .ndo_tx_timeout = usbnet_tx_timeout, | |
1009 | .ndo_change_mtu = usbnet_change_mtu, | |
1010 | .ndo_set_mac_address = eth_mac_addr, | |
1011 | .ndo_validate_addr = eth_validate_addr, | |
1012 | .ndo_do_ioctl = smsc95xx_ioctl, | |
afc4b13d | 1013 | .ndo_set_rx_mode = smsc95xx_set_multicast, |
78e47fe4 | 1014 | .ndo_set_features = smsc95xx_set_features, |
63e77b39 SH |
1015 | }; |
1016 | ||
2f7ca802 SG |
1017 | static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf) |
1018 | { | |
1019 | struct smsc95xx_priv *pdata = NULL; | |
1020 | int ret; | |
1021 | ||
1022 | printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n"); | |
1023 | ||
1024 | ret = usbnet_get_endpoints(dev, intf); | |
769ea6d8 | 1025 | check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret); |
2f7ca802 SG |
1026 | |
1027 | dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv), | |
1028 | GFP_KERNEL); | |
1029 | ||
1030 | pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1031 | if (!pdata) { | |
60b86755 | 1032 | netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n"); |
2f7ca802 SG |
1033 | return -ENOMEM; |
1034 | } | |
1035 | ||
1036 | spin_lock_init(&pdata->mac_cr_lock); | |
1037 | ||
78e47fe4 MM |
1038 | if (DEFAULT_TX_CSUM_ENABLE) |
1039 | dev->net->features |= NETIF_F_HW_CSUM; | |
1040 | if (DEFAULT_RX_CSUM_ENABLE) | |
1041 | dev->net->features |= NETIF_F_RXCSUM; | |
1042 | ||
1043 | dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM; | |
2f7ca802 | 1044 | |
f4e8ab7c BB |
1045 | smsc95xx_init_mac_address(dev); |
1046 | ||
2f7ca802 SG |
1047 | /* Init all registers */ |
1048 | ret = smsc95xx_reset(dev); | |
1049 | ||
63e77b39 | 1050 | dev->net->netdev_ops = &smsc95xx_netdev_ops; |
2f7ca802 | 1051 | dev->net->ethtool_ops = &smsc95xx_ethtool_ops; |
2f7ca802 | 1052 | dev->net->flags |= IFF_MULTICAST; |
78e47fe4 | 1053 | dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM; |
9bbf5660 | 1054 | dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; |
2f7ca802 SG |
1055 | return 0; |
1056 | } | |
1057 | ||
1058 | static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf) | |
1059 | { | |
1060 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1061 | if (pdata) { | |
a475f603 | 1062 | netif_dbg(dev, ifdown, dev->net, "free pdata\n"); |
2f7ca802 SG |
1063 | kfree(pdata); |
1064 | pdata = NULL; | |
1065 | dev->data[0] = 0; | |
1066 | } | |
1067 | } | |
1068 | ||
b5a04475 SG |
1069 | static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message) |
1070 | { | |
1071 | struct usbnet *dev = usb_get_intfdata(intf); | |
e0e474a8 | 1072 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); |
b5a04475 SG |
1073 | int ret; |
1074 | u32 val; | |
1075 | ||
b5a04475 SG |
1076 | ret = usbnet_suspend(intf, message); |
1077 | check_warn_return(ret, "usbnet_suspend error"); | |
1078 | ||
e0e474a8 SG |
1079 | /* if no wol options set, enter lowest power SUSPEND2 mode */ |
1080 | if (!(pdata->wolopts & SUPPORTED_WAKE)) { | |
1081 | netdev_info(dev->net, "entering SUSPEND2 mode"); | |
1082 | ||
1083 | /* disable energy detect (link up) & wake up events */ | |
1084 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1085 | check_warn_return(ret, "Error reading WUCSR"); | |
1086 | ||
1087 | val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_); | |
1088 | ||
1089 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1090 | check_warn_return(ret, "Error writing WUCSR"); | |
1091 | ||
1092 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1093 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1094 | ||
1095 | val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_); | |
1096 | ||
1097 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1098 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1099 | ||
1100 | /* enter suspend2 mode */ | |
1101 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1102 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1103 | ||
1104 | val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); | |
1105 | val |= PM_CTL_SUS_MODE_2; | |
1106 | ||
1107 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1108 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | if (pdata->wolopts & WAKE_MAGIC) { | |
1114 | /* clear any pending magic packet status */ | |
1115 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1116 | check_warn_return(ret, "Error reading WUCSR"); | |
1117 | ||
1118 | val |= WUCSR_MPR_; | |
1119 | ||
1120 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1121 | check_warn_return(ret, "Error writing WUCSR"); | |
1122 | } | |
1123 | ||
1124 | /* enable/disable magic packup wake */ | |
1125 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1126 | check_warn_return(ret, "Error reading WUCSR"); | |
1127 | ||
1128 | if (pdata->wolopts & WAKE_MAGIC) { | |
1129 | netdev_info(dev->net, "enabling magic packet wakeup"); | |
1130 | val |= WUCSR_MPEN_; | |
1131 | } else { | |
1132 | netdev_info(dev->net, "disabling magic packet wakeup"); | |
1133 | val &= ~WUCSR_MPEN_; | |
1134 | } | |
1135 | ||
1136 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1137 | check_warn_return(ret, "Error writing WUCSR"); | |
1138 | ||
1139 | /* enable wol wakeup source */ | |
1140 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1141 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1142 | ||
1143 | val |= PM_CTL_WOL_EN_; | |
1144 | ||
1145 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1146 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1147 | ||
1148 | /* enable receiver */ | |
1149 | smsc95xx_start_rx_path(dev); | |
1150 | ||
1151 | /* some wol options are enabled, so enter SUSPEND0 */ | |
1152 | netdev_info(dev->net, "entering SUSPEND0 mode"); | |
b5a04475 SG |
1153 | |
1154 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1155 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1156 | ||
e0e474a8 SG |
1157 | val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_)); |
1158 | val |= PM_CTL_SUS_MODE_0; | |
b5a04475 SG |
1159 | |
1160 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1161 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1162 | ||
e0e474a8 SG |
1163 | /* clear wol status */ |
1164 | val &= ~PM_CTL_WUPS_; | |
1165 | val |= PM_CTL_WUPS_WOL_; | |
1166 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1167 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1168 | ||
1169 | /* read back PM_CTRL */ | |
1170 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1171 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1172 | ||
1173 | smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP); | |
1174 | ||
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | static int smsc95xx_resume(struct usb_interface *intf) | |
1179 | { | |
1180 | struct usbnet *dev = usb_get_intfdata(intf); | |
1181 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1182 | int ret; | |
1183 | u32 val; | |
1184 | ||
1185 | BUG_ON(!dev); | |
1186 | ||
1187 | if (pdata->wolopts & WAKE_MAGIC) { | |
1188 | smsc95xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP); | |
1189 | ||
1190 | /* Disable magic packup wake */ | |
1191 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1192 | check_warn_return(ret, "Error reading WUCSR"); | |
1193 | ||
1194 | val &= ~WUCSR_MPEN_; | |
1195 | ||
1196 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1197 | check_warn_return(ret, "Error writing WUCSR"); | |
1198 | ||
1199 | /* clear wake-up status */ | |
1200 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1201 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1202 | ||
1203 | val &= ~PM_CTL_WOL_EN_; | |
1204 | val |= PM_CTL_WUPS_; | |
1205 | ||
1206 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1207 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1208 | } | |
1209 | ||
1210 | return usbnet_resume(intf); | |
1211 | check_warn_return(ret, "usbnet_resume error"); | |
1212 | ||
b5a04475 SG |
1213 | return 0; |
1214 | } | |
1215 | ||
2f7ca802 SG |
1216 | static void smsc95xx_rx_csum_offload(struct sk_buff *skb) |
1217 | { | |
1218 | skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2); | |
1219 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1220 | skb_trim(skb, skb->len - 2); | |
1221 | } | |
1222 | ||
1223 | static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
1224 | { | |
2f7ca802 SG |
1225 | while (skb->len > 0) { |
1226 | u32 header, align_count; | |
1227 | struct sk_buff *ax_skb; | |
1228 | unsigned char *packet; | |
1229 | u16 size; | |
1230 | ||
1231 | memcpy(&header, skb->data, sizeof(header)); | |
1232 | le32_to_cpus(&header); | |
1233 | skb_pull(skb, 4 + NET_IP_ALIGN); | |
1234 | packet = skb->data; | |
1235 | ||
1236 | /* get the packet length */ | |
1237 | size = (u16)((header & RX_STS_FL_) >> 16); | |
1238 | align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4; | |
1239 | ||
1240 | if (unlikely(header & RX_STS_ES_)) { | |
a475f603 JP |
1241 | netif_dbg(dev, rx_err, dev->net, |
1242 | "Error header=0x%08x\n", header); | |
80667ac1 HX |
1243 | dev->net->stats.rx_errors++; |
1244 | dev->net->stats.rx_dropped++; | |
2f7ca802 SG |
1245 | |
1246 | if (header & RX_STS_CRC_) { | |
80667ac1 | 1247 | dev->net->stats.rx_crc_errors++; |
2f7ca802 SG |
1248 | } else { |
1249 | if (header & (RX_STS_TL_ | RX_STS_RF_)) | |
80667ac1 | 1250 | dev->net->stats.rx_frame_errors++; |
2f7ca802 SG |
1251 | |
1252 | if ((header & RX_STS_LE_) && | |
1253 | (!(header & RX_STS_FT_))) | |
80667ac1 | 1254 | dev->net->stats.rx_length_errors++; |
2f7ca802 SG |
1255 | } |
1256 | } else { | |
1257 | /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */ | |
1258 | if (unlikely(size > (ETH_FRAME_LEN + 12))) { | |
a475f603 JP |
1259 | netif_dbg(dev, rx_err, dev->net, |
1260 | "size err header=0x%08x\n", header); | |
2f7ca802 SG |
1261 | return 0; |
1262 | } | |
1263 | ||
1264 | /* last frame in this batch */ | |
1265 | if (skb->len == size) { | |
78e47fe4 | 1266 | if (dev->net->features & NETIF_F_RXCSUM) |
2f7ca802 | 1267 | smsc95xx_rx_csum_offload(skb); |
df18acca | 1268 | skb_trim(skb, skb->len - 4); /* remove fcs */ |
2f7ca802 SG |
1269 | skb->truesize = size + sizeof(struct sk_buff); |
1270 | ||
1271 | return 1; | |
1272 | } | |
1273 | ||
1274 | ax_skb = skb_clone(skb, GFP_ATOMIC); | |
1275 | if (unlikely(!ax_skb)) { | |
60b86755 | 1276 | netdev_warn(dev->net, "Error allocating skb\n"); |
2f7ca802 SG |
1277 | return 0; |
1278 | } | |
1279 | ||
1280 | ax_skb->len = size; | |
1281 | ax_skb->data = packet; | |
1282 | skb_set_tail_pointer(ax_skb, size); | |
1283 | ||
78e47fe4 | 1284 | if (dev->net->features & NETIF_F_RXCSUM) |
2f7ca802 | 1285 | smsc95xx_rx_csum_offload(ax_skb); |
df18acca | 1286 | skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ |
2f7ca802 SG |
1287 | ax_skb->truesize = size + sizeof(struct sk_buff); |
1288 | ||
1289 | usbnet_skb_return(dev, ax_skb); | |
1290 | } | |
1291 | ||
1292 | skb_pull(skb, size); | |
1293 | ||
1294 | /* padding bytes before the next frame starts */ | |
1295 | if (skb->len) | |
1296 | skb_pull(skb, align_count); | |
1297 | } | |
1298 | ||
1299 | if (unlikely(skb->len < 0)) { | |
60b86755 | 1300 | netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len); |
2f7ca802 SG |
1301 | return 0; |
1302 | } | |
1303 | ||
1304 | return 1; | |
1305 | } | |
1306 | ||
f7b29271 SG |
1307 | static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb) |
1308 | { | |
55508d60 MM |
1309 | u16 low_16 = (u16)skb_checksum_start_offset(skb); |
1310 | u16 high_16 = low_16 + skb->csum_offset; | |
f7b29271 SG |
1311 | return (high_16 << 16) | low_16; |
1312 | } | |
1313 | ||
2f7ca802 SG |
1314 | static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev, |
1315 | struct sk_buff *skb, gfp_t flags) | |
1316 | { | |
78e47fe4 | 1317 | bool csum = skb->ip_summed == CHECKSUM_PARTIAL; |
f7b29271 | 1318 | int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD; |
2f7ca802 SG |
1319 | u32 tx_cmd_a, tx_cmd_b; |
1320 | ||
f7b29271 SG |
1321 | /* We do not advertise SG, so skbs should be already linearized */ |
1322 | BUG_ON(skb_shinfo(skb)->nr_frags); | |
1323 | ||
1324 | if (skb_headroom(skb) < overhead) { | |
2f7ca802 | 1325 | struct sk_buff *skb2 = skb_copy_expand(skb, |
f7b29271 | 1326 | overhead, 0, flags); |
2f7ca802 SG |
1327 | dev_kfree_skb_any(skb); |
1328 | skb = skb2; | |
1329 | if (!skb) | |
1330 | return NULL; | |
1331 | } | |
1332 | ||
f7b29271 | 1333 | if (csum) { |
11bc3088 SG |
1334 | if (skb->len <= 45) { |
1335 | /* workaround - hardware tx checksum does not work | |
1336 | * properly with extremely small packets */ | |
55508d60 | 1337 | long csstart = skb_checksum_start_offset(skb); |
11bc3088 SG |
1338 | __wsum calc = csum_partial(skb->data + csstart, |
1339 | skb->len - csstart, 0); | |
1340 | *((__sum16 *)(skb->data + csstart | |
1341 | + skb->csum_offset)) = csum_fold(calc); | |
1342 | ||
1343 | csum = false; | |
1344 | } else { | |
1345 | u32 csum_preamble = smsc95xx_calc_csum_preamble(skb); | |
1346 | skb_push(skb, 4); | |
1347 | memcpy(skb->data, &csum_preamble, 4); | |
1348 | } | |
f7b29271 SG |
1349 | } |
1350 | ||
2f7ca802 SG |
1351 | skb_push(skb, 4); |
1352 | tx_cmd_b = (u32)(skb->len - 4); | |
f7b29271 SG |
1353 | if (csum) |
1354 | tx_cmd_b |= TX_CMD_B_CSUM_ENABLE; | |
2f7ca802 SG |
1355 | cpu_to_le32s(&tx_cmd_b); |
1356 | memcpy(skb->data, &tx_cmd_b, 4); | |
1357 | ||
1358 | skb_push(skb, 4); | |
1359 | tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ | | |
1360 | TX_CMD_A_LAST_SEG_; | |
1361 | cpu_to_le32s(&tx_cmd_a); | |
1362 | memcpy(skb->data, &tx_cmd_a, 4); | |
1363 | ||
1364 | return skb; | |
1365 | } | |
1366 | ||
1367 | static const struct driver_info smsc95xx_info = { | |
1368 | .description = "smsc95xx USB 2.0 Ethernet", | |
1369 | .bind = smsc95xx_bind, | |
1370 | .unbind = smsc95xx_unbind, | |
1371 | .link_reset = smsc95xx_link_reset, | |
1372 | .reset = smsc95xx_reset, | |
1373 | .rx_fixup = smsc95xx_rx_fixup, | |
1374 | .tx_fixup = smsc95xx_tx_fixup, | |
1375 | .status = smsc95xx_status, | |
07d69d42 | 1376 | .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR, |
2f7ca802 SG |
1377 | }; |
1378 | ||
1379 | static const struct usb_device_id products[] = { | |
1380 | { | |
1381 | /* SMSC9500 USB Ethernet Device */ | |
1382 | USB_DEVICE(0x0424, 0x9500), | |
1383 | .driver_info = (unsigned long) &smsc95xx_info, | |
1384 | }, | |
6f41d12b SG |
1385 | { |
1386 | /* SMSC9505 USB Ethernet Device */ | |
1387 | USB_DEVICE(0x0424, 0x9505), | |
1388 | .driver_info = (unsigned long) &smsc95xx_info, | |
1389 | }, | |
1390 | { | |
1391 | /* SMSC9500A USB Ethernet Device */ | |
1392 | USB_DEVICE(0x0424, 0x9E00), | |
1393 | .driver_info = (unsigned long) &smsc95xx_info, | |
1394 | }, | |
1395 | { | |
1396 | /* SMSC9505A USB Ethernet Device */ | |
1397 | USB_DEVICE(0x0424, 0x9E01), | |
1398 | .driver_info = (unsigned long) &smsc95xx_info, | |
1399 | }, | |
726474b8 SG |
1400 | { |
1401 | /* SMSC9512/9514 USB Hub & Ethernet Device */ | |
1402 | USB_DEVICE(0x0424, 0xec00), | |
1403 | .driver_info = (unsigned long) &smsc95xx_info, | |
1404 | }, | |
6f41d12b SG |
1405 | { |
1406 | /* SMSC9500 USB Ethernet Device (SAL10) */ | |
1407 | USB_DEVICE(0x0424, 0x9900), | |
1408 | .driver_info = (unsigned long) &smsc95xx_info, | |
1409 | }, | |
1410 | { | |
1411 | /* SMSC9505 USB Ethernet Device (SAL10) */ | |
1412 | USB_DEVICE(0x0424, 0x9901), | |
1413 | .driver_info = (unsigned long) &smsc95xx_info, | |
1414 | }, | |
1415 | { | |
1416 | /* SMSC9500A USB Ethernet Device (SAL10) */ | |
1417 | USB_DEVICE(0x0424, 0x9902), | |
1418 | .driver_info = (unsigned long) &smsc95xx_info, | |
1419 | }, | |
1420 | { | |
1421 | /* SMSC9505A USB Ethernet Device (SAL10) */ | |
1422 | USB_DEVICE(0x0424, 0x9903), | |
1423 | .driver_info = (unsigned long) &smsc95xx_info, | |
1424 | }, | |
1425 | { | |
1426 | /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */ | |
1427 | USB_DEVICE(0x0424, 0x9904), | |
1428 | .driver_info = (unsigned long) &smsc95xx_info, | |
1429 | }, | |
1430 | { | |
1431 | /* SMSC9500A USB Ethernet Device (HAL) */ | |
1432 | USB_DEVICE(0x0424, 0x9905), | |
1433 | .driver_info = (unsigned long) &smsc95xx_info, | |
1434 | }, | |
1435 | { | |
1436 | /* SMSC9505A USB Ethernet Device (HAL) */ | |
1437 | USB_DEVICE(0x0424, 0x9906), | |
1438 | .driver_info = (unsigned long) &smsc95xx_info, | |
1439 | }, | |
1440 | { | |
1441 | /* SMSC9500 USB Ethernet Device (Alternate ID) */ | |
1442 | USB_DEVICE(0x0424, 0x9907), | |
1443 | .driver_info = (unsigned long) &smsc95xx_info, | |
1444 | }, | |
1445 | { | |
1446 | /* SMSC9500A USB Ethernet Device (Alternate ID) */ | |
1447 | USB_DEVICE(0x0424, 0x9908), | |
1448 | .driver_info = (unsigned long) &smsc95xx_info, | |
1449 | }, | |
1450 | { | |
1451 | /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */ | |
1452 | USB_DEVICE(0x0424, 0x9909), | |
1453 | .driver_info = (unsigned long) &smsc95xx_info, | |
1454 | }, | |
88edaa41 SG |
1455 | { |
1456 | /* SMSC LAN9530 USB Ethernet Device */ | |
1457 | USB_DEVICE(0x0424, 0x9530), | |
1458 | .driver_info = (unsigned long) &smsc95xx_info, | |
1459 | }, | |
1460 | { | |
1461 | /* SMSC LAN9730 USB Ethernet Device */ | |
1462 | USB_DEVICE(0x0424, 0x9730), | |
1463 | .driver_info = (unsigned long) &smsc95xx_info, | |
1464 | }, | |
1465 | { | |
1466 | /* SMSC LAN89530 USB Ethernet Device */ | |
1467 | USB_DEVICE(0x0424, 0x9E08), | |
1468 | .driver_info = (unsigned long) &smsc95xx_info, | |
1469 | }, | |
2f7ca802 SG |
1470 | { }, /* END */ |
1471 | }; | |
1472 | MODULE_DEVICE_TABLE(usb, products); | |
1473 | ||
1474 | static struct usb_driver smsc95xx_driver = { | |
1475 | .name = "smsc95xx", | |
1476 | .id_table = products, | |
1477 | .probe = usbnet_probe, | |
b5a04475 | 1478 | .suspend = smsc95xx_suspend, |
e0e474a8 SG |
1479 | .resume = smsc95xx_resume, |
1480 | .reset_resume = smsc95xx_resume, | |
2f7ca802 | 1481 | .disconnect = usbnet_disconnect, |
e1f12eb6 | 1482 | .disable_hub_initiated_lpm = 1, |
2f7ca802 SG |
1483 | }; |
1484 | ||
d632eb1b | 1485 | module_usb_driver(smsc95xx_driver); |
2f7ca802 SG |
1486 | |
1487 | MODULE_AUTHOR("Nancy Lin"); | |
90b24cfb | 1488 | MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); |
2f7ca802 SG |
1489 | MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices"); |
1490 | MODULE_LICENSE("GPL"); |