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2f7ca802 SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2007-2008 SMSC | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | * | |
19 | *****************************************************************************/ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/kmod.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/ethtool.h> | |
27 | #include <linux/mii.h> | |
28 | #include <linux/usb.h> | |
29 | #include <linux/crc32.h> | |
30 | #include <linux/usb/usbnet.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2f7ca802 SG |
32 | #include "smsc95xx.h" |
33 | ||
34 | #define SMSC_CHIPNAME "smsc95xx" | |
f7b29271 | 35 | #define SMSC_DRIVER_VERSION "1.0.4" |
2f7ca802 SG |
36 | #define HS_USB_PKT_SIZE (512) |
37 | #define FS_USB_PKT_SIZE (64) | |
38 | #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) | |
39 | #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) | |
40 | #define DEFAULT_BULK_IN_DELAY (0x00002000) | |
41 | #define MAX_SINGLE_PACKET_SIZE (2048) | |
42 | #define LAN95XX_EEPROM_MAGIC (0x9500) | |
43 | #define EEPROM_MAC_OFFSET (0x01) | |
f7b29271 | 44 | #define DEFAULT_TX_CSUM_ENABLE (true) |
2f7ca802 SG |
45 | #define DEFAULT_RX_CSUM_ENABLE (true) |
46 | #define SMSC95XX_INTERNAL_PHY_ID (1) | |
47 | #define SMSC95XX_TX_OVERHEAD (8) | |
f7b29271 | 48 | #define SMSC95XX_TX_OVERHEAD_CSUM (12) |
e0e474a8 | 49 | #define SUPPORTED_WAKE (WAKE_MAGIC) |
2f7ca802 | 50 | |
769ea6d8 SG |
51 | #define check_warn(ret, fmt, args...) \ |
52 | ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); }) | |
53 | ||
54 | #define check_warn_return(ret, fmt, args...) \ | |
55 | ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } }) | |
56 | ||
57 | #define check_warn_goto_done(ret, fmt, args...) \ | |
58 | ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } }) | |
59 | ||
2f7ca802 SG |
60 | struct smsc95xx_priv { |
61 | u32 mac_cr; | |
3c0f3c60 MZ |
62 | u32 hash_hi; |
63 | u32 hash_lo; | |
e0e474a8 | 64 | u32 wolopts; |
2f7ca802 | 65 | spinlock_t mac_cr_lock; |
2f7ca802 SG |
66 | }; |
67 | ||
eb939922 | 68 | static bool turbo_mode = true; |
2f7ca802 SG |
69 | module_param(turbo_mode, bool, 0644); |
70 | MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); | |
71 | ||
769ea6d8 SG |
72 | static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index, |
73 | u32 *data) | |
2f7ca802 | 74 | { |
72108fd2 | 75 | u32 buf; |
2f7ca802 SG |
76 | int ret; |
77 | ||
78 | BUG_ON(!dev); | |
79 | ||
72108fd2 ML |
80 | ret = usbnet_read_cmd(dev, USB_VENDOR_REQUEST_READ_REGISTER, |
81 | USB_DIR_IN | USB_TYPE_VENDOR | | |
82 | USB_RECIP_DEVICE, | |
83 | 0, index, &buf, 4); | |
2f7ca802 | 84 | if (unlikely(ret < 0)) |
60b86755 | 85 | netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index); |
2f7ca802 | 86 | |
72108fd2 ML |
87 | le32_to_cpus(&buf); |
88 | *data = buf; | |
2f7ca802 SG |
89 | |
90 | return ret; | |
91 | } | |
92 | ||
769ea6d8 SG |
93 | static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index, |
94 | u32 data) | |
2f7ca802 | 95 | { |
72108fd2 | 96 | u32 buf; |
2f7ca802 SG |
97 | int ret; |
98 | ||
99 | BUG_ON(!dev); | |
100 | ||
72108fd2 ML |
101 | buf = data; |
102 | cpu_to_le32s(&buf); | |
2f7ca802 | 103 | |
2f7ca802 | 104 | |
72108fd2 ML |
105 | ret = usbnet_write_cmd(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, |
106 | USB_DIR_OUT | USB_TYPE_VENDOR | | |
107 | USB_RECIP_DEVICE, | |
108 | 0, index, &buf, 4); | |
2f7ca802 | 109 | if (unlikely(ret < 0)) |
60b86755 | 110 | netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index); |
2f7ca802 | 111 | |
2f7ca802 SG |
112 | return ret; |
113 | } | |
114 | ||
e0e474a8 SG |
115 | static int smsc95xx_set_feature(struct usbnet *dev, u32 feature) |
116 | { | |
117 | if (WARN_ON_ONCE(!dev)) | |
118 | return -EINVAL; | |
119 | ||
72108fd2 ML |
120 | return usbnet_write_cmd(dev, USB_REQ_SET_FEATURE, |
121 | USB_RECIP_DEVICE, feature, 0, NULL, 0); | |
e0e474a8 SG |
122 | } |
123 | ||
124 | static int smsc95xx_clear_feature(struct usbnet *dev, u32 feature) | |
125 | { | |
126 | if (WARN_ON_ONCE(!dev)) | |
127 | return -EINVAL; | |
128 | ||
72108fd2 ML |
129 | return usbnet_write_cmd(dev, USB_REQ_CLEAR_FEATURE, |
130 | USB_RECIP_DEVICE, feature, 0, NULL, 0); | |
e0e474a8 SG |
131 | } |
132 | ||
2f7ca802 SG |
133 | /* Loop until the read is completed with timeout |
134 | * called with phy_mutex held */ | |
769ea6d8 | 135 | static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev) |
2f7ca802 SG |
136 | { |
137 | unsigned long start_time = jiffies; | |
138 | u32 val; | |
769ea6d8 | 139 | int ret; |
2f7ca802 SG |
140 | |
141 | do { | |
769ea6d8 SG |
142 | ret = smsc95xx_read_reg(dev, MII_ADDR, &val); |
143 | check_warn_return(ret, "Error reading MII_ACCESS"); | |
2f7ca802 SG |
144 | if (!(val & MII_BUSY_)) |
145 | return 0; | |
146 | } while (!time_after(jiffies, start_time + HZ)); | |
147 | ||
148 | return -EIO; | |
149 | } | |
150 | ||
151 | static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx) | |
152 | { | |
153 | struct usbnet *dev = netdev_priv(netdev); | |
154 | u32 val, addr; | |
769ea6d8 | 155 | int ret; |
2f7ca802 SG |
156 | |
157 | mutex_lock(&dev->phy_mutex); | |
158 | ||
159 | /* confirm MII not busy */ | |
769ea6d8 SG |
160 | ret = smsc95xx_phy_wait_not_busy(dev); |
161 | check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read"); | |
2f7ca802 SG |
162 | |
163 | /* set the address, index & direction (read from PHY) */ | |
164 | phy_id &= dev->mii.phy_id_mask; | |
165 | idx &= dev->mii.reg_num_mask; | |
166 | addr = (phy_id << 11) | (idx << 6) | MII_READ_; | |
769ea6d8 SG |
167 | ret = smsc95xx_write_reg(dev, MII_ADDR, addr); |
168 | check_warn_goto_done(ret, "Error writing MII_ADDR"); | |
2f7ca802 | 169 | |
769ea6d8 SG |
170 | ret = smsc95xx_phy_wait_not_busy(dev); |
171 | check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx); | |
2f7ca802 | 172 | |
769ea6d8 SG |
173 | ret = smsc95xx_read_reg(dev, MII_DATA, &val); |
174 | check_warn_goto_done(ret, "Error reading MII_DATA"); | |
2f7ca802 | 175 | |
769ea6d8 | 176 | ret = (u16)(val & 0xFFFF); |
2f7ca802 | 177 | |
769ea6d8 SG |
178 | done: |
179 | mutex_unlock(&dev->phy_mutex); | |
180 | return ret; | |
2f7ca802 SG |
181 | } |
182 | ||
183 | static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx, | |
184 | int regval) | |
185 | { | |
186 | struct usbnet *dev = netdev_priv(netdev); | |
187 | u32 val, addr; | |
769ea6d8 | 188 | int ret; |
2f7ca802 SG |
189 | |
190 | mutex_lock(&dev->phy_mutex); | |
191 | ||
192 | /* confirm MII not busy */ | |
769ea6d8 SG |
193 | ret = smsc95xx_phy_wait_not_busy(dev); |
194 | check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write"); | |
2f7ca802 SG |
195 | |
196 | val = regval; | |
769ea6d8 SG |
197 | ret = smsc95xx_write_reg(dev, MII_DATA, val); |
198 | check_warn_goto_done(ret, "Error writing MII_DATA"); | |
2f7ca802 SG |
199 | |
200 | /* set the address, index & direction (write to PHY) */ | |
201 | phy_id &= dev->mii.phy_id_mask; | |
202 | idx &= dev->mii.reg_num_mask; | |
203 | addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; | |
769ea6d8 SG |
204 | ret = smsc95xx_write_reg(dev, MII_ADDR, addr); |
205 | check_warn_goto_done(ret, "Error writing MII_ADDR"); | |
2f7ca802 | 206 | |
769ea6d8 SG |
207 | ret = smsc95xx_phy_wait_not_busy(dev); |
208 | check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx); | |
2f7ca802 | 209 | |
769ea6d8 | 210 | done: |
2f7ca802 SG |
211 | mutex_unlock(&dev->phy_mutex); |
212 | } | |
213 | ||
769ea6d8 | 214 | static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev) |
2f7ca802 SG |
215 | { |
216 | unsigned long start_time = jiffies; | |
217 | u32 val; | |
769ea6d8 | 218 | int ret; |
2f7ca802 SG |
219 | |
220 | do { | |
769ea6d8 SG |
221 | ret = smsc95xx_read_reg(dev, E2P_CMD, &val); |
222 | check_warn_return(ret, "Error reading E2P_CMD"); | |
2f7ca802 SG |
223 | if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) |
224 | break; | |
225 | udelay(40); | |
226 | } while (!time_after(jiffies, start_time + HZ)); | |
227 | ||
228 | if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { | |
60b86755 | 229 | netdev_warn(dev->net, "EEPROM read operation timeout\n"); |
2f7ca802 SG |
230 | return -EIO; |
231 | } | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
769ea6d8 | 236 | static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev) |
2f7ca802 SG |
237 | { |
238 | unsigned long start_time = jiffies; | |
239 | u32 val; | |
769ea6d8 | 240 | int ret; |
2f7ca802 SG |
241 | |
242 | do { | |
769ea6d8 SG |
243 | ret = smsc95xx_read_reg(dev, E2P_CMD, &val); |
244 | check_warn_return(ret, "Error reading E2P_CMD"); | |
2f7ca802 | 245 | |
2f7ca802 SG |
246 | if (!(val & E2P_CMD_BUSY_)) |
247 | return 0; | |
248 | ||
249 | udelay(40); | |
250 | } while (!time_after(jiffies, start_time + HZ)); | |
251 | ||
60b86755 | 252 | netdev_warn(dev->net, "EEPROM is busy\n"); |
2f7ca802 SG |
253 | return -EIO; |
254 | } | |
255 | ||
256 | static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length, | |
257 | u8 *data) | |
258 | { | |
259 | u32 val; | |
260 | int i, ret; | |
261 | ||
262 | BUG_ON(!dev); | |
263 | BUG_ON(!data); | |
264 | ||
265 | ret = smsc95xx_eeprom_confirm_not_busy(dev); | |
266 | if (ret) | |
267 | return ret; | |
268 | ||
269 | for (i = 0; i < length; i++) { | |
270 | val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); | |
769ea6d8 SG |
271 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
272 | check_warn_return(ret, "Error writing E2P_CMD"); | |
2f7ca802 SG |
273 | |
274 | ret = smsc95xx_wait_eeprom(dev); | |
275 | if (ret < 0) | |
276 | return ret; | |
277 | ||
769ea6d8 SG |
278 | ret = smsc95xx_read_reg(dev, E2P_DATA, &val); |
279 | check_warn_return(ret, "Error reading E2P_DATA"); | |
2f7ca802 SG |
280 | |
281 | data[i] = val & 0xFF; | |
282 | offset++; | |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length, | |
289 | u8 *data) | |
290 | { | |
291 | u32 val; | |
292 | int i, ret; | |
293 | ||
294 | BUG_ON(!dev); | |
295 | BUG_ON(!data); | |
296 | ||
297 | ret = smsc95xx_eeprom_confirm_not_busy(dev); | |
298 | if (ret) | |
299 | return ret; | |
300 | ||
301 | /* Issue write/erase enable command */ | |
302 | val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_; | |
769ea6d8 SG |
303 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
304 | check_warn_return(ret, "Error writing E2P_DATA"); | |
2f7ca802 SG |
305 | |
306 | ret = smsc95xx_wait_eeprom(dev); | |
307 | if (ret < 0) | |
308 | return ret; | |
309 | ||
310 | for (i = 0; i < length; i++) { | |
311 | ||
312 | /* Fill data register */ | |
313 | val = data[i]; | |
769ea6d8 SG |
314 | ret = smsc95xx_write_reg(dev, E2P_DATA, val); |
315 | check_warn_return(ret, "Error writing E2P_DATA"); | |
2f7ca802 SG |
316 | |
317 | /* Send "write" command */ | |
318 | val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_); | |
769ea6d8 SG |
319 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
320 | check_warn_return(ret, "Error writing E2P_CMD"); | |
2f7ca802 SG |
321 | |
322 | ret = smsc95xx_wait_eeprom(dev); | |
323 | if (ret < 0) | |
324 | return ret; | |
325 | ||
326 | offset++; | |
327 | } | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
769ea6d8 SG |
332 | static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index, |
333 | u32 *data) | |
2f7ca802 | 334 | { |
1d74a6bd | 335 | const u16 size = 4; |
72108fd2 | 336 | int ret; |
2f7ca802 | 337 | |
72108fd2 ML |
338 | ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, |
339 | USB_DIR_OUT | USB_TYPE_VENDOR | | |
340 | USB_RECIP_DEVICE, | |
341 | 0, index, data, size); | |
342 | if (ret < 0) | |
343 | netdev_warn(dev->net, "Error write async cmd, sts=%d\n", | |
344 | ret); | |
345 | return ret; | |
2f7ca802 SG |
346 | } |
347 | ||
348 | /* returns hash bit number for given MAC address | |
349 | * example: | |
350 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
351 | static unsigned int smsc95xx_hash(char addr[ETH_ALEN]) | |
352 | { | |
353 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
354 | } | |
355 | ||
356 | static void smsc95xx_set_multicast(struct net_device *netdev) | |
357 | { | |
358 | struct usbnet *dev = netdev_priv(netdev); | |
359 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
2f7ca802 | 360 | unsigned long flags; |
769ea6d8 | 361 | int ret; |
2f7ca802 | 362 | |
3c0f3c60 MZ |
363 | pdata->hash_hi = 0; |
364 | pdata->hash_lo = 0; | |
365 | ||
2f7ca802 SG |
366 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); |
367 | ||
368 | if (dev->net->flags & IFF_PROMISC) { | |
a475f603 | 369 | netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n"); |
2f7ca802 SG |
370 | pdata->mac_cr |= MAC_CR_PRMS_; |
371 | pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
372 | } else if (dev->net->flags & IFF_ALLMULTI) { | |
a475f603 | 373 | netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n"); |
2f7ca802 SG |
374 | pdata->mac_cr |= MAC_CR_MCPAS_; |
375 | pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
4cd24eaf | 376 | } else if (!netdev_mc_empty(dev->net)) { |
22bedad3 | 377 | struct netdev_hw_addr *ha; |
2f7ca802 SG |
378 | |
379 | pdata->mac_cr |= MAC_CR_HPFILT_; | |
380 | pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
381 | ||
22bedad3 JP |
382 | netdev_for_each_mc_addr(ha, netdev) { |
383 | u32 bitnum = smsc95xx_hash(ha->addr); | |
a92635dc JP |
384 | u32 mask = 0x01 << (bitnum & 0x1F); |
385 | if (bitnum & 0x20) | |
3c0f3c60 | 386 | pdata->hash_hi |= mask; |
a92635dc | 387 | else |
3c0f3c60 | 388 | pdata->hash_lo |= mask; |
2f7ca802 SG |
389 | } |
390 | ||
a475f603 | 391 | netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n", |
3c0f3c60 | 392 | pdata->hash_hi, pdata->hash_lo); |
2f7ca802 | 393 | } else { |
a475f603 | 394 | netif_dbg(dev, drv, dev->net, "receive own packets only\n"); |
2f7ca802 SG |
395 | pdata->mac_cr &= |
396 | ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
397 | } | |
398 | ||
399 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
400 | ||
401 | /* Initiate async writes, as we can't wait for completion here */ | |
769ea6d8 SG |
402 | ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi); |
403 | check_warn(ret, "failed to initiate async write to HASHH"); | |
404 | ||
405 | ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo); | |
406 | check_warn(ret, "failed to initiate async write to HASHL"); | |
407 | ||
408 | ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr); | |
409 | check_warn(ret, "failed to initiate async write to MAC_CR"); | |
2f7ca802 SG |
410 | } |
411 | ||
769ea6d8 SG |
412 | static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex, |
413 | u16 lcladv, u16 rmtadv) | |
2f7ca802 SG |
414 | { |
415 | u32 flow, afc_cfg = 0; | |
416 | ||
417 | int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg); | |
769ea6d8 | 418 | check_warn_return(ret, "Error reading AFC_CFG"); |
2f7ca802 SG |
419 | |
420 | if (duplex == DUPLEX_FULL) { | |
bc02ff95 | 421 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
2f7ca802 SG |
422 | |
423 | if (cap & FLOW_CTRL_RX) | |
424 | flow = 0xFFFF0002; | |
425 | else | |
426 | flow = 0; | |
427 | ||
428 | if (cap & FLOW_CTRL_TX) | |
429 | afc_cfg |= 0xF; | |
430 | else | |
431 | afc_cfg &= ~0xF; | |
432 | ||
a475f603 | 433 | netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n", |
60b86755 JP |
434 | cap & FLOW_CTRL_RX ? "enabled" : "disabled", |
435 | cap & FLOW_CTRL_TX ? "enabled" : "disabled"); | |
2f7ca802 | 436 | } else { |
a475f603 | 437 | netif_dbg(dev, link, dev->net, "half duplex\n"); |
2f7ca802 SG |
438 | flow = 0; |
439 | afc_cfg |= 0xF; | |
440 | } | |
441 | ||
769ea6d8 SG |
442 | ret = smsc95xx_write_reg(dev, FLOW, flow); |
443 | check_warn_return(ret, "Error writing FLOW"); | |
444 | ||
445 | ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg); | |
446 | check_warn_return(ret, "Error writing AFC_CFG"); | |
447 | ||
448 | return 0; | |
2f7ca802 SG |
449 | } |
450 | ||
451 | static int smsc95xx_link_reset(struct usbnet *dev) | |
452 | { | |
453 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
454 | struct mii_if_info *mii = &dev->mii; | |
8ae6daca | 455 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
2f7ca802 SG |
456 | unsigned long flags; |
457 | u16 lcladv, rmtadv; | |
769ea6d8 | 458 | int ret; |
2f7ca802 SG |
459 | |
460 | /* clear interrupt status */ | |
769ea6d8 SG |
461 | ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC); |
462 | check_warn_return(ret, "Error reading PHY_INT_SRC"); | |
463 | ||
464 | ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); | |
465 | check_warn_return(ret, "Error writing INT_STS"); | |
2f7ca802 SG |
466 | |
467 | mii_check_media(mii, 1, 1); | |
468 | mii_ethtool_gset(&dev->mii, &ecmd); | |
469 | lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE); | |
470 | rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA); | |
471 | ||
8ae6daca DD |
472 | netif_dbg(dev, link, dev->net, |
473 | "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n", | |
474 | ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv); | |
2f7ca802 SG |
475 | |
476 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
477 | if (ecmd.duplex != DUPLEX_FULL) { | |
478 | pdata->mac_cr &= ~MAC_CR_FDPX_; | |
479 | pdata->mac_cr |= MAC_CR_RCVOWN_; | |
480 | } else { | |
481 | pdata->mac_cr &= ~MAC_CR_RCVOWN_; | |
482 | pdata->mac_cr |= MAC_CR_FDPX_; | |
483 | } | |
484 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
485 | ||
769ea6d8 SG |
486 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
487 | check_warn_return(ret, "Error writing MAC_CR"); | |
2f7ca802 | 488 | |
769ea6d8 SG |
489 | ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv); |
490 | check_warn_return(ret, "Error updating PHY flow control"); | |
2f7ca802 SG |
491 | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static void smsc95xx_status(struct usbnet *dev, struct urb *urb) | |
496 | { | |
497 | u32 intdata; | |
498 | ||
499 | if (urb->actual_length != 4) { | |
60b86755 JP |
500 | netdev_warn(dev->net, "unexpected urb length %d\n", |
501 | urb->actual_length); | |
2f7ca802 SG |
502 | return; |
503 | } | |
504 | ||
505 | memcpy(&intdata, urb->transfer_buffer, 4); | |
1d74a6bd | 506 | le32_to_cpus(&intdata); |
2f7ca802 | 507 | |
a475f603 | 508 | netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata); |
2f7ca802 SG |
509 | |
510 | if (intdata & INT_ENP_PHY_INT_) | |
511 | usbnet_defer_kevent(dev, EVENT_LINK_RESET); | |
512 | else | |
60b86755 JP |
513 | netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n", |
514 | intdata); | |
2f7ca802 SG |
515 | } |
516 | ||
f7b29271 | 517 | /* Enable or disable Tx & Rx checksum offload engines */ |
c8f44aff MM |
518 | static int smsc95xx_set_features(struct net_device *netdev, |
519 | netdev_features_t features) | |
2f7ca802 | 520 | { |
78e47fe4 | 521 | struct usbnet *dev = netdev_priv(netdev); |
2f7ca802 | 522 | u32 read_buf; |
78e47fe4 MM |
523 | int ret; |
524 | ||
525 | ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); | |
769ea6d8 | 526 | check_warn_return(ret, "Failed to read COE_CR: %d\n", ret); |
2f7ca802 | 527 | |
78e47fe4 | 528 | if (features & NETIF_F_HW_CSUM) |
f7b29271 SG |
529 | read_buf |= Tx_COE_EN_; |
530 | else | |
531 | read_buf &= ~Tx_COE_EN_; | |
532 | ||
78e47fe4 | 533 | if (features & NETIF_F_RXCSUM) |
2f7ca802 SG |
534 | read_buf |= Rx_COE_EN_; |
535 | else | |
536 | read_buf &= ~Rx_COE_EN_; | |
537 | ||
538 | ret = smsc95xx_write_reg(dev, COE_CR, read_buf); | |
769ea6d8 | 539 | check_warn_return(ret, "Failed to write COE_CR: %d\n", ret); |
2f7ca802 | 540 | |
a475f603 | 541 | netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf); |
2f7ca802 SG |
542 | return 0; |
543 | } | |
544 | ||
545 | static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net) | |
546 | { | |
547 | return MAX_EEPROM_SIZE; | |
548 | } | |
549 | ||
550 | static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev, | |
551 | struct ethtool_eeprom *ee, u8 *data) | |
552 | { | |
553 | struct usbnet *dev = netdev_priv(netdev); | |
554 | ||
555 | ee->magic = LAN95XX_EEPROM_MAGIC; | |
556 | ||
557 | return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data); | |
558 | } | |
559 | ||
560 | static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev, | |
561 | struct ethtool_eeprom *ee, u8 *data) | |
562 | { | |
563 | struct usbnet *dev = netdev_priv(netdev); | |
564 | ||
565 | if (ee->magic != LAN95XX_EEPROM_MAGIC) { | |
60b86755 JP |
566 | netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n", |
567 | ee->magic); | |
2f7ca802 SG |
568 | return -EINVAL; |
569 | } | |
570 | ||
571 | return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data); | |
572 | } | |
573 | ||
9fa32e94 EV |
574 | static int smsc95xx_ethtool_getregslen(struct net_device *netdev) |
575 | { | |
576 | /* all smsc95xx registers */ | |
577 | return COE_CR - ID_REV + 1; | |
578 | } | |
579 | ||
580 | static void | |
581 | smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs, | |
582 | void *buf) | |
583 | { | |
584 | struct usbnet *dev = netdev_priv(netdev); | |
d348446b DC |
585 | unsigned int i, j; |
586 | int retval; | |
9fa32e94 EV |
587 | u32 *data = buf; |
588 | ||
589 | retval = smsc95xx_read_reg(dev, ID_REV, ®s->version); | |
590 | if (retval < 0) { | |
591 | netdev_warn(netdev, "REGS: cannot read ID_REV\n"); | |
592 | return; | |
593 | } | |
594 | ||
595 | for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) { | |
596 | retval = smsc95xx_read_reg(dev, i, &data[j]); | |
597 | if (retval < 0) { | |
598 | netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i); | |
599 | return; | |
600 | } | |
601 | } | |
602 | } | |
603 | ||
e0e474a8 SG |
604 | static void smsc95xx_ethtool_get_wol(struct net_device *net, |
605 | struct ethtool_wolinfo *wolinfo) | |
606 | { | |
607 | struct usbnet *dev = netdev_priv(net); | |
608 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
609 | ||
610 | wolinfo->supported = SUPPORTED_WAKE; | |
611 | wolinfo->wolopts = pdata->wolopts; | |
612 | } | |
613 | ||
614 | static int smsc95xx_ethtool_set_wol(struct net_device *net, | |
615 | struct ethtool_wolinfo *wolinfo) | |
616 | { | |
617 | struct usbnet *dev = netdev_priv(net); | |
618 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
619 | ||
620 | pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE; | |
621 | return 0; | |
622 | } | |
623 | ||
0fc0b732 | 624 | static const struct ethtool_ops smsc95xx_ethtool_ops = { |
2f7ca802 SG |
625 | .get_link = usbnet_get_link, |
626 | .nway_reset = usbnet_nway_reset, | |
627 | .get_drvinfo = usbnet_get_drvinfo, | |
628 | .get_msglevel = usbnet_get_msglevel, | |
629 | .set_msglevel = usbnet_set_msglevel, | |
630 | .get_settings = usbnet_get_settings, | |
631 | .set_settings = usbnet_set_settings, | |
632 | .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len, | |
633 | .get_eeprom = smsc95xx_ethtool_get_eeprom, | |
634 | .set_eeprom = smsc95xx_ethtool_set_eeprom, | |
9fa32e94 EV |
635 | .get_regs_len = smsc95xx_ethtool_getregslen, |
636 | .get_regs = smsc95xx_ethtool_getregs, | |
e0e474a8 SG |
637 | .get_wol = smsc95xx_ethtool_get_wol, |
638 | .set_wol = smsc95xx_ethtool_set_wol, | |
2f7ca802 SG |
639 | }; |
640 | ||
641 | static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
642 | { | |
643 | struct usbnet *dev = netdev_priv(netdev); | |
644 | ||
645 | if (!netif_running(netdev)) | |
646 | return -EINVAL; | |
647 | ||
648 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
649 | } | |
650 | ||
651 | static void smsc95xx_init_mac_address(struct usbnet *dev) | |
652 | { | |
653 | /* try reading mac address from EEPROM */ | |
654 | if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, | |
655 | dev->net->dev_addr) == 0) { | |
656 | if (is_valid_ether_addr(dev->net->dev_addr)) { | |
657 | /* eeprom values are valid so use them */ | |
a475f603 | 658 | netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n"); |
2f7ca802 SG |
659 | return; |
660 | } | |
661 | } | |
662 | ||
663 | /* no eeprom, or eeprom values are invalid. generate random MAC */ | |
f2cedb63 | 664 | eth_hw_addr_random(dev->net); |
c7e12ead | 665 | netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n"); |
2f7ca802 SG |
666 | } |
667 | ||
668 | static int smsc95xx_set_mac_address(struct usbnet *dev) | |
669 | { | |
670 | u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 | | |
671 | dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24; | |
672 | u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8; | |
673 | int ret; | |
674 | ||
675 | ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); | |
769ea6d8 | 676 | check_warn_return(ret, "Failed to write ADDRL: %d\n", ret); |
2f7ca802 SG |
677 | |
678 | ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); | |
769ea6d8 | 679 | check_warn_return(ret, "Failed to write ADDRH: %d\n", ret); |
2f7ca802 SG |
680 | |
681 | return 0; | |
682 | } | |
683 | ||
684 | /* starts the TX path */ | |
769ea6d8 | 685 | static int smsc95xx_start_tx_path(struct usbnet *dev) |
2f7ca802 SG |
686 | { |
687 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
688 | unsigned long flags; | |
769ea6d8 | 689 | int ret; |
2f7ca802 SG |
690 | |
691 | /* Enable Tx at MAC */ | |
692 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
693 | pdata->mac_cr |= MAC_CR_TXEN_; | |
694 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
695 | ||
769ea6d8 SG |
696 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
697 | check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); | |
2f7ca802 SG |
698 | |
699 | /* Enable Tx at SCSRs */ | |
769ea6d8 SG |
700 | ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_); |
701 | check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret); | |
702 | ||
703 | return 0; | |
2f7ca802 SG |
704 | } |
705 | ||
706 | /* Starts the Receive path */ | |
769ea6d8 | 707 | static int smsc95xx_start_rx_path(struct usbnet *dev) |
2f7ca802 SG |
708 | { |
709 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
710 | unsigned long flags; | |
769ea6d8 | 711 | int ret; |
2f7ca802 SG |
712 | |
713 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
714 | pdata->mac_cr |= MAC_CR_RXEN_; | |
715 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
716 | ||
769ea6d8 SG |
717 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
718 | check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); | |
719 | ||
720 | return 0; | |
2f7ca802 SG |
721 | } |
722 | ||
723 | static int smsc95xx_phy_initialize(struct usbnet *dev) | |
724 | { | |
769ea6d8 | 725 | int bmcr, ret, timeout = 0; |
db443c44 | 726 | |
2f7ca802 SG |
727 | /* Initialize MII structure */ |
728 | dev->mii.dev = dev->net; | |
729 | dev->mii.mdio_read = smsc95xx_mdio_read; | |
730 | dev->mii.mdio_write = smsc95xx_mdio_write; | |
731 | dev->mii.phy_id_mask = 0x1f; | |
732 | dev->mii.reg_num_mask = 0x1f; | |
733 | dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID; | |
734 | ||
db443c44 | 735 | /* reset phy and wait for reset to complete */ |
2f7ca802 | 736 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
db443c44 SG |
737 | |
738 | do { | |
739 | msleep(10); | |
740 | bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR); | |
741 | timeout++; | |
d9460920 | 742 | } while ((bmcr & BMCR_RESET) && (timeout < 100)); |
db443c44 SG |
743 | |
744 | if (timeout >= 100) { | |
745 | netdev_warn(dev->net, "timeout on PHY Reset"); | |
746 | return -EIO; | |
747 | } | |
748 | ||
2f7ca802 SG |
749 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, |
750 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | | |
751 | ADVERTISE_PAUSE_ASYM); | |
752 | ||
753 | /* read to clear */ | |
769ea6d8 SG |
754 | ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC); |
755 | check_warn_return(ret, "Failed to read PHY_INT_SRC during init"); | |
2f7ca802 SG |
756 | |
757 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK, | |
758 | PHY_INT_MASK_DEFAULT_); | |
759 | mii_nway_restart(&dev->mii); | |
760 | ||
a475f603 | 761 | netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n"); |
2f7ca802 SG |
762 | return 0; |
763 | } | |
764 | ||
765 | static int smsc95xx_reset(struct usbnet *dev) | |
766 | { | |
767 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
768 | u32 read_buf, write_buf, burst_cap; | |
769 | int ret = 0, timeout; | |
2f7ca802 | 770 | |
a475f603 | 771 | netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n"); |
2f7ca802 | 772 | |
4436761b | 773 | ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_); |
769ea6d8 | 774 | check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n"); |
2f7ca802 SG |
775 | |
776 | timeout = 0; | |
777 | do { | |
cf2acec2 | 778 | msleep(10); |
2f7ca802 | 779 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); |
769ea6d8 | 780 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
2f7ca802 SG |
781 | timeout++; |
782 | } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); | |
783 | ||
784 | if (timeout >= 100) { | |
60b86755 | 785 | netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n"); |
2f7ca802 SG |
786 | return ret; |
787 | } | |
788 | ||
4436761b | 789 | ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); |
769ea6d8 | 790 | check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret); |
2f7ca802 SG |
791 | |
792 | timeout = 0; | |
793 | do { | |
cf2acec2 | 794 | msleep(10); |
2f7ca802 | 795 | ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); |
769ea6d8 | 796 | check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret); |
2f7ca802 SG |
797 | timeout++; |
798 | } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); | |
799 | ||
800 | if (timeout >= 100) { | |
60b86755 | 801 | netdev_warn(dev->net, "timeout waiting for PHY Reset\n"); |
2f7ca802 SG |
802 | return ret; |
803 | } | |
804 | ||
2f7ca802 SG |
805 | ret = smsc95xx_set_mac_address(dev); |
806 | if (ret < 0) | |
807 | return ret; | |
808 | ||
a475f603 JP |
809 | netif_dbg(dev, ifup, dev->net, |
810 | "MAC Address: %pM\n", dev->net->dev_addr); | |
2f7ca802 SG |
811 | |
812 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 | 813 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
2f7ca802 | 814 | |
a475f603 JP |
815 | netif_dbg(dev, ifup, dev->net, |
816 | "Read Value from HW_CFG : 0x%08x\n", read_buf); | |
2f7ca802 SG |
817 | |
818 | read_buf |= HW_CFG_BIR_; | |
819 | ||
820 | ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); | |
769ea6d8 | 821 | check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n"); |
2f7ca802 SG |
822 | |
823 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 | 824 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
a475f603 JP |
825 | netif_dbg(dev, ifup, dev->net, |
826 | "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n", | |
827 | read_buf); | |
2f7ca802 SG |
828 | |
829 | if (!turbo_mode) { | |
830 | burst_cap = 0; | |
831 | dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; | |
832 | } else if (dev->udev->speed == USB_SPEED_HIGH) { | |
833 | burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; | |
834 | dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; | |
835 | } else { | |
836 | burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; | |
837 | dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; | |
838 | } | |
839 | ||
a475f603 JP |
840 | netif_dbg(dev, ifup, dev->net, |
841 | "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size); | |
2f7ca802 SG |
842 | |
843 | ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); | |
769ea6d8 | 844 | check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret); |
2f7ca802 SG |
845 | |
846 | ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); | |
769ea6d8 SG |
847 | check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret); |
848 | ||
a475f603 JP |
849 | netif_dbg(dev, ifup, dev->net, |
850 | "Read Value from BURST_CAP after writing: 0x%08x\n", | |
851 | read_buf); | |
2f7ca802 | 852 | |
4436761b | 853 | ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); |
769ea6d8 | 854 | check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret); |
2f7ca802 SG |
855 | |
856 | ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); | |
769ea6d8 SG |
857 | check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret); |
858 | ||
a475f603 JP |
859 | netif_dbg(dev, ifup, dev->net, |
860 | "Read Value from BULK_IN_DLY after writing: 0x%08x\n", | |
861 | read_buf); | |
2f7ca802 SG |
862 | |
863 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 SG |
864 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
865 | ||
a475f603 JP |
866 | netif_dbg(dev, ifup, dev->net, |
867 | "Read Value from HW_CFG: 0x%08x\n", read_buf); | |
2f7ca802 SG |
868 | |
869 | if (turbo_mode) | |
870 | read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); | |
871 | ||
872 | read_buf &= ~HW_CFG_RXDOFF_; | |
873 | ||
874 | /* set Rx data offset=2, Make IP header aligns on word boundary. */ | |
875 | read_buf |= NET_IP_ALIGN << 9; | |
876 | ||
877 | ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); | |
769ea6d8 | 878 | check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret); |
2f7ca802 SG |
879 | |
880 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 SG |
881 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
882 | ||
a475f603 JP |
883 | netif_dbg(dev, ifup, dev->net, |
884 | "Read Value from HW_CFG after writing: 0x%08x\n", read_buf); | |
2f7ca802 | 885 | |
4436761b | 886 | ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); |
769ea6d8 | 887 | check_warn_return(ret, "Failed to write INT_STS: %d\n", ret); |
2f7ca802 SG |
888 | |
889 | ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); | |
769ea6d8 | 890 | check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); |
a475f603 | 891 | netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf); |
2f7ca802 | 892 | |
f293501c SG |
893 | /* Configure GPIO pins as LED outputs */ |
894 | write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | | |
895 | LED_GPIO_CFG_FDX_LED; | |
896 | ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf); | |
769ea6d8 | 897 | check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret); |
f293501c | 898 | |
2f7ca802 | 899 | /* Init Tx */ |
4436761b | 900 | ret = smsc95xx_write_reg(dev, FLOW, 0); |
769ea6d8 | 901 | check_warn_return(ret, "Failed to write FLOW: %d\n", ret); |
2f7ca802 | 902 | |
4436761b | 903 | ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT); |
769ea6d8 | 904 | check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret); |
2f7ca802 SG |
905 | |
906 | /* Don't need mac_cr_lock during initialisation */ | |
907 | ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr); | |
769ea6d8 | 908 | check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret); |
2f7ca802 SG |
909 | |
910 | /* Init Rx */ | |
911 | /* Set Vlan */ | |
4436761b | 912 | ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q); |
769ea6d8 | 913 | check_warn_return(ret, "Failed to write VLAN1: %d\n", ret); |
2f7ca802 | 914 | |
f7b29271 | 915 | /* Enable or disable checksum offload engines */ |
769ea6d8 SG |
916 | ret = smsc95xx_set_features(dev->net, dev->net->features); |
917 | check_warn_return(ret, "Failed to set checksum offload features"); | |
2f7ca802 SG |
918 | |
919 | smsc95xx_set_multicast(dev->net); | |
920 | ||
769ea6d8 SG |
921 | ret = smsc95xx_phy_initialize(dev); |
922 | check_warn_return(ret, "Failed to init PHY"); | |
2f7ca802 SG |
923 | |
924 | ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); | |
769ea6d8 | 925 | check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret); |
2f7ca802 SG |
926 | |
927 | /* enable PHY interrupts */ | |
928 | read_buf |= INT_EP_CTL_PHY_INT_; | |
929 | ||
930 | ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); | |
769ea6d8 | 931 | check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret); |
2f7ca802 | 932 | |
769ea6d8 SG |
933 | ret = smsc95xx_start_tx_path(dev); |
934 | check_warn_return(ret, "Failed to start TX path"); | |
935 | ||
936 | ret = smsc95xx_start_rx_path(dev); | |
937 | check_warn_return(ret, "Failed to start RX path"); | |
2f7ca802 | 938 | |
a475f603 | 939 | netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n"); |
2f7ca802 SG |
940 | return 0; |
941 | } | |
942 | ||
63e77b39 SH |
943 | static const struct net_device_ops smsc95xx_netdev_ops = { |
944 | .ndo_open = usbnet_open, | |
945 | .ndo_stop = usbnet_stop, | |
946 | .ndo_start_xmit = usbnet_start_xmit, | |
947 | .ndo_tx_timeout = usbnet_tx_timeout, | |
948 | .ndo_change_mtu = usbnet_change_mtu, | |
949 | .ndo_set_mac_address = eth_mac_addr, | |
950 | .ndo_validate_addr = eth_validate_addr, | |
951 | .ndo_do_ioctl = smsc95xx_ioctl, | |
afc4b13d | 952 | .ndo_set_rx_mode = smsc95xx_set_multicast, |
78e47fe4 | 953 | .ndo_set_features = smsc95xx_set_features, |
63e77b39 SH |
954 | }; |
955 | ||
2f7ca802 SG |
956 | static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf) |
957 | { | |
958 | struct smsc95xx_priv *pdata = NULL; | |
959 | int ret; | |
960 | ||
961 | printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n"); | |
962 | ||
963 | ret = usbnet_get_endpoints(dev, intf); | |
769ea6d8 | 964 | check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret); |
2f7ca802 SG |
965 | |
966 | dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv), | |
967 | GFP_KERNEL); | |
968 | ||
969 | pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
970 | if (!pdata) { | |
60b86755 | 971 | netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n"); |
2f7ca802 SG |
972 | return -ENOMEM; |
973 | } | |
974 | ||
975 | spin_lock_init(&pdata->mac_cr_lock); | |
976 | ||
78e47fe4 MM |
977 | if (DEFAULT_TX_CSUM_ENABLE) |
978 | dev->net->features |= NETIF_F_HW_CSUM; | |
979 | if (DEFAULT_RX_CSUM_ENABLE) | |
980 | dev->net->features |= NETIF_F_RXCSUM; | |
981 | ||
982 | dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM; | |
2f7ca802 | 983 | |
f4e8ab7c BB |
984 | smsc95xx_init_mac_address(dev); |
985 | ||
2f7ca802 SG |
986 | /* Init all registers */ |
987 | ret = smsc95xx_reset(dev); | |
988 | ||
63e77b39 | 989 | dev->net->netdev_ops = &smsc95xx_netdev_ops; |
2f7ca802 | 990 | dev->net->ethtool_ops = &smsc95xx_ethtool_ops; |
2f7ca802 | 991 | dev->net->flags |= IFF_MULTICAST; |
78e47fe4 | 992 | dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM; |
9bbf5660 | 993 | dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; |
2f7ca802 SG |
994 | return 0; |
995 | } | |
996 | ||
997 | static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf) | |
998 | { | |
999 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1000 | if (pdata) { | |
a475f603 | 1001 | netif_dbg(dev, ifdown, dev->net, "free pdata\n"); |
2f7ca802 SG |
1002 | kfree(pdata); |
1003 | pdata = NULL; | |
1004 | dev->data[0] = 0; | |
1005 | } | |
1006 | } | |
1007 | ||
b5a04475 SG |
1008 | static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message) |
1009 | { | |
1010 | struct usbnet *dev = usb_get_intfdata(intf); | |
e0e474a8 | 1011 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); |
b5a04475 SG |
1012 | int ret; |
1013 | u32 val; | |
1014 | ||
b5a04475 SG |
1015 | ret = usbnet_suspend(intf, message); |
1016 | check_warn_return(ret, "usbnet_suspend error"); | |
1017 | ||
e0e474a8 SG |
1018 | /* if no wol options set, enter lowest power SUSPEND2 mode */ |
1019 | if (!(pdata->wolopts & SUPPORTED_WAKE)) { | |
1020 | netdev_info(dev->net, "entering SUSPEND2 mode"); | |
1021 | ||
1022 | /* disable energy detect (link up) & wake up events */ | |
1023 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1024 | check_warn_return(ret, "Error reading WUCSR"); | |
1025 | ||
1026 | val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_); | |
1027 | ||
1028 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1029 | check_warn_return(ret, "Error writing WUCSR"); | |
1030 | ||
1031 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1032 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1033 | ||
1034 | val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_); | |
1035 | ||
1036 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1037 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1038 | ||
1039 | /* enter suspend2 mode */ | |
1040 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1041 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1042 | ||
1043 | val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); | |
1044 | val |= PM_CTL_SUS_MODE_2; | |
1045 | ||
1046 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1047 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | if (pdata->wolopts & WAKE_MAGIC) { | |
1053 | /* clear any pending magic packet status */ | |
1054 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1055 | check_warn_return(ret, "Error reading WUCSR"); | |
1056 | ||
1057 | val |= WUCSR_MPR_; | |
1058 | ||
1059 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1060 | check_warn_return(ret, "Error writing WUCSR"); | |
1061 | } | |
1062 | ||
1063 | /* enable/disable magic packup wake */ | |
1064 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1065 | check_warn_return(ret, "Error reading WUCSR"); | |
1066 | ||
1067 | if (pdata->wolopts & WAKE_MAGIC) { | |
1068 | netdev_info(dev->net, "enabling magic packet wakeup"); | |
1069 | val |= WUCSR_MPEN_; | |
1070 | } else { | |
1071 | netdev_info(dev->net, "disabling magic packet wakeup"); | |
1072 | val &= ~WUCSR_MPEN_; | |
1073 | } | |
1074 | ||
1075 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1076 | check_warn_return(ret, "Error writing WUCSR"); | |
1077 | ||
1078 | /* enable wol wakeup source */ | |
1079 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1080 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1081 | ||
1082 | val |= PM_CTL_WOL_EN_; | |
1083 | ||
1084 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1085 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1086 | ||
1087 | /* enable receiver */ | |
1088 | smsc95xx_start_rx_path(dev); | |
1089 | ||
1090 | /* some wol options are enabled, so enter SUSPEND0 */ | |
1091 | netdev_info(dev->net, "entering SUSPEND0 mode"); | |
b5a04475 SG |
1092 | |
1093 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1094 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1095 | ||
e0e474a8 SG |
1096 | val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_)); |
1097 | val |= PM_CTL_SUS_MODE_0; | |
b5a04475 SG |
1098 | |
1099 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1100 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1101 | ||
e0e474a8 SG |
1102 | /* clear wol status */ |
1103 | val &= ~PM_CTL_WUPS_; | |
1104 | val |= PM_CTL_WUPS_WOL_; | |
1105 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1106 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1107 | ||
1108 | /* read back PM_CTRL */ | |
1109 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1110 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1111 | ||
1112 | smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP); | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static int smsc95xx_resume(struct usb_interface *intf) | |
1118 | { | |
1119 | struct usbnet *dev = usb_get_intfdata(intf); | |
1120 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1121 | int ret; | |
1122 | u32 val; | |
1123 | ||
1124 | BUG_ON(!dev); | |
1125 | ||
1126 | if (pdata->wolopts & WAKE_MAGIC) { | |
1127 | smsc95xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP); | |
1128 | ||
1129 | /* Disable magic packup wake */ | |
1130 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1131 | check_warn_return(ret, "Error reading WUCSR"); | |
1132 | ||
1133 | val &= ~WUCSR_MPEN_; | |
1134 | ||
1135 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1136 | check_warn_return(ret, "Error writing WUCSR"); | |
1137 | ||
1138 | /* clear wake-up status */ | |
1139 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1140 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1141 | ||
1142 | val &= ~PM_CTL_WOL_EN_; | |
1143 | val |= PM_CTL_WUPS_; | |
1144 | ||
1145 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1146 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1147 | } | |
1148 | ||
1149 | return usbnet_resume(intf); | |
1150 | check_warn_return(ret, "usbnet_resume error"); | |
1151 | ||
b5a04475 SG |
1152 | return 0; |
1153 | } | |
1154 | ||
2f7ca802 SG |
1155 | static void smsc95xx_rx_csum_offload(struct sk_buff *skb) |
1156 | { | |
1157 | skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2); | |
1158 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1159 | skb_trim(skb, skb->len - 2); | |
1160 | } | |
1161 | ||
1162 | static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
1163 | { | |
2f7ca802 SG |
1164 | while (skb->len > 0) { |
1165 | u32 header, align_count; | |
1166 | struct sk_buff *ax_skb; | |
1167 | unsigned char *packet; | |
1168 | u16 size; | |
1169 | ||
1170 | memcpy(&header, skb->data, sizeof(header)); | |
1171 | le32_to_cpus(&header); | |
1172 | skb_pull(skb, 4 + NET_IP_ALIGN); | |
1173 | packet = skb->data; | |
1174 | ||
1175 | /* get the packet length */ | |
1176 | size = (u16)((header & RX_STS_FL_) >> 16); | |
1177 | align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4; | |
1178 | ||
1179 | if (unlikely(header & RX_STS_ES_)) { | |
a475f603 JP |
1180 | netif_dbg(dev, rx_err, dev->net, |
1181 | "Error header=0x%08x\n", header); | |
80667ac1 HX |
1182 | dev->net->stats.rx_errors++; |
1183 | dev->net->stats.rx_dropped++; | |
2f7ca802 SG |
1184 | |
1185 | if (header & RX_STS_CRC_) { | |
80667ac1 | 1186 | dev->net->stats.rx_crc_errors++; |
2f7ca802 SG |
1187 | } else { |
1188 | if (header & (RX_STS_TL_ | RX_STS_RF_)) | |
80667ac1 | 1189 | dev->net->stats.rx_frame_errors++; |
2f7ca802 SG |
1190 | |
1191 | if ((header & RX_STS_LE_) && | |
1192 | (!(header & RX_STS_FT_))) | |
80667ac1 | 1193 | dev->net->stats.rx_length_errors++; |
2f7ca802 SG |
1194 | } |
1195 | } else { | |
1196 | /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */ | |
1197 | if (unlikely(size > (ETH_FRAME_LEN + 12))) { | |
a475f603 JP |
1198 | netif_dbg(dev, rx_err, dev->net, |
1199 | "size err header=0x%08x\n", header); | |
2f7ca802 SG |
1200 | return 0; |
1201 | } | |
1202 | ||
1203 | /* last frame in this batch */ | |
1204 | if (skb->len == size) { | |
78e47fe4 | 1205 | if (dev->net->features & NETIF_F_RXCSUM) |
2f7ca802 | 1206 | smsc95xx_rx_csum_offload(skb); |
df18acca | 1207 | skb_trim(skb, skb->len - 4); /* remove fcs */ |
2f7ca802 SG |
1208 | skb->truesize = size + sizeof(struct sk_buff); |
1209 | ||
1210 | return 1; | |
1211 | } | |
1212 | ||
1213 | ax_skb = skb_clone(skb, GFP_ATOMIC); | |
1214 | if (unlikely(!ax_skb)) { | |
60b86755 | 1215 | netdev_warn(dev->net, "Error allocating skb\n"); |
2f7ca802 SG |
1216 | return 0; |
1217 | } | |
1218 | ||
1219 | ax_skb->len = size; | |
1220 | ax_skb->data = packet; | |
1221 | skb_set_tail_pointer(ax_skb, size); | |
1222 | ||
78e47fe4 | 1223 | if (dev->net->features & NETIF_F_RXCSUM) |
2f7ca802 | 1224 | smsc95xx_rx_csum_offload(ax_skb); |
df18acca | 1225 | skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ |
2f7ca802 SG |
1226 | ax_skb->truesize = size + sizeof(struct sk_buff); |
1227 | ||
1228 | usbnet_skb_return(dev, ax_skb); | |
1229 | } | |
1230 | ||
1231 | skb_pull(skb, size); | |
1232 | ||
1233 | /* padding bytes before the next frame starts */ | |
1234 | if (skb->len) | |
1235 | skb_pull(skb, align_count); | |
1236 | } | |
1237 | ||
1238 | if (unlikely(skb->len < 0)) { | |
60b86755 | 1239 | netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len); |
2f7ca802 SG |
1240 | return 0; |
1241 | } | |
1242 | ||
1243 | return 1; | |
1244 | } | |
1245 | ||
f7b29271 SG |
1246 | static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb) |
1247 | { | |
55508d60 MM |
1248 | u16 low_16 = (u16)skb_checksum_start_offset(skb); |
1249 | u16 high_16 = low_16 + skb->csum_offset; | |
f7b29271 SG |
1250 | return (high_16 << 16) | low_16; |
1251 | } | |
1252 | ||
2f7ca802 SG |
1253 | static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev, |
1254 | struct sk_buff *skb, gfp_t flags) | |
1255 | { | |
78e47fe4 | 1256 | bool csum = skb->ip_summed == CHECKSUM_PARTIAL; |
f7b29271 | 1257 | int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD; |
2f7ca802 SG |
1258 | u32 tx_cmd_a, tx_cmd_b; |
1259 | ||
f7b29271 SG |
1260 | /* We do not advertise SG, so skbs should be already linearized */ |
1261 | BUG_ON(skb_shinfo(skb)->nr_frags); | |
1262 | ||
1263 | if (skb_headroom(skb) < overhead) { | |
2f7ca802 | 1264 | struct sk_buff *skb2 = skb_copy_expand(skb, |
f7b29271 | 1265 | overhead, 0, flags); |
2f7ca802 SG |
1266 | dev_kfree_skb_any(skb); |
1267 | skb = skb2; | |
1268 | if (!skb) | |
1269 | return NULL; | |
1270 | } | |
1271 | ||
f7b29271 | 1272 | if (csum) { |
11bc3088 SG |
1273 | if (skb->len <= 45) { |
1274 | /* workaround - hardware tx checksum does not work | |
1275 | * properly with extremely small packets */ | |
55508d60 | 1276 | long csstart = skb_checksum_start_offset(skb); |
11bc3088 SG |
1277 | __wsum calc = csum_partial(skb->data + csstart, |
1278 | skb->len - csstart, 0); | |
1279 | *((__sum16 *)(skb->data + csstart | |
1280 | + skb->csum_offset)) = csum_fold(calc); | |
1281 | ||
1282 | csum = false; | |
1283 | } else { | |
1284 | u32 csum_preamble = smsc95xx_calc_csum_preamble(skb); | |
1285 | skb_push(skb, 4); | |
1286 | memcpy(skb->data, &csum_preamble, 4); | |
1287 | } | |
f7b29271 SG |
1288 | } |
1289 | ||
2f7ca802 SG |
1290 | skb_push(skb, 4); |
1291 | tx_cmd_b = (u32)(skb->len - 4); | |
f7b29271 SG |
1292 | if (csum) |
1293 | tx_cmd_b |= TX_CMD_B_CSUM_ENABLE; | |
2f7ca802 SG |
1294 | cpu_to_le32s(&tx_cmd_b); |
1295 | memcpy(skb->data, &tx_cmd_b, 4); | |
1296 | ||
1297 | skb_push(skb, 4); | |
1298 | tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ | | |
1299 | TX_CMD_A_LAST_SEG_; | |
1300 | cpu_to_le32s(&tx_cmd_a); | |
1301 | memcpy(skb->data, &tx_cmd_a, 4); | |
1302 | ||
1303 | return skb; | |
1304 | } | |
1305 | ||
1306 | static const struct driver_info smsc95xx_info = { | |
1307 | .description = "smsc95xx USB 2.0 Ethernet", | |
1308 | .bind = smsc95xx_bind, | |
1309 | .unbind = smsc95xx_unbind, | |
1310 | .link_reset = smsc95xx_link_reset, | |
1311 | .reset = smsc95xx_reset, | |
1312 | .rx_fixup = smsc95xx_rx_fixup, | |
1313 | .tx_fixup = smsc95xx_tx_fixup, | |
1314 | .status = smsc95xx_status, | |
07d69d42 | 1315 | .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR, |
2f7ca802 SG |
1316 | }; |
1317 | ||
1318 | static const struct usb_device_id products[] = { | |
1319 | { | |
1320 | /* SMSC9500 USB Ethernet Device */ | |
1321 | USB_DEVICE(0x0424, 0x9500), | |
1322 | .driver_info = (unsigned long) &smsc95xx_info, | |
1323 | }, | |
6f41d12b SG |
1324 | { |
1325 | /* SMSC9505 USB Ethernet Device */ | |
1326 | USB_DEVICE(0x0424, 0x9505), | |
1327 | .driver_info = (unsigned long) &smsc95xx_info, | |
1328 | }, | |
1329 | { | |
1330 | /* SMSC9500A USB Ethernet Device */ | |
1331 | USB_DEVICE(0x0424, 0x9E00), | |
1332 | .driver_info = (unsigned long) &smsc95xx_info, | |
1333 | }, | |
1334 | { | |
1335 | /* SMSC9505A USB Ethernet Device */ | |
1336 | USB_DEVICE(0x0424, 0x9E01), | |
1337 | .driver_info = (unsigned long) &smsc95xx_info, | |
1338 | }, | |
726474b8 SG |
1339 | { |
1340 | /* SMSC9512/9514 USB Hub & Ethernet Device */ | |
1341 | USB_DEVICE(0x0424, 0xec00), | |
1342 | .driver_info = (unsigned long) &smsc95xx_info, | |
1343 | }, | |
6f41d12b SG |
1344 | { |
1345 | /* SMSC9500 USB Ethernet Device (SAL10) */ | |
1346 | USB_DEVICE(0x0424, 0x9900), | |
1347 | .driver_info = (unsigned long) &smsc95xx_info, | |
1348 | }, | |
1349 | { | |
1350 | /* SMSC9505 USB Ethernet Device (SAL10) */ | |
1351 | USB_DEVICE(0x0424, 0x9901), | |
1352 | .driver_info = (unsigned long) &smsc95xx_info, | |
1353 | }, | |
1354 | { | |
1355 | /* SMSC9500A USB Ethernet Device (SAL10) */ | |
1356 | USB_DEVICE(0x0424, 0x9902), | |
1357 | .driver_info = (unsigned long) &smsc95xx_info, | |
1358 | }, | |
1359 | { | |
1360 | /* SMSC9505A USB Ethernet Device (SAL10) */ | |
1361 | USB_DEVICE(0x0424, 0x9903), | |
1362 | .driver_info = (unsigned long) &smsc95xx_info, | |
1363 | }, | |
1364 | { | |
1365 | /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */ | |
1366 | USB_DEVICE(0x0424, 0x9904), | |
1367 | .driver_info = (unsigned long) &smsc95xx_info, | |
1368 | }, | |
1369 | { | |
1370 | /* SMSC9500A USB Ethernet Device (HAL) */ | |
1371 | USB_DEVICE(0x0424, 0x9905), | |
1372 | .driver_info = (unsigned long) &smsc95xx_info, | |
1373 | }, | |
1374 | { | |
1375 | /* SMSC9505A USB Ethernet Device (HAL) */ | |
1376 | USB_DEVICE(0x0424, 0x9906), | |
1377 | .driver_info = (unsigned long) &smsc95xx_info, | |
1378 | }, | |
1379 | { | |
1380 | /* SMSC9500 USB Ethernet Device (Alternate ID) */ | |
1381 | USB_DEVICE(0x0424, 0x9907), | |
1382 | .driver_info = (unsigned long) &smsc95xx_info, | |
1383 | }, | |
1384 | { | |
1385 | /* SMSC9500A USB Ethernet Device (Alternate ID) */ | |
1386 | USB_DEVICE(0x0424, 0x9908), | |
1387 | .driver_info = (unsigned long) &smsc95xx_info, | |
1388 | }, | |
1389 | { | |
1390 | /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */ | |
1391 | USB_DEVICE(0x0424, 0x9909), | |
1392 | .driver_info = (unsigned long) &smsc95xx_info, | |
1393 | }, | |
88edaa41 SG |
1394 | { |
1395 | /* SMSC LAN9530 USB Ethernet Device */ | |
1396 | USB_DEVICE(0x0424, 0x9530), | |
1397 | .driver_info = (unsigned long) &smsc95xx_info, | |
1398 | }, | |
1399 | { | |
1400 | /* SMSC LAN9730 USB Ethernet Device */ | |
1401 | USB_DEVICE(0x0424, 0x9730), | |
1402 | .driver_info = (unsigned long) &smsc95xx_info, | |
1403 | }, | |
1404 | { | |
1405 | /* SMSC LAN89530 USB Ethernet Device */ | |
1406 | USB_DEVICE(0x0424, 0x9E08), | |
1407 | .driver_info = (unsigned long) &smsc95xx_info, | |
1408 | }, | |
2f7ca802 SG |
1409 | { }, /* END */ |
1410 | }; | |
1411 | MODULE_DEVICE_TABLE(usb, products); | |
1412 | ||
1413 | static struct usb_driver smsc95xx_driver = { | |
1414 | .name = "smsc95xx", | |
1415 | .id_table = products, | |
1416 | .probe = usbnet_probe, | |
b5a04475 | 1417 | .suspend = smsc95xx_suspend, |
e0e474a8 SG |
1418 | .resume = smsc95xx_resume, |
1419 | .reset_resume = smsc95xx_resume, | |
2f7ca802 | 1420 | .disconnect = usbnet_disconnect, |
e1f12eb6 | 1421 | .disable_hub_initiated_lpm = 1, |
2f7ca802 SG |
1422 | }; |
1423 | ||
d632eb1b | 1424 | module_usb_driver(smsc95xx_driver); |
2f7ca802 SG |
1425 | |
1426 | MODULE_AUTHOR("Nancy Lin"); | |
90b24cfb | 1427 | MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); |
2f7ca802 SG |
1428 | MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices"); |
1429 | MODULE_LICENSE("GPL"); |