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[deliverable/linux.git] / drivers / net / usb / smsc95xx.c
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2f7ca802
SG		 1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 *****************************************************************************/
20
21#include <linux/module.h>
22#include <linux/kmod.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/mii.h>
28#include <linux/usb.h>
29#include <linux/crc32.h>
30#include <linux/usb/usbnet.h>
31#include "smsc95xx.h"
32
33#define SMSC_CHIPNAME "smsc95xx"
34#define SMSC_DRIVER_VERSION "1.0.3"
35#define HS_USB_PKT_SIZE (512)
36#define FS_USB_PKT_SIZE (64)
37#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
38#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
39#define DEFAULT_BULK_IN_DELAY (0x00002000)
40#define MAX_SINGLE_PACKET_SIZE (2048)
41#define LAN95XX_EEPROM_MAGIC (0x9500)
42#define EEPROM_MAC_OFFSET (0x01)
43#define DEFAULT_RX_CSUM_ENABLE (true)
44#define SMSC95XX_INTERNAL_PHY_ID (1)
45#define SMSC95XX_TX_OVERHEAD (8)
46#define FLOW_CTRL_TX (1)
47#define FLOW_CTRL_RX (2)
48
49struct smsc95xx_priv {
50 u32 mac_cr;
51 spinlock_t mac_cr_lock;
52 bool use_rx_csum;
53};
54
55struct usb_context {
56 struct usb_ctrlrequest req;
57 struct completion notify;
58 struct usbnet *dev;
59};
60
61int turbo_mode = true;
62module_param(turbo_mode, bool, 0644);
63MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
64
65static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
66{
67 u32 *buf = kmalloc(4, GFP_KERNEL);
68 int ret;
69
70 BUG_ON(!dev);
71
72 if (!buf)
73 return -ENOMEM;
74
75 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
76 USB_VENDOR_REQUEST_READ_REGISTER,
77 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
78 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
79
80 if (unlikely(ret < 0))
81 devwarn(dev, "Failed to read register index 0x%08x", index);
82
83 le32_to_cpus(buf);
84 *data = *buf;
85 kfree(buf);
86
87 return ret;
88}
89
90static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
91{
92 u32 *buf = kmalloc(4, GFP_KERNEL);
93 int ret;
94
95 BUG_ON(!dev);
96
97 if (!buf)
98 return -ENOMEM;
99
100 *buf = data;
101 cpu_to_le32s(buf);
102
103 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
104 USB_VENDOR_REQUEST_WRITE_REGISTER,
105 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
106 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
107
108 if (unlikely(ret < 0))
109 devwarn(dev, "Failed to write register index 0x%08x", index);
110
111 kfree(buf);
112
113 return ret;
114}
115
116/* Loop until the read is completed with timeout
117 * called with phy_mutex held */
118static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
119{
120 unsigned long start_time = jiffies;
121 u32 val;
122
123 do {
124 smsc95xx_read_reg(dev, MII_ADDR, &val);
125 if (!(val & MII_BUSY_))
126 return 0;
127 } while (!time_after(jiffies, start_time + HZ));
128
129 return -EIO;
130}
131
132static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
133{
134 struct usbnet *dev = netdev_priv(netdev);
135 u32 val, addr;
136
137 mutex_lock(&dev->phy_mutex);
138
139 /* confirm MII not busy */
140 if (smsc95xx_phy_wait_not_busy(dev)) {
141 devwarn(dev, "MII is busy in smsc95xx_mdio_read");
142 mutex_unlock(&dev->phy_mutex);
143 return -EIO;
144 }
145
146 /* set the address, index & direction (read from PHY) */
147 phy_id &= dev->mii.phy_id_mask;
148 idx &= dev->mii.reg_num_mask;
149 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
150 smsc95xx_write_reg(dev, MII_ADDR, addr);
151
152 if (smsc95xx_phy_wait_not_busy(dev)) {
153 devwarn(dev, "Timed out reading MII reg %02X", idx);
154 mutex_unlock(&dev->phy_mutex);
155 return -EIO;
156 }
157
158 smsc95xx_read_reg(dev, MII_DATA, &val);
159
160 mutex_unlock(&dev->phy_mutex);
161
162 return (u16)(val & 0xFFFF);
163}
164
165static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
166 int regval)
167{
168 struct usbnet *dev = netdev_priv(netdev);
169 u32 val, addr;
170
171 mutex_lock(&dev->phy_mutex);
172
173 /* confirm MII not busy */
174 if (smsc95xx_phy_wait_not_busy(dev)) {
175 devwarn(dev, "MII is busy in smsc95xx_mdio_write");
176 mutex_unlock(&dev->phy_mutex);
177 return;
178 }
179
180 val = regval;
181 smsc95xx_write_reg(dev, MII_DATA, val);
182
183 /* set the address, index & direction (write to PHY) */
184 phy_id &= dev->mii.phy_id_mask;
185 idx &= dev->mii.reg_num_mask;
186 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
187 smsc95xx_write_reg(dev, MII_ADDR, addr);
188
189 if (smsc95xx_phy_wait_not_busy(dev))
190 devwarn(dev, "Timed out writing MII reg %02X", idx);
191
192 mutex_unlock(&dev->phy_mutex);
193}
194
195static int smsc95xx_wait_eeprom(struct usbnet *dev)
196{
197 unsigned long start_time = jiffies;
198 u32 val;
199
200 do {
201 smsc95xx_read_reg(dev, E2P_CMD, &val);
202 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
203 break;
204 udelay(40);
205 } while (!time_after(jiffies, start_time + HZ));
206
207 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
208 devwarn(dev, "EEPROM read operation timeout");
209 return -EIO;
210 }
211
212 return 0;
213}
214
215static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
216{
217 unsigned long start_time = jiffies;
218 u32 val;
219
220 do {
221 smsc95xx_read_reg(dev, E2P_CMD, &val);
222
223 if (!(val & E2P_CMD_LOADED_)) {
224 devwarn(dev, "No EEPROM present");
225 return -EIO;
226 }
227
228 if (!(val & E2P_CMD_BUSY_))
229 return 0;
230
231 udelay(40);
232 } while (!time_after(jiffies, start_time + HZ));
233
234 devwarn(dev, "EEPROM is busy");
235 return -EIO;
236}
237
238static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
239 u8 *data)
240{
241 u32 val;
242 int i, ret;
243
244 BUG_ON(!dev);
245 BUG_ON(!data);
246
247 ret = smsc95xx_eeprom_confirm_not_busy(dev);
248 if (ret)
249 return ret;
250
251 for (i = 0; i < length; i++) {
252 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
253 smsc95xx_write_reg(dev, E2P_CMD, val);
254
255 ret = smsc95xx_wait_eeprom(dev);
256 if (ret < 0)
257 return ret;
258
259 smsc95xx_read_reg(dev, E2P_DATA, &val);
260
261 data[i] = val & 0xFF;
262 offset++;
263 }
264
265 return 0;
266}
267
268static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
269 u8 *data)
270{
271 u32 val;
272 int i, ret;
273
274 BUG_ON(!dev);
275 BUG_ON(!data);
276
277 ret = smsc95xx_eeprom_confirm_not_busy(dev);
278 if (ret)
279 return ret;
280
281 /* Issue write/erase enable command */
282 val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
283 smsc95xx_write_reg(dev, E2P_CMD, val);
284
285 ret = smsc95xx_wait_eeprom(dev);
286 if (ret < 0)
287 return ret;
288
289 for (i = 0; i < length; i++) {
290
291 /* Fill data register */
292 val = data[i];
293 smsc95xx_write_reg(dev, E2P_DATA, val);
294
295 /* Send "write" command */
296 val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
297 smsc95xx_write_reg(dev, E2P_CMD, val);
298
299 ret = smsc95xx_wait_eeprom(dev);
300 if (ret < 0)
301 return ret;
302
303 offset++;
304 }
305
306 return 0;
307}
308
309static void smsc95xx_async_cmd_callback(struct urb *urb, struct pt_regs *regs)
310{
311 struct usb_context *usb_context = urb->context;
312 struct usbnet *dev = usb_context->dev;
313
314 if (urb->status < 0)
315 devwarn(dev, "async callback failed with %d", urb->status);
316
317 complete(&usb_context->notify);
318
319 kfree(usb_context);
320 usb_free_urb(urb);
321}
322
1d74a6bd 323static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
2f7ca802
SG		 324{
325 struct usb_context *usb_context;
326 int status;
327 struct urb *urb;
1d74a6bd 328 const u16 size = 4;
2f7ca802
SG		 329
330 urb = usb_alloc_urb(0, GFP_ATOMIC);
331 if (!urb) {
332 devwarn(dev, "Error allocating URB");
333 return -ENOMEM;
334 }
335
336 usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
337 if (usb_context == NULL) {
338 devwarn(dev, "Error allocating control msg");
339 usb_free_urb(urb);
340 return -ENOMEM;
341 }
342
343 usb_context->req.bRequestType =
344 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
345 usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
346 usb_context->req.wValue = 00;
1d74a6bd
SG		 347 usb_context->req.wIndex = cpu_to_le16(index);
348 usb_context->req.wLength = cpu_to_le16(size);
2f7ca802
SG		 349 init_completion(&usb_context->notify);
350
351 usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
352 (void *)&usb_context->req, data, size,
353 (usb_complete_t)smsc95xx_async_cmd_callback,
354 (void *)usb_context);
355
356 status = usb_submit_urb(urb, GFP_ATOMIC);
357 if (status < 0) {
358 devwarn(dev, "Error submitting control msg, sts=%d", status);
359 kfree(usb_context);
360 usb_free_urb(urb);
361 }
362
363 return status;
364}
365
366/* returns hash bit number for given MAC address
367 * example:
368 * 01 00 5E 00 00 01 -> returns bit number 31 */
369static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
370{
371 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
372}
373
374static void smsc95xx_set_multicast(struct net_device *netdev)
375{
376 struct usbnet *dev = netdev_priv(netdev);
377 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
378 u32 hash_hi = 0;
379 u32 hash_lo = 0;
380 unsigned long flags;
381
382 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
383
384 if (dev->net->flags & IFF_PROMISC) {
385 if (netif_msg_drv(dev))
386 devdbg(dev, "promiscuous mode enabled");
387 pdata->mac_cr |= MAC_CR_PRMS_;
388 pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
389 } else if (dev->net->flags & IFF_ALLMULTI) {
390 if (netif_msg_drv(dev))
391 devdbg(dev, "receive all multicast enabled");
392 pdata->mac_cr |= MAC_CR_MCPAS_;
393 pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
394 } else if (dev->net->mc_count > 0) {
395 struct dev_mc_list *mc_list = dev->net->mc_list;
396 int count = 0;
397
398 pdata->mac_cr |= MAC_CR_HPFILT_;
399 pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
400
401 while (mc_list) {
402 count++;
403 if (mc_list->dmi_addrlen == ETH_ALEN) {
404 u32 bitnum = smsc95xx_hash(mc_list->dmi_addr);
405 u32 mask = 0x01 << (bitnum & 0x1F);
406 if (bitnum & 0x20)
407 hash_hi |= mask;
408 else
409 hash_lo |= mask;
410 } else {
411 devwarn(dev, "dmi_addrlen != 6");
412 }
413 mc_list = mc_list->next;
414 }
415
416 if (count != ((u32)dev->net->mc_count))
417 devwarn(dev, "mc_count != dev->mc_count");
418
419 if (netif_msg_drv(dev))
420 devdbg(dev, "HASHH=0x%08X, HASHL=0x%08X", hash_hi,
421 hash_lo);
422 } else {
423 if (netif_msg_drv(dev))
424 devdbg(dev, "receive own packets only");
425 pdata->mac_cr &=
426 ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
427 }
428
429 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
430
431 /* Initiate async writes, as we can't wait for completion here */
432 smsc95xx_write_reg_async(dev, HASHH, &hash_hi);
433 smsc95xx_write_reg_async(dev, HASHL, &hash_lo);
434 smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
435}
436
437static u8 smsc95xx_resolve_flowctrl_fulldplx(u16 lcladv, u16 rmtadv)
438{
439 u8 cap = 0;
440
441 if (lcladv & ADVERTISE_PAUSE_CAP) {
442 if (lcladv & ADVERTISE_PAUSE_ASYM) {
443 if (rmtadv & LPA_PAUSE_CAP)
444 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
445 else if (rmtadv & LPA_PAUSE_ASYM)
446 cap = FLOW_CTRL_RX;
447 } else {
448 if (rmtadv & LPA_PAUSE_CAP)
449 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
450 }
451 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
452 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
453 cap = FLOW_CTRL_TX;
454 }
455
456 return cap;
457}
458
459static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
460 u16 lcladv, u16 rmtadv)
461{
462 u32 flow, afc_cfg = 0;
463
464 int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
465 if (ret < 0) {
466 devwarn(dev, "error reading AFC_CFG");
467 return;
468 }
469
470 if (duplex == DUPLEX_FULL) {
471 u8 cap = smsc95xx_resolve_flowctrl_fulldplx(lcladv, rmtadv);
472
473 if (cap & FLOW_CTRL_RX)
474 flow = 0xFFFF0002;
475 else
476 flow = 0;
477
478 if (cap & FLOW_CTRL_TX)
479 afc_cfg |= 0xF;
480 else
481 afc_cfg &= ~0xF;
482
483 if (netif_msg_link(dev))
484 devdbg(dev, "rx pause %s, tx pause %s",
485 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
486 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
487 } else {
488 if (netif_msg_link(dev))
489 devdbg(dev, "half duplex");
490 flow = 0;
491 afc_cfg |= 0xF;
492 }
493
494 smsc95xx_write_reg(dev, FLOW, flow);
495 smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
496}
497
498static int smsc95xx_link_reset(struct usbnet *dev)
499{
500 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
501 struct mii_if_info *mii = &dev->mii;
502 struct ethtool_cmd ecmd;
503 unsigned long flags;
504 u16 lcladv, rmtadv;
505 u32 intdata;
506
507 /* clear interrupt status */
508 smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
509 intdata = 0xFFFFFFFF;
510 smsc95xx_write_reg(dev, INT_STS, intdata);
511
512 mii_check_media(mii, 1, 1);
513 mii_ethtool_gset(&dev->mii, &ecmd);
514 lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
515 rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
516
517 if (netif_msg_link(dev))
518 devdbg(dev, "speed: %d duplex: %d lcladv: %04x rmtadv: %04x",
519 ecmd.speed, ecmd.duplex, lcladv, rmtadv);
520
521 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
522 if (ecmd.duplex != DUPLEX_FULL) {
523 pdata->mac_cr &= ~MAC_CR_FDPX_;
524 pdata->mac_cr |= MAC_CR_RCVOWN_;
525 } else {
526 pdata->mac_cr &= ~MAC_CR_RCVOWN_;
527 pdata->mac_cr |= MAC_CR_FDPX_;
528 }
529 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
530
531 smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
532
533 smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
534
535 return 0;
536}
537
538static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
539{
540 u32 intdata;
541
542 if (urb->actual_length != 4) {
543 devwarn(dev, "unexpected urb length %d", urb->actual_length);
544 return;
545 }
546
547 memcpy(&intdata, urb->transfer_buffer, 4);
1d74a6bd 548 le32_to_cpus(&intdata);
2f7ca802
SG		 549
550 if (netif_msg_link(dev))
551 devdbg(dev, "intdata: 0x%08X", intdata);
552
553 if (intdata & INT_ENP_PHY_INT_)
554 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
555 else
556 devwarn(dev, "unexpected interrupt, intdata=0x%08X", intdata);
557}
558
559/* Enable or disable Rx checksum offload engine */
560static int smsc95xx_set_rx_csum(struct usbnet *dev, bool enable)
561{
562 u32 read_buf;
563 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
564 if (ret < 0) {
565 devwarn(dev, "Failed to read COE_CR: %d", ret);
566 return ret;
567 }
568
569 if (enable)
570 read_buf |= Rx_COE_EN_;
571 else
572 read_buf &= ~Rx_COE_EN_;
573
574 ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
575 if (ret < 0) {
576 devwarn(dev, "Failed to write COE_CR: %d", ret);
577 return ret;
578 }
579
580 if (netif_msg_hw(dev))
581 devdbg(dev, "COE_CR = 0x%08x", read_buf);
582 return 0;
583}
584
585static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
586{
587 return MAX_EEPROM_SIZE;
588}
589
590static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
591 struct ethtool_eeprom *ee, u8 *data)
592{
593 struct usbnet *dev = netdev_priv(netdev);
594
595 ee->magic = LAN95XX_EEPROM_MAGIC;
596
597 return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
598}
599
600static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
601 struct ethtool_eeprom *ee, u8 *data)
602{
603 struct usbnet *dev = netdev_priv(netdev);
604
605 if (ee->magic != LAN95XX_EEPROM_MAGIC) {
606 devwarn(dev, "EEPROM: magic value mismatch, magic = 0x%x",
607 ee->magic);
608 return -EINVAL;
609 }
610
611 return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
612}
613
614static u32 smsc95xx_ethtool_get_rx_csum(struct net_device *netdev)
615{
616 struct usbnet *dev = netdev_priv(netdev);
617 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
618
619 return pdata->use_rx_csum;
620}
621
622static int smsc95xx_ethtool_set_rx_csum(struct net_device *netdev, u32 val)
623{
624 struct usbnet *dev = netdev_priv(netdev);
625 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
626
627 pdata->use_rx_csum = !!val;
628
629 return smsc95xx_set_rx_csum(dev, pdata->use_rx_csum);
630}
631
632static struct ethtool_ops smsc95xx_ethtool_ops = {
633 .get_link = usbnet_get_link,
634 .nway_reset = usbnet_nway_reset,
635 .get_drvinfo = usbnet_get_drvinfo,
636 .get_msglevel = usbnet_get_msglevel,
637 .set_msglevel = usbnet_set_msglevel,
638 .get_settings = usbnet_get_settings,
639 .set_settings = usbnet_set_settings,
640 .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
641 .get_eeprom = smsc95xx_ethtool_get_eeprom,
642 .set_eeprom = smsc95xx_ethtool_set_eeprom,
643 .get_rx_csum = smsc95xx_ethtool_get_rx_csum,
644 .set_rx_csum = smsc95xx_ethtool_set_rx_csum,
645};
646
647static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
648{
649 struct usbnet *dev = netdev_priv(netdev);
650
651 if (!netif_running(netdev))
652 return -EINVAL;
653
654 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
655}
656
657static void smsc95xx_init_mac_address(struct usbnet *dev)
658{
659 /* try reading mac address from EEPROM */
660 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
661 dev->net->dev_addr) == 0) {
662 if (is_valid_ether_addr(dev->net->dev_addr)) {
663 /* eeprom values are valid so use them */
664 if (netif_msg_ifup(dev))
665 devdbg(dev, "MAC address read from EEPROM");
666 return;
667 }
668 }
669
670 /* no eeprom, or eeprom values are invalid. generate random MAC */
671 random_ether_addr(dev->net->dev_addr);
672 if (netif_msg_ifup(dev))
673 devdbg(dev, "MAC address set to random_ether_addr");
674}
675
676static int smsc95xx_set_mac_address(struct usbnet *dev)
677{
678 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
679 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
680 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
681 int ret;
682
683 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
684 if (ret < 0) {
685 devwarn(dev, "Failed to write ADDRL: %d", ret);
686 return ret;
687 }
688
689 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
690 if (ret < 0) {
691 devwarn(dev, "Failed to write ADDRH: %d", ret);
692 return ret;
693 }
694
695 return 0;
696}
697
698/* starts the TX path */
699static void smsc95xx_start_tx_path(struct usbnet *dev)
700{
701 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
702 unsigned long flags;
703 u32 reg_val;
704
705 /* Enable Tx at MAC */
706 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
707 pdata->mac_cr |= MAC_CR_TXEN_;
708 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
709
710 smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
711
712 /* Enable Tx at SCSRs */
713 reg_val = TX_CFG_ON_;
714 smsc95xx_write_reg(dev, TX_CFG, reg_val);
715}
716
717/* Starts the Receive path */
718static void smsc95xx_start_rx_path(struct usbnet *dev)
719{
720 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
721 unsigned long flags;
722
723 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
724 pdata->mac_cr |= MAC_CR_RXEN_;
725 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
726
727 smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
728}
729
730static int smsc95xx_phy_initialize(struct usbnet *dev)
731{
732 /* Initialize MII structure */
733 dev->mii.dev = dev->net;
734 dev->mii.mdio_read = smsc95xx_mdio_read;
735 dev->mii.mdio_write = smsc95xx_mdio_write;
736 dev->mii.phy_id_mask = 0x1f;
737 dev->mii.reg_num_mask = 0x1f;
738 dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
739
740 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
741 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
742 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
743 ADVERTISE_PAUSE_ASYM);
744
745 /* read to clear */
746 smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
747
748 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
749 PHY_INT_MASK_DEFAULT_);
750 mii_nway_restart(&dev->mii);
751
752 if (netif_msg_ifup(dev))
753 devdbg(dev, "phy initialised succesfully");
754 return 0;
755}
756
757static int smsc95xx_reset(struct usbnet *dev)
758{
759 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
760 u32 read_buf, write_buf, burst_cap;
761 int ret = 0, timeout;
2f7ca802
SG		 762
763 if (netif_msg_ifup(dev))
764 devdbg(dev, "entering smsc95xx_reset");
765
766 write_buf = HW_CFG_LRST_;
767 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
768 if (ret < 0) {
769 devwarn(dev, "Failed to write HW_CFG_LRST_ bit in HW_CFG "
770 "register, ret = %d", ret);
771 return ret;
772 }
773
774 timeout = 0;
775 do {
776 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
777 if (ret < 0) {
778 devwarn(dev, "Failed to read HW_CFG: %d", ret);
779 return ret;
780 }
781 msleep(10);
782 timeout++;
783 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
784
785 if (timeout >= 100) {
786 devwarn(dev, "timeout waiting for completion of Lite Reset");
787 return ret;
788 }
789
790 write_buf = PM_CTL_PHY_RST_;
791 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
792 if (ret < 0) {
793 devwarn(dev, "Failed to write PM_CTRL: %d", ret);
794 return ret;
795 }
796
797 timeout = 0;
798 do {
799 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
800 if (ret < 0) {
801 devwarn(dev, "Failed to read PM_CTRL: %d", ret);
802 return ret;
803 }
804 msleep(10);
805 timeout++;
806 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
807
808 if (timeout >= 100) {
809 devwarn(dev, "timeout waiting for PHY Reset");
810 return ret;
811 }
812
813 smsc95xx_init_mac_address(dev);
814
815 ret = smsc95xx_set_mac_address(dev);
816 if (ret < 0)
817 return ret;
818
819 if (netif_msg_ifup(dev))
e174961c 820 devdbg(dev, "MAC Address: %pM", dev->net->dev_addr);
2f7ca802
SG		 821
822 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
823 if (ret < 0) {
824 devwarn(dev, "Failed to read HW_CFG: %d", ret);
825 return ret;
826 }
827
828 if (netif_msg_ifup(dev))
829 devdbg(dev, "Read Value from HW_CFG : 0x%08x", read_buf);
830
831 read_buf |= HW_CFG_BIR_;
832
833 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
834 if (ret < 0) {
835 devwarn(dev, "Failed to write HW_CFG_BIR_ bit in HW_CFG "
836 "register, ret = %d", ret);
837 return ret;
838 }
839
840 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
841 if (ret < 0) {
842 devwarn(dev, "Failed to read HW_CFG: %d", ret);
843 return ret;
844 }
845 if (netif_msg_ifup(dev))
846 devdbg(dev, "Read Value from HW_CFG after writing "
847 "HW_CFG_BIR_: 0x%08x", read_buf);
848
849 if (!turbo_mode) {
850 burst_cap = 0;
851 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
852 } else if (dev->udev->speed == USB_SPEED_HIGH) {
853 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
854 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
855 } else {
856 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
857 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
858 }
859
860 if (netif_msg_ifup(dev))
861 devdbg(dev, "rx_urb_size=%ld", (ulong)dev->rx_urb_size);
862
863 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
864 if (ret < 0) {
865 devwarn(dev, "Failed to write BURST_CAP: %d", ret);
866 return ret;
867 }
868
869 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
870 if (ret < 0) {
871 devwarn(dev, "Failed to read BURST_CAP: %d", ret);
872 return ret;
873 }
874 if (netif_msg_ifup(dev))
875 devdbg(dev, "Read Value from BURST_CAP after writing: 0x%08x",
876 read_buf);
877
878 read_buf = DEFAULT_BULK_IN_DELAY;
879 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
880 if (ret < 0) {
881 devwarn(dev, "ret = %d", ret);
882 return ret;
883 }
884
885 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
886 if (ret < 0) {
887 devwarn(dev, "Failed to read BULK_IN_DLY: %d", ret);
888 return ret;
889 }
890 if (netif_msg_ifup(dev))
891 devdbg(dev, "Read Value from BULK_IN_DLY after writing: "
892 "0x%08x", read_buf);
893
894 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
895 if (ret < 0) {
896 devwarn(dev, "Failed to read HW_CFG: %d", ret);
897 return ret;
898 }
899 if (netif_msg_ifup(dev))
900 devdbg(dev, "Read Value from HW_CFG: 0x%08x", read_buf);
901
902 if (turbo_mode)
903 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
904
905 read_buf &= ~HW_CFG_RXDOFF_;
906
907 /* set Rx data offset=2, Make IP header aligns on word boundary. */
908 read_buf |= NET_IP_ALIGN << 9;
909
910 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
911 if (ret < 0) {
912 devwarn(dev, "Failed to write HW_CFG register, ret=%d", ret);
913 return ret;
914 }
915
916 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
917 if (ret < 0) {
918 devwarn(dev, "Failed to read HW_CFG: %d", ret);
919 return ret;
920 }
921 if (netif_msg_ifup(dev))
922 devdbg(dev, "Read Value from HW_CFG after writing: 0x%08x",
923 read_buf);
924
925 write_buf = 0xFFFFFFFF;
926 ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
927 if (ret < 0) {
928 devwarn(dev, "Failed to write INT_STS register, ret=%d", ret);
929 return ret;
930 }
931
932 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
933 if (ret < 0) {
934 devwarn(dev, "Failed to read ID_REV: %d", ret);
935 return ret;
936 }
937 if (netif_msg_ifup(dev))
938 devdbg(dev, "ID_REV = 0x%08x", read_buf);
939
940 /* Init Tx */
941 write_buf = 0;
942 ret = smsc95xx_write_reg(dev, FLOW, write_buf);
943 if (ret < 0) {
944 devwarn(dev, "Failed to write FLOW: %d", ret);
945 return ret;
946 }
947
948 read_buf = AFC_CFG_DEFAULT;
949 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
950 if (ret < 0) {
951 devwarn(dev, "Failed to write AFC_CFG: %d", ret);
952 return ret;
953 }
954
955 /* Don't need mac_cr_lock during initialisation */
956 ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
957 if (ret < 0) {
958 devwarn(dev, "Failed to read MAC_CR: %d", ret);
959 return ret;
960 }
961
962 /* Init Rx */
963 /* Set Vlan */
964 write_buf = (u32)ETH_P_8021Q;
965 ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
966 if (ret < 0) {
967 devwarn(dev, "Failed to write VAN1: %d", ret);
968 return ret;
969 }
970
971 /* Enable or disable Rx checksum offload engine */
972 ret = smsc95xx_set_rx_csum(dev, pdata->use_rx_csum);
973 if (ret < 0) {
974 devwarn(dev, "Failed to set Rx csum offload: %d", ret);
975 return ret;
976 }
977
978 smsc95xx_set_multicast(dev->net);
979
980 if (smsc95xx_phy_initialize(dev) < 0)
981 return -EIO;
982
983 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
984 if (ret < 0) {
985 devwarn(dev, "Failed to read INT_EP_CTL: %d", ret);
986 return ret;
987 }
988
989 /* enable PHY interrupts */
990 read_buf |= INT_EP_CTL_PHY_INT_;
991
992 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
993 if (ret < 0) {
994 devwarn(dev, "Failed to write INT_EP_CTL: %d", ret);
995 return ret;
996 }
997
998 smsc95xx_start_tx_path(dev);
999 smsc95xx_start_rx_path(dev);
1000
1001 if (netif_msg_ifup(dev))
1002 devdbg(dev, "smsc95xx_reset, return 0");
1003 return 0;
1004}
1005
1006static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
1007{
1008 struct smsc95xx_priv *pdata = NULL;
1009 int ret;
1010
1011 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1012
1013 ret = usbnet_get_endpoints(dev, intf);
1014 if (ret < 0) {
1015 devwarn(dev, "usbnet_get_endpoints failed: %d", ret);
1016 return ret;
1017 }
1018
1019 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
1020 GFP_KERNEL);
1021
1022 pdata = (struct smsc95xx_priv *)(dev->data[0]);
1023 if (!pdata) {
1024 devwarn(dev, "Unable to allocate struct smsc95xx_priv");
1025 return -ENOMEM;
1026 }
1027
1028 spin_lock_init(&pdata->mac_cr_lock);
1029
1030 pdata->use_rx_csum = DEFAULT_RX_CSUM_ENABLE;
1031
1032 /* Init all registers */
1033 ret = smsc95xx_reset(dev);
1034
1035 dev->net->do_ioctl = smsc95xx_ioctl;
1036 dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
1037 dev->net->set_multicast_list = smsc95xx_set_multicast;
1038 dev->net->flags |= IFF_MULTICAST;
1039 dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD;
1040 return 0;
1041}
1042
1043static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1044{
1045 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1046 if (pdata) {
1047 if (netif_msg_ifdown(dev))
1048 devdbg(dev, "free pdata");
1049 kfree(pdata);
1050 pdata = NULL;
1051 dev->data[0] = 0;
1052 }
1053}
1054
1055static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
1056{
1057 skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
1058 skb->ip_summed = CHECKSUM_COMPLETE;
1059 skb_trim(skb, skb->len - 2);
1060}
1061
1062static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
1063{
1064 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1065
1066 while (skb->len > 0) {
1067 u32 header, align_count;
1068 struct sk_buff *ax_skb;
1069 unsigned char *packet;
1070 u16 size;
1071
1072 memcpy(&header, skb->data, sizeof(header));
1073 le32_to_cpus(&header);
1074 skb_pull(skb, 4 + NET_IP_ALIGN);
1075 packet = skb->data;
1076
1077 /* get the packet length */
1078 size = (u16)((header & RX_STS_FL_) >> 16);
1079 align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
1080
1081 if (unlikely(header & RX_STS_ES_)) {
1082 if (netif_msg_rx_err(dev))
1083 devdbg(dev, "Error header=0x%08x", header);
1084 dev->stats.rx_errors++;
1085 dev->stats.rx_dropped++;
1086
1087 if (header & RX_STS_CRC_) {
1088 dev->stats.rx_crc_errors++;
1089 } else {
1090 if (header & (RX_STS_TL_ | RX_STS_RF_))
1091 dev->stats.rx_frame_errors++;
1092
1093 if ((header & RX_STS_LE_) &&
1094 (!(header & RX_STS_FT_)))
1095 dev->stats.rx_length_errors++;
1096 }
1097 } else {
1098 /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
1099 if (unlikely(size > (ETH_FRAME_LEN + 12))) {
1100 if (netif_msg_rx_err(dev))
1101 devdbg(dev, "size err header=0x%08x",
1102 header);
1103 return 0;
1104 }
1105
1106 /* last frame in this batch */
1107 if (skb->len == size) {
1108 if (pdata->use_rx_csum)
1109 smsc95xx_rx_csum_offload(skb);
1110
1111 skb->truesize = size + sizeof(struct sk_buff);
1112
1113 return 1;
1114 }
1115
1116 ax_skb = skb_clone(skb, GFP_ATOMIC);
1117 if (unlikely(!ax_skb)) {
1118 devwarn(dev, "Error allocating skb");
1119 return 0;
1120 }
1121
1122 ax_skb->len = size;
1123 ax_skb->data = packet;
1124 skb_set_tail_pointer(ax_skb, size);
1125
1126 if (pdata->use_rx_csum)
1127 smsc95xx_rx_csum_offload(ax_skb);
1128
1129 ax_skb->truesize = size + sizeof(struct sk_buff);
1130
1131 usbnet_skb_return(dev, ax_skb);
1132 }
1133
1134 skb_pull(skb, size);
1135
1136 /* padding bytes before the next frame starts */
1137 if (skb->len)
1138 skb_pull(skb, align_count);
1139 }
1140
1141 if (unlikely(skb->len < 0)) {
1142 devwarn(dev, "invalid rx length<0 %d", skb->len);
1143 return 0;
1144 }
1145
1146 return 1;
1147}
1148
1149static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
1150 struct sk_buff *skb, gfp_t flags)
1151{
1152 u32 tx_cmd_a, tx_cmd_b;
1153
1154 if (skb_headroom(skb) < SMSC95XX_TX_OVERHEAD) {
1155 struct sk_buff *skb2 = skb_copy_expand(skb,
1156 SMSC95XX_TX_OVERHEAD, 0, flags);
1157 dev_kfree_skb_any(skb);
1158 skb = skb2;
1159 if (!skb)
1160 return NULL;
1161 }
1162
1163 skb_push(skb, 4);
1164 tx_cmd_b = (u32)(skb->len - 4);
1165 cpu_to_le32s(&tx_cmd_b);
1166 memcpy(skb->data, &tx_cmd_b, 4);
1167
1168 skb_push(skb, 4);
1169 tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
1170 TX_CMD_A_LAST_SEG_;
1171 cpu_to_le32s(&tx_cmd_a);
1172 memcpy(skb->data, &tx_cmd_a, 4);
1173
1174 return skb;
1175}
1176
1177static const struct driver_info smsc95xx_info = {
1178 .description = "smsc95xx USB 2.0 Ethernet",
1179 .bind = smsc95xx_bind,
1180 .unbind = smsc95xx_unbind,
1181 .link_reset = smsc95xx_link_reset,
1182 .reset = smsc95xx_reset,
1183 .rx_fixup = smsc95xx_rx_fixup,
1184 .tx_fixup = smsc95xx_tx_fixup,
1185 .status = smsc95xx_status,
1186 .flags = FLAG_ETHER,
1187};
1188
1189static const struct usb_device_id products[] = {
1190 {
1191 /* SMSC9500 USB Ethernet Device */
1192 USB_DEVICE(0x0424, 0x9500),
1193 .driver_info = (unsigned long) &smsc95xx_info,
1194 },
1195 { }, /* END */
1196};
1197MODULE_DEVICE_TABLE(usb, products);
1198
1199static struct usb_driver smsc95xx_driver = {
1200 .name = "smsc95xx",
1201 .id_table = products,
1202 .probe = usbnet_probe,
1203 .suspend = usbnet_suspend,
1204 .resume = usbnet_resume,
1205 .disconnect = usbnet_disconnect,
1206};
1207
1208static int __init smsc95xx_init(void)
1209{
1210 return usb_register(&smsc95xx_driver);
1211}
1212module_init(smsc95xx_init);
1213
1214static void __exit smsc95xx_exit(void)
1215{
1216 usb_deregister(&smsc95xx_driver);
1217}
1218module_exit(smsc95xx_exit);
1219
1220MODULE_AUTHOR("Nancy Lin");
1221MODULE_AUTHOR("Steve Glendinning <steve.glendinning@smsc.com>");
1222MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
1223MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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