projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 2f7ca802 SG |
1 | /*************************************************************************** |
| 2 | * | |
| 3 | * Copyright (C) 2007-2008 SMSC | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or | |
| 6 | * modify it under the terms of the GNU General Public License | |
| 7 | * as published by the Free Software Foundation; either version 2 | |
| 8 | * of the License, or (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 18 | * | |
| 19 | *****************************************************************************/ | |
| 20 | ||
| 21 | #ifndef _SMSC95XX_H | |
| 22 | #define _SMSC95XX_H | |
| 23 | ||
| 24 | /* Tx command words */ | |
| 25 | #define TX_CMD_A_DATA_OFFSET_ (0x001F0000) | |
| 26 | #define TX_CMD_A_FIRST_SEG_ (0x00002000) | |
| 27 | #define TX_CMD_A_LAST_SEG_ (0x00001000) | |
| 28 | #define TX_CMD_A_BUF_SIZE_ (0x000007FF) | |
| 29 | ||
| 30 | #define TX_CMD_B_CSUM_ENABLE (0x00004000) | |
| 31 | #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000) | |
| 32 | #define TX_CMD_B_DISABLE_PADDING_ (0x00001000) | |
| 33 | #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF) | |
| 34 | ||
| 35 | /* Rx status word */ | |
| 36 | #define RX_STS_FF_ (0x40000000) /* Filter Fail */ | |
| 37 | #define RX_STS_FL_ (0x3FFF0000) /* Frame Length */ | |
| 38 | #define RX_STS_ES_ (0x00008000) /* Error Summary */ | |
| 39 | #define RX_STS_BF_ (0x00002000) /* Broadcast Frame */ | |
| 40 | #define RX_STS_LE_ (0x00001000) /* Length Error */ | |
| 41 | #define RX_STS_RF_ (0x00000800) /* Runt Frame */ | |
| 42 | #define RX_STS_MF_ (0x00000400) /* Multicast Frame */ | |
| 43 | #define RX_STS_TL_ (0x00000080) /* Frame too long */ | |
| 44 | #define RX_STS_CS_ (0x00000040) /* Collision Seen */ | |
| 45 | #define RX_STS_FT_ (0x00000020) /* Frame Type */ | |
| 46 | #define RX_STS_RW_ (0x00000010) /* Receive Watchdog */ | |
| 47 | #define RX_STS_ME_ (0x00000008) /* Mii Error */ | |
| 48 | #define RX_STS_DB_ (0x00000004) /* Dribbling */ | |
| 49 | #define RX_STS_CRC_ (0x00000002) /* CRC Error */ | |
| 50 | ||
| 51 | /* SCSRs */ | |
| 52 | #define ID_REV (0x00) | |
| 53 | #define ID_REV_CHIP_ID_MASK_ (0xFFFF0000) | |
| 54 | #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) | |
| 55 | #define ID_REV_CHIP_ID_9500_ (0x9500) | |
| bbd9f9ee SG |
56 | #define ID_REV_CHIP_ID_9500A_ (0x9E00) |
| 57 | #define ID_REV_CHIP_ID_9512_ (0xEC00) | |
| 2f7ca802 SG |
58 | |
| 59 | #define INT_STS (0x08) | |
| 60 | #define INT_STS_TX_STOP_ (0x00020000) | |
| 61 | #define INT_STS_RX_STOP_ (0x00010000) | |
| 62 | #define INT_STS_PHY_INT_ (0x00008000) | |
| 63 | #define INT_STS_TXE_ (0x00004000) | |
| 64 | #define INT_STS_TDFU_ (0x00002000) | |
| 65 | #define INT_STS_TDFO_ (0x00001000) | |
| 66 | #define INT_STS_RXDF_ (0x00000800) | |
| 67 | #define INT_STS_GPIOS_ (0x000007FF) | |
| 4436761b | 68 | #define INT_STS_CLEAR_ALL_ (0xFFFFFFFF) |
| 2f7ca802 SG |
69 | |
| 70 | #define RX_CFG (0x0C) | |
| 71 | #define RX_FIFO_FLUSH_ (0x00000001) | |
| 72 | ||
| 73 | #define TX_CFG (0x10) | |
| 74 | #define TX_CFG_ON_ (0x00000004) | |
| 75 | #define TX_CFG_STOP_ (0x00000002) | |
| 76 | #define TX_CFG_FIFO_FLUSH_ (0x00000001) | |
| 77 | ||
| 78 | #define HW_CFG (0x14) | |
| 79 | #define HW_CFG_BIR_ (0x00001000) | |
| 80 | #define HW_CFG_LEDB_ (0x00000800) | |
| 81 | #define HW_CFG_RXDOFF_ (0x00000600) | |
| 82 | #define HW_CFG_DRP_ (0x00000040) | |
| 83 | #define HW_CFG_MEF_ (0x00000020) | |
| 84 | #define HW_CFG_LRST_ (0x00000008) | |
| 85 | #define HW_CFG_PSEL_ (0x00000004) | |
| 86 | #define HW_CFG_BCE_ (0x00000002) | |
| 87 | #define HW_CFG_SRST_ (0x00000001) | |
| 88 | ||
| b5a04475 SG |
89 | #define RX_FIFO_INF (0x18) |
| 90 | ||
| 2f7ca802 | 91 | #define PM_CTRL (0x20) |
| b5a04475 | 92 | #define PM_CTL_RES_CLR_WKP_STS (0x00000200) |
| 2f7ca802 SG |
93 | #define PM_CTL_DEV_RDY_ (0x00000080) |
| 94 | #define PM_CTL_SUS_MODE_ (0x00000060) | |
| 95 | #define PM_CTL_SUS_MODE_0 (0x00000000) | |
| 96 | #define PM_CTL_SUS_MODE_1 (0x00000020) | |
| b5a04475 SG |
97 | #define PM_CTL_SUS_MODE_2 (0x00000040) |
| 98 | #define PM_CTL_SUS_MODE_3 (0x00000060) | |
| 2f7ca802 SG |
99 | #define PM_CTL_PHY_RST_ (0x00000010) |
| 100 | #define PM_CTL_WOL_EN_ (0x00000008) | |
| 101 | #define PM_CTL_ED_EN_ (0x00000004) | |
| 102 | #define PM_CTL_WUPS_ (0x00000003) | |
| 103 | #define PM_CTL_WUPS_NO_ (0x00000000) | |
| 104 | #define PM_CTL_WUPS_ED_ (0x00000001) | |
| 105 | #define PM_CTL_WUPS_WOL_ (0x00000002) | |
| 106 | #define PM_CTL_WUPS_MULTI_ (0x00000003) | |
| 107 | ||
| 108 | #define LED_GPIO_CFG (0x24) | |
| f293501c SG |
109 | #define LED_GPIO_CFG_SPD_LED (0x01000000) |
| 110 | #define LED_GPIO_CFG_LNK_LED (0x00100000) | |
| 111 | #define LED_GPIO_CFG_FDX_LED (0x00010000) | |
| 2f7ca802 SG |
112 | |
| 113 | #define GPIO_CFG (0x28) | |
| 114 | ||
| 115 | #define AFC_CFG (0x2C) | |
| 116 | ||
| 117 | /* Hi watermark = 15.5Kb (~10 mtu pkts) */ | |
| 118 | /* low watermark = 3k (~2 mtu pkts) */ | |
| 119 | /* backpressure duration = ~ 350us */ | |
| 120 | /* Apply FC on any frame. */ | |
| 121 | #define AFC_CFG_DEFAULT (0x00F830A1) | |
| 122 | ||
| 123 | #define E2P_CMD (0x30) | |
| 124 | #define E2P_CMD_BUSY_ (0x80000000) | |
| 125 | #define E2P_CMD_MASK_ (0x70000000) | |
| 126 | #define E2P_CMD_READ_ (0x00000000) | |
| 127 | #define E2P_CMD_EWDS_ (0x10000000) | |
| 128 | #define E2P_CMD_EWEN_ (0x20000000) | |
| 129 | #define E2P_CMD_WRITE_ (0x30000000) | |
| 130 | #define E2P_CMD_WRAL_ (0x40000000) | |
| 131 | #define E2P_CMD_ERASE_ (0x50000000) | |
| 132 | #define E2P_CMD_ERAL_ (0x60000000) | |
| 133 | #define E2P_CMD_RELOAD_ (0x70000000) | |
| 134 | #define E2P_CMD_TIMEOUT_ (0x00000400) | |
| 135 | #define E2P_CMD_LOADED_ (0x00000200) | |
| 136 | #define E2P_CMD_ADDR_ (0x000001FF) | |
| 137 | ||
| 138 | #define MAX_EEPROM_SIZE (512) | |
| 139 | ||
| 140 | #define E2P_DATA (0x34) | |
| 141 | #define E2P_DATA_MASK_ (0x000000FF) | |
| 142 | ||
| 143 | #define BURST_CAP (0x38) | |
| 144 | ||
| 145 | #define GPIO_WAKE (0x64) | |
| 146 | ||
| 147 | #define INT_EP_CTL (0x68) | |
| 148 | #define INT_EP_CTL_INTEP_ (0x80000000) | |
| 149 | #define INT_EP_CTL_MACRTO_ (0x00080000) | |
| 150 | #define INT_EP_CTL_TX_STOP_ (0x00020000) | |
| 151 | #define INT_EP_CTL_RX_STOP_ (0x00010000) | |
| 152 | #define INT_EP_CTL_PHY_INT_ (0x00008000) | |
| 153 | #define INT_EP_CTL_TXE_ (0x00004000) | |
| 154 | #define INT_EP_CTL_TDFU_ (0x00002000) | |
| 155 | #define INT_EP_CTL_TDFO_ (0x00001000) | |
| 156 | #define INT_EP_CTL_RXDF_ (0x00000800) | |
| 157 | #define INT_EP_CTL_GPIOS_ (0x000007FF) | |
| 158 | ||
| 159 | #define BULK_IN_DLY (0x6C) | |
| 160 | ||
| 161 | /* MAC CSRs */ | |
| 162 | #define MAC_CR (0x100) | |
| 163 | #define MAC_CR_RXALL_ (0x80000000) | |
| 164 | #define MAC_CR_RCVOWN_ (0x00800000) | |
| 165 | #define MAC_CR_LOOPBK_ (0x00200000) | |
| 166 | #define MAC_CR_FDPX_ (0x00100000) | |
| 167 | #define MAC_CR_MCPAS_ (0x00080000) | |
| 168 | #define MAC_CR_PRMS_ (0x00040000) | |
| 169 | #define MAC_CR_INVFILT_ (0x00020000) | |
| 170 | #define MAC_CR_PASSBAD_ (0x00010000) | |
| 171 | #define MAC_CR_HFILT_ (0x00008000) | |
| 172 | #define MAC_CR_HPFILT_ (0x00002000) | |
| 173 | #define MAC_CR_LCOLL_ (0x00001000) | |
| 174 | #define MAC_CR_BCAST_ (0x00000800) | |
| 175 | #define MAC_CR_DISRTY_ (0x00000400) | |
| 176 | #define MAC_CR_PADSTR_ (0x00000100) | |
| 177 | #define MAC_CR_BOLMT_MASK (0x000000C0) | |
| 178 | #define MAC_CR_DFCHK_ (0x00000020) | |
| 179 | #define MAC_CR_TXEN_ (0x00000008) | |
| 180 | #define MAC_CR_RXEN_ (0x00000004) | |
| 181 | ||
| 182 | #define ADDRH (0x104) | |
| 183 | ||
| 184 | #define ADDRL (0x108) | |
| 185 | ||
| 186 | #define HASHH (0x10C) | |
| 187 | ||
| 188 | #define HASHL (0x110) | |
| 189 | ||
| 190 | #define MII_ADDR (0x114) | |
| 191 | #define MII_WRITE_ (0x02) | |
| 192 | #define MII_BUSY_ (0x01) | |
| 193 | #define MII_READ_ (0x00) /* ~of MII Write bit */ | |
| 194 | ||
| 195 | #define MII_DATA (0x118) | |
| 196 | ||
| 197 | #define FLOW (0x11C) | |
| 198 | #define FLOW_FCPT_ (0xFFFF0000) | |
| 199 | #define FLOW_FCPASS_ (0x00000004) | |
| 200 | #define FLOW_FCEN_ (0x00000002) | |
| 201 | #define FLOW_FCBSY_ (0x00000001) | |
| 202 | ||
| 203 | #define VLAN1 (0x120) | |
| 204 | ||
| 205 | #define VLAN2 (0x124) | |
| 206 | ||
| 207 | #define WUFF (0x128) | |
| bbd9f9ee SG |
208 | #define LAN9500_WUFF_NUM (4) |
| 209 | #define LAN9500A_WUFF_NUM (8) | |
| 2f7ca802 SG |
210 | |
| 211 | #define WUCSR (0x12C) | |
| bbd9f9ee | 212 | #define WUCSR_WFF_PTR_RST_ (0x80000000) |
| e0e474a8 SG |
213 | #define WUCSR_GUE_ (0x00000200) |
| 214 | #define WUCSR_WUFR_ (0x00000040) | |
| 215 | #define WUCSR_MPR_ (0x00000020) | |
| 216 | #define WUCSR_WAKE_EN_ (0x00000004) | |
| 217 | #define WUCSR_MPEN_ (0x00000002) | |
| 2f7ca802 SG |
218 | |
| 219 | #define COE_CR (0x130) | |
| 220 | #define Tx_COE_EN_ (0x00010000) | |
| 221 | #define Rx_COE_MODE_ (0x00000002) | |
| 222 | #define Rx_COE_EN_ (0x00000001) | |
| 223 | ||
| 224 | /* Vendor-specific PHY Definitions */ | |
| 225 | ||
| 226 | /* Mode Control/Status Register */ | |
| 227 | #define PHY_MODE_CTRL_STS (17) | |
| 228 | #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000) | |
| 229 | #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002) | |
| 230 | ||
| 231 | #define SPECIAL_CTRL_STS (27) | |
| 232 | #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((u16)0x8000) | |
| 233 | #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((u16)0x4000) | |
| 234 | #define SPECIAL_CTRL_STS_AMDIX_STATE_ ((u16)0x2000) | |
| 235 | ||
| 236 | #define PHY_INT_SRC (29) | |
| 237 | #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080) | |
| 238 | #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040) | |
| 239 | #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020) | |
| 240 | #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010) | |
| 241 | ||
| 242 | #define PHY_INT_MASK (30) | |
| 243 | #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080) | |
| 244 | #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) | |
| 245 | #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020) | |
| 246 | #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) | |
| 247 | #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ | |
| 248 | PHY_INT_MASK_LINK_DOWN_) | |
| 249 | ||
| 250 | #define PHY_SPECIAL (31) | |
| 251 | #define PHY_SPECIAL_SPD_ ((u16)0x001C) | |
| 252 | #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004) | |
| 253 | #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014) | |
| 254 | #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008) | |
| 255 | #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018) | |
| 256 | ||
| 257 | /* USB Vendor Requests */ | |
| 258 | #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 | |
| 259 | #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 | |
| 260 | #define USB_VENDOR_REQUEST_GET_STATS 0xA2 | |
| 261 | ||
| 262 | /* Interrupt Endpoint status word bitfields */ | |
| 263 | #define INT_ENP_TX_STOP_ ((u32)BIT(17)) | |
| 264 | #define INT_ENP_RX_STOP_ ((u32)BIT(16)) | |
| 265 | #define INT_ENP_PHY_INT_ ((u32)BIT(15)) | |
| 266 | #define INT_ENP_TXE_ ((u32)BIT(14)) | |
| 267 | #define INT_ENP_TDFU_ ((u32)BIT(13)) | |
| 268 | #define INT_ENP_TDFO_ ((u32)BIT(12)) | |
| 269 | #define INT_ENP_RXDF_ ((u32)BIT(11)) | |
| 270 | ||
| 271 | #endif /* _SMSC95XX_H */ |