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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This software may be redistributed and/or modified under | |
6 | * the terms of the GNU General Public License as published by the Free | |
7 | * Software Foundation; either version 2 of the License, or | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * File: via-velocity.h | |
16 | * | |
17 | * Purpose: Header file to define driver's private structures. | |
18 | * | |
19 | * Author: Chuang Liang-Shing, AJ Jiang | |
20 | * | |
21 | * Date: Jan 24, 2003 | |
22 | */ | |
23 | ||
24 | ||
25 | #ifndef VELOCITY_H | |
26 | #define VELOCITY_H | |
27 | ||
28 | #define VELOCITY_TX_CSUM_SUPPORT | |
29 | ||
30 | #define VELOCITY_NAME "via-velocity" | |
31 | #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver" | |
d5b20697 | 32 | #define VELOCITY_VERSION "1.14" |
1da177e4 | 33 | |
cabb7667 JG |
34 | #define VELOCITY_IO_SIZE 256 |
35 | ||
1da177e4 LT |
36 | #define PKT_BUF_SZ 1540 |
37 | ||
38 | #define MAX_UNITS 8 | |
39 | #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1} | |
40 | ||
41 | #define REV_ID_VT6110 (0) | |
42 | ||
43 | #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0) | |
44 | #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0) | |
45 | #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0) | |
46 | ||
47 | #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x)) | |
48 | #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x)) | |
49 | #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x)) | |
50 | ||
51 | #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0) | |
52 | #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0) | |
53 | #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0) | |
54 | ||
55 | #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0) | |
56 | #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0) | |
57 | #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0) | |
58 | ||
59 | #define VAR_USED(p) do {(p)=(p);} while (0) | |
60 | ||
61 | /* | |
62 | * Purpose: Structures for MAX RX/TX descriptors. | |
63 | */ | |
64 | ||
65 | ||
66 | #define B_OWNED_BY_CHIP 1 | |
67 | #define B_OWNED_BY_HOST 0 | |
68 | ||
69 | /* | |
70 | * Bits in the RSR0 register | |
71 | */ | |
72 | ||
4a51c0d0 AV |
73 | #define RSR_DETAG cpu_to_le16(0x0080) |
74 | #define RSR_SNTAG cpu_to_le16(0x0040) | |
75 | #define RSR_RXER cpu_to_le16(0x0020) | |
76 | #define RSR_RL cpu_to_le16(0x0010) | |
77 | #define RSR_CE cpu_to_le16(0x0008) | |
78 | #define RSR_FAE cpu_to_le16(0x0004) | |
79 | #define RSR_CRC cpu_to_le16(0x0002) | |
80 | #define RSR_VIDM cpu_to_le16(0x0001) | |
1da177e4 LT |
81 | |
82 | /* | |
83 | * Bits in the RSR1 register | |
84 | */ | |
85 | ||
4a51c0d0 AV |
86 | #define RSR_RXOK cpu_to_le16(0x8000) // rx OK |
87 | #define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match | |
88 | #define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet | |
89 | #define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet | |
90 | #define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet | |
91 | #define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator | |
92 | #define RSR_STP cpu_to_le16(0x0200) // start of packet | |
93 | #define RSR_EDP cpu_to_le16(0x0100) // end of packet | |
1da177e4 LT |
94 | |
95 | /* | |
96 | * Bits in the CSM register | |
97 | */ | |
98 | ||
99 | #define CSM_IPOK 0x40 //IP Checkusm validatiaon ok | |
100 | #define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok | |
101 | #define CSM_FRAG 0x10 //Fragment IP datagram | |
102 | #define CSM_IPKT 0x04 //Received an IP packet | |
103 | #define CSM_TCPKT 0x02 //Received a TCP packet | |
104 | #define CSM_UDPKT 0x01 //Received a UDP packet | |
105 | ||
106 | /* | |
107 | * Bits in the TSR0 register | |
108 | */ | |
109 | ||
4a51c0d0 AV |
110 | #define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision |
111 | #define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort | |
112 | #define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision | |
113 | #define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event | |
114 | #define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3] | |
115 | #define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2] | |
116 | #define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1] | |
117 | #define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0] | |
118 | #define TSR0_TERR cpu_to_le16(0x8000) // | |
119 | #define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode | |
120 | #define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode | |
121 | #define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down | |
122 | #define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case | |
123 | #define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost | |
124 | #define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat) | |
1da177e4 LT |
125 | |
126 | // | |
127 | // Bits in the TCR0 register | |
128 | // | |
129 | #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete | |
130 | #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme | |
131 | #define TCR0_VETAG 0x20 // enable VLAN tag | |
132 | #define TCR0_IPCK 0x10 // request IP checksum calculation. | |
133 | #define TCR0_UDPCK 0x08 // request UDP checksum calculation. | |
134 | #define TCR0_TCPCK 0x04 // request TCP checksum calculation. | |
135 | #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side | |
136 | #define TCR0_CRC 0x01 // disable CRC generation | |
137 | ||
138 | #define TCPLS_NORMAL 3 | |
139 | #define TCPLS_START 2 | |
140 | #define TCPLS_END 1 | |
141 | #define TCPLS_MED 0 | |
142 | ||
143 | ||
144 | // max transmit or receive buffer size | |
145 | #define CB_RX_BUF_SIZE 2048UL // max buffer size | |
146 | // NOTE: must be multiple of 4 | |
147 | ||
148 | #define CB_MAX_RD_NUM 512 // MAX # of RD | |
149 | #define CB_MAX_TD_NUM 256 // MAX # of TD | |
150 | ||
151 | #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119 | |
152 | #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119 | |
153 | ||
154 | #define CB_INIT_RD_NUM 128 // init # of RD, for setup default | |
155 | #define CB_INIT_TD_NUM 64 // init # of TD, for setup default | |
156 | ||
157 | // for 3119 | |
158 | #define CB_TD_RING_NUM 4 // # of TD rings. | |
159 | #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx) | |
160 | ||
161 | ||
162 | /* | |
163 | * If collisions excess 15 times , tx will abort, and | |
164 | * if tx fifo underflow, tx will fail | |
165 | * we should try to resend it | |
166 | */ | |
167 | ||
168 | #define CB_MAX_TX_ABORT_RETRY 3 | |
169 | ||
170 | /* | |
171 | * Receive descriptor | |
172 | */ | |
173 | ||
174 | struct rdesc0 { | |
4a51c0d0 AV |
175 | __le16 RSR; /* Receive status */ |
176 | __le16 len; /* bits 0--13; bit 15 - owner */ | |
1da177e4 LT |
177 | }; |
178 | ||
179 | struct rdesc1 { | |
4a51c0d0 | 180 | __le16 PQTAG; |
1da177e4 LT |
181 | u8 CSM; |
182 | u8 IPKT; | |
183 | }; | |
184 | ||
4a51c0d0 AV |
185 | enum { |
186 | RX_INTEN = __constant_cpu_to_le16(0x8000) | |
187 | }; | |
188 | ||
1da177e4 LT |
189 | struct rx_desc { |
190 | struct rdesc0 rdesc0; | |
191 | struct rdesc1 rdesc1; | |
4a51c0d0 AV |
192 | __le32 pa_low; /* Low 32 bit PCI address */ |
193 | __le16 pa_high; /* Next 16 bit PCI address (48 total) */ | |
194 | __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */ | |
1da177e4 LT |
195 | } __attribute__ ((__packed__)); |
196 | ||
197 | /* | |
198 | * Transmit descriptor | |
199 | */ | |
200 | ||
201 | struct tdesc0 { | |
4a51c0d0 AV |
202 | __le16 TSR; /* Transmit status register */ |
203 | __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */ | |
1da177e4 LT |
204 | }; |
205 | ||
1da177e4 | 206 | struct tdesc1 { |
4a51c0d0 | 207 | __le16 vlan; |
1da177e4 | 208 | u8 TCR; |
4a51c0d0 | 209 | u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */ |
1da177e4 LT |
210 | } __attribute__ ((__packed__)); |
211 | ||
4a51c0d0 AV |
212 | enum { |
213 | TD_QUEUE = __constant_cpu_to_le16(0x8000) | |
214 | }; | |
215 | ||
1da177e4 | 216 | struct td_buf { |
4a51c0d0 AV |
217 | __le32 pa_low; |
218 | __le16 pa_high; | |
219 | __le16 size; /* bits 0--13 - size, bit 15 - queue */ | |
1da177e4 LT |
220 | } __attribute__ ((__packed__)); |
221 | ||
222 | struct tx_desc { | |
223 | struct tdesc0 tdesc0; | |
224 | struct tdesc1 tdesc1; | |
225 | struct td_buf td_buf[7]; | |
226 | }; | |
227 | ||
228 | struct velocity_rd_info { | |
229 | struct sk_buff *skb; | |
230 | dma_addr_t skb_dma; | |
231 | }; | |
232 | ||
1da177e4 LT |
233 | /* |
234 | * Used to track transmit side buffers. | |
235 | */ | |
236 | ||
237 | struct velocity_td_info { | |
238 | struct sk_buff *skb; | |
239 | u8 *buf; | |
240 | int nskb_dma; | |
241 | dma_addr_t skb_dma[7]; | |
242 | dma_addr_t buf_dma; | |
243 | }; | |
244 | ||
245 | enum velocity_owner { | |
246 | OWNED_BY_HOST = 0, | |
4a51c0d0 | 247 | OWNED_BY_NIC = __constant_cpu_to_le16(0x8000) |
1da177e4 LT |
248 | }; |
249 | ||
250 | ||
251 | /* | |
252 | * MAC registers and macros. | |
253 | */ | |
254 | ||
255 | ||
256 | #define MCAM_SIZE 64 | |
257 | #define VCAM_SIZE 64 | |
258 | #define TX_QUEUE_NO 4 | |
259 | ||
260 | #define MAX_HW_MIB_COUNTER 32 | |
83055d46 | 261 | #define VELOCITY_MIN_MTU (64) |
1da177e4 LT |
262 | #define VELOCITY_MAX_MTU (9000) |
263 | ||
264 | /* | |
265 | * Registers in the MAC | |
266 | */ | |
267 | ||
268 | #define MAC_REG_PAR 0x00 // physical address | |
269 | #define MAC_REG_RCR 0x06 | |
270 | #define MAC_REG_TCR 0x07 | |
271 | #define MAC_REG_CR0_SET 0x08 | |
272 | #define MAC_REG_CR1_SET 0x09 | |
273 | #define MAC_REG_CR2_SET 0x0A | |
274 | #define MAC_REG_CR3_SET 0x0B | |
275 | #define MAC_REG_CR0_CLR 0x0C | |
276 | #define MAC_REG_CR1_CLR 0x0D | |
277 | #define MAC_REG_CR2_CLR 0x0E | |
278 | #define MAC_REG_CR3_CLR 0x0F | |
279 | #define MAC_REG_MAR 0x10 | |
280 | #define MAC_REG_CAM 0x10 | |
281 | #define MAC_REG_DEC_BASE_HI 0x18 | |
282 | #define MAC_REG_DBF_BASE_HI 0x1C | |
283 | #define MAC_REG_ISR_CTL 0x20 | |
284 | #define MAC_REG_ISR_HOTMR 0x20 | |
285 | #define MAC_REG_ISR_TSUPTHR 0x20 | |
286 | #define MAC_REG_ISR_RSUPTHR 0x20 | |
287 | #define MAC_REG_ISR_CTL1 0x21 | |
288 | #define MAC_REG_TXE_SR 0x22 | |
289 | #define MAC_REG_RXE_SR 0x23 | |
290 | #define MAC_REG_ISR 0x24 | |
291 | #define MAC_REG_ISR0 0x24 | |
292 | #define MAC_REG_ISR1 0x25 | |
293 | #define MAC_REG_ISR2 0x26 | |
294 | #define MAC_REG_ISR3 0x27 | |
295 | #define MAC_REG_IMR 0x28 | |
296 | #define MAC_REG_IMR0 0x28 | |
297 | #define MAC_REG_IMR1 0x29 | |
298 | #define MAC_REG_IMR2 0x2A | |
299 | #define MAC_REG_IMR3 0x2B | |
300 | #define MAC_REG_TDCSR_SET 0x30 | |
301 | #define MAC_REG_RDCSR_SET 0x32 | |
302 | #define MAC_REG_TDCSR_CLR 0x34 | |
303 | #define MAC_REG_RDCSR_CLR 0x36 | |
304 | #define MAC_REG_RDBASE_LO 0x38 | |
305 | #define MAC_REG_RDINDX 0x3C | |
306 | #define MAC_REG_TDBASE_LO 0x40 | |
307 | #define MAC_REG_RDCSIZE 0x50 | |
308 | #define MAC_REG_TDCSIZE 0x52 | |
309 | #define MAC_REG_TDINDX 0x54 | |
310 | #define MAC_REG_TDIDX0 0x54 | |
311 | #define MAC_REG_TDIDX1 0x56 | |
312 | #define MAC_REG_TDIDX2 0x58 | |
313 | #define MAC_REG_TDIDX3 0x5A | |
314 | #define MAC_REG_PAUSE_TIMER 0x5C | |
315 | #define MAC_REG_RBRDU 0x5E | |
316 | #define MAC_REG_FIFO_TEST0 0x60 | |
317 | #define MAC_REG_FIFO_TEST1 0x64 | |
318 | #define MAC_REG_CAMADDR 0x68 | |
319 | #define MAC_REG_CAMCR 0x69 | |
320 | #define MAC_REG_GFTEST 0x6A | |
321 | #define MAC_REG_FTSTCMD 0x6B | |
322 | #define MAC_REG_MIICFG 0x6C | |
323 | #define MAC_REG_MIISR 0x6D | |
324 | #define MAC_REG_PHYSR0 0x6E | |
325 | #define MAC_REG_PHYSR1 0x6F | |
326 | #define MAC_REG_MIICR 0x70 | |
327 | #define MAC_REG_MIIADR 0x71 | |
328 | #define MAC_REG_MIIDATA 0x72 | |
329 | #define MAC_REG_SOFT_TIMER0 0x74 | |
330 | #define MAC_REG_SOFT_TIMER1 0x76 | |
331 | #define MAC_REG_CFGA 0x78 | |
332 | #define MAC_REG_CFGB 0x79 | |
333 | #define MAC_REG_CFGC 0x7A | |
334 | #define MAC_REG_CFGD 0x7B | |
335 | #define MAC_REG_DCFG0 0x7C | |
336 | #define MAC_REG_DCFG1 0x7D | |
337 | #define MAC_REG_MCFG0 0x7E | |
338 | #define MAC_REG_MCFG1 0x7F | |
339 | ||
340 | #define MAC_REG_TBIST 0x80 | |
341 | #define MAC_REG_RBIST 0x81 | |
342 | #define MAC_REG_PMCC 0x82 | |
343 | #define MAC_REG_STICKHW 0x83 | |
344 | #define MAC_REG_MIBCR 0x84 | |
345 | #define MAC_REG_EERSV 0x85 | |
346 | #define MAC_REG_REVID 0x86 | |
347 | #define MAC_REG_MIBREAD 0x88 | |
348 | #define MAC_REG_BPMA 0x8C | |
349 | #define MAC_REG_EEWR_DATA 0x8C | |
350 | #define MAC_REG_BPMD_WR 0x8F | |
351 | #define MAC_REG_BPCMD 0x90 | |
352 | #define MAC_REG_BPMD_RD 0x91 | |
353 | #define MAC_REG_EECHKSUM 0x92 | |
354 | #define MAC_REG_EECSR 0x93 | |
355 | #define MAC_REG_EERD_DATA 0x94 | |
356 | #define MAC_REG_EADDR 0x96 | |
357 | #define MAC_REG_EMBCMD 0x97 | |
358 | #define MAC_REG_JMPSR0 0x98 | |
359 | #define MAC_REG_JMPSR1 0x99 | |
360 | #define MAC_REG_JMPSR2 0x9A | |
361 | #define MAC_REG_JMPSR3 0x9B | |
362 | #define MAC_REG_CHIPGSR 0x9C | |
363 | #define MAC_REG_TESTCFG 0x9D | |
364 | #define MAC_REG_DEBUG 0x9E | |
365 | #define MAC_REG_CHIPGCR 0x9F | |
366 | #define MAC_REG_WOLCR0_SET 0xA0 | |
367 | #define MAC_REG_WOLCR1_SET 0xA1 | |
368 | #define MAC_REG_PWCFG_SET 0xA2 | |
369 | #define MAC_REG_WOLCFG_SET 0xA3 | |
370 | #define MAC_REG_WOLCR0_CLR 0xA4 | |
371 | #define MAC_REG_WOLCR1_CLR 0xA5 | |
372 | #define MAC_REG_PWCFG_CLR 0xA6 | |
373 | #define MAC_REG_WOLCFG_CLR 0xA7 | |
374 | #define MAC_REG_WOLSR0_SET 0xA8 | |
375 | #define MAC_REG_WOLSR1_SET 0xA9 | |
376 | #define MAC_REG_WOLSR0_CLR 0xAC | |
377 | #define MAC_REG_WOLSR1_CLR 0xAD | |
378 | #define MAC_REG_PATRN_CRC0 0xB0 | |
379 | #define MAC_REG_PATRN_CRC1 0xB2 | |
380 | #define MAC_REG_PATRN_CRC2 0xB4 | |
381 | #define MAC_REG_PATRN_CRC3 0xB6 | |
382 | #define MAC_REG_PATRN_CRC4 0xB8 | |
383 | #define MAC_REG_PATRN_CRC5 0xBA | |
384 | #define MAC_REG_PATRN_CRC6 0xBC | |
385 | #define MAC_REG_PATRN_CRC7 0xBE | |
386 | #define MAC_REG_BYTEMSK0_0 0xC0 | |
387 | #define MAC_REG_BYTEMSK0_1 0xC4 | |
388 | #define MAC_REG_BYTEMSK0_2 0xC8 | |
389 | #define MAC_REG_BYTEMSK0_3 0xCC | |
390 | #define MAC_REG_BYTEMSK1_0 0xD0 | |
391 | #define MAC_REG_BYTEMSK1_1 0xD4 | |
392 | #define MAC_REG_BYTEMSK1_2 0xD8 | |
393 | #define MAC_REG_BYTEMSK1_3 0xDC | |
394 | #define MAC_REG_BYTEMSK2_0 0xE0 | |
395 | #define MAC_REG_BYTEMSK2_1 0xE4 | |
396 | #define MAC_REG_BYTEMSK2_2 0xE8 | |
397 | #define MAC_REG_BYTEMSK2_3 0xEC | |
398 | #define MAC_REG_BYTEMSK3_0 0xF0 | |
399 | #define MAC_REG_BYTEMSK3_1 0xF4 | |
400 | #define MAC_REG_BYTEMSK3_2 0xF8 | |
401 | #define MAC_REG_BYTEMSK3_3 0xFC | |
402 | ||
403 | /* | |
404 | * Bits in the RCR register | |
405 | */ | |
406 | ||
407 | #define RCR_AS 0x80 | |
408 | #define RCR_AP 0x40 | |
409 | #define RCR_AL 0x20 | |
410 | #define RCR_PROM 0x10 | |
411 | #define RCR_AB 0x08 | |
412 | #define RCR_AM 0x04 | |
413 | #define RCR_AR 0x02 | |
414 | #define RCR_SEP 0x01 | |
415 | ||
416 | /* | |
417 | * Bits in the TCR register | |
418 | */ | |
419 | ||
420 | #define TCR_TB2BDIS 0x80 | |
421 | #define TCR_COLTMC1 0x08 | |
422 | #define TCR_COLTMC0 0x04 | |
423 | #define TCR_LB1 0x02 /* loopback[1] */ | |
424 | #define TCR_LB0 0x01 /* loopback[0] */ | |
425 | ||
426 | /* | |
427 | * Bits in the CR0 register | |
428 | */ | |
429 | ||
430 | #define CR0_TXON 0x00000008UL | |
431 | #define CR0_RXON 0x00000004UL | |
432 | #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */ | |
433 | #define CR0_STRT 0x00000001UL /* start MAC */ | |
434 | #define CR0_SFRST 0x00008000UL /* software reset */ | |
435 | #define CR0_TM1EN 0x00004000UL | |
436 | #define CR0_TM0EN 0x00002000UL | |
437 | #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */ | |
438 | #define CR0_DISAU 0x00000100UL | |
439 | #define CR0_XONEN 0x00800000UL | |
440 | #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */ | |
441 | #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */ | |
442 | #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */ | |
443 | #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */ | |
444 | #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */ | |
445 | #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */ | |
446 | #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */ | |
447 | #define CR0_GSPRST 0x80000000UL | |
448 | #define CR0_FORSRST 0x40000000UL | |
449 | #define CR0_FPHYRST 0x20000000UL | |
450 | #define CR0_DIAG 0x10000000UL | |
451 | #define CR0_INTPCTL 0x04000000UL | |
452 | #define CR0_GINTMSK1 0x02000000UL | |
453 | #define CR0_GINTMSK0 0x01000000UL | |
454 | ||
455 | /* | |
456 | * Bits in the CR1 register | |
457 | */ | |
458 | ||
459 | #define CR1_SFRST 0x80 /* software reset */ | |
460 | #define CR1_TM1EN 0x40 | |
461 | #define CR1_TM0EN 0x20 | |
462 | #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */ | |
463 | #define CR1_DISAU 0x01 | |
464 | ||
465 | /* | |
466 | * Bits in the CR2 register | |
467 | */ | |
468 | ||
469 | #define CR2_XONEN 0x80 | |
470 | #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */ | |
471 | #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */ | |
472 | #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */ | |
473 | #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */ | |
474 | #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */ | |
475 | #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */ | |
476 | #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */ | |
477 | ||
478 | /* | |
479 | * Bits in the CR3 register | |
480 | */ | |
481 | ||
482 | #define CR3_GSPRST 0x80 | |
483 | #define CR3_FORSRST 0x40 | |
484 | #define CR3_FPHYRST 0x20 | |
485 | #define CR3_DIAG 0x10 | |
486 | #define CR3_INTPCTL 0x04 | |
487 | #define CR3_GINTMSK1 0x02 | |
488 | #define CR3_GINTMSK0 0x01 | |
489 | ||
490 | #define ISRCTL_UDPINT 0x8000 | |
491 | #define ISRCTL_TSUPDIS 0x4000 | |
492 | #define ISRCTL_RSUPDIS 0x2000 | |
493 | #define ISRCTL_PMSK1 0x1000 | |
494 | #define ISRCTL_PMSK0 0x0800 | |
495 | #define ISRCTL_INTPD 0x0400 | |
496 | #define ISRCTL_HCRLD 0x0200 | |
497 | #define ISRCTL_SCRLD 0x0100 | |
498 | ||
499 | /* | |
500 | * Bits in the ISR_CTL1 register | |
501 | */ | |
502 | ||
503 | #define ISRCTL1_UDPINT 0x80 | |
504 | #define ISRCTL1_TSUPDIS 0x40 | |
505 | #define ISRCTL1_RSUPDIS 0x20 | |
506 | #define ISRCTL1_PMSK1 0x10 | |
507 | #define ISRCTL1_PMSK0 0x08 | |
508 | #define ISRCTL1_INTPD 0x04 | |
509 | #define ISRCTL1_HCRLD 0x02 | |
510 | #define ISRCTL1_SCRLD 0x01 | |
511 | ||
512 | /* | |
513 | * Bits in the TXE_SR register | |
514 | */ | |
515 | ||
516 | #define TXESR_TFDBS 0x08 | |
517 | #define TXESR_TDWBS 0x04 | |
518 | #define TXESR_TDRBS 0x02 | |
519 | #define TXESR_TDSTR 0x01 | |
520 | ||
521 | /* | |
522 | * Bits in the RXE_SR register | |
523 | */ | |
524 | ||
525 | #define RXESR_RFDBS 0x08 | |
526 | #define RXESR_RDWBS 0x04 | |
527 | #define RXESR_RDRBS 0x02 | |
528 | #define RXESR_RDSTR 0x01 | |
529 | ||
530 | /* | |
531 | * Bits in the ISR register | |
532 | */ | |
533 | ||
534 | #define ISR_ISR3 0x80000000UL | |
535 | #define ISR_ISR2 0x40000000UL | |
536 | #define ISR_ISR1 0x20000000UL | |
537 | #define ISR_ISR0 0x10000000UL | |
538 | #define ISR_TXSTLI 0x02000000UL | |
539 | #define ISR_RXSTLI 0x01000000UL | |
540 | #define ISR_HFLD 0x00800000UL | |
541 | #define ISR_UDPI 0x00400000UL | |
542 | #define ISR_MIBFI 0x00200000UL | |
543 | #define ISR_SHDNI 0x00100000UL | |
544 | #define ISR_PHYI 0x00080000UL | |
545 | #define ISR_PWEI 0x00040000UL | |
546 | #define ISR_TMR1I 0x00020000UL | |
547 | #define ISR_TMR0I 0x00010000UL | |
548 | #define ISR_SRCI 0x00008000UL | |
549 | #define ISR_LSTPEI 0x00004000UL | |
550 | #define ISR_LSTEI 0x00002000UL | |
551 | #define ISR_OVFI 0x00001000UL | |
552 | #define ISR_FLONI 0x00000800UL | |
553 | #define ISR_RACEI 0x00000400UL | |
554 | #define ISR_TXWB1I 0x00000200UL | |
555 | #define ISR_TXWB0I 0x00000100UL | |
556 | #define ISR_PTX3I 0x00000080UL | |
557 | #define ISR_PTX2I 0x00000040UL | |
558 | #define ISR_PTX1I 0x00000020UL | |
559 | #define ISR_PTX0I 0x00000010UL | |
560 | #define ISR_PTXI 0x00000008UL | |
561 | #define ISR_PRXI 0x00000004UL | |
562 | #define ISR_PPTXI 0x00000002UL | |
563 | #define ISR_PPRXI 0x00000001UL | |
564 | ||
565 | /* | |
566 | * Bits in the IMR register | |
567 | */ | |
568 | ||
569 | #define IMR_TXSTLM 0x02000000UL | |
570 | #define IMR_UDPIM 0x00400000UL | |
571 | #define IMR_MIBFIM 0x00200000UL | |
572 | #define IMR_SHDNIM 0x00100000UL | |
573 | #define IMR_PHYIM 0x00080000UL | |
574 | #define IMR_PWEIM 0x00040000UL | |
575 | #define IMR_TMR1IM 0x00020000UL | |
576 | #define IMR_TMR0IM 0x00010000UL | |
577 | ||
578 | #define IMR_SRCIM 0x00008000UL | |
579 | #define IMR_LSTPEIM 0x00004000UL | |
580 | #define IMR_LSTEIM 0x00002000UL | |
581 | #define IMR_OVFIM 0x00001000UL | |
582 | #define IMR_FLONIM 0x00000800UL | |
583 | #define IMR_RACEIM 0x00000400UL | |
584 | #define IMR_TXWB1IM 0x00000200UL | |
585 | #define IMR_TXWB0IM 0x00000100UL | |
586 | ||
587 | #define IMR_PTX3IM 0x00000080UL | |
588 | #define IMR_PTX2IM 0x00000040UL | |
589 | #define IMR_PTX1IM 0x00000020UL | |
590 | #define IMR_PTX0IM 0x00000010UL | |
591 | #define IMR_PTXIM 0x00000008UL | |
592 | #define IMR_PRXIM 0x00000004UL | |
593 | #define IMR_PPTXIM 0x00000002UL | |
594 | #define IMR_PPRXIM 0x00000001UL | |
595 | ||
596 | /* 0x0013FB0FUL = initial value of IMR */ | |
597 | ||
598 | #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\ | |
599 | IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\ | |
600 | IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\ | |
601 | IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM) | |
602 | ||
603 | /* | |
604 | * Bits in the TDCSR0/1, RDCSR0 register | |
605 | */ | |
606 | ||
607 | #define TRDCSR_DEAD 0x0008 | |
608 | #define TRDCSR_WAK 0x0004 | |
609 | #define TRDCSR_ACT 0x0002 | |
610 | #define TRDCSR_RUN 0x0001 | |
611 | ||
612 | /* | |
613 | * Bits in the CAMADDR register | |
614 | */ | |
615 | ||
616 | #define CAMADDR_CAMEN 0x80 | |
617 | #define CAMADDR_VCAMSL 0x40 | |
618 | ||
619 | /* | |
620 | * Bits in the CAMCR register | |
621 | */ | |
622 | ||
623 | #define CAMCR_PS1 0x80 | |
624 | #define CAMCR_PS0 0x40 | |
625 | #define CAMCR_AITRPKT 0x20 | |
626 | #define CAMCR_AITR16 0x10 | |
627 | #define CAMCR_CAMRD 0x08 | |
628 | #define CAMCR_CAMWR 0x04 | |
629 | #define CAMCR_PS_CAM_MASK 0x40 | |
630 | #define CAMCR_PS_CAM_DATA 0x80 | |
631 | #define CAMCR_PS_MAR 0x00 | |
632 | ||
633 | /* | |
634 | * Bits in the MIICFG register | |
635 | */ | |
636 | ||
637 | #define MIICFG_MPO1 0x80 | |
638 | #define MIICFG_MPO0 0x40 | |
639 | #define MIICFG_MFDC 0x20 | |
640 | ||
641 | /* | |
642 | * Bits in the MIISR register | |
643 | */ | |
644 | ||
645 | #define MIISR_MIDLE 0x80 | |
646 | ||
647 | /* | |
648 | * Bits in the PHYSR0 register | |
649 | */ | |
650 | ||
651 | #define PHYSR0_PHYRST 0x80 | |
652 | #define PHYSR0_LINKGD 0x40 | |
653 | #define PHYSR0_FDPX 0x10 | |
654 | #define PHYSR0_SPDG 0x08 | |
655 | #define PHYSR0_SPD10 0x04 | |
656 | #define PHYSR0_RXFLC 0x02 | |
657 | #define PHYSR0_TXFLC 0x01 | |
658 | ||
659 | /* | |
660 | * Bits in the PHYSR1 register | |
661 | */ | |
662 | ||
663 | #define PHYSR1_PHYTBI 0x01 | |
664 | ||
665 | /* | |
666 | * Bits in the MIICR register | |
667 | */ | |
668 | ||
669 | #define MIICR_MAUTO 0x80 | |
670 | #define MIICR_RCMD 0x40 | |
671 | #define MIICR_WCMD 0x20 | |
672 | #define MIICR_MDPM 0x10 | |
673 | #define MIICR_MOUT 0x08 | |
674 | #define MIICR_MDO 0x04 | |
675 | #define MIICR_MDI 0x02 | |
676 | #define MIICR_MDC 0x01 | |
677 | ||
678 | /* | |
679 | * Bits in the MIIADR register | |
680 | */ | |
681 | ||
682 | #define MIIADR_SWMPL 0x80 | |
683 | ||
684 | /* | |
685 | * Bits in the CFGA register | |
686 | */ | |
687 | ||
688 | #define CFGA_PMHCTG 0x08 | |
689 | #define CFGA_GPIO1PD 0x04 | |
690 | #define CFGA_ABSHDN 0x02 | |
691 | #define CFGA_PACPI 0x01 | |
692 | ||
693 | /* | |
694 | * Bits in the CFGB register | |
695 | */ | |
696 | ||
697 | #define CFGB_GTCKOPT 0x80 | |
698 | #define CFGB_MIIOPT 0x40 | |
699 | #define CFGB_CRSEOPT 0x20 | |
700 | #define CFGB_OFSET 0x10 | |
701 | #define CFGB_CRANDOM 0x08 | |
702 | #define CFGB_CAP 0x04 | |
703 | #define CFGB_MBA 0x02 | |
704 | #define CFGB_BAKOPT 0x01 | |
705 | ||
706 | /* | |
707 | * Bits in the CFGC register | |
708 | */ | |
709 | ||
710 | #define CFGC_EELOAD 0x80 | |
711 | #define CFGC_BROPT 0x40 | |
712 | #define CFGC_DLYEN 0x20 | |
713 | #define CFGC_DTSEL 0x10 | |
714 | #define CFGC_BTSEL 0x08 | |
715 | #define CFGC_BPS2 0x04 /* bootrom select[2] */ | |
716 | #define CFGC_BPS1 0x02 /* bootrom select[1] */ | |
717 | #define CFGC_BPS0 0x01 /* bootrom select[0] */ | |
718 | ||
719 | /* | |
720 | * Bits in the CFGD register | |
721 | */ | |
722 | ||
723 | #define CFGD_IODIS 0x80 | |
724 | #define CFGD_MSLVDACEN 0x40 | |
725 | #define CFGD_CFGDACEN 0x20 | |
726 | #define CFGD_PCI64EN 0x10 | |
727 | #define CFGD_HTMRL4 0x08 | |
728 | ||
729 | /* | |
730 | * Bits in the DCFG1 register | |
731 | */ | |
732 | ||
733 | #define DCFG_XMWI 0x8000 | |
734 | #define DCFG_XMRM 0x4000 | |
735 | #define DCFG_XMRL 0x2000 | |
736 | #define DCFG_PERDIS 0x1000 | |
737 | #define DCFG_MRWAIT 0x0400 | |
738 | #define DCFG_MWWAIT 0x0200 | |
739 | #define DCFG_LATMEN 0x0100 | |
740 | ||
741 | /* | |
742 | * Bits in the MCFG0 register | |
743 | */ | |
744 | ||
745 | #define MCFG_RXARB 0x0080 | |
746 | #define MCFG_RFT1 0x0020 | |
747 | #define MCFG_RFT0 0x0010 | |
748 | #define MCFG_LOWTHOPT 0x0008 | |
749 | #define MCFG_PQEN 0x0004 | |
750 | #define MCFG_RTGOPT 0x0002 | |
751 | #define MCFG_VIDFR 0x0001 | |
752 | ||
753 | /* | |
754 | * Bits in the MCFG1 register | |
755 | */ | |
756 | ||
757 | #define MCFG_TXARB 0x8000 | |
758 | #define MCFG_TXQBK1 0x0800 | |
759 | #define MCFG_TXQBK0 0x0400 | |
760 | #define MCFG_TXQNOBK 0x0200 | |
761 | #define MCFG_SNAPOPT 0x0100 | |
762 | ||
763 | /* | |
764 | * Bits in the PMCC register | |
765 | */ | |
766 | ||
767 | #define PMCC_DSI 0x80 | |
768 | #define PMCC_D2_DIS 0x40 | |
769 | #define PMCC_D1_DIS 0x20 | |
770 | #define PMCC_D3C_EN 0x10 | |
771 | #define PMCC_D3H_EN 0x08 | |
772 | #define PMCC_D2_EN 0x04 | |
773 | #define PMCC_D1_EN 0x02 | |
774 | #define PMCC_D0_EN 0x01 | |
775 | ||
776 | /* | |
777 | * Bits in STICKHW | |
778 | */ | |
779 | ||
780 | #define STICKHW_SWPTAG 0x10 | |
781 | #define STICKHW_WOLSR 0x08 | |
782 | #define STICKHW_WOLEN 0x04 | |
783 | #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */ | |
784 | #define STICKHW_DS0 0x01 /* suspend well DS write port */ | |
785 | ||
786 | /* | |
787 | * Bits in the MIBCR register | |
788 | */ | |
789 | ||
790 | #define MIBCR_MIBISTOK 0x80 | |
791 | #define MIBCR_MIBISTGO 0x40 | |
792 | #define MIBCR_MIBINC 0x20 | |
793 | #define MIBCR_MIBHI 0x10 | |
794 | #define MIBCR_MIBFRZ 0x08 | |
795 | #define MIBCR_MIBFLSH 0x04 | |
796 | #define MIBCR_MPTRINI 0x02 | |
797 | #define MIBCR_MIBCLR 0x01 | |
798 | ||
799 | /* | |
800 | * Bits in the EERSV register | |
801 | */ | |
802 | ||
803 | #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */ | |
804 | ||
805 | #define EERSV_BOOT_MASK ((u8) 0x06) | |
806 | #define EERSV_BOOT_INT19 ((u8) 0x00) | |
807 | #define EERSV_BOOT_INT18 ((u8) 0x02) | |
808 | #define EERSV_BOOT_LOCAL ((u8) 0x04) | |
809 | #define EERSV_BOOT_BEV ((u8) 0x06) | |
810 | ||
811 | ||
812 | /* | |
813 | * Bits in BPCMD | |
814 | */ | |
815 | ||
816 | #define BPCMD_BPDNE 0x80 | |
817 | #define BPCMD_EBPWR 0x02 | |
818 | #define BPCMD_EBPRD 0x01 | |
819 | ||
820 | /* | |
821 | * Bits in the EECSR register | |
822 | */ | |
823 | ||
824 | #define EECSR_EMBP 0x40 /* eeprom embeded programming */ | |
825 | #define EECSR_RELOAD 0x20 /* eeprom content reload */ | |
826 | #define EECSR_DPM 0x10 /* eeprom direct programming */ | |
827 | #define EECSR_ECS 0x08 /* eeprom CS pin */ | |
828 | #define EECSR_ECK 0x04 /* eeprom CK pin */ | |
829 | #define EECSR_EDI 0x02 /* eeprom DI pin */ | |
830 | #define EECSR_EDO 0x01 /* eeprom DO pin */ | |
831 | ||
832 | /* | |
833 | * Bits in the EMBCMD register | |
834 | */ | |
835 | ||
836 | #define EMBCMD_EDONE 0x80 | |
837 | #define EMBCMD_EWDIS 0x08 | |
838 | #define EMBCMD_EWEN 0x04 | |
839 | #define EMBCMD_EWR 0x02 | |
840 | #define EMBCMD_ERD 0x01 | |
841 | ||
842 | /* | |
843 | * Bits in TESTCFG register | |
844 | */ | |
845 | ||
846 | #define TESTCFG_HBDIS 0x80 | |
847 | ||
848 | /* | |
849 | * Bits in CHIPGCR register | |
850 | */ | |
851 | ||
852 | #define CHIPGCR_FCGMII 0x80 | |
853 | #define CHIPGCR_FCFDX 0x40 | |
854 | #define CHIPGCR_FCRESV 0x20 | |
855 | #define CHIPGCR_FCMODE 0x10 | |
856 | #define CHIPGCR_LPSOPT 0x08 | |
857 | #define CHIPGCR_TM1US 0x04 | |
858 | #define CHIPGCR_TM0US 0x02 | |
859 | #define CHIPGCR_PHYINTEN 0x01 | |
860 | ||
861 | /* | |
862 | * Bits in WOLCR0 | |
863 | */ | |
864 | ||
865 | #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */ | |
866 | #define WOLCR_MSWOLEN6 0x0040 | |
867 | #define WOLCR_MSWOLEN5 0x0020 | |
868 | #define WOLCR_MSWOLEN4 0x0010 | |
869 | #define WOLCR_MSWOLEN3 0x0008 | |
870 | #define WOLCR_MSWOLEN2 0x0004 | |
871 | #define WOLCR_MSWOLEN1 0x0002 | |
872 | #define WOLCR_MSWOLEN0 0x0001 | |
873 | #define WOLCR_ARP_EN 0x0001 | |
874 | ||
875 | /* | |
876 | * Bits in WOLCR1 | |
877 | */ | |
878 | ||
879 | #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */ | |
880 | #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */ | |
881 | #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */ | |
882 | #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */ | |
883 | ||
884 | ||
885 | /* | |
886 | * Bits in PWCFG | |
887 | */ | |
888 | ||
889 | #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */ | |
890 | #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */ | |
891 | #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */ | |
892 | #define PWCFG_LEGCY_WOL 0x10 | |
893 | #define PWCFG_PMCSR_PME_SR 0x08 | |
894 | #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */ | |
895 | #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */ | |
896 | #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */ | |
897 | ||
898 | /* | |
899 | * Bits in WOLCFG | |
900 | */ | |
901 | ||
902 | #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */ | |
903 | #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */ | |
904 | #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */ | |
905 | #define WOLCFG_SMIIACC 0x08 /* ?? */ | |
906 | #define WOLCFG_SGENWH 0x02 | |
907 | #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII | |
908 | to report status change */ | |
909 | /* | |
910 | * Bits in WOLSR1 | |
911 | */ | |
912 | ||
913 | #define WOLSR_LINKOFF_INT 0x0800 | |
914 | #define WOLSR_LINKON_INT 0x0400 | |
915 | #define WOLSR_MAGIC_INT 0x0200 | |
916 | #define WOLSR_UNICAST_INT 0x0100 | |
917 | ||
918 | /* | |
919 | * Ethernet address filter type | |
920 | */ | |
921 | ||
922 | #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */ | |
923 | #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */ | |
924 | #define PKT_TYPE_MULTICAST 0x0002 | |
925 | #define PKT_TYPE_ALL_MULTICAST 0x0004 | |
926 | #define PKT_TYPE_BROADCAST 0x0008 | |
927 | #define PKT_TYPE_PROMISCUOUS 0x0020 | |
928 | #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */ | |
929 | #define PKT_TYPE_RUNT 0x4000 | |
930 | #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */ | |
931 | ||
932 | /* | |
933 | * Loopback mode | |
934 | */ | |
935 | ||
936 | #define MAC_LB_NONE 0x00 | |
937 | #define MAC_LB_INTERNAL 0x01 | |
938 | #define MAC_LB_EXTERNAL 0x02 | |
939 | ||
940 | /* | |
941 | * Enabled mask value of irq | |
942 | */ | |
943 | ||
944 | #if defined(_SIM) | |
945 | #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR | |
946 | set IMR0 to 0x0F according to spec */ | |
947 | ||
948 | #else | |
949 | #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR | |
950 | ignore MIBFI,RACEI to | |
951 | reduce intr. frequency | |
952 | NOTE.... do not enable NoBuf int mask at driver driver | |
953 | when (1) NoBuf -> RxThreshold = SF | |
954 | (2) OK -> RxThreshold = original value | |
955 | */ | |
956 | #endif | |
957 | ||
958 | /* | |
959 | * Revision id | |
960 | */ | |
961 | ||
962 | #define REV_ID_VT3119_A0 0x00 | |
963 | #define REV_ID_VT3119_A1 0x01 | |
964 | #define REV_ID_VT3216_A0 0x10 | |
965 | ||
966 | /* | |
967 | * Max time out delay time | |
968 | */ | |
969 | ||
970 | #define W_MAX_TIMEOUT 0x0FFFU | |
971 | ||
972 | ||
973 | /* | |
974 | * MAC registers as a structure. Cannot be directly accessed this | |
975 | * way but generates offsets for readl/writel() calls | |
976 | */ | |
977 | ||
978 | struct mac_regs { | |
979 | volatile u8 PAR[6]; /* 0x00 */ | |
980 | volatile u8 RCR; | |
981 | volatile u8 TCR; | |
982 | ||
4a51c0d0 AV |
983 | volatile __le32 CR0Set; /* 0x08 */ |
984 | volatile __le32 CR0Clr; /* 0x0C */ | |
1da177e4 LT |
985 | |
986 | volatile u8 MARCAM[8]; /* 0x10 */ | |
987 | ||
4a51c0d0 AV |
988 | volatile __le32 DecBaseHi; /* 0x18 */ |
989 | volatile __le16 DbfBaseHi; /* 0x1C */ | |
990 | volatile __le16 reserved_1E; | |
1da177e4 | 991 | |
4a51c0d0 | 992 | volatile __le16 ISRCTL; /* 0x20 */ |
1da177e4 LT |
993 | volatile u8 TXESR; |
994 | volatile u8 RXESR; | |
995 | ||
4a51c0d0 AV |
996 | volatile __le32 ISR; /* 0x24 */ |
997 | volatile __le32 IMR; | |
1da177e4 | 998 | |
4a51c0d0 | 999 | volatile __le32 TDStatusPort; /* 0x2C */ |
1da177e4 | 1000 | |
4a51c0d0 | 1001 | volatile __le16 TDCSRSet; /* 0x30 */ |
1da177e4 LT |
1002 | volatile u8 RDCSRSet; |
1003 | volatile u8 reserved_33; | |
4a51c0d0 | 1004 | volatile __le16 TDCSRClr; |
1da177e4 LT |
1005 | volatile u8 RDCSRClr; |
1006 | volatile u8 reserved_37; | |
1007 | ||
4a51c0d0 AV |
1008 | volatile __le32 RDBaseLo; /* 0x38 */ |
1009 | volatile __le16 RDIdx; /* 0x3C */ | |
1010 | volatile __le16 reserved_3E; | |
1da177e4 | 1011 | |
4a51c0d0 | 1012 | volatile __le32 TDBaseLo[4]; /* 0x40 */ |
1da177e4 | 1013 | |
4a51c0d0 AV |
1014 | volatile __le16 RDCSize; /* 0x50 */ |
1015 | volatile __le16 TDCSize; /* 0x52 */ | |
1016 | volatile __le16 TDIdx[4]; /* 0x54 */ | |
1017 | volatile __le16 tx_pause_timer; /* 0x5C */ | |
1018 | volatile __le16 RBRDU; /* 0x5E */ | |
1da177e4 | 1019 | |
4a51c0d0 AV |
1020 | volatile __le32 FIFOTest0; /* 0x60 */ |
1021 | volatile __le32 FIFOTest1; /* 0x64 */ | |
1da177e4 LT |
1022 | |
1023 | volatile u8 CAMADDR; /* 0x68 */ | |
1024 | volatile u8 CAMCR; /* 0x69 */ | |
1025 | volatile u8 GFTEST; /* 0x6A */ | |
1026 | volatile u8 FTSTCMD; /* 0x6B */ | |
1027 | ||
1028 | volatile u8 MIICFG; /* 0x6C */ | |
1029 | volatile u8 MIISR; | |
1030 | volatile u8 PHYSR0; | |
1031 | volatile u8 PHYSR1; | |
1032 | volatile u8 MIICR; | |
1033 | volatile u8 MIIADR; | |
4a51c0d0 | 1034 | volatile __le16 MIIDATA; |
1da177e4 | 1035 | |
4a51c0d0 AV |
1036 | volatile __le16 SoftTimer0; /* 0x74 */ |
1037 | volatile __le16 SoftTimer1; | |
1da177e4 LT |
1038 | |
1039 | volatile u8 CFGA; /* 0x78 */ | |
1040 | volatile u8 CFGB; | |
1041 | volatile u8 CFGC; | |
1042 | volatile u8 CFGD; | |
1043 | ||
4a51c0d0 AV |
1044 | volatile __le16 DCFG; /* 0x7C */ |
1045 | volatile __le16 MCFG; | |
1da177e4 LT |
1046 | |
1047 | volatile u8 TBIST; /* 0x80 */ | |
1048 | volatile u8 RBIST; | |
1049 | volatile u8 PMCPORT; | |
1050 | volatile u8 STICKHW; | |
1051 | ||
1052 | volatile u8 MIBCR; /* 0x84 */ | |
1053 | volatile u8 reserved_85; | |
1054 | volatile u8 rev_id; | |
1055 | volatile u8 PORSTS; | |
1056 | ||
4a51c0d0 | 1057 | volatile __le32 MIBData; /* 0x88 */ |
1da177e4 | 1058 | |
4a51c0d0 | 1059 | volatile __le16 EEWrData; |
1da177e4 LT |
1060 | |
1061 | volatile u8 reserved_8E; | |
1062 | volatile u8 BPMDWr; | |
1063 | volatile u8 BPCMD; | |
1064 | volatile u8 BPMDRd; | |
1065 | ||
1066 | volatile u8 EECHKSUM; /* 0x92 */ | |
1067 | volatile u8 EECSR; | |
1068 | ||
4a51c0d0 | 1069 | volatile __le16 EERdData; /* 0x94 */ |
1da177e4 LT |
1070 | volatile u8 EADDR; |
1071 | volatile u8 EMBCMD; | |
1072 | ||
1073 | ||
1074 | volatile u8 JMPSR0; /* 0x98 */ | |
1075 | volatile u8 JMPSR1; | |
1076 | volatile u8 JMPSR2; | |
1077 | volatile u8 JMPSR3; | |
1078 | volatile u8 CHIPGSR; /* 0x9C */ | |
1079 | volatile u8 TESTCFG; | |
1080 | volatile u8 DEBUG; | |
1081 | volatile u8 CHIPGCR; | |
1082 | ||
4a51c0d0 | 1083 | volatile __le16 WOLCRSet; /* 0xA0 */ |
1da177e4 LT |
1084 | volatile u8 PWCFGSet; |
1085 | volatile u8 WOLCFGSet; | |
1086 | ||
4a51c0d0 | 1087 | volatile __le16 WOLCRClr; /* 0xA4 */ |
1da177e4 LT |
1088 | volatile u8 PWCFGCLR; |
1089 | volatile u8 WOLCFGClr; | |
1090 | ||
4a51c0d0 AV |
1091 | volatile __le16 WOLSRSet; /* 0xA8 */ |
1092 | volatile __le16 reserved_AA; | |
1da177e4 | 1093 | |
4a51c0d0 AV |
1094 | volatile __le16 WOLSRClr; /* 0xAC */ |
1095 | volatile __le16 reserved_AE; | |
1da177e4 | 1096 | |
4a51c0d0 AV |
1097 | volatile __le16 PatternCRC[8]; /* 0xB0 */ |
1098 | volatile __le32 ByteMask[4][4]; /* 0xC0 */ | |
1da177e4 LT |
1099 | } __attribute__ ((__packed__)); |
1100 | ||
1101 | ||
1102 | enum hw_mib { | |
1103 | HW_MIB_ifRxAllPkts = 0, | |
1104 | HW_MIB_ifRxOkPkts, | |
1105 | HW_MIB_ifTxOkPkts, | |
1106 | HW_MIB_ifRxErrorPkts, | |
1107 | HW_MIB_ifRxRuntOkPkt, | |
1108 | HW_MIB_ifRxRuntErrPkt, | |
1109 | HW_MIB_ifRx64Pkts, | |
1110 | HW_MIB_ifTx64Pkts, | |
1111 | HW_MIB_ifRx65To127Pkts, | |
1112 | HW_MIB_ifTx65To127Pkts, | |
1113 | HW_MIB_ifRx128To255Pkts, | |
1114 | HW_MIB_ifTx128To255Pkts, | |
1115 | HW_MIB_ifRx256To511Pkts, | |
1116 | HW_MIB_ifTx256To511Pkts, | |
1117 | HW_MIB_ifRx512To1023Pkts, | |
1118 | HW_MIB_ifTx512To1023Pkts, | |
1119 | HW_MIB_ifRx1024To1518Pkts, | |
1120 | HW_MIB_ifTx1024To1518Pkts, | |
1121 | HW_MIB_ifTxEtherCollisions, | |
1122 | HW_MIB_ifRxPktCRCE, | |
1123 | HW_MIB_ifRxJumboPkts, | |
1124 | HW_MIB_ifTxJumboPkts, | |
1125 | HW_MIB_ifRxMacControlFrames, | |
1126 | HW_MIB_ifTxMacControlFrames, | |
1127 | HW_MIB_ifRxPktFAE, | |
1128 | HW_MIB_ifRxLongOkPkt, | |
1129 | HW_MIB_ifRxLongPktErrPkt, | |
1130 | HW_MIB_ifTXSQEErrors, | |
1131 | HW_MIB_ifRxNobuf, | |
1132 | HW_MIB_ifRxSymbolErrors, | |
1133 | HW_MIB_ifInRangeLengthErrors, | |
1134 | HW_MIB_ifLateCollisions, | |
1135 | HW_MIB_SIZE | |
1136 | }; | |
1137 | ||
1138 | enum chip_type { | |
1139 | CHIP_TYPE_VT6110 = 1, | |
1140 | }; | |
1141 | ||
1142 | struct velocity_info_tbl { | |
1143 | enum chip_type chip_id; | |
01faccbf | 1144 | const char *name; |
1da177e4 LT |
1145 | int txqueue; |
1146 | u32 flags; | |
1147 | }; | |
1148 | ||
1149 | #define mac_hw_mibs_init(regs) {\ | |
1150 | BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\ | |
1151 | BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\ | |
1152 | do {}\ | |
1153 | while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\ | |
1154 | BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\ | |
1155 | } | |
1156 | ||
1157 | #define mac_read_isr(regs) readl(&((regs)->ISR)) | |
1158 | #define mac_write_isr(regs, x) writel((x),&((regs)->ISR)) | |
1159 | #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR)) | |
1160 | ||
1161 | #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR)); | |
1162 | #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr)) | |
1163 | #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set)) | |
1164 | ||
1da177e4 LT |
1165 | #define mac_set_dma_length(regs, n) {\ |
1166 | BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\ | |
1167 | } | |
1168 | ||
1169 | #define mac_set_rx_thresh(regs, n) {\ | |
1170 | BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\ | |
1171 | } | |
1172 | ||
1173 | #define mac_rx_queue_run(regs) {\ | |
1174 | writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\ | |
1175 | } | |
1176 | ||
1177 | #define mac_rx_queue_wake(regs) {\ | |
1178 | writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\ | |
1179 | } | |
1180 | ||
1181 | #define mac_tx_queue_run(regs, n) {\ | |
1182 | writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\ | |
1183 | } | |
1184 | ||
1185 | #define mac_tx_queue_wake(regs, n) {\ | |
1186 | writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\ | |
1187 | } | |
1188 | ||
01faccbf SH |
1189 | static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) { |
1190 | int i=0; | |
1da177e4 | 1191 | |
01faccbf SH |
1192 | BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR)); |
1193 | do { | |
1194 | udelay(10); | |
1195 | if (i++>0x1000) | |
1196 | break; | |
1197 | } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR))); | |
1da177e4 LT |
1198 | } |
1199 | ||
1da177e4 LT |
1200 | /* |
1201 | * Header for WOL definitions. Used to compute hashes | |
1202 | */ | |
1203 | ||
1204 | typedef u8 MCAM_ADDR[ETH_ALEN]; | |
1205 | ||
1206 | struct arp_packet { | |
1207 | u8 dest_mac[ETH_ALEN]; | |
1208 | u8 src_mac[ETH_ALEN]; | |
4a51c0d0 AV |
1209 | __be16 type; |
1210 | __be16 ar_hrd; | |
1211 | __be16 ar_pro; | |
1da177e4 LT |
1212 | u8 ar_hln; |
1213 | u8 ar_pln; | |
4a51c0d0 | 1214 | __be16 ar_op; |
1da177e4 LT |
1215 | u8 ar_sha[ETH_ALEN]; |
1216 | u8 ar_sip[4]; | |
1217 | u8 ar_tha[ETH_ALEN]; | |
1218 | u8 ar_tip[4]; | |
1219 | } __attribute__ ((__packed__)); | |
1220 | ||
1221 | struct _magic_packet { | |
1222 | u8 dest_mac[6]; | |
1223 | u8 src_mac[6]; | |
4a51c0d0 | 1224 | __be16 type; |
1da177e4 LT |
1225 | u8 MAC[16][6]; |
1226 | u8 password[6]; | |
1227 | } __attribute__ ((__packed__)); | |
1228 | ||
1229 | /* | |
1230 | * Store for chip context when saving and restoring status. Not | |
1231 | * all fields are saved/restored currently. | |
1232 | */ | |
1233 | ||
1234 | struct velocity_context { | |
1235 | u8 mac_reg[256]; | |
1236 | MCAM_ADDR cam_addr[MCAM_SIZE]; | |
1237 | u16 vcam[VCAM_SIZE]; | |
1238 | u32 cammask[2]; | |
1239 | u32 patcrc[2]; | |
1240 | u32 pattern[8]; | |
1241 | }; | |
1242 | ||
1243 | ||
1244 | /* | |
1245 | * MII registers. | |
1246 | */ | |
1247 | ||
1248 | ||
1249 | /* | |
1250 | * Registers in the MII (offset unit is WORD) | |
1251 | */ | |
1252 | ||
1253 | #define MII_REG_BMCR 0x00 // physical address | |
1254 | #define MII_REG_BMSR 0x01 // | |
1255 | #define MII_REG_PHYID1 0x02 // OUI | |
1256 | #define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID | |
1257 | #define MII_REG_ANAR 0x04 // | |
1258 | #define MII_REG_ANLPAR 0x05 // | |
1259 | #define MII_REG_G1000CR 0x09 // | |
1260 | #define MII_REG_G1000SR 0x0A // | |
1261 | #define MII_REG_MODCFG 0x10 // | |
1262 | #define MII_REG_TCSR 0x16 // | |
1263 | #define MII_REG_PLED 0x1B // | |
1264 | // NS, MYSON only | |
1265 | #define MII_REG_PCR 0x17 // | |
1266 | // ESI only | |
1267 | #define MII_REG_PCSR 0x17 // | |
1268 | #define MII_REG_AUXCR 0x1C // | |
1269 | ||
1270 | // Marvell 88E1000/88E1000S | |
1271 | #define MII_REG_PSCR 0x10 // PHY specific control register | |
1272 | ||
1273 | // | |
1274 | // Bits in the BMCR register | |
1275 | // | |
1276 | #define BMCR_RESET 0x8000 // | |
1277 | #define BMCR_LBK 0x4000 // | |
1278 | #define BMCR_SPEED100 0x2000 // | |
1279 | #define BMCR_AUTO 0x1000 // | |
1280 | #define BMCR_PD 0x0800 // | |
1281 | #define BMCR_ISO 0x0400 // | |
1282 | #define BMCR_REAUTO 0x0200 // | |
1283 | #define BMCR_FDX 0x0100 // | |
1284 | #define BMCR_SPEED1G 0x0040 // | |
1285 | // | |
1286 | // Bits in the BMSR register | |
1287 | // | |
1288 | #define BMSR_AUTOCM 0x0020 // | |
1289 | #define BMSR_LNK 0x0004 // | |
1290 | ||
1291 | // | |
1292 | // Bits in the ANAR register | |
1293 | // | |
1294 | #define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support | |
1295 | #define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support | |
1296 | #define ANAR_T4 0x0200 // | |
1297 | #define ANAR_TXFD 0x0100 // | |
1298 | #define ANAR_TX 0x0080 // | |
1299 | #define ANAR_10FD 0x0040 // | |
1300 | #define ANAR_10 0x0020 // | |
1301 | // | |
1302 | // Bits in the ANLPAR register | |
1303 | // | |
1304 | #define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support | |
1305 | #define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support | |
1306 | #define ANLPAR_T4 0x0200 // | |
1307 | #define ANLPAR_TXFD 0x0100 // | |
1308 | #define ANLPAR_TX 0x0080 // | |
1309 | #define ANLPAR_10FD 0x0040 // | |
1310 | #define ANLPAR_10 0x0020 // | |
1311 | ||
1312 | // | |
1313 | // Bits in the G1000CR register | |
1314 | // | |
1315 | #define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable | |
1316 | #define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable | |
1317 | ||
1318 | // | |
1319 | // Bits in the G1000SR register | |
1320 | // | |
1321 | #define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable | |
1322 | #define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable | |
1323 | ||
1324 | #define TCSR_ECHODIS 0x2000 // | |
1325 | #define AUXCR_MDPPS 0x0004 // | |
1326 | ||
1327 | // Bits in the PLED register | |
1328 | #define PLED_LALBE 0x0004 // | |
1329 | ||
1330 | // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h) | |
1331 | #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit | |
1332 | ||
1333 | #define PHYID_CICADA_CS8201 0x000FC410UL | |
1334 | #define PHYID_VT3216_32BIT 0x000FC610UL | |
1335 | #define PHYID_VT3216_64BIT 0x000FC600UL | |
1336 | #define PHYID_MARVELL_1000 0x01410C50UL | |
1337 | #define PHYID_MARVELL_1000S 0x01410C40UL | |
1338 | ||
1339 | #define PHYID_REV_ID_MASK 0x0000000FUL | |
1340 | ||
1341 | #define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK) | |
1342 | #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK) | |
1343 | ||
1344 | #define MII_REG_BITS_ON(x,i,p) do {\ | |
1345 | u16 w;\ | |
1346 | velocity_mii_read((p),(i),&(w));\ | |
1347 | (w)|=(x);\ | |
1348 | velocity_mii_write((p),(i),(w));\ | |
1349 | } while (0) | |
1350 | ||
1351 | #define MII_REG_BITS_OFF(x,i,p) do {\ | |
1352 | u16 w;\ | |
1353 | velocity_mii_read((p),(i),&(w));\ | |
1354 | (w)&=(~(x));\ | |
1355 | velocity_mii_write((p),(i),(w));\ | |
1356 | } while (0) | |
1357 | ||
1358 | #define MII_REG_BITS_IS_ON(x,i,p) ({\ | |
1359 | u16 w;\ | |
1360 | velocity_mii_read((p),(i),&(w));\ | |
1361 | ((int) ((w) & (x)));}) | |
1362 | ||
1363 | #define MII_GET_PHY_ID(p) ({\ | |
1364 | u32 id;\ | |
1365 | velocity_mii_read((p),MII_REG_PHYID2,(u16 *) &id);\ | |
1366 | velocity_mii_read((p),MII_REG_PHYID1,((u16 *) &id)+1);\ | |
1367 | (id);}) | |
1368 | ||
1369 | /* | |
1370 | * Inline debug routine | |
1371 | */ | |
1372 | ||
1373 | ||
1374 | enum velocity_msg_level { | |
1375 | MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation. | |
1376 | MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified. | |
1377 | MSG_LEVEL_INFO = 2, //Normal message. | |
1378 | MSG_LEVEL_VERBOSE = 3, //Will report all trival errors. | |
1379 | MSG_LEVEL_DEBUG = 4 //Only for debug purpose. | |
1380 | }; | |
1381 | ||
1382 | #ifdef VELOCITY_DEBUG | |
1383 | #define ASSERT(x) { \ | |
1384 | if (!(x)) { \ | |
1385 | printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\ | |
1386 | __FUNCTION__, __LINE__);\ | |
1387 | BUG(); \ | |
1388 | }\ | |
1389 | } | |
1390 | #define VELOCITY_DBG(p,args...) printk(p, ##args) | |
1391 | #else | |
1392 | #define ASSERT(x) | |
1393 | #define VELOCITY_DBG(x) | |
1394 | #endif | |
1395 | ||
1396 | #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0) | |
1397 | ||
1398 | #define VELOCITY_PRT_CAMMASK(p,t) {\ | |
1399 | int i;\ | |
1400 | if ((t)==VELOCITY_MULTICAST_CAM) {\ | |
1401 | for (i=0;i<(MCAM_SIZE/8);i++)\ | |
1402 | printk("%02X",(p)->mCAMmask[i]);\ | |
1403 | }\ | |
1404 | else {\ | |
1405 | for (i=0;i<(VCAM_SIZE/8);i++)\ | |
1406 | printk("%02X",(p)->vCAMmask[i]);\ | |
1407 | }\ | |
1408 | printk("\n");\ | |
1409 | } | |
1410 | ||
1411 | ||
1412 | ||
1413 | #define VELOCITY_WOL_MAGIC 0x00000000UL | |
1414 | #define VELOCITY_WOL_PHY 0x00000001UL | |
1415 | #define VELOCITY_WOL_ARP 0x00000002UL | |
1416 | #define VELOCITY_WOL_UCAST 0x00000004UL | |
1417 | #define VELOCITY_WOL_BCAST 0x00000010UL | |
1418 | #define VELOCITY_WOL_MCAST 0x00000020UL | |
1419 | #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL | |
1420 | ||
1421 | /* | |
1422 | * Flags for options | |
1423 | */ | |
1424 | ||
1425 | #define VELOCITY_FLAGS_TAGGING 0x00000001UL | |
1426 | #define VELOCITY_FLAGS_TX_CSUM 0x00000002UL | |
1427 | #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL | |
1428 | #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL | |
1429 | #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL | |
1430 | ||
1431 | #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL | |
1432 | ||
1433 | /* | |
1434 | * Flags for driver status | |
1435 | */ | |
1436 | ||
1437 | #define VELOCITY_FLAGS_OPENED 0x00010000UL | |
1438 | #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL | |
1439 | #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL | |
1440 | #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL | |
1441 | ||
1442 | /* | |
1443 | * Flags for MII status | |
1444 | */ | |
1445 | ||
1446 | #define VELOCITY_LINK_FAIL 0x00000001UL | |
1447 | #define VELOCITY_SPEED_10 0x00000002UL | |
1448 | #define VELOCITY_SPEED_100 0x00000004UL | |
1449 | #define VELOCITY_SPEED_1000 0x00000008UL | |
1450 | #define VELOCITY_DUPLEX_FULL 0x00000010UL | |
1451 | #define VELOCITY_AUTONEG_ENABLE 0x00000020UL | |
1452 | #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL | |
1453 | ||
1454 | /* | |
1455 | * For velocity_set_media_duplex | |
1456 | */ | |
1457 | ||
1458 | #define VELOCITY_LINK_CHANGE 0x00000001UL | |
1459 | ||
1460 | enum speed_opt { | |
1461 | SPD_DPX_AUTO = 0, | |
1462 | SPD_DPX_100_HALF = 1, | |
1463 | SPD_DPX_100_FULL = 2, | |
1464 | SPD_DPX_10_HALF = 3, | |
1465 | SPD_DPX_10_FULL = 4 | |
1466 | }; | |
1467 | ||
1468 | enum velocity_init_type { | |
1469 | VELOCITY_INIT_COLD = 0, | |
1470 | VELOCITY_INIT_RESET, | |
1471 | VELOCITY_INIT_WOL | |
1472 | }; | |
1473 | ||
1474 | enum velocity_flow_cntl_type { | |
1475 | FLOW_CNTL_DEFAULT = 1, | |
1476 | FLOW_CNTL_TX, | |
1477 | FLOW_CNTL_RX, | |
1478 | FLOW_CNTL_TX_RX, | |
1479 | FLOW_CNTL_DISABLE, | |
1480 | }; | |
1481 | ||
1482 | struct velocity_opt { | |
1483 | int numrx; /* Number of RX descriptors */ | |
1484 | int numtx; /* Number of TX descriptors */ | |
1485 | enum speed_opt spd_dpx; /* Media link mode */ | |
501e4d24 | 1486 | |
1da177e4 LT |
1487 | int DMA_length; /* DMA length */ |
1488 | int rx_thresh; /* RX_THRESH */ | |
1489 | int flow_cntl; | |
1490 | int wol_opts; /* Wake on lan options */ | |
1491 | int td_int_count; | |
1492 | int int_works; | |
1493 | int rx_bandwidth_hi; | |
1494 | int rx_bandwidth_lo; | |
1495 | int rx_bandwidth_en; | |
1496 | u32 flags; | |
1497 | }; | |
1498 | ||
1499 | struct velocity_info { | |
1500 | struct list_head list; | |
1501 | ||
1502 | struct pci_dev *pdev; | |
1503 | struct net_device *dev; | |
1504 | struct net_device_stats stats; | |
1505 | ||
1506 | dma_addr_t rd_pool_dma; | |
1507 | dma_addr_t td_pool_dma[TX_QUEUE_NO]; | |
1508 | ||
1509 | dma_addr_t tx_bufs_dma; | |
1510 | u8 *tx_bufs; | |
1511 | ||
501e4d24 | 1512 | struct vlan_group *vlgrp; |
1da177e4 LT |
1513 | u8 ip_addr[4]; |
1514 | enum chip_type chip_id; | |
1515 | ||
1516 | struct mac_regs __iomem * mac_regs; | |
1517 | unsigned long memaddr; | |
1518 | unsigned long ioaddr; | |
1da177e4 LT |
1519 | |
1520 | u8 rev_id; | |
1521 | ||
1522 | #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)])) | |
1523 | ||
1524 | int num_txq; | |
1525 | ||
1526 | volatile int td_used[TX_QUEUE_NO]; | |
1527 | int td_curr[TX_QUEUE_NO]; | |
1528 | int td_tail[TX_QUEUE_NO]; | |
1529 | struct tx_desc *td_rings[TX_QUEUE_NO]; | |
1530 | struct velocity_td_info *td_infos[TX_QUEUE_NO]; | |
1531 | ||
1532 | int rd_curr; | |
1533 | int rd_dirty; | |
1534 | u32 rd_filled; | |
1535 | struct rx_desc *rd_ring; | |
1536 | struct velocity_rd_info *rd_info; /* It's an array */ | |
1537 | ||
1538 | #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx]) | |
1539 | u32 mib_counter[MAX_HW_MIB_COUNTER]; | |
1540 | struct velocity_opt options; | |
1541 | ||
1542 | u32 int_mask; | |
1543 | ||
1544 | u32 flags; | |
1545 | ||
1546 | int rx_buf_sz; | |
1547 | u32 mii_status; | |
1548 | u32 phy_id; | |
1549 | int multicast_limit; | |
1550 | ||
1551 | u8 vCAMmask[(VCAM_SIZE / 8)]; | |
1552 | u8 mCAMmask[(MCAM_SIZE / 8)]; | |
1553 | ||
1554 | spinlock_t lock; | |
1555 | ||
1556 | int wol_opts; | |
1557 | u8 wol_passwd[6]; | |
1558 | ||
1559 | struct velocity_context context; | |
1560 | ||
1561 | u32 ticks; | |
1562 | u32 rx_bytes; | |
1563 | ||
1564 | }; | |
1565 | ||
1566 | /** | |
1567 | * velocity_get_ip - find an IP address for the device | |
1568 | * @vptr: Velocity to query | |
1569 | * | |
1570 | * Dig out an IP address for this interface so that we can | |
1571 | * configure wakeup with WOL for ARP. If there are multiple IP | |
1572 | * addresses on this chain then we use the first - multi-IP WOL is not | |
1573 | * supported. | |
1574 | * | |
1575 | * CHECK ME: locking | |
1576 | */ | |
1577 | ||
77933d72 | 1578 | static inline int velocity_get_ip(struct velocity_info *vptr) |
1da177e4 LT |
1579 | { |
1580 | struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr; | |
1581 | struct in_ifaddr *ifa; | |
1582 | ||
1583 | if (in_dev != NULL) { | |
1584 | ifa = (struct in_ifaddr *) in_dev->ifa_list; | |
1585 | if (ifa != NULL) { | |
1586 | memcpy(vptr->ip_addr, &ifa->ifa_address, 4); | |
1587 | return 0; | |
1588 | } | |
1589 | } | |
1590 | return -ENOENT; | |
1591 | } | |
1592 | ||
1593 | /** | |
1594 | * velocity_update_hw_mibs - fetch MIB counters from chip | |
1595 | * @vptr: velocity to update | |
1596 | * | |
1597 | * The velocity hardware keeps certain counters in the hardware | |
1598 | * side. We need to read these when the user asks for statistics | |
1599 | * or when they overflow (causing an interrupt). The read of the | |
1600 | * statistic clears it, so we keep running master counters in user | |
1601 | * space. | |
1602 | */ | |
1603 | ||
1604 | static inline void velocity_update_hw_mibs(struct velocity_info *vptr) | |
1605 | { | |
1606 | u32 tmp; | |
1607 | int i; | |
1608 | BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)); | |
1609 | ||
1610 | while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR))); | |
1611 | ||
1612 | BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR)); | |
1613 | for (i = 0; i < HW_MIB_SIZE; i++) { | |
1614 | tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL; | |
1615 | vptr->mib_counter[i] += tmp; | |
1616 | } | |
1617 | } | |
1618 | ||
1619 | /** | |
1620 | * init_flow_control_register - set up flow control | |
1621 | * @vptr: velocity to configure | |
1622 | * | |
1623 | * Configure the flow control registers for this velocity device. | |
1624 | */ | |
1625 | ||
1626 | static inline void init_flow_control_register(struct velocity_info *vptr) | |
1627 | { | |
1628 | struct mac_regs __iomem * regs = vptr->mac_regs; | |
1629 | ||
1630 | /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1} | |
1631 | depend on RD=64, and Turn on XNOEN in FlowCR1 */ | |
1632 | writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set); | |
1633 | writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr); | |
1634 | ||
1635 | /* Set TxPauseTimer to 0xFFFF */ | |
1636 | writew(0xFFFF, ®s->tx_pause_timer); | |
1637 | ||
1638 | /* Initialize RBRDU to Rx buffer count. */ | |
1639 | writew(vptr->options.numrx, ®s->RBRDU); | |
1640 | } | |
1641 | ||
1642 | ||
1643 | #endif |