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S2io: Fixed synchronization between scheduling of napi with card reset and close
[deliverable/linux.git] / drivers / net / wan / dscc4.c
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1da177e4
LT		 1/*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83#include <linux/module.h>
84#include <linux/types.h>
85#include <linux/errno.h>
86#include <linux/list.h>
87#include <linux/ioport.h>
88#include <linux/pci.h>
89#include <linux/kernel.h>
90#include <linux/mm.h>
91
92#include <asm/system.h>
93#include <asm/cache.h>
94#include <asm/byteorder.h>
95#include <asm/uaccess.h>
96#include <asm/io.h>
97#include <asm/irq.h>
98
99#include <linux/init.h>
100#include <linux/string.h>
101
102#include <linux/if_arp.h>
103#include <linux/netdevice.h>
104#include <linux/skbuff.h>
105#include <linux/delay.h>
106#include <net/syncppp.h>
107#include <linux/hdlc.h>
14cc3e2b 108#include <linux/mutex.h>
1da177e4
LT		 109
110/* Version */
111static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
112static int debug;
113static int quartz;
114
115#ifdef CONFIG_DSCC4_PCI_RST
14cc3e2b 116static DEFINE_MUTEX(dscc4_mutex);
1da177e4
LT		 117static u32 dscc4_pci_config_store[16];
118#endif
119
120#define DRV_NAME "dscc4"
121
122#undef DSCC4_POLLING
123
124/* Module parameters */
125
126MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
127MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
128MODULE_LICENSE("GPL");
129module_param(debug, int, 0);
130MODULE_PARM_DESC(debug,"Enable/disable extra messages");
131module_param(quartz, int, 0);
132MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
133
134/* Structures */
135
136struct thingie {
137 int define;
138 u32 bits;
139};
140
141struct TxFD {
142 u32 state;
143 u32 next;
144 u32 data;
145 u32 complete;
146 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
147};
148
149struct RxFD {
150 u32 state1;
151 u32 next;
152 u32 data;
153 u32 state2;
154 u32 end;
155};
156
157#define DUMMY_SKB_SIZE 64
158#define TX_LOW 8
159#define TX_RING_SIZE 32
160#define RX_RING_SIZE 32
161#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
162#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
163#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
164#define TX_TIMEOUT (HZ/10)
165#define DSCC4_HZ_MAX 33000000
166#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
167#define dev_per_card 4
168#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
169
170#define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
171#define TO_SIZE(state) (((state) >> 16) & 0x1fff)
172
173/*
174 * Given the operating range of Linux HDLC, the 2 defines below could be
175 * made simpler. However they are a fine reminder for the limitations of
176 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
177 */
178#define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
179#define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
180#define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
181#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
182
183struct dscc4_pci_priv {
184 u32 *iqcfg;
185 int cfg_cur;
186 spinlock_t lock;
187 struct pci_dev *pdev;
188
189 struct dscc4_dev_priv *root;
190 dma_addr_t iqcfg_dma;
191 u32 xtal_hz;
192};
193
194struct dscc4_dev_priv {
195 struct sk_buff *rx_skbuff[RX_RING_SIZE];
196 struct sk_buff *tx_skbuff[TX_RING_SIZE];
197
198 struct RxFD *rx_fd;
199 struct TxFD *tx_fd;
200 u32 *iqrx;
201 u32 *iqtx;
202
203 /* FIXME: check all the volatile are required */
204 volatile u32 tx_current;
205 u32 rx_current;
206 u32 iqtx_current;
207 u32 iqrx_current;
208
209 volatile u32 tx_dirty;
210 volatile u32 ltda;
211 u32 rx_dirty;
212 u32 lrda;
213
214 dma_addr_t tx_fd_dma;
215 dma_addr_t rx_fd_dma;
216 dma_addr_t iqtx_dma;
217 dma_addr_t iqrx_dma;
218
219 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
220
221 struct timer_list timer;
222
223 struct dscc4_pci_priv *pci_priv;
224 spinlock_t lock;
225
226 int dev_id;
227 volatile u32 flags;
228 u32 timer_help;
229
230 unsigned short encoding;
231 unsigned short parity;
232 struct net_device *dev;
233 sync_serial_settings settings;
234 void __iomem *base_addr;
235 u32 __pad __attribute__ ((aligned (4)));
236};
237
238/* GLOBAL registers definitions */
239#define GCMDR 0x00
240#define GSTAR 0x04
241#define GMODE 0x08
242#define IQLENR0 0x0C
243#define IQLENR1 0x10
244#define IQRX0 0x14
245#define IQTX0 0x24
246#define IQCFG 0x3c
247#define FIFOCR1 0x44
248#define FIFOCR2 0x48
249#define FIFOCR3 0x4c
250#define FIFOCR4 0x34
251#define CH0CFG 0x50
252#define CH0BRDA 0x54
253#define CH0BTDA 0x58
254#define CH0FRDA 0x98
255#define CH0FTDA 0xb0
256#define CH0LRDA 0xc8
257#define CH0LTDA 0xe0
258
259/* SCC registers definitions */
260#define SCC_START 0x0100
261#define SCC_OFFSET 0x80
262#define CMDR 0x00
263#define STAR 0x04
264#define CCR0 0x08
265#define CCR1 0x0c
266#define CCR2 0x10
267#define BRR 0x2C
268#define RLCR 0x40
269#define IMR 0x54
270#define ISR 0x58
271
272#define GPDIR 0x0400
273#define GPDATA 0x0404
274#define GPIM 0x0408
275
276/* Bit masks */
277#define EncodingMask 0x00700000
278#define CrcMask 0x00000003
279
280#define IntRxScc0 0x10000000
281#define IntTxScc0 0x01000000
282
283#define TxPollCmd 0x00000400
284#define RxActivate 0x08000000
285#define MTFi 0x04000000
286#define Rdr 0x00400000
287#define Rdt 0x00200000
288#define Idr 0x00100000
289#define Idt 0x00080000
290#define TxSccRes 0x01000000
291#define RxSccRes 0x00010000
292#define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
293#define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
294
295#define Ccr0ClockMask 0x0000003f
296#define Ccr1LoopMask 0x00000200
297#define IsrMask 0x000fffff
298#define BrrExpMask 0x00000f00
299#define BrrMultMask 0x0000003f
300#define EncodingMask 0x00700000
301#define Hold 0x40000000
302#define SccBusy 0x10000000
303#define PowerUp 0x80000000
304#define Vis 0x00001000
305#define FrameOk (FrameVfr | FrameCrc)
306#define FrameVfr 0x80
307#define FrameRdo 0x40
308#define FrameCrc 0x20
309#define FrameRab 0x10
310#define FrameAborted 0x00000200
311#define FrameEnd 0x80000000
312#define DataComplete 0x40000000
313#define LengthCheck 0x00008000
314#define SccEvt 0x02000000
315#define NoAck 0x00000200
316#define Action 0x00000001
317#define HiDesc 0x20000000
318
319/* SCC events */
320#define RxEvt 0xf0000000
321#define TxEvt 0x0f000000
322#define Alls 0x00040000
323#define Xdu 0x00010000
324#define Cts 0x00004000
325#define Xmr 0x00002000
326#define Xpr 0x00001000
327#define Rdo 0x00000080
328#define Rfs 0x00000040
329#define Cd 0x00000004
330#define Rfo 0x00000002
331#define Flex 0x00000001
332
333/* DMA core events */
334#define Cfg 0x00200000
335#define Hi 0x00040000
336#define Fi 0x00020000
337#define Err 0x00010000
338#define Arf 0x00000002
339#define ArAck 0x00000001
340
341/* State flags */
342#define Ready 0x00000000
343#define NeedIDR 0x00000001
344#define NeedIDT 0x00000002
345#define RdoSet 0x00000004
346#define FakeReset 0x00000008
347
348/* Don't mask RDO. Ever. */
349#ifdef DSCC4_POLLING
350#define EventsMask 0xfffeef7f
351#else
352#define EventsMask 0xfffa8f7a
353#endif
354
355/* Functions prototypes */
356static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
357static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
358static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
359static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
360static int dscc4_open(struct net_device *);
361static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
362static int dscc4_close(struct net_device *);
363static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
364static int dscc4_init_ring(struct net_device *);
365static void dscc4_release_ring(struct dscc4_dev_priv *);
366static void dscc4_timer(unsigned long);
367static void dscc4_tx_timeout(struct net_device *);
7d12e780 368static irqreturn_t dscc4_irq(int irq, void *dev_id);
1da177e4
LT		 369static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
370static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
371#ifdef DSCC4_POLLING
372static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
373#endif
374
375static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
376{
377 return dev_to_hdlc(dev)->priv;
378}
379
380static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
381{
382 return p->dev;
383}
384
385static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
386 struct net_device *dev, int offset)
387{
388 u32 state;
389
390 /* Cf scc_writel for concern regarding thread-safety */
391 state = dpriv->scc_regs[offset >> 2];
392 state &= ~mask;
393 state |= value;
394 dpriv->scc_regs[offset >> 2] = state;
395 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
396}
397
398static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
399 struct net_device *dev, int offset)
400{
401 /*
402 * Thread-UNsafe.
403 * As of 2002/02/16, there are no thread racing for access.
404 */
405 dpriv->scc_regs[offset >> 2] = bits;
406 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
407}
408
409static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
410{
411 return dpriv->scc_regs[offset >> 2];
412}
413
414static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
415{
416 /* Cf errata DS5 p.4 */
417 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
418 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
419}
420
421static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
422 struct net_device *dev)
423{
424 dpriv->ltda = dpriv->tx_fd_dma +
425 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
426 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
427 /* Flush posted writes *NOW* */
428 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
429}
430
431static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
432 struct net_device *dev)
433{
434 dpriv->lrda = dpriv->rx_fd_dma +
435 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
436 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
437}
438
439static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
440{
441 return dpriv->tx_current == dpriv->tx_dirty;
442}
443
444static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
445 struct net_device *dev)
446{
447 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
448}
449
7665a089
AB		 450static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
451 struct net_device *dev, const char *msg)
1da177e4
LT		 452{
453 int ret = 0;
454
455 if (debug > 1) {
456 if (SOURCE_ID(state) != dpriv->dev_id) {
457 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
458 dev->name, msg, SOURCE_ID(state), state );
459 ret = -1;
460 }
461 if (state & 0x0df80c00) {
462 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
463 dev->name, msg, state);
464 ret = -1;
465 }
466 }
467 return ret;
468}
469
7665a089
AB		 470static void dscc4_tx_print(struct net_device *dev,
471 struct dscc4_dev_priv *dpriv,
472 char *msg)
1da177e4
LT		 473{
474 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
475 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
476}
477
478static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
479{
480 struct pci_dev *pdev = dpriv->pci_priv->pdev;
481 struct TxFD *tx_fd = dpriv->tx_fd;
482 struct RxFD *rx_fd = dpriv->rx_fd;
483 struct sk_buff **skbuff;
484 int i;
485
486 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
487 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
488
489 skbuff = dpriv->tx_skbuff;
490 for (i = 0; i < TX_RING_SIZE; i++) {
491 if (*skbuff) {
492 pci_unmap_single(pdev, tx_fd->data, (*skbuff)->len,
493 PCI_DMA_TODEVICE);
494 dev_kfree_skb(*skbuff);
495 }
496 skbuff++;
497 tx_fd++;
498 }
499
500 skbuff = dpriv->rx_skbuff;
501 for (i = 0; i < RX_RING_SIZE; i++) {
502 if (*skbuff) {
503 pci_unmap_single(pdev, rx_fd->data,
504 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
505 dev_kfree_skb(*skbuff);
506 }
507 skbuff++;
508 rx_fd++;
509 }
510}
511
7665a089
AB		 512static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
513 struct net_device *dev)
1da177e4
LT		 514{
515 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
516 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
517 const int len = RX_MAX(HDLC_MAX_MRU);
518 struct sk_buff *skb;
519 int ret = 0;
520
521 skb = dev_alloc_skb(len);
522 dpriv->rx_skbuff[dirty] = skb;
523 if (skb) {
524 skb->protocol = hdlc_type_trans(skb, dev);
525 rx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
526 len, PCI_DMA_FROMDEVICE);
527 } else {
528 rx_fd->data = (u32) NULL;
529 ret = -1;
530 }
531 return ret;
532}
533
534/*
535 * IRQ/thread/whatever safe
536 */
537static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
538 struct net_device *dev, char *msg)
539{
540 s8 i = 0;
541
542 do {
543 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
544 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
545 msg, i);
546 goto done;
547 }
3173c890 548 schedule_timeout_uninterruptible(10);
1da177e4
LT		 549 rmb();
550 } while (++i > 0);
551 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
552done:
553 return (i >= 0) ? i : -EAGAIN;
554}
555
556static int dscc4_do_action(struct net_device *dev, char *msg)
557{
558 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
559 s16 i = 0;
560
561 writel(Action, ioaddr + GCMDR);
562 ioaddr += GSTAR;
563 do {
564 u32 state = readl(ioaddr);
565
566 if (state & ArAck) {
567 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
568 writel(ArAck, ioaddr);
569 goto done;
570 } else if (state & Arf) {
571 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
572 writel(Arf, ioaddr);
573 i = -1;
574 goto done;
575 }
576 rmb();
577 } while (++i > 0);
578 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
579done:
580 return i;
581}
582
583static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
584{
585 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
586 s8 i = 0;
587
588 do {
589 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
590 (dpriv->iqtx[cur] & Xpr))
591 break;
592 smp_rmb();
3173c890 593 schedule_timeout_uninterruptible(10);
1da177e4
LT		 594 } while (++i > 0);
595
596 return (i >= 0 ) ? i : -EAGAIN;
597}
598
599#if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
600static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
601{
602 unsigned long flags;
603
604 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
605 /* Cf errata DS5 p.6 */
606 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
607 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
608 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
609 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
610 writel(Action, dpriv->base_addr + GCMDR);
611 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
612}
613
614#endif
615
616#if 0
617static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
618{
619 u16 i = 0;
620
621 /* Cf errata DS5 p.7 */
622 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
623 scc_writel(0x00050000, dpriv, dev, CCR2);
624 /*
625 * Must be longer than the time required to fill the fifo.
626 */
627 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
628 udelay(1);
629 wmb();
630 }
631
632 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
633 if (dscc4_do_action(dev, "Rdt") < 0)
634 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
635}
636#endif
637
638/* TODO: (ab)use this function to refill a completely depleted RX ring. */
639static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
640 struct net_device *dev)
641{
642 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
643 struct net_device_stats *stats = hdlc_stats(dev);
644 struct pci_dev *pdev = dpriv->pci_priv->pdev;
645 struct sk_buff *skb;
646 int pkt_len;
647
648 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
649 if (!skb) {
650 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__);
651 goto refill;
652 }
653 pkt_len = TO_SIZE(rx_fd->state2);
654 pci_unmap_single(pdev, rx_fd->data, RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
655 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
656 stats->rx_packets++;
657 stats->rx_bytes += pkt_len;
658 skb_put(skb, pkt_len);
659 if (netif_running(dev))
660 skb->protocol = hdlc_type_trans(skb, dev);
661 skb->dev->last_rx = jiffies;
662 netif_rx(skb);
663 } else {
664 if (skb->data[pkt_len] & FrameRdo)
665 stats->rx_fifo_errors++;
666 else if (!(skb->data[pkt_len] | ~FrameCrc))
667 stats->rx_crc_errors++;
668 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
669 stats->rx_length_errors++;
670 else
671 stats->rx_errors++;
672 dev_kfree_skb_irq(skb);
673 }
674refill:
675 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
676 if (try_get_rx_skb(dpriv, dev) < 0)
677 break;
678 dpriv->rx_dirty++;
679 }
680 dscc4_rx_update(dpriv, dev);
681 rx_fd->state2 = 0x00000000;
682 rx_fd->end = 0xbabeface;
683}
684
685static void dscc4_free1(struct pci_dev *pdev)
686{
687 struct dscc4_pci_priv *ppriv;
688 struct dscc4_dev_priv *root;
689 int i;
690
691 ppriv = pci_get_drvdata(pdev);
692 root = ppriv->root;
693
694 for (i = 0; i < dev_per_card; i++)
695 unregister_hdlc_device(dscc4_to_dev(root + i));
696
697 pci_set_drvdata(pdev, NULL);
698
699 for (i = 0; i < dev_per_card; i++)
700 free_netdev(root[i].dev);
701 kfree(root);
702 kfree(ppriv);
703}
704
705static int __devinit dscc4_init_one(struct pci_dev *pdev,
706 const struct pci_device_id *ent)
707{
708 struct dscc4_pci_priv *priv;
709 struct dscc4_dev_priv *dpriv;
710 void __iomem *ioaddr;
711 int i, rc;
712
713 printk(KERN_DEBUG "%s", version);
714
715 rc = pci_enable_device(pdev);
716 if (rc < 0)
717 goto out;
718
719 rc = pci_request_region(pdev, 0, "registers");
720 if (rc < 0) {
721 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
722 DRV_NAME);
723 goto err_disable_0;
724 }
725 rc = pci_request_region(pdev, 1, "LBI interface");
726 if (rc < 0) {
727 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
728 DRV_NAME);
729 goto err_free_mmio_region_1;
730 }
731
732 ioaddr = ioremap(pci_resource_start(pdev, 0),
733 pci_resource_len(pdev, 0));
734 if (!ioaddr) {
7c7459d1
GKH		 735 printk(KERN_ERR "%s: cannot remap MMIO region %llx @ %llx\n",
736 DRV_NAME, (unsigned long long)pci_resource_len(pdev, 0),
737 (unsigned long long)pci_resource_start(pdev, 0));
1da177e4
LT		 738 rc = -EIO;
739 goto err_free_mmio_regions_2;
740 }
7c7459d1
GKH		 741 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
742 (unsigned long long)pci_resource_start(pdev, 0),
743 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
1da177e4
LT		 744
745 /* Cf errata DS5 p.2 */
746 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
747 pci_set_master(pdev);
748
749 rc = dscc4_found1(pdev, ioaddr);
750 if (rc < 0)
751 goto err_iounmap_3;
752
753 priv = pci_get_drvdata(pdev);
754
1fb9df5d 755 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
1da177e4
LT		 756 if (rc < 0) {
757 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
758 goto err_release_4;
759 }
760
761 /* power up/little endian/dma core controlled via lrda/ltda */
762 writel(0x00000001, ioaddr + GMODE);
763 /* Shared interrupt queue */
764 {
765 u32 bits;
766
767 bits = (IRQ_RING_SIZE >> 5) - 1;
768 bits |= bits << 4;
769 bits |= bits << 8;
770 bits |= bits << 16;
771 writel(bits, ioaddr + IQLENR0);
772 }
773 /* Global interrupt queue */
774 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
775 priv->iqcfg = (u32 *) pci_alloc_consistent(pdev,
776 IRQ_RING_SIZE*sizeof(u32), &priv->iqcfg_dma);
777 if (!priv->iqcfg)
778 goto err_free_irq_5;
779 writel(priv->iqcfg_dma, ioaddr + IQCFG);
780
781 rc = -ENOMEM;
782
783 /*
784 * SCC 0-3 private rx/tx irq structures
785 * IQRX/TXi needs to be set soon. Learned it the hard way...
786 */
787 for (i = 0; i < dev_per_card; i++) {
788 dpriv = priv->root + i;
789 dpriv->iqtx = (u32 *) pci_alloc_consistent(pdev,
790 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
791 if (!dpriv->iqtx)
792 goto err_free_iqtx_6;
793 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
794 }
795 for (i = 0; i < dev_per_card; i++) {
796 dpriv = priv->root + i;
797 dpriv->iqrx = (u32 *) pci_alloc_consistent(pdev,
798 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
799 if (!dpriv->iqrx)
800 goto err_free_iqrx_7;
801 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
802 }
803
804 /* Cf application hint. Beware of hard-lock condition on threshold. */
805 writel(0x42104000, ioaddr + FIFOCR1);
806 //writel(0x9ce69800, ioaddr + FIFOCR2);
807 writel(0xdef6d800, ioaddr + FIFOCR2);
808 //writel(0x11111111, ioaddr + FIFOCR4);
809 writel(0x18181818, ioaddr + FIFOCR4);
810 // FIXME: should depend on the chipset revision
811 writel(0x0000000e, ioaddr + FIFOCR3);
812
813 writel(0xff200001, ioaddr + GCMDR);
814
815 rc = 0;
816out:
817 return rc;
818
819err_free_iqrx_7:
820 while (--i >= 0) {
821 dpriv = priv->root + i;
822 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
823 dpriv->iqrx, dpriv->iqrx_dma);
824 }
825 i = dev_per_card;
826err_free_iqtx_6:
827 while (--i >= 0) {
828 dpriv = priv->root + i;
829 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
830 dpriv->iqtx, dpriv->iqtx_dma);
831 }
832 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
833 priv->iqcfg_dma);
834err_free_irq_5:
835 free_irq(pdev->irq, priv->root);
836err_release_4:
837 dscc4_free1(pdev);
838err_iounmap_3:
839 iounmap (ioaddr);
840err_free_mmio_regions_2:
841 pci_release_region(pdev, 1);
842err_free_mmio_region_1:
843 pci_release_region(pdev, 0);
844err_disable_0:
845 pci_disable_device(pdev);
846 goto out;
847};
848
849/*
850 * Let's hope the default values are decent enough to protect my
851 * feet from the user's gun - Ueimor
852 */
853static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
854 struct net_device *dev)
855{
856 /* No interrupts, SCC core disabled. Let's relax */
857 scc_writel(0x00000000, dpriv, dev, CCR0);
858
859 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
860
861 /*
862 * No address recognition/crc-CCITT/cts enabled
863 * Shared flags transmission disabled - cf errata DS5 p.11
864 * Carrier detect disabled - cf errata p.14
865 * FIXME: carrier detection/polarity may be handled more gracefully.
866 */
867 scc_writel(0x02408000, dpriv, dev, CCR1);
868
869 /* crc not forwarded - Cf errata DS5 p.11 */
870 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
871 // crc forwarded
872 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
873}
874
875static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
876{
877 int ret = 0;
878
879 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
880 ret = -EOPNOTSUPP;
881 else
882 dpriv->pci_priv->xtal_hz = hz;
883
884 return ret;
885}
886
887static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
888{
889 struct dscc4_pci_priv *ppriv;
890 struct dscc4_dev_priv *root;
891 int i, ret = -ENOMEM;
892
dd00cc48 893 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
1da177e4
LT		 894 if (!root) {
895 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
896 goto err_out;
897 }
1da177e4
LT		 898
899 for (i = 0; i < dev_per_card; i++) {
900 root[i].dev = alloc_hdlcdev(root + i);
901 if (!root[i].dev)
902 goto err_free_dev;
903 }
904
dd00cc48 905 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
1da177e4
LT		 906 if (!ppriv) {
907 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
908 goto err_free_dev;
909 }
1da177e4
LT		 910
911 ppriv->root = root;
912 spin_lock_init(&ppriv->lock);
913
914 for (i = 0; i < dev_per_card; i++) {
915 struct dscc4_dev_priv *dpriv = root + i;
916 struct net_device *d = dscc4_to_dev(dpriv);
917 hdlc_device *hdlc = dev_to_hdlc(d);
918
919 d->base_addr = (unsigned long)ioaddr;
920 d->init = NULL;
921 d->irq = pdev->irq;
922 d->open = dscc4_open;
923 d->stop = dscc4_close;
924 d->set_multicast_list = NULL;
925 d->do_ioctl = dscc4_ioctl;
926 d->tx_timeout = dscc4_tx_timeout;
927 d->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 928 SET_NETDEV_DEV(d, &pdev->dev);
929
930 dpriv->dev_id = i;
931 dpriv->pci_priv = ppriv;
932 dpriv->base_addr = ioaddr;
933 spin_lock_init(&dpriv->lock);
934
935 hdlc->xmit = dscc4_start_xmit;
936 hdlc->attach = dscc4_hdlc_attach;
937
938 dscc4_init_registers(dpriv, d);
939 dpriv->parity = PARITY_CRC16_PR0_CCITT;
940 dpriv->encoding = ENCODING_NRZ;
941
942 ret = dscc4_init_ring(d);
943 if (ret < 0)
944 goto err_unregister;
945
946 ret = register_hdlc_device(d);
947 if (ret < 0) {
948 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
949 dscc4_release_ring(dpriv);
950 goto err_unregister;
951 }
952 }
953
954 ret = dscc4_set_quartz(root, quartz);
955 if (ret < 0)
956 goto err_unregister;
957
958 pci_set_drvdata(pdev, ppriv);
959 return ret;
960
961err_unregister:
962 while (i-- > 0) {
963 dscc4_release_ring(root + i);
964 unregister_hdlc_device(dscc4_to_dev(root + i));
965 }
966 kfree(ppriv);
967 i = dev_per_card;
968err_free_dev:
969 while (i-- > 0)
970 free_netdev(root[i].dev);
971 kfree(root);
972err_out:
973 return ret;
974};
975
976/* FIXME: get rid of the unneeded code */
977static void dscc4_timer(unsigned long data)
978{
979 struct net_device *dev = (struct net_device *)data;
980 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
981// struct dscc4_pci_priv *ppriv;
982
983 goto done;
984done:
985 dpriv->timer.expires = jiffies + TX_TIMEOUT;
986 add_timer(&dpriv->timer);
987}
988
989static void dscc4_tx_timeout(struct net_device *dev)
990{
991 /* FIXME: something is missing there */
992}
993
994static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
995{
996 sync_serial_settings *settings = &dpriv->settings;
997
998 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
999 struct net_device *dev = dscc4_to_dev(dpriv);
1000
1001 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
1002 return -1;
1003 }
1004 return 0;
1005}
1006
1007#ifdef CONFIG_DSCC4_PCI_RST
1008/*
1009 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1010 * so as to provide a safe way to reset the asic while not the whole machine
1011 * rebooting.
1012 *
1013 * This code doesn't need to be efficient. Keep It Simple
1014 */
1015static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1016{
1017 int i;
1018
14cc3e2b 1019 mutex_lock(&dscc4_mutex);
1da177e4
LT		 1020 for (i = 0; i < 16; i++)
1021 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1022
1023 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1024 writel(0x001c0000, ioaddr + GMODE);
1025 /* Configure GPIO port as output */
1026 writel(0x0000ffff, ioaddr + GPDIR);
1027 /* Disable interruption */
1028 writel(0x0000ffff, ioaddr + GPIM);
1029
1030 writel(0x0000ffff, ioaddr + GPDATA);
1031 writel(0x00000000, ioaddr + GPDATA);
1032
1033 /* Flush posted writes */
1034 readl(ioaddr + GSTAR);
1035
3173c890 1036 schedule_timeout_uninterruptible(10);
1da177e4
LT		 1037
1038 for (i = 0; i < 16; i++)
1039 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
14cc3e2b 1040 mutex_unlock(&dscc4_mutex);
1da177e4
LT		 1041}
1042#else
1043#define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1044#endif /* CONFIG_DSCC4_PCI_RST */
1045
1046static int dscc4_open(struct net_device *dev)
1047{
1048 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1049 struct dscc4_pci_priv *ppriv;
1050 int ret = -EAGAIN;
1051
1052 if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
1053 goto err;
1054
1055 if ((ret = hdlc_open(dev)))
1056 goto err;
1057
1058 ppriv = dpriv->pci_priv;
1059
1060 /*
1061 * Due to various bugs, there is no way to reliably reset a
1062 * specific port (manufacturer's dependant special PCI #RST wiring
1063 * apart: it affects all ports). Thus the device goes in the best
1064 * silent mode possible at dscc4_close() time and simply claims to
1065 * be up if it's opened again. It still isn't possible to change
1066 * the HDLC configuration without rebooting but at least the ports
1067 * can be up/down ifconfig'ed without killing the host.
1068 */
1069 if (dpriv->flags & FakeReset) {
1070 dpriv->flags &= ~FakeReset;
1071 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1072 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1073 scc_writel(EventsMask, dpriv, dev, IMR);
1074 printk(KERN_INFO "%s: up again.\n", dev->name);
1075 goto done;
1076 }
1077
1078 /* IDT+IDR during XPR */
1079 dpriv->flags = NeedIDR | NeedIDT;
1080
1081 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1082
1083 /*
1084 * The following is a bit paranoid...
1085 *
1086 * NB: the datasheet "...CEC will stay active if the SCC is in
1087 * power-down mode or..." and CCR2.RAC = 1 are two different
1088 * situations.
1089 */
1090 if (scc_readl_star(dpriv, dev) & SccBusy) {
1091 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1092 ret = -EAGAIN;
1093 goto err_out;
1094 } else
1095 printk(KERN_INFO "%s: available. Good\n", dev->name);
1096
1097 scc_writel(EventsMask, dpriv, dev, IMR);
1098
1099 /* Posted write is flushed in the wait_ack loop */
1100 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1101
1102 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1103 goto err_disable_scc_events;
1104
1105 /*
1106 * I would expect XPR near CE completion (before ? after ?).
1107 * At worst, this code won't see a late XPR and people
1108 * will have to re-issue an ifconfig (this is harmless).
1109 * WARNING, a really missing XPR usually means a hardware
1110 * reset is needed. Suggestions anyone ?
1111 */
1112 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1113 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1114 goto err_disable_scc_events;
1115 }
1116
1117 if (debug > 2)
1118 dscc4_tx_print(dev, dpriv, "Open");
1119
1120done:
1121 netif_start_queue(dev);
1122
1123 init_timer(&dpriv->timer);
1124 dpriv->timer.expires = jiffies + 10*HZ;
1125 dpriv->timer.data = (unsigned long)dev;
1126 dpriv->timer.function = &dscc4_timer;
1127 add_timer(&dpriv->timer);
1128 netif_carrier_on(dev);
1129
1130 return 0;
1131
1132err_disable_scc_events:
1133 scc_writel(0xffffffff, dpriv, dev, IMR);
1134 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1135err_out:
1136 hdlc_close(dev);
1137err:
1138 return ret;
1139}
1140
1141#ifdef DSCC4_POLLING
1142static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1143{
1144 /* FIXME: it's gonna be easy (TM), for sure */
1145}
1146#endif /* DSCC4_POLLING */
1147
1148static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
1149{
1150 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1151 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1152 struct TxFD *tx_fd;
1153 int next;
1154
1155 next = dpriv->tx_current%TX_RING_SIZE;
1156 dpriv->tx_skbuff[next] = skb;
1157 tx_fd = dpriv->tx_fd + next;
1158 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1159 tx_fd->data = pci_map_single(ppriv->pdev, skb->data, skb->len,
1160 PCI_DMA_TODEVICE);
1161 tx_fd->complete = 0x00000000;
1162 tx_fd->jiffies = jiffies;
1163 mb();
1164
1165#ifdef DSCC4_POLLING
1166 spin_lock(&dpriv->lock);
1167 while (dscc4_tx_poll(dpriv, dev));
1168 spin_unlock(&dpriv->lock);
1169#endif
1170
1171 dev->trans_start = jiffies;
1172
1173 if (debug > 2)
1174 dscc4_tx_print(dev, dpriv, "Xmit");
1175 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1176 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1177 netif_stop_queue(dev);
1178
1179 if (dscc4_tx_quiescent(dpriv, dev))
1180 dscc4_do_tx(dpriv, dev);
1181
1182 return 0;
1183}
1184
1185static int dscc4_close(struct net_device *dev)
1186{
1187 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1188
1189 del_timer_sync(&dpriv->timer);
1190 netif_stop_queue(dev);
1191
1192 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1193 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1194 scc_writel(0xffffffff, dpriv, dev, IMR);
1195
1196 dpriv->flags |= FakeReset;
1197
1198 hdlc_close(dev);
1199
1200 return 0;
1201}
1202
1203static inline int dscc4_check_clock_ability(int port)
1204{
1205 int ret = 0;
1206
1207#ifdef CONFIG_DSCC4_PCISYNC
1208 if (port >= 2)
1209 ret = -1;
1210#endif
1211 return ret;
1212}
1213
1214/*
1215 * DS1 p.137: "There are a total of 13 different clocking modes..."
1216 * ^^
1217 * Design choices:
1218 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1219 * Clock mode 3b _should_ work but the testing seems to make this point
1220 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1221 * This is supposed to provide least surprise "DTE like" behavior.
1222 * - if line rate is specified, clocks are assumed to be locally generated.
1223 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1224 * between these it automagically done according on the required frequency
1225 * scaling. Of course some rounding may take place.
1226 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1227 * appropriate external clocking device for testing.
1228 * - no time-slot/clock mode 5: shameless lazyness.
1229 *
1230 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1231 *
1232 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1233 * won't pass the init sequence. For example, straight back-to-back DTE without
1234 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1235 * called.
1236 *
1237 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1238 * DS0 for example)
1239 *
1240 * Clock mode related bits of CCR0:
1241 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1242 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1243 * | | +-------- High Speed: say 0
1244 * | | | +-+-+-- Clock Mode: 0..7
1245 * | | | | | |
1246 * -+-+-+-+-+-+-+-+
1247 * x|x|5|4|3|2|1|0| lower bits
1248 *
1249 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1250 * +-+-+-+------------------ M (0..15)
1251 * | | | | +-+-+-+-+-+-- N (0..63)
1252 * 0 0 0 0 | | | | 0 0 | | | | | |
1253 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1254 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1255 *
1256 */
1257static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1258{
1259 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1260 int ret = -1;
1261 u32 brr;
1262
1263 *state &= ~Ccr0ClockMask;
1264 if (*bps) { /* Clock generated - required for DCE */
1265 u32 n = 0, m = 0, divider;
1266 int xtal;
1267
1268 xtal = dpriv->pci_priv->xtal_hz;
1269 if (!xtal)
1270 goto done;
1271 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1272 goto done;
1273 divider = xtal / *bps;
1274 if (divider > BRR_DIVIDER_MAX) {
1275 divider >>= 4;
1276 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1277 } else
1278 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1279 if (divider >> 22) {
1280 n = 63;
1281 m = 15;
1282 } else if (divider) {
1283 /* Extraction of the 6 highest weighted bits */
1284 m = 0;
1285 while (0xffffffc0 & divider) {
1286 m++;
1287 divider >>= 1;
1288 }
1289 n = divider;
1290 }
1291 brr = (m << 8) | n;
1292 divider = n << m;
1293 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1294 divider <<= 4;
1295 *bps = xtal / divider;
1296 } else {
1297 /*
1298 * External clock - DTE
1299 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1300 * Nothing more to be done
1301 */
1302 brr = 0;
1303 }
1304 scc_writel(brr, dpriv, dev, BRR);
1305 ret = 0;
1306done:
1307 return ret;
1308}
1309
1310static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1311{
1312 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1313 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1314 const size_t size = sizeof(dpriv->settings);
1315 int ret = 0;
1316
1317 if (dev->flags & IFF_UP)
1318 return -EBUSY;
1319
1320 if (cmd != SIOCWANDEV)
1321 return -EOPNOTSUPP;
1322
1323 switch(ifr->ifr_settings.type) {
1324 case IF_GET_IFACE:
1325 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1326 if (ifr->ifr_settings.size < size) {
1327 ifr->ifr_settings.size = size; /* data size wanted */
1328 return -ENOBUFS;
1329 }
1330 if (copy_to_user(line, &dpriv->settings, size))
1331 return -EFAULT;
1332 break;
1333
1334 case IF_IFACE_SYNC_SERIAL:
1335 if (!capable(CAP_NET_ADMIN))
1336 return -EPERM;
1337
1338 if (dpriv->flags & FakeReset) {
1339 printk(KERN_INFO "%s: please reset the device"
1340 " before this command\n", dev->name);
1341 return -EPERM;
1342 }
1343 if (copy_from_user(&dpriv->settings, line, size))
1344 return -EFAULT;
1345 ret = dscc4_set_iface(dpriv, dev);
1346 break;
1347
1348 default:
1349 ret = hdlc_ioctl(dev, ifr, cmd);
1350 break;
1351 }
1352
1353 return ret;
1354}
1355
1356static int dscc4_match(struct thingie *p, int value)
1357{
1358 int i;
1359
1360 for (i = 0; p[i].define != -1; i++) {
1361 if (value == p[i].define)
1362 break;
1363 }
1364 if (p[i].define == -1)
1365 return -1;
1366 else
1367 return i;
1368}
1369
1370static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1371 struct net_device *dev)
1372{
1373 sync_serial_settings *settings = &dpriv->settings;
1374 int ret = -EOPNOTSUPP;
1375 u32 bps, state;
1376
1377 bps = settings->clock_rate;
1378 state = scc_readl(dpriv, CCR0);
1379 if (dscc4_set_clock(dev, &bps, &state) < 0)
1380 goto done;
1381 if (bps) { /* DCE */
1382 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1383 if (settings->clock_rate != bps) {
1384 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1385 dev->name, settings->clock_rate, bps);
1386 settings->clock_rate = bps;
1387 }
1388 } else { /* DTE */
1389 state |= PowerUp | Vis;
1390 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1391 }
1392 scc_writel(state, dpriv, dev, CCR0);
1393 ret = 0;
1394done:
1395 return ret;
1396}
1397
1398static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1399 struct net_device *dev)
1400{
1401 struct thingie encoding[] = {
1402 { ENCODING_NRZ, 0x00000000 },
1403 { ENCODING_NRZI, 0x00200000 },
1404 { ENCODING_FM_MARK, 0x00400000 },
1405 { ENCODING_FM_SPACE, 0x00500000 },
1406 { ENCODING_MANCHESTER, 0x00600000 },
1407 { -1, 0}
1408 };
1409 int i, ret = 0;
1410
1411 i = dscc4_match(encoding, dpriv->encoding);
1412 if (i >= 0)
1413 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1414 else
1415 ret = -EOPNOTSUPP;
1416 return ret;
1417}
1418
1419static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1420 struct net_device *dev)
1421{
1422 sync_serial_settings *settings = &dpriv->settings;
1423 u32 state;
1424
1425 state = scc_readl(dpriv, CCR1);
1426 if (settings->loopback) {
1427 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1428 state |= 0x00000100;
1429 } else {
1430 printk(KERN_DEBUG "%s: normal\n", dev->name);
1431 state &= ~0x00000100;
1432 }
1433 scc_writel(state, dpriv, dev, CCR1);
1434 return 0;
1435}
1436
1437static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1438 struct net_device *dev)
1439{
1440 struct thingie crc[] = {
1441 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1442 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1443 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1444 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1445 };
1446 int i, ret = 0;
1447
1448 i = dscc4_match(crc, dpriv->parity);
1449 if (i >= 0)
1450 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1451 else
1452 ret = -EOPNOTSUPP;
1453 return ret;
1454}
1455
1456static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1457{
1458 struct {
1459 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1460 } *p, do_setting[] = {
1461 { dscc4_encoding_setting },
1462 { dscc4_clock_setting },
1463 { dscc4_loopback_setting },
1464 { dscc4_crc_setting },
1465 { NULL }
1466 };
1467 int ret = 0;
1468
1469 for (p = do_setting; p->action; p++) {
1470 if ((ret = p->action(dpriv, dev)) < 0)
1471 break;
1472 }
1473 return ret;
1474}
1475
7d12e780 1476static irqreturn_t dscc4_irq(int irq, void *token)
1da177e4
LT		 1477{
1478 struct dscc4_dev_priv *root = token;
1479 struct dscc4_pci_priv *priv;
1480 struct net_device *dev;
1481 void __iomem *ioaddr;
1482 u32 state;
1483 unsigned long flags;
1484 int i, handled = 1;
1485
1486 priv = root->pci_priv;
1487 dev = dscc4_to_dev(root);
1488
1489 spin_lock_irqsave(&priv->lock, flags);
1490
1491 ioaddr = root->base_addr;
1492
1493 state = readl(ioaddr + GSTAR);
1494 if (!state) {
1495 handled = 0;
1496 goto out;
1497 }
1498 if (debug > 3)
1499 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1500 writel(state, ioaddr + GSTAR);
1501
1502 if (state & Arf) {
1503 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1504 dev->name);
1505 goto out;
1506 }
1507 state &= ~ArAck;
1508 if (state & Cfg) {
1509 if (debug > 0)
1510 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1511 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & Arf)
1512 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1513 if (!(state &= ~Cfg))
1514 goto out;
1515 }
1516 if (state & RxEvt) {
1517 i = dev_per_card - 1;
1518 do {
1519 dscc4_rx_irq(priv, root + i);
1520 } while (--i >= 0);
1521 state &= ~RxEvt;
1522 }
1523 if (state & TxEvt) {
1524 i = dev_per_card - 1;
1525 do {
1526 dscc4_tx_irq(priv, root + i);
1527 } while (--i >= 0);
1528 state &= ~TxEvt;
1529 }
1530out:
1531 spin_unlock_irqrestore(&priv->lock, flags);
1532 return IRQ_RETVAL(handled);
1533}
1534
1535static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1536 struct dscc4_dev_priv *dpriv)
1537{
1538 struct net_device *dev = dscc4_to_dev(dpriv);
1539 u32 state;
1540 int cur, loop = 0;
1541
1542try:
1543 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1544 state = dpriv->iqtx[cur];
1545 if (!state) {
1546 if (debug > 4)
1547 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1548 state);
1549 if ((debug > 1) && (loop > 1))
1550 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1551 if (loop && netif_queue_stopped(dev))
1552 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1553 netif_wake_queue(dev);
1554
1555 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1556 !dscc4_tx_done(dpriv))
1557 dscc4_do_tx(dpriv, dev);
1558 return;
1559 }
1560 loop++;
1561 dpriv->iqtx[cur] = 0;
1562 dpriv->iqtx_current++;
1563
1564 if (state_check(state, dpriv, dev, "Tx") < 0)
1565 return;
1566
1567 if (state & SccEvt) {
1568 if (state & Alls) {
1569 struct net_device_stats *stats = hdlc_stats(dev);
1570 struct sk_buff *skb;
1571 struct TxFD *tx_fd;
1572
1573 if (debug > 2)
1574 dscc4_tx_print(dev, dpriv, "Alls");
1575 /*
1576 * DataComplete can't be trusted for Tx completion.
1577 * Cf errata DS5 p.8
1578 */
1579 cur = dpriv->tx_dirty%TX_RING_SIZE;
1580 tx_fd = dpriv->tx_fd + cur;
1581 skb = dpriv->tx_skbuff[cur];
1582 if (skb) {
1583 pci_unmap_single(ppriv->pdev, tx_fd->data,
1584 skb->len, PCI_DMA_TODEVICE);
1585 if (tx_fd->state & FrameEnd) {
1586 stats->tx_packets++;
1587 stats->tx_bytes += skb->len;
1588 }
1589 dev_kfree_skb_irq(skb);
1590 dpriv->tx_skbuff[cur] = NULL;
1591 ++dpriv->tx_dirty;
1592 } else {
1593 if (debug > 1)
1594 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1595 dev->name, cur);
1596 }
1597 /*
1598 * If the driver ends sending crap on the wire, it
1599 * will be way easier to diagnose than the (not so)
1600 * random freeze induced by null sized tx frames.
1601 */
1602 tx_fd->data = tx_fd->next;
1603 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1604 tx_fd->complete = 0x00000000;
1605 tx_fd->jiffies = 0;
1606
1607 if (!(state &= ~Alls))
1608 goto try;
1609 }
1610 /*
1611 * Transmit Data Underrun
1612 */
1613 if (state & Xdu) {
1614 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1615 dpriv->flags = NeedIDT;
1616 /* Tx reset */
1617 writel(MTFi | Rdt,
1618 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1619 writel(Action, dpriv->base_addr + GCMDR);
1620 return;
1621 }
1622 if (state & Cts) {
1623 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1624 if (!(state &= ~Cts)) /* DEBUG */
1625 goto try;
1626 }
1627 if (state & Xmr) {
1628 /* Frame needs to be sent again - FIXME */
1629 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1630 if (!(state &= ~Xmr)) /* DEBUG */
1631 goto try;
1632 }
1633 if (state & Xpr) {
1634 void __iomem *scc_addr;
1635 unsigned long ring;
1636 int i;
1637
1638 /*
1639 * - the busy condition happens (sometimes);
1640 * - it doesn't seem to make the handler unreliable.
1641 */
1642 for (i = 1; i; i <<= 1) {
1643 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1644 break;
1645 }
1646 if (!i)
1647 printk(KERN_INFO "%s busy in irq\n", dev->name);
1648
1649 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1650 /* Keep this order: IDT before IDR */
1651 if (dpriv->flags & NeedIDT) {
1652 if (debug > 2)
1653 dscc4_tx_print(dev, dpriv, "Xpr");
1654 ring = dpriv->tx_fd_dma +
1655 (dpriv->tx_dirty%TX_RING_SIZE)*
1656 sizeof(struct TxFD);
1657 writel(ring, scc_addr + CH0BTDA);
1658 dscc4_do_tx(dpriv, dev);
1659 writel(MTFi | Idt, scc_addr + CH0CFG);
1660 if (dscc4_do_action(dev, "IDT") < 0)
1661 goto err_xpr;
1662 dpriv->flags &= ~NeedIDT;
1663 }
1664 if (dpriv->flags & NeedIDR) {
1665 ring = dpriv->rx_fd_dma +
1666 (dpriv->rx_current%RX_RING_SIZE)*
1667 sizeof(struct RxFD);
1668 writel(ring, scc_addr + CH0BRDA);
1669 dscc4_rx_update(dpriv, dev);
1670 writel(MTFi | Idr, scc_addr + CH0CFG);
1671 if (dscc4_do_action(dev, "IDR") < 0)
1672 goto err_xpr;
1673 dpriv->flags &= ~NeedIDR;
1674 smp_wmb();
1675 /* Activate receiver and misc */
1676 scc_writel(0x08050008, dpriv, dev, CCR2);
1677 }
1678 err_xpr:
1679 if (!(state &= ~Xpr))
1680 goto try;
1681 }
1682 if (state & Cd) {
1683 if (debug > 0)
1684 printk(KERN_INFO "%s: CD transition\n", dev->name);
1685 if (!(state &= ~Cd)) /* DEBUG */
1686 goto try;
1687 }
1688 } else { /* ! SccEvt */
1689 if (state & Hi) {
1690#ifdef DSCC4_POLLING
1691 while (!dscc4_tx_poll(dpriv, dev));
1692#endif
1693 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1694 state &= ~Hi;
1695 }
1696 if (state & Err) {
1697 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
1698 hdlc_stats(dev)->tx_errors++;
1699 state &= ~Err;
1700 }
1701 }
1702 goto try;
1703}
1704
1705static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1706 struct dscc4_dev_priv *dpriv)
1707{
1708 struct net_device *dev = dscc4_to_dev(dpriv);
1709 u32 state;
1710 int cur;
1711
1712try:
1713 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1714 state = dpriv->iqrx[cur];
1715 if (!state)
1716 return;
1717 dpriv->iqrx[cur] = 0;
1718 dpriv->iqrx_current++;
1719
1720 if (state_check(state, dpriv, dev, "Rx") < 0)
1721 return;
1722
1723 if (!(state & SccEvt)){
1724 struct RxFD *rx_fd;
1725
1726 if (debug > 4)
1727 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1728 state);
1729 state &= 0x00ffffff;
1730 if (state & Err) { /* Hold or reset */
1731 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1732 cur = dpriv->rx_current%RX_RING_SIZE;
1733 rx_fd = dpriv->rx_fd + cur;
1734 /*
1735 * Presume we're not facing a DMAC receiver reset.
1736 * As We use the rx size-filtering feature of the
1737 * DSCC4, the beginning of a new frame is waiting in
1738 * the rx fifo. I bet a Receive Data Overflow will
1739 * happen most of time but let's try and avoid it.
1740 * Btw (as for RDO) if one experiences ERR whereas
1741 * the system looks rather idle, there may be a
1742 * problem with latency. In this case, increasing
1743 * RX_RING_SIZE may help.
1744 */
1745 //while (dpriv->rx_needs_refill) {
1746 while (!(rx_fd->state1 & Hold)) {
1747 rx_fd++;
1748 cur++;
1749 if (!(cur = cur%RX_RING_SIZE))
1750 rx_fd = dpriv->rx_fd;
1751 }
1752 //dpriv->rx_needs_refill--;
1753 try_get_rx_skb(dpriv, dev);
1754 if (!rx_fd->data)
1755 goto try;
1756 rx_fd->state1 &= ~Hold;
1757 rx_fd->state2 = 0x00000000;
1758 rx_fd->end = 0xbabeface;
1759 //}
1760 goto try;
1761 }
1762 if (state & Fi) {
1763 dscc4_rx_skb(dpriv, dev);
1764 goto try;
1765 }
1766 if (state & Hi ) { /* HI bit */
1767 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1768 state &= ~Hi;
1769 goto try;
1770 }
1771 } else { /* SccEvt */
1772 if (debug > 1) {
1773 //FIXME: verifier la presence de tous les evenements
1774 static struct {
1775 u32 mask;
1776 const char *irq_name;
1777 } evts[] = {
1778 { 0x00008000, "TIN"},
1779 { 0x00000020, "RSC"},
1780 { 0x00000010, "PCE"},
1781 { 0x00000008, "PLLA"},
1782 { 0, NULL}
1783 }, *evt;
1784
1785 for (evt = evts; evt->irq_name; evt++) {
1786 if (state & evt->mask) {
1787 printk(KERN_DEBUG "%s: %s\n",
1788 dev->name, evt->irq_name);
1789 if (!(state &= ~evt->mask))
1790 goto try;
1791 }
1792 }
1793 } else {
1794 if (!(state &= ~0x0000c03c))
1795 goto try;
1796 }
1797 if (state & Cts) {
1798 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1799 if (!(state &= ~Cts)) /* DEBUG */
1800 goto try;
1801 }
1802 /*
1803 * Receive Data Overflow (FIXME: fscked)
1804 */
1805 if (state & Rdo) {
1806 struct RxFD *rx_fd;
1807 void __iomem *scc_addr;
1808 int cur;
1809
1810 //if (debug)
1811 // dscc4_rx_dump(dpriv);
1812 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1813
1814 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1815 /*
1816 * This has no effect. Why ?
1817 * ORed with TxSccRes, one sees the CFG ack (for
1818 * the TX part only).
1819 */
1820 scc_writel(RxSccRes, dpriv, dev, CMDR);
1821 dpriv->flags |= RdoSet;
1822
1823 /*
1824 * Let's try and save something in the received data.
1825 * rx_current must be incremented at least once to
1826 * avoid HOLD in the BRDA-to-be-pointed desc.
1827 */
1828 do {
1829 cur = dpriv->rx_current++%RX_RING_SIZE;
1830 rx_fd = dpriv->rx_fd + cur;
1831 if (!(rx_fd->state2 & DataComplete))
1832 break;
1833 if (rx_fd->state2 & FrameAborted) {
1834 hdlc_stats(dev)->rx_over_errors++;
1835 rx_fd->state1 |= Hold;
1836 rx_fd->state2 = 0x00000000;
1837 rx_fd->end = 0xbabeface;
1838 } else
1839 dscc4_rx_skb(dpriv, dev);
1840 } while (1);
1841
1842 if (debug > 0) {
1843 if (dpriv->flags & RdoSet)
1844 printk(KERN_DEBUG
1845 "%s: no RDO in Rx data\n", DRV_NAME);
1846 }
1847#ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1848 /*
1849 * FIXME: must the reset be this violent ?
1850 */
1851#warning "FIXME: CH0BRDA"
1852 writel(dpriv->rx_fd_dma +
1853 (dpriv->rx_current%RX_RING_SIZE)*
1854 sizeof(struct RxFD), scc_addr + CH0BRDA);
1855 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1856 if (dscc4_do_action(dev, "RDR") < 0) {
1857 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1858 dev->name, "RDR");
1859 goto rdo_end;
1860 }
1861 writel(MTFi|Idr, scc_addr + CH0CFG);
1862 if (dscc4_do_action(dev, "IDR") < 0) {
1863 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1864 dev->name, "IDR");
1865 goto rdo_end;
1866 }
1867 rdo_end:
1868#endif
1869 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1870 goto try;
1871 }
1872 if (state & Cd) {
1873 printk(KERN_INFO "%s: CD transition\n", dev->name);
1874 if (!(state &= ~Cd)) /* DEBUG */
1875 goto try;
1876 }
1877 if (state & Flex) {
1878 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1879 if (!(state &= ~Flex))
1880 goto try;
1881 }
1882 }
1883}
1884
1885/*
1886 * I had expected the following to work for the first descriptor
1887 * (tx_fd->state = 0xc0000000)
1888 * - Hold=1 (don't try and branch to the next descripto);
1889 * - No=0 (I want an empty data section, i.e. size=0);
1890 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1891 * It failed and locked solid. Thus the introduction of a dummy skb.
1892 * Problem is acknowledged in errata sheet DS5. Joy :o/
1893 */
7665a089 1894static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1da177e4
LT		 1895{
1896 struct sk_buff *skb;
1897
1898 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1899 if (skb) {
1900 int last = dpriv->tx_dirty%TX_RING_SIZE;
1901 struct TxFD *tx_fd = dpriv->tx_fd + last;
1902
1903 skb->len = DUMMY_SKB_SIZE;
27d7ff46
ACM		 1904 skb_copy_to_linear_data(skb, version,
1905 strlen(version) % DUMMY_SKB_SIZE);
1da177e4
LT		 1906 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1907 tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
1908 DUMMY_SKB_SIZE, PCI_DMA_TODEVICE);
1909 dpriv->tx_skbuff[last] = skb;
1910 }
1911 return skb;
1912}
1913
1914static int dscc4_init_ring(struct net_device *dev)
1915{
1916 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1917 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1918 struct TxFD *tx_fd;
1919 struct RxFD *rx_fd;
1920 void *ring;
1921 int i;
1922
1923 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1924 if (!ring)
1925 goto err_out;
1926 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1927
1928 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1929 if (!ring)
1930 goto err_free_dma_rx;
1931 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1932
1933 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1934 dpriv->tx_dirty = 0xffffffff;
1935 i = dpriv->tx_current = 0;
1936 do {
1937 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1938 tx_fd->complete = 0x00000000;
1939 /* FIXME: NULL should be ok - to be tried */
1940 tx_fd->data = dpriv->tx_fd_dma;
1941 (tx_fd++)->next = (u32)(dpriv->tx_fd_dma +
1942 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1943 } while (i < TX_RING_SIZE);
1944
3e710bfa 1945 if (!dscc4_init_dummy_skb(dpriv))
1da177e4
LT		 1946 goto err_free_dma_tx;
1947
1948 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1949 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1950 do {
1951 /* size set by the host. Multiple of 4 bytes please */
1952 rx_fd->state1 = HiDesc;
1953 rx_fd->state2 = 0x00000000;
1954 rx_fd->end = 0xbabeface;
1955 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1956 // FIXME: return value verifiee mais traitement suspect
1957 if (try_get_rx_skb(dpriv, dev) >= 0)
1958 dpriv->rx_dirty++;
1959 (rx_fd++)->next = (u32)(dpriv->rx_fd_dma +
1960 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1961 } while (i < RX_RING_SIZE);
1962
1963 return 0;
1964
1965err_free_dma_tx:
1966 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1967err_free_dma_rx:
1968 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1969err_out:
1970 return -ENOMEM;
1971}
1972
1973static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1974{
1975 struct dscc4_pci_priv *ppriv;
1976 struct dscc4_dev_priv *root;
1977 void __iomem *ioaddr;
1978 int i;
1979
1980 ppriv = pci_get_drvdata(pdev);
1981 root = ppriv->root;
1982
1983 ioaddr = root->base_addr;
1984
1985 dscc4_pci_reset(pdev, ioaddr);
1986
1987 free_irq(pdev->irq, root);
1988 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1989 ppriv->iqcfg_dma);
1990 for (i = 0; i < dev_per_card; i++) {
1991 struct dscc4_dev_priv *dpriv = root + i;
1992
1993 dscc4_release_ring(dpriv);
1994 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1995 dpriv->iqrx, dpriv->iqrx_dma);
1996 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1997 dpriv->iqtx, dpriv->iqtx_dma);
1998 }
1999
2000 dscc4_free1(pdev);
2001
2002 iounmap(ioaddr);
2003
2004 pci_release_region(pdev, 1);
2005 pci_release_region(pdev, 0);
2006
2007 pci_disable_device(pdev);
2008}
2009
2010static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2011 unsigned short parity)
2012{
2013 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2014
2015 if (encoding != ENCODING_NRZ &&
2016 encoding != ENCODING_NRZI &&
2017 encoding != ENCODING_FM_MARK &&
2018 encoding != ENCODING_FM_SPACE &&
2019 encoding != ENCODING_MANCHESTER)
2020 return -EINVAL;
2021
2022 if (parity != PARITY_NONE &&
2023 parity != PARITY_CRC16_PR0_CCITT &&
2024 parity != PARITY_CRC16_PR1_CCITT &&
2025 parity != PARITY_CRC32_PR0_CCITT &&
2026 parity != PARITY_CRC32_PR1_CCITT)
2027 return -EINVAL;
2028
2029 dpriv->encoding = encoding;
2030 dpriv->parity = parity;
2031 return 0;
2032}
2033
2034#ifndef MODULE
2035static int __init dscc4_setup(char *str)
2036{
2037 int *args[] = { &debug, &quartz, NULL }, **p = args;
2038
2039 while (*p && (get_option(&str, *p) == 2))
2040 p++;
2041 return 1;
2042}
2043
2044__setup("dscc4.setup=", dscc4_setup);
2045#endif
2046
2047static struct pci_device_id dscc4_pci_tbl[] = {
2048 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2049 PCI_ANY_ID, PCI_ANY_ID, },
2050 { 0,}
2051};
2052MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2053
2054static struct pci_driver dscc4_driver = {
2055 .name = DRV_NAME,
2056 .id_table = dscc4_pci_tbl,
2057 .probe = dscc4_init_one,
2058 .remove = __devexit_p(dscc4_remove_one),
2059};
2060
2061static int __init dscc4_init_module(void)
2062{
29917620 2063 return pci_register_driver(&dscc4_driver);
1da177e4
LT		 2064}
2065
2066static void __exit dscc4_cleanup_module(void)
2067{
2068 pci_unregister_driver(&dscc4_driver);
2069}
2070
2071module_init(dscc4_init_module);
2072module_exit(dscc4_cleanup_module);
Linux kernel - Deliverables
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