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tc35815: Define more Rx status bits
[deliverable/linux.git] / drivers / net / wan / dscc4.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83#include <linux/module.h>
84#include <linux/types.h>
85#include <linux/errno.h>
86#include <linux/list.h>
87#include <linux/ioport.h>
88#include <linux/pci.h>
89#include <linux/kernel.h>
90#include <linux/mm.h>
91
92#include <asm/system.h>
93#include <asm/cache.h>
94#include <asm/byteorder.h>
95#include <asm/uaccess.h>
96#include <asm/io.h>
97#include <asm/irq.h>
98
99#include <linux/init.h>
100#include <linux/string.h>
101
102#include <linux/if_arp.h>
103#include <linux/netdevice.h>
104#include <linux/skbuff.h>
105#include <linux/delay.h>
1da177e4 106#include <linux/hdlc.h>
14cc3e2b 107#include <linux/mutex.h>
1da177e4
LT		 108
109/* Version */
110static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
111static int debug;
112static int quartz;
113
114#ifdef CONFIG_DSCC4_PCI_RST
14cc3e2b 115static DEFINE_MUTEX(dscc4_mutex);
1da177e4
LT		 116static u32 dscc4_pci_config_store[16];
117#endif
118
119#define DRV_NAME "dscc4"
120
121#undef DSCC4_POLLING
122
123/* Module parameters */
124
125MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
126MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
127MODULE_LICENSE("GPL");
128module_param(debug, int, 0);
129MODULE_PARM_DESC(debug,"Enable/disable extra messages");
130module_param(quartz, int, 0);
131MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
132
133/* Structures */
134
135struct thingie {
136 int define;
137 u32 bits;
138};
139
140struct TxFD {
409cd63e
AV		 141 __le32 state;
142 __le32 next;
143 __le32 data;
144 __le32 complete;
1da177e4 145 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
409cd63e
AV		 146 /* FWIW, datasheet calls that "dummy" and says that card
147 * never looks at it; neither does the driver */
1da177e4
LT		 148};
149
150struct RxFD {
409cd63e
AV		 151 __le32 state1;
152 __le32 next;
153 __le32 data;
154 __le32 state2;
155 __le32 end;
1da177e4
LT		 156};
157
158#define DUMMY_SKB_SIZE 64
159#define TX_LOW 8
160#define TX_RING_SIZE 32
161#define RX_RING_SIZE 32
162#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
163#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
164#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
165#define TX_TIMEOUT (HZ/10)
166#define DSCC4_HZ_MAX 33000000
167#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
168#define dev_per_card 4
169#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
170
171#define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
172#define TO_SIZE(state) (((state) >> 16) & 0x1fff)
173
174/*
175 * Given the operating range of Linux HDLC, the 2 defines below could be
176 * made simpler. However they are a fine reminder for the limitations of
177 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
178 */
179#define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
180#define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
181#define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
182#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
183
184struct dscc4_pci_priv {
409cd63e 185 __le32 *iqcfg;
1da177e4
LT		 186 int cfg_cur;
187 spinlock_t lock;
188 struct pci_dev *pdev;
189
190 struct dscc4_dev_priv *root;
191 dma_addr_t iqcfg_dma;
192 u32 xtal_hz;
193};
194
195struct dscc4_dev_priv {
196 struct sk_buff *rx_skbuff[RX_RING_SIZE];
197 struct sk_buff *tx_skbuff[TX_RING_SIZE];
198
199 struct RxFD *rx_fd;
200 struct TxFD *tx_fd;
409cd63e
AV		 201 __le32 *iqrx;
202 __le32 *iqtx;
1da177e4
LT		 203
204 /* FIXME: check all the volatile are required */
205 volatile u32 tx_current;
206 u32 rx_current;
207 u32 iqtx_current;
208 u32 iqrx_current;
209
210 volatile u32 tx_dirty;
211 volatile u32 ltda;
212 u32 rx_dirty;
213 u32 lrda;
214
215 dma_addr_t tx_fd_dma;
216 dma_addr_t rx_fd_dma;
217 dma_addr_t iqtx_dma;
218 dma_addr_t iqrx_dma;
219
220 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
221
222 struct timer_list timer;
223
224 struct dscc4_pci_priv *pci_priv;
225 spinlock_t lock;
226
227 int dev_id;
228 volatile u32 flags;
229 u32 timer_help;
230
231 unsigned short encoding;
232 unsigned short parity;
233 struct net_device *dev;
234 sync_serial_settings settings;
235 void __iomem *base_addr;
236 u32 __pad __attribute__ ((aligned (4)));
237};
238
239/* GLOBAL registers definitions */
240#define GCMDR 0x00
241#define GSTAR 0x04
242#define GMODE 0x08
243#define IQLENR0 0x0C
244#define IQLENR1 0x10
245#define IQRX0 0x14
246#define IQTX0 0x24
247#define IQCFG 0x3c
248#define FIFOCR1 0x44
249#define FIFOCR2 0x48
250#define FIFOCR3 0x4c
251#define FIFOCR4 0x34
252#define CH0CFG 0x50
253#define CH0BRDA 0x54
254#define CH0BTDA 0x58
255#define CH0FRDA 0x98
256#define CH0FTDA 0xb0
257#define CH0LRDA 0xc8
258#define CH0LTDA 0xe0
259
260/* SCC registers definitions */
261#define SCC_START 0x0100
262#define SCC_OFFSET 0x80
263#define CMDR 0x00
264#define STAR 0x04
265#define CCR0 0x08
266#define CCR1 0x0c
267#define CCR2 0x10
268#define BRR 0x2C
269#define RLCR 0x40
270#define IMR 0x54
271#define ISR 0x58
272
273#define GPDIR 0x0400
274#define GPDATA 0x0404
275#define GPIM 0x0408
276
277/* Bit masks */
278#define EncodingMask 0x00700000
279#define CrcMask 0x00000003
280
281#define IntRxScc0 0x10000000
282#define IntTxScc0 0x01000000
283
284#define TxPollCmd 0x00000400
285#define RxActivate 0x08000000
286#define MTFi 0x04000000
287#define Rdr 0x00400000
288#define Rdt 0x00200000
289#define Idr 0x00100000
290#define Idt 0x00080000
291#define TxSccRes 0x01000000
292#define RxSccRes 0x00010000
293#define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
294#define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
295
296#define Ccr0ClockMask 0x0000003f
297#define Ccr1LoopMask 0x00000200
298#define IsrMask 0x000fffff
299#define BrrExpMask 0x00000f00
300#define BrrMultMask 0x0000003f
301#define EncodingMask 0x00700000
409cd63e 302#define Hold cpu_to_le32(0x40000000)
1da177e4
LT		 303#define SccBusy 0x10000000
304#define PowerUp 0x80000000
305#define Vis 0x00001000
306#define FrameOk (FrameVfr | FrameCrc)
307#define FrameVfr 0x80
308#define FrameRdo 0x40
309#define FrameCrc 0x20
310#define FrameRab 0x10
409cd63e
AV		 311#define FrameAborted cpu_to_le32(0x00000200)
312#define FrameEnd cpu_to_le32(0x80000000)
313#define DataComplete cpu_to_le32(0x40000000)
1da177e4
LT		 314#define LengthCheck 0x00008000
315#define SccEvt 0x02000000
316#define NoAck 0x00000200
317#define Action 0x00000001
409cd63e 318#define HiDesc cpu_to_le32(0x20000000)
1da177e4
LT		 319
320/* SCC events */
321#define RxEvt 0xf0000000
322#define TxEvt 0x0f000000
323#define Alls 0x00040000
324#define Xdu 0x00010000
325#define Cts 0x00004000
326#define Xmr 0x00002000
327#define Xpr 0x00001000
328#define Rdo 0x00000080
329#define Rfs 0x00000040
330#define Cd 0x00000004
331#define Rfo 0x00000002
332#define Flex 0x00000001
333
334/* DMA core events */
335#define Cfg 0x00200000
336#define Hi 0x00040000
337#define Fi 0x00020000
338#define Err 0x00010000
339#define Arf 0x00000002
340#define ArAck 0x00000001
341
342/* State flags */
343#define Ready 0x00000000
344#define NeedIDR 0x00000001
345#define NeedIDT 0x00000002
346#define RdoSet 0x00000004
347#define FakeReset 0x00000008
348
349/* Don't mask RDO. Ever. */
350#ifdef DSCC4_POLLING
351#define EventsMask 0xfffeef7f
352#else
353#define EventsMask 0xfffa8f7a
354#endif
355
356/* Functions prototypes */
357static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
358static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
359static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
360static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
361static int dscc4_open(struct net_device *);
362static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
363static int dscc4_close(struct net_device *);
364static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
365static int dscc4_init_ring(struct net_device *);
366static void dscc4_release_ring(struct dscc4_dev_priv *);
367static void dscc4_timer(unsigned long);
368static void dscc4_tx_timeout(struct net_device *);
7d12e780 369static irqreturn_t dscc4_irq(int irq, void *dev_id);
1da177e4
LT		 370static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
371static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
372#ifdef DSCC4_POLLING
373static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
374#endif
375
376static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
377{
378 return dev_to_hdlc(dev)->priv;
379}
380
381static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
382{
383 return p->dev;
384}
385
386static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
387 struct net_device *dev, int offset)
388{
389 u32 state;
390
391 /* Cf scc_writel for concern regarding thread-safety */
392 state = dpriv->scc_regs[offset >> 2];
393 state &= ~mask;
394 state |= value;
395 dpriv->scc_regs[offset >> 2] = state;
396 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
397}
398
399static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
400 struct net_device *dev, int offset)
401{
402 /*
403 * Thread-UNsafe.
404 * As of 2002/02/16, there are no thread racing for access.
405 */
406 dpriv->scc_regs[offset >> 2] = bits;
407 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
408}
409
410static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
411{
412 return dpriv->scc_regs[offset >> 2];
413}
414
415static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
416{
417 /* Cf errata DS5 p.4 */
418 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
419 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
420}
421
422static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
423 struct net_device *dev)
424{
425 dpriv->ltda = dpriv->tx_fd_dma +
426 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
427 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
428 /* Flush posted writes *NOW* */
429 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
430}
431
432static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
433 struct net_device *dev)
434{
435 dpriv->lrda = dpriv->rx_fd_dma +
436 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
437 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
438}
439
440static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
441{
442 return dpriv->tx_current == dpriv->tx_dirty;
443}
444
445static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
446 struct net_device *dev)
447{
448 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
449}
450
7665a089
AB		 451static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
452 struct net_device *dev, const char *msg)
1da177e4
LT		 453{
454 int ret = 0;
455
456 if (debug > 1) {
457 if (SOURCE_ID(state) != dpriv->dev_id) {
458 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
459 dev->name, msg, SOURCE_ID(state), state );
460 ret = -1;
461 }
462 if (state & 0x0df80c00) {
463 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
464 dev->name, msg, state);
465 ret = -1;
466 }
467 }
468 return ret;
469}
470
7665a089
AB		 471static void dscc4_tx_print(struct net_device *dev,
472 struct dscc4_dev_priv *dpriv,
473 char *msg)
1da177e4
LT		 474{
475 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
476 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
477}
478
479static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
480{
481 struct pci_dev *pdev = dpriv->pci_priv->pdev;
482 struct TxFD *tx_fd = dpriv->tx_fd;
483 struct RxFD *rx_fd = dpriv->rx_fd;
484 struct sk_buff **skbuff;
485 int i;
486
487 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
488 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
489
490 skbuff = dpriv->tx_skbuff;
491 for (i = 0; i < TX_RING_SIZE; i++) {
492 if (*skbuff) {
409cd63e
AV		 493 pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
494 (*skbuff)->len, PCI_DMA_TODEVICE);
1da177e4
LT		 495 dev_kfree_skb(*skbuff);
496 }
497 skbuff++;
498 tx_fd++;
499 }
500
501 skbuff = dpriv->rx_skbuff;
502 for (i = 0; i < RX_RING_SIZE; i++) {
503 if (*skbuff) {
409cd63e 504 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
1da177e4
LT		 505 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
506 dev_kfree_skb(*skbuff);
507 }
508 skbuff++;
509 rx_fd++;
510 }
511}
512
7665a089
AB		 513static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
514 struct net_device *dev)
1da177e4
LT		 515{
516 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
517 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
518 const int len = RX_MAX(HDLC_MAX_MRU);
519 struct sk_buff *skb;
520 int ret = 0;
521
522 skb = dev_alloc_skb(len);
523 dpriv->rx_skbuff[dirty] = skb;
524 if (skb) {
525 skb->protocol = hdlc_type_trans(skb, dev);
409cd63e
AV		 526 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
527 skb->data, len, PCI_DMA_FROMDEVICE));
1da177e4 528 } else {
409cd63e 529 rx_fd->data = 0;
1da177e4
LT		 530 ret = -1;
531 }
532 return ret;
533}
534
535/*
536 * IRQ/thread/whatever safe
537 */
538static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
539 struct net_device *dev, char *msg)
540{
541 s8 i = 0;
542
543 do {
544 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
545 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
546 msg, i);
547 goto done;
548 }
3173c890 549 schedule_timeout_uninterruptible(10);
1da177e4
LT		 550 rmb();
551 } while (++i > 0);
552 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
553done:
554 return (i >= 0) ? i : -EAGAIN;
555}
556
557static int dscc4_do_action(struct net_device *dev, char *msg)
558{
559 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
560 s16 i = 0;
561
562 writel(Action, ioaddr + GCMDR);
563 ioaddr += GSTAR;
564 do {
565 u32 state = readl(ioaddr);
566
567 if (state & ArAck) {
568 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
569 writel(ArAck, ioaddr);
570 goto done;
571 } else if (state & Arf) {
572 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
573 writel(Arf, ioaddr);
574 i = -1;
575 goto done;
576 }
577 rmb();
578 } while (++i > 0);
579 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
580done:
581 return i;
582}
583
584static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
585{
586 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
587 s8 i = 0;
588
589 do {
590 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
409cd63e 591 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
1da177e4
LT		 592 break;
593 smp_rmb();
3173c890 594 schedule_timeout_uninterruptible(10);
1da177e4
LT		 595 } while (++i > 0);
596
597 return (i >= 0 ) ? i : -EAGAIN;
598}
599
600#if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
601static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
602{
603 unsigned long flags;
604
605 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
606 /* Cf errata DS5 p.6 */
607 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
608 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
609 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
610 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
611 writel(Action, dpriv->base_addr + GCMDR);
612 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
613}
614
615#endif
616
617#if 0
618static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
619{
620 u16 i = 0;
621
622 /* Cf errata DS5 p.7 */
623 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
624 scc_writel(0x00050000, dpriv, dev, CCR2);
625 /*
626 * Must be longer than the time required to fill the fifo.
627 */
628 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
629 udelay(1);
630 wmb();
631 }
632
633 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
634 if (dscc4_do_action(dev, "Rdt") < 0)
635 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
636}
637#endif
638
639/* TODO: (ab)use this function to refill a completely depleted RX ring. */
640static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
641 struct net_device *dev)
642{
643 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
1da177e4
LT		 644 struct pci_dev *pdev = dpriv->pci_priv->pdev;
645 struct sk_buff *skb;
646 int pkt_len;
647
648 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
649 if (!skb) {
b39d66a8 650 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
1da177e4
LT		 651 goto refill;
652 }
409cd63e
AV		 653 pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
654 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
655 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
1da177e4 656 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
198191c4
KH		 657 dev->stats.rx_packets++;
658 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 659 skb_put(skb, pkt_len);
660 if (netif_running(dev))
661 skb->protocol = hdlc_type_trans(skb, dev);
662 skb->dev->last_rx = jiffies;
663 netif_rx(skb);
664 } else {
665 if (skb->data[pkt_len] & FrameRdo)
198191c4 666 dev->stats.rx_fifo_errors++;
1da177e4 667 else if (!(skb->data[pkt_len] | ~FrameCrc))
198191c4 668 dev->stats.rx_crc_errors++;
1da177e4 669 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
198191c4 670 dev->stats.rx_length_errors++;
1da177e4 671 else
198191c4 672 dev->stats.rx_errors++;
1da177e4
LT		 673 dev_kfree_skb_irq(skb);
674 }
675refill:
676 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
677 if (try_get_rx_skb(dpriv, dev) < 0)
678 break;
679 dpriv->rx_dirty++;
680 }
681 dscc4_rx_update(dpriv, dev);
682 rx_fd->state2 = 0x00000000;
409cd63e 683 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 684}
685
686static void dscc4_free1(struct pci_dev *pdev)
687{
688 struct dscc4_pci_priv *ppriv;
689 struct dscc4_dev_priv *root;
690 int i;
691
692 ppriv = pci_get_drvdata(pdev);
693 root = ppriv->root;
694
695 for (i = 0; i < dev_per_card; i++)
696 unregister_hdlc_device(dscc4_to_dev(root + i));
697
698 pci_set_drvdata(pdev, NULL);
699
700 for (i = 0; i < dev_per_card; i++)
701 free_netdev(root[i].dev);
702 kfree(root);
703 kfree(ppriv);
704}
705
706static int __devinit dscc4_init_one(struct pci_dev *pdev,
707 const struct pci_device_id *ent)
708{
709 struct dscc4_pci_priv *priv;
710 struct dscc4_dev_priv *dpriv;
711 void __iomem *ioaddr;
712 int i, rc;
713
714 printk(KERN_DEBUG "%s", version);
715
716 rc = pci_enable_device(pdev);
717 if (rc < 0)
718 goto out;
719
720 rc = pci_request_region(pdev, 0, "registers");
721 if (rc < 0) {
722 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
723 DRV_NAME);
724 goto err_disable_0;
725 }
726 rc = pci_request_region(pdev, 1, "LBI interface");
727 if (rc < 0) {
728 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
729 DRV_NAME);
730 goto err_free_mmio_region_1;
731 }
732
733 ioaddr = ioremap(pci_resource_start(pdev, 0),
734 pci_resource_len(pdev, 0));
735 if (!ioaddr) {
7c7459d1
GKH		 736 printk(KERN_ERR "%s: cannot remap MMIO region %llx @ %llx\n",
737 DRV_NAME, (unsigned long long)pci_resource_len(pdev, 0),
738 (unsigned long long)pci_resource_start(pdev, 0));
1da177e4
LT		 739 rc = -EIO;
740 goto err_free_mmio_regions_2;
741 }
7c7459d1
GKH		 742 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
743 (unsigned long long)pci_resource_start(pdev, 0),
744 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
1da177e4
LT		 745
746 /* Cf errata DS5 p.2 */
747 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
748 pci_set_master(pdev);
749
750 rc = dscc4_found1(pdev, ioaddr);
751 if (rc < 0)
752 goto err_iounmap_3;
753
754 priv = pci_get_drvdata(pdev);
755
1fb9df5d 756 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
1da177e4
LT		 757 if (rc < 0) {
758 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
759 goto err_release_4;
760 }
761
762 /* power up/little endian/dma core controlled via lrda/ltda */
763 writel(0x00000001, ioaddr + GMODE);
764 /* Shared interrupt queue */
765 {
766 u32 bits;
767
768 bits = (IRQ_RING_SIZE >> 5) - 1;
769 bits |= bits << 4;
770 bits |= bits << 8;
771 bits |= bits << 16;
772 writel(bits, ioaddr + IQLENR0);
773 }
774 /* Global interrupt queue */
775 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
409cd63e
AV		 776 priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
777 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
1da177e4
LT		 778 if (!priv->iqcfg)
779 goto err_free_irq_5;
780 writel(priv->iqcfg_dma, ioaddr + IQCFG);
781
782 rc = -ENOMEM;
783
784 /*
785 * SCC 0-3 private rx/tx irq structures
786 * IQRX/TXi needs to be set soon. Learned it the hard way...
787 */
788 for (i = 0; i < dev_per_card; i++) {
789 dpriv = priv->root + i;
409cd63e 790 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
1da177e4
LT		 791 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
792 if (!dpriv->iqtx)
793 goto err_free_iqtx_6;
794 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
795 }
796 for (i = 0; i < dev_per_card; i++) {
797 dpriv = priv->root + i;
409cd63e 798 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
1da177e4
LT		 799 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
800 if (!dpriv->iqrx)
801 goto err_free_iqrx_7;
802 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
803 }
804
805 /* Cf application hint. Beware of hard-lock condition on threshold. */
806 writel(0x42104000, ioaddr + FIFOCR1);
807 //writel(0x9ce69800, ioaddr + FIFOCR2);
808 writel(0xdef6d800, ioaddr + FIFOCR2);
809 //writel(0x11111111, ioaddr + FIFOCR4);
810 writel(0x18181818, ioaddr + FIFOCR4);
811 // FIXME: should depend on the chipset revision
812 writel(0x0000000e, ioaddr + FIFOCR3);
813
814 writel(0xff200001, ioaddr + GCMDR);
815
816 rc = 0;
817out:
818 return rc;
819
820err_free_iqrx_7:
821 while (--i >= 0) {
822 dpriv = priv->root + i;
823 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
824 dpriv->iqrx, dpriv->iqrx_dma);
825 }
826 i = dev_per_card;
827err_free_iqtx_6:
828 while (--i >= 0) {
829 dpriv = priv->root + i;
830 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
831 dpriv->iqtx, dpriv->iqtx_dma);
832 }
833 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
834 priv->iqcfg_dma);
835err_free_irq_5:
836 free_irq(pdev->irq, priv->root);
837err_release_4:
838 dscc4_free1(pdev);
839err_iounmap_3:
840 iounmap (ioaddr);
841err_free_mmio_regions_2:
842 pci_release_region(pdev, 1);
843err_free_mmio_region_1:
844 pci_release_region(pdev, 0);
845err_disable_0:
846 pci_disable_device(pdev);
847 goto out;
848};
849
850/*
851 * Let's hope the default values are decent enough to protect my
852 * feet from the user's gun - Ueimor
853 */
854static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
855 struct net_device *dev)
856{
857 /* No interrupts, SCC core disabled. Let's relax */
858 scc_writel(0x00000000, dpriv, dev, CCR0);
859
860 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
861
862 /*
863 * No address recognition/crc-CCITT/cts enabled
864 * Shared flags transmission disabled - cf errata DS5 p.11
865 * Carrier detect disabled - cf errata p.14
866 * FIXME: carrier detection/polarity may be handled more gracefully.
867 */
868 scc_writel(0x02408000, dpriv, dev, CCR1);
869
870 /* crc not forwarded - Cf errata DS5 p.11 */
871 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
872 // crc forwarded
873 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
874}
875
876static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
877{
878 int ret = 0;
879
880 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
881 ret = -EOPNOTSUPP;
882 else
883 dpriv->pci_priv->xtal_hz = hz;
884
885 return ret;
886}
887
888static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
889{
890 struct dscc4_pci_priv *ppriv;
891 struct dscc4_dev_priv *root;
892 int i, ret = -ENOMEM;
893
dd00cc48 894 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
1da177e4
LT		 895 if (!root) {
896 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
897 goto err_out;
898 }
1da177e4
LT		 899
900 for (i = 0; i < dev_per_card; i++) {
901 root[i].dev = alloc_hdlcdev(root + i);
902 if (!root[i].dev)
903 goto err_free_dev;
904 }
905
dd00cc48 906 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
1da177e4
LT		 907 if (!ppriv) {
908 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
909 goto err_free_dev;
910 }
1da177e4
LT		 911
912 ppriv->root = root;
913 spin_lock_init(&ppriv->lock);
914
915 for (i = 0; i < dev_per_card; i++) {
916 struct dscc4_dev_priv *dpriv = root + i;
917 struct net_device *d = dscc4_to_dev(dpriv);
918 hdlc_device *hdlc = dev_to_hdlc(d);
919
920 d->base_addr = (unsigned long)ioaddr;
921 d->init = NULL;
922 d->irq = pdev->irq;
923 d->open = dscc4_open;
924 d->stop = dscc4_close;
925 d->set_multicast_list = NULL;
926 d->do_ioctl = dscc4_ioctl;
927 d->tx_timeout = dscc4_tx_timeout;
928 d->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 929 SET_NETDEV_DEV(d, &pdev->dev);
930
931 dpriv->dev_id = i;
932 dpriv->pci_priv = ppriv;
933 dpriv->base_addr = ioaddr;
934 spin_lock_init(&dpriv->lock);
935
936 hdlc->xmit = dscc4_start_xmit;
937 hdlc->attach = dscc4_hdlc_attach;
938
939 dscc4_init_registers(dpriv, d);
940 dpriv->parity = PARITY_CRC16_PR0_CCITT;
941 dpriv->encoding = ENCODING_NRZ;
942
943 ret = dscc4_init_ring(d);
944 if (ret < 0)
945 goto err_unregister;
946
947 ret = register_hdlc_device(d);
948 if (ret < 0) {
949 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
950 dscc4_release_ring(dpriv);
951 goto err_unregister;
952 }
953 }
954
955 ret = dscc4_set_quartz(root, quartz);
956 if (ret < 0)
957 goto err_unregister;
958
959 pci_set_drvdata(pdev, ppriv);
960 return ret;
961
962err_unregister:
963 while (i-- > 0) {
964 dscc4_release_ring(root + i);
965 unregister_hdlc_device(dscc4_to_dev(root + i));
966 }
967 kfree(ppriv);
968 i = dev_per_card;
969err_free_dev:
970 while (i-- > 0)
971 free_netdev(root[i].dev);
972 kfree(root);
973err_out:
974 return ret;
975};
976
977/* FIXME: get rid of the unneeded code */
978static void dscc4_timer(unsigned long data)
979{
980 struct net_device *dev = (struct net_device *)data;
981 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
982// struct dscc4_pci_priv *ppriv;
983
984 goto done;
985done:
986 dpriv->timer.expires = jiffies + TX_TIMEOUT;
987 add_timer(&dpriv->timer);
988}
989
990static void dscc4_tx_timeout(struct net_device *dev)
991{
992 /* FIXME: something is missing there */
993}
994
995static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
996{
997 sync_serial_settings *settings = &dpriv->settings;
998
999 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
1000 struct net_device *dev = dscc4_to_dev(dpriv);
1001
1002 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
1003 return -1;
1004 }
1005 return 0;
1006}
1007
1008#ifdef CONFIG_DSCC4_PCI_RST
1009/*
1010 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1011 * so as to provide a safe way to reset the asic while not the whole machine
1012 * rebooting.
1013 *
1014 * This code doesn't need to be efficient. Keep It Simple
1015 */
1016static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1017{
1018 int i;
1019
14cc3e2b 1020 mutex_lock(&dscc4_mutex);
1da177e4
LT		 1021 for (i = 0; i < 16; i++)
1022 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1023
1024 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1025 writel(0x001c0000, ioaddr + GMODE);
1026 /* Configure GPIO port as output */
1027 writel(0x0000ffff, ioaddr + GPDIR);
1028 /* Disable interruption */
1029 writel(0x0000ffff, ioaddr + GPIM);
1030
1031 writel(0x0000ffff, ioaddr + GPDATA);
1032 writel(0x00000000, ioaddr + GPDATA);
1033
1034 /* Flush posted writes */
1035 readl(ioaddr + GSTAR);
1036
3173c890 1037 schedule_timeout_uninterruptible(10);
1da177e4
LT		 1038
1039 for (i = 0; i < 16; i++)
1040 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
14cc3e2b 1041 mutex_unlock(&dscc4_mutex);
1da177e4
LT		 1042}
1043#else
1044#define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1045#endif /* CONFIG_DSCC4_PCI_RST */
1046
1047static int dscc4_open(struct net_device *dev)
1048{
1049 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1050 struct dscc4_pci_priv *ppriv;
1051 int ret = -EAGAIN;
1052
1053 if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
1054 goto err;
1055
1056 if ((ret = hdlc_open(dev)))
1057 goto err;
1058
1059 ppriv = dpriv->pci_priv;
1060
1061 /*
1062 * Due to various bugs, there is no way to reliably reset a
1063 * specific port (manufacturer's dependant special PCI #RST wiring
1064 * apart: it affects all ports). Thus the device goes in the best
1065 * silent mode possible at dscc4_close() time and simply claims to
1066 * be up if it's opened again. It still isn't possible to change
1067 * the HDLC configuration without rebooting but at least the ports
1068 * can be up/down ifconfig'ed without killing the host.
1069 */
1070 if (dpriv->flags & FakeReset) {
1071 dpriv->flags &= ~FakeReset;
1072 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1073 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1074 scc_writel(EventsMask, dpriv, dev, IMR);
1075 printk(KERN_INFO "%s: up again.\n", dev->name);
1076 goto done;
1077 }
1078
1079 /* IDT+IDR during XPR */
1080 dpriv->flags = NeedIDR | NeedIDT;
1081
1082 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1083
1084 /*
1085 * The following is a bit paranoid...
1086 *
1087 * NB: the datasheet "...CEC will stay active if the SCC is in
1088 * power-down mode or..." and CCR2.RAC = 1 are two different
1089 * situations.
1090 */
1091 if (scc_readl_star(dpriv, dev) & SccBusy) {
1092 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1093 ret = -EAGAIN;
1094 goto err_out;
1095 } else
1096 printk(KERN_INFO "%s: available. Good\n", dev->name);
1097
1098 scc_writel(EventsMask, dpriv, dev, IMR);
1099
1100 /* Posted write is flushed in the wait_ack loop */
1101 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1102
1103 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1104 goto err_disable_scc_events;
1105
1106 /*
1107 * I would expect XPR near CE completion (before ? after ?).
1108 * At worst, this code won't see a late XPR and people
1109 * will have to re-issue an ifconfig (this is harmless).
1110 * WARNING, a really missing XPR usually means a hardware
1111 * reset is needed. Suggestions anyone ?
1112 */
1113 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1114 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1115 goto err_disable_scc_events;
1116 }
1117
1118 if (debug > 2)
1119 dscc4_tx_print(dev, dpriv, "Open");
1120
1121done:
1122 netif_start_queue(dev);
1123
1124 init_timer(&dpriv->timer);
1125 dpriv->timer.expires = jiffies + 10*HZ;
1126 dpriv->timer.data = (unsigned long)dev;
1127 dpriv->timer.function = &dscc4_timer;
1128 add_timer(&dpriv->timer);
1129 netif_carrier_on(dev);
1130
1131 return 0;
1132
1133err_disable_scc_events:
1134 scc_writel(0xffffffff, dpriv, dev, IMR);
1135 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1136err_out:
1137 hdlc_close(dev);
1138err:
1139 return ret;
1140}
1141
1142#ifdef DSCC4_POLLING
1143static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1144{
1145 /* FIXME: it's gonna be easy (TM), for sure */
1146}
1147#endif /* DSCC4_POLLING */
1148
1149static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
1150{
1151 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1152 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1153 struct TxFD *tx_fd;
1154 int next;
1155
1156 next = dpriv->tx_current%TX_RING_SIZE;
1157 dpriv->tx_skbuff[next] = skb;
1158 tx_fd = dpriv->tx_fd + next;
1159 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
409cd63e
AV		 1160 tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1161 PCI_DMA_TODEVICE));
1da177e4
LT		 1162 tx_fd->complete = 0x00000000;
1163 tx_fd->jiffies = jiffies;
1164 mb();
1165
1166#ifdef DSCC4_POLLING
1167 spin_lock(&dpriv->lock);
1168 while (dscc4_tx_poll(dpriv, dev));
1169 spin_unlock(&dpriv->lock);
1170#endif
1171
1172 dev->trans_start = jiffies;
1173
1174 if (debug > 2)
1175 dscc4_tx_print(dev, dpriv, "Xmit");
1176 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1177 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1178 netif_stop_queue(dev);
1179
1180 if (dscc4_tx_quiescent(dpriv, dev))
1181 dscc4_do_tx(dpriv, dev);
1182
1183 return 0;
1184}
1185
1186static int dscc4_close(struct net_device *dev)
1187{
1188 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1189
1190 del_timer_sync(&dpriv->timer);
1191 netif_stop_queue(dev);
1192
1193 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1194 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1195 scc_writel(0xffffffff, dpriv, dev, IMR);
1196
1197 dpriv->flags |= FakeReset;
1198
1199 hdlc_close(dev);
1200
1201 return 0;
1202}
1203
1204static inline int dscc4_check_clock_ability(int port)
1205{
1206 int ret = 0;
1207
1208#ifdef CONFIG_DSCC4_PCISYNC
1209 if (port >= 2)
1210 ret = -1;
1211#endif
1212 return ret;
1213}
1214
1215/*
1216 * DS1 p.137: "There are a total of 13 different clocking modes..."
1217 * ^^
1218 * Design choices:
1219 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1220 * Clock mode 3b _should_ work but the testing seems to make this point
1221 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1222 * This is supposed to provide least surprise "DTE like" behavior.
1223 * - if line rate is specified, clocks are assumed to be locally generated.
1224 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1225 * between these it automagically done according on the required frequency
1226 * scaling. Of course some rounding may take place.
1227 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1228 * appropriate external clocking device for testing.
1229 * - no time-slot/clock mode 5: shameless lazyness.
1230 *
1231 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1232 *
1233 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1234 * won't pass the init sequence. For example, straight back-to-back DTE without
1235 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1236 * called.
1237 *
1238 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1239 * DS0 for example)
1240 *
1241 * Clock mode related bits of CCR0:
1242 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1243 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1244 * | | +-------- High Speed: say 0
1245 * | | | +-+-+-- Clock Mode: 0..7
1246 * | | | | | |
1247 * -+-+-+-+-+-+-+-+
1248 * x|x|5|4|3|2|1|0| lower bits
1249 *
1250 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1251 * +-+-+-+------------------ M (0..15)
1252 * | | | | +-+-+-+-+-+-- N (0..63)
1253 * 0 0 0 0 | | | | 0 0 | | | | | |
1254 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1255 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1256 *
1257 */
1258static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1259{
1260 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1261 int ret = -1;
1262 u32 brr;
1263
1264 *state &= ~Ccr0ClockMask;
1265 if (*bps) { /* Clock generated - required for DCE */
1266 u32 n = 0, m = 0, divider;
1267 int xtal;
1268
1269 xtal = dpriv->pci_priv->xtal_hz;
1270 if (!xtal)
1271 goto done;
1272 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1273 goto done;
1274 divider = xtal / *bps;
1275 if (divider > BRR_DIVIDER_MAX) {
1276 divider >>= 4;
1277 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1278 } else
1279 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1280 if (divider >> 22) {
1281 n = 63;
1282 m = 15;
1283 } else if (divider) {
1284 /* Extraction of the 6 highest weighted bits */
1285 m = 0;
1286 while (0xffffffc0 & divider) {
1287 m++;
1288 divider >>= 1;
1289 }
1290 n = divider;
1291 }
1292 brr = (m << 8) | n;
1293 divider = n << m;
1294 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1295 divider <<= 4;
1296 *bps = xtal / divider;
1297 } else {
1298 /*
1299 * External clock - DTE
1300 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1301 * Nothing more to be done
1302 */
1303 brr = 0;
1304 }
1305 scc_writel(brr, dpriv, dev, BRR);
1306 ret = 0;
1307done:
1308 return ret;
1309}
1310
1311static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1312{
1313 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1314 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1315 const size_t size = sizeof(dpriv->settings);
1316 int ret = 0;
1317
1318 if (dev->flags & IFF_UP)
1319 return -EBUSY;
1320
1321 if (cmd != SIOCWANDEV)
1322 return -EOPNOTSUPP;
1323
1324 switch(ifr->ifr_settings.type) {
1325 case IF_GET_IFACE:
1326 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1327 if (ifr->ifr_settings.size < size) {
1328 ifr->ifr_settings.size = size; /* data size wanted */
1329 return -ENOBUFS;
1330 }
1331 if (copy_to_user(line, &dpriv->settings, size))
1332 return -EFAULT;
1333 break;
1334
1335 case IF_IFACE_SYNC_SERIAL:
1336 if (!capable(CAP_NET_ADMIN))
1337 return -EPERM;
1338
1339 if (dpriv->flags & FakeReset) {
1340 printk(KERN_INFO "%s: please reset the device"
1341 " before this command\n", dev->name);
1342 return -EPERM;
1343 }
1344 if (copy_from_user(&dpriv->settings, line, size))
1345 return -EFAULT;
1346 ret = dscc4_set_iface(dpriv, dev);
1347 break;
1348
1349 default:
1350 ret = hdlc_ioctl(dev, ifr, cmd);
1351 break;
1352 }
1353
1354 return ret;
1355}
1356
1357static int dscc4_match(struct thingie *p, int value)
1358{
1359 int i;
1360
1361 for (i = 0; p[i].define != -1; i++) {
1362 if (value == p[i].define)
1363 break;
1364 }
1365 if (p[i].define == -1)
1366 return -1;
1367 else
1368 return i;
1369}
1370
1371static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1372 struct net_device *dev)
1373{
1374 sync_serial_settings *settings = &dpriv->settings;
1375 int ret = -EOPNOTSUPP;
1376 u32 bps, state;
1377
1378 bps = settings->clock_rate;
1379 state = scc_readl(dpriv, CCR0);
1380 if (dscc4_set_clock(dev, &bps, &state) < 0)
1381 goto done;
1382 if (bps) { /* DCE */
1383 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1384 if (settings->clock_rate != bps) {
1385 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1386 dev->name, settings->clock_rate, bps);
1387 settings->clock_rate = bps;
1388 }
1389 } else { /* DTE */
1390 state |= PowerUp | Vis;
1391 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1392 }
1393 scc_writel(state, dpriv, dev, CCR0);
1394 ret = 0;
1395done:
1396 return ret;
1397}
1398
1399static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1400 struct net_device *dev)
1401{
1402 struct thingie encoding[] = {
1403 { ENCODING_NRZ, 0x00000000 },
1404 { ENCODING_NRZI, 0x00200000 },
1405 { ENCODING_FM_MARK, 0x00400000 },
1406 { ENCODING_FM_SPACE, 0x00500000 },
1407 { ENCODING_MANCHESTER, 0x00600000 },
1408 { -1, 0}
1409 };
1410 int i, ret = 0;
1411
1412 i = dscc4_match(encoding, dpriv->encoding);
1413 if (i >= 0)
1414 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1415 else
1416 ret = -EOPNOTSUPP;
1417 return ret;
1418}
1419
1420static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1421 struct net_device *dev)
1422{
1423 sync_serial_settings *settings = &dpriv->settings;
1424 u32 state;
1425
1426 state = scc_readl(dpriv, CCR1);
1427 if (settings->loopback) {
1428 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1429 state |= 0x00000100;
1430 } else {
1431 printk(KERN_DEBUG "%s: normal\n", dev->name);
1432 state &= ~0x00000100;
1433 }
1434 scc_writel(state, dpriv, dev, CCR1);
1435 return 0;
1436}
1437
1438static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1439 struct net_device *dev)
1440{
1441 struct thingie crc[] = {
1442 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1443 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1444 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1445 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1446 };
1447 int i, ret = 0;
1448
1449 i = dscc4_match(crc, dpriv->parity);
1450 if (i >= 0)
1451 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1452 else
1453 ret = -EOPNOTSUPP;
1454 return ret;
1455}
1456
1457static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1458{
1459 struct {
1460 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1461 } *p, do_setting[] = {
1462 { dscc4_encoding_setting },
1463 { dscc4_clock_setting },
1464 { dscc4_loopback_setting },
1465 { dscc4_crc_setting },
1466 { NULL }
1467 };
1468 int ret = 0;
1469
1470 for (p = do_setting; p->action; p++) {
1471 if ((ret = p->action(dpriv, dev)) < 0)
1472 break;
1473 }
1474 return ret;
1475}
1476
7d12e780 1477static irqreturn_t dscc4_irq(int irq, void *token)
1da177e4
LT		 1478{
1479 struct dscc4_dev_priv *root = token;
1480 struct dscc4_pci_priv *priv;
1481 struct net_device *dev;
1482 void __iomem *ioaddr;
1483 u32 state;
1484 unsigned long flags;
1485 int i, handled = 1;
1486
1487 priv = root->pci_priv;
1488 dev = dscc4_to_dev(root);
1489
1490 spin_lock_irqsave(&priv->lock, flags);
1491
1492 ioaddr = root->base_addr;
1493
1494 state = readl(ioaddr + GSTAR);
1495 if (!state) {
1496 handled = 0;
1497 goto out;
1498 }
1499 if (debug > 3)
1500 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1501 writel(state, ioaddr + GSTAR);
1502
1503 if (state & Arf) {
1504 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1505 dev->name);
1506 goto out;
1507 }
1508 state &= ~ArAck;
1509 if (state & Cfg) {
1510 if (debug > 0)
1511 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
409cd63e 1512 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
1da177e4
LT		 1513 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1514 if (!(state &= ~Cfg))
1515 goto out;
1516 }
1517 if (state & RxEvt) {
1518 i = dev_per_card - 1;
1519 do {
1520 dscc4_rx_irq(priv, root + i);
1521 } while (--i >= 0);
1522 state &= ~RxEvt;
1523 }
1524 if (state & TxEvt) {
1525 i = dev_per_card - 1;
1526 do {
1527 dscc4_tx_irq(priv, root + i);
1528 } while (--i >= 0);
1529 state &= ~TxEvt;
1530 }
1531out:
1532 spin_unlock_irqrestore(&priv->lock, flags);
1533 return IRQ_RETVAL(handled);
1534}
1535
1536static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1537 struct dscc4_dev_priv *dpriv)
1538{
1539 struct net_device *dev = dscc4_to_dev(dpriv);
1540 u32 state;
1541 int cur, loop = 0;
1542
1543try:
1544 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
409cd63e 1545 state = le32_to_cpu(dpriv->iqtx[cur]);
1da177e4
LT		 1546 if (!state) {
1547 if (debug > 4)
1548 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1549 state);
1550 if ((debug > 1) && (loop > 1))
1551 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1552 if (loop && netif_queue_stopped(dev))
1553 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1554 netif_wake_queue(dev);
1555
1556 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1557 !dscc4_tx_done(dpriv))
1558 dscc4_do_tx(dpriv, dev);
1559 return;
1560 }
1561 loop++;
1562 dpriv->iqtx[cur] = 0;
1563 dpriv->iqtx_current++;
1564
1565 if (state_check(state, dpriv, dev, "Tx") < 0)
1566 return;
1567
1568 if (state & SccEvt) {
1569 if (state & Alls) {
1da177e4
LT		 1570 struct sk_buff *skb;
1571 struct TxFD *tx_fd;
1572
1573 if (debug > 2)
1574 dscc4_tx_print(dev, dpriv, "Alls");
1575 /*
1576 * DataComplete can't be trusted for Tx completion.
1577 * Cf errata DS5 p.8
1578 */
1579 cur = dpriv->tx_dirty%TX_RING_SIZE;
1580 tx_fd = dpriv->tx_fd + cur;
1581 skb = dpriv->tx_skbuff[cur];
1582 if (skb) {
409cd63e 1583 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1da177e4
LT		 1584 skb->len, PCI_DMA_TODEVICE);
1585 if (tx_fd->state & FrameEnd) {
198191c4
KH		 1586 dev->stats.tx_packets++;
1587 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 1588 }
1589 dev_kfree_skb_irq(skb);
1590 dpriv->tx_skbuff[cur] = NULL;
1591 ++dpriv->tx_dirty;
1592 } else {
1593 if (debug > 1)
1594 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1595 dev->name, cur);
1596 }
1597 /*
1598 * If the driver ends sending crap on the wire, it
1599 * will be way easier to diagnose than the (not so)
1600 * random freeze induced by null sized tx frames.
1601 */
1602 tx_fd->data = tx_fd->next;
1603 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1604 tx_fd->complete = 0x00000000;
1605 tx_fd->jiffies = 0;
1606
1607 if (!(state &= ~Alls))
1608 goto try;
1609 }
1610 /*
1611 * Transmit Data Underrun
1612 */
1613 if (state & Xdu) {
1614 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1615 dpriv->flags = NeedIDT;
1616 /* Tx reset */
1617 writel(MTFi | Rdt,
1618 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1619 writel(Action, dpriv->base_addr + GCMDR);
1620 return;
1621 }
1622 if (state & Cts) {
1623 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1624 if (!(state &= ~Cts)) /* DEBUG */
1625 goto try;
1626 }
1627 if (state & Xmr) {
1628 /* Frame needs to be sent again - FIXME */
1629 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1630 if (!(state &= ~Xmr)) /* DEBUG */
1631 goto try;
1632 }
1633 if (state & Xpr) {
1634 void __iomem *scc_addr;
1635 unsigned long ring;
1636 int i;
1637
1638 /*
1639 * - the busy condition happens (sometimes);
1640 * - it doesn't seem to make the handler unreliable.
1641 */
1642 for (i = 1; i; i <<= 1) {
1643 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1644 break;
1645 }
1646 if (!i)
1647 printk(KERN_INFO "%s busy in irq\n", dev->name);
1648
1649 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1650 /* Keep this order: IDT before IDR */
1651 if (dpriv->flags & NeedIDT) {
1652 if (debug > 2)
1653 dscc4_tx_print(dev, dpriv, "Xpr");
1654 ring = dpriv->tx_fd_dma +
1655 (dpriv->tx_dirty%TX_RING_SIZE)*
1656 sizeof(struct TxFD);
1657 writel(ring, scc_addr + CH0BTDA);
1658 dscc4_do_tx(dpriv, dev);
1659 writel(MTFi | Idt, scc_addr + CH0CFG);
1660 if (dscc4_do_action(dev, "IDT") < 0)
1661 goto err_xpr;
1662 dpriv->flags &= ~NeedIDT;
1663 }
1664 if (dpriv->flags & NeedIDR) {
1665 ring = dpriv->rx_fd_dma +
1666 (dpriv->rx_current%RX_RING_SIZE)*
1667 sizeof(struct RxFD);
1668 writel(ring, scc_addr + CH0BRDA);
1669 dscc4_rx_update(dpriv, dev);
1670 writel(MTFi | Idr, scc_addr + CH0CFG);
1671 if (dscc4_do_action(dev, "IDR") < 0)
1672 goto err_xpr;
1673 dpriv->flags &= ~NeedIDR;
1674 smp_wmb();
1675 /* Activate receiver and misc */
1676 scc_writel(0x08050008, dpriv, dev, CCR2);
1677 }
1678 err_xpr:
1679 if (!(state &= ~Xpr))
1680 goto try;
1681 }
1682 if (state & Cd) {
1683 if (debug > 0)
1684 printk(KERN_INFO "%s: CD transition\n", dev->name);
1685 if (!(state &= ~Cd)) /* DEBUG */
1686 goto try;
1687 }
1688 } else { /* ! SccEvt */
1689 if (state & Hi) {
1690#ifdef DSCC4_POLLING
1691 while (!dscc4_tx_poll(dpriv, dev));
1692#endif
1693 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1694 state &= ~Hi;
1695 }
1696 if (state & Err) {
1697 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
198191c4 1698 dev->stats.tx_errors++;
1da177e4
LT		 1699 state &= ~Err;
1700 }
1701 }
1702 goto try;
1703}
1704
1705static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1706 struct dscc4_dev_priv *dpriv)
1707{
1708 struct net_device *dev = dscc4_to_dev(dpriv);
1709 u32 state;
1710 int cur;
1711
1712try:
1713 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
409cd63e 1714 state = le32_to_cpu(dpriv->iqrx[cur]);
1da177e4
LT		 1715 if (!state)
1716 return;
1717 dpriv->iqrx[cur] = 0;
1718 dpriv->iqrx_current++;
1719
1720 if (state_check(state, dpriv, dev, "Rx") < 0)
1721 return;
1722
1723 if (!(state & SccEvt)){
1724 struct RxFD *rx_fd;
1725
1726 if (debug > 4)
1727 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1728 state);
1729 state &= 0x00ffffff;
1730 if (state & Err) { /* Hold or reset */
1731 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1732 cur = dpriv->rx_current%RX_RING_SIZE;
1733 rx_fd = dpriv->rx_fd + cur;
1734 /*
1735 * Presume we're not facing a DMAC receiver reset.
1736 * As We use the rx size-filtering feature of the
1737 * DSCC4, the beginning of a new frame is waiting in
1738 * the rx fifo. I bet a Receive Data Overflow will
1739 * happen most of time but let's try and avoid it.
1740 * Btw (as for RDO) if one experiences ERR whereas
1741 * the system looks rather idle, there may be a
1742 * problem with latency. In this case, increasing
1743 * RX_RING_SIZE may help.
1744 */
1745 //while (dpriv->rx_needs_refill) {
1746 while (!(rx_fd->state1 & Hold)) {
1747 rx_fd++;
1748 cur++;
1749 if (!(cur = cur%RX_RING_SIZE))
1750 rx_fd = dpriv->rx_fd;
1751 }
1752 //dpriv->rx_needs_refill--;
1753 try_get_rx_skb(dpriv, dev);
1754 if (!rx_fd->data)
1755 goto try;
1756 rx_fd->state1 &= ~Hold;
1757 rx_fd->state2 = 0x00000000;
409cd63e 1758 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1759 //}
1760 goto try;
1761 }
1762 if (state & Fi) {
1763 dscc4_rx_skb(dpriv, dev);
1764 goto try;
1765 }
1766 if (state & Hi ) { /* HI bit */
1767 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1768 state &= ~Hi;
1769 goto try;
1770 }
1771 } else { /* SccEvt */
1772 if (debug > 1) {
1773 //FIXME: verifier la presence de tous les evenements
1774 static struct {
1775 u32 mask;
1776 const char *irq_name;
1777 } evts[] = {
1778 { 0x00008000, "TIN"},
1779 { 0x00000020, "RSC"},
1780 { 0x00000010, "PCE"},
1781 { 0x00000008, "PLLA"},
1782 { 0, NULL}
1783 }, *evt;
1784
1785 for (evt = evts; evt->irq_name; evt++) {
1786 if (state & evt->mask) {
1787 printk(KERN_DEBUG "%s: %s\n",
1788 dev->name, evt->irq_name);
1789 if (!(state &= ~evt->mask))
1790 goto try;
1791 }
1792 }
1793 } else {
1794 if (!(state &= ~0x0000c03c))
1795 goto try;
1796 }
1797 if (state & Cts) {
1798 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1799 if (!(state &= ~Cts)) /* DEBUG */
1800 goto try;
1801 }
1802 /*
1803 * Receive Data Overflow (FIXME: fscked)
1804 */
1805 if (state & Rdo) {
1806 struct RxFD *rx_fd;
1807 void __iomem *scc_addr;
1808 int cur;
1809
1810 //if (debug)
1811 // dscc4_rx_dump(dpriv);
1812 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1813
1814 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1815 /*
1816 * This has no effect. Why ?
1817 * ORed with TxSccRes, one sees the CFG ack (for
1818 * the TX part only).
1819 */
1820 scc_writel(RxSccRes, dpriv, dev, CMDR);
1821 dpriv->flags |= RdoSet;
1822
1823 /*
1824 * Let's try and save something in the received data.
1825 * rx_current must be incremented at least once to
1826 * avoid HOLD in the BRDA-to-be-pointed desc.
1827 */
1828 do {
1829 cur = dpriv->rx_current++%RX_RING_SIZE;
1830 rx_fd = dpriv->rx_fd + cur;
1831 if (!(rx_fd->state2 & DataComplete))
1832 break;
1833 if (rx_fd->state2 & FrameAborted) {
198191c4 1834 dev->stats.rx_over_errors++;
1da177e4
LT		 1835 rx_fd->state1 |= Hold;
1836 rx_fd->state2 = 0x00000000;
409cd63e 1837 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1838 } else
1839 dscc4_rx_skb(dpriv, dev);
1840 } while (1);
1841
1842 if (debug > 0) {
1843 if (dpriv->flags & RdoSet)
1844 printk(KERN_DEBUG
1845 "%s: no RDO in Rx data\n", DRV_NAME);
1846 }
1847#ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1848 /*
1849 * FIXME: must the reset be this violent ?
1850 */
1851#warning "FIXME: CH0BRDA"
1852 writel(dpriv->rx_fd_dma +
1853 (dpriv->rx_current%RX_RING_SIZE)*
1854 sizeof(struct RxFD), scc_addr + CH0BRDA);
1855 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1856 if (dscc4_do_action(dev, "RDR") < 0) {
1857 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1858 dev->name, "RDR");
1859 goto rdo_end;
1860 }
1861 writel(MTFi|Idr, scc_addr + CH0CFG);
1862 if (dscc4_do_action(dev, "IDR") < 0) {
1863 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1864 dev->name, "IDR");
1865 goto rdo_end;
1866 }
1867 rdo_end:
1868#endif
1869 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1870 goto try;
1871 }
1872 if (state & Cd) {
1873 printk(KERN_INFO "%s: CD transition\n", dev->name);
1874 if (!(state &= ~Cd)) /* DEBUG */
1875 goto try;
1876 }
1877 if (state & Flex) {
1878 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1879 if (!(state &= ~Flex))
1880 goto try;
1881 }
1882 }
1883}
1884
1885/*
1886 * I had expected the following to work for the first descriptor
1887 * (tx_fd->state = 0xc0000000)
1888 * - Hold=1 (don't try and branch to the next descripto);
1889 * - No=0 (I want an empty data section, i.e. size=0);
1890 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1891 * It failed and locked solid. Thus the introduction of a dummy skb.
1892 * Problem is acknowledged in errata sheet DS5. Joy :o/
1893 */
7665a089 1894static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1da177e4
LT		 1895{
1896 struct sk_buff *skb;
1897
1898 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1899 if (skb) {
1900 int last = dpriv->tx_dirty%TX_RING_SIZE;
1901 struct TxFD *tx_fd = dpriv->tx_fd + last;
1902
1903 skb->len = DUMMY_SKB_SIZE;
27d7ff46
ACM		 1904 skb_copy_to_linear_data(skb, version,
1905 strlen(version) % DUMMY_SKB_SIZE);
1da177e4 1906 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
409cd63e
AV		 1907 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1908 skb->data, DUMMY_SKB_SIZE,
1909 PCI_DMA_TODEVICE));
1da177e4
LT		 1910 dpriv->tx_skbuff[last] = skb;
1911 }
1912 return skb;
1913}
1914
1915static int dscc4_init_ring(struct net_device *dev)
1916{
1917 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1918 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1919 struct TxFD *tx_fd;
1920 struct RxFD *rx_fd;
1921 void *ring;
1922 int i;
1923
1924 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1925 if (!ring)
1926 goto err_out;
1927 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1928
1929 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1930 if (!ring)
1931 goto err_free_dma_rx;
1932 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1933
1934 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1935 dpriv->tx_dirty = 0xffffffff;
1936 i = dpriv->tx_current = 0;
1937 do {
1938 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1939 tx_fd->complete = 0x00000000;
1940 /* FIXME: NULL should be ok - to be tried */
409cd63e
AV		 1941 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1942 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1da177e4
LT		 1943 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1944 } while (i < TX_RING_SIZE);
1945
3e710bfa 1946 if (!dscc4_init_dummy_skb(dpriv))
1da177e4
LT		 1947 goto err_free_dma_tx;
1948
1949 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1950 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1951 do {
1952 /* size set by the host. Multiple of 4 bytes please */
1953 rx_fd->state1 = HiDesc;
1954 rx_fd->state2 = 0x00000000;
409cd63e 1955 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1956 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1957 // FIXME: return value verifiee mais traitement suspect
1958 if (try_get_rx_skb(dpriv, dev) >= 0)
1959 dpriv->rx_dirty++;
409cd63e 1960 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1da177e4
LT		 1961 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1962 } while (i < RX_RING_SIZE);
1963
1964 return 0;
1965
1966err_free_dma_tx:
1967 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1968err_free_dma_rx:
1969 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1970err_out:
1971 return -ENOMEM;
1972}
1973
1974static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1975{
1976 struct dscc4_pci_priv *ppriv;
1977 struct dscc4_dev_priv *root;
1978 void __iomem *ioaddr;
1979 int i;
1980
1981 ppriv = pci_get_drvdata(pdev);
1982 root = ppriv->root;
1983
1984 ioaddr = root->base_addr;
1985
1986 dscc4_pci_reset(pdev, ioaddr);
1987
1988 free_irq(pdev->irq, root);
1989 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1990 ppriv->iqcfg_dma);
1991 for (i = 0; i < dev_per_card; i++) {
1992 struct dscc4_dev_priv *dpriv = root + i;
1993
1994 dscc4_release_ring(dpriv);
1995 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1996 dpriv->iqrx, dpriv->iqrx_dma);
1997 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1998 dpriv->iqtx, dpriv->iqtx_dma);
1999 }
2000
2001 dscc4_free1(pdev);
2002
2003 iounmap(ioaddr);
2004
2005 pci_release_region(pdev, 1);
2006 pci_release_region(pdev, 0);
2007
2008 pci_disable_device(pdev);
2009}
2010
2011static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2012 unsigned short parity)
2013{
2014 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2015
2016 if (encoding != ENCODING_NRZ &&
2017 encoding != ENCODING_NRZI &&
2018 encoding != ENCODING_FM_MARK &&
2019 encoding != ENCODING_FM_SPACE &&
2020 encoding != ENCODING_MANCHESTER)
2021 return -EINVAL;
2022
2023 if (parity != PARITY_NONE &&
2024 parity != PARITY_CRC16_PR0_CCITT &&
2025 parity != PARITY_CRC16_PR1_CCITT &&
2026 parity != PARITY_CRC32_PR0_CCITT &&
2027 parity != PARITY_CRC32_PR1_CCITT)
2028 return -EINVAL;
2029
2030 dpriv->encoding = encoding;
2031 dpriv->parity = parity;
2032 return 0;
2033}
2034
2035#ifndef MODULE
2036static int __init dscc4_setup(char *str)
2037{
2038 int *args[] = { &debug, &quartz, NULL }, **p = args;
2039
2040 while (*p && (get_option(&str, *p) == 2))
2041 p++;
2042 return 1;
2043}
2044
2045__setup("dscc4.setup=", dscc4_setup);
2046#endif
2047
2048static struct pci_device_id dscc4_pci_tbl[] = {
2049 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2050 PCI_ANY_ID, PCI_ANY_ID, },
2051 { 0,}
2052};
2053MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2054
2055static struct pci_driver dscc4_driver = {
2056 .name = DRV_NAME,
2057 .id_table = dscc4_pci_tbl,
2058 .probe = dscc4_init_one,
2059 .remove = __devexit_p(dscc4_remove_one),
2060};
2061
2062static int __init dscc4_init_module(void)
2063{
29917620 2064 return pci_register_driver(&dscc4_driver);
1da177e4
LT		 2065}
2066
2067static void __exit dscc4_cleanup_module(void)
2068{
2069 pci_unregister_driver(&dscc4_driver);
2070}
2071
2072module_init(dscc4_init_module);
2073module_exit(dscc4_cleanup_module);
Linux kernel - Deliverables
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