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WAN: dscc4: Fix warning pointing out a bug.
[deliverable/linux.git] / drivers / net / wan / dscc4.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83#include <linux/module.h>
84#include <linux/types.h>
85#include <linux/errno.h>
86#include <linux/list.h>
87#include <linux/ioport.h>
88#include <linux/pci.h>
89#include <linux/kernel.h>
90#include <linux/mm.h>
91
92#include <asm/system.h>
93#include <asm/cache.h>
94#include <asm/byteorder.h>
95#include <asm/uaccess.h>
96#include <asm/io.h>
97#include <asm/irq.h>
98
99#include <linux/init.h>
100#include <linux/string.h>
101
102#include <linux/if_arp.h>
103#include <linux/netdevice.h>
104#include <linux/skbuff.h>
105#include <linux/delay.h>
1da177e4 106#include <linux/hdlc.h>
14cc3e2b 107#include <linux/mutex.h>
1da177e4
LT		 108
109/* Version */
110static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
111static int debug;
112static int quartz;
113
114#ifdef CONFIG_DSCC4_PCI_RST
14cc3e2b 115static DEFINE_MUTEX(dscc4_mutex);
1da177e4
LT		 116static u32 dscc4_pci_config_store[16];
117#endif
118
119#define DRV_NAME "dscc4"
120
121#undef DSCC4_POLLING
122
123/* Module parameters */
124
125MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
126MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
127MODULE_LICENSE("GPL");
128module_param(debug, int, 0);
129MODULE_PARM_DESC(debug,"Enable/disable extra messages");
130module_param(quartz, int, 0);
131MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
132
133/* Structures */
134
135struct thingie {
136 int define;
137 u32 bits;
138};
139
140struct TxFD {
409cd63e
AV		 141 __le32 state;
142 __le32 next;
143 __le32 data;
144 __le32 complete;
1da177e4 145 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
409cd63e
AV		 146 /* FWIW, datasheet calls that "dummy" and says that card
147 * never looks at it; neither does the driver */
1da177e4
LT		 148};
149
150struct RxFD {
409cd63e
AV		 151 __le32 state1;
152 __le32 next;
153 __le32 data;
154 __le32 state2;
155 __le32 end;
1da177e4
LT		 156};
157
158#define DUMMY_SKB_SIZE 64
159#define TX_LOW 8
160#define TX_RING_SIZE 32
161#define RX_RING_SIZE 32
162#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
163#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
164#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
165#define TX_TIMEOUT (HZ/10)
166#define DSCC4_HZ_MAX 33000000
167#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
168#define dev_per_card 4
169#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
170
171#define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
172#define TO_SIZE(state) (((state) >> 16) & 0x1fff)
173
174/*
175 * Given the operating range of Linux HDLC, the 2 defines below could be
176 * made simpler. However they are a fine reminder for the limitations of
177 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
178 */
179#define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
180#define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
181#define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
182#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
183
184struct dscc4_pci_priv {
409cd63e 185 __le32 *iqcfg;
1da177e4
LT		 186 int cfg_cur;
187 spinlock_t lock;
188 struct pci_dev *pdev;
189
190 struct dscc4_dev_priv *root;
191 dma_addr_t iqcfg_dma;
192 u32 xtal_hz;
193};
194
195struct dscc4_dev_priv {
196 struct sk_buff *rx_skbuff[RX_RING_SIZE];
197 struct sk_buff *tx_skbuff[TX_RING_SIZE];
198
199 struct RxFD *rx_fd;
200 struct TxFD *tx_fd;
409cd63e
AV		 201 __le32 *iqrx;
202 __le32 *iqtx;
1da177e4
LT		 203
204 /* FIXME: check all the volatile are required */
205 volatile u32 tx_current;
206 u32 rx_current;
207 u32 iqtx_current;
208 u32 iqrx_current;
209
210 volatile u32 tx_dirty;
211 volatile u32 ltda;
212 u32 rx_dirty;
213 u32 lrda;
214
215 dma_addr_t tx_fd_dma;
216 dma_addr_t rx_fd_dma;
217 dma_addr_t iqtx_dma;
218 dma_addr_t iqrx_dma;
219
220 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
221
222 struct timer_list timer;
223
224 struct dscc4_pci_priv *pci_priv;
225 spinlock_t lock;
226
227 int dev_id;
228 volatile u32 flags;
229 u32 timer_help;
230
231 unsigned short encoding;
232 unsigned short parity;
233 struct net_device *dev;
234 sync_serial_settings settings;
235 void __iomem *base_addr;
236 u32 __pad __attribute__ ((aligned (4)));
237};
238
239/* GLOBAL registers definitions */
240#define GCMDR 0x00
241#define GSTAR 0x04
242#define GMODE 0x08
243#define IQLENR0 0x0C
244#define IQLENR1 0x10
245#define IQRX0 0x14
246#define IQTX0 0x24
247#define IQCFG 0x3c
248#define FIFOCR1 0x44
249#define FIFOCR2 0x48
250#define FIFOCR3 0x4c
251#define FIFOCR4 0x34
252#define CH0CFG 0x50
253#define CH0BRDA 0x54
254#define CH0BTDA 0x58
255#define CH0FRDA 0x98
256#define CH0FTDA 0xb0
257#define CH0LRDA 0xc8
258#define CH0LTDA 0xe0
259
260/* SCC registers definitions */
261#define SCC_START 0x0100
262#define SCC_OFFSET 0x80
263#define CMDR 0x00
264#define STAR 0x04
265#define CCR0 0x08
266#define CCR1 0x0c
267#define CCR2 0x10
268#define BRR 0x2C
269#define RLCR 0x40
270#define IMR 0x54
271#define ISR 0x58
272
273#define GPDIR 0x0400
274#define GPDATA 0x0404
275#define GPIM 0x0408
276
277/* Bit masks */
278#define EncodingMask 0x00700000
279#define CrcMask 0x00000003
280
281#define IntRxScc0 0x10000000
282#define IntTxScc0 0x01000000
283
284#define TxPollCmd 0x00000400
285#define RxActivate 0x08000000
286#define MTFi 0x04000000
287#define Rdr 0x00400000
288#define Rdt 0x00200000
289#define Idr 0x00100000
290#define Idt 0x00080000
291#define TxSccRes 0x01000000
292#define RxSccRes 0x00010000
293#define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
294#define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
295
296#define Ccr0ClockMask 0x0000003f
297#define Ccr1LoopMask 0x00000200
298#define IsrMask 0x000fffff
299#define BrrExpMask 0x00000f00
300#define BrrMultMask 0x0000003f
301#define EncodingMask 0x00700000
409cd63e 302#define Hold cpu_to_le32(0x40000000)
1da177e4
LT		 303#define SccBusy 0x10000000
304#define PowerUp 0x80000000
305#define Vis 0x00001000
306#define FrameOk (FrameVfr | FrameCrc)
307#define FrameVfr 0x80
308#define FrameRdo 0x40
309#define FrameCrc 0x20
310#define FrameRab 0x10
409cd63e
AV		 311#define FrameAborted cpu_to_le32(0x00000200)
312#define FrameEnd cpu_to_le32(0x80000000)
313#define DataComplete cpu_to_le32(0x40000000)
1da177e4
LT		 314#define LengthCheck 0x00008000
315#define SccEvt 0x02000000
316#define NoAck 0x00000200
317#define Action 0x00000001
409cd63e 318#define HiDesc cpu_to_le32(0x20000000)
1da177e4
LT		 319
320/* SCC events */
321#define RxEvt 0xf0000000
322#define TxEvt 0x0f000000
323#define Alls 0x00040000
324#define Xdu 0x00010000
325#define Cts 0x00004000
326#define Xmr 0x00002000
327#define Xpr 0x00001000
328#define Rdo 0x00000080
329#define Rfs 0x00000040
330#define Cd 0x00000004
331#define Rfo 0x00000002
332#define Flex 0x00000001
333
334/* DMA core events */
335#define Cfg 0x00200000
336#define Hi 0x00040000
337#define Fi 0x00020000
338#define Err 0x00010000
339#define Arf 0x00000002
340#define ArAck 0x00000001
341
342/* State flags */
343#define Ready 0x00000000
344#define NeedIDR 0x00000001
345#define NeedIDT 0x00000002
346#define RdoSet 0x00000004
347#define FakeReset 0x00000008
348
349/* Don't mask RDO. Ever. */
350#ifdef DSCC4_POLLING
351#define EventsMask 0xfffeef7f
352#else
353#define EventsMask 0xfffa8f7a
354#endif
355
356/* Functions prototypes */
357static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
358static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
359static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
360static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
361static int dscc4_open(struct net_device *);
d71a6749
SH		 362static netdev_tx_t dscc4_start_xmit(struct sk_buff *,
363 struct net_device *);
1da177e4
LT		 364static int dscc4_close(struct net_device *);
365static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
366static int dscc4_init_ring(struct net_device *);
367static void dscc4_release_ring(struct dscc4_dev_priv *);
368static void dscc4_timer(unsigned long);
369static void dscc4_tx_timeout(struct net_device *);
7d12e780 370static irqreturn_t dscc4_irq(int irq, void *dev_id);
1da177e4
LT		 371static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
372static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
373#ifdef DSCC4_POLLING
374static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
375#endif
376
377static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
378{
379 return dev_to_hdlc(dev)->priv;
380}
381
382static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
383{
384 return p->dev;
385}
386
387static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
388 struct net_device *dev, int offset)
389{
390 u32 state;
391
392 /* Cf scc_writel for concern regarding thread-safety */
393 state = dpriv->scc_regs[offset >> 2];
394 state &= ~mask;
395 state |= value;
396 dpriv->scc_regs[offset >> 2] = state;
397 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
398}
399
400static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
401 struct net_device *dev, int offset)
402{
403 /*
404 * Thread-UNsafe.
405 * As of 2002/02/16, there are no thread racing for access.
406 */
407 dpriv->scc_regs[offset >> 2] = bits;
408 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
409}
410
411static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
412{
413 return dpriv->scc_regs[offset >> 2];
414}
415
416static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
417{
418 /* Cf errata DS5 p.4 */
419 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
420 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
421}
422
423static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
424 struct net_device *dev)
425{
426 dpriv->ltda = dpriv->tx_fd_dma +
427 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
428 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
429 /* Flush posted writes *NOW* */
430 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
431}
432
433static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
434 struct net_device *dev)
435{
436 dpriv->lrda = dpriv->rx_fd_dma +
437 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
438 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
439}
440
441static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
442{
443 return dpriv->tx_current == dpriv->tx_dirty;
444}
445
446static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
447 struct net_device *dev)
448{
449 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
450}
451
7665a089
AB		 452static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
453 struct net_device *dev, const char *msg)
1da177e4
LT		 454{
455 int ret = 0;
456
457 if (debug > 1) {
458 if (SOURCE_ID(state) != dpriv->dev_id) {
459 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
460 dev->name, msg, SOURCE_ID(state), state );
461 ret = -1;
462 }
463 if (state & 0x0df80c00) {
464 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
465 dev->name, msg, state);
466 ret = -1;
467 }
468 }
469 return ret;
470}
471
7665a089
AB		 472static void dscc4_tx_print(struct net_device *dev,
473 struct dscc4_dev_priv *dpriv,
474 char *msg)
1da177e4
LT		 475{
476 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
477 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
478}
479
480static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
481{
482 struct pci_dev *pdev = dpriv->pci_priv->pdev;
483 struct TxFD *tx_fd = dpriv->tx_fd;
484 struct RxFD *rx_fd = dpriv->rx_fd;
485 struct sk_buff **skbuff;
486 int i;
487
488 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
489 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
490
491 skbuff = dpriv->tx_skbuff;
492 for (i = 0; i < TX_RING_SIZE; i++) {
493 if (*skbuff) {
409cd63e
AV		 494 pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
495 (*skbuff)->len, PCI_DMA_TODEVICE);
1da177e4
LT		 496 dev_kfree_skb(*skbuff);
497 }
498 skbuff++;
499 tx_fd++;
500 }
501
502 skbuff = dpriv->rx_skbuff;
503 for (i = 0; i < RX_RING_SIZE; i++) {
504 if (*skbuff) {
409cd63e 505 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
1da177e4
LT		 506 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
507 dev_kfree_skb(*skbuff);
508 }
509 skbuff++;
510 rx_fd++;
511 }
512}
513
7665a089
AB		 514static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
515 struct net_device *dev)
1da177e4
LT		 516{
517 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
518 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
519 const int len = RX_MAX(HDLC_MAX_MRU);
520 struct sk_buff *skb;
521 int ret = 0;
522
523 skb = dev_alloc_skb(len);
524 dpriv->rx_skbuff[dirty] = skb;
525 if (skb) {
526 skb->protocol = hdlc_type_trans(skb, dev);
409cd63e
AV		 527 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
528 skb->data, len, PCI_DMA_FROMDEVICE));
1da177e4 529 } else {
409cd63e 530 rx_fd->data = 0;
1da177e4
LT		 531 ret = -1;
532 }
533 return ret;
534}
535
536/*
537 * IRQ/thread/whatever safe
538 */
539static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
540 struct net_device *dev, char *msg)
541{
542 s8 i = 0;
543
544 do {
545 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
546 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
547 msg, i);
548 goto done;
549 }
3173c890 550 schedule_timeout_uninterruptible(10);
1da177e4
LT		 551 rmb();
552 } while (++i > 0);
553 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
554done:
555 return (i >= 0) ? i : -EAGAIN;
556}
557
558static int dscc4_do_action(struct net_device *dev, char *msg)
559{
560 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
561 s16 i = 0;
562
563 writel(Action, ioaddr + GCMDR);
564 ioaddr += GSTAR;
565 do {
566 u32 state = readl(ioaddr);
567
568 if (state & ArAck) {
569 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
570 writel(ArAck, ioaddr);
571 goto done;
572 } else if (state & Arf) {
573 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
574 writel(Arf, ioaddr);
575 i = -1;
576 goto done;
577 }
578 rmb();
579 } while (++i > 0);
580 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
581done:
582 return i;
583}
584
585static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
586{
587 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
588 s8 i = 0;
589
590 do {
591 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
409cd63e 592 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
1da177e4
LT		 593 break;
594 smp_rmb();
3173c890 595 schedule_timeout_uninterruptible(10);
1da177e4
LT		 596 } while (++i > 0);
597
598 return (i >= 0 ) ? i : -EAGAIN;
599}
600
601#if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
602static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
603{
604 unsigned long flags;
605
606 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
607 /* Cf errata DS5 p.6 */
608 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
609 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
610 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
611 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
612 writel(Action, dpriv->base_addr + GCMDR);
613 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
614}
615
616#endif
617
618#if 0
619static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
620{
621 u16 i = 0;
622
623 /* Cf errata DS5 p.7 */
624 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
625 scc_writel(0x00050000, dpriv, dev, CCR2);
626 /*
627 * Must be longer than the time required to fill the fifo.
628 */
629 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
630 udelay(1);
631 wmb();
632 }
633
634 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
635 if (dscc4_do_action(dev, "Rdt") < 0)
636 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
637}
638#endif
639
640/* TODO: (ab)use this function to refill a completely depleted RX ring. */
641static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
642 struct net_device *dev)
643{
644 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
1da177e4
LT		 645 struct pci_dev *pdev = dpriv->pci_priv->pdev;
646 struct sk_buff *skb;
647 int pkt_len;
648
649 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
650 if (!skb) {
b39d66a8 651 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
1da177e4
LT		 652 goto refill;
653 }
409cd63e
AV		 654 pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
655 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
656 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
1da177e4 657 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
198191c4
KH		 658 dev->stats.rx_packets++;
659 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 660 skb_put(skb, pkt_len);
661 if (netif_running(dev))
662 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4
LT		 663 netif_rx(skb);
664 } else {
665 if (skb->data[pkt_len] & FrameRdo)
198191c4 666 dev->stats.rx_fifo_errors++;
5de3fcab 667 else if (!(skb->data[pkt_len] & FrameCrc))
198191c4 668 dev->stats.rx_crc_errors++;
5de3fcab 669 else if ((skb->data[pkt_len] & (FrameVfr | FrameRab)) !=
fab4e763 670 (FrameVfr | FrameRab))
198191c4 671 dev->stats.rx_length_errors++;
5de3fcab 672 dev->stats.rx_errors++;
1da177e4
LT		 673 dev_kfree_skb_irq(skb);
674 }
675refill:
676 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
677 if (try_get_rx_skb(dpriv, dev) < 0)
678 break;
679 dpriv->rx_dirty++;
680 }
681 dscc4_rx_update(dpriv, dev);
682 rx_fd->state2 = 0x00000000;
409cd63e 683 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 684}
685
686static void dscc4_free1(struct pci_dev *pdev)
687{
688 struct dscc4_pci_priv *ppriv;
689 struct dscc4_dev_priv *root;
690 int i;
691
692 ppriv = pci_get_drvdata(pdev);
693 root = ppriv->root;
694
695 for (i = 0; i < dev_per_card; i++)
696 unregister_hdlc_device(dscc4_to_dev(root + i));
697
698 pci_set_drvdata(pdev, NULL);
699
700 for (i = 0; i < dev_per_card; i++)
701 free_netdev(root[i].dev);
702 kfree(root);
703 kfree(ppriv);
704}
705
706static int __devinit dscc4_init_one(struct pci_dev *pdev,
707 const struct pci_device_id *ent)
708{
709 struct dscc4_pci_priv *priv;
710 struct dscc4_dev_priv *dpriv;
711 void __iomem *ioaddr;
712 int i, rc;
713
714 printk(KERN_DEBUG "%s", version);
715
716 rc = pci_enable_device(pdev);
717 if (rc < 0)
718 goto out;
719
720 rc = pci_request_region(pdev, 0, "registers");
721 if (rc < 0) {
722 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
723 DRV_NAME);
724 goto err_disable_0;
725 }
726 rc = pci_request_region(pdev, 1, "LBI interface");
727 if (rc < 0) {
728 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
729 DRV_NAME);
730 goto err_free_mmio_region_1;
731 }
732
275f165f 733 ioaddr = pci_ioremap_bar(pdev, 0);
1da177e4 734 if (!ioaddr) {
7c7459d1
GKH		 735 printk(KERN_ERR "%s: cannot remap MMIO region %llx @ %llx\n",
736 DRV_NAME, (unsigned long long)pci_resource_len(pdev, 0),
737 (unsigned long long)pci_resource_start(pdev, 0));
1da177e4
LT		 738 rc = -EIO;
739 goto err_free_mmio_regions_2;
740 }
7c7459d1
GKH		 741 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
742 (unsigned long long)pci_resource_start(pdev, 0),
743 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
1da177e4
LT		 744
745 /* Cf errata DS5 p.2 */
746 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
747 pci_set_master(pdev);
748
749 rc = dscc4_found1(pdev, ioaddr);
750 if (rc < 0)
751 goto err_iounmap_3;
752
753 priv = pci_get_drvdata(pdev);
754
1fb9df5d 755 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
1da177e4
LT		 756 if (rc < 0) {
757 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
758 goto err_release_4;
759 }
760
761 /* power up/little endian/dma core controlled via lrda/ltda */
762 writel(0x00000001, ioaddr + GMODE);
763 /* Shared interrupt queue */
764 {
765 u32 bits;
766
767 bits = (IRQ_RING_SIZE >> 5) - 1;
768 bits |= bits << 4;
769 bits |= bits << 8;
770 bits |= bits << 16;
771 writel(bits, ioaddr + IQLENR0);
772 }
773 /* Global interrupt queue */
774 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
409cd63e
AV		 775 priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
776 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
1da177e4
LT		 777 if (!priv->iqcfg)
778 goto err_free_irq_5;
779 writel(priv->iqcfg_dma, ioaddr + IQCFG);
780
781 rc = -ENOMEM;
782
783 /*
784 * SCC 0-3 private rx/tx irq structures
785 * IQRX/TXi needs to be set soon. Learned it the hard way...
786 */
787 for (i = 0; i < dev_per_card; i++) {
788 dpriv = priv->root + i;
409cd63e 789 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
1da177e4
LT		 790 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
791 if (!dpriv->iqtx)
792 goto err_free_iqtx_6;
793 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
794 }
795 for (i = 0; i < dev_per_card; i++) {
796 dpriv = priv->root + i;
409cd63e 797 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
1da177e4
LT		 798 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
799 if (!dpriv->iqrx)
800 goto err_free_iqrx_7;
801 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
802 }
803
804 /* Cf application hint. Beware of hard-lock condition on threshold. */
805 writel(0x42104000, ioaddr + FIFOCR1);
806 //writel(0x9ce69800, ioaddr + FIFOCR2);
807 writel(0xdef6d800, ioaddr + FIFOCR2);
808 //writel(0x11111111, ioaddr + FIFOCR4);
809 writel(0x18181818, ioaddr + FIFOCR4);
810 // FIXME: should depend on the chipset revision
811 writel(0x0000000e, ioaddr + FIFOCR3);
812
813 writel(0xff200001, ioaddr + GCMDR);
814
815 rc = 0;
816out:
817 return rc;
818
819err_free_iqrx_7:
820 while (--i >= 0) {
821 dpriv = priv->root + i;
822 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
823 dpriv->iqrx, dpriv->iqrx_dma);
824 }
825 i = dev_per_card;
826err_free_iqtx_6:
827 while (--i >= 0) {
828 dpriv = priv->root + i;
829 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
830 dpriv->iqtx, dpriv->iqtx_dma);
831 }
832 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
833 priv->iqcfg_dma);
834err_free_irq_5:
835 free_irq(pdev->irq, priv->root);
836err_release_4:
837 dscc4_free1(pdev);
838err_iounmap_3:
839 iounmap (ioaddr);
840err_free_mmio_regions_2:
841 pci_release_region(pdev, 1);
842err_free_mmio_region_1:
843 pci_release_region(pdev, 0);
844err_disable_0:
845 pci_disable_device(pdev);
846 goto out;
847};
848
849/*
850 * Let's hope the default values are decent enough to protect my
851 * feet from the user's gun - Ueimor
852 */
853static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
854 struct net_device *dev)
855{
856 /* No interrupts, SCC core disabled. Let's relax */
857 scc_writel(0x00000000, dpriv, dev, CCR0);
858
859 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
860
861 /*
862 * No address recognition/crc-CCITT/cts enabled
863 * Shared flags transmission disabled - cf errata DS5 p.11
864 * Carrier detect disabled - cf errata p.14
865 * FIXME: carrier detection/polarity may be handled more gracefully.
866 */
867 scc_writel(0x02408000, dpriv, dev, CCR1);
868
869 /* crc not forwarded - Cf errata DS5 p.11 */
870 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
871 // crc forwarded
872 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
873}
874
875static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
876{
877 int ret = 0;
878
879 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
880 ret = -EOPNOTSUPP;
881 else
882 dpriv->pci_priv->xtal_hz = hz;
883
884 return ret;
885}
886
991990a1
KH		 887static const struct net_device_ops dscc4_ops = {
888 .ndo_open = dscc4_open,
889 .ndo_stop = dscc4_close,
890 .ndo_change_mtu = hdlc_change_mtu,
891 .ndo_start_xmit = hdlc_start_xmit,
892 .ndo_do_ioctl = dscc4_ioctl,
893 .ndo_tx_timeout = dscc4_tx_timeout,
894};
895
1da177e4
LT		 896static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
897{
898 struct dscc4_pci_priv *ppriv;
899 struct dscc4_dev_priv *root;
900 int i, ret = -ENOMEM;
901
dd00cc48 902 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
1da177e4
LT		 903 if (!root) {
904 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
905 goto err_out;
906 }
1da177e4
LT		 907
908 for (i = 0; i < dev_per_card; i++) {
909 root[i].dev = alloc_hdlcdev(root + i);
910 if (!root[i].dev)
911 goto err_free_dev;
912 }
913
dd00cc48 914 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
1da177e4
LT		 915 if (!ppriv) {
916 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
917 goto err_free_dev;
918 }
1da177e4
LT		 919
920 ppriv->root = root;
921 spin_lock_init(&ppriv->lock);
922
923 for (i = 0; i < dev_per_card; i++) {
924 struct dscc4_dev_priv *dpriv = root + i;
925 struct net_device *d = dscc4_to_dev(dpriv);
926 hdlc_device *hdlc = dev_to_hdlc(d);
927
928 d->base_addr = (unsigned long)ioaddr;
1da177e4 929 d->irq = pdev->irq;
991990a1 930 d->netdev_ops = &dscc4_ops;
1da177e4 931 d->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 932 SET_NETDEV_DEV(d, &pdev->dev);
933
934 dpriv->dev_id = i;
935 dpriv->pci_priv = ppriv;
936 dpriv->base_addr = ioaddr;
937 spin_lock_init(&dpriv->lock);
938
939 hdlc->xmit = dscc4_start_xmit;
940 hdlc->attach = dscc4_hdlc_attach;
941
942 dscc4_init_registers(dpriv, d);
943 dpriv->parity = PARITY_CRC16_PR0_CCITT;
944 dpriv->encoding = ENCODING_NRZ;
945
946 ret = dscc4_init_ring(d);
947 if (ret < 0)
948 goto err_unregister;
949
950 ret = register_hdlc_device(d);
951 if (ret < 0) {
952 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
953 dscc4_release_ring(dpriv);
954 goto err_unregister;
955 }
956 }
957
958 ret = dscc4_set_quartz(root, quartz);
959 if (ret < 0)
960 goto err_unregister;
961
962 pci_set_drvdata(pdev, ppriv);
963 return ret;
964
965err_unregister:
966 while (i-- > 0) {
967 dscc4_release_ring(root + i);
968 unregister_hdlc_device(dscc4_to_dev(root + i));
969 }
970 kfree(ppriv);
971 i = dev_per_card;
972err_free_dev:
973 while (i-- > 0)
974 free_netdev(root[i].dev);
975 kfree(root);
976err_out:
977 return ret;
978};
979
980/* FIXME: get rid of the unneeded code */
981static void dscc4_timer(unsigned long data)
982{
983 struct net_device *dev = (struct net_device *)data;
984 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
985// struct dscc4_pci_priv *ppriv;
986
987 goto done;
988done:
989 dpriv->timer.expires = jiffies + TX_TIMEOUT;
990 add_timer(&dpriv->timer);
991}
992
993static void dscc4_tx_timeout(struct net_device *dev)
994{
995 /* FIXME: something is missing there */
996}
997
998static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
999{
1000 sync_serial_settings *settings = &dpriv->settings;
1001
1002 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
1003 struct net_device *dev = dscc4_to_dev(dpriv);
1004
1005 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
1006 return -1;
1007 }
1008 return 0;
1009}
1010
1011#ifdef CONFIG_DSCC4_PCI_RST
1012/*
1013 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1014 * so as to provide a safe way to reset the asic while not the whole machine
1015 * rebooting.
1016 *
1017 * This code doesn't need to be efficient. Keep It Simple
1018 */
1019static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1020{
1021 int i;
1022
14cc3e2b 1023 mutex_lock(&dscc4_mutex);
1da177e4
LT		 1024 for (i = 0; i < 16; i++)
1025 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1026
1027 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1028 writel(0x001c0000, ioaddr + GMODE);
1029 /* Configure GPIO port as output */
1030 writel(0x0000ffff, ioaddr + GPDIR);
1031 /* Disable interruption */
1032 writel(0x0000ffff, ioaddr + GPIM);
1033
1034 writel(0x0000ffff, ioaddr + GPDATA);
1035 writel(0x00000000, ioaddr + GPDATA);
1036
1037 /* Flush posted writes */
1038 readl(ioaddr + GSTAR);
1039
3173c890 1040 schedule_timeout_uninterruptible(10);
1da177e4
LT		 1041
1042 for (i = 0; i < 16; i++)
1043 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
14cc3e2b 1044 mutex_unlock(&dscc4_mutex);
1da177e4
LT		 1045}
1046#else
1047#define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1048#endif /* CONFIG_DSCC4_PCI_RST */
1049
1050static int dscc4_open(struct net_device *dev)
1051{
1052 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1053 struct dscc4_pci_priv *ppriv;
1054 int ret = -EAGAIN;
1055
991990a1 1056 if ((dscc4_loopback_check(dpriv) < 0))
1da177e4
LT		 1057 goto err;
1058
1059 if ((ret = hdlc_open(dev)))
1060 goto err;
1061
1062 ppriv = dpriv->pci_priv;
1063
1064 /*
1065 * Due to various bugs, there is no way to reliably reset a
1066 * specific port (manufacturer's dependant special PCI #RST wiring
1067 * apart: it affects all ports). Thus the device goes in the best
1068 * silent mode possible at dscc4_close() time and simply claims to
1069 * be up if it's opened again. It still isn't possible to change
1070 * the HDLC configuration without rebooting but at least the ports
1071 * can be up/down ifconfig'ed without killing the host.
1072 */
1073 if (dpriv->flags & FakeReset) {
1074 dpriv->flags &= ~FakeReset;
1075 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1076 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1077 scc_writel(EventsMask, dpriv, dev, IMR);
1078 printk(KERN_INFO "%s: up again.\n", dev->name);
1079 goto done;
1080 }
1081
1082 /* IDT+IDR during XPR */
1083 dpriv->flags = NeedIDR | NeedIDT;
1084
1085 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1086
1087 /*
1088 * The following is a bit paranoid...
1089 *
1090 * NB: the datasheet "...CEC will stay active if the SCC is in
1091 * power-down mode or..." and CCR2.RAC = 1 are two different
1092 * situations.
1093 */
1094 if (scc_readl_star(dpriv, dev) & SccBusy) {
1095 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1096 ret = -EAGAIN;
1097 goto err_out;
1098 } else
1099 printk(KERN_INFO "%s: available. Good\n", dev->name);
1100
1101 scc_writel(EventsMask, dpriv, dev, IMR);
1102
1103 /* Posted write is flushed in the wait_ack loop */
1104 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1105
1106 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1107 goto err_disable_scc_events;
1108
1109 /*
1110 * I would expect XPR near CE completion (before ? after ?).
1111 * At worst, this code won't see a late XPR and people
1112 * will have to re-issue an ifconfig (this is harmless).
1113 * WARNING, a really missing XPR usually means a hardware
1114 * reset is needed. Suggestions anyone ?
1115 */
1116 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1117 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1118 goto err_disable_scc_events;
1119 }
1120
1121 if (debug > 2)
1122 dscc4_tx_print(dev, dpriv, "Open");
1123
1124done:
1125 netif_start_queue(dev);
1126
1127 init_timer(&dpriv->timer);
1128 dpriv->timer.expires = jiffies + 10*HZ;
1129 dpriv->timer.data = (unsigned long)dev;
1130 dpriv->timer.function = &dscc4_timer;
1131 add_timer(&dpriv->timer);
1132 netif_carrier_on(dev);
1133
1134 return 0;
1135
1136err_disable_scc_events:
1137 scc_writel(0xffffffff, dpriv, dev, IMR);
1138 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1139err_out:
1140 hdlc_close(dev);
1141err:
1142 return ret;
1143}
1144
1145#ifdef DSCC4_POLLING
1146static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1147{
1148 /* FIXME: it's gonna be easy (TM), for sure */
1149}
1150#endif /* DSCC4_POLLING */
1151
d71a6749
SH		 1152static netdev_tx_t dscc4_start_xmit(struct sk_buff *skb,
1153 struct net_device *dev)
1da177e4
LT		 1154{
1155 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1156 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1157 struct TxFD *tx_fd;
1158 int next;
1159
1160 next = dpriv->tx_current%TX_RING_SIZE;
1161 dpriv->tx_skbuff[next] = skb;
1162 tx_fd = dpriv->tx_fd + next;
1163 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
409cd63e
AV		 1164 tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1165 PCI_DMA_TODEVICE));
1da177e4
LT		 1166 tx_fd->complete = 0x00000000;
1167 tx_fd->jiffies = jiffies;
1168 mb();
1169
1170#ifdef DSCC4_POLLING
1171 spin_lock(&dpriv->lock);
1172 while (dscc4_tx_poll(dpriv, dev));
1173 spin_unlock(&dpriv->lock);
1174#endif
1175
1176 dev->trans_start = jiffies;
1177
1178 if (debug > 2)
1179 dscc4_tx_print(dev, dpriv, "Xmit");
1180 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1181 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1182 netif_stop_queue(dev);
1183
1184 if (dscc4_tx_quiescent(dpriv, dev))
1185 dscc4_do_tx(dpriv, dev);
1186
ec634fe3 1187 return NETDEV_TX_OK;
1da177e4
LT		 1188}
1189
1190static int dscc4_close(struct net_device *dev)
1191{
1192 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1193
1194 del_timer_sync(&dpriv->timer);
1195 netif_stop_queue(dev);
1196
1197 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1198 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1199 scc_writel(0xffffffff, dpriv, dev, IMR);
1200
1201 dpriv->flags |= FakeReset;
1202
1203 hdlc_close(dev);
1204
1205 return 0;
1206}
1207
1208static inline int dscc4_check_clock_ability(int port)
1209{
1210 int ret = 0;
1211
1212#ifdef CONFIG_DSCC4_PCISYNC
1213 if (port >= 2)
1214 ret = -1;
1215#endif
1216 return ret;
1217}
1218
1219/*
1220 * DS1 p.137: "There are a total of 13 different clocking modes..."
1221 * ^^
1222 * Design choices:
1223 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1224 * Clock mode 3b _should_ work but the testing seems to make this point
1225 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1226 * This is supposed to provide least surprise "DTE like" behavior.
1227 * - if line rate is specified, clocks are assumed to be locally generated.
1228 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1229 * between these it automagically done according on the required frequency
1230 * scaling. Of course some rounding may take place.
1231 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1232 * appropriate external clocking device for testing.
1233 * - no time-slot/clock mode 5: shameless lazyness.
1234 *
1235 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1236 *
1237 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1238 * won't pass the init sequence. For example, straight back-to-back DTE without
1239 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1240 * called.
1241 *
1242 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1243 * DS0 for example)
1244 *
1245 * Clock mode related bits of CCR0:
1246 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1247 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1248 * | | +-------- High Speed: say 0
1249 * | | | +-+-+-- Clock Mode: 0..7
1250 * | | | | | |
1251 * -+-+-+-+-+-+-+-+
1252 * x|x|5|4|3|2|1|0| lower bits
1253 *
1254 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1255 * +-+-+-+------------------ M (0..15)
1256 * | | | | +-+-+-+-+-+-- N (0..63)
1257 * 0 0 0 0 | | | | 0 0 | | | | | |
1258 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1259 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1260 *
1261 */
1262static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1263{
1264 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1265 int ret = -1;
1266 u32 brr;
1267
1268 *state &= ~Ccr0ClockMask;
1269 if (*bps) { /* Clock generated - required for DCE */
1270 u32 n = 0, m = 0, divider;
1271 int xtal;
1272
1273 xtal = dpriv->pci_priv->xtal_hz;
1274 if (!xtal)
1275 goto done;
1276 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1277 goto done;
1278 divider = xtal / *bps;
1279 if (divider > BRR_DIVIDER_MAX) {
1280 divider >>= 4;
1281 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1282 } else
1283 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1284 if (divider >> 22) {
1285 n = 63;
1286 m = 15;
1287 } else if (divider) {
1288 /* Extraction of the 6 highest weighted bits */
1289 m = 0;
1290 while (0xffffffc0 & divider) {
1291 m++;
1292 divider >>= 1;
1293 }
1294 n = divider;
1295 }
1296 brr = (m << 8) | n;
1297 divider = n << m;
1298 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1299 divider <<= 4;
1300 *bps = xtal / divider;
1301 } else {
1302 /*
1303 * External clock - DTE
1304 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1305 * Nothing more to be done
1306 */
1307 brr = 0;
1308 }
1309 scc_writel(brr, dpriv, dev, BRR);
1310 ret = 0;
1311done:
1312 return ret;
1313}
1314
1315static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1316{
1317 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1318 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1319 const size_t size = sizeof(dpriv->settings);
1320 int ret = 0;
1321
1322 if (dev->flags & IFF_UP)
1323 return -EBUSY;
1324
1325 if (cmd != SIOCWANDEV)
1326 return -EOPNOTSUPP;
1327
1328 switch(ifr->ifr_settings.type) {
1329 case IF_GET_IFACE:
1330 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1331 if (ifr->ifr_settings.size < size) {
1332 ifr->ifr_settings.size = size; /* data size wanted */
1333 return -ENOBUFS;
1334 }
1335 if (copy_to_user(line, &dpriv->settings, size))
1336 return -EFAULT;
1337 break;
1338
1339 case IF_IFACE_SYNC_SERIAL:
1340 if (!capable(CAP_NET_ADMIN))
1341 return -EPERM;
1342
1343 if (dpriv->flags & FakeReset) {
1344 printk(KERN_INFO "%s: please reset the device"
1345 " before this command\n", dev->name);
1346 return -EPERM;
1347 }
1348 if (copy_from_user(&dpriv->settings, line, size))
1349 return -EFAULT;
1350 ret = dscc4_set_iface(dpriv, dev);
1351 break;
1352
1353 default:
1354 ret = hdlc_ioctl(dev, ifr, cmd);
1355 break;
1356 }
1357
1358 return ret;
1359}
1360
1361static int dscc4_match(struct thingie *p, int value)
1362{
1363 int i;
1364
1365 for (i = 0; p[i].define != -1; i++) {
1366 if (value == p[i].define)
1367 break;
1368 }
1369 if (p[i].define == -1)
1370 return -1;
1371 else
1372 return i;
1373}
1374
1375static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1376 struct net_device *dev)
1377{
1378 sync_serial_settings *settings = &dpriv->settings;
1379 int ret = -EOPNOTSUPP;
1380 u32 bps, state;
1381
1382 bps = settings->clock_rate;
1383 state = scc_readl(dpriv, CCR0);
1384 if (dscc4_set_clock(dev, &bps, &state) < 0)
1385 goto done;
1386 if (bps) { /* DCE */
1387 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1388 if (settings->clock_rate != bps) {
1389 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1390 dev->name, settings->clock_rate, bps);
1391 settings->clock_rate = bps;
1392 }
1393 } else { /* DTE */
1394 state |= PowerUp | Vis;
1395 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1396 }
1397 scc_writel(state, dpriv, dev, CCR0);
1398 ret = 0;
1399done:
1400 return ret;
1401}
1402
1403static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1404 struct net_device *dev)
1405{
1406 struct thingie encoding[] = {
1407 { ENCODING_NRZ, 0x00000000 },
1408 { ENCODING_NRZI, 0x00200000 },
1409 { ENCODING_FM_MARK, 0x00400000 },
1410 { ENCODING_FM_SPACE, 0x00500000 },
1411 { ENCODING_MANCHESTER, 0x00600000 },
1412 { -1, 0}
1413 };
1414 int i, ret = 0;
1415
1416 i = dscc4_match(encoding, dpriv->encoding);
1417 if (i >= 0)
1418 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1419 else
1420 ret = -EOPNOTSUPP;
1421 return ret;
1422}
1423
1424static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1425 struct net_device *dev)
1426{
1427 sync_serial_settings *settings = &dpriv->settings;
1428 u32 state;
1429
1430 state = scc_readl(dpriv, CCR1);
1431 if (settings->loopback) {
1432 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1433 state |= 0x00000100;
1434 } else {
1435 printk(KERN_DEBUG "%s: normal\n", dev->name);
1436 state &= ~0x00000100;
1437 }
1438 scc_writel(state, dpriv, dev, CCR1);
1439 return 0;
1440}
1441
1442static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1443 struct net_device *dev)
1444{
1445 struct thingie crc[] = {
1446 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1447 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1448 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1449 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1450 };
1451 int i, ret = 0;
1452
1453 i = dscc4_match(crc, dpriv->parity);
1454 if (i >= 0)
1455 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1456 else
1457 ret = -EOPNOTSUPP;
1458 return ret;
1459}
1460
1461static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1462{
1463 struct {
1464 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1465 } *p, do_setting[] = {
1466 { dscc4_encoding_setting },
1467 { dscc4_clock_setting },
1468 { dscc4_loopback_setting },
1469 { dscc4_crc_setting },
1470 { NULL }
1471 };
1472 int ret = 0;
1473
1474 for (p = do_setting; p->action; p++) {
1475 if ((ret = p->action(dpriv, dev)) < 0)
1476 break;
1477 }
1478 return ret;
1479}
1480
7d12e780 1481static irqreturn_t dscc4_irq(int irq, void *token)
1da177e4
LT		 1482{
1483 struct dscc4_dev_priv *root = token;
1484 struct dscc4_pci_priv *priv;
1485 struct net_device *dev;
1486 void __iomem *ioaddr;
1487 u32 state;
1488 unsigned long flags;
1489 int i, handled = 1;
1490
1491 priv = root->pci_priv;
1492 dev = dscc4_to_dev(root);
1493
1494 spin_lock_irqsave(&priv->lock, flags);
1495
1496 ioaddr = root->base_addr;
1497
1498 state = readl(ioaddr + GSTAR);
1499 if (!state) {
1500 handled = 0;
1501 goto out;
1502 }
1503 if (debug > 3)
1504 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1505 writel(state, ioaddr + GSTAR);
1506
1507 if (state & Arf) {
1508 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1509 dev->name);
1510 goto out;
1511 }
1512 state &= ~ArAck;
1513 if (state & Cfg) {
1514 if (debug > 0)
1515 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
409cd63e 1516 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
1da177e4
LT		 1517 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1518 if (!(state &= ~Cfg))
1519 goto out;
1520 }
1521 if (state & RxEvt) {
1522 i = dev_per_card - 1;
1523 do {
1524 dscc4_rx_irq(priv, root + i);
1525 } while (--i >= 0);
1526 state &= ~RxEvt;
1527 }
1528 if (state & TxEvt) {
1529 i = dev_per_card - 1;
1530 do {
1531 dscc4_tx_irq(priv, root + i);
1532 } while (--i >= 0);
1533 state &= ~TxEvt;
1534 }
1535out:
1536 spin_unlock_irqrestore(&priv->lock, flags);
1537 return IRQ_RETVAL(handled);
1538}
1539
1540static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1541 struct dscc4_dev_priv *dpriv)
1542{
1543 struct net_device *dev = dscc4_to_dev(dpriv);
1544 u32 state;
1545 int cur, loop = 0;
1546
1547try:
1548 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
409cd63e 1549 state = le32_to_cpu(dpriv->iqtx[cur]);
1da177e4
LT		 1550 if (!state) {
1551 if (debug > 4)
1552 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1553 state);
1554 if ((debug > 1) && (loop > 1))
1555 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1556 if (loop && netif_queue_stopped(dev))
1557 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1558 netif_wake_queue(dev);
1559
1560 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1561 !dscc4_tx_done(dpriv))
1562 dscc4_do_tx(dpriv, dev);
1563 return;
1564 }
1565 loop++;
1566 dpriv->iqtx[cur] = 0;
1567 dpriv->iqtx_current++;
1568
1569 if (state_check(state, dpriv, dev, "Tx") < 0)
1570 return;
1571
1572 if (state & SccEvt) {
1573 if (state & Alls) {
1da177e4
LT		 1574 struct sk_buff *skb;
1575 struct TxFD *tx_fd;
1576
1577 if (debug > 2)
1578 dscc4_tx_print(dev, dpriv, "Alls");
1579 /*
1580 * DataComplete can't be trusted for Tx completion.
1581 * Cf errata DS5 p.8
1582 */
1583 cur = dpriv->tx_dirty%TX_RING_SIZE;
1584 tx_fd = dpriv->tx_fd + cur;
1585 skb = dpriv->tx_skbuff[cur];
1586 if (skb) {
409cd63e 1587 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1da177e4
LT		 1588 skb->len, PCI_DMA_TODEVICE);
1589 if (tx_fd->state & FrameEnd) {
198191c4
KH		 1590 dev->stats.tx_packets++;
1591 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 1592 }
1593 dev_kfree_skb_irq(skb);
1594 dpriv->tx_skbuff[cur] = NULL;
1595 ++dpriv->tx_dirty;
1596 } else {
1597 if (debug > 1)
1598 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1599 dev->name, cur);
1600 }
1601 /*
1602 * If the driver ends sending crap on the wire, it
1603 * will be way easier to diagnose than the (not so)
1604 * random freeze induced by null sized tx frames.
1605 */
1606 tx_fd->data = tx_fd->next;
1607 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1608 tx_fd->complete = 0x00000000;
1609 tx_fd->jiffies = 0;
1610
1611 if (!(state &= ~Alls))
1612 goto try;
1613 }
1614 /*
1615 * Transmit Data Underrun
1616 */
1617 if (state & Xdu) {
1618 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1619 dpriv->flags = NeedIDT;
1620 /* Tx reset */
1621 writel(MTFi | Rdt,
1622 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1623 writel(Action, dpriv->base_addr + GCMDR);
1624 return;
1625 }
1626 if (state & Cts) {
1627 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1628 if (!(state &= ~Cts)) /* DEBUG */
1629 goto try;
1630 }
1631 if (state & Xmr) {
1632 /* Frame needs to be sent again - FIXME */
1633 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1634 if (!(state &= ~Xmr)) /* DEBUG */
1635 goto try;
1636 }
1637 if (state & Xpr) {
1638 void __iomem *scc_addr;
1639 unsigned long ring;
1640 int i;
1641
1642 /*
1643 * - the busy condition happens (sometimes);
1644 * - it doesn't seem to make the handler unreliable.
1645 */
1646 for (i = 1; i; i <<= 1) {
1647 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1648 break;
1649 }
1650 if (!i)
1651 printk(KERN_INFO "%s busy in irq\n", dev->name);
1652
1653 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1654 /* Keep this order: IDT before IDR */
1655 if (dpriv->flags & NeedIDT) {
1656 if (debug > 2)
1657 dscc4_tx_print(dev, dpriv, "Xpr");
1658 ring = dpriv->tx_fd_dma +
1659 (dpriv->tx_dirty%TX_RING_SIZE)*
1660 sizeof(struct TxFD);
1661 writel(ring, scc_addr + CH0BTDA);
1662 dscc4_do_tx(dpriv, dev);
1663 writel(MTFi | Idt, scc_addr + CH0CFG);
1664 if (dscc4_do_action(dev, "IDT") < 0)
1665 goto err_xpr;
1666 dpriv->flags &= ~NeedIDT;
1667 }
1668 if (dpriv->flags & NeedIDR) {
1669 ring = dpriv->rx_fd_dma +
1670 (dpriv->rx_current%RX_RING_SIZE)*
1671 sizeof(struct RxFD);
1672 writel(ring, scc_addr + CH0BRDA);
1673 dscc4_rx_update(dpriv, dev);
1674 writel(MTFi | Idr, scc_addr + CH0CFG);
1675 if (dscc4_do_action(dev, "IDR") < 0)
1676 goto err_xpr;
1677 dpriv->flags &= ~NeedIDR;
1678 smp_wmb();
1679 /* Activate receiver and misc */
1680 scc_writel(0x08050008, dpriv, dev, CCR2);
1681 }
1682 err_xpr:
1683 if (!(state &= ~Xpr))
1684 goto try;
1685 }
1686 if (state & Cd) {
1687 if (debug > 0)
1688 printk(KERN_INFO "%s: CD transition\n", dev->name);
1689 if (!(state &= ~Cd)) /* DEBUG */
1690 goto try;
1691 }
1692 } else { /* ! SccEvt */
1693 if (state & Hi) {
1694#ifdef DSCC4_POLLING
1695 while (!dscc4_tx_poll(dpriv, dev));
1696#endif
1697 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1698 state &= ~Hi;
1699 }
1700 if (state & Err) {
1701 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
198191c4 1702 dev->stats.tx_errors++;
1da177e4
LT		 1703 state &= ~Err;
1704 }
1705 }
1706 goto try;
1707}
1708
1709static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1710 struct dscc4_dev_priv *dpriv)
1711{
1712 struct net_device *dev = dscc4_to_dev(dpriv);
1713 u32 state;
1714 int cur;
1715
1716try:
1717 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
409cd63e 1718 state = le32_to_cpu(dpriv->iqrx[cur]);
1da177e4
LT		 1719 if (!state)
1720 return;
1721 dpriv->iqrx[cur] = 0;
1722 dpriv->iqrx_current++;
1723
1724 if (state_check(state, dpriv, dev, "Rx") < 0)
1725 return;
1726
1727 if (!(state & SccEvt)){
1728 struct RxFD *rx_fd;
1729
1730 if (debug > 4)
1731 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1732 state);
1733 state &= 0x00ffffff;
1734 if (state & Err) { /* Hold or reset */
1735 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1736 cur = dpriv->rx_current%RX_RING_SIZE;
1737 rx_fd = dpriv->rx_fd + cur;
1738 /*
1739 * Presume we're not facing a DMAC receiver reset.
1740 * As We use the rx size-filtering feature of the
1741 * DSCC4, the beginning of a new frame is waiting in
1742 * the rx fifo. I bet a Receive Data Overflow will
1743 * happen most of time but let's try and avoid it.
1744 * Btw (as for RDO) if one experiences ERR whereas
1745 * the system looks rather idle, there may be a
1746 * problem with latency. In this case, increasing
1747 * RX_RING_SIZE may help.
1748 */
1749 //while (dpriv->rx_needs_refill) {
1750 while (!(rx_fd->state1 & Hold)) {
1751 rx_fd++;
1752 cur++;
1753 if (!(cur = cur%RX_RING_SIZE))
1754 rx_fd = dpriv->rx_fd;
1755 }
1756 //dpriv->rx_needs_refill--;
1757 try_get_rx_skb(dpriv, dev);
1758 if (!rx_fd->data)
1759 goto try;
1760 rx_fd->state1 &= ~Hold;
1761 rx_fd->state2 = 0x00000000;
409cd63e 1762 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1763 //}
1764 goto try;
1765 }
1766 if (state & Fi) {
1767 dscc4_rx_skb(dpriv, dev);
1768 goto try;
1769 }
1770 if (state & Hi ) { /* HI bit */
1771 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1772 state &= ~Hi;
1773 goto try;
1774 }
1775 } else { /* SccEvt */
1776 if (debug > 1) {
1777 //FIXME: verifier la presence de tous les evenements
1778 static struct {
1779 u32 mask;
1780 const char *irq_name;
1781 } evts[] = {
1782 { 0x00008000, "TIN"},
1783 { 0x00000020, "RSC"},
1784 { 0x00000010, "PCE"},
1785 { 0x00000008, "PLLA"},
1786 { 0, NULL}
1787 }, *evt;
1788
1789 for (evt = evts; evt->irq_name; evt++) {
1790 if (state & evt->mask) {
1791 printk(KERN_DEBUG "%s: %s\n",
1792 dev->name, evt->irq_name);
1793 if (!(state &= ~evt->mask))
1794 goto try;
1795 }
1796 }
1797 } else {
1798 if (!(state &= ~0x0000c03c))
1799 goto try;
1800 }
1801 if (state & Cts) {
1802 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1803 if (!(state &= ~Cts)) /* DEBUG */
1804 goto try;
1805 }
1806 /*
1807 * Receive Data Overflow (FIXME: fscked)
1808 */
1809 if (state & Rdo) {
1810 struct RxFD *rx_fd;
1811 void __iomem *scc_addr;
1812 int cur;
1813
1814 //if (debug)
1815 // dscc4_rx_dump(dpriv);
1816 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1817
1818 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1819 /*
1820 * This has no effect. Why ?
1821 * ORed with TxSccRes, one sees the CFG ack (for
1822 * the TX part only).
1823 */
1824 scc_writel(RxSccRes, dpriv, dev, CMDR);
1825 dpriv->flags |= RdoSet;
1826
1827 /*
1828 * Let's try and save something in the received data.
1829 * rx_current must be incremented at least once to
1830 * avoid HOLD in the BRDA-to-be-pointed desc.
1831 */
1832 do {
1833 cur = dpriv->rx_current++%RX_RING_SIZE;
1834 rx_fd = dpriv->rx_fd + cur;
1835 if (!(rx_fd->state2 & DataComplete))
1836 break;
1837 if (rx_fd->state2 & FrameAborted) {
198191c4 1838 dev->stats.rx_over_errors++;
1da177e4
LT		 1839 rx_fd->state1 |= Hold;
1840 rx_fd->state2 = 0x00000000;
409cd63e 1841 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1842 } else
1843 dscc4_rx_skb(dpriv, dev);
1844 } while (1);
1845
1846 if (debug > 0) {
1847 if (dpriv->flags & RdoSet)
1848 printk(KERN_DEBUG
1849 "%s: no RDO in Rx data\n", DRV_NAME);
1850 }
1851#ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1852 /*
1853 * FIXME: must the reset be this violent ?
1854 */
1855#warning "FIXME: CH0BRDA"
1856 writel(dpriv->rx_fd_dma +
1857 (dpriv->rx_current%RX_RING_SIZE)*
1858 sizeof(struct RxFD), scc_addr + CH0BRDA);
1859 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1860 if (dscc4_do_action(dev, "RDR") < 0) {
1861 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1862 dev->name, "RDR");
1863 goto rdo_end;
1864 }
1865 writel(MTFi|Idr, scc_addr + CH0CFG);
1866 if (dscc4_do_action(dev, "IDR") < 0) {
1867 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1868 dev->name, "IDR");
1869 goto rdo_end;
1870 }
1871 rdo_end:
1872#endif
1873 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1874 goto try;
1875 }
1876 if (state & Cd) {
1877 printk(KERN_INFO "%s: CD transition\n", dev->name);
1878 if (!(state &= ~Cd)) /* DEBUG */
1879 goto try;
1880 }
1881 if (state & Flex) {
1882 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1883 if (!(state &= ~Flex))
1884 goto try;
1885 }
1886 }
1887}
1888
1889/*
1890 * I had expected the following to work for the first descriptor
1891 * (tx_fd->state = 0xc0000000)
1892 * - Hold=1 (don't try and branch to the next descripto);
1893 * - No=0 (I want an empty data section, i.e. size=0);
1894 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1895 * It failed and locked solid. Thus the introduction of a dummy skb.
1896 * Problem is acknowledged in errata sheet DS5. Joy :o/
1897 */
7665a089 1898static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1da177e4
LT		 1899{
1900 struct sk_buff *skb;
1901
1902 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1903 if (skb) {
1904 int last = dpriv->tx_dirty%TX_RING_SIZE;
1905 struct TxFD *tx_fd = dpriv->tx_fd + last;
1906
1907 skb->len = DUMMY_SKB_SIZE;
27d7ff46
ACM		 1908 skb_copy_to_linear_data(skb, version,
1909 strlen(version) % DUMMY_SKB_SIZE);
1da177e4 1910 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
409cd63e
AV		 1911 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1912 skb->data, DUMMY_SKB_SIZE,
1913 PCI_DMA_TODEVICE));
1da177e4
LT		 1914 dpriv->tx_skbuff[last] = skb;
1915 }
1916 return skb;
1917}
1918
1919static int dscc4_init_ring(struct net_device *dev)
1920{
1921 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1922 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1923 struct TxFD *tx_fd;
1924 struct RxFD *rx_fd;
1925 void *ring;
1926 int i;
1927
1928 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1929 if (!ring)
1930 goto err_out;
1931 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1932
1933 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1934 if (!ring)
1935 goto err_free_dma_rx;
1936 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1937
1938 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1939 dpriv->tx_dirty = 0xffffffff;
1940 i = dpriv->tx_current = 0;
1941 do {
1942 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1943 tx_fd->complete = 0x00000000;
1944 /* FIXME: NULL should be ok - to be tried */
409cd63e
AV		 1945 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1946 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1da177e4
LT		 1947 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1948 } while (i < TX_RING_SIZE);
1949
3e710bfa 1950 if (!dscc4_init_dummy_skb(dpriv))
1da177e4
LT		 1951 goto err_free_dma_tx;
1952
1953 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1954 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1955 do {
1956 /* size set by the host. Multiple of 4 bytes please */
1957 rx_fd->state1 = HiDesc;
1958 rx_fd->state2 = 0x00000000;
409cd63e 1959 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1960 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1961 // FIXME: return value verifiee mais traitement suspect
1962 if (try_get_rx_skb(dpriv, dev) >= 0)
1963 dpriv->rx_dirty++;
409cd63e 1964 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1da177e4
LT		 1965 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1966 } while (i < RX_RING_SIZE);
1967
1968 return 0;
1969
1970err_free_dma_tx:
1971 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1972err_free_dma_rx:
1973 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1974err_out:
1975 return -ENOMEM;
1976}
1977
1978static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1979{
1980 struct dscc4_pci_priv *ppriv;
1981 struct dscc4_dev_priv *root;
1982 void __iomem *ioaddr;
1983 int i;
1984
1985 ppriv = pci_get_drvdata(pdev);
1986 root = ppriv->root;
1987
1988 ioaddr = root->base_addr;
1989
1990 dscc4_pci_reset(pdev, ioaddr);
1991
1992 free_irq(pdev->irq, root);
1993 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1994 ppriv->iqcfg_dma);
1995 for (i = 0; i < dev_per_card; i++) {
1996 struct dscc4_dev_priv *dpriv = root + i;
1997
1998 dscc4_release_ring(dpriv);
1999 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
2000 dpriv->iqrx, dpriv->iqrx_dma);
2001 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
2002 dpriv->iqtx, dpriv->iqtx_dma);
2003 }
2004
2005 dscc4_free1(pdev);
2006
2007 iounmap(ioaddr);
2008
2009 pci_release_region(pdev, 1);
2010 pci_release_region(pdev, 0);
2011
2012 pci_disable_device(pdev);
2013}
2014
2015static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2016 unsigned short parity)
2017{
2018 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2019
2020 if (encoding != ENCODING_NRZ &&
2021 encoding != ENCODING_NRZI &&
2022 encoding != ENCODING_FM_MARK &&
2023 encoding != ENCODING_FM_SPACE &&
2024 encoding != ENCODING_MANCHESTER)
2025 return -EINVAL;
2026
2027 if (parity != PARITY_NONE &&
2028 parity != PARITY_CRC16_PR0_CCITT &&
2029 parity != PARITY_CRC16_PR1_CCITT &&
2030 parity != PARITY_CRC32_PR0_CCITT &&
2031 parity != PARITY_CRC32_PR1_CCITT)
2032 return -EINVAL;
2033
2034 dpriv->encoding = encoding;
2035 dpriv->parity = parity;
2036 return 0;
2037}
2038
2039#ifndef MODULE
2040static int __init dscc4_setup(char *str)
2041{
2042 int *args[] = { &debug, &quartz, NULL }, **p = args;
2043
2044 while (*p && (get_option(&str, *p) == 2))
2045 p++;
2046 return 1;
2047}
2048
2049__setup("dscc4.setup=", dscc4_setup);
2050#endif
2051
2052static struct pci_device_id dscc4_pci_tbl[] = {
2053 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2054 PCI_ANY_ID, PCI_ANY_ID, },
2055 { 0,}
2056};
2057MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2058
2059static struct pci_driver dscc4_driver = {
2060 .name = DRV_NAME,
2061 .id_table = dscc4_pci_tbl,
2062 .probe = dscc4_init_one,
2063 .remove = __devexit_p(dscc4_remove_one),
2064};
2065
2066static int __init dscc4_init_module(void)
2067{
29917620 2068 return pci_register_driver(&dscc4_driver);
1da177e4
LT		 2069}
2070
2071static void __exit dscc4_cleanup_module(void)
2072{
2073 pci_unregister_driver(&dscc4_driver);
2074}
2075
2076module_init(dscc4_init_module);
2077module_exit(dscc4_cleanup_module);
Linux kernel - Deliverables
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