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Merge branch 'r8169-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/romieu...
[deliverable/linux.git] / drivers / net / wan / wanxl.c
CommitLineData
1da177e4
LT		 1/*
2 * wanXL serial card driver for Linux
3 * host part
4 *
5 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
10 *
11 * Status:
12 * - Only DTE (external clock) support with NRZ and NRZI encodings
13 * - wanXL100 will require minor driver modifications, no access to hw
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/sched.h>
20#include <linux/types.h>
21#include <linux/fcntl.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/netdevice.h>
27#include <linux/hdlc.h>
28#include <linux/pci.h>
1e7f0bd8 29#include <linux/dma-mapping.h>
164006da 30#include <linux/delay.h>
1da177e4 31#include <asm/io.h>
1da177e4
LT		 32
33#include "wanxl.h"
34
35static const char* version = "wanXL serial card driver version: 0.48";
36
37#define PLX_CTL_RESET 0x40000000 /* adapter reset */
38
39#undef DEBUG_PKT
40#undef DEBUG_PCI
41
42/* MAILBOX #1 - PUTS COMMANDS */
43#define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
44#ifdef __LITTLE_ENDIAN
45#define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
46#else
47#define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
48#endif
49
50/* MAILBOX #2 - DRAM SIZE */
51#define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
52
53
54typedef struct {
55 struct net_device *dev;
56 struct card_t *card;
57 spinlock_t lock; /* for wanxl_xmit */
58 int node; /* physical port #0 - 3 */
59 unsigned int clock_type;
60 int tx_in, tx_out;
61 struct sk_buff *tx_skbs[TX_BUFFERS];
62}port_t;
63
64
65typedef struct {
66 desc_t rx_descs[RX_QUEUE_LENGTH];
67 port_status_t port_status[4];
68}card_status_t;
69
70
71typedef struct card_t {
72 int n_ports; /* 1, 2 or 4 ports */
73 u8 irq;
74
75 u8 __iomem *plx; /* PLX PCI9060 virtual base address */
76 struct pci_dev *pdev; /* for pci_name(pdev) */
77 int rx_in;
78 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
79 card_status_t *status; /* shared between host and card */
80 dma_addr_t status_address;
81 port_t ports[0]; /* 1 - 4 port_t structures follow */
82}card_t;
83
84
85
86static inline port_t* dev_to_port(struct net_device *dev)
87{
88 return (port_t *)dev_to_hdlc(dev)->priv;
89}
90
91
92static inline port_status_t* get_status(port_t *port)
93{
94 return &port->card->status->port_status[port->node];
95}
96
97
98#ifdef DEBUG_PCI
99static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr,
100 size_t size, int direction)
101{
102 dma_addr_t addr = pci_map_single(pdev, ptr, size, direction);
103 if (addr + size > 0x100000000LL)
104 printk(KERN_CRIT "wanXL %s: pci_map_single() returned memory"
105 " at 0x%LX!\n", pci_name(pdev),
106 (unsigned long long)addr);
107 return addr;
108}
109
110#undef pci_map_single
111#define pci_map_single pci_map_single_debug
112#endif
113
114
115/* Cable and/or personality module change interrupt service */
116static inline void wanxl_cable_intr(port_t *port)
117{
118 u32 value = get_status(port)->cable;
119 int valid = 1;
120 const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
121
122 switch(value & 0x7) {
123 case STATUS_CABLE_V35: cable = "V.35"; break;
124 case STATUS_CABLE_X21: cable = "X.21"; break;
125 case STATUS_CABLE_V24: cable = "V.24"; break;
126 case STATUS_CABLE_EIA530: cable = "EIA530"; break;
127 case STATUS_CABLE_NONE: cable = "no"; break;
128 default: cable = "invalid";
129 }
130
131 switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
132 case STATUS_CABLE_V35: pm = "V.35"; break;
133 case STATUS_CABLE_X21: pm = "X.21"; break;
134 case STATUS_CABLE_V24: pm = "V.24"; break;
135 case STATUS_CABLE_EIA530: pm = "EIA530"; break;
136 case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break;
137 default: pm = "invalid personality"; valid = 0;
138 }
139
140 if (valid) {
141 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
142 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
143 ", DSR off";
144 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
145 ", carrier off";
146 }
147 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
148 }
149 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n",
150 port->dev->name, pm, dte, cable, dsr, dcd);
151
c2ce9204
KH		 152 if (value & STATUS_CABLE_DCD)
153 netif_carrier_on(port->dev);
154 else
155 netif_carrier_off(port->dev);
1da177e4
LT		 156}
157
158
159
160/* Transmit complete interrupt service */
161static inline void wanxl_tx_intr(port_t *port)
162{
163 struct net_device *dev = port->dev;
1da177e4
LT		 164 while (1) {
165 desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
166 struct sk_buff *skb = port->tx_skbs[port->tx_in];
167
168 switch (desc->stat) {
169 case PACKET_FULL:
170 case PACKET_EMPTY:
171 netif_wake_queue(dev);
172 return;
173
174 case PACKET_UNDERRUN:
198191c4
KH		 175 dev->stats.tx_errors++;
176 dev->stats.tx_fifo_errors++;
1da177e4
LT		 177 break;
178
179 default:
198191c4
KH		 180 dev->stats.tx_packets++;
181 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 182 }
183 desc->stat = PACKET_EMPTY; /* Free descriptor */
184 pci_unmap_single(port->card->pdev, desc->address, skb->len,
185 PCI_DMA_TODEVICE);
186 dev_kfree_skb_irq(skb);
187 port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
188 }
189}
190
191
192
193/* Receive complete interrupt service */
194static inline void wanxl_rx_intr(card_t *card)
195{
196 desc_t *desc;
197 while (desc = &card->status->rx_descs[card->rx_in],
198 desc->stat != PACKET_EMPTY) {
199 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports)
200 printk(KERN_CRIT "wanXL %s: received packet for"
201 " nonexistent port\n", pci_name(card->pdev));
202 else {
203 struct sk_buff *skb = card->rx_skbs[card->rx_in];
204 port_t *port = &card->ports[desc->stat &
205 PACKET_PORT_MASK];
206 struct net_device *dev = port->dev;
1da177e4
LT		 207
208 if (!skb)
198191c4 209 dev->stats.rx_dropped++;
1da177e4
LT		 210 else {
211 pci_unmap_single(card->pdev, desc->address,
212 BUFFER_LENGTH,
213 PCI_DMA_FROMDEVICE);
214 skb_put(skb, desc->length);
215
216#ifdef DEBUG_PKT
217 printk(KERN_DEBUG "%s RX(%i):", dev->name,
218 skb->len);
219 debug_frame(skb);
220#endif
198191c4
KH		 221 dev->stats.rx_packets++;
222 dev->stats.rx_bytes += skb->len;
1da177e4
LT		 223 dev->last_rx = jiffies;
224 skb->protocol = hdlc_type_trans(skb, dev);
225 netif_rx(skb);
226 skb = NULL;
227 }
228
229 if (!skb) {
230 skb = dev_alloc_skb(BUFFER_LENGTH);
231 desc->address = skb ?
232 pci_map_single(card->pdev, skb->data,
233 BUFFER_LENGTH,
234 PCI_DMA_FROMDEVICE) : 0;
235 card->rx_skbs[card->rx_in] = skb;
236 }
237 }
238 desc->stat = PACKET_EMPTY; /* Free descriptor */
239 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
240 }
241}
242
243
244
7d12e780 245static irqreturn_t wanxl_intr(int irq, void* dev_id)
1da177e4
LT		 246{
247 card_t *card = dev_id;
248 int i;
249 u32 stat;
250 int handled = 0;
251
252
253 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
254 handled = 1;
255 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
256
257 for (i = 0; i < card->n_ports; i++) {
258 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
259 wanxl_tx_intr(&card->ports[i]);
260 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
261 wanxl_cable_intr(&card->ports[i]);
262 }
263 if (stat & (1 << DOORBELL_FROM_CARD_RX))
264 wanxl_rx_intr(card);
265 }
266
267 return IRQ_RETVAL(handled);
268}
269
270
271
272static int wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
273{
274 port_t *port = dev_to_port(dev);
275 desc_t *desc;
276
277 spin_lock(&port->lock);
278
279 desc = &get_status(port)->tx_descs[port->tx_out];
280 if (desc->stat != PACKET_EMPTY) {
281 /* should never happen - previous xmit should stop queue */
282#ifdef DEBUG_PKT
283 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
284#endif
285 netif_stop_queue(dev);
286 spin_unlock_irq(&port->lock);
287 return 1; /* request packet to be queued */
288 }
289
290#ifdef DEBUG_PKT
291 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
292 debug_frame(skb);
293#endif
294
295 port->tx_skbs[port->tx_out] = skb;
296 desc->address = pci_map_single(port->card->pdev, skb->data, skb->len,
297 PCI_DMA_TODEVICE);
298 desc->length = skb->len;
299 desc->stat = PACKET_FULL;
300 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
301 port->card->plx + PLX_DOORBELL_TO_CARD);
302 dev->trans_start = jiffies;
303
304 port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
305
306 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
307 netif_stop_queue(dev);
308#ifdef DEBUG_PKT
309 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
310#endif
311 }
312
313 spin_unlock(&port->lock);
314 return 0;
315}
316
317
318
319static int wanxl_attach(struct net_device *dev, unsigned short encoding,
320 unsigned short parity)
321{
322 port_t *port = dev_to_port(dev);
323
324 if (encoding != ENCODING_NRZ &&
325 encoding != ENCODING_NRZI)
326 return -EINVAL;
327
328 if (parity != PARITY_NONE &&
329 parity != PARITY_CRC32_PR1_CCITT &&
330 parity != PARITY_CRC16_PR1_CCITT &&
331 parity != PARITY_CRC32_PR0_CCITT &&
332 parity != PARITY_CRC16_PR0_CCITT)
333 return -EINVAL;
334
335 get_status(port)->encoding = encoding;
336 get_status(port)->parity = parity;
337 return 0;
338}
339
340
341
342static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
343{
344 const size_t size = sizeof(sync_serial_settings);
345 sync_serial_settings line;
346 port_t *port = dev_to_port(dev);
347
348 if (cmd != SIOCWANDEV)
349 return hdlc_ioctl(dev, ifr, cmd);
350
351 switch (ifr->ifr_settings.type) {
352 case IF_GET_IFACE:
353 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
354 if (ifr->ifr_settings.size < size) {
355 ifr->ifr_settings.size = size; /* data size wanted */
356 return -ENOBUFS;
357 }
358 line.clock_type = get_status(port)->clocking;
359 line.clock_rate = 0;
360 line.loopback = 0;
361
362 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
363 return -EFAULT;
364 return 0;
365
366 case IF_IFACE_SYNC_SERIAL:
367 if (!capable(CAP_NET_ADMIN))
368 return -EPERM;
369 if (dev->flags & IFF_UP)
370 return -EBUSY;
371
372 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync,
373 size))
374 return -EFAULT;
375
376 if (line.clock_type != CLOCK_EXT &&
377 line.clock_type != CLOCK_TXFROMRX)
378 return -EINVAL; /* No such clock setting */
379
380 if (line.loopback != 0)
381 return -EINVAL;
382
383 get_status(port)->clocking = line.clock_type;
384 return 0;
385
386 default:
387 return hdlc_ioctl(dev, ifr, cmd);
388 }
389}
390
391
392
393static int wanxl_open(struct net_device *dev)
394{
395 port_t *port = dev_to_port(dev);
396 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
397 unsigned long timeout;
398 int i;
399
400 if (get_status(port)->open) {
401 printk(KERN_ERR "%s: port already open\n", dev->name);
402 return -EIO;
403 }
404 if ((i = hdlc_open(dev)) != 0)
405 return i;
406
407 port->tx_in = port->tx_out = 0;
408 for (i = 0; i < TX_BUFFERS; i++)
409 get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
410 /* signal the card */
411 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
412
413 timeout = jiffies + HZ;
414 do
415 if (get_status(port)->open) {
416 netif_start_queue(dev);
417 return 0;
418 }
419 while (time_after(timeout, jiffies));
420
421 printk(KERN_ERR "%s: unable to open port\n", dev->name);
422 /* ask the card to close the port, should it be still alive */
423 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
424 return -EFAULT;
425}
426
427
428
429static int wanxl_close(struct net_device *dev)
430{
431 port_t *port = dev_to_port(dev);
432 unsigned long timeout;
433 int i;
434
435 hdlc_close(dev);
436 /* signal the card */
437 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
438 port->card->plx + PLX_DOORBELL_TO_CARD);
439
440 timeout = jiffies + HZ;
441 do
442 if (!get_status(port)->open)
443 break;
444 while (time_after(timeout, jiffies));
445
446 if (get_status(port)->open)
447 printk(KERN_ERR "%s: unable to close port\n", dev->name);
448
449 netif_stop_queue(dev);
450
451 for (i = 0; i < TX_BUFFERS; i++) {
452 desc_t *desc = &get_status(port)->tx_descs[i];
453
454 if (desc->stat != PACKET_EMPTY) {
455 desc->stat = PACKET_EMPTY;
456 pci_unmap_single(port->card->pdev, desc->address,
457 port->tx_skbs[i]->len,
458 PCI_DMA_TODEVICE);
459 dev_kfree_skb(port->tx_skbs[i]);
460 }
461 }
462 return 0;
463}
464
465
466
467static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
468{
1da177e4
LT		 469 port_t *port = dev_to_port(dev);
470
198191c4
KH		 471 dev->stats.rx_over_errors = get_status(port)->rx_overruns;
472 dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors;
473 dev->stats.rx_errors = dev->stats.rx_over_errors +
474 dev->stats.rx_frame_errors;
475 return &dev->stats;
1da177e4
LT		 476}
477
478
479
480static int wanxl_puts_command(card_t *card, u32 cmd)
481{
482 unsigned long timeout = jiffies + 5 * HZ;
483
484 writel(cmd, card->plx + PLX_MAILBOX_1);
485 do {
486 if (readl(card->plx + PLX_MAILBOX_1) == 0)
487 return 0;
488
489 schedule();
490 }while (time_after(timeout, jiffies));
491
492 return -1;
493}
494
495
496
497static void wanxl_reset(card_t *card)
498{
499 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
500
501 writel(0x80, card->plx + PLX_MAILBOX_0);
502 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
503 readl(card->plx + PLX_CONTROL); /* wait for posted write */
504 udelay(1);
505 writel(old_value, card->plx + PLX_CONTROL);
506 readl(card->plx + PLX_CONTROL); /* wait for posted write */
507}
508
509
510
511static void wanxl_pci_remove_one(struct pci_dev *pdev)
512{
513 card_t *card = pci_get_drvdata(pdev);
514 int i;
515
516 for (i = 0; i < card->n_ports; i++) {
517 unregister_hdlc_device(card->ports[i].dev);
518 free_netdev(card->ports[i].dev);
519 }
520
521 /* unregister and free all host resources */
522 if (card->irq)
523 free_irq(card->irq, card);
524
525 wanxl_reset(card);
526
527 for (i = 0; i < RX_QUEUE_LENGTH; i++)
528 if (card->rx_skbs[i]) {
529 pci_unmap_single(card->pdev,
530 card->status->rx_descs[i].address,
531 BUFFER_LENGTH, PCI_DMA_FROMDEVICE);
532 dev_kfree_skb(card->rx_skbs[i]);
533 }
534
535 if (card->plx)
536 iounmap(card->plx);
537
538 if (card->status)
539 pci_free_consistent(pdev, sizeof(card_status_t),
540 card->status, card->status_address);
541
542 pci_release_regions(pdev);
543 pci_disable_device(pdev);
544 pci_set_drvdata(pdev, NULL);
545 kfree(card);
546}
547
548
549#include "wanxlfw.inc"
550
551static int __devinit wanxl_pci_init_one(struct pci_dev *pdev,
552 const struct pci_device_id *ent)
553{
554 card_t *card;
555 u32 ramsize, stat;
556 unsigned long timeout;
557 u32 plx_phy; /* PLX PCI base address */
558 u32 mem_phy; /* memory PCI base addr */
559 u8 __iomem *mem; /* memory virtual base addr */
560 int i, ports, alloc_size;
561
562#ifndef MODULE
563 static int printed_version;
564 if (!printed_version) {
565 printed_version++;
566 printk(KERN_INFO "%s\n", version);
567 }
568#endif
569
570 i = pci_enable_device(pdev);
571 if (i)
572 return i;
573
574 /* QUICC can only access first 256 MB of host RAM directly,
575 but PLX9060 DMA does 32-bits for actual packet data transfers */
576
577 /* FIXME when PCI/DMA subsystems are fixed.
578 We set both dma_mask and consistent_dma_mask to 28 bits
579 and pray pci_alloc_consistent() will use this info. It should
580 work on most platforms */
910638ae
MG		 581 if (pci_set_consistent_dma_mask(pdev, DMA_28BIT_MASK) ||
582 pci_set_dma_mask(pdev, DMA_28BIT_MASK)) {
1da177e4
LT		 583 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
584 return -EIO;
585 }
586
587 i = pci_request_regions(pdev, "wanXL");
588 if (i) {
589 pci_disable_device(pdev);
590 return i;
591 }
592
593 switch (pdev->device) {
594 case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break;
595 case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break;
596 default: ports = 4;
597 }
598
599 alloc_size = sizeof(card_t) + ports * sizeof(port_t);
dd00cc48 600 card = kzalloc(alloc_size, GFP_KERNEL);
1da177e4
LT		 601 if (card == NULL) {
602 printk(KERN_ERR "wanXL %s: unable to allocate memory\n",
603 pci_name(pdev));
604 pci_release_regions(pdev);
605 pci_disable_device(pdev);
606 return -ENOBUFS;
607 }
1da177e4
LT		 608
609 pci_set_drvdata(pdev, card);
610 card->pdev = pdev;
611
612 card->status = pci_alloc_consistent(pdev, sizeof(card_status_t),
613 &card->status_address);
614 if (card->status == NULL) {
615 wanxl_pci_remove_one(pdev);
616 return -ENOBUFS;
617 }
618
619#ifdef DEBUG_PCI
620 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
621 " at 0x%LX\n", pci_name(pdev),
622 (unsigned long long)card->status_address);
623#endif
624
625 /* FIXME when PCI/DMA subsystems are fixed.
626 We set both dma_mask and consistent_dma_mask back to 32 bits
627 to indicate the card can do 32-bit DMA addressing */
1e7f0bd8
DP		 628 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK) ||
629 pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 630 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
631 wanxl_pci_remove_one(pdev);
632 return -EIO;
633 }
634
635 /* set up PLX mapping */
636 plx_phy = pci_resource_start(pdev, 0);
4446065a 637
1da177e4 638 card->plx = ioremap_nocache(plx_phy, 0x70);
4446065a
KH		 639 if (!card->plx) {
640 printk(KERN_ERR "wanxl: ioremap() failed\n");
641 wanxl_pci_remove_one(pdev);
642 return -EFAULT;
643 }
1da177e4
LT		 644
645#if RESET_WHILE_LOADING
646 wanxl_reset(card);
647#endif
648
649 timeout = jiffies + 20 * HZ;
650 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
651 if (time_before(timeout, jiffies)) {
652 printk(KERN_WARNING "wanXL %s: timeout waiting for"
653 " PUTS to complete\n", pci_name(pdev));
654 wanxl_pci_remove_one(pdev);
655 return -ENODEV;
656 }
657
658 switch(stat & 0xC0) {
659 case 0x00: /* hmm - PUTS completed with non-zero code? */
660 case 0x80: /* PUTS still testing the hardware */
661 break;
662
663 default:
664 printk(KERN_WARNING "wanXL %s: PUTS test 0x%X"
665 " failed\n", pci_name(pdev), stat & 0x30);
666 wanxl_pci_remove_one(pdev);
667 return -ENODEV;
668 }
669
670 schedule();
671 }
672
673 /* get on-board memory size (PUTS detects no more than 4 MB) */
674 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
675
676 /* set up on-board RAM mapping */
677 mem_phy = pci_resource_start(pdev, 2);
678
679
680 /* sanity check the board's reported memory size */
681 if (ramsize < BUFFERS_ADDR +
682 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
683 printk(KERN_WARNING "wanXL %s: no enough on-board RAM"
684 " (%u bytes detected, %u bytes required)\n",
685 pci_name(pdev), ramsize, BUFFERS_ADDR +
686 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
687 wanxl_pci_remove_one(pdev);
688 return -ENODEV;
689 }
690
691 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
692 printk(KERN_WARNING "wanXL %s: unable to Set Byte Swap"
693 " Mode\n", pci_name(pdev));
694 wanxl_pci_remove_one(pdev);
695 return -ENODEV;
696 }
697
698 for (i = 0; i < RX_QUEUE_LENGTH; i++) {
699 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
700 card->rx_skbs[i] = skb;
701 if (skb)
702 card->status->rx_descs[i].address =
703 pci_map_single(card->pdev, skb->data,
704 BUFFER_LENGTH,
705 PCI_DMA_FROMDEVICE);
706 }
707
708 mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware));
4446065a
KH		 709 if (!mem) {
710 printk(KERN_ERR "wanxl: ioremap() failed\n");
711 wanxl_pci_remove_one(pdev);
712 return -EFAULT;
713 }
714
1da177e4 715 for (i = 0; i < sizeof(firmware); i += 4)
90458401 716 writel(ntohl(*(__be32*)(firmware + i)), mem + PDM_OFFSET + i);
1da177e4
LT		 717
718 for (i = 0; i < ports; i++)
719 writel(card->status_address +
720 (void *)&card->status->port_status[i] -
721 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
722 writel(card->status_address, mem + PDM_OFFSET + 20);
723 writel(PDM_OFFSET, mem);
724 iounmap(mem);
725
726 writel(0, card->plx + PLX_MAILBOX_5);
727
728 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
729 printk(KERN_WARNING "wanXL %s: unable to Abort and Jump\n",
730 pci_name(pdev));
731 wanxl_pci_remove_one(pdev);
732 return -ENODEV;
733 }
734
735 stat = 0;
736 timeout = jiffies + 5 * HZ;
737 do {
738 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)
739 break;
740 schedule();
741 }while (time_after(timeout, jiffies));
742
743 if (!stat) {
93ab8e84 744 printk(KERN_WARNING "wanXL %s: timeout while initializing card "
1da177e4
LT		 745 "firmware\n", pci_name(pdev));
746 wanxl_pci_remove_one(pdev);
747 return -ENODEV;
748 }
749
750#if DETECT_RAM
751 ramsize = stat;
752#endif
753
754 printk(KERN_INFO "wanXL %s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n",
755 pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq);
756
757 /* Allocate IRQ */
1fb9df5d 758 if (request_irq(pdev->irq, wanxl_intr, IRQF_SHARED, "wanXL", card)) {
1da177e4
LT		 759 printk(KERN_WARNING "wanXL %s: could not allocate IRQ%i.\n",
760 pci_name(pdev), pdev->irq);
761 wanxl_pci_remove_one(pdev);
762 return -EBUSY;
763 }
764 card->irq = pdev->irq;
765
766 for (i = 0; i < ports; i++) {
767 hdlc_device *hdlc;
768 port_t *port = &card->ports[i];
769 struct net_device *dev = alloc_hdlcdev(port);
770 if (!dev) {
771 printk(KERN_ERR "wanXL %s: unable to allocate"
772 " memory\n", pci_name(pdev));
773 wanxl_pci_remove_one(pdev);
774 return -ENOMEM;
775 }
776
777 port->dev = dev;
778 hdlc = dev_to_hdlc(dev);
779 spin_lock_init(&port->lock);
1da177e4
LT		 780 dev->tx_queue_len = 50;
781 dev->do_ioctl = wanxl_ioctl;
782 dev->open = wanxl_open;
783 dev->stop = wanxl_close;
784 hdlc->attach = wanxl_attach;
785 hdlc->xmit = wanxl_xmit;
786 dev->get_stats = wanxl_get_stats;
787 port->card = card;
788 port->node = i;
789 get_status(port)->clocking = CLOCK_EXT;
790 if (register_hdlc_device(dev)) {
791 printk(KERN_ERR "wanXL %s: unable to register hdlc"
792 " device\n", pci_name(pdev));
793 free_netdev(dev);
794 wanxl_pci_remove_one(pdev);
795 return -ENOBUFS;
796 }
797 card->n_ports++;
798 }
799
800 printk(KERN_INFO "wanXL %s: port", pci_name(pdev));
801 for (i = 0; i < ports; i++)
802 printk("%s #%i: %s", i ? "," : "", i,
803 card->ports[i].dev->name);
804 printk("\n");
805
806 for (i = 0; i < ports; i++)
807 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/
808
809 return 0;
810}
811
812static struct pci_device_id wanxl_pci_tbl[] __devinitdata = {
813 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID,
814 PCI_ANY_ID, 0, 0, 0 },
815 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID,
816 PCI_ANY_ID, 0, 0, 0 },
817 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID,
818 PCI_ANY_ID, 0, 0, 0 },
819 { 0, }
820};
821
822
823static struct pci_driver wanxl_pci_driver = {
824 .name = "wanXL",
825 .id_table = wanxl_pci_tbl,
826 .probe = wanxl_pci_init_one,
827 .remove = wanxl_pci_remove_one,
828};
829
830
831static int __init wanxl_init_module(void)
832{
833#ifdef MODULE
834 printk(KERN_INFO "%s\n", version);
835#endif
29917620 836 return pci_register_driver(&wanxl_pci_driver);
1da177e4
LT		 837}
838
839static void __exit wanxl_cleanup_module(void)
840{
841 pci_unregister_driver(&wanxl_pci_driver);
842}
843
844
845MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
846MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
847MODULE_LICENSE("GPL v2");
848MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
849
850module_init(wanxl_init_module);
851module_exit(wanxl_cleanup_module);
Linux kernel - Deliverables
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