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dma-mapping: replace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32)
[deliverable/linux.git] / drivers / net / wireless / adm8211.c
CommitLineData
cc0b88cf
MW		 1
2/*
3 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
4 *
5 * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
6 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
7 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
8 * and used with permission.
9 *
10 * Much thanks to Infineon-ADMtek for their support of this driver.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. See README and COPYING for
15 * more details.
16 */
17
18#include <linux/init.h>
19#include <linux/if.h>
20#include <linux/skbuff.h>
21#include <linux/etherdevice.h>
22#include <linux/pci.h>
23#include <linux/delay.h>
24#include <linux/crc32.h>
25#include <linux/eeprom_93cx6.h>
26#include <net/mac80211.h>
27
28#include "adm8211.h"
29
30MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
31MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
32MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
33MODULE_SUPPORTED_DEVICE("ADM8211");
34MODULE_LICENSE("GPL");
35
36static unsigned int tx_ring_size __read_mostly = 16;
37static unsigned int rx_ring_size __read_mostly = 16;
38
39module_param(tx_ring_size, uint, 0);
40module_param(rx_ring_size, uint, 0);
41
cc0b88cf
MW		 42static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
43 /* ADMtek ADM8211 */
44 { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
45 { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
46 { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
47 { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
48 { 0 }
49};
50
8318d78a
JB		 51static struct ieee80211_rate adm8211_rates[] = {
52 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
53 { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
54 { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
55 { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
56 { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
57};
58
59static const struct ieee80211_channel adm8211_channels[] = {
60 { .center_freq = 2412},
61 { .center_freq = 2417},
62 { .center_freq = 2422},
63 { .center_freq = 2427},
64 { .center_freq = 2432},
65 { .center_freq = 2437},
66 { .center_freq = 2442},
67 { .center_freq = 2447},
68 { .center_freq = 2452},
69 { .center_freq = 2457},
70 { .center_freq = 2462},
71 { .center_freq = 2467},
72 { .center_freq = 2472},
73 { .center_freq = 2484},
74};
75
76
cc0b88cf
MW		 77static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
78{
79 struct adm8211_priv *priv = eeprom->data;
80 u32 reg = ADM8211_CSR_READ(SPR);
81
82 eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
83 eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
84 eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
85 eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
86}
87
88static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
89{
90 struct adm8211_priv *priv = eeprom->data;
91 u32 reg = 0x4000 | ADM8211_SPR_SRS;
92
93 if (eeprom->reg_data_in)
94 reg |= ADM8211_SPR_SDI;
95 if (eeprom->reg_data_out)
96 reg |= ADM8211_SPR_SDO;
97 if (eeprom->reg_data_clock)
98 reg |= ADM8211_SPR_SCLK;
99 if (eeprom->reg_chip_select)
100 reg |= ADM8211_SPR_SCS;
101
102 ADM8211_CSR_WRITE(SPR, reg);
103 ADM8211_CSR_READ(SPR); /* eeprom_delay */
104}
105
106static int adm8211_read_eeprom(struct ieee80211_hw *dev)
107{
108 struct adm8211_priv *priv = dev->priv;
109 unsigned int words, i;
110 struct ieee80211_chan_range chan_range;
111 u16 cr49;
112 struct eeprom_93cx6 eeprom = {
113 .data = priv,
114 .register_read = adm8211_eeprom_register_read,
115 .register_write = adm8211_eeprom_register_write
116 };
117
118 if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
119 /* 256 * 16-bit = 512 bytes */
120 eeprom.width = PCI_EEPROM_WIDTH_93C66;
121 words = 256;
122 } else {
123 /* 64 * 16-bit = 128 bytes */
124 eeprom.width = PCI_EEPROM_WIDTH_93C46;
125 words = 64;
126 }
127
128 priv->eeprom_len = words * 2;
129 priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
130 if (!priv->eeprom)
131 return -ENOMEM;
132
0e5ce1f3 133 eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
cc0b88cf
MW		 134
135 cr49 = le16_to_cpu(priv->eeprom->cr49);
136 priv->rf_type = (cr49 >> 3) & 0x7;
137 switch (priv->rf_type) {
138 case ADM8211_TYPE_INTERSIL:
139 case ADM8211_TYPE_RFMD:
140 case ADM8211_TYPE_MARVEL:
141 case ADM8211_TYPE_AIROHA:
142 case ADM8211_TYPE_ADMTEK:
143 break;
144
145 default:
f6ac0adf 146 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 147 priv->rf_type = ADM8211_TYPE_RFMD;
148 else
149 priv->rf_type = ADM8211_TYPE_AIROHA;
150
151 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
152 pci_name(priv->pdev), (cr49 >> 3) & 0x7);
153 }
154
155 priv->bbp_type = cr49 & 0x7;
156 switch (priv->bbp_type) {
157 case ADM8211_TYPE_INTERSIL:
158 case ADM8211_TYPE_RFMD:
159 case ADM8211_TYPE_MARVEL:
160 case ADM8211_TYPE_AIROHA:
161 case ADM8211_TYPE_ADMTEK:
162 break;
163 default:
f6ac0adf 164 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 165 priv->bbp_type = ADM8211_TYPE_RFMD;
166 else
167 priv->bbp_type = ADM8211_TYPE_ADMTEK;
168
169 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
170 pci_name(priv->pdev), cr49 >> 3);
171 }
172
173 if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
174 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
175 pci_name(priv->pdev), priv->eeprom->country_code);
176
177 chan_range = cranges[2];
178 } else
179 chan_range = cranges[priv->eeprom->country_code];
180
181 printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
182 pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
183
8318d78a 184 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
cc0b88cf 185
8318d78a
JB		 186 memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
187 priv->band.channels = priv->channels;
188 priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
189 priv->band.bitrates = adm8211_rates;
190 priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
cc0b88cf
MW		 191
192 for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
8318d78a
JB		 193 if (i < chan_range.min || i > chan_range.max)
194 priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
cc0b88cf
MW		 195
196 switch (priv->eeprom->specific_bbptype) {
197 case ADM8211_BBP_RFMD3000:
198 case ADM8211_BBP_RFMD3002:
199 case ADM8211_BBP_ADM8011:
200 priv->specific_bbptype = priv->eeprom->specific_bbptype;
201 break;
202
203 default:
f6ac0adf 204 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 205 priv->specific_bbptype = ADM8211_BBP_RFMD3000;
206 else
207 priv->specific_bbptype = ADM8211_BBP_ADM8011;
208
209 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
210 pci_name(priv->pdev), priv->eeprom->specific_bbptype);
211 }
212
213 switch (priv->eeprom->specific_rftype) {
214 case ADM8211_RFMD2948:
215 case ADM8211_RFMD2958:
216 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
217 case ADM8211_MAX2820:
218 case ADM8211_AL2210L:
219 priv->transceiver_type = priv->eeprom->specific_rftype;
220 break;
221
222 default:
f6ac0adf 223 if (priv->pdev->revision == ADM8211_REV_BA)
cc0b88cf 224 priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
f6ac0adf 225 else if (priv->pdev->revision == ADM8211_REV_CA)
cc0b88cf 226 priv->transceiver_type = ADM8211_AL2210L;
f6ac0adf 227 else if (priv->pdev->revision == ADM8211_REV_AB)
cc0b88cf
MW		 228 priv->transceiver_type = ADM8211_RFMD2948;
229
230 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
231 pci_name(priv->pdev), priv->eeprom->specific_rftype);
232
233 break;
234 }
235
236 printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
237 "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
238 priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
239
240 return 0;
241}
242
243static inline void adm8211_write_sram(struct ieee80211_hw *dev,
244 u32 addr, u32 data)
245{
246 struct adm8211_priv *priv = dev->priv;
247
248 ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
f6ac0adf 249 (priv->pdev->revision < ADM8211_REV_BA ?
cc0b88cf
MW		 250 0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
251 ADM8211_CSR_READ(WEPCTL);
252 msleep(1);
253
254 ADM8211_CSR_WRITE(WESK, data);
255 ADM8211_CSR_READ(WESK);
256 msleep(1);
257}
258
259static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
260 unsigned int addr, u8 *buf,
261 unsigned int len)
262{
263 struct adm8211_priv *priv = dev->priv;
264 u32 reg = ADM8211_CSR_READ(WEPCTL);
265 unsigned int i;
266
f6ac0adf 267 if (priv->pdev->revision < ADM8211_REV_BA) {
cc0b88cf
MW		 268 for (i = 0; i < len; i += 2) {
269 u16 val = buf[i] | (buf[i + 1] << 8);
270 adm8211_write_sram(dev, addr + i / 2, val);
271 }
272 } else {
273 for (i = 0; i < len; i += 4) {
274 u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
275 (buf[i + 2] << 16) | (buf[i + 3] << 24);
276 adm8211_write_sram(dev, addr + i / 4, val);
277 }
278 }
279
280 ADM8211_CSR_WRITE(WEPCTL, reg);
281}
282
283static void adm8211_clear_sram(struct ieee80211_hw *dev)
284{
285 struct adm8211_priv *priv = dev->priv;
286 u32 reg = ADM8211_CSR_READ(WEPCTL);
287 unsigned int addr;
288
289 for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
290 adm8211_write_sram(dev, addr, 0);
291
292 ADM8211_CSR_WRITE(WEPCTL, reg);
293}
294
295static int adm8211_get_stats(struct ieee80211_hw *dev,
296 struct ieee80211_low_level_stats *stats)
297{
298 struct adm8211_priv *priv = dev->priv;
299
300 memcpy(stats, &priv->stats, sizeof(*stats));
301
302 return 0;
303}
304
cc0b88cf
MW		 305static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
306 struct ieee80211_tx_queue_stats *stats)
307{
308 struct adm8211_priv *priv = dev->priv;
cc0b88cf 309
57ffc589
JB		 310 stats[0].len = priv->cur_tx - priv->dirty_tx;
311 stats[0].limit = priv->tx_ring_size - 2;
312 stats[0].count = priv->dirty_tx;
cc0b88cf
MW		 313
314 return 0;
315}
316
317static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
318{
319 struct adm8211_priv *priv = dev->priv;
320 unsigned int dirty_tx;
321
322 spin_lock(&priv->lock);
323
324 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
325 unsigned int entry = dirty_tx % priv->tx_ring_size;
326 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
e039fa4a 327 struct ieee80211_tx_info *txi;
cc0b88cf
MW		 328 struct adm8211_tx_ring_info *info;
329 struct sk_buff *skb;
330
331 if (status & TDES0_CONTROL_OWN ||
332 !(status & TDES0_CONTROL_DONE))
333 break;
334
335 info = &priv->tx_buffers[entry];
336 skb = info->skb;
e039fa4a 337 txi = IEEE80211_SKB_CB(skb);
cc0b88cf
MW		 338
339 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
340
341 pci_unmap_single(priv->pdev, info->mapping,
342 info->skb->len, PCI_DMA_TODEVICE);
343
e6a9854b
JB		 344 ieee80211_tx_info_clear_status(txi);
345
d703e29a
MW		 346 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
347 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
e6a9854b
JB		 348 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
349 !(status & TDES0_STATUS_ES))
350 txi->flags |= IEEE80211_TX_STAT_ACK;
351
e039fa4a 352 ieee80211_tx_status_irqsafe(dev, skb);
d703e29a 353
cc0b88cf
MW		 354 info->skb = NULL;
355 }
356
357 if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
358 ieee80211_wake_queue(dev, 0);
359
360 priv->dirty_tx = dirty_tx;
361 spin_unlock(&priv->lock);
362}
363
364
365static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
366{
367 struct adm8211_priv *priv = dev->priv;
368 unsigned int entry = priv->cur_rx % priv->rx_ring_size;
369 u32 status;
370 unsigned int pktlen;
371 struct sk_buff *skb, *newskb;
372 unsigned int limit = priv->rx_ring_size;
cc0b88cf
MW		 373 u8 rssi, rate;
374
375 while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
376 if (!limit--)
377 break;
378
379 status = le32_to_cpu(priv->rx_ring[entry].status);
380 rate = (status & RDES0_STATUS_RXDR) >> 12;
381 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
382 RDES1_STATUS_RSSI;
383
384 pktlen = status & RDES0_STATUS_FL;
385 if (pktlen > RX_PKT_SIZE) {
386 if (net_ratelimit())
387 printk(KERN_DEBUG "%s: frame too long (%d)\n",
388 wiphy_name(dev->wiphy), pktlen);
389 pktlen = RX_PKT_SIZE;
390 }
391
392 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
393 skb = NULL; /* old buffer will be reused */
394 /* TODO: update RX error stats */
395 /* TODO: check RDES0_STATUS_CRC*E */
396 } else if (pktlen < RX_COPY_BREAK) {
397 skb = dev_alloc_skb(pktlen);
398 if (skb) {
399 pci_dma_sync_single_for_cpu(
400 priv->pdev,
401 priv->rx_buffers[entry].mapping,
402 pktlen, PCI_DMA_FROMDEVICE);
403 memcpy(skb_put(skb, pktlen),
404 skb_tail_pointer(priv->rx_buffers[entry].skb),
405 pktlen);
406 pci_dma_sync_single_for_device(
407 priv->pdev,
408 priv->rx_buffers[entry].mapping,
409 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
410 }
411 } else {
412 newskb = dev_alloc_skb(RX_PKT_SIZE);
413 if (newskb) {
414 skb = priv->rx_buffers[entry].skb;
415 skb_put(skb, pktlen);
416 pci_unmap_single(
417 priv->pdev,
418 priv->rx_buffers[entry].mapping,
419 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
420 priv->rx_buffers[entry].skb = newskb;
421 priv->rx_buffers[entry].mapping =
422 pci_map_single(priv->pdev,
423 skb_tail_pointer(newskb),
424 RX_PKT_SIZE,
425 PCI_DMA_FROMDEVICE);
426 } else {
427 skb = NULL;
428 /* TODO: update rx dropped stats */
429 }
430
431 priv->rx_ring[entry].buffer1 =
432 cpu_to_le32(priv->rx_buffers[entry].mapping);
433 }
434
435 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
436 RDES0_STATUS_SQL);
437 priv->rx_ring[entry].length =
438 cpu_to_le32(RX_PKT_SIZE |
439 (entry == priv->rx_ring_size - 1 ?
440 RDES1_CONTROL_RER : 0));
441
442 if (skb) {
443 struct ieee80211_rx_status rx_status = {0};
444
f6ac0adf 445 if (priv->pdev->revision < ADM8211_REV_CA)
566bfe5a 446 rx_status.signal = rssi;
cc0b88cf 447 else
566bfe5a 448 rx_status.signal = 100 - rssi;
cc0b88cf 449
8318d78a 450 rx_status.rate_idx = rate;
cc0b88cf 451
8318d78a
JB		 452 rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
453 rx_status.band = IEEE80211_BAND_2GHZ;
cc0b88cf
MW		 454
455 ieee80211_rx_irqsafe(dev, skb, &rx_status);
456 }
457
458 entry = (++priv->cur_rx) % priv->rx_ring_size;
459 }
460
461 /* TODO: check LPC and update stats? */
462}
463
464
465static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
466{
467#define ADM8211_INT(x) \
468do { \
469 if (unlikely(stsr & ADM8211_STSR_ ## x)) \
470 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
471} while (0)
472
473 struct ieee80211_hw *dev = dev_id;
474 struct adm8211_priv *priv = dev->priv;
2e08ac7e
MW		 475 u32 stsr = ADM8211_CSR_READ(STSR);
476 ADM8211_CSR_WRITE(STSR, stsr);
477 if (stsr == 0xffffffff)
478 return IRQ_HANDLED;
479
480 if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
481 return IRQ_HANDLED;
482
483 if (stsr & ADM8211_STSR_RCI)
484 adm8211_interrupt_rci(dev);
485 if (stsr & ADM8211_STSR_TCI)
486 adm8211_interrupt_tci(dev);
487
2e08ac7e
MW		 488 ADM8211_INT(PCF);
489 ADM8211_INT(BCNTC);
490 ADM8211_INT(GPINT);
491 ADM8211_INT(ATIMTC);
492 ADM8211_INT(TSFTF);
493 ADM8211_INT(TSCZ);
494 ADM8211_INT(SQL);
495 ADM8211_INT(WEPTD);
496 ADM8211_INT(ATIME);
2e08ac7e
MW		 497 ADM8211_INT(TEIS);
498 ADM8211_INT(FBE);
499 ADM8211_INT(REIS);
500 ADM8211_INT(GPTT);
501 ADM8211_INT(RPS);
502 ADM8211_INT(RDU);
503 ADM8211_INT(TUF);
2e08ac7e
MW		 504 ADM8211_INT(TPS);
505
506 return IRQ_HANDLED;
cc0b88cf
MW		 507
508#undef ADM8211_INT
509}
510
511#define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
512static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev, \
513 u16 addr, u32 value) { \
514 struct adm8211_priv *priv = dev->priv; \
515 unsigned int i; \
516 u32 reg, bitbuf; \
517 \
518 value &= v_mask; \
519 addr &= a_mask; \
520 bitbuf = (value << v_shift) | (addr << a_shift); \
521 \
522 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1); \
523 ADM8211_CSR_READ(SYNRF); \
524 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0); \
525 ADM8211_CSR_READ(SYNRF); \
526 \
527 if (prewrite) { \
528 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0); \
529 ADM8211_CSR_READ(SYNRF); \
530 } \
531 \
532 for (i = 0; i <= bits; i++) { \
533 if (bitbuf & (1 << (bits - i))) \
534 reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \
535 else \
536 reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \
537 \
538 ADM8211_CSR_WRITE(SYNRF, reg); \
539 ADM8211_CSR_READ(SYNRF); \
540 \
541 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
542 ADM8211_CSR_READ(SYNRF); \
543 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
544 ADM8211_CSR_READ(SYNRF); \
545 } \
546 \
547 if (postwrite == 1) { \
548 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \
549 ADM8211_CSR_READ(SYNRF); \
550 } \
551 if (postwrite == 2) { \
552 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \
553 ADM8211_CSR_READ(SYNRF); \
554 } \
555 \
556 ADM8211_CSR_WRITE(SYNRF, 0); \
557 ADM8211_CSR_READ(SYNRF); \
558}
559
560WRITE_SYN(max2820, 0x00FFF, 0, 0x0F, 12, 15, 1, 1)
561WRITE_SYN(al2210l, 0xFFFFF, 4, 0x0F, 0, 23, 1, 1)
562WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
563WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F, 0, 21, 0, 2)
564
565#undef WRITE_SYN
566
567static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
568{
569 struct adm8211_priv *priv = dev->priv;
570 unsigned int timeout;
571 u32 reg;
572
573 timeout = 10;
574 while (timeout > 0) {
575 reg = ADM8211_CSR_READ(BBPCTL);
576 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
577 break;
578 timeout--;
579 msleep(2);
580 }
581
582 if (timeout == 0) {
583 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
584 " prewrite (reg=0x%08x)\n",
585 wiphy_name(dev->wiphy), addr, data, reg);
586 return -ETIMEDOUT;
587 }
588
589 switch (priv->bbp_type) {
590 case ADM8211_TYPE_INTERSIL:
591 reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */
592 break;
593 case ADM8211_TYPE_RFMD:
594 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
595 (0x01 << 18);
596 break;
597 case ADM8211_TYPE_ADMTEK:
598 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
599 (0x05 << 18);
600 break;
601 }
602 reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
603
604 ADM8211_CSR_WRITE(BBPCTL, reg);
605
606 timeout = 10;
607 while (timeout > 0) {
608 reg = ADM8211_CSR_READ(BBPCTL);
609 if (!(reg & ADM8211_BBPCTL_WR))
610 break;
611 timeout--;
612 msleep(2);
613 }
614
615 if (timeout == 0) {
616 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
617 ~ADM8211_BBPCTL_WR);
618 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
619 " postwrite (reg=0x%08x)\n",
620 wiphy_name(dev->wiphy), addr, data, reg);
621 return -ETIMEDOUT;
622 }
623
624 return 0;
625}
626
627static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
628{
629 static const u32 adm8211_rfmd2958_reg5[] =
630 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
631 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
632 static const u32 adm8211_rfmd2958_reg6[] =
633 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
634 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
635
636 struct adm8211_priv *priv = dev->priv;
637 u8 ant_power = priv->ant_power > 0x3F ?
638 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
639 u8 tx_power = priv->tx_power > 0x3F ?
640 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
641 u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
642 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
643 u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
644 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
645 u32 reg;
646
647 ADM8211_IDLE();
648
649 /* Program synthesizer to new channel */
650 switch (priv->transceiver_type) {
651 case ADM8211_RFMD2958:
652 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
653 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
654 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
655
656 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
657 adm8211_rfmd2958_reg5[chan - 1]);
658 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
659 adm8211_rfmd2958_reg6[chan - 1]);
660 break;
661
662 case ADM8211_RFMD2948:
663 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
664 SI4126_MAIN_XINDIV2);
665 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
666 SI4126_POWERDOWN_PDIB |
667 SI4126_POWERDOWN_PDRB);
668 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
669 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
670 (chan == 14 ?
671 2110 : (2033 + (chan * 5))));
672 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
673 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
674 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
675 break;
676
677 case ADM8211_MAX2820:
678 adm8211_rf_write_syn_max2820(dev, 0x3,
679 (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
680 break;
681
682 case ADM8211_AL2210L:
683 adm8211_rf_write_syn_al2210l(dev, 0x0,
684 (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
685 break;
686
687 default:
688 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
689 wiphy_name(dev->wiphy), priv->transceiver_type);
690 break;
691 }
692
693 /* write BBP regs */
694 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
695
696 /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
697 /* TODO: remove if SMC 2635W doesn't need this */
698 if (priv->transceiver_type == ADM8211_RFMD2948) {
699 reg = ADM8211_CSR_READ(GPIO);
700 reg &= 0xfffc0000;
701 reg |= ADM8211_CSR_GPIO_EN0;
702 if (chan != 14)
703 reg |= ADM8211_CSR_GPIO_O0;
704 ADM8211_CSR_WRITE(GPIO, reg);
705 }
706
707 if (priv->transceiver_type == ADM8211_RFMD2958) {
708 /* set PCNT2 */
709 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
710 /* set PCNT1 P_DESIRED/MID_BIAS */
711 reg = le16_to_cpu(priv->eeprom->cr49);
712 reg >>= 13;
713 reg <<= 15;
714 reg |= ant_power << 9;
715 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
716 /* set TXRX TX_GAIN */
717 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
f6ac0adf 718 (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
cc0b88cf
MW		 719 } else {
720 reg = ADM8211_CSR_READ(PLCPHD);
721 reg &= 0xff00ffff;
722 reg |= tx_power << 18;
723 ADM8211_CSR_WRITE(PLCPHD, reg);
724 }
725
726 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
727 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
728 ADM8211_CSR_READ(SYNRF);
729 msleep(30);
730
731 /* RF3000 BBP */
732 if (priv->transceiver_type != ADM8211_RFMD2958)
733 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
734 tx_power<<2);
735 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
736 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
f6ac0adf 737 adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
cc0b88cf
MW		 738 priv->eeprom->cr28 : 0);
739 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
740
741 ADM8211_CSR_WRITE(SYNRF, 0);
742
743 /* Nothing to do for ADMtek BBP */
744 } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
745 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
746 wiphy_name(dev->wiphy), priv->bbp_type);
747
748 ADM8211_RESTORE();
749
750 /* update current channel for adhoc (and maybe AP mode) */
751 reg = ADM8211_CSR_READ(CAP0);
752 reg &= ~0xF;
753 reg |= chan;
754 ADM8211_CSR_WRITE(CAP0, reg);
755
756 return 0;
757}
758
759static void adm8211_update_mode(struct ieee80211_hw *dev)
760{
761 struct adm8211_priv *priv = dev->priv;
762
763 ADM8211_IDLE();
764
765 priv->soft_rx_crc = 0;
766 switch (priv->mode) {
05c914fe 767 case NL80211_IFTYPE_STATION:
cc0b88cf
MW		 768 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
769 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
770 break;
05c914fe 771 case NL80211_IFTYPE_ADHOC:
cc0b88cf
MW		 772 priv->nar &= ~ADM8211_NAR_PR;
773 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
774
775 /* don't trust the error bits on rev 0x20 and up in adhoc */
f6ac0adf 776 if (priv->pdev->revision >= ADM8211_REV_BA)
cc0b88cf
MW		 777 priv->soft_rx_crc = 1;
778 break;
05c914fe 779 case NL80211_IFTYPE_MONITOR:
cc0b88cf
MW		 780 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
781 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
782 break;
783 }
784
785 ADM8211_RESTORE();
786}
787
788static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
789{
790 struct adm8211_priv *priv = dev->priv;
791
792 switch (priv->transceiver_type) {
793 case ADM8211_RFMD2958:
794 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
795 /* comments taken from ADMtek vendor driver */
796
797 /* Reset RF2958 after power on */
798 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
799 /* Initialize RF VCO Core Bias to maximum */
800 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
801 /* Initialize IF PLL */
802 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
803 /* Initialize IF PLL Coarse Tuning */
804 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
805 /* Initialize RF PLL */
806 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
807 /* Initialize RF PLL Coarse Tuning */
808 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
809 /* Initialize TX gain and filter BW (R9) */
810 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
811 (priv->transceiver_type == ADM8211_RFMD2958 ?
812 0x10050 : 0x00050));
813 /* Initialize CAL register */
814 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
815 break;
816
817 case ADM8211_MAX2820:
818 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
819 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
820 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
821 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
822 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
823 break;
824
825 case ADM8211_AL2210L:
826 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
827 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
828 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
829 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
830 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
831 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
832 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
833 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
834 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
835 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
836 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
837 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
838 break;
839
840 case ADM8211_RFMD2948:
841 default:
842 break;
843 }
844}
845
846static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
847{
848 struct adm8211_priv *priv = dev->priv;
849 u32 reg;
850
851 /* write addresses */
852 if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
853 ADM8211_CSR_WRITE(MMIWA, 0x100E0C0A);
854 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
855 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
856 } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
857 priv->bbp_type == ADM8211_TYPE_ADMTEK) {
858 /* check specific BBP type */
859 switch (priv->specific_bbptype) {
860 case ADM8211_BBP_RFMD3000:
861 case ADM8211_BBP_RFMD3002:
862 ADM8211_CSR_WRITE(MMIWA, 0x00009101);
863 ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
864 break;
865
866 case ADM8211_BBP_ADM8011:
867 ADM8211_CSR_WRITE(MMIWA, 0x00008903);
868 ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
869
870 reg = ADM8211_CSR_READ(BBPCTL);
871 reg &= ~ADM8211_BBPCTL_TYPE;
872 reg |= 0x5 << 18;
873 ADM8211_CSR_WRITE(BBPCTL, reg);
874 break;
875 }
876
f6ac0adf 877 switch (priv->pdev->revision) {
cc0b88cf
MW		 878 case ADM8211_REV_CA:
879 if (priv->transceiver_type == ADM8211_RFMD2958 ||
880 priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
881 priv->transceiver_type == ADM8211_RFMD2948)
882 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
883 else if (priv->transceiver_type == ADM8211_MAX2820 ||
884 priv->transceiver_type == ADM8211_AL2210L)
885 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
886 break;
887
888 case ADM8211_REV_BA:
889 reg = ADM8211_CSR_READ(MMIRD1);
890 reg &= 0x0000FFFF;
891 reg |= 0x7e100000;
892 ADM8211_CSR_WRITE(MMIRD1, reg);
893 break;
894
895 case ADM8211_REV_AB:
896 case ADM8211_REV_AF:
897 default:
898 ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
899 break;
900 }
901
902 /* For RFMD */
903 ADM8211_CSR_WRITE(MACTEST, 0x800);
904 }
905
906 adm8211_hw_init_syn(dev);
907
908 /* Set RF Power control IF pin to PE1+PHYRST# */
909 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
910 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
911 ADM8211_CSR_READ(SYNRF);
912 msleep(20);
913
914 /* write BBP regs */
915 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
916 /* RF3000 BBP */
917 /* another set:
918 * 11: c8
919 * 14: 14
920 * 15: 50 (chan 1..13; chan 14: d0)
921 * 1c: 00
922 * 1d: 84
923 */
924 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
925 /* antenna selection: diversity */
926 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
927 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
928 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
929 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
930
931 if (priv->eeprom->major_version < 2) {
932 adm8211_write_bbp(dev, 0x1c, 0x00);
933 adm8211_write_bbp(dev, 0x1d, 0x80);
934 } else {
f6ac0adf 935 if (priv->pdev->revision == ADM8211_REV_BA)
cc0b88cf
MW		 936 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
937 else
938 adm8211_write_bbp(dev, 0x1c, 0x00);
939
940 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
941 }
942 } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
943 /* reset baseband */
944 adm8211_write_bbp(dev, 0x00, 0xFF);
945 /* antenna selection: diversity */
946 adm8211_write_bbp(dev, 0x07, 0x0A);
947
948 /* TODO: find documentation for this */
949 switch (priv->transceiver_type) {
950 case ADM8211_RFMD2958:
951 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
952 adm8211_write_bbp(dev, 0x00, 0x00);
953 adm8211_write_bbp(dev, 0x01, 0x00);
954 adm8211_write_bbp(dev, 0x02, 0x00);
955 adm8211_write_bbp(dev, 0x03, 0x00);
956 adm8211_write_bbp(dev, 0x06, 0x0f);
957 adm8211_write_bbp(dev, 0x09, 0x00);
958 adm8211_write_bbp(dev, 0x0a, 0x00);
959 adm8211_write_bbp(dev, 0x0b, 0x00);
960 adm8211_write_bbp(dev, 0x0c, 0x00);
961 adm8211_write_bbp(dev, 0x0f, 0xAA);
962 adm8211_write_bbp(dev, 0x10, 0x8c);
963 adm8211_write_bbp(dev, 0x11, 0x43);
964 adm8211_write_bbp(dev, 0x18, 0x40);
965 adm8211_write_bbp(dev, 0x20, 0x23);
966 adm8211_write_bbp(dev, 0x21, 0x02);
967 adm8211_write_bbp(dev, 0x22, 0x28);
968 adm8211_write_bbp(dev, 0x23, 0x30);
969 adm8211_write_bbp(dev, 0x24, 0x2d);
970 adm8211_write_bbp(dev, 0x28, 0x35);
971 adm8211_write_bbp(dev, 0x2a, 0x8c);
972 adm8211_write_bbp(dev, 0x2b, 0x81);
973 adm8211_write_bbp(dev, 0x2c, 0x44);
974 adm8211_write_bbp(dev, 0x2d, 0x0A);
975 adm8211_write_bbp(dev, 0x29, 0x40);
976 adm8211_write_bbp(dev, 0x60, 0x08);
977 adm8211_write_bbp(dev, 0x64, 0x01);
978 break;
979
980 case ADM8211_MAX2820:
981 adm8211_write_bbp(dev, 0x00, 0x00);
982 adm8211_write_bbp(dev, 0x01, 0x00);
983 adm8211_write_bbp(dev, 0x02, 0x00);
984 adm8211_write_bbp(dev, 0x03, 0x00);
985 adm8211_write_bbp(dev, 0x06, 0x0f);
986 adm8211_write_bbp(dev, 0x09, 0x05);
987 adm8211_write_bbp(dev, 0x0a, 0x02);
988 adm8211_write_bbp(dev, 0x0b, 0x00);
989 adm8211_write_bbp(dev, 0x0c, 0x0f);
990 adm8211_write_bbp(dev, 0x0f, 0x55);
991 adm8211_write_bbp(dev, 0x10, 0x8d);
992 adm8211_write_bbp(dev, 0x11, 0x43);
993 adm8211_write_bbp(dev, 0x18, 0x4a);
994 adm8211_write_bbp(dev, 0x20, 0x20);
995 adm8211_write_bbp(dev, 0x21, 0x02);
996 adm8211_write_bbp(dev, 0x22, 0x23);
997 adm8211_write_bbp(dev, 0x23, 0x30);
998 adm8211_write_bbp(dev, 0x24, 0x2d);
999 adm8211_write_bbp(dev, 0x2a, 0x8c);
1000 adm8211_write_bbp(dev, 0x2b, 0x81);
1001 adm8211_write_bbp(dev, 0x2c, 0x44);
1002 adm8211_write_bbp(dev, 0x29, 0x4a);
1003 adm8211_write_bbp(dev, 0x60, 0x2b);
1004 adm8211_write_bbp(dev, 0x64, 0x01);
1005 break;
1006
1007 case ADM8211_AL2210L:
1008 adm8211_write_bbp(dev, 0x00, 0x00);
1009 adm8211_write_bbp(dev, 0x01, 0x00);
1010 adm8211_write_bbp(dev, 0x02, 0x00);
1011 adm8211_write_bbp(dev, 0x03, 0x00);
1012 adm8211_write_bbp(dev, 0x06, 0x0f);
1013 adm8211_write_bbp(dev, 0x07, 0x05);
1014 adm8211_write_bbp(dev, 0x08, 0x03);
1015 adm8211_write_bbp(dev, 0x09, 0x00);
1016 adm8211_write_bbp(dev, 0x0a, 0x00);
1017 adm8211_write_bbp(dev, 0x0b, 0x00);
1018 adm8211_write_bbp(dev, 0x0c, 0x10);
1019 adm8211_write_bbp(dev, 0x0f, 0x55);
1020 adm8211_write_bbp(dev, 0x10, 0x8d);
1021 adm8211_write_bbp(dev, 0x11, 0x43);
1022 adm8211_write_bbp(dev, 0x18, 0x4a);
1023 adm8211_write_bbp(dev, 0x20, 0x20);
1024 adm8211_write_bbp(dev, 0x21, 0x02);
1025 adm8211_write_bbp(dev, 0x22, 0x23);
1026 adm8211_write_bbp(dev, 0x23, 0x30);
1027 adm8211_write_bbp(dev, 0x24, 0x2d);
1028 adm8211_write_bbp(dev, 0x2a, 0xaa);
1029 adm8211_write_bbp(dev, 0x2b, 0x81);
1030 adm8211_write_bbp(dev, 0x2c, 0x44);
1031 adm8211_write_bbp(dev, 0x29, 0xfa);
1032 adm8211_write_bbp(dev, 0x60, 0x2d);
1033 adm8211_write_bbp(dev, 0x64, 0x01);
1034 break;
1035
1036 case ADM8211_RFMD2948:
1037 break;
1038
1039 default:
1040 printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1041 wiphy_name(dev->wiphy), priv->transceiver_type);
1042 break;
1043 }
1044 } else
1045 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1046 wiphy_name(dev->wiphy), priv->bbp_type);
1047
1048 ADM8211_CSR_WRITE(SYNRF, 0);
1049
1050 /* Set RF CAL control source to MAC control */
1051 reg = ADM8211_CSR_READ(SYNCTL);
1052 reg |= ADM8211_SYNCTL_SELCAL;
1053 ADM8211_CSR_WRITE(SYNCTL, reg);
1054
1055 return 0;
1056}
1057
1058/* configures hw beacons/probe responses */
1059static int adm8211_set_rate(struct ieee80211_hw *dev)
1060{
1061 struct adm8211_priv *priv = dev->priv;
1062 u32 reg;
1063 int i = 0;
1064 u8 rate_buf[12] = {0};
1065
1066 /* write supported rates */
f6ac0adf 1067 if (priv->pdev->revision != ADM8211_REV_BA) {
cc0b88cf
MW		 1068 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1069 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
8318d78a 1070 rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
cc0b88cf
MW		 1071 } else {
1072 /* workaround for rev BA specific bug */
1073 rate_buf[0] = 0x04;
1074 rate_buf[1] = 0x82;
1075 rate_buf[2] = 0x04;
1076 rate_buf[3] = 0x0b;
1077 rate_buf[4] = 0x16;
1078 }
1079
1080 adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1081 ARRAY_SIZE(adm8211_rates) + 1);
1082
1083 reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1084 reg |= 1 << 15; /* short preamble */
1085 reg |= 110 << 24;
1086 ADM8211_CSR_WRITE(PLCPHD, reg);
1087
1088 /* MTMLT = 512 TU (max TX MSDU lifetime)
1089 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1090 * SRTYLIM = 224 (short retry limit, TX header value is default) */
1091 ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1092
1093 return 0;
1094}
1095
1096static void adm8211_hw_init(struct ieee80211_hw *dev)
1097{
1098 struct adm8211_priv *priv = dev->priv;
1099 u32 reg;
1100 u8 cline;
1101
e63e3fa7 1102 reg = ADM8211_CSR_READ(PAR);
cc0b88cf
MW		 1103 reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1104 reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1105
1106 if (!pci_set_mwi(priv->pdev)) {
1107 reg |= 0x1 << 24;
1108 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1109
1110 switch (cline) {
1111 case 0x8: reg |= (0x1 << 14);
1112 break;
1113 case 0x16: reg |= (0x2 << 14);
1114 break;
1115 case 0x32: reg |= (0x3 << 14);
1116 break;
1117 default: reg |= (0x0 << 14);
1118 break;
1119 }
1120 }
1121
1122 ADM8211_CSR_WRITE(PAR, reg);
1123
1124 reg = ADM8211_CSR_READ(CSR_TEST1);
1125 reg &= ~(0xF << 28);
1126 reg |= (1 << 28) | (1 << 31);
1127 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1128
1129 /* lose link after 4 lost beacons */
1130 reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1131 ADM8211_CSR_WRITE(WCSR, reg);
1132
1133 /* Disable APM, enable receive FIFO threshold, and set drain receive
1134 * threshold to store-and-forward */
1135 reg = ADM8211_CSR_READ(CMDR);
1136 reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1137 reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1138 ADM8211_CSR_WRITE(CMDR, reg);
1139
1140 adm8211_set_rate(dev);
1141
1142 /* 4-bit values:
1143 * PWR1UP = 8 * 2 ms
1144 * PWR0PAPE = 8 us or 5 us
1145 * PWR1PAPE = 1 us or 3 us
1146 * PWR0TRSW = 5 us
1147 * PWR1TRSW = 12 us
1148 * PWR0PE2 = 13 us
1149 * PWR1PE2 = 1 us
1150 * PWR0TXPE = 8 or 6 */
f6ac0adf 1151 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 1152 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1153 else
1154 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1155
1156 /* Enable store and forward for transmit */
1157 priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1158 ADM8211_CSR_WRITE(NAR, priv->nar);
1159
1160 /* Reset RF */
1161 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1162 ADM8211_CSR_READ(SYNRF);
1163 msleep(10);
1164 ADM8211_CSR_WRITE(SYNRF, 0);
1165 ADM8211_CSR_READ(SYNRF);
1166 msleep(5);
1167
1168 /* Set CFP Max Duration to 0x10 TU */
1169 reg = ADM8211_CSR_READ(CFPP);
1170 reg &= ~(0xffff << 8);
1171 reg |= 0x0010 << 8;
1172 ADM8211_CSR_WRITE(CFPP, reg);
1173
1174 /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1175 * TUCNT = 0x3ff - Tu counter 1024 us */
1176 ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1177
1178 /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1179 * DIFS=50 us, EIFS=100 us */
f6ac0adf 1180 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 1181 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1182 (50 << 9) | 100);
1183 else
1184 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1185 (50 << 9) | 100);
1186
1187 /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1188 * RMRD = 2346 * 8 + 1 us (max RX duration) */
1189 ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1190
1191 /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1192 ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1193
1194 /* Initialize BBP (and SYN) */
1195 adm8211_hw_init_bbp(dev);
1196
1197 /* make sure interrupts are off */
1198 ADM8211_CSR_WRITE(IER, 0);
1199
1200 /* ACK interrupts */
1201 ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1202
1203 /* Setup WEP (turns it off for now) */
1204 reg = ADM8211_CSR_READ(MACTEST);
1205 reg &= ~(7 << 20);
1206 ADM8211_CSR_WRITE(MACTEST, reg);
1207
1208 reg = ADM8211_CSR_READ(WEPCTL);
1209 reg &= ~ADM8211_WEPCTL_WEPENABLE;
1210 reg |= ADM8211_WEPCTL_WEPRXBYP;
1211 ADM8211_CSR_WRITE(WEPCTL, reg);
1212
1213 /* Clear the missed-packet counter. */
1214 ADM8211_CSR_READ(LPC);
cc0b88cf
MW		 1215}
1216
1217static int adm8211_hw_reset(struct ieee80211_hw *dev)
1218{
1219 struct adm8211_priv *priv = dev->priv;
1220 u32 reg, tmp;
1221 int timeout = 100;
1222
1223 /* Power-on issue */
1224 /* TODO: check if this is necessary */
1225 ADM8211_CSR_WRITE(FRCTL, 0);
1226
1227 /* Reset the chip */
1228 tmp = ADM8211_CSR_READ(PAR);
1229 ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1230
1231 while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1232 msleep(50);
1233
1234 if (timeout <= 0)
1235 return -ETIMEDOUT;
1236
1237 ADM8211_CSR_WRITE(PAR, tmp);
1238
f6ac0adf 1239 if (priv->pdev->revision == ADM8211_REV_BA &&
cc0b88cf
MW		 1240 (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1241 priv->transceiver_type == ADM8211_RFMD2958)) {
1242 reg = ADM8211_CSR_READ(CSR_TEST1);
1243 reg |= (1 << 4) | (1 << 5);
1244 ADM8211_CSR_WRITE(CSR_TEST1, reg);
f6ac0adf 1245 } else if (priv->pdev->revision == ADM8211_REV_CA) {
cc0b88cf
MW		 1246 reg = ADM8211_CSR_READ(CSR_TEST1);
1247 reg &= ~((1 << 4) | (1 << 5));
1248 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1249 }
1250
1251 ADM8211_CSR_WRITE(FRCTL, 0);
1252
1253 reg = ADM8211_CSR_READ(CSR_TEST0);
1254 reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1255 ADM8211_CSR_WRITE(CSR_TEST0, reg);
1256
1257 adm8211_clear_sram(dev);
1258
1259 return 0;
1260}
1261
1262static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1263{
1264 struct adm8211_priv *priv = dev->priv;
1265 u32 tsftl;
1266 u64 tsft;
1267
1268 tsftl = ADM8211_CSR_READ(TSFTL);
1269 tsft = ADM8211_CSR_READ(TSFTH);
1270 tsft <<= 32;
1271 tsft |= tsftl;
1272
1273 return tsft;
1274}
1275
1276static void adm8211_set_interval(struct ieee80211_hw *dev,
1277 unsigned short bi, unsigned short li)
1278{
1279 struct adm8211_priv *priv = dev->priv;
1280 u32 reg;
1281
1282 /* BP (beacon interval) = data->beacon_interval
1283 * LI (listen interval) = data->listen_interval (in beacon intervals) */
1284 reg = (bi << 16) | li;
1285 ADM8211_CSR_WRITE(BPLI, reg);
1286}
1287
4150c572 1288static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
cc0b88cf
MW		 1289{
1290 struct adm8211_priv *priv = dev->priv;
1291 u32 reg;
1292
fb9bc28f 1293 ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
cc0b88cf
MW		 1294 reg = ADM8211_CSR_READ(ABDA1);
1295 reg &= 0x0000ffff;
1296 reg |= (bssid[4] << 16) | (bssid[5] << 24);
1297 ADM8211_CSR_WRITE(ABDA1, reg);
1298}
1299
e8975581 1300static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
cc0b88cf
MW		 1301{
1302 struct adm8211_priv *priv = dev->priv;
e8975581 1303 struct ieee80211_conf *conf = &dev->conf;
8318d78a 1304 int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
cc0b88cf 1305
8318d78a
JB		 1306 if (channel != priv->channel) {
1307 priv->channel = channel;
cc0b88cf
MW		 1308 adm8211_rf_set_channel(dev, priv->channel);
1309 }
1310
1311 return 0;
1312}
1313
32bfd35d
JB		 1314static int adm8211_config_interface(struct ieee80211_hw *dev,
1315 struct ieee80211_vif *vif,
cc0b88cf
MW		 1316 struct ieee80211_if_conf *conf)
1317{
1318 struct adm8211_priv *priv = dev->priv;
1319
1320 if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1321 adm8211_set_bssid(dev, conf->bssid);
1322 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1323 }
1324
cc0b88cf
MW		 1325 return 0;
1326}
1327
4150c572
JB		 1328static void adm8211_configure_filter(struct ieee80211_hw *dev,
1329 unsigned int changed_flags,
1330 unsigned int *total_flags,
1331 int mc_count, struct dev_mc_list *mclist)
1332{
1333 static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1334 struct adm8211_priv *priv = dev->priv;
1335 unsigned int bit_nr, new_flags;
1336 u32 mc_filter[2];
1337 int i;
1338
1339 new_flags = 0;
1340
1341 if (*total_flags & FIF_PROMISC_IN_BSS) {
1342 new_flags |= FIF_PROMISC_IN_BSS;
1343 priv->nar |= ADM8211_NAR_PR;
1344 priv->nar &= ~ADM8211_NAR_MM;
1345 mc_filter[1] = mc_filter[0] = ~0;
1346 } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
1347 new_flags |= FIF_ALLMULTI;
1348 priv->nar &= ~ADM8211_NAR_PR;
1349 priv->nar |= ADM8211_NAR_MM;
1350 mc_filter[1] = mc_filter[0] = ~0;
1351 } else {
1352 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1353 mc_filter[1] = mc_filter[0] = 0;
1354 for (i = 0; i < mc_count; i++) {
1355 if (!mclist)
1356 break;
1357 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1358
1359 bit_nr &= 0x3F;
1360 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1361 mclist = mclist->next;
1362 }
1363 }
1364
1365 ADM8211_IDLE_RX();
1366
1367 ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1368 ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1369 ADM8211_CSR_READ(NAR);
1370
1371 if (priv->nar & ADM8211_NAR_PR)
1372 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1373 else
1374 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1375
1376 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1377 adm8211_set_bssid(dev, bcast);
1378 else
1379 adm8211_set_bssid(dev, priv->bssid);
1380
1381 ADM8211_RESTORE();
1382
1383 *total_flags = new_flags;
1384}
1385
cc0b88cf
MW		 1386static int adm8211_add_interface(struct ieee80211_hw *dev,
1387 struct ieee80211_if_init_conf *conf)
1388{
1389 struct adm8211_priv *priv = dev->priv;
05c914fe 1390 if (priv->mode != NL80211_IFTYPE_MONITOR)
4150c572 1391 return -EOPNOTSUPP;
cc0b88cf
MW		 1392
1393 switch (conf->type) {
05c914fe 1394 case NL80211_IFTYPE_STATION:
cc0b88cf
MW		 1395 priv->mode = conf->type;
1396 break;
1397 default:
1398 return -EOPNOTSUPP;
1399 }
1400
4150c572
JB		 1401 ADM8211_IDLE();
1402
fb9bc28f
MW		 1403 ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)conf->mac_addr));
1404 ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
4150c572
JB		 1405
1406 adm8211_update_mode(dev);
1407
1408 ADM8211_RESTORE();
cc0b88cf
MW		 1409
1410 return 0;
1411}
1412
1413static void adm8211_remove_interface(struct ieee80211_hw *dev,
1414 struct ieee80211_if_init_conf *conf)
1415{
1416 struct adm8211_priv *priv = dev->priv;
05c914fe 1417 priv->mode = NL80211_IFTYPE_MONITOR;
cc0b88cf
MW		 1418}
1419
1420static int adm8211_init_rings(struct ieee80211_hw *dev)
1421{
1422 struct adm8211_priv *priv = dev->priv;
1423 struct adm8211_desc *desc = NULL;
1424 struct adm8211_rx_ring_info *rx_info;
1425 struct adm8211_tx_ring_info *tx_info;
1426 unsigned int i;
1427
1428 for (i = 0; i < priv->rx_ring_size; i++) {
1429 desc = &priv->rx_ring[i];
1430 desc->status = 0;
1431 desc->length = cpu_to_le32(RX_PKT_SIZE);
1432 priv->rx_buffers[i].skb = NULL;
1433 }
1434 /* Mark the end of RX ring; hw returns to base address after this
1435 * descriptor */
1436 desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1437
1438 for (i = 0; i < priv->rx_ring_size; i++) {
1439 desc = &priv->rx_ring[i];
1440 rx_info = &priv->rx_buffers[i];
1441
1442 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1443 if (rx_info->skb == NULL)
1444 break;
1445 rx_info->mapping = pci_map_single(priv->pdev,
1446 skb_tail_pointer(rx_info->skb),
1447 RX_PKT_SIZE,
1448 PCI_DMA_FROMDEVICE);
1449 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1450 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1451 }
1452
1453 /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1454 for (i = 0; i < priv->tx_ring_size; i++) {
1455 desc = &priv->tx_ring[i];
1456 tx_info = &priv->tx_buffers[i];
1457
1458 tx_info->skb = NULL;
1459 tx_info->mapping = 0;
1460 desc->status = 0;
1461 }
1462 desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1463
1464 priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1465 ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1466 ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1467
1468 return 0;
1469}
1470
1471static void adm8211_free_rings(struct ieee80211_hw *dev)
1472{
1473 struct adm8211_priv *priv = dev->priv;
1474 unsigned int i;
1475
1476 for (i = 0; i < priv->rx_ring_size; i++) {
1477 if (!priv->rx_buffers[i].skb)
1478 continue;
1479
1480 pci_unmap_single(
1481 priv->pdev,
1482 priv->rx_buffers[i].mapping,
1483 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1484
1485 dev_kfree_skb(priv->rx_buffers[i].skb);
1486 }
1487
1488 for (i = 0; i < priv->tx_ring_size; i++) {
1489 if (!priv->tx_buffers[i].skb)
1490 continue;
1491
1492 pci_unmap_single(priv->pdev,
1493 priv->tx_buffers[i].mapping,
1494 priv->tx_buffers[i].skb->len,
1495 PCI_DMA_TODEVICE);
1496
1497 dev_kfree_skb(priv->tx_buffers[i].skb);
1498 }
1499}
1500
4150c572 1501static int adm8211_start(struct ieee80211_hw *dev)
cc0b88cf
MW		 1502{
1503 struct adm8211_priv *priv = dev->priv;
1504 int retval;
1505
1506 /* Power up MAC and RF chips */
1507 retval = adm8211_hw_reset(dev);
1508 if (retval) {
1509 printk(KERN_ERR "%s: hardware reset failed\n",
1510 wiphy_name(dev->wiphy));
1511 goto fail;
1512 }
1513
1514 retval = adm8211_init_rings(dev);
1515 if (retval) {
1516 printk(KERN_ERR "%s: failed to initialize rings\n",
1517 wiphy_name(dev->wiphy));
1518 goto fail;
1519 }
1520
1521 /* Init hardware */
1522 adm8211_hw_init(dev);
1523 adm8211_rf_set_channel(dev, priv->channel);
1524
1525 retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
1526 IRQF_SHARED, "adm8211", dev);
1527 if (retval) {
1528 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1529 wiphy_name(dev->wiphy));
1530 goto fail;
1531 }
1532
1533 ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1534 ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1535 ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
05c914fe 1536 priv->mode = NL80211_IFTYPE_MONITOR;
cc0b88cf
MW		 1537 adm8211_update_mode(dev);
1538 ADM8211_CSR_WRITE(RDR, 0);
1539
1540 adm8211_set_interval(dev, 100, 10);
1541 return 0;
1542
1543fail:
1544 return retval;
1545}
1546
4150c572 1547static void adm8211_stop(struct ieee80211_hw *dev)
cc0b88cf
MW		 1548{
1549 struct adm8211_priv *priv = dev->priv;
1550
05c914fe 1551 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
cc0b88cf
MW		 1552 priv->nar = 0;
1553 ADM8211_CSR_WRITE(NAR, 0);
1554 ADM8211_CSR_WRITE(IER, 0);
1555 ADM8211_CSR_READ(NAR);
1556
1557 free_irq(priv->pdev->irq, dev);
1558
1559 adm8211_free_rings(dev);
cc0b88cf
MW		 1560}
1561
1562static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1563 int plcp_signal, int short_preamble)
1564{
1565 /* Alternative calculation from NetBSD: */
1566
1567/* IEEE 802.11b durations for DSSS PHY in microseconds */
1568#define IEEE80211_DUR_DS_LONG_PREAMBLE 144
1569#define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1570#define IEEE80211_DUR_DS_FAST_PLCPHDR 24
1571#define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
1572#define IEEE80211_DUR_DS_SLOW_ACK 112
1573#define IEEE80211_DUR_DS_FAST_ACK 56
1574#define IEEE80211_DUR_DS_SLOW_CTS 112
1575#define IEEE80211_DUR_DS_FAST_CTS 56
1576#define IEEE80211_DUR_DS_SLOT 20
1577#define IEEE80211_DUR_DS_SIFS 10
1578
1579 int remainder;
1580
1581 *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1582 / plcp_signal;
1583
1584 if (plcp_signal <= PLCP_SIGNAL_2M)
1585 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1586 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1587 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1588 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1589 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1590 else
1591 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1592 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1593 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1594 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1595 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1596
1597 /* lengthen duration if long preamble */
1598 if (!short_preamble)
1599 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1600 IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1601 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1602 IEEE80211_DUR_DS_FAST_PLCPHDR);
1603
1604
1605 *plcp = (80 * len) / plcp_signal;
1606 remainder = (80 * len) % plcp_signal;
1607 if (plcp_signal == PLCP_SIGNAL_11M &&
1608 remainder <= 30 && remainder > 0)
1609 *plcp = (*plcp | 0x8000) + 1;
1610 else if (remainder)
1611 (*plcp)++;
1612}
1613
1614/* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1615static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1616 u16 plcp_signal,
cc0b88cf
MW		 1617 size_t hdrlen)
1618{
1619 struct adm8211_priv *priv = dev->priv;
1620 unsigned long flags;
1621 dma_addr_t mapping;
1622 unsigned int entry;
1623 u32 flag;
1624
1625 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1626 PCI_DMA_TODEVICE);
1627
1628 spin_lock_irqsave(&priv->lock, flags);
1629
1630 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1631 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1632 else
1633 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1634
1635 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1636 ieee80211_stop_queue(dev, 0);
1637
1638 entry = priv->cur_tx % priv->tx_ring_size;
1639
1640 priv->tx_buffers[entry].skb = skb;
1641 priv->tx_buffers[entry].mapping = mapping;
cc0b88cf
MW		 1642 priv->tx_buffers[entry].hdrlen = hdrlen;
1643 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1644
1645 if (entry == priv->tx_ring_size - 1)
1646 flag |= TDES1_CONTROL_TER;
1647 priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1648
1649 /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1650 flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1651 priv->tx_ring[entry].status = cpu_to_le32(flag);
1652
1653 priv->cur_tx++;
1654
1655 spin_unlock_irqrestore(&priv->lock, flags);
1656
1657 /* Trigger transmit poll */
1658 ADM8211_CSR_WRITE(TDR, 0);
1659}
1660
1661/* Put adm8211_tx_hdr on skb and transmit */
e039fa4a 1662static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
cc0b88cf
MW		 1663{
1664 struct adm8211_tx_hdr *txhdr;
cc0b88cf
MW		 1665 size_t payload_len, hdrlen;
1666 int plcp, dur, len, plcp_signal, short_preamble;
1667 struct ieee80211_hdr *hdr;
e039fa4a
JB		 1668 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1669 struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
e6a9854b 1670 u8 rc_flags;
cc0b88cf 1671
e6a9854b
JB		 1672 rc_flags = info->control.rates[0].flags;
1673 short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
2e92e6f2 1674 plcp_signal = txrate->bitrate;
cc0b88cf
MW		 1675
1676 hdr = (struct ieee80211_hdr *)skb->data;
316af76f 1677 hdrlen = ieee80211_hdrlen(hdr->frame_control);
cc0b88cf
MW		 1678 memcpy(skb->cb, skb->data, hdrlen);
1679 hdr = (struct ieee80211_hdr *)skb->cb;
1680 skb_pull(skb, hdrlen);
1681 payload_len = skb->len;
1682
1683 txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1684 memset(txhdr, 0, sizeof(*txhdr));
1685 memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1686 txhdr->signal = plcp_signal;
1687 txhdr->frame_body_size = cpu_to_le16(payload_len);
1688 txhdr->frame_control = hdr->frame_control;
1689
1690 len = hdrlen + payload_len + FCS_LEN;
cc0b88cf
MW		 1691
1692 txhdr->frag = cpu_to_le16(0x0FFF);
1693 adm8211_calc_durations(&dur, &plcp, payload_len,
1694 len, plcp_signal, short_preamble);
1695 txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1696 txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1697 txhdr->dur_frag_head = cpu_to_le16(dur);
1698 txhdr->dur_frag_tail = cpu_to_le16(dur);
1699
1700 txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1701
1702 if (short_preamble)
1703 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1704
e6a9854b 1705 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
cc0b88cf
MW		 1706 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1707
e6a9854b 1708 txhdr->retry_limit = info->control.rates[0].count;
cc0b88cf 1709
e039fa4a 1710 adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
cc0b88cf
MW		 1711
1712 return NETDEV_TX_OK;
1713}
1714
1715static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1716{
1717 struct adm8211_priv *priv = dev->priv;
1718 unsigned int ring_size;
1719
1720 priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1721 sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1722 if (!priv->rx_buffers)
1723 return -ENOMEM;
1724
1725 priv->tx_buffers = (void *)priv->rx_buffers +
1726 sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1727
1728 /* Allocate TX/RX descriptors */
1729 ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1730 sizeof(struct adm8211_desc) * priv->tx_ring_size;
1731 priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1732 &priv->rx_ring_dma);
1733
1734 if (!priv->rx_ring) {
1735 kfree(priv->rx_buffers);
1736 priv->rx_buffers = NULL;
1737 priv->tx_buffers = NULL;
1738 return -ENOMEM;
1739 }
1740
1741 priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1742 priv->rx_ring_size);
1743 priv->tx_ring_dma = priv->rx_ring_dma +
1744 sizeof(struct adm8211_desc) * priv->rx_ring_size;
1745
1746 return 0;
1747}
1748
1749static const struct ieee80211_ops adm8211_ops = {
1750 .tx = adm8211_tx,
4150c572 1751 .start = adm8211_start,
cc0b88cf
MW		 1752 .stop = adm8211_stop,
1753 .add_interface = adm8211_add_interface,
1754 .remove_interface = adm8211_remove_interface,
1755 .config = adm8211_config,
1756 .config_interface = adm8211_config_interface,
4150c572 1757 .configure_filter = adm8211_configure_filter,
cc0b88cf
MW		 1758 .get_stats = adm8211_get_stats,
1759 .get_tx_stats = adm8211_get_tx_stats,
1760 .get_tsf = adm8211_get_tsft
1761};
1762
1763static int __devinit adm8211_probe(struct pci_dev *pdev,
1764 const struct pci_device_id *id)
1765{
1766 struct ieee80211_hw *dev;
1767 struct adm8211_priv *priv;
1768 unsigned long mem_addr, mem_len;
1769 unsigned int io_addr, io_len;
1770 int err;
1771 u32 reg;
1772 u8 perm_addr[ETH_ALEN];
1773
cc0b88cf
MW		 1774 err = pci_enable_device(pdev);
1775 if (err) {
1776 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1777 pci_name(pdev));
1778 return err;
1779 }
1780
1781 io_addr = pci_resource_start(pdev, 0);
1782 io_len = pci_resource_len(pdev, 0);
1783 mem_addr = pci_resource_start(pdev, 1);
1784 mem_len = pci_resource_len(pdev, 1);
1785 if (io_len < 256 || mem_len < 1024) {
1786 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1787 pci_name(pdev));
1788 goto err_disable_pdev;
1789 }
1790
1791
1792 /* check signature */
1793 pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1794 if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1795 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1796 pci_name(pdev), reg);
1797 goto err_disable_pdev;
1798 }
1799
1800 err = pci_request_regions(pdev, "adm8211");
1801 if (err) {
1802 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1803 pci_name(pdev));
1804 return err; /* someone else grabbed it? don't disable it */
1805 }
1806
284901a9
YH		 1807 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
1808 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
cc0b88cf
MW		 1809 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1810 pci_name(pdev));
1811 goto err_free_reg;
1812 }
1813
1814 pci_set_master(pdev);
1815
1816 dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1817 if (!dev) {
1818 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1819 pci_name(pdev));
1820 err = -ENOMEM;
1821 goto err_free_reg;
1822 }
1823 priv = dev->priv;
1824 priv->pdev = pdev;
1825
1826 spin_lock_init(&priv->lock);
1827
1828 SET_IEEE80211_DEV(dev, &pdev->dev);
1829
1830 pci_set_drvdata(pdev, dev);
1831
1832 priv->map = pci_iomap(pdev, 1, mem_len);
1833 if (!priv->map)
1834 priv->map = pci_iomap(pdev, 0, io_len);
1835
1836 if (!priv->map) {
1837 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1838 pci_name(pdev));
1839 goto err_free_dev;
1840 }
1841
1842 priv->rx_ring_size = rx_ring_size;
1843 priv->tx_ring_size = tx_ring_size;
1844
1845 if (adm8211_alloc_rings(dev)) {
1846 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1847 pci_name(pdev));
1848 goto err_iounmap;
1849 }
1850
0e5ce1f3
AV		 1851 *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1852 *(__le16 *)&perm_addr[4] =
1853 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
cc0b88cf
MW		 1854
1855 if (!is_valid_ether_addr(perm_addr)) {
1856 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1857 pci_name(pdev));
1858 random_ether_addr(perm_addr);
1859 }
1860 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1861
1862 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
8318d78a 1863 /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
566bfe5a 1864 dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
f59ac048 1865 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
cc0b88cf
MW		 1866
1867 dev->channel_change_time = 1000;
566bfe5a 1868 dev->max_signal = 100; /* FIXME: find better value */
cc0b88cf 1869
cc0b88cf
MW		 1870 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1871
1872 priv->retry_limit = 3;
1873 priv->ant_power = 0x40;
1874 priv->tx_power = 0x40;
1875 priv->lpf_cutoff = 0xFF;
1876 priv->lnags_threshold = 0xFF;
05c914fe 1877 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
cc0b88cf
MW		 1878
1879 /* Power-on issue. EEPROM won't read correctly without */
f6ac0adf 1880 if (pdev->revision >= ADM8211_REV_BA) {
cc0b88cf
MW		 1881 ADM8211_CSR_WRITE(FRCTL, 0);
1882 ADM8211_CSR_READ(FRCTL);
1883 ADM8211_CSR_WRITE(FRCTL, 1);
1884 ADM8211_CSR_READ(FRCTL);
1885 msleep(100);
1886 }
1887
1888 err = adm8211_read_eeprom(dev);
1889 if (err) {
1890 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1891 pci_name(pdev));
1892 goto err_free_desc;
1893 }
1894
8318d78a 1895 priv->channel = 1;
cc0b88cf 1896
9a89c839
JB		 1897 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1898
cc0b88cf
MW		 1899 err = ieee80211_register_hw(dev);
1900 if (err) {
1901 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1902 pci_name(pdev));
1903 goto err_free_desc;
1904 }
1905
e174961c
JB		 1906 printk(KERN_INFO "%s: hwaddr %pM, Rev 0x%02x\n",
1907 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
f6ac0adf 1908 pdev->revision);
cc0b88cf
MW		 1909
1910 return 0;
1911
1912 err_free_desc:
1913 pci_free_consistent(pdev,
1914 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1915 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1916 priv->rx_ring, priv->rx_ring_dma);
1917 kfree(priv->rx_buffers);
1918
1919 err_iounmap:
1920 pci_iounmap(pdev, priv->map);
1921
1922 err_free_dev:
1923 pci_set_drvdata(pdev, NULL);
1924 ieee80211_free_hw(dev);
1925
1926 err_free_reg:
1927 pci_release_regions(pdev);
1928
1929 err_disable_pdev:
1930 pci_disable_device(pdev);
1931 return err;
1932}
1933
1934
1935static void __devexit adm8211_remove(struct pci_dev *pdev)
1936{
1937 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1938 struct adm8211_priv *priv;
1939
1940 if (!dev)
1941 return;
1942
1943 ieee80211_unregister_hw(dev);
1944
1945 priv = dev->priv;
1946
1947 pci_free_consistent(pdev,
1948 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1949 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1950 priv->rx_ring, priv->rx_ring_dma);
1951
1952 kfree(priv->rx_buffers);
1953 kfree(priv->eeprom);
1954 pci_iounmap(pdev, priv->map);
1955 pci_release_regions(pdev);
1956 pci_disable_device(pdev);
1957 ieee80211_free_hw(dev);
1958}
1959
1960
1961#ifdef CONFIG_PM
1962static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1963{
1964 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1965 struct adm8211_priv *priv = dev->priv;
1966
05c914fe 1967 if (priv->mode != NL80211_IFTYPE_UNSPECIFIED) {
cc0b88cf
MW		 1968 ieee80211_stop_queues(dev);
1969 adm8211_stop(dev);
1970 }
1971
1972 pci_save_state(pdev);
1973 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1974 return 0;
1975}
1976
1977static int adm8211_resume(struct pci_dev *pdev)
1978{
1979 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1980 struct adm8211_priv *priv = dev->priv;
1981
1982 pci_set_power_state(pdev, PCI_D0);
1983 pci_restore_state(pdev);
1984
05c914fe 1985 if (priv->mode != NL80211_IFTYPE_UNSPECIFIED) {
4150c572 1986 adm8211_start(dev);
36d6825b 1987 ieee80211_wake_queues(dev);
cc0b88cf
MW		 1988 }
1989
1990 return 0;
1991}
1992#endif /* CONFIG_PM */
1993
1994
1995MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
1996
1997/* TODO: implement enable_wake */
1998static struct pci_driver adm8211_driver = {
1999 .name = "adm8211",
2000 .id_table = adm8211_pci_id_table,
2001 .probe = adm8211_probe,
2002 .remove = __devexit_p(adm8211_remove),
2003#ifdef CONFIG_PM
2004 .suspend = adm8211_suspend,
2005 .resume = adm8211_resume,
2006#endif /* CONFIG_PM */
2007};
2008
2009
2010
2011static int __init adm8211_init(void)
2012{
cc0b88cf
MW		 2013 return pci_register_driver(&adm8211_driver);
2014}
2015
2016
2017static void __exit adm8211_exit(void)
2018{
2019 pci_unregister_driver(&adm8211_driver);
2020}
2021
2022
2023module_init(adm8211_init);
2024module_exit(adm8211_exit);
Linux kernel - Deliverables
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