Commit | Line | Data |
---|---|---|
d15dd3e5 LR |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH_H | |
18 | #define ATH_H | |
19 | ||
f1d267ca | 20 | #include <linux/etherdevice.h> |
d15dd3e5 | 21 | #include <linux/skbuff.h> |
bcd8f54a | 22 | #include <linux/if_ether.h> |
b5bfc568 | 23 | #include <linux/spinlock.h> |
b002a4a9 | 24 | #include <net/mac80211.h> |
d15dd3e5 | 25 | |
7e86c104 LR |
26 | /* |
27 | * The key cache is used for h/w cipher state and also for | |
28 | * tracking station state such as the current tx antenna. | |
29 | * We also setup a mapping table between key cache slot indices | |
30 | * and station state to short-circuit node lookups on rx. | |
31 | * Different parts have different size key caches. We handle | |
32 | * up to ATH_KEYMAX entries (could dynamically allocate state). | |
33 | */ | |
34 | #define ATH_KEYMAX 128 /* max key cache size we handle */ | |
35 | ||
17753748 LR |
36 | static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; |
37 | ||
3d536acf LR |
38 | struct ath_ani { |
39 | bool caldone; | |
3d536acf LR |
40 | unsigned int longcal_timer; |
41 | unsigned int shortcal_timer; | |
42 | unsigned int resetcal_timer; | |
43 | unsigned int checkani_timer; | |
44 | struct timer_list timer; | |
45 | }; | |
46 | ||
b5bfc568 FF |
47 | struct ath_cycle_counters { |
48 | u32 cycles; | |
49 | u32 rx_busy; | |
50 | u32 rx_frame; | |
51 | u32 tx_frame; | |
52 | }; | |
53 | ||
211f5859 LR |
54 | enum ath_device_state { |
55 | ATH_HW_UNAVAILABLE, | |
56 | ATH_HW_INITIALIZED, | |
57 | }; | |
58 | ||
497ad9ad S |
59 | enum ath_bus_type { |
60 | ATH_PCI, | |
61 | ATH_AHB, | |
62 | ATH_USB, | |
63 | }; | |
64 | ||
608b88cb | 65 | struct reg_dmn_pair_mapping { |
ef8c0017 | 66 | u16 reg_domain; |
608b88cb LR |
67 | u16 reg_5ghz_ctl; |
68 | u16 reg_2ghz_ctl; | |
69 | }; | |
70 | ||
71 | struct ath_regulatory { | |
72 | char alpha2[2]; | |
73 | u16 country_code; | |
74 | u16 max_power_level; | |
608b88cb | 75 | u16 current_rd; |
608b88cb LR |
76 | int16_t power_limit; |
77 | struct reg_dmn_pair_mapping *regpair; | |
78 | }; | |
79 | ||
34a13051 | 80 | enum ath_crypt_caps { |
ce2220d1 BR |
81 | ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), |
82 | ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), | |
34a13051 BR |
83 | }; |
84 | ||
1bba5b73 BR |
85 | struct ath_keyval { |
86 | u8 kv_type; | |
87 | u8 kv_pad; | |
88 | u16 kv_len; | |
89 | u8 kv_val[16]; /* TK */ | |
90 | u8 kv_mic[8]; /* Michael MIC key */ | |
91 | u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware | |
92 | * supports both MIC keys in the same key cache entry; | |
93 | * in that case, kv_mic is the RX key) */ | |
94 | }; | |
95 | ||
96 | enum ath_cipher { | |
97 | ATH_CIPHER_WEP = 0, | |
98 | ATH_CIPHER_AES_OCB = 1, | |
99 | ATH_CIPHER_AES_CCM = 2, | |
100 | ATH_CIPHER_CKIP = 3, | |
101 | ATH_CIPHER_TKIP = 4, | |
102 | ATH_CIPHER_CLR = 5, | |
103 | ATH_CIPHER_MIC = 127 | |
104 | }; | |
105 | ||
50f56316 S |
106 | /** |
107 | * struct ath_ops - Register read/write operations | |
108 | * | |
109 | * @read: Register read | |
09a525d3 | 110 | * @multi_read: Multiple register read |
50f56316 S |
111 | * @write: Register write |
112 | * @enable_write_buffer: Enable multiple register writes | |
435c1610 | 113 | * @write_flush: flush buffered register writes and disable buffering |
50f56316 | 114 | */ |
9e4bffd2 LR |
115 | struct ath_ops { |
116 | unsigned int (*read)(void *, u32 reg_offset); | |
09a525d3 | 117 | void (*multi_read)(void *, u32 *addr, u32 *val, u16 count); |
50f56316 S |
118 | void (*write)(void *, u32 val, u32 reg_offset); |
119 | void (*enable_write_buffer)(void *); | |
50f56316 | 120 | void (*write_flush) (void *); |
845e03c9 | 121 | u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); |
9e4bffd2 LR |
122 | }; |
123 | ||
5bb12791 | 124 | struct ath_common; |
0cb9e06b | 125 | struct ath_bus_ops; |
5bb12791 | 126 | |
d15dd3e5 | 127 | struct ath_common { |
13b81559 | 128 | void *ah; |
bc974f4a | 129 | void *priv; |
b002a4a9 | 130 | struct ieee80211_hw *hw; |
c46917bb | 131 | int debug_mask; |
211f5859 | 132 | enum ath_device_state state; |
c46917bb | 133 | |
3d536acf LR |
134 | struct ath_ani ani; |
135 | ||
d15dd3e5 | 136 | u16 cachelsz; |
1510718d LR |
137 | u16 curaid; |
138 | u8 macaddr[ETH_ALEN]; | |
139 | u8 curbssid[ETH_ALEN]; | |
140 | u8 bssidmask[ETH_ALEN]; | |
c46917bb | 141 | |
cc861f74 LR |
142 | u32 rx_bufsize; |
143 | ||
7e86c104 LR |
144 | u32 keymax; |
145 | DECLARE_BITMAP(keymap, ATH_KEYMAX); | |
56363dde | 146 | DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); |
bed3d9c0 | 147 | DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX); |
34a13051 | 148 | enum ath_crypt_caps crypt_caps; |
7e86c104 | 149 | |
dfdac8ac FF |
150 | unsigned int clockrate; |
151 | ||
b5bfc568 FF |
152 | spinlock_t cc_lock; |
153 | struct ath_cycle_counters cc_ani; | |
154 | struct ath_cycle_counters cc_survey; | |
155 | ||
608b88cb | 156 | struct ath_regulatory regulatory; |
de1c732b | 157 | struct ath_regulatory reg_world_copy; |
9adca126 | 158 | const struct ath_ops *ops; |
5bb12791 | 159 | const struct ath_bus_ops *bus_ops; |
8f5dcb1c VT |
160 | |
161 | bool btcoex_enabled; | |
05c0be2f | 162 | bool disable_ani; |
63081305 | 163 | bool bt_ant_diversity; |
2f2cb326 OR |
164 | |
165 | int last_rssi; | |
d15dd3e5 LR |
166 | }; |
167 | ||
168 | struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, | |
169 | u32 len, | |
170 | gfp_t gfp_mask); | |
f1d267ca | 171 | bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr); |
d15dd3e5 | 172 | |
13b81559 | 173 | void ath_hw_setbssidmask(struct ath_common *common); |
1bba5b73 BR |
174 | void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key); |
175 | int ath_key_config(struct ath_common *common, | |
176 | struct ieee80211_vif *vif, | |
177 | struct ieee80211_sta *sta, | |
178 | struct ieee80211_key_conf *key); | |
179 | bool ath_hw_keyreset(struct ath_common *common, u16 entry); | |
b5bfc568 FF |
180 | void ath_hw_cycle_counters_update(struct ath_common *common); |
181 | int32_t ath_hw_get_listen_time(struct ath_common *common); | |
13b81559 | 182 | |
98b36a02 BG |
183 | __printf(3, 4) |
184 | void ath_printk(const char *level, const struct ath_common *common, | |
185 | const char *fmt, ...); | |
21a99f93 JP |
186 | |
187 | #define ath_emerg(common, fmt, ...) \ | |
98b36a02 | 188 | ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__) |
21a99f93 | 189 | #define ath_alert(common, fmt, ...) \ |
98b36a02 | 190 | ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__) |
21a99f93 | 191 | #define ath_crit(common, fmt, ...) \ |
98b36a02 | 192 | ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__) |
21a99f93 | 193 | #define ath_err(common, fmt, ...) \ |
98b36a02 | 194 | ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__) |
21a99f93 | 195 | #define ath_warn(common, fmt, ...) \ |
98b36a02 | 196 | ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__) |
21a99f93 | 197 | #define ath_notice(common, fmt, ...) \ |
98b36a02 | 198 | ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__) |
21a99f93 | 199 | #define ath_info(common, fmt, ...) \ |
98b36a02 | 200 | ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__) |
21a99f93 JP |
201 | |
202 | /** | |
203 | * enum ath_debug_level - atheros wireless debug level | |
204 | * | |
205 | * @ATH_DBG_RESET: reset processing | |
206 | * @ATH_DBG_QUEUE: hardware queue management | |
207 | * @ATH_DBG_EEPROM: eeprom processing | |
208 | * @ATH_DBG_CALIBRATE: periodic calibration | |
209 | * @ATH_DBG_INTERRUPT: interrupt processing | |
210 | * @ATH_DBG_REGULATORY: regulatory processing | |
211 | * @ATH_DBG_ANI: adaptive noise immunitive processing | |
212 | * @ATH_DBG_XMIT: basic xmit operation | |
213 | * @ATH_DBG_BEACON: beacon handling | |
214 | * @ATH_DBG_CONFIG: configuration of the hardware | |
215 | * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT | |
216 | * @ATH_DBG_PS: power save processing | |
217 | * @ATH_DBG_HWTIMER: hardware timer handling | |
218 | * @ATH_DBG_BTCOEX: bluetooth coexistance | |
219 | * @ATH_DBG_BSTUCK: stuck beacons | |
55e435de LR |
220 | * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol |
221 | * used exclusively for WLAN-BT coexistence starting from | |
222 | * AR9462. | |
9b203c8f | 223 | * @ATH_DBG_DFS: radar datection |
b3ba6c52 | 224 | * @ATH_DBG_WOW: Wake on Wireless |
21a99f93 JP |
225 | * @ATH_DBG_ANY: enable all debugging |
226 | * | |
227 | * The debug level is used to control the amount and type of debugging output | |
228 | * we want to see. Each driver has its own method for enabling debugging and | |
229 | * modifying debug level states -- but this is typically done through a | |
230 | * module parameter 'debug' along with a respective 'debug' debugfs file | |
231 | * entry. | |
232 | */ | |
233 | enum ATH_DEBUG { | |
234 | ATH_DBG_RESET = 0x00000001, | |
235 | ATH_DBG_QUEUE = 0x00000002, | |
236 | ATH_DBG_EEPROM = 0x00000004, | |
237 | ATH_DBG_CALIBRATE = 0x00000008, | |
238 | ATH_DBG_INTERRUPT = 0x00000010, | |
239 | ATH_DBG_REGULATORY = 0x00000020, | |
240 | ATH_DBG_ANI = 0x00000040, | |
241 | ATH_DBG_XMIT = 0x00000080, | |
242 | ATH_DBG_BEACON = 0x00000100, | |
243 | ATH_DBG_CONFIG = 0x00000200, | |
244 | ATH_DBG_FATAL = 0x00000400, | |
245 | ATH_DBG_PS = 0x00000800, | |
14335310 SM |
246 | ATH_DBG_BTCOEX = 0x00001000, |
247 | ATH_DBG_WMI = 0x00002000, | |
248 | ATH_DBG_BSTUCK = 0x00004000, | |
249 | ATH_DBG_MCI = 0x00008000, | |
250 | ATH_DBG_DFS = 0x00010000, | |
251 | ATH_DBG_WOW = 0x00020000, | |
21a99f93 JP |
252 | ATH_DBG_ANY = 0xffffffff |
253 | }; | |
254 | ||
255 | #define ATH_DBG_DEFAULT (ATH_DBG_FATAL) | |
256 | ||
257 | #ifdef CONFIG_ATH_DEBUG | |
258 | ||
7b8112d6 JP |
259 | #define ath_dbg(common, dbg_mask, fmt, ...) \ |
260 | do { \ | |
d2182b69 | 261 | if ((common)->debug_mask & ATH_DBG_##dbg_mask) \ |
98b36a02 | 262 | ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ |
7b8112d6 JP |
263 | } while (0) |
264 | ||
21a99f93 | 265 | #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg) |
d7fd1b50 | 266 | #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo) |
21a99f93 JP |
267 | |
268 | #else | |
269 | ||
b9075fa9 | 270 | static inline __attribute__ ((format (printf, 3, 4))) |
d2182b69 | 271 | void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, |
7b8112d6 | 272 | const char *fmt, ...) |
21a99f93 | 273 | { |
21a99f93 | 274 | } |
d2182b69 JP |
275 | #define ath_dbg(common, dbg_mask, fmt, ...) \ |
276 | _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__) | |
277 | ||
21a99f93 | 278 | #define ATH_DBG_WARN(foo, arg...) do {} while (0) |
b7613370 JL |
279 | #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ |
280 | int __ret_warn_once = !!(foo); \ | |
281 | unlikely(__ret_warn_once); \ | |
282 | }) | |
21a99f93 JP |
283 | |
284 | #endif /* CONFIG_ATH_DEBUG */ | |
285 | ||
286 | /** Returns string describing opmode, or NULL if unknown mode. */ | |
287 | #ifdef CONFIG_ATH_DEBUG | |
288 | const char *ath_opmode_to_string(enum nl80211_iftype opmode); | |
289 | #else | |
290 | static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode) | |
291 | { | |
292 | return "UNKNOWN"; | |
293 | } | |
294 | #endif | |
295 | ||
d15dd3e5 | 296 | #endif /* ATH_H */ |