[deliverable/linux.git] / drivers / net / wireless / ath / ath.h

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef ATH_H
#define ATH_H

#include <linux/skbuff.h>
#include <linux/if_ether.h>
#include <net/mac80211.h>

/*
 * The key cache is used for h/w cipher state and also for
 * tracking station state such as the current tx antenna.
 * We also setup a mapping table between key cache slot indices
 * and station state to short-circuit node lookups on rx.
 * Different parts have different size key caches.  We handle
 * up to ATH_KEYMAX entries (could dynamically allocate state).
 */
#define	ATH_KEYMAX	        128     /* max key cache size we handle */

static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};

struct ath_ani {
	bool caldone;
	int16_t noise_floor;
	unsigned int longcal_timer;
	unsigned int shortcal_timer;
	unsigned int resetcal_timer;
	unsigned int checkani_timer;
	struct timer_list timer;
};

enum ath_device_state {
	ATH_HW_UNAVAILABLE,
	ATH_HW_INITIALIZED,
};

enum ath_bus_type {
	ATH_PCI,
	ATH_AHB,
	ATH_USB,
};

struct reg_dmn_pair_mapping {
	u16 regDmnEnum;
	u16 reg_5ghz_ctl;
	u16 reg_2ghz_ctl;
};

struct ath_regulatory {
	char alpha2[2];
	u16 country_code;
	u16 max_power_level;
	u32 tp_scale;
	u16 current_rd;
	u16 current_rd_ext;
	int16_t power_limit;
	struct reg_dmn_pair_mapping *regpair;
};

enum ath_crypt_caps {
	ATH_CRYPT_CAP_MIC_AESCCM		= BIT(0),
	ATH_CRYPT_CAP_MIC_CKIP			= BIT(1),
	ATH_CRYPT_CAP_MIC_TKIP			= BIT(2),
	ATH_CRYPT_CAP_CIPHER_AESCCM		= BIT(3),
	ATH_CRYPT_CAP_CIPHER_CKIP		= BIT(4),
	ATH_CRYPT_CAP_CIPHER_TKIP		= BIT(5),
};

/**
 * struct ath_ops - Register read/write operations
 *
 * @read: Register read
 * @write: Register write
 * @enable_write_buffer: Enable multiple register writes
 * @disable_write_buffer: Disable multiple register writes
 * @write_flush: Flush buffered register writes
 */
struct ath_ops {
	unsigned int (*read)(void *, u32 reg_offset);
	void (*write)(void *, u32 val, u32 reg_offset);
	void (*enable_write_buffer)(void *);
	void (*disable_write_buffer)(void *);
	void (*write_flush) (void *);
};

struct ath_common;

struct ath_bus_ops {
	enum ath_bus_type ath_bus_type;
	void (*read_cachesize)(struct ath_common *common, int *csz);
	bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
	void (*bt_coex_prep)(struct ath_common *common);
};

struct ath_common {
	void *ah;
	void *priv;
	struct ieee80211_hw *hw;
	int debug_mask;
	enum ath_device_state state;

	struct ath_ani ani;

	u16 cachelsz;
	u16 curaid;
	u8 macaddr[ETH_ALEN];
	u8 curbssid[ETH_ALEN];
	u8 bssidmask[ETH_ALEN];

	u8 tx_chainmask;
	u8 rx_chainmask;

	u32 rx_bufsize;

	u32 keymax;
	DECLARE_BITMAP(keymap, ATH_KEYMAX);
	DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
	u8 splitmic;
	enum ath_crypt_caps crypt_caps;

	struct ath_regulatory regulatory;
	const struct ath_ops *ops;
	const struct ath_bus_ops *bus_ops;
};

struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
				u32 len,
				gfp_t gfp_mask);

void ath_hw_setbssidmask(struct ath_common *common);

#endif /* ATH_H */
Commit	Line	Data
d15dd3e5 LR	1	/*
	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef ATH_H
	18	#define ATH_H
	19
	20	#include <linux/skbuff.h>
bcd8f54a	21	#include <linux/if_ether.h>
b002a4a9	22	#include <net/mac80211.h>
d15dd3e5	23
7e86c104 LR	24	/*
	25	* The key cache is used for h/w cipher state and also for
	26	* tracking station state such as the current tx antenna.
	27	* We also setup a mapping table between key cache slot indices
	28	* and station state to short-circuit node lookups on rx.
	29	* Different parts have different size key caches. We handle
	30	* up to ATH_KEYMAX entries (could dynamically allocate state).
	31	*/
	32	#define ATH_KEYMAX 128 /* max key cache size we handle */
	33
17753748 LR	34	static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
17753748 LR	35
3d536acf LR	36	struct ath_ani {
	37	bool caldone;
	38	int16_t noise_floor;
	39	unsigned int longcal_timer;
	40	unsigned int shortcal_timer;
	41	unsigned int resetcal_timer;
	42	unsigned int checkani_timer;
	43	struct timer_list timer;
	44	};
	45
211f5859 LR	46	enum ath_device_state {
	47	ATH_HW_UNAVAILABLE,
	48	ATH_HW_INITIALIZED,
	49	};
	50
497ad9ad S	51	enum ath_bus_type {
	52	ATH_PCI,
	53	ATH_AHB,
	54	ATH_USB,
	55	};
	56
608b88cb LR	57	struct reg_dmn_pair_mapping {
	58	u16 regDmnEnum;
	59	u16 reg_5ghz_ctl;
	60	u16 reg_2ghz_ctl;
	61	};
	62
	63	struct ath_regulatory {
	64	char alpha2[2];
	65	u16 country_code;
	66	u16 max_power_level;
	67	u32 tp_scale;
	68	u16 current_rd;
	69	u16 current_rd_ext;
	70	int16_t power_limit;
	71	struct reg_dmn_pair_mapping *regpair;
	72	};
	73
34a13051 BR	74	enum ath_crypt_caps {
	75	ATH_CRYPT_CAP_MIC_AESCCM = BIT(0),
	76	ATH_CRYPT_CAP_MIC_CKIP = BIT(1),
	77	ATH_CRYPT_CAP_MIC_TKIP = BIT(2),
	78	ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(3),
	79	ATH_CRYPT_CAP_CIPHER_CKIP = BIT(4),
	80	ATH_CRYPT_CAP_CIPHER_TKIP = BIT(5),
	81	};
	82
50f56316 S	83	/**
	84	* struct ath_ops - Register read/write operations
	85	*
	86	* @read: Register read
	87	* @write: Register write
	88	* @enable_write_buffer: Enable multiple register writes
	89	* @disable_write_buffer: Disable multiple register writes
	90	* @write_flush: Flush buffered register writes
	91	*/
9e4bffd2 LR	92	struct ath_ops {
9e4bffd2 LR	93	unsigned int (read)(void , u32 reg_offset);
50f56316 S	94	void (write)(void , u32 val, u32 reg_offset);
	95	void (enable_write_buffer)(void );
	96	void (disable_write_buffer)(void );
	97	void (write_flush) (void );
9e4bffd2 LR	98	};
9e4bffd2 LR	99
5bb12791 LR	100	struct ath_common;
	101
	102	struct ath_bus_ops {
497ad9ad S	103	enum ath_bus_type ath_bus_type;
	104	void (read_cachesize)(struct ath_common common, int *csz);
	105	bool (eeprom_read)(struct ath_common common, u32 off, u16 *data);
	106	void (bt_coex_prep)(struct ath_common common);
5bb12791 LR	107	};
5bb12791 LR	108
d15dd3e5	109	struct ath_common {
13b81559	110	void *ah;
bc974f4a	111	void *priv;
b002a4a9	112	struct ieee80211_hw *hw;
c46917bb	113	int debug_mask;
211f5859	114	enum ath_device_state state;
c46917bb	115
3d536acf LR	116	struct ath_ani ani;
3d536acf LR	117
d15dd3e5	118	u16 cachelsz;
1510718d LR	119	u16 curaid;
	120	u8 macaddr[ETH_ALEN];
	121	u8 curbssid[ETH_ALEN];
	122	u8 bssidmask[ETH_ALEN];
c46917bb	123
43c27613 LR	124	u8 tx_chainmask;
	125	u8 rx_chainmask;
	126
cc861f74 LR	127	u32 rx_bufsize;
cc861f74 LR	128
7e86c104 LR	129	u32 keymax;
7e86c104 LR	130	DECLARE_BITMAP(keymap, ATH_KEYMAX);
56363dde	131	DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
7e86c104	132	u8 splitmic;
34a13051	133	enum ath_crypt_caps crypt_caps;
7e86c104	134
608b88cb	135	struct ath_regulatory regulatory;
9adca126	136	const struct ath_ops *ops;
5bb12791	137	const struct ath_bus_ops *bus_ops;
d15dd3e5 LR	138	};
	139
	140	struct sk_buff ath_rxbuf_alloc(struct ath_common common,
	141	u32 len,
	142	gfp_t gfp_mask);
	143
13b81559 LR	144	void ath_hw_setbssidmask(struct ath_common *common);
13b81559 LR	145
d15dd3e5	146	#endif /* ATH_H */