[deliverable/linux.git] / drivers / net / wireless / ath / ath.h

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef ATH_H
#define ATH_H

#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_ether.h>
#include <linux/spinlock.h>
#include <net/mac80211.h>

/*
 * The key cache is used for h/w cipher state and also for
 * tracking station state such as the current tx antenna.
 * We also setup a mapping table between key cache slot indices
 * and station state to short-circuit node lookups on rx.
 * Different parts have different size key caches.  We handle
 * up to ATH_KEYMAX entries (could dynamically allocate state).
 */
#define	ATH_KEYMAX	        128     /* max key cache size we handle */

static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};

struct ath_ani {
	bool caldone;
	unsigned int longcal_timer;
	unsigned int shortcal_timer;
	unsigned int resetcal_timer;
	unsigned int checkani_timer;
	struct timer_list timer;
};

struct ath_cycle_counters {
	u32 cycles;
	u32 rx_busy;
	u32 rx_frame;
	u32 tx_frame;
};

enum ath_device_state {
	ATH_HW_UNAVAILABLE,
	ATH_HW_INITIALIZED,
};

enum ath_op_flags {
	ATH_OP_INVALID,
	ATH_OP_BEACONS,
	ATH_OP_ANI_RUN,
	ATH_OP_PRIM_STA_VIF,
	ATH_OP_HW_RESET,
	ATH_OP_SCANNING,
	ATH_OP_MULTI_CHANNEL,
};

enum ath_bus_type {
	ATH_PCI,
	ATH_AHB,
	ATH_USB,
};

struct reg_dmn_pair_mapping {
	u16 reg_domain;
	u16 reg_5ghz_ctl;
	u16 reg_2ghz_ctl;
};

struct ath_regulatory {
	char alpha2[2];
	u16 country_code;
	u16 max_power_level;
	u16 current_rd;
	int16_t power_limit;
	struct reg_dmn_pair_mapping *regpair;
};

enum ath_crypt_caps {
	ATH_CRYPT_CAP_CIPHER_AESCCM		= BIT(0),
	ATH_CRYPT_CAP_MIC_COMBINED		= BIT(1),
};

struct ath_keyval {
	u8 kv_type;
	u8 kv_pad;
	u16 kv_len;
	u8 kv_val[16]; /* TK */
	u8 kv_mic[8]; /* Michael MIC key */
	u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
			 * supports both MIC keys in the same key cache entry;
			 * in that case, kv_mic is the RX key) */
};

enum ath_cipher {
	ATH_CIPHER_WEP = 0,
	ATH_CIPHER_AES_OCB = 1,
	ATH_CIPHER_AES_CCM = 2,
	ATH_CIPHER_CKIP = 3,
	ATH_CIPHER_TKIP = 4,
	ATH_CIPHER_CLR = 5,
	ATH_CIPHER_MIC = 127
};

/**
 * struct ath_ops - Register read/write operations
 *
 * @read: Register read
 * @multi_read: Multiple register read
 * @write: Register write
 * @enable_write_buffer: Enable multiple register writes
 * @write_flush: flush buffered register writes and disable buffering
 */
struct ath_ops {
	unsigned int (*read)(void *, u32 reg_offset);
	void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
	void (*write)(void *, u32 val, u32 reg_offset);
	void (*enable_write_buffer)(void *);
	void (*write_flush) (void *);
	u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
};

struct ath_common;
struct ath_bus_ops;

struct ath_common {
	void *ah;
	void *priv;
	struct ieee80211_hw *hw;
	int debug_mask;
	enum ath_device_state state;
	unsigned long op_flags;

	struct ath_ani ani;

	u16 cachelsz;
	u16 curaid;
	u8 macaddr[ETH_ALEN];
	u8 curbssid[ETH_ALEN];
	u8 bssidmask[ETH_ALEN];

	u32 rx_bufsize;

	u32 keymax;
	DECLARE_BITMAP(keymap, ATH_KEYMAX);
	DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
	DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
	enum ath_crypt_caps crypt_caps;

	unsigned int clockrate;

	spinlock_t cc_lock;
	struct ath_cycle_counters cc_ani;
	struct ath_cycle_counters cc_survey;

	struct ath_regulatory regulatory;
	struct ath_regulatory reg_world_copy;
	const struct ath_ops *ops;
	const struct ath_bus_ops *bus_ops;

	bool btcoex_enabled;
	bool disable_ani;
	bool bt_ant_diversity;

	int last_rssi;
	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
};

struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
				u32 len,
				gfp_t gfp_mask);
bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr);

void ath_hw_setbssidmask(struct ath_common *common);
void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
int ath_key_config(struct ath_common *common,
			  struct ieee80211_vif *vif,
			  struct ieee80211_sta *sta,
			  struct ieee80211_key_conf *key);
bool ath_hw_keyreset(struct ath_common *common, u16 entry);
void ath_hw_cycle_counters_update(struct ath_common *common);
int32_t ath_hw_get_listen_time(struct ath_common *common);

__printf(3, 4)
void ath_printk(const char *level, const struct ath_common *common,
		const char *fmt, ...);

#define ath_emerg(common, fmt, ...)				\
	ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
#define ath_alert(common, fmt, ...)				\
	ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
#define ath_crit(common, fmt, ...)				\
	ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
#define ath_err(common, fmt, ...)				\
	ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
#define ath_warn(common, fmt, ...)				\
	ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
#define ath_notice(common, fmt, ...)				\
	ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
#define ath_info(common, fmt, ...)				\
	ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)

/**
 * enum ath_debug_level - atheros wireless debug level
 *
 * @ATH_DBG_RESET: reset processing
 * @ATH_DBG_QUEUE: hardware queue management
 * @ATH_DBG_EEPROM: eeprom processing
 * @ATH_DBG_CALIBRATE: periodic calibration
 * @ATH_DBG_INTERRUPT: interrupt processing
 * @ATH_DBG_REGULATORY: regulatory processing
 * @ATH_DBG_ANI: adaptive noise immunitive processing
 * @ATH_DBG_XMIT: basic xmit operation
 * @ATH_DBG_BEACON: beacon handling
 * @ATH_DBG_CONFIG: configuration of the hardware
 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
 * @ATH_DBG_PS: power save processing
 * @ATH_DBG_HWTIMER: hardware timer handling
 * @ATH_DBG_BTCOEX: bluetooth coexistance
 * @ATH_DBG_BSTUCK: stuck beacons
 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
 *	used exclusively for WLAN-BT coexistence starting from
 *	AR9462.
 * @ATH_DBG_DFS: radar datection
 * @ATH_DBG_WOW: Wake on Wireless
 * @ATH_DBG_DYNACK: dynack handling
 * @ATH_DBG_ANY: enable all debugging
 *
 * The debug level is used to control the amount and type of debugging output
 * we want to see. Each driver has its own method for enabling debugging and
 * modifying debug level states -- but this is typically done through a
 * module parameter 'debug' along with a respective 'debug' debugfs file
 * entry.
 */
enum ATH_DEBUG {
	ATH_DBG_RESET		= 0x00000001,
	ATH_DBG_QUEUE		= 0x00000002,
	ATH_DBG_EEPROM		= 0x00000004,
	ATH_DBG_CALIBRATE	= 0x00000008,
	ATH_DBG_INTERRUPT	= 0x00000010,
	ATH_DBG_REGULATORY	= 0x00000020,
	ATH_DBG_ANI		= 0x00000040,
	ATH_DBG_XMIT		= 0x00000080,
	ATH_DBG_BEACON		= 0x00000100,
	ATH_DBG_CONFIG		= 0x00000200,
	ATH_DBG_FATAL		= 0x00000400,
	ATH_DBG_PS		= 0x00000800,
	ATH_DBG_BTCOEX		= 0x00001000,
	ATH_DBG_WMI		= 0x00002000,
	ATH_DBG_BSTUCK		= 0x00004000,
	ATH_DBG_MCI		= 0x00008000,
	ATH_DBG_DFS		= 0x00010000,
	ATH_DBG_WOW		= 0x00020000,
	ATH_DBG_CHAN_CTX	= 0x00040000,
	ATH_DBG_DYNACK		= 0x00080000,
	ATH_DBG_ANY		= 0xffffffff
};

#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
#define ATH_DBG_MAX_LEN 512

#ifdef CONFIG_ATH_DEBUG

#define ath_dbg(common, dbg_mask, fmt, ...)				\
do {									\
	if ((common)->debug_mask & ATH_DBG_##dbg_mask)			\
		ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__);	\
} while (0)

#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)

#else

static inline  __attribute__ ((format (printf, 3, 4)))
void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
	     const char *fmt, ...)
{
}
#define ath_dbg(common, dbg_mask, fmt, ...)				\
	_ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)

#define ATH_DBG_WARN(foo, arg...) do {} while (0)
#define ATH_DBG_WARN_ON_ONCE(foo) ({				\
	int __ret_warn_once = !!(foo);				\
	unlikely(__ret_warn_once);				\
})

#endif /* CONFIG_ATH_DEBUG */

/** Returns string describing opmode, or NULL if unknown mode. */
#ifdef CONFIG_ATH_DEBUG
const char *ath_opmode_to_string(enum nl80211_iftype opmode);
#else
static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
{
	return "UNKNOWN";
}
#endif

#endif /* ATH_H */
Commit	Line	Data
d15dd3e5 LR	1	/*
	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef ATH_H
	18	#define ATH_H
	19
f1d267ca	20	#include <linux/etherdevice.h>
d15dd3e5	21	#include <linux/skbuff.h>
bcd8f54a	22	#include <linux/if_ether.h>
b5bfc568	23	#include <linux/spinlock.h>
b002a4a9	24	#include <net/mac80211.h>
d15dd3e5	25
7e86c104 LR	26	/*
	27	* The key cache is used for h/w cipher state and also for
	28	* tracking station state such as the current tx antenna.
	29	* We also setup a mapping table between key cache slot indices
	30	* and station state to short-circuit node lookups on rx.
	31	* Different parts have different size key caches. We handle
	32	* up to ATH_KEYMAX entries (could dynamically allocate state).
	33	*/
	34	#define ATH_KEYMAX 128 /* max key cache size we handle */
	35
17753748 LR	36	static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
17753748 LR	37
3d536acf LR	38	struct ath_ani {
3d536acf LR	39	bool caldone;
3d536acf LR	40	unsigned int longcal_timer;
	41	unsigned int shortcal_timer;
	42	unsigned int resetcal_timer;
	43	unsigned int checkani_timer;
	44	struct timer_list timer;
	45	};
	46
b5bfc568 FF	47	struct ath_cycle_counters {
	48	u32 cycles;
	49	u32 rx_busy;
	50	u32 rx_frame;
	51	u32 tx_frame;
	52	};
	53
211f5859 LR	54	enum ath_device_state {
	55	ATH_HW_UNAVAILABLE,
	56	ATH_HW_INITIALIZED,
	57	};
	58
eefa01dd OR	59	enum ath_op_flags {
	60	ATH_OP_INVALID,
	61	ATH_OP_BEACONS,
	62	ATH_OP_ANI_RUN,
	63	ATH_OP_PRIM_STA_VIF,
	64	ATH_OP_HW_RESET,
	65	ATH_OP_SCANNING,
26f16c24	66	ATH_OP_MULTI_CHANNEL,
eefa01dd OR	67	};
eefa01dd OR	68
497ad9ad S	69	enum ath_bus_type {
	70	ATH_PCI,
	71	ATH_AHB,
	72	ATH_USB,
	73	};
	74
608b88cb	75	struct reg_dmn_pair_mapping {
ef8c0017	76	u16 reg_domain;
608b88cb LR	77	u16 reg_5ghz_ctl;
	78	u16 reg_2ghz_ctl;
	79	};
	80
	81	struct ath_regulatory {
	82	char alpha2[2];
	83	u16 country_code;
	84	u16 max_power_level;
608b88cb	85	u16 current_rd;
608b88cb LR	86	int16_t power_limit;
	87	struct reg_dmn_pair_mapping *regpair;
	88	};
	89
34a13051	90	enum ath_crypt_caps {
ce2220d1 BR	91	ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
ce2220d1 BR	92	ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
34a13051 BR	93	};
34a13051 BR	94
1bba5b73 BR	95	struct ath_keyval {
	96	u8 kv_type;
	97	u8 kv_pad;
	98	u16 kv_len;
	99	u8 kv_val[16]; /* TK */
	100	u8 kv_mic[8]; /* Michael MIC key */
	101	u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
	102	* supports both MIC keys in the same key cache entry;
	103	* in that case, kv_mic is the RX key) */
	104	};
	105
	106	enum ath_cipher {
	107	ATH_CIPHER_WEP = 0,
	108	ATH_CIPHER_AES_OCB = 1,
	109	ATH_CIPHER_AES_CCM = 2,
	110	ATH_CIPHER_CKIP = 3,
	111	ATH_CIPHER_TKIP = 4,
	112	ATH_CIPHER_CLR = 5,
	113	ATH_CIPHER_MIC = 127
	114	};
	115
50f56316 S	116	/**
	117	* struct ath_ops - Register read/write operations
	118	*
	119	* @read: Register read
09a525d3	120	* @multi_read: Multiple register read
50f56316 S	121	* @write: Register write
50f56316 S	122	* @enable_write_buffer: Enable multiple register writes
435c1610	123	* @write_flush: flush buffered register writes and disable buffering
50f56316	124	*/
9e4bffd2 LR	125	struct ath_ops {
9e4bffd2 LR	126	unsigned int (read)(void , u32 reg_offset);
09a525d3	127	void (multi_read)(void , u32 addr, u32 val, u16 count);
50f56316 S	128	void (write)(void , u32 val, u32 reg_offset);
50f56316 S	129	void (enable_write_buffer)(void );
50f56316	130	void (write_flush) (void );
845e03c9	131	u32 (rmw)(void , u32 reg_offset, u32 set, u32 clr);
9e4bffd2 LR	132	};
9e4bffd2 LR	133
5bb12791	134	struct ath_common;
0cb9e06b	135	struct ath_bus_ops;
5bb12791	136
d15dd3e5	137	struct ath_common {
13b81559	138	void *ah;
bc974f4a	139	void *priv;
b002a4a9	140	struct ieee80211_hw *hw;
c46917bb	141	int debug_mask;
211f5859	142	enum ath_device_state state;
eefa01dd	143	unsigned long op_flags;
c46917bb	144
3d536acf LR	145	struct ath_ani ani;
3d536acf LR	146
d15dd3e5	147	u16 cachelsz;
1510718d LR	148	u16 curaid;
	149	u8 macaddr[ETH_ALEN];
	150	u8 curbssid[ETH_ALEN];
	151	u8 bssidmask[ETH_ALEN];
c46917bb	152
cc861f74 LR	153	u32 rx_bufsize;
cc861f74 LR	154
7e86c104 LR	155	u32 keymax;
7e86c104 LR	156	DECLARE_BITMAP(keymap, ATH_KEYMAX);
56363dde	157	DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
bed3d9c0	158	DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
34a13051	159	enum ath_crypt_caps crypt_caps;
7e86c104	160
dfdac8ac FF	161	unsigned int clockrate;
dfdac8ac FF	162
b5bfc568 FF	163	spinlock_t cc_lock;
	164	struct ath_cycle_counters cc_ani;
	165	struct ath_cycle_counters cc_survey;
	166
608b88cb	167	struct ath_regulatory regulatory;
de1c732b	168	struct ath_regulatory reg_world_copy;
9adca126	169	const struct ath_ops *ops;
5bb12791	170	const struct ath_bus_ops *bus_ops;
8f5dcb1c VT	171
8f5dcb1c VT	172	bool btcoex_enabled;
05c0be2f	173	bool disable_ani;
63081305	174	bool bt_ant_diversity;
2f2cb326 OR	175
2f2cb326 OR	176	int last_rssi;
13f71050	177	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
d15dd3e5 LR	178	};
	179
	180	struct sk_buff ath_rxbuf_alloc(struct ath_common common,
	181	u32 len,
	182	gfp_t gfp_mask);
f1d267ca	183	bool ath_is_mybeacon(struct ath_common common, struct ieee80211_hdr hdr);
d15dd3e5	184
13b81559	185	void ath_hw_setbssidmask(struct ath_common *common);
1bba5b73 BR	186	void ath_key_delete(struct ath_common common, struct ieee80211_key_conf key);
	187	int ath_key_config(struct ath_common *common,
	188	struct ieee80211_vif *vif,
	189	struct ieee80211_sta *sta,
	190	struct ieee80211_key_conf *key);
	191	bool ath_hw_keyreset(struct ath_common *common, u16 entry);
b5bfc568 FF	192	void ath_hw_cycle_counters_update(struct ath_common *common);
b5bfc568 FF	193	int32_t ath_hw_get_listen_time(struct ath_common *common);
13b81559	194
98b36a02 BG	195	__printf(3, 4)
	196	void ath_printk(const char level, const struct ath_common common,
	197	const char *fmt, ...);
21a99f93 JP	198
21a99f93 JP	199	#define ath_emerg(common, fmt, ...) \
98b36a02	200	ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
21a99f93	201	#define ath_alert(common, fmt, ...) \
98b36a02	202	ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
21a99f93	203	#define ath_crit(common, fmt, ...) \
98b36a02	204	ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
21a99f93	205	#define ath_err(common, fmt, ...) \
98b36a02	206	ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
21a99f93	207	#define ath_warn(common, fmt, ...) \
98b36a02	208	ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
21a99f93	209	#define ath_notice(common, fmt, ...) \
98b36a02	210	ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
21a99f93	211	#define ath_info(common, fmt, ...) \
98b36a02	212	ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
21a99f93 JP	213
	214	/**
	215	* enum ath_debug_level - atheros wireless debug level
	216	*
	217	* @ATH_DBG_RESET: reset processing
	218	* @ATH_DBG_QUEUE: hardware queue management
	219	* @ATH_DBG_EEPROM: eeprom processing
	220	* @ATH_DBG_CALIBRATE: periodic calibration
	221	* @ATH_DBG_INTERRUPT: interrupt processing
	222	* @ATH_DBG_REGULATORY: regulatory processing
	223	* @ATH_DBG_ANI: adaptive noise immunitive processing
	224	* @ATH_DBG_XMIT: basic xmit operation
	225	* @ATH_DBG_BEACON: beacon handling
	226	* @ATH_DBG_CONFIG: configuration of the hardware
	227	* @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
	228	* @ATH_DBG_PS: power save processing
	229	* @ATH_DBG_HWTIMER: hardware timer handling
	230	* @ATH_DBG_BTCOEX: bluetooth coexistance
	231	* @ATH_DBG_BSTUCK: stuck beacons
55e435de LR	232	* @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
	233	* used exclusively for WLAN-BT coexistence starting from
	234	* AR9462.
9b203c8f	235	* @ATH_DBG_DFS: radar datection
b3ba6c52	236	* @ATH_DBG_WOW: Wake on Wireless
c774d57f	237	* @ATH_DBG_DYNACK: dynack handling
21a99f93 JP	238	* @ATH_DBG_ANY: enable all debugging
	239	*
	240	* The debug level is used to control the amount and type of debugging output
	241	* we want to see. Each driver has its own method for enabling debugging and
	242	* modifying debug level states -- but this is typically done through a
	243	* module parameter 'debug' along with a respective 'debug' debugfs file
	244	* entry.
	245	*/
	246	enum ATH_DEBUG {
	247	ATH_DBG_RESET = 0x00000001,
	248	ATH_DBG_QUEUE = 0x00000002,
	249	ATH_DBG_EEPROM = 0x00000004,
	250	ATH_DBG_CALIBRATE = 0x00000008,
	251	ATH_DBG_INTERRUPT = 0x00000010,
	252	ATH_DBG_REGULATORY = 0x00000020,
	253	ATH_DBG_ANI = 0x00000040,
	254	ATH_DBG_XMIT = 0x00000080,
	255	ATH_DBG_BEACON = 0x00000100,
	256	ATH_DBG_CONFIG = 0x00000200,
	257	ATH_DBG_FATAL = 0x00000400,
	258	ATH_DBG_PS = 0x00000800,
14335310 SM	259	ATH_DBG_BTCOEX = 0x00001000,
	260	ATH_DBG_WMI = 0x00002000,
	261	ATH_DBG_BSTUCK = 0x00004000,
	262	ATH_DBG_MCI = 0x00008000,
	263	ATH_DBG_DFS = 0x00010000,
	264	ATH_DBG_WOW = 0x00020000,
27328a75	265	ATH_DBG_CHAN_CTX = 0x00040000,
c774d57f	266	ATH_DBG_DYNACK = 0x00080000,
21a99f93 JP	267	ATH_DBG_ANY = 0xffffffff
	268	};
	269
	270	#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
e6664dff	271	#define ATH_DBG_MAX_LEN 512
21a99f93 JP	272
	273	#ifdef CONFIG_ATH_DEBUG
	274
7b8112d6 JP	275	#define ath_dbg(common, dbg_mask, fmt, ...) \
7b8112d6 JP	276	do { \
d2182b69	277	if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
98b36a02	278	ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
7b8112d6 JP	279	} while (0)
7b8112d6 JP	280
21a99f93	281	#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
d7fd1b50	282	#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
21a99f93 JP	283
	284	#else
	285
b9075fa9	286	static inline __attribute__ ((format (printf, 3, 4)))
d2182b69	287	void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
7b8112d6	288	const char *fmt, ...)
21a99f93	289	{
21a99f93	290	}
d2182b69 JP	291	#define ath_dbg(common, dbg_mask, fmt, ...) \
	292	_ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
	293
21a99f93	294	#define ATH_DBG_WARN(foo, arg...) do {} while (0)
b7613370 JL	295	#define ATH_DBG_WARN_ON_ONCE(foo) ({ \
	296	int __ret_warn_once = !!(foo); \
	297	unlikely(__ret_warn_once); \
	298	})
21a99f93 JP	299
	300	#endif /* CONFIG_ATH_DEBUG */
	301
	302	/** Returns string describing opmode, or NULL if unknown mode. */
	303	#ifdef CONFIG_ATH_DEBUG
	304	const char *ath_opmode_to_string(enum nl80211_iftype opmode);
	305	#else
	306	static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
	307	{
	308	return "UNKNOWN";
	309	}
	310	#endif
	311
d15dd3e5	312	#endif /* ATH_H */