Commit | Line | Data |
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d15dd3e5 LR |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH_H | |
18 | #define ATH_H | |
19 | ||
20 | #include <linux/skbuff.h> | |
bcd8f54a | 21 | #include <linux/if_ether.h> |
b002a4a9 | 22 | #include <net/mac80211.h> |
d15dd3e5 | 23 | |
7e86c104 LR |
24 | /* |
25 | * The key cache is used for h/w cipher state and also for | |
26 | * tracking station state such as the current tx antenna. | |
27 | * We also setup a mapping table between key cache slot indices | |
28 | * and station state to short-circuit node lookups on rx. | |
29 | * Different parts have different size key caches. We handle | |
30 | * up to ATH_KEYMAX entries (could dynamically allocate state). | |
31 | */ | |
32 | #define ATH_KEYMAX 128 /* max key cache size we handle */ | |
33 | ||
17753748 LR |
34 | static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; |
35 | ||
3d536acf LR |
36 | struct ath_ani { |
37 | bool caldone; | |
38 | int16_t noise_floor; | |
39 | unsigned int longcal_timer; | |
40 | unsigned int shortcal_timer; | |
41 | unsigned int resetcal_timer; | |
42 | unsigned int checkani_timer; | |
43 | struct timer_list timer; | |
44 | }; | |
45 | ||
211f5859 LR |
46 | enum ath_device_state { |
47 | ATH_HW_UNAVAILABLE, | |
48 | ATH_HW_INITIALIZED, | |
49 | }; | |
50 | ||
497ad9ad S |
51 | enum ath_bus_type { |
52 | ATH_PCI, | |
53 | ATH_AHB, | |
54 | ATH_USB, | |
55 | }; | |
56 | ||
608b88cb LR |
57 | struct reg_dmn_pair_mapping { |
58 | u16 regDmnEnum; | |
59 | u16 reg_5ghz_ctl; | |
60 | u16 reg_2ghz_ctl; | |
61 | }; | |
62 | ||
63 | struct ath_regulatory { | |
64 | char alpha2[2]; | |
65 | u16 country_code; | |
66 | u16 max_power_level; | |
67 | u32 tp_scale; | |
68 | u16 current_rd; | |
69 | u16 current_rd_ext; | |
70 | int16_t power_limit; | |
71 | struct reg_dmn_pair_mapping *regpair; | |
72 | }; | |
73 | ||
50f56316 S |
74 | /** |
75 | * struct ath_ops - Register read/write operations | |
76 | * | |
77 | * @read: Register read | |
78 | * @write: Register write | |
79 | * @enable_write_buffer: Enable multiple register writes | |
80 | * @disable_write_buffer: Disable multiple register writes | |
81 | * @write_flush: Flush buffered register writes | |
82 | */ | |
9e4bffd2 LR |
83 | struct ath_ops { |
84 | unsigned int (*read)(void *, u32 reg_offset); | |
50f56316 S |
85 | void (*write)(void *, u32 val, u32 reg_offset); |
86 | void (*enable_write_buffer)(void *); | |
87 | void (*disable_write_buffer)(void *); | |
88 | void (*write_flush) (void *); | |
9e4bffd2 LR |
89 | }; |
90 | ||
5bb12791 LR |
91 | struct ath_common; |
92 | ||
93 | struct ath_bus_ops { | |
497ad9ad S |
94 | enum ath_bus_type ath_bus_type; |
95 | void (*read_cachesize)(struct ath_common *common, int *csz); | |
96 | bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); | |
97 | void (*bt_coex_prep)(struct ath_common *common); | |
5bb12791 LR |
98 | }; |
99 | ||
d15dd3e5 | 100 | struct ath_common { |
13b81559 | 101 | void *ah; |
bc974f4a | 102 | void *priv; |
b002a4a9 | 103 | struct ieee80211_hw *hw; |
c46917bb | 104 | int debug_mask; |
211f5859 | 105 | enum ath_device_state state; |
c46917bb | 106 | |
3d536acf LR |
107 | struct ath_ani ani; |
108 | ||
d15dd3e5 | 109 | u16 cachelsz; |
1510718d LR |
110 | u16 curaid; |
111 | u8 macaddr[ETH_ALEN]; | |
112 | u8 curbssid[ETH_ALEN]; | |
113 | u8 bssidmask[ETH_ALEN]; | |
c46917bb | 114 | |
43c27613 LR |
115 | u8 tx_chainmask; |
116 | u8 rx_chainmask; | |
117 | ||
cc861f74 LR |
118 | u32 rx_bufsize; |
119 | ||
7e86c104 LR |
120 | u32 keymax; |
121 | DECLARE_BITMAP(keymap, ATH_KEYMAX); | |
56363dde | 122 | DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); |
7e86c104 LR |
123 | u8 splitmic; |
124 | ||
608b88cb | 125 | struct ath_regulatory regulatory; |
9adca126 | 126 | const struct ath_ops *ops; |
5bb12791 | 127 | const struct ath_bus_ops *bus_ops; |
d15dd3e5 LR |
128 | }; |
129 | ||
130 | struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, | |
131 | u32 len, | |
132 | gfp_t gfp_mask); | |
133 | ||
13b81559 LR |
134 | void ath_hw_setbssidmask(struct ath_common *common); |
135 | ||
d15dd3e5 | 136 | #endif /* ATH_H */ |