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5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/firmware.h> | |
5aabff05 | 20 | #include <linux/of.h> |
5e3dd157 KV |
21 | |
22 | #include "core.h" | |
23 | #include "mac.h" | |
24 | #include "htc.h" | |
25 | #include "hif.h" | |
26 | #include "wmi.h" | |
27 | #include "bmi.h" | |
28 | #include "debug.h" | |
29 | #include "htt.h" | |
43d2a30f | 30 | #include "testmode.h" |
d7579d12 | 31 | #include "wmi-ops.h" |
5e3dd157 KV |
32 | |
33 | unsigned int ath10k_debug_mask; | |
34 | static bool uart_print; | |
8868b12c RM |
35 | static bool skip_otp; |
36 | ||
5e3dd157 KV |
37 | module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); |
38 | module_param(uart_print, bool, 0644); | |
8868b12c RM |
39 | module_param(skip_otp, bool, 0644); |
40 | ||
5e3dd157 KV |
41 | MODULE_PARM_DESC(debug_mask, "Debugging mask"); |
42 | MODULE_PARM_DESC(uart_print, "Uart target debugging"); | |
8868b12c | 43 | MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); |
5e3dd157 KV |
44 | |
45 | static const struct ath10k_hw_params ath10k_hw_params_list[] = { | |
5e3dd157 KV |
46 | { |
47 | .id = QCA988X_HW_2_0_VERSION, | |
48 | .name = "qca988x hw2.0", | |
49 | .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, | |
3a8200b2 | 50 | .uart_pin = 7, |
587f7031 | 51 | .has_shifted_cc_wraparound = true, |
d772703e | 52 | .otp_exe_param = 0, |
5e3dd157 KV |
53 | .fw = { |
54 | .dir = QCA988X_HW_2_0_FW_DIR, | |
55 | .fw = QCA988X_HW_2_0_FW_FILE, | |
56 | .otp = QCA988X_HW_2_0_OTP_FILE, | |
57 | .board = QCA988X_HW_2_0_BOARD_DATA_FILE, | |
9764a2af MK |
58 | .board_size = QCA988X_BOARD_DATA_SZ, |
59 | .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, | |
5e3dd157 KV |
60 | }, |
61 | }, | |
d63955b3 MK |
62 | { |
63 | .id = QCA6174_HW_2_1_VERSION, | |
64 | .name = "qca6174 hw2.1", | |
65 | .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, | |
66 | .uart_pin = 6, | |
d772703e | 67 | .otp_exe_param = 0, |
d63955b3 MK |
68 | .fw = { |
69 | .dir = QCA6174_HW_2_1_FW_DIR, | |
70 | .fw = QCA6174_HW_2_1_FW_FILE, | |
71 | .otp = QCA6174_HW_2_1_OTP_FILE, | |
72 | .board = QCA6174_HW_2_1_BOARD_DATA_FILE, | |
73 | .board_size = QCA6174_BOARD_DATA_SZ, | |
74 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
75 | }, | |
76 | }, | |
77 | { | |
78 | .id = QCA6174_HW_3_0_VERSION, | |
79 | .name = "qca6174 hw3.0", | |
80 | .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, | |
81 | .uart_pin = 6, | |
d772703e | 82 | .otp_exe_param = 0, |
d63955b3 MK |
83 | .fw = { |
84 | .dir = QCA6174_HW_3_0_FW_DIR, | |
85 | .fw = QCA6174_HW_3_0_FW_FILE, | |
86 | .otp = QCA6174_HW_3_0_OTP_FILE, | |
87 | .board = QCA6174_HW_3_0_BOARD_DATA_FILE, | |
88 | .board_size = QCA6174_BOARD_DATA_SZ, | |
89 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
90 | }, | |
91 | }, | |
608b8f73 MK |
92 | { |
93 | .id = QCA6174_HW_3_2_VERSION, | |
94 | .name = "qca6174 hw3.2", | |
95 | .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, | |
96 | .uart_pin = 6, | |
d772703e | 97 | .otp_exe_param = 0, |
608b8f73 MK |
98 | .fw = { |
99 | /* uses same binaries as hw3.0 */ | |
100 | .dir = QCA6174_HW_3_0_FW_DIR, | |
101 | .fw = QCA6174_HW_3_0_FW_FILE, | |
102 | .otp = QCA6174_HW_3_0_OTP_FILE, | |
103 | .board = QCA6174_HW_3_0_BOARD_DATA_FILE, | |
104 | .board_size = QCA6174_BOARD_DATA_SZ, | |
105 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
106 | }, | |
107 | }, | |
8bd47021 VT |
108 | { |
109 | .id = QCA99X0_HW_2_0_DEV_VERSION, | |
110 | .name = "qca99x0 hw2.0", | |
111 | .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, | |
112 | .uart_pin = 7, | |
d772703e | 113 | .otp_exe_param = 0x00000700, |
8bd47021 VT |
114 | .fw = { |
115 | .dir = QCA99X0_HW_2_0_FW_DIR, | |
116 | .fw = QCA99X0_HW_2_0_FW_FILE, | |
117 | .otp = QCA99X0_HW_2_0_OTP_FILE, | |
118 | .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, | |
119 | .board_size = QCA99X0_BOARD_DATA_SZ, | |
120 | .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, | |
121 | }, | |
122 | }, | |
5e3dd157 KV |
123 | }; |
124 | ||
b27bc5a4 MK |
125 | static const char *const ath10k_core_fw_feature_str[] = { |
126 | [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", | |
127 | [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", | |
128 | [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", | |
129 | [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", | |
130 | [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", | |
131 | [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", | |
132 | [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", | |
133 | [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", | |
134 | [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", | |
135 | [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", | |
136 | }; | |
137 | ||
138 | static unsigned int ath10k_core_get_fw_feature_str(char *buf, | |
139 | size_t buf_len, | |
140 | enum ath10k_fw_features feat) | |
141 | { | |
142 | if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || | |
143 | WARN_ON(!ath10k_core_fw_feature_str[feat])) { | |
144 | return scnprintf(buf, buf_len, "bit%d", feat); | |
145 | } | |
146 | ||
147 | return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); | |
148 | } | |
149 | ||
150 | void ath10k_core_get_fw_features_str(struct ath10k *ar, | |
151 | char *buf, | |
152 | size_t buf_len) | |
153 | { | |
154 | unsigned int len = 0; | |
155 | int i; | |
156 | ||
157 | for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { | |
158 | if (test_bit(i, ar->fw_features)) { | |
159 | if (len > 0) | |
160 | len += scnprintf(buf + len, buf_len - len, ","); | |
161 | ||
162 | len += ath10k_core_get_fw_feature_str(buf + len, | |
163 | buf_len - len, | |
164 | i); | |
165 | } | |
166 | } | |
167 | } | |
168 | ||
5e3dd157 KV |
169 | static void ath10k_send_suspend_complete(struct ath10k *ar) |
170 | { | |
7aa7a72a | 171 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); |
5e3dd157 | 172 | |
9042e17d | 173 | complete(&ar->target_suspend); |
5e3dd157 KV |
174 | } |
175 | ||
5e3dd157 KV |
176 | static int ath10k_init_configure_target(struct ath10k *ar) |
177 | { | |
178 | u32 param_host; | |
179 | int ret; | |
180 | ||
181 | /* tell target which HTC version it is used*/ | |
182 | ret = ath10k_bmi_write32(ar, hi_app_host_interest, | |
183 | HTC_PROTOCOL_VERSION); | |
184 | if (ret) { | |
7aa7a72a | 185 | ath10k_err(ar, "settings HTC version failed\n"); |
5e3dd157 KV |
186 | return ret; |
187 | } | |
188 | ||
189 | /* set the firmware mode to STA/IBSS/AP */ | |
190 | ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); | |
191 | if (ret) { | |
7aa7a72a | 192 | ath10k_err(ar, "setting firmware mode (1/2) failed\n"); |
5e3dd157 KV |
193 | return ret; |
194 | } | |
195 | ||
196 | /* TODO following parameters need to be re-visited. */ | |
197 | /* num_device */ | |
198 | param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); | |
199 | /* Firmware mode */ | |
200 | /* FIXME: Why FW_MODE_AP ??.*/ | |
201 | param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); | |
202 | /* mac_addr_method */ | |
203 | param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); | |
204 | /* firmware_bridge */ | |
205 | param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); | |
206 | /* fwsubmode */ | |
207 | param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); | |
208 | ||
209 | ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); | |
210 | if (ret) { | |
7aa7a72a | 211 | ath10k_err(ar, "setting firmware mode (2/2) failed\n"); |
5e3dd157 KV |
212 | return ret; |
213 | } | |
214 | ||
215 | /* We do all byte-swapping on the host */ | |
216 | ret = ath10k_bmi_write32(ar, hi_be, 0); | |
217 | if (ret) { | |
7aa7a72a | 218 | ath10k_err(ar, "setting host CPU BE mode failed\n"); |
5e3dd157 KV |
219 | return ret; |
220 | } | |
221 | ||
222 | /* FW descriptor/Data swap flags */ | |
223 | ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); | |
224 | ||
225 | if (ret) { | |
7aa7a72a | 226 | ath10k_err(ar, "setting FW data/desc swap flags failed\n"); |
5e3dd157 KV |
227 | return ret; |
228 | } | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
233 | static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, | |
234 | const char *dir, | |
235 | const char *file) | |
236 | { | |
237 | char filename[100]; | |
238 | const struct firmware *fw; | |
239 | int ret; | |
240 | ||
241 | if (file == NULL) | |
242 | return ERR_PTR(-ENOENT); | |
243 | ||
244 | if (dir == NULL) | |
245 | dir = "."; | |
246 | ||
247 | snprintf(filename, sizeof(filename), "%s/%s", dir, file); | |
248 | ret = request_firmware(&fw, filename, ar->dev); | |
249 | if (ret) | |
250 | return ERR_PTR(ret); | |
251 | ||
252 | return fw; | |
253 | } | |
254 | ||
a58227ef KV |
255 | static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, |
256 | size_t data_len) | |
5e3dd157 | 257 | { |
9764a2af MK |
258 | u32 board_data_size = ar->hw_params.fw.board_size; |
259 | u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; | |
5e3dd157 KV |
260 | u32 board_ext_data_addr; |
261 | int ret; | |
262 | ||
263 | ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); | |
264 | if (ret) { | |
7aa7a72a MK |
265 | ath10k_err(ar, "could not read board ext data addr (%d)\n", |
266 | ret); | |
5e3dd157 KV |
267 | return ret; |
268 | } | |
269 | ||
7aa7a72a | 270 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
effea968 | 271 | "boot push board extended data addr 0x%x\n", |
5e3dd157 KV |
272 | board_ext_data_addr); |
273 | ||
274 | if (board_ext_data_addr == 0) | |
275 | return 0; | |
276 | ||
a58227ef | 277 | if (data_len != (board_data_size + board_ext_data_size)) { |
7aa7a72a | 278 | ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", |
a58227ef | 279 | data_len, board_data_size, board_ext_data_size); |
5e3dd157 KV |
280 | return -EINVAL; |
281 | } | |
282 | ||
283 | ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, | |
a58227ef | 284 | data + board_data_size, |
5e3dd157 KV |
285 | board_ext_data_size); |
286 | if (ret) { | |
7aa7a72a | 287 | ath10k_err(ar, "could not write board ext data (%d)\n", ret); |
5e3dd157 KV |
288 | return ret; |
289 | } | |
290 | ||
291 | ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, | |
292 | (board_ext_data_size << 16) | 1); | |
293 | if (ret) { | |
7aa7a72a MK |
294 | ath10k_err(ar, "could not write board ext data bit (%d)\n", |
295 | ret); | |
5e3dd157 KV |
296 | return ret; |
297 | } | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
a58227ef KV |
302 | static int ath10k_download_board_data(struct ath10k *ar, const void *data, |
303 | size_t data_len) | |
5e3dd157 | 304 | { |
9764a2af | 305 | u32 board_data_size = ar->hw_params.fw.board_size; |
5e3dd157 | 306 | u32 address; |
5e3dd157 KV |
307 | int ret; |
308 | ||
a58227ef | 309 | ret = ath10k_push_board_ext_data(ar, data, data_len); |
5e3dd157 | 310 | if (ret) { |
7aa7a72a | 311 | ath10k_err(ar, "could not push board ext data (%d)\n", ret); |
5e3dd157 KV |
312 | goto exit; |
313 | } | |
314 | ||
315 | ret = ath10k_bmi_read32(ar, hi_board_data, &address); | |
316 | if (ret) { | |
7aa7a72a | 317 | ath10k_err(ar, "could not read board data addr (%d)\n", ret); |
5e3dd157 KV |
318 | goto exit; |
319 | } | |
320 | ||
a58227ef | 321 | ret = ath10k_bmi_write_memory(ar, address, data, |
958df3a0 | 322 | min_t(u32, board_data_size, |
a58227ef | 323 | data_len)); |
5e3dd157 | 324 | if (ret) { |
7aa7a72a | 325 | ath10k_err(ar, "could not write board data (%d)\n", ret); |
5e3dd157 KV |
326 | goto exit; |
327 | } | |
328 | ||
329 | ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); | |
330 | if (ret) { | |
7aa7a72a | 331 | ath10k_err(ar, "could not write board data bit (%d)\n", ret); |
5e3dd157 KV |
332 | goto exit; |
333 | } | |
334 | ||
335 | exit: | |
5e3dd157 KV |
336 | return ret; |
337 | } | |
338 | ||
a58227ef KV |
339 | static int ath10k_download_cal_file(struct ath10k *ar) |
340 | { | |
341 | int ret; | |
342 | ||
343 | if (!ar->cal_file) | |
344 | return -ENOENT; | |
345 | ||
346 | if (IS_ERR(ar->cal_file)) | |
347 | return PTR_ERR(ar->cal_file); | |
348 | ||
349 | ret = ath10k_download_board_data(ar, ar->cal_file->data, | |
350 | ar->cal_file->size); | |
351 | if (ret) { | |
352 | ath10k_err(ar, "failed to download cal_file data: %d\n", ret); | |
353 | return ret; | |
354 | } | |
355 | ||
356 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
5aabff05 TK |
361 | static int ath10k_download_cal_dt(struct ath10k *ar) |
362 | { | |
363 | struct device_node *node; | |
364 | int data_len; | |
365 | void *data; | |
366 | int ret; | |
367 | ||
368 | node = ar->dev->of_node; | |
369 | if (!node) | |
370 | /* Device Tree is optional, don't print any warnings if | |
371 | * there's no node for ath10k. | |
372 | */ | |
373 | return -ENOENT; | |
374 | ||
375 | if (!of_get_property(node, "qcom,ath10k-calibration-data", | |
376 | &data_len)) { | |
377 | /* The calibration data node is optional */ | |
378 | return -ENOENT; | |
379 | } | |
380 | ||
381 | if (data_len != QCA988X_CAL_DATA_LEN) { | |
382 | ath10k_warn(ar, "invalid calibration data length in DT: %d\n", | |
383 | data_len); | |
384 | ret = -EMSGSIZE; | |
385 | goto out; | |
386 | } | |
387 | ||
388 | data = kmalloc(data_len, GFP_KERNEL); | |
389 | if (!data) { | |
390 | ret = -ENOMEM; | |
391 | goto out; | |
392 | } | |
393 | ||
394 | ret = of_property_read_u8_array(node, "qcom,ath10k-calibration-data", | |
395 | data, data_len); | |
396 | if (ret) { | |
397 | ath10k_warn(ar, "failed to read calibration data from DT: %d\n", | |
398 | ret); | |
399 | goto out_free; | |
400 | } | |
401 | ||
402 | ret = ath10k_download_board_data(ar, data, data_len); | |
403 | if (ret) { | |
404 | ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", | |
405 | ret); | |
406 | goto out_free; | |
407 | } | |
408 | ||
409 | ret = 0; | |
410 | ||
411 | out_free: | |
412 | kfree(data); | |
413 | ||
414 | out: | |
415 | return ret; | |
416 | } | |
417 | ||
5e3dd157 KV |
418 | static int ath10k_download_and_run_otp(struct ath10k *ar) |
419 | { | |
d6d4a58d | 420 | u32 result, address = ar->hw_params.patch_load_addr; |
d772703e | 421 | u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; |
5e3dd157 KV |
422 | int ret; |
423 | ||
a58227ef | 424 | ret = ath10k_download_board_data(ar, ar->board_data, ar->board_len); |
83091559 KV |
425 | if (ret) { |
426 | ath10k_err(ar, "failed to download board data: %d\n", ret); | |
427 | return ret; | |
428 | } | |
429 | ||
5e3dd157 KV |
430 | /* OTP is optional */ |
431 | ||
7f06ea1e | 432 | if (!ar->otp_data || !ar->otp_len) { |
7aa7a72a | 433 | ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n", |
36a8f413 | 434 | ar->otp_data, ar->otp_len); |
5e3dd157 | 435 | return 0; |
7f06ea1e KV |
436 | } |
437 | ||
7aa7a72a | 438 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", |
7f06ea1e | 439 | address, ar->otp_len); |
5e3dd157 | 440 | |
958df3a0 | 441 | ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len); |
5e3dd157 | 442 | if (ret) { |
7aa7a72a | 443 | ath10k_err(ar, "could not write otp (%d)\n", ret); |
7f06ea1e | 444 | return ret; |
5e3dd157 KV |
445 | } |
446 | ||
d772703e | 447 | ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); |
5e3dd157 | 448 | if (ret) { |
7aa7a72a | 449 | ath10k_err(ar, "could not execute otp (%d)\n", ret); |
7f06ea1e | 450 | return ret; |
5e3dd157 KV |
451 | } |
452 | ||
7aa7a72a | 453 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); |
7f06ea1e | 454 | |
d9153546 KV |
455 | if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, |
456 | ar->fw_features)) | |
457 | && result != 0) { | |
7aa7a72a | 458 | ath10k_err(ar, "otp calibration failed: %d", result); |
7f06ea1e KV |
459 | return -EINVAL; |
460 | } | |
461 | ||
462 | return 0; | |
5e3dd157 KV |
463 | } |
464 | ||
43d2a30f | 465 | static int ath10k_download_fw(struct ath10k *ar, enum ath10k_firmware_mode mode) |
5e3dd157 | 466 | { |
43d2a30f KV |
467 | u32 address, data_len; |
468 | const char *mode_name; | |
469 | const void *data; | |
5e3dd157 KV |
470 | int ret; |
471 | ||
5e3dd157 KV |
472 | address = ar->hw_params.patch_load_addr; |
473 | ||
43d2a30f KV |
474 | switch (mode) { |
475 | case ATH10K_FIRMWARE_MODE_NORMAL: | |
476 | data = ar->firmware_data; | |
477 | data_len = ar->firmware_len; | |
478 | mode_name = "normal"; | |
dcb02db1 VT |
479 | ret = ath10k_swap_code_seg_configure(ar, |
480 | ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW); | |
481 | if (ret) { | |
482 | ath10k_err(ar, "failed to configure fw code swap: %d\n", | |
483 | ret); | |
484 | return ret; | |
485 | } | |
43d2a30f KV |
486 | break; |
487 | case ATH10K_FIRMWARE_MODE_UTF: | |
488 | data = ar->testmode.utf->data; | |
489 | data_len = ar->testmode.utf->size; | |
490 | mode_name = "utf"; | |
491 | break; | |
492 | default: | |
493 | ath10k_err(ar, "unknown firmware mode: %d\n", mode); | |
494 | return -EINVAL; | |
495 | } | |
496 | ||
497 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
498 | "boot uploading firmware image %p len %d mode %s\n", | |
499 | data, data_len, mode_name); | |
500 | ||
501 | ret = ath10k_bmi_fast_download(ar, address, data, data_len); | |
5e3dd157 | 502 | if (ret) { |
43d2a30f KV |
503 | ath10k_err(ar, "failed to download %s firmware: %d\n", |
504 | mode_name, ret); | |
505 | return ret; | |
5e3dd157 KV |
506 | } |
507 | ||
29385057 MK |
508 | return ret; |
509 | } | |
510 | ||
511 | static void ath10k_core_free_firmware_files(struct ath10k *ar) | |
512 | { | |
db2cf865 | 513 | if (!IS_ERR(ar->board)) |
36527916 | 514 | release_firmware(ar->board); |
29385057 | 515 | |
db2cf865 | 516 | if (!IS_ERR(ar->otp)) |
29385057 MK |
517 | release_firmware(ar->otp); |
518 | ||
db2cf865 | 519 | if (!IS_ERR(ar->firmware)) |
29385057 MK |
520 | release_firmware(ar->firmware); |
521 | ||
db2cf865 | 522 | if (!IS_ERR(ar->cal_file)) |
a58227ef KV |
523 | release_firmware(ar->cal_file); |
524 | ||
dcb02db1 VT |
525 | ath10k_swap_code_seg_release(ar); |
526 | ||
36527916 | 527 | ar->board = NULL; |
958df3a0 KV |
528 | ar->board_data = NULL; |
529 | ar->board_len = 0; | |
530 | ||
29385057 | 531 | ar->otp = NULL; |
958df3a0 KV |
532 | ar->otp_data = NULL; |
533 | ar->otp_len = 0; | |
534 | ||
29385057 | 535 | ar->firmware = NULL; |
958df3a0 KV |
536 | ar->firmware_data = NULL; |
537 | ar->firmware_len = 0; | |
a58227ef KV |
538 | |
539 | ar->cal_file = NULL; | |
dcb02db1 | 540 | |
a58227ef KV |
541 | } |
542 | ||
543 | static int ath10k_fetch_cal_file(struct ath10k *ar) | |
544 | { | |
545 | char filename[100]; | |
546 | ||
547 | /* cal-<bus>-<id>.bin */ | |
548 | scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", | |
549 | ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); | |
550 | ||
551 | ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); | |
552 | if (IS_ERR(ar->cal_file)) | |
553 | /* calibration file is optional, don't print any warnings */ | |
554 | return PTR_ERR(ar->cal_file); | |
555 | ||
556 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", | |
557 | ATH10K_FW_DIR, filename); | |
558 | ||
559 | return 0; | |
29385057 MK |
560 | } |
561 | ||
de57e2c8 | 562 | static int ath10k_core_fetch_spec_board_file(struct ath10k *ar) |
29385057 | 563 | { |
de57e2c8 MK |
564 | char filename[100]; |
565 | ||
566 | scnprintf(filename, sizeof(filename), "board-%s-%s.bin", | |
567 | ath10k_bus_str(ar->hif.bus), ar->spec_board_id); | |
568 | ||
569 | ar->board = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, filename); | |
570 | if (IS_ERR(ar->board)) | |
571 | return PTR_ERR(ar->board); | |
572 | ||
573 | ar->board_data = ar->board->data; | |
574 | ar->board_len = ar->board->size; | |
575 | ar->spec_board_loaded = true; | |
29385057 | 576 | |
de57e2c8 MK |
577 | return 0; |
578 | } | |
579 | ||
580 | static int ath10k_core_fetch_generic_board_file(struct ath10k *ar) | |
581 | { | |
d0ed74f3 MK |
582 | if (!ar->hw_params.fw.board) { |
583 | ath10k_err(ar, "failed to find board file fw entry\n"); | |
29385057 MK |
584 | return -EINVAL; |
585 | } | |
586 | ||
36527916 KV |
587 | ar->board = ath10k_fetch_fw_file(ar, |
588 | ar->hw_params.fw.dir, | |
589 | ar->hw_params.fw.board); | |
de57e2c8 MK |
590 | if (IS_ERR(ar->board)) |
591 | return PTR_ERR(ar->board); | |
29385057 | 592 | |
958df3a0 KV |
593 | ar->board_data = ar->board->data; |
594 | ar->board_len = ar->board->size; | |
de57e2c8 MK |
595 | ar->spec_board_loaded = false; |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | static int ath10k_core_fetch_board_file(struct ath10k *ar) | |
601 | { | |
602 | int ret; | |
603 | ||
604 | if (strlen(ar->spec_board_id) > 0) { | |
605 | ret = ath10k_core_fetch_spec_board_file(ar); | |
606 | if (ret) { | |
607 | ath10k_info(ar, "failed to load spec board file, falling back to generic: %d\n", | |
608 | ret); | |
609 | goto generic; | |
610 | } | |
611 | ||
612 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found specific board file for %s\n", | |
613 | ar->spec_board_id); | |
614 | return 0; | |
615 | } | |
616 | ||
617 | generic: | |
618 | ret = ath10k_core_fetch_generic_board_file(ar); | |
619 | if (ret) { | |
620 | ath10k_err(ar, "failed to fetch generic board data: %d\n", ret); | |
621 | return ret; | |
622 | } | |
958df3a0 | 623 | |
d0ed74f3 MK |
624 | return 0; |
625 | } | |
626 | ||
627 | static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar) | |
628 | { | |
629 | int ret = 0; | |
630 | ||
631 | if (ar->hw_params.fw.fw == NULL) { | |
632 | ath10k_err(ar, "firmware file not defined\n"); | |
633 | return -EINVAL; | |
634 | } | |
635 | ||
29385057 MK |
636 | ar->firmware = ath10k_fetch_fw_file(ar, |
637 | ar->hw_params.fw.dir, | |
638 | ar->hw_params.fw.fw); | |
639 | if (IS_ERR(ar->firmware)) { | |
640 | ret = PTR_ERR(ar->firmware); | |
7aa7a72a | 641 | ath10k_err(ar, "could not fetch firmware (%d)\n", ret); |
29385057 MK |
642 | goto err; |
643 | } | |
644 | ||
958df3a0 KV |
645 | ar->firmware_data = ar->firmware->data; |
646 | ar->firmware_len = ar->firmware->size; | |
647 | ||
29385057 MK |
648 | /* OTP may be undefined. If so, don't fetch it at all */ |
649 | if (ar->hw_params.fw.otp == NULL) | |
650 | return 0; | |
651 | ||
652 | ar->otp = ath10k_fetch_fw_file(ar, | |
653 | ar->hw_params.fw.dir, | |
654 | ar->hw_params.fw.otp); | |
655 | if (IS_ERR(ar->otp)) { | |
656 | ret = PTR_ERR(ar->otp); | |
7aa7a72a | 657 | ath10k_err(ar, "could not fetch otp (%d)\n", ret); |
29385057 MK |
658 | goto err; |
659 | } | |
660 | ||
958df3a0 KV |
661 | ar->otp_data = ar->otp->data; |
662 | ar->otp_len = ar->otp->size; | |
663 | ||
29385057 MK |
664 | return 0; |
665 | ||
666 | err: | |
667 | ath10k_core_free_firmware_files(ar); | |
5e3dd157 KV |
668 | return ret; |
669 | } | |
670 | ||
1a222435 KV |
671 | static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name) |
672 | { | |
673 | size_t magic_len, len, ie_len; | |
674 | int ie_id, i, index, bit, ret; | |
675 | struct ath10k_fw_ie *hdr; | |
676 | const u8 *data; | |
202e86e6 | 677 | __le32 *timestamp, *version; |
1a222435 KV |
678 | |
679 | /* first fetch the firmware file (firmware-*.bin) */ | |
680 | ar->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, name); | |
681 | if (IS_ERR(ar->firmware)) { | |
7aa7a72a | 682 | ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n", |
53c02284 | 683 | ar->hw_params.fw.dir, name, PTR_ERR(ar->firmware)); |
1a222435 KV |
684 | return PTR_ERR(ar->firmware); |
685 | } | |
686 | ||
687 | data = ar->firmware->data; | |
688 | len = ar->firmware->size; | |
689 | ||
690 | /* magic also includes the null byte, check that as well */ | |
691 | magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; | |
692 | ||
693 | if (len < magic_len) { | |
7aa7a72a | 694 | ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", |
53c02284 | 695 | ar->hw_params.fw.dir, name, len); |
9bab1cc0 MK |
696 | ret = -EINVAL; |
697 | goto err; | |
1a222435 KV |
698 | } |
699 | ||
700 | if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { | |
7aa7a72a | 701 | ath10k_err(ar, "invalid firmware magic\n"); |
9bab1cc0 MK |
702 | ret = -EINVAL; |
703 | goto err; | |
1a222435 KV |
704 | } |
705 | ||
706 | /* jump over the padding */ | |
707 | magic_len = ALIGN(magic_len, 4); | |
708 | ||
709 | len -= magic_len; | |
710 | data += magic_len; | |
711 | ||
712 | /* loop elements */ | |
713 | while (len > sizeof(struct ath10k_fw_ie)) { | |
714 | hdr = (struct ath10k_fw_ie *)data; | |
715 | ||
716 | ie_id = le32_to_cpu(hdr->id); | |
717 | ie_len = le32_to_cpu(hdr->len); | |
718 | ||
719 | len -= sizeof(*hdr); | |
720 | data += sizeof(*hdr); | |
721 | ||
722 | if (len < ie_len) { | |
7aa7a72a | 723 | ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", |
1a222435 | 724 | ie_id, len, ie_len); |
9bab1cc0 MK |
725 | ret = -EINVAL; |
726 | goto err; | |
1a222435 KV |
727 | } |
728 | ||
729 | switch (ie_id) { | |
730 | case ATH10K_FW_IE_FW_VERSION: | |
731 | if (ie_len > sizeof(ar->hw->wiphy->fw_version) - 1) | |
732 | break; | |
733 | ||
734 | memcpy(ar->hw->wiphy->fw_version, data, ie_len); | |
735 | ar->hw->wiphy->fw_version[ie_len] = '\0'; | |
736 | ||
7aa7a72a | 737 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
738 | "found fw version %s\n", |
739 | ar->hw->wiphy->fw_version); | |
740 | break; | |
741 | case ATH10K_FW_IE_TIMESTAMP: | |
742 | if (ie_len != sizeof(u32)) | |
743 | break; | |
744 | ||
745 | timestamp = (__le32 *)data; | |
746 | ||
7aa7a72a | 747 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", |
1a222435 KV |
748 | le32_to_cpup(timestamp)); |
749 | break; | |
750 | case ATH10K_FW_IE_FEATURES: | |
7aa7a72a | 751 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
752 | "found firmware features ie (%zd B)\n", |
753 | ie_len); | |
754 | ||
755 | for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { | |
756 | index = i / 8; | |
757 | bit = i % 8; | |
758 | ||
759 | if (index == ie_len) | |
760 | break; | |
761 | ||
f591a1a5 | 762 | if (data[index] & (1 << bit)) { |
7aa7a72a | 763 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
f591a1a5 BG |
764 | "Enabling feature bit: %i\n", |
765 | i); | |
1a222435 | 766 | __set_bit(i, ar->fw_features); |
f591a1a5 | 767 | } |
1a222435 KV |
768 | } |
769 | ||
7aa7a72a | 770 | ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", |
1a222435 KV |
771 | ar->fw_features, |
772 | sizeof(ar->fw_features)); | |
773 | break; | |
774 | case ATH10K_FW_IE_FW_IMAGE: | |
7aa7a72a | 775 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
776 | "found fw image ie (%zd B)\n", |
777 | ie_len); | |
778 | ||
779 | ar->firmware_data = data; | |
780 | ar->firmware_len = ie_len; | |
781 | ||
782 | break; | |
783 | case ATH10K_FW_IE_OTP_IMAGE: | |
7aa7a72a | 784 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
785 | "found otp image ie (%zd B)\n", |
786 | ie_len); | |
787 | ||
788 | ar->otp_data = data; | |
789 | ar->otp_len = ie_len; | |
790 | ||
791 | break; | |
202e86e6 KV |
792 | case ATH10K_FW_IE_WMI_OP_VERSION: |
793 | if (ie_len != sizeof(u32)) | |
794 | break; | |
795 | ||
796 | version = (__le32 *)data; | |
797 | ||
798 | ar->wmi.op_version = le32_to_cpup(version); | |
799 | ||
800 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", | |
801 | ar->wmi.op_version); | |
802 | break; | |
8348db29 RM |
803 | case ATH10K_FW_IE_HTT_OP_VERSION: |
804 | if (ie_len != sizeof(u32)) | |
805 | break; | |
806 | ||
807 | version = (__le32 *)data; | |
808 | ||
809 | ar->htt.op_version = le32_to_cpup(version); | |
810 | ||
811 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", | |
812 | ar->htt.op_version); | |
813 | break; | |
dcb02db1 VT |
814 | case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: |
815 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
816 | "found fw code swap image ie (%zd B)\n", | |
817 | ie_len); | |
818 | ar->swap.firmware_codeswap_data = data; | |
819 | ar->swap.firmware_codeswap_len = ie_len; | |
820 | break; | |
1a222435 | 821 | default: |
7aa7a72a | 822 | ath10k_warn(ar, "Unknown FW IE: %u\n", |
1a222435 KV |
823 | le32_to_cpu(hdr->id)); |
824 | break; | |
825 | } | |
826 | ||
827 | /* jump over the padding */ | |
828 | ie_len = ALIGN(ie_len, 4); | |
829 | ||
830 | len -= ie_len; | |
831 | data += ie_len; | |
e05634ee | 832 | } |
1a222435 KV |
833 | |
834 | if (!ar->firmware_data || !ar->firmware_len) { | |
7aa7a72a | 835 | ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", |
53c02284 | 836 | ar->hw_params.fw.dir, name); |
1a222435 KV |
837 | ret = -ENOMEDIUM; |
838 | goto err; | |
839 | } | |
840 | ||
1a222435 KV |
841 | return 0; |
842 | ||
843 | err: | |
844 | ath10k_core_free_firmware_files(ar); | |
845 | return ret; | |
846 | } | |
847 | ||
848 | static int ath10k_core_fetch_firmware_files(struct ath10k *ar) | |
849 | { | |
850 | int ret; | |
851 | ||
a58227ef KV |
852 | /* calibration file is optional, don't check for any errors */ |
853 | ath10k_fetch_cal_file(ar); | |
854 | ||
d0ed74f3 MK |
855 | ret = ath10k_core_fetch_board_file(ar); |
856 | if (ret) { | |
857 | ath10k_err(ar, "failed to fetch board file: %d\n", ret); | |
858 | return ret; | |
859 | } | |
860 | ||
53513c30 KV |
861 | ar->fw_api = 5; |
862 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); | |
863 | ||
864 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE); | |
865 | if (ret == 0) | |
866 | goto success; | |
867 | ||
4a16fbec RM |
868 | ar->fw_api = 4; |
869 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); | |
870 | ||
871 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE); | |
872 | if (ret == 0) | |
873 | goto success; | |
874 | ||
24c88f78 | 875 | ar->fw_api = 3; |
7aa7a72a | 876 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); |
24c88f78 MK |
877 | |
878 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE); | |
879 | if (ret == 0) | |
880 | goto success; | |
881 | ||
53c02284 | 882 | ar->fw_api = 2; |
7aa7a72a | 883 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); |
53c02284 | 884 | |
1a222435 | 885 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE); |
53c02284 BG |
886 | if (ret == 0) |
887 | goto success; | |
888 | ||
889 | ar->fw_api = 1; | |
7aa7a72a | 890 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); |
1a222435 KV |
891 | |
892 | ret = ath10k_core_fetch_firmware_api_1(ar); | |
893 | if (ret) | |
894 | return ret; | |
895 | ||
53c02284 | 896 | success: |
7aa7a72a | 897 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); |
1a222435 KV |
898 | |
899 | return 0; | |
900 | } | |
901 | ||
83091559 | 902 | static int ath10k_download_cal_data(struct ath10k *ar) |
5e3dd157 KV |
903 | { |
904 | int ret; | |
905 | ||
a58227ef KV |
906 | ret = ath10k_download_cal_file(ar); |
907 | if (ret == 0) { | |
908 | ar->cal_mode = ATH10K_CAL_MODE_FILE; | |
909 | goto done; | |
910 | } | |
911 | ||
912 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
5aabff05 TK |
913 | "boot did not find a calibration file, try DT next: %d\n", |
914 | ret); | |
915 | ||
916 | ret = ath10k_download_cal_dt(ar); | |
917 | if (ret == 0) { | |
918 | ar->cal_mode = ATH10K_CAL_MODE_DT; | |
919 | goto done; | |
920 | } | |
921 | ||
922 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
923 | "boot did not find DT entry, try OTP next: %d\n", | |
a58227ef KV |
924 | ret); |
925 | ||
5e3dd157 | 926 | ret = ath10k_download_and_run_otp(ar); |
36a8f413 | 927 | if (ret) { |
7aa7a72a | 928 | ath10k_err(ar, "failed to run otp: %d\n", ret); |
5e3dd157 | 929 | return ret; |
36a8f413 | 930 | } |
5e3dd157 | 931 | |
a58227ef KV |
932 | ar->cal_mode = ATH10K_CAL_MODE_OTP; |
933 | ||
934 | done: | |
935 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", | |
936 | ath10k_cal_mode_str(ar->cal_mode)); | |
937 | return 0; | |
5e3dd157 KV |
938 | } |
939 | ||
940 | static int ath10k_init_uart(struct ath10k *ar) | |
941 | { | |
942 | int ret; | |
943 | ||
944 | /* | |
945 | * Explicitly setting UART prints to zero as target turns it on | |
946 | * based on scratch registers. | |
947 | */ | |
948 | ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); | |
949 | if (ret) { | |
7aa7a72a | 950 | ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); |
5e3dd157 KV |
951 | return ret; |
952 | } | |
953 | ||
c8c39afe | 954 | if (!uart_print) |
5e3dd157 | 955 | return 0; |
5e3dd157 | 956 | |
3a8200b2 | 957 | ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); |
5e3dd157 | 958 | if (ret) { |
7aa7a72a | 959 | ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); |
5e3dd157 KV |
960 | return ret; |
961 | } | |
962 | ||
963 | ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); | |
964 | if (ret) { | |
7aa7a72a | 965 | ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); |
5e3dd157 KV |
966 | return ret; |
967 | } | |
968 | ||
03fc137b BM |
969 | /* Set the UART baud rate to 19200. */ |
970 | ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); | |
971 | if (ret) { | |
7aa7a72a | 972 | ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); |
03fc137b BM |
973 | return ret; |
974 | } | |
975 | ||
7aa7a72a | 976 | ath10k_info(ar, "UART prints enabled\n"); |
5e3dd157 KV |
977 | return 0; |
978 | } | |
979 | ||
980 | static int ath10k_init_hw_params(struct ath10k *ar) | |
981 | { | |
982 | const struct ath10k_hw_params *uninitialized_var(hw_params); | |
983 | int i; | |
984 | ||
985 | for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { | |
986 | hw_params = &ath10k_hw_params_list[i]; | |
987 | ||
988 | if (hw_params->id == ar->target_version) | |
989 | break; | |
990 | } | |
991 | ||
992 | if (i == ARRAY_SIZE(ath10k_hw_params_list)) { | |
7aa7a72a | 993 | ath10k_err(ar, "Unsupported hardware version: 0x%x\n", |
5e3dd157 KV |
994 | ar->target_version); |
995 | return -EINVAL; | |
996 | } | |
997 | ||
998 | ar->hw_params = *hw_params; | |
999 | ||
7aa7a72a | 1000 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", |
c8c39afe | 1001 | ar->hw_params.name, ar->target_version); |
5e3dd157 KV |
1002 | |
1003 | return 0; | |
1004 | } | |
1005 | ||
affd3217 MK |
1006 | static void ath10k_core_restart(struct work_struct *work) |
1007 | { | |
1008 | struct ath10k *ar = container_of(work, struct ath10k, restart_work); | |
1009 | ||
7962b0d8 MK |
1010 | set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); |
1011 | ||
1012 | /* Place a barrier to make sure the compiler doesn't reorder | |
1013 | * CRASH_FLUSH and calling other functions. | |
1014 | */ | |
1015 | barrier(); | |
1016 | ||
1017 | ieee80211_stop_queues(ar->hw); | |
1018 | ath10k_drain_tx(ar); | |
1019 | complete_all(&ar->scan.started); | |
1020 | complete_all(&ar->scan.completed); | |
1021 | complete_all(&ar->scan.on_channel); | |
1022 | complete_all(&ar->offchan_tx_completed); | |
1023 | complete_all(&ar->install_key_done); | |
1024 | complete_all(&ar->vdev_setup_done); | |
ac2953fc | 1025 | complete_all(&ar->thermal.wmi_sync); |
7962b0d8 MK |
1026 | wake_up(&ar->htt.empty_tx_wq); |
1027 | wake_up(&ar->wmi.tx_credits_wq); | |
1028 | wake_up(&ar->peer_mapping_wq); | |
1029 | ||
affd3217 MK |
1030 | mutex_lock(&ar->conf_mutex); |
1031 | ||
1032 | switch (ar->state) { | |
1033 | case ATH10K_STATE_ON: | |
affd3217 | 1034 | ar->state = ATH10K_STATE_RESTARTING; |
61e9aab7 | 1035 | ath10k_hif_stop(ar); |
5c81c7fd | 1036 | ath10k_scan_finish(ar); |
affd3217 MK |
1037 | ieee80211_restart_hw(ar->hw); |
1038 | break; | |
1039 | case ATH10K_STATE_OFF: | |
5e90de86 MK |
1040 | /* this can happen if driver is being unloaded |
1041 | * or if the crash happens during FW probing */ | |
7aa7a72a | 1042 | ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); |
affd3217 MK |
1043 | break; |
1044 | case ATH10K_STATE_RESTARTING: | |
c5058f5b MK |
1045 | /* hw restart might be requested from multiple places */ |
1046 | break; | |
affd3217 MK |
1047 | case ATH10K_STATE_RESTARTED: |
1048 | ar->state = ATH10K_STATE_WEDGED; | |
1049 | /* fall through */ | |
1050 | case ATH10K_STATE_WEDGED: | |
7aa7a72a | 1051 | ath10k_warn(ar, "device is wedged, will not restart\n"); |
affd3217 | 1052 | break; |
43d2a30f KV |
1053 | case ATH10K_STATE_UTF: |
1054 | ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); | |
1055 | break; | |
affd3217 MK |
1056 | } |
1057 | ||
1058 | mutex_unlock(&ar->conf_mutex); | |
1059 | } | |
1060 | ||
5f2144d9 | 1061 | static int ath10k_core_init_firmware_features(struct ath10k *ar) |
cfd1061e | 1062 | { |
5f2144d9 KV |
1063 | if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features) && |
1064 | !test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) { | |
1065 | ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); | |
1066 | return -EINVAL; | |
1067 | } | |
1068 | ||
202e86e6 KV |
1069 | if (ar->wmi.op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { |
1070 | ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", | |
1071 | ATH10K_FW_WMI_OP_VERSION_MAX, ar->wmi.op_version); | |
1072 | return -EINVAL; | |
1073 | } | |
1074 | ||
1075 | /* Backwards compatibility for firmwares without | |
1076 | * ATH10K_FW_IE_WMI_OP_VERSION. | |
1077 | */ | |
1078 | if (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { | |
1079 | if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) { | |
4a16fbec RM |
1080 | if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, |
1081 | ar->fw_features)) | |
202e86e6 KV |
1082 | ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_2; |
1083 | else | |
1084 | ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_1; | |
1085 | } else { | |
1086 | ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; | |
1087 | } | |
1088 | } | |
1089 | ||
1090 | switch (ar->wmi.op_version) { | |
1091 | case ATH10K_FW_WMI_OP_VERSION_MAIN: | |
cfd1061e MK |
1092 | ar->max_num_peers = TARGET_NUM_PEERS; |
1093 | ar->max_num_stations = TARGET_NUM_STATIONS; | |
30c78167 | 1094 | ar->max_num_vdevs = TARGET_NUM_VDEVS; |
91ad5f56 | 1095 | ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; |
6274cd41 YL |
1096 | ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | |
1097 | WMI_STAT_PEER; | |
202e86e6 KV |
1098 | break; |
1099 | case ATH10K_FW_WMI_OP_VERSION_10_1: | |
1100 | case ATH10K_FW_WMI_OP_VERSION_10_2: | |
4a16fbec | 1101 | case ATH10K_FW_WMI_OP_VERSION_10_2_4: |
202e86e6 KV |
1102 | ar->max_num_peers = TARGET_10X_NUM_PEERS; |
1103 | ar->max_num_stations = TARGET_10X_NUM_STATIONS; | |
30c78167 | 1104 | ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; |
91ad5f56 | 1105 | ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; |
6274cd41 | 1106 | ar->fw_stats_req_mask = WMI_STAT_PEER; |
202e86e6 | 1107 | break; |
ca996ec5 MK |
1108 | case ATH10K_FW_WMI_OP_VERSION_TLV: |
1109 | ar->max_num_peers = TARGET_TLV_NUM_PEERS; | |
1110 | ar->max_num_stations = TARGET_TLV_NUM_STATIONS; | |
49274332 | 1111 | ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; |
8cca3d60 | 1112 | ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; |
ca996ec5 | 1113 | ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; |
25c86619 | 1114 | ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; |
6274cd41 YL |
1115 | ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | |
1116 | WMI_STAT_PEER; | |
ca996ec5 | 1117 | break; |
9bd21322 | 1118 | case ATH10K_FW_WMI_OP_VERSION_10_4: |
202e86e6 KV |
1119 | case ATH10K_FW_WMI_OP_VERSION_UNSET: |
1120 | case ATH10K_FW_WMI_OP_VERSION_MAX: | |
1121 | WARN_ON(1); | |
1122 | return -EINVAL; | |
cfd1061e | 1123 | } |
5f2144d9 | 1124 | |
dc3632a1 KV |
1125 | /* Backwards compatibility for firmwares without |
1126 | * ATH10K_FW_IE_HTT_OP_VERSION. | |
1127 | */ | |
1128 | if (ar->htt.op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { | |
1129 | switch (ar->wmi.op_version) { | |
1130 | case ATH10K_FW_WMI_OP_VERSION_MAIN: | |
1131 | ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; | |
1132 | break; | |
1133 | case ATH10K_FW_WMI_OP_VERSION_10_1: | |
1134 | case ATH10K_FW_WMI_OP_VERSION_10_2: | |
1135 | case ATH10K_FW_WMI_OP_VERSION_10_2_4: | |
1136 | ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_10_1; | |
1137 | break; | |
1138 | case ATH10K_FW_WMI_OP_VERSION_TLV: | |
1139 | ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_TLV; | |
1140 | break; | |
9bd21322 | 1141 | case ATH10K_FW_WMI_OP_VERSION_10_4: |
dc3632a1 KV |
1142 | case ATH10K_FW_WMI_OP_VERSION_UNSET: |
1143 | case ATH10K_FW_WMI_OP_VERSION_MAX: | |
1144 | WARN_ON(1); | |
1145 | return -EINVAL; | |
1146 | } | |
1147 | } | |
1148 | ||
5f2144d9 | 1149 | return 0; |
cfd1061e MK |
1150 | } |
1151 | ||
43d2a30f | 1152 | int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode) |
5e3dd157 | 1153 | { |
5e3dd157 KV |
1154 | int status; |
1155 | ||
60631c5c KV |
1156 | lockdep_assert_held(&ar->conf_mutex); |
1157 | ||
7962b0d8 MK |
1158 | clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); |
1159 | ||
64d151d4 MK |
1160 | ath10k_bmi_start(ar); |
1161 | ||
5e3dd157 KV |
1162 | if (ath10k_init_configure_target(ar)) { |
1163 | status = -EINVAL; | |
1164 | goto err; | |
1165 | } | |
1166 | ||
83091559 KV |
1167 | status = ath10k_download_cal_data(ar); |
1168 | if (status) | |
1169 | goto err; | |
1170 | ||
163f5264 RM |
1171 | /* Some of of qca988x solutions are having global reset issue |
1172 | * during target initialization. Bypassing PLL setting before | |
1173 | * downloading firmware and letting the SoC run on REF_CLK is | |
1174 | * fixing the problem. Corresponding firmware change is also needed | |
1175 | * to set the clock source once the target is initialized. | |
1176 | */ | |
1177 | if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, | |
1178 | ar->fw_features)) { | |
1179 | status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); | |
1180 | if (status) { | |
1181 | ath10k_err(ar, "could not write to skip_clock_init: %d\n", | |
1182 | status); | |
1183 | goto err; | |
1184 | } | |
1185 | } | |
1186 | ||
83091559 | 1187 | status = ath10k_download_fw(ar, mode); |
5e3dd157 KV |
1188 | if (status) |
1189 | goto err; | |
1190 | ||
1191 | status = ath10k_init_uart(ar); | |
1192 | if (status) | |
1193 | goto err; | |
1194 | ||
cd003fad MK |
1195 | ar->htc.htc_ops.target_send_suspend_complete = |
1196 | ath10k_send_suspend_complete; | |
5e3dd157 | 1197 | |
cd003fad MK |
1198 | status = ath10k_htc_init(ar); |
1199 | if (status) { | |
7aa7a72a | 1200 | ath10k_err(ar, "could not init HTC (%d)\n", status); |
5e3dd157 KV |
1201 | goto err; |
1202 | } | |
1203 | ||
1204 | status = ath10k_bmi_done(ar); | |
1205 | if (status) | |
cd003fad | 1206 | goto err; |
5e3dd157 KV |
1207 | |
1208 | status = ath10k_wmi_attach(ar); | |
1209 | if (status) { | |
7aa7a72a | 1210 | ath10k_err(ar, "WMI attach failed: %d\n", status); |
cd003fad | 1211 | goto err; |
5e3dd157 KV |
1212 | } |
1213 | ||
95bf21f9 MK |
1214 | status = ath10k_htt_init(ar); |
1215 | if (status) { | |
7aa7a72a | 1216 | ath10k_err(ar, "failed to init htt: %d\n", status); |
95bf21f9 MK |
1217 | goto err_wmi_detach; |
1218 | } | |
1219 | ||
1220 | status = ath10k_htt_tx_alloc(&ar->htt); | |
1221 | if (status) { | |
7aa7a72a | 1222 | ath10k_err(ar, "failed to alloc htt tx: %d\n", status); |
95bf21f9 MK |
1223 | goto err_wmi_detach; |
1224 | } | |
1225 | ||
1226 | status = ath10k_htt_rx_alloc(&ar->htt); | |
1227 | if (status) { | |
7aa7a72a | 1228 | ath10k_err(ar, "failed to alloc htt rx: %d\n", status); |
95bf21f9 MK |
1229 | goto err_htt_tx_detach; |
1230 | } | |
1231 | ||
67e3c63f MK |
1232 | status = ath10k_hif_start(ar); |
1233 | if (status) { | |
7aa7a72a | 1234 | ath10k_err(ar, "could not start HIF: %d\n", status); |
95bf21f9 | 1235 | goto err_htt_rx_detach; |
67e3c63f MK |
1236 | } |
1237 | ||
1238 | status = ath10k_htc_wait_target(&ar->htc); | |
1239 | if (status) { | |
7aa7a72a | 1240 | ath10k_err(ar, "failed to connect to HTC: %d\n", status); |
67e3c63f MK |
1241 | goto err_hif_stop; |
1242 | } | |
5e3dd157 | 1243 | |
43d2a30f KV |
1244 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { |
1245 | status = ath10k_htt_connect(&ar->htt); | |
1246 | if (status) { | |
1247 | ath10k_err(ar, "failed to connect htt (%d)\n", status); | |
1248 | goto err_hif_stop; | |
1249 | } | |
5e3dd157 KV |
1250 | } |
1251 | ||
95bf21f9 MK |
1252 | status = ath10k_wmi_connect(ar); |
1253 | if (status) { | |
7aa7a72a | 1254 | ath10k_err(ar, "could not connect wmi: %d\n", status); |
95bf21f9 MK |
1255 | goto err_hif_stop; |
1256 | } | |
1257 | ||
1258 | status = ath10k_htc_start(&ar->htc); | |
1259 | if (status) { | |
7aa7a72a | 1260 | ath10k_err(ar, "failed to start htc: %d\n", status); |
95bf21f9 MK |
1261 | goto err_hif_stop; |
1262 | } | |
1263 | ||
43d2a30f KV |
1264 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { |
1265 | status = ath10k_wmi_wait_for_service_ready(ar); | |
9eea5689 | 1266 | if (status) { |
43d2a30f | 1267 | ath10k_warn(ar, "wmi service ready event not received"); |
43d2a30f KV |
1268 | goto err_hif_stop; |
1269 | } | |
95bf21f9 | 1270 | } |
5e3dd157 | 1271 | |
7aa7a72a | 1272 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", |
c8c39afe | 1273 | ar->hw->wiphy->fw_version); |
5e3dd157 | 1274 | |
5e3dd157 KV |
1275 | status = ath10k_wmi_cmd_init(ar); |
1276 | if (status) { | |
7aa7a72a MK |
1277 | ath10k_err(ar, "could not send WMI init command (%d)\n", |
1278 | status); | |
b7967dc7 | 1279 | goto err_hif_stop; |
5e3dd157 KV |
1280 | } |
1281 | ||
1282 | status = ath10k_wmi_wait_for_unified_ready(ar); | |
9eea5689 | 1283 | if (status) { |
7aa7a72a | 1284 | ath10k_err(ar, "wmi unified ready event not received\n"); |
b7967dc7 | 1285 | goto err_hif_stop; |
5e3dd157 KV |
1286 | } |
1287 | ||
c545070e MK |
1288 | /* If firmware indicates Full Rx Reorder support it must be used in a |
1289 | * slightly different manner. Let HTT code know. | |
1290 | */ | |
1291 | ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, | |
1292 | ar->wmi.svc_map)); | |
1293 | ||
1294 | status = ath10k_htt_rx_ring_refill(ar); | |
1295 | if (status) { | |
1296 | ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); | |
1297 | goto err_hif_stop; | |
1298 | } | |
1299 | ||
43d2a30f KV |
1300 | /* we don't care about HTT in UTF mode */ |
1301 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { | |
1302 | status = ath10k_htt_setup(&ar->htt); | |
1303 | if (status) { | |
1304 | ath10k_err(ar, "failed to setup htt: %d\n", status); | |
1305 | goto err_hif_stop; | |
1306 | } | |
95bf21f9 | 1307 | } |
5e3dd157 | 1308 | |
db66ea04 KV |
1309 | status = ath10k_debug_start(ar); |
1310 | if (status) | |
b7967dc7 | 1311 | goto err_hif_stop; |
db66ea04 | 1312 | |
30c78167 | 1313 | ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; |
dfa413de | 1314 | |
0579119f | 1315 | INIT_LIST_HEAD(&ar->arvifs); |
1a1b8a88 | 1316 | |
dd30a36e MK |
1317 | return 0; |
1318 | ||
67e3c63f MK |
1319 | err_hif_stop: |
1320 | ath10k_hif_stop(ar); | |
95bf21f9 MK |
1321 | err_htt_rx_detach: |
1322 | ath10k_htt_rx_free(&ar->htt); | |
1323 | err_htt_tx_detach: | |
1324 | ath10k_htt_tx_free(&ar->htt); | |
dd30a36e MK |
1325 | err_wmi_detach: |
1326 | ath10k_wmi_detach(ar); | |
1327 | err: | |
1328 | return status; | |
1329 | } | |
818bdd16 | 1330 | EXPORT_SYMBOL(ath10k_core_start); |
dd30a36e | 1331 | |
00f5482b MP |
1332 | int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) |
1333 | { | |
1334 | int ret; | |
a7a42849 | 1335 | unsigned long time_left; |
00f5482b MP |
1336 | |
1337 | reinit_completion(&ar->target_suspend); | |
1338 | ||
1339 | ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); | |
1340 | if (ret) { | |
7aa7a72a | 1341 | ath10k_warn(ar, "could not suspend target (%d)\n", ret); |
00f5482b MP |
1342 | return ret; |
1343 | } | |
1344 | ||
a7a42849 | 1345 | time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); |
00f5482b | 1346 | |
a7a42849 | 1347 | if (!time_left) { |
7aa7a72a | 1348 | ath10k_warn(ar, "suspend timed out - target pause event never came\n"); |
00f5482b MP |
1349 | return -ETIMEDOUT; |
1350 | } | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
dd30a36e MK |
1355 | void ath10k_core_stop(struct ath10k *ar) |
1356 | { | |
60631c5c KV |
1357 | lockdep_assert_held(&ar->conf_mutex); |
1358 | ||
00f5482b | 1359 | /* try to suspend target */ |
43d2a30f KV |
1360 | if (ar->state != ATH10K_STATE_RESTARTING && |
1361 | ar->state != ATH10K_STATE_UTF) | |
216a1836 MK |
1362 | ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); |
1363 | ||
db66ea04 | 1364 | ath10k_debug_stop(ar); |
95bf21f9 MK |
1365 | ath10k_hif_stop(ar); |
1366 | ath10k_htt_tx_free(&ar->htt); | |
1367 | ath10k_htt_rx_free(&ar->htt); | |
dd30a36e MK |
1368 | ath10k_wmi_detach(ar); |
1369 | } | |
818bdd16 MK |
1370 | EXPORT_SYMBOL(ath10k_core_stop); |
1371 | ||
1372 | /* mac80211 manages fw/hw initialization through start/stop hooks. However in | |
1373 | * order to know what hw capabilities should be advertised to mac80211 it is | |
1374 | * necessary to load the firmware (and tear it down immediately since start | |
1375 | * hook will try to init it again) before registering */ | |
1376 | static int ath10k_core_probe_fw(struct ath10k *ar) | |
1377 | { | |
29385057 MK |
1378 | struct bmi_target_info target_info; |
1379 | int ret = 0; | |
818bdd16 MK |
1380 | |
1381 | ret = ath10k_hif_power_up(ar); | |
1382 | if (ret) { | |
7aa7a72a | 1383 | ath10k_err(ar, "could not start pci hif (%d)\n", ret); |
818bdd16 MK |
1384 | return ret; |
1385 | } | |
1386 | ||
29385057 MK |
1387 | memset(&target_info, 0, sizeof(target_info)); |
1388 | ret = ath10k_bmi_get_target_info(ar, &target_info); | |
1389 | if (ret) { | |
7aa7a72a | 1390 | ath10k_err(ar, "could not get target info (%d)\n", ret); |
c6ce492d | 1391 | goto err_power_down; |
29385057 MK |
1392 | } |
1393 | ||
1394 | ar->target_version = target_info.version; | |
1395 | ar->hw->wiphy->hw_version = target_info.version; | |
1396 | ||
1397 | ret = ath10k_init_hw_params(ar); | |
1398 | if (ret) { | |
7aa7a72a | 1399 | ath10k_err(ar, "could not get hw params (%d)\n", ret); |
c6ce492d | 1400 | goto err_power_down; |
29385057 MK |
1401 | } |
1402 | ||
1403 | ret = ath10k_core_fetch_firmware_files(ar); | |
1404 | if (ret) { | |
7aa7a72a | 1405 | ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); |
c6ce492d | 1406 | goto err_power_down; |
29385057 MK |
1407 | } |
1408 | ||
5f2144d9 KV |
1409 | ret = ath10k_core_init_firmware_features(ar); |
1410 | if (ret) { | |
1411 | ath10k_err(ar, "fatal problem with firmware features: %d\n", | |
1412 | ret); | |
1413 | goto err_free_firmware_files; | |
1414 | } | |
cfd1061e | 1415 | |
dcb02db1 VT |
1416 | ret = ath10k_swap_code_seg_init(ar); |
1417 | if (ret) { | |
1418 | ath10k_err(ar, "failed to initialize code swap segment: %d\n", | |
1419 | ret); | |
1420 | goto err_free_firmware_files; | |
1421 | } | |
1422 | ||
60631c5c KV |
1423 | mutex_lock(&ar->conf_mutex); |
1424 | ||
43d2a30f | 1425 | ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL); |
818bdd16 | 1426 | if (ret) { |
7aa7a72a | 1427 | ath10k_err(ar, "could not init core (%d)\n", ret); |
c6ce492d | 1428 | goto err_unlock; |
818bdd16 MK |
1429 | } |
1430 | ||
8079de0d | 1431 | ath10k_print_driver_info(ar); |
818bdd16 | 1432 | ath10k_core_stop(ar); |
60631c5c KV |
1433 | |
1434 | mutex_unlock(&ar->conf_mutex); | |
1435 | ||
818bdd16 MK |
1436 | ath10k_hif_power_down(ar); |
1437 | return 0; | |
c6ce492d KV |
1438 | |
1439 | err_unlock: | |
1440 | mutex_unlock(&ar->conf_mutex); | |
1441 | ||
5f2144d9 | 1442 | err_free_firmware_files: |
c6ce492d KV |
1443 | ath10k_core_free_firmware_files(ar); |
1444 | ||
1445 | err_power_down: | |
1446 | ath10k_hif_power_down(ar); | |
1447 | ||
1448 | return ret; | |
818bdd16 | 1449 | } |
dd30a36e | 1450 | |
6782cb69 | 1451 | static void ath10k_core_register_work(struct work_struct *work) |
dd30a36e | 1452 | { |
6782cb69 | 1453 | struct ath10k *ar = container_of(work, struct ath10k, register_work); |
dd30a36e MK |
1454 | int status; |
1455 | ||
818bdd16 MK |
1456 | status = ath10k_core_probe_fw(ar); |
1457 | if (status) { | |
7aa7a72a | 1458 | ath10k_err(ar, "could not probe fw (%d)\n", status); |
6782cb69 | 1459 | goto err; |
818bdd16 | 1460 | } |
dd30a36e | 1461 | |
5e3dd157 | 1462 | status = ath10k_mac_register(ar); |
818bdd16 | 1463 | if (status) { |
7aa7a72a | 1464 | ath10k_err(ar, "could not register to mac80211 (%d)\n", status); |
29385057 | 1465 | goto err_release_fw; |
818bdd16 | 1466 | } |
5e3dd157 | 1467 | |
e13cf7a3 | 1468 | status = ath10k_debug_register(ar); |
5e3dd157 | 1469 | if (status) { |
7aa7a72a | 1470 | ath10k_err(ar, "unable to initialize debugfs\n"); |
5e3dd157 KV |
1471 | goto err_unregister_mac; |
1472 | } | |
1473 | ||
855aed12 SW |
1474 | status = ath10k_spectral_create(ar); |
1475 | if (status) { | |
7aa7a72a | 1476 | ath10k_err(ar, "failed to initialize spectral\n"); |
855aed12 SW |
1477 | goto err_debug_destroy; |
1478 | } | |
1479 | ||
fe6f36d6 RM |
1480 | status = ath10k_thermal_register(ar); |
1481 | if (status) { | |
1482 | ath10k_err(ar, "could not register thermal device: %d\n", | |
1483 | status); | |
1484 | goto err_spectral_destroy; | |
1485 | } | |
1486 | ||
6782cb69 MK |
1487 | set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); |
1488 | return; | |
5e3dd157 | 1489 | |
fe6f36d6 RM |
1490 | err_spectral_destroy: |
1491 | ath10k_spectral_destroy(ar); | |
855aed12 SW |
1492 | err_debug_destroy: |
1493 | ath10k_debug_destroy(ar); | |
5e3dd157 KV |
1494 | err_unregister_mac: |
1495 | ath10k_mac_unregister(ar); | |
29385057 MK |
1496 | err_release_fw: |
1497 | ath10k_core_free_firmware_files(ar); | |
6782cb69 | 1498 | err: |
a491a920 MK |
1499 | /* TODO: It's probably a good idea to release device from the driver |
1500 | * but calling device_release_driver() here will cause a deadlock. | |
1501 | */ | |
6782cb69 MK |
1502 | return; |
1503 | } | |
1504 | ||
1505 | int ath10k_core_register(struct ath10k *ar, u32 chip_id) | |
1506 | { | |
6782cb69 | 1507 | ar->chip_id = chip_id; |
6782cb69 MK |
1508 | queue_work(ar->workqueue, &ar->register_work); |
1509 | ||
1510 | return 0; | |
5e3dd157 KV |
1511 | } |
1512 | EXPORT_SYMBOL(ath10k_core_register); | |
1513 | ||
1514 | void ath10k_core_unregister(struct ath10k *ar) | |
1515 | { | |
6782cb69 MK |
1516 | cancel_work_sync(&ar->register_work); |
1517 | ||
1518 | if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) | |
1519 | return; | |
1520 | ||
fe6f36d6 | 1521 | ath10k_thermal_unregister(ar); |
804eef14 SW |
1522 | /* Stop spectral before unregistering from mac80211 to remove the |
1523 | * relayfs debugfs file cleanly. Otherwise the parent debugfs tree | |
1524 | * would be already be free'd recursively, leading to a double free. | |
1525 | */ | |
1526 | ath10k_spectral_destroy(ar); | |
1527 | ||
5e3dd157 KV |
1528 | /* We must unregister from mac80211 before we stop HTC and HIF. |
1529 | * Otherwise we will fail to submit commands to FW and mac80211 will be | |
1530 | * unhappy about callback failures. */ | |
1531 | ath10k_mac_unregister(ar); | |
db66ea04 | 1532 | |
43d2a30f KV |
1533 | ath10k_testmode_destroy(ar); |
1534 | ||
29385057 | 1535 | ath10k_core_free_firmware_files(ar); |
6f1f56ea | 1536 | |
e13cf7a3 | 1537 | ath10k_debug_unregister(ar); |
5e3dd157 KV |
1538 | } |
1539 | EXPORT_SYMBOL(ath10k_core_unregister); | |
1540 | ||
e7b54194 | 1541 | struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, |
e07db352 | 1542 | enum ath10k_bus bus, |
d63955b3 | 1543 | enum ath10k_hw_rev hw_rev, |
0d0a6939 MK |
1544 | const struct ath10k_hif_ops *hif_ops) |
1545 | { | |
1546 | struct ath10k *ar; | |
e13cf7a3 | 1547 | int ret; |
0d0a6939 | 1548 | |
e7b54194 | 1549 | ar = ath10k_mac_create(priv_size); |
0d0a6939 MK |
1550 | if (!ar) |
1551 | return NULL; | |
1552 | ||
1553 | ar->ath_common.priv = ar; | |
1554 | ar->ath_common.hw = ar->hw; | |
0d0a6939 | 1555 | ar->dev = dev; |
d63955b3 | 1556 | ar->hw_rev = hw_rev; |
0d0a6939 | 1557 | ar->hif.ops = hif_ops; |
e07db352 | 1558 | ar->hif.bus = bus; |
0d0a6939 | 1559 | |
d63955b3 MK |
1560 | switch (hw_rev) { |
1561 | case ATH10K_HW_QCA988X: | |
1562 | ar->regs = &qca988x_regs; | |
2f2cfc4a | 1563 | ar->hw_values = &qca988x_values; |
d63955b3 MK |
1564 | break; |
1565 | case ATH10K_HW_QCA6174: | |
1566 | ar->regs = &qca6174_regs; | |
2f2cfc4a | 1567 | ar->hw_values = &qca6174_values; |
d63955b3 | 1568 | break; |
8bd47021 VT |
1569 | case ATH10K_HW_QCA99X0: |
1570 | ar->regs = &qca99x0_regs; | |
1571 | ar->hw_values = &qca99x0_values; | |
1572 | break; | |
d63955b3 MK |
1573 | default: |
1574 | ath10k_err(ar, "unsupported core hardware revision %d\n", | |
1575 | hw_rev); | |
1576 | ret = -ENOTSUPP; | |
1577 | goto err_free_mac; | |
1578 | } | |
1579 | ||
0d0a6939 MK |
1580 | init_completion(&ar->scan.started); |
1581 | init_completion(&ar->scan.completed); | |
1582 | init_completion(&ar->scan.on_channel); | |
1583 | init_completion(&ar->target_suspend); | |
5fd3ac3c | 1584 | init_completion(&ar->wow.wakeup_completed); |
0d0a6939 MK |
1585 | |
1586 | init_completion(&ar->install_key_done); | |
1587 | init_completion(&ar->vdev_setup_done); | |
ac2953fc | 1588 | init_completion(&ar->thermal.wmi_sync); |
0d0a6939 | 1589 | |
5c81c7fd | 1590 | INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); |
0d0a6939 MK |
1591 | |
1592 | ar->workqueue = create_singlethread_workqueue("ath10k_wq"); | |
1593 | if (!ar->workqueue) | |
e13cf7a3 | 1594 | goto err_free_mac; |
0d0a6939 MK |
1595 | |
1596 | mutex_init(&ar->conf_mutex); | |
1597 | spin_lock_init(&ar->data_lock); | |
1598 | ||
1599 | INIT_LIST_HEAD(&ar->peers); | |
1600 | init_waitqueue_head(&ar->peer_mapping_wq); | |
7962b0d8 MK |
1601 | init_waitqueue_head(&ar->htt.empty_tx_wq); |
1602 | init_waitqueue_head(&ar->wmi.tx_credits_wq); | |
0d0a6939 MK |
1603 | |
1604 | init_completion(&ar->offchan_tx_completed); | |
1605 | INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); | |
1606 | skb_queue_head_init(&ar->offchan_tx_queue); | |
1607 | ||
1608 | INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); | |
1609 | skb_queue_head_init(&ar->wmi_mgmt_tx_queue); | |
1610 | ||
6782cb69 | 1611 | INIT_WORK(&ar->register_work, ath10k_core_register_work); |
0d0a6939 MK |
1612 | INIT_WORK(&ar->restart_work, ath10k_core_restart); |
1613 | ||
e13cf7a3 MK |
1614 | ret = ath10k_debug_create(ar); |
1615 | if (ret) | |
1616 | goto err_free_wq; | |
1617 | ||
0d0a6939 MK |
1618 | return ar; |
1619 | ||
e13cf7a3 MK |
1620 | err_free_wq: |
1621 | destroy_workqueue(ar->workqueue); | |
1622 | ||
1623 | err_free_mac: | |
0d0a6939 | 1624 | ath10k_mac_destroy(ar); |
e13cf7a3 | 1625 | |
0d0a6939 MK |
1626 | return NULL; |
1627 | } | |
1628 | EXPORT_SYMBOL(ath10k_core_create); | |
1629 | ||
1630 | void ath10k_core_destroy(struct ath10k *ar) | |
1631 | { | |
1632 | flush_workqueue(ar->workqueue); | |
1633 | destroy_workqueue(ar->workqueue); | |
1634 | ||
e13cf7a3 | 1635 | ath10k_debug_destroy(ar); |
0d0a6939 MK |
1636 | ath10k_mac_destroy(ar); |
1637 | } | |
1638 | EXPORT_SYMBOL(ath10k_core_destroy); | |
1639 | ||
5e3dd157 KV |
1640 | MODULE_AUTHOR("Qualcomm Atheros"); |
1641 | MODULE_DESCRIPTION("Core module for QCA988X PCIe devices."); | |
1642 | MODULE_LICENSE("Dual BSD/GPL"); |