[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / core.h

/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef _CORE_H_
#define _CORE_H_

#include <linux/completion.h>
#include <linux/if_ether.h>
#include <linux/types.h>
#include <linux/pci.h>

#include "htt.h"
#include "htc.h"
#include "hw.h"
#include "targaddrs.h"
#include "wmi.h"
#include "../ath.h"
#include "../regd.h"
#include "../dfs_pattern_detector.h"

#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
#define WO(_f)      ((_f##_OFFSET) >> 2)

#define ATH10K_SCAN_ID 0
#define WMI_READY_TIMEOUT (5 * HZ)
#define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
#define ATH10K_NUM_CHANS 38

/* Antenna noise floor */
#define ATH10K_DEFAULT_NOISE_FLOOR -95

#define ATH10K_MAX_NUM_MGMT_PENDING 128

/* number of failed packets */
#define ATH10K_KICKOUT_THRESHOLD 50

/*
 * Use insanely high numbers to make sure that the firmware implementation
 * won't start, we have the same functionality already in hostapd. Unit
 * is seconds.
 */
#define ATH10K_KEEPALIVE_MIN_IDLE 3747
#define ATH10K_KEEPALIVE_MAX_IDLE 3895
#define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900

struct ath10k;

struct ath10k_skb_cb {
	dma_addr_t paddr;
	u8 vdev_id;

	struct {
		u8 tid;
		bool is_offchan;
		struct ath10k_htt_txbuf *txbuf;
		u32 txbuf_paddr;
	} __packed htt;

	struct {
		bool dtim_zero;
		bool deliver_cab;
	} bcn;
} __packed;

static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
{
	BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
		     IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
	return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
}

static inline u32 host_interest_item_address(u32 item_offset)
{
	return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
}

struct ath10k_bmi {
	bool done_sent;
};

#define ATH10K_MAX_MEM_REQS 16

struct ath10k_mem_chunk {
	void *vaddr;
	dma_addr_t paddr;
	u32 len;
	u32 req_id;
};

struct ath10k_wmi {
	enum ath10k_htc_ep_id eid;
	struct completion service_ready;
	struct completion unified_ready;
	wait_queue_head_t tx_credits_wq;
	struct wmi_cmd_map *cmd;
	struct wmi_vdev_param_map *vdev_param;
	struct wmi_pdev_param_map *pdev_param;

	u32 num_mem_chunks;
	struct ath10k_mem_chunk mem_chunks[ATH10K_MAX_MEM_REQS];
};

struct ath10k_peer_stat {
	u8 peer_macaddr[ETH_ALEN];
	u32 peer_rssi;
	u32 peer_tx_rate;
};

struct ath10k_target_stats {
	/* PDEV stats */
	s32 ch_noise_floor;
	u32 tx_frame_count;
	u32 rx_frame_count;
	u32 rx_clear_count;
	u32 cycle_count;
	u32 phy_err_count;
	u32 chan_tx_power;

	/* PDEV TX stats */
	s32 comp_queued;
	s32 comp_delivered;
	s32 msdu_enqued;
	s32 mpdu_enqued;
	s32 wmm_drop;
	s32 local_enqued;
	s32 local_freed;
	s32 hw_queued;
	s32 hw_reaped;
	s32 underrun;
	s32 tx_abort;
	s32 mpdus_requed;
	u32 tx_ko;
	u32 data_rc;
	u32 self_triggers;
	u32 sw_retry_failure;
	u32 illgl_rate_phy_err;
	u32 pdev_cont_xretry;
	u32 pdev_tx_timeout;
	u32 pdev_resets;
	u32 phy_underrun;
	u32 txop_ovf;

	/* PDEV RX stats */
	s32 mid_ppdu_route_change;
	s32 status_rcvd;
	s32 r0_frags;
	s32 r1_frags;
	s32 r2_frags;
	s32 r3_frags;
	s32 htt_msdus;
	s32 htt_mpdus;
	s32 loc_msdus;
	s32 loc_mpdus;
	s32 oversize_amsdu;
	s32 phy_errs;
	s32 phy_err_drop;
	s32 mpdu_errs;

	/* VDEV STATS */

	/* PEER STATS */
	u8 peers;
	struct ath10k_peer_stat peer_stat[TARGET_NUM_PEERS];

	/* TODO: Beacon filter stats */

};

struct ath10k_dfs_stats {
	u32 phy_errors;
	u32 pulses_total;
	u32 pulses_detected;
	u32 pulses_discarded;
	u32 radar_detected;
};

#define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */

struct ath10k_peer {
	struct list_head list;
	int vdev_id;
	u8 addr[ETH_ALEN];
	DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
	struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
};

struct ath10k_sta {
	struct ath10k_vif *arvif;

	/* the following are protected by ar->data_lock */
	u32 changed; /* IEEE80211_RC_* */
	u32 bw;
	u32 nss;
	u32 smps;

	struct work_struct update_wk;
};

#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)

struct ath10k_vif {
	struct list_head list;

	u32 vdev_id;
	enum wmi_vdev_type vdev_type;
	enum wmi_vdev_subtype vdev_subtype;
	u32 beacon_interval;
	u32 dtim_period;
	struct sk_buff *beacon;
	/* protected by data_lock */
	bool beacon_sent;

	struct ath10k *ar;
	struct ieee80211_vif *vif;

	bool is_started;
	bool is_up;
	u32 aid;
	u8 bssid[ETH_ALEN];

	struct work_struct wep_key_work;
	struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
	u8 def_wep_key_idx;
	u8 def_wep_key_newidx;

	u16 tx_seq_no;

	union {
		struct {
			u32 uapsd;
		} sta;
		struct {
			/* 127 stations; wmi limit */
			u8 tim_bitmap[16];
			u8 tim_len;
			u32 ssid_len;
			u8 ssid[IEEE80211_MAX_SSID_LEN];
			bool hidden_ssid;
			/* P2P_IE with NoA attribute for P2P_GO case */
			u32 noa_len;
			u8 *noa_data;
		} ap;
	} u;

	u8 fixed_rate;
	u8 fixed_nss;
	u8 force_sgi;
};

struct ath10k_vif_iter {
	u32 vdev_id;
	struct ath10k_vif *arvif;
};

struct ath10k_debug {
	struct dentry *debugfs_phy;

	struct ath10k_target_stats target_stats;
	u32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE];

	struct completion event_stats_compl;

	unsigned long htt_stats_mask;
	struct delayed_work htt_stats_dwork;
	struct ath10k_dfs_stats dfs_stats;
	struct ath_dfs_pool_stats dfs_pool_stats;

	u32 fw_dbglog_mask;
};

enum ath10k_state {
	ATH10K_STATE_OFF = 0,
	ATH10K_STATE_ON,

	/* When doing firmware recovery the device is first powered down.
	 * mac80211 is supposed to call in to start() hook later on. It is
	 * however possible that driver unloading and firmware crash overlap.
	 * mac80211 can wait on conf_mutex in stop() while the device is
	 * stopped in ath10k_core_restart() work holding conf_mutex. The state
	 * RESTARTED means that the device is up and mac80211 has started hw
	 * reconfiguration. Once mac80211 is done with the reconfiguration we
	 * set the state to STATE_ON in restart_complete(). */
	ATH10K_STATE_RESTARTING,
	ATH10K_STATE_RESTARTED,

	/* The device has crashed while restarting hw. This state is like ON
	 * but commands are blocked in HTC and -ECOMM response is given. This
	 * prevents completion timeouts and makes the driver more responsive to
	 * userspace commands. This is also prevents recursive recovery. */
	ATH10K_STATE_WEDGED,
};

enum ath10k_fw_features {
	/* wmi_mgmt_rx_hdr contains extra RSSI information */
	ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,

	/* firmware from 10X branch */
	ATH10K_FW_FEATURE_WMI_10X = 1,

	/* firmware support tx frame management over WMI, otherwise it's HTT */
	ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,

	/* Firmware does not support P2P */
	ATH10K_FW_FEATURE_NO_P2P = 3,

	/* keep last */
	ATH10K_FW_FEATURE_COUNT,
};

enum ath10k_dev_flags {
	/* Indicates that ath10k device is during CAC phase of DFS */
	ATH10K_CAC_RUNNING,
	ATH10K_FLAG_FIRST_BOOT_DONE,
};

struct ath10k {
	struct ath_common ath_common;
	struct ieee80211_hw *hw;
	struct device *dev;
	u8 mac_addr[ETH_ALEN];

	u32 chip_id;
	u32 target_version;
	u8 fw_version_major;
	u32 fw_version_minor;
	u16 fw_version_release;
	u16 fw_version_build;
	u32 phy_capability;
	u32 hw_min_tx_power;
	u32 hw_max_tx_power;
	u32 ht_cap_info;
	u32 vht_cap_info;
	u32 num_rf_chains;

	DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);

	struct targetdef *targetdef;
	struct hostdef *hostdef;

	bool p2p;

	struct {
		void *priv;
		const struct ath10k_hif_ops *ops;
	} hif;

	struct completion target_suspend;

	struct ath10k_bmi bmi;
	struct ath10k_wmi wmi;
	struct ath10k_htc htc;
	struct ath10k_htt htt;

	struct ath10k_hw_params {
		u32 id;
		const char *name;
		u32 patch_load_addr;

		struct ath10k_hw_params_fw {
			const char *dir;
			const char *fw;
			const char *otp;
			const char *board;
		} fw;
	} hw_params;

	const struct firmware *board;
	const void *board_data;
	size_t board_len;

	const struct firmware *otp;
	const void *otp_data;
	size_t otp_len;

	const struct firmware *firmware;
	const void *firmware_data;
	size_t firmware_len;

	int fw_api;

	struct {
		struct completion started;
		struct completion completed;
		struct completion on_channel;
		struct timer_list timeout;
		bool is_roc;
		bool in_progress;
		bool aborting;
		int vdev_id;
		int roc_freq;
	} scan;

	struct {
		struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
	} mac;

	/* should never be NULL; needed for regular htt rx */
	struct ieee80211_channel *rx_channel;

	/* valid during scan; needed for mgmt rx during scan */
	struct ieee80211_channel *scan_channel;

	/* current operating channel definition */
	struct cfg80211_chan_def chandef;

	int free_vdev_map;
	int monitor_vdev_id;
	bool monitor_enabled;
	bool monitor_present;
	unsigned int filter_flags;
	unsigned long dev_flags;
	u32 dfs_block_radar_events;

	struct wmi_pdev_set_wmm_params_arg wmm_params;
	struct completion install_key_done;

	struct completion vdev_setup_done;

	struct workqueue_struct *workqueue;

	/* prevents concurrent FW reconfiguration */
	struct mutex conf_mutex;

	/* protects shared structure data */
	spinlock_t data_lock;

	struct list_head arvifs;
	struct list_head peers;
	wait_queue_head_t peer_mapping_wq;

	/* number of created peers; protected by data_lock */
	int num_peers;

	struct work_struct offchan_tx_work;
	struct sk_buff_head offchan_tx_queue;
	struct completion offchan_tx_completed;
	struct sk_buff *offchan_tx_skb;

	struct work_struct wmi_mgmt_tx_work;
	struct sk_buff_head wmi_mgmt_tx_queue;

	enum ath10k_state state;

	struct work_struct restart_work;

	/* cycle count is reported twice for each visited channel during scan.
	 * access protected by data_lock */
	u32 survey_last_rx_clear_count;
	u32 survey_last_cycle_count;
	struct survey_info survey[ATH10K_NUM_CHANS];

	struct dfs_pattern_detector *dfs_detector;

#ifdef CONFIG_ATH10K_DEBUGFS
	struct ath10k_debug debug;
#endif
};

struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
				  const struct ath10k_hif_ops *hif_ops);
void ath10k_core_destroy(struct ath10k *ar);

int ath10k_core_start(struct ath10k *ar);
int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
void ath10k_core_stop(struct ath10k *ar);
int ath10k_core_register(struct ath10k *ar, u32 chip_id);
void ath10k_core_unregister(struct ath10k *ar);

#endif /* _CORE_H_ */
Commit	Line	Data
5e3dd157 KV	1	/*
	2	* Copyright (c) 2005-2011 Atheros Communications Inc.
	3	* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
	4	*
	5	* Permission to use, copy, modify, and/or distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*/
	17
	18	#ifndef _CORE_H_
	19	#define _CORE_H_
	20
	21	#include <linux/completion.h>
	22	#include <linux/if_ether.h>
	23	#include <linux/types.h>
	24	#include <linux/pci.h>
	25
edb8236d	26	#include "htt.h"
5e3dd157 KV	27	#include "htc.h"
	28	#include "hw.h"
	29	#include "targaddrs.h"
	30	#include "wmi.h"
	31	#include "../ath.h"
	32	#include "../regd.h"
9702c686	33	#include "../dfs_pattern_detector.h"
5e3dd157 KV	34
	35	#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
	36	#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
	37	#define WO(_f) ((_f##_OFFSET) >> 2)
	38
	39	#define ATH10K_SCAN_ID 0
	40	#define WMI_READY_TIMEOUT (5 * HZ)
	41	#define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
2e1dea40	42	#define ATH10K_NUM_CHANS 38
5e3dd157 KV	43
	44	/* Antenna noise floor */
	45	#define ATH10K_DEFAULT_NOISE_FLOOR -95
	46
71098615	47	#define ATH10K_MAX_NUM_MGMT_PENDING 128
5e00d31a	48
5a13e76e KV	49	/* number of failed packets */
	50	#define ATH10K_KICKOUT_THRESHOLD 50
	51
	52	/*
	53	* Use insanely high numbers to make sure that the firmware implementation
	54	* won't start, we have the same functionality already in hostapd. Unit
	55	* is seconds.
	56	*/
	57	#define ATH10K_KEEPALIVE_MIN_IDLE 3747
	58	#define ATH10K_KEEPALIVE_MAX_IDLE 3895
	59	#define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
	60
5e3dd157 KV	61	struct ath10k;
5e3dd157 KV	62
5e3dd157 KV	63	struct ath10k_skb_cb {
5e3dd157 KV	64	dma_addr_t paddr;
5e00d31a	65	u8 vdev_id;
5e3dd157 KV	66
5e3dd157 KV	67	struct {
5e3dd157 KV	68	u8 tid;
5e3dd157 KV	69	bool is_offchan;
a16942e6 MK	70	struct ath10k_htt_txbuf *txbuf;
a16942e6 MK	71	u32 txbuf_paddr;
5e3dd157	72	} __packed htt;
748afc47 MK	73
	74	struct {
	75	bool dtim_zero;
	76	bool deliver_cab;
	77	} bcn;
5e3dd157 KV	78	} __packed;
	79
	80	static inline struct ath10k_skb_cb ATH10K_SKB_CB(struct sk_buff skb)
	81	{
	82	BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
	83	IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
	84	return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
	85	}
	86
5e3dd157 KV	87	static inline u32 host_interest_item_address(u32 item_offset)
	88	{
	89	return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
	90	}
	91
	92	struct ath10k_bmi {
	93	bool done_sent;
	94	};
	95
b3effe61 BM	96	#define ATH10K_MAX_MEM_REQS 16
	97
	98	struct ath10k_mem_chunk {
	99	void *vaddr;
	100	dma_addr_t paddr;
	101	u32 len;
	102	u32 req_id;
	103	};
	104
5e3dd157 KV	105	struct ath10k_wmi {
	106	enum ath10k_htc_ep_id eid;
	107	struct completion service_ready;
	108	struct completion unified_ready;
be8b3943	109	wait_queue_head_t tx_credits_wq;
ce42870e	110	struct wmi_cmd_map *cmd;
6d1506e7	111	struct wmi_vdev_param_map *vdev_param;
226a339b	112	struct wmi_pdev_param_map *pdev_param;
b3effe61 BM	113
	114	u32 num_mem_chunks;
	115	struct ath10k_mem_chunk mem_chunks[ATH10K_MAX_MEM_REQS];
5e3dd157 KV	116	};
	117
	118	struct ath10k_peer_stat {
	119	u8 peer_macaddr[ETH_ALEN];
	120	u32 peer_rssi;
	121	u32 peer_tx_rate;
	122	};
	123
	124	struct ath10k_target_stats {
	125	/* PDEV stats */
	126	s32 ch_noise_floor;
	127	u32 tx_frame_count;
	128	u32 rx_frame_count;
	129	u32 rx_clear_count;
	130	u32 cycle_count;
	131	u32 phy_err_count;
	132	u32 chan_tx_power;
	133
	134	/* PDEV TX stats */
	135	s32 comp_queued;
	136	s32 comp_delivered;
	137	s32 msdu_enqued;
	138	s32 mpdu_enqued;
	139	s32 wmm_drop;
	140	s32 local_enqued;
	141	s32 local_freed;
	142	s32 hw_queued;
	143	s32 hw_reaped;
	144	s32 underrun;
	145	s32 tx_abort;
	146	s32 mpdus_requed;
	147	u32 tx_ko;
	148	u32 data_rc;
	149	u32 self_triggers;
	150	u32 sw_retry_failure;
	151	u32 illgl_rate_phy_err;
	152	u32 pdev_cont_xretry;
	153	u32 pdev_tx_timeout;
	154	u32 pdev_resets;
	155	u32 phy_underrun;
	156	u32 txop_ovf;
	157
	158	/* PDEV RX stats */
	159	s32 mid_ppdu_route_change;
	160	s32 status_rcvd;
	161	s32 r0_frags;
	162	s32 r1_frags;
	163	s32 r2_frags;
	164	s32 r3_frags;
	165	s32 htt_msdus;
	166	s32 htt_mpdus;
	167	s32 loc_msdus;
	168	s32 loc_mpdus;
	169	s32 oversize_amsdu;
	170	s32 phy_errs;
	171	s32 phy_err_drop;
	172	s32 mpdu_errs;
	173
	174	/* VDEV STATS */
	175
	176	/* PEER STATS */
	177	u8 peers;
	178	struct ath10k_peer_stat peer_stat[TARGET_NUM_PEERS];
	179
180	/* TODO: Beacon filter stats */
181
182	};
183
9702c686 JD	184	struct ath10k_dfs_stats {
	185	u32 phy_errors;
	186	u32 pulses_total;
	187	u32 pulses_detected;
	188	u32 pulses_discarded;
	189	u32 radar_detected;
	190	};
	191
5e3dd157 KV	192	#define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
	193
	194	struct ath10k_peer {
	195	struct list_head list;
	196	int vdev_id;
	197	u8 addr[ETH_ALEN];
	198	DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
	199	struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
	200	};
	201
9797febc MK	202	struct ath10k_sta {
	203	struct ath10k_vif *arvif;
	204
	205	/* the following are protected by ar->data_lock */
	206	u32 changed; /* IEEE80211_RC_* */
	207	u32 bw;
	208	u32 nss;
	209	u32 smps;
	210
	211	struct work_struct update_wk;
	212	};
	213
5e3dd157 KV	214	#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
	215
	216	struct ath10k_vif {
0579119f MK	217	struct list_head list;
0579119f MK	218
5e3dd157 KV	219	u32 vdev_id;
	220	enum wmi_vdev_type vdev_type;
	221	enum wmi_vdev_subtype vdev_subtype;
	222	u32 beacon_interval;
	223	u32 dtim_period;
ed54388a	224	struct sk_buff *beacon;
748afc47 MK	225	/* protected by data_lock */
748afc47 MK	226	bool beacon_sent;
5e3dd157 KV	227
	228	struct ath10k *ar;
	229	struct ieee80211_vif *vif;
	230
c930f744 MK	231	bool is_started;
	232	bool is_up;
	233	u32 aid;
	234	u8 bssid[ETH_ALEN];
	235
cc4827b9	236	struct work_struct wep_key_work;
5e3dd157	237	struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
cc4827b9 MK	238	u8 def_wep_key_idx;
cc4827b9 MK	239	u8 def_wep_key_newidx;
5e3dd157 KV	240
	241	u16 tx_seq_no;
	242
	243	union {
	244	struct {
5e3dd157 KV	245	u32 uapsd;
	246	} sta;
	247	struct {
	248	/* 127 stations; wmi limit */
	249	u8 tim_bitmap[16];
	250	u8 tim_len;
	251	u32 ssid_len;
	252	u8 ssid[IEEE80211_MAX_SSID_LEN];
	253	bool hidden_ssid;
	254	/* P2P_IE with NoA attribute for P2P_GO case */
	255	u32 noa_len;
	256	u8 *noa_data;
	257	} ap;
5e3dd157	258	} u;
51ab1a0a JD	259
	260	u8 fixed_rate;
	261	u8 fixed_nss;
9f81f725	262	u8 force_sgi;
5e3dd157 KV	263	};
	264
	265	struct ath10k_vif_iter {
	266	u32 vdev_id;
	267	struct ath10k_vif *arvif;
	268	};
	269
	270	struct ath10k_debug {
	271	struct dentry *debugfs_phy;
	272
	273	struct ath10k_target_stats target_stats;
	274	u32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE];
	275
	276	struct completion event_stats_compl;
a3d135e5 KV	277
	278	unsigned long htt_stats_mask;
	279	struct delayed_work htt_stats_dwork;
9702c686 JD	280	struct ath10k_dfs_stats dfs_stats;
9702c686 JD	281	struct ath_dfs_pool_stats dfs_pool_stats;
f118a3e5 KV	282
f118a3e5 KV	283	u32 fw_dbglog_mask;
5e3dd157 KV	284	};
5e3dd157 KV	285
f7843d7f MK	286	enum ath10k_state {
	287	ATH10K_STATE_OFF = 0,
	288	ATH10K_STATE_ON,
affd3217 MK	289
	290	/* When doing firmware recovery the device is first powered down.
	291	* mac80211 is supposed to call in to start() hook later on. It is
	292	* however possible that driver unloading and firmware crash overlap.
	293	* mac80211 can wait on conf_mutex in stop() while the device is
	294	* stopped in ath10k_core_restart() work holding conf_mutex. The state
	295	* RESTARTED means that the device is up and mac80211 has started hw
	296	* reconfiguration. Once mac80211 is done with the reconfiguration we
	297	* set the state to STATE_ON in restart_complete(). */
	298	ATH10K_STATE_RESTARTING,
	299	ATH10K_STATE_RESTARTED,
	300
	301	/* The device has crashed while restarting hw. This state is like ON
	302	* but commands are blocked in HTC and -ECOMM response is given. This
	303	* prevents completion timeouts and makes the driver more responsive to
	304	* userspace commands. This is also prevents recursive recovery. */
	305	ATH10K_STATE_WEDGED,
f7843d7f MK	306	};
f7843d7f MK	307
0d9b0438 MK	308	enum ath10k_fw_features {
	309	/* wmi_mgmt_rx_hdr contains extra RSSI information */
	310	ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
	311
ce42870e BM	312	/* firmware from 10X branch */
	313	ATH10K_FW_FEATURE_WMI_10X = 1,
	314
5e00d31a BM	315	/* firmware support tx frame management over WMI, otherwise it's HTT */
	316	ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
	317
d354181f BM	318	/* Firmware does not support P2P */
	319	ATH10K_FW_FEATURE_NO_P2P = 3,
	320
0d9b0438 MK	321	/* keep last */
	322	ATH10K_FW_FEATURE_COUNT,
	323	};
	324
e8a50f8b MP	325	enum ath10k_dev_flags {
	326	/* Indicates that ath10k device is during CAC phase of DFS */
	327	ATH10K_CAC_RUNNING,
650b91fb	328	ATH10K_FLAG_FIRST_BOOT_DONE,
e8a50f8b MP	329	};
e8a50f8b MP	330
5e3dd157 KV	331	struct ath10k {
	332	struct ath_common ath_common;
	333	struct ieee80211_hw *hw;
	334	struct device *dev;
	335	u8 mac_addr[ETH_ALEN];
	336
e01ae68c	337	u32 chip_id;
5e3dd157 KV	338	u32 target_version;
	339	u8 fw_version_major;
	340	u32 fw_version_minor;
	341	u16 fw_version_release;
	342	u16 fw_version_build;
	343	u32 phy_capability;
	344	u32 hw_min_tx_power;
	345	u32 hw_max_tx_power;
	346	u32 ht_cap_info;
	347	u32 vht_cap_info;
8865bee4	348	u32 num_rf_chains;
5e3dd157	349
0d9b0438 MK	350	DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
0d9b0438 MK	351
5e3dd157 KV	352	struct targetdef *targetdef;
	353	struct hostdef *hostdef;
	354
	355	bool p2p;
	356
	357	struct {
	358	void *priv;
5e3dd157 KV	359	const struct ath10k_hif_ops *ops;
	360	} hif;
	361
9042e17d	362	struct completion target_suspend;
5e3dd157 KV	363
5e3dd157 KV	364	struct ath10k_bmi bmi;
edb8236d	365	struct ath10k_wmi wmi;
cd003fad	366	struct ath10k_htc htc;
edb8236d	367	struct ath10k_htt htt;
5e3dd157 KV	368
	369	struct ath10k_hw_params {
	370	u32 id;
	371	const char *name;
	372	u32 patch_load_addr;
	373
	374	struct ath10k_hw_params_fw {
	375	const char *dir;
	376	const char *fw;
	377	const char *otp;
	378	const char *board;
	379	} fw;
	380	} hw_params;
	381
36527916	382	const struct firmware *board;
958df3a0 KV	383	const void *board_data;
	384	size_t board_len;
	385
29385057	386	const struct firmware *otp;
958df3a0 KV	387	const void *otp_data;
	388	size_t otp_len;
	389
29385057	390	const struct firmware *firmware;
958df3a0 KV	391	const void *firmware_data;
958df3a0 KV	392	size_t firmware_len;
29385057	393
1a222435 KV	394	int fw_api;
1a222435 KV	395
5e3dd157 KV	396	struct {
	397	struct completion started;
	398	struct completion completed;
	399	struct completion on_channel;
	400	struct timer_list timeout;
	401	bool is_roc;
	402	bool in_progress;
	403	bool aborting;
	404	int vdev_id;
	405	int roc_freq;
	406	} scan;
	407
	408	struct {
	409	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
	410	} mac;
	411
	412	/* should never be NULL; needed for regular htt rx */
	413	struct ieee80211_channel *rx_channel;
	414
	415	/* valid during scan; needed for mgmt rx during scan */
	416	struct ieee80211_channel *scan_channel;
	417
c930f744 MK	418	/* current operating channel definition */
	419	struct cfg80211_chan_def chandef;
	420
5e3dd157 KV	421	int free_vdev_map;
	422	int monitor_vdev_id;
	423	bool monitor_enabled;
	424	bool monitor_present;
	425	unsigned int filter_flags;
e8a50f8b	426	unsigned long dev_flags;
7d9b40b4	427	u32 dfs_block_radar_events;
5e3dd157 KV	428
	429	struct wmi_pdev_set_wmm_params_arg wmm_params;
	430	struct completion install_key_done;
	431
	432	struct completion vdev_setup_done;
	433
	434	struct workqueue_struct *workqueue;
	435
	436	/* prevents concurrent FW reconfiguration */
	437	struct mutex conf_mutex;
	438
	439	/* protects shared structure data */
	440	spinlock_t data_lock;
	441
0579119f	442	struct list_head arvifs;
5e3dd157 KV	443	struct list_head peers;
	444	wait_queue_head_t peer_mapping_wq;
	445
0e759f36 BM	446	/* number of created peers; protected by data_lock */
	447	int num_peers;
	448
5e3dd157 KV	449	struct work_struct offchan_tx_work;
	450	struct sk_buff_head offchan_tx_queue;
	451	struct completion offchan_tx_completed;
	452	struct sk_buff *offchan_tx_skb;
	453
5e00d31a BM	454	struct work_struct wmi_mgmt_tx_work;
	455	struct sk_buff_head wmi_mgmt_tx_queue;
	456
f7843d7f MK	457	enum ath10k_state state;
f7843d7f MK	458
affd3217 MK	459	struct work_struct restart_work;
affd3217 MK	460
2e1dea40 MK	461	/* cycle count is reported twice for each visited channel during scan.
	462	* access protected by data_lock */
	463	u32 survey_last_rx_clear_count;
	464	u32 survey_last_cycle_count;
	465	struct survey_info survey[ATH10K_NUM_CHANS];
	466
9702c686 JD	467	struct dfs_pattern_detector *dfs_detector;
9702c686 JD	468
5e3dd157 KV	469	#ifdef CONFIG_ATH10K_DEBUGFS
	470	struct ath10k_debug debug;
	471	#endif
	472	};
	473
	474	struct ath10k ath10k_core_create(void hif_priv, struct device *dev,
5e3dd157 KV	475	const struct ath10k_hif_ops *hif_ops);
	476	void ath10k_core_destroy(struct ath10k *ar);
	477
dd30a36e	478	int ath10k_core_start(struct ath10k *ar);
00f5482b	479	int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
dd30a36e	480	void ath10k_core_stop(struct ath10k *ar);
e01ae68c	481	int ath10k_core_register(struct ath10k *ar, u32 chip_id);
5e3dd157 KV	482	void ath10k_core_unregister(struct ath10k *ar);
5e3dd157 KV	483
5e3dd157	484	#endif /* _CORE_H_ */