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ath10k: kill not needed fields from htt_rx_info
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / htt_rx.c
CommitLineData
5e3dd157
KV		 1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
edb8236d 18#include "core.h"
5e3dd157
KV		 19#include "htc.h"
20#include "htt.h"
21#include "txrx.h"
22#include "debug.h"
a9bf0506 23#include "trace.h"
5e3dd157
KV		 24
25#include <linux/log2.h>
26
27/* slightly larger than one large A-MPDU */
28#define HTT_RX_RING_SIZE_MIN 128
29
30/* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
31#define HTT_RX_RING_SIZE_MAX 2048
32
33#define HTT_RX_AVG_FRM_BYTES 1000
34
35/* ms, very conservative */
36#define HTT_RX_HOST_LATENCY_MAX_MS 20
37
38/* ms, conservative */
39#define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
40
41/* when under memory pressure rx ring refill may fail and needs a retry */
42#define HTT_RX_RING_REFILL_RETRY_MS 50
43
f6dc2095
MK		 44
45static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
6c5151a9 46static void ath10k_htt_txrx_compl_task(unsigned long ptr);
f6dc2095 47
5e3dd157
KV		 48static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
49{
50 int size;
51
52 /*
53 * It is expected that the host CPU will typically be able to
54 * service the rx indication from one A-MPDU before the rx
55 * indication from the subsequent A-MPDU happens, roughly 1-2 ms
56 * later. However, the rx ring should be sized very conservatively,
57 * to accomodate the worst reasonable delay before the host CPU
58 * services a rx indication interrupt.
59 *
60 * The rx ring need not be kept full of empty buffers. In theory,
61 * the htt host SW can dynamically track the low-water mark in the
62 * rx ring, and dynamically adjust the level to which the rx ring
63 * is filled with empty buffers, to dynamically meet the desired
64 * low-water mark.
65 *
66 * In contrast, it's difficult to resize the rx ring itself, once
67 * it's in use. Thus, the ring itself should be sized very
68 * conservatively, while the degree to which the ring is filled
69 * with empty buffers should be sized moderately conservatively.
70 */
71
72 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
73 size =
74 htt->max_throughput_mbps +
75 1000 /
76 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
77
78 if (size < HTT_RX_RING_SIZE_MIN)
79 size = HTT_RX_RING_SIZE_MIN;
80
81 if (size > HTT_RX_RING_SIZE_MAX)
82 size = HTT_RX_RING_SIZE_MAX;
83
84 size = roundup_pow_of_two(size);
85
86 return size;
87}
88
89static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
90{
91 int size;
92
93 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
94 size =
95 htt->max_throughput_mbps *
96 1000 /
97 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
98
99 /*
100 * Make sure the fill level is at least 1 less than the ring size.
101 * Leaving 1 element empty allows the SW to easily distinguish
102 * between a full ring vs. an empty ring.
103 */
104 if (size >= htt->rx_ring.size)
105 size = htt->rx_ring.size - 1;
106
107 return size;
108}
109
110static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
111{
112 struct sk_buff *skb;
113 struct ath10k_skb_cb *cb;
114 int i;
115
116 for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
117 skb = htt->rx_ring.netbufs_ring[i];
118 cb = ATH10K_SKB_CB(skb);
119 dma_unmap_single(htt->ar->dev, cb->paddr,
120 skb->len + skb_tailroom(skb),
121 DMA_FROM_DEVICE);
122 dev_kfree_skb_any(skb);
123 }
124
125 htt->rx_ring.fill_cnt = 0;
126}
127
128static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
129{
130 struct htt_rx_desc *rx_desc;
131 struct sk_buff *skb;
132 dma_addr_t paddr;
133 int ret = 0, idx;
134
135 idx = __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr));
136 while (num > 0) {
137 skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
138 if (!skb) {
139 ret = -ENOMEM;
140 goto fail;
141 }
142
143 if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
144 skb_pull(skb,
145 PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
146 skb->data);
147
148 /* Clear rx_desc attention word before posting to Rx ring */
149 rx_desc = (struct htt_rx_desc *)skb->data;
150 rx_desc->attention.flags = __cpu_to_le32(0);
151
152 paddr = dma_map_single(htt->ar->dev, skb->data,
153 skb->len + skb_tailroom(skb),
154 DMA_FROM_DEVICE);
155
156 if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
157 dev_kfree_skb_any(skb);
158 ret = -ENOMEM;
159 goto fail;
160 }
161
162 ATH10K_SKB_CB(skb)->paddr = paddr;
163 htt->rx_ring.netbufs_ring[idx] = skb;
164 htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
165 htt->rx_ring.fill_cnt++;
166
167 num--;
168 idx++;
169 idx &= htt->rx_ring.size_mask;
170 }
171
172fail:
173 *(htt->rx_ring.alloc_idx.vaddr) = __cpu_to_le32(idx);
174 return ret;
175}
176
177static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
178{
179 lockdep_assert_held(&htt->rx_ring.lock);
180 return __ath10k_htt_rx_ring_fill_n(htt, num);
181}
182
183static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
184{
6e712d42 185 int ret, num_deficit, num_to_fill;
5e3dd157 186
6e712d42
MK		 187 /* Refilling the whole RX ring buffer proves to be a bad idea. The
188 * reason is RX may take up significant amount of CPU cycles and starve
189 * other tasks, e.g. TX on an ethernet device while acting as a bridge
190 * with ath10k wlan interface. This ended up with very poor performance
191 * once CPU the host system was overwhelmed with RX on ath10k.
192 *
193 * By limiting the number of refills the replenishing occurs
194 * progressively. This in turns makes use of the fact tasklets are
195 * processed in FIFO order. This means actual RX processing can starve
196 * out refilling. If there's not enough buffers on RX ring FW will not
197 * report RX until it is refilled with enough buffers. This
198 * automatically balances load wrt to CPU power.
199 *
200 * This probably comes at a cost of lower maximum throughput but
201 * improves the avarage and stability. */
5e3dd157 202 spin_lock_bh(&htt->rx_ring.lock);
6e712d42
MK		 203 num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
204 num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
205 num_deficit -= num_to_fill;
5e3dd157
KV		 206 ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
207 if (ret == -ENOMEM) {
208 /*
209 * Failed to fill it to the desired level -
210 * we'll start a timer and try again next time.
211 * As long as enough buffers are left in the ring for
212 * another A-MPDU rx, no special recovery is needed.
213 */
214 mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
215 msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
6e712d42
MK		 216 } else if (num_deficit > 0) {
217 tasklet_schedule(&htt->rx_replenish_task);
5e3dd157
KV		 218 }
219 spin_unlock_bh(&htt->rx_ring.lock);
220}
221
222static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
223{
224 struct ath10k_htt *htt = (struct ath10k_htt *)arg;
225 ath10k_htt_rx_msdu_buff_replenish(htt);
226}
227
5e3dd157
KV		 228void ath10k_htt_rx_detach(struct ath10k_htt *htt)
229{
230 int sw_rd_idx = htt->rx_ring.sw_rd_idx.msdu_payld;
231
232 del_timer_sync(&htt->rx_ring.refill_retry_timer);
6e712d42 233 tasklet_kill(&htt->rx_replenish_task);
6c5151a9
MK		 234 tasklet_kill(&htt->txrx_compl_task);
235
236 skb_queue_purge(&htt->tx_compl_q);
237 skb_queue_purge(&htt->rx_compl_q);
5e3dd157
KV		 238
239 while (sw_rd_idx != __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr))) {
240 struct sk_buff *skb =
241 htt->rx_ring.netbufs_ring[sw_rd_idx];
242 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
243
244 dma_unmap_single(htt->ar->dev, cb->paddr,
245 skb->len + skb_tailroom(skb),
246 DMA_FROM_DEVICE);
247 dev_kfree_skb_any(htt->rx_ring.netbufs_ring[sw_rd_idx]);
248 sw_rd_idx++;
249 sw_rd_idx &= htt->rx_ring.size_mask;
250 }
251
252 dma_free_coherent(htt->ar->dev,
253 (htt->rx_ring.size *
254 sizeof(htt->rx_ring.paddrs_ring)),
255 htt->rx_ring.paddrs_ring,
256 htt->rx_ring.base_paddr);
257
258 dma_free_coherent(htt->ar->dev,
259 sizeof(*htt->rx_ring.alloc_idx.vaddr),
260 htt->rx_ring.alloc_idx.vaddr,
261 htt->rx_ring.alloc_idx.paddr);
262
263 kfree(htt->rx_ring.netbufs_ring);
264}
265
266static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
267{
268 int idx;
269 struct sk_buff *msdu;
270
45967089 271 lockdep_assert_held(&htt->rx_ring.lock);
5e3dd157 272
8d60ee87
MK		 273 if (htt->rx_ring.fill_cnt == 0) {
274 ath10k_warn("tried to pop sk_buff from an empty rx ring\n");
275 return NULL;
276 }
5e3dd157
KV		 277
278 idx = htt->rx_ring.sw_rd_idx.msdu_payld;
279 msdu = htt->rx_ring.netbufs_ring[idx];
280
281 idx++;
282 idx &= htt->rx_ring.size_mask;
283 htt->rx_ring.sw_rd_idx.msdu_payld = idx;
284 htt->rx_ring.fill_cnt--;
285
5e3dd157
KV		 286 return msdu;
287}
288
289static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb)
290{
291 struct sk_buff *next;
292
293 while (skb) {
294 next = skb->next;
295 dev_kfree_skb_any(skb);
296 skb = next;
297 }
298}
299
300static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
301 u8 **fw_desc, int *fw_desc_len,
302 struct sk_buff **head_msdu,
303 struct sk_buff **tail_msdu)
304{
305 int msdu_len, msdu_chaining = 0;
306 struct sk_buff *msdu;
307 struct htt_rx_desc *rx_desc;
308
45967089
MK		 309 lockdep_assert_held(&htt->rx_ring.lock);
310
5e3dd157
KV		 311 if (htt->rx_confused) {
312 ath10k_warn("htt is confused. refusing rx\n");
313 return 0;
314 }
315
316 msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt);
317 while (msdu) {
318 int last_msdu, msdu_len_invalid, msdu_chained;
319
320 dma_unmap_single(htt->ar->dev,
321 ATH10K_SKB_CB(msdu)->paddr,
322 msdu->len + skb_tailroom(msdu),
323 DMA_FROM_DEVICE);
324
75fb2f94 325 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ",
5e3dd157
KV		 326 msdu->data, msdu->len + skb_tailroom(msdu));
327
328 rx_desc = (struct htt_rx_desc *)msdu->data;
329
330 /* FIXME: we must report msdu payload since this is what caller
331 * expects now */
332 skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
333 skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
334
335 /*
336 * Sanity check - confirm the HW is finished filling in the
337 * rx data.
338 * If the HW and SW are working correctly, then it's guaranteed
339 * that the HW's MAC DMA is done before this point in the SW.
340 * To prevent the case that we handle a stale Rx descriptor,
341 * just assert for now until we have a way to recover.
342 */
343 if (!(__le32_to_cpu(rx_desc->attention.flags)
344 & RX_ATTENTION_FLAGS_MSDU_DONE)) {
345 ath10k_htt_rx_free_msdu_chain(*head_msdu);
346 *head_msdu = NULL;
347 msdu = NULL;
348 ath10k_err("htt rx stopped. cannot recover\n");
349 htt->rx_confused = true;
350 break;
351 }
352
353 /*
354 * Copy the FW rx descriptor for this MSDU from the rx
355 * indication message into the MSDU's netbuf. HL uses the
356 * same rx indication message definition as LL, and simply
357 * appends new info (fields from the HW rx desc, and the
358 * MSDU payload itself). So, the offset into the rx
359 * indication message only has to account for the standard
360 * offset of the per-MSDU FW rx desc info within the
361 * message, and how many bytes of the per-MSDU FW rx desc
362 * info have already been consumed. (And the endianness of
363 * the host, since for a big-endian host, the rx ind
364 * message contents, including the per-MSDU rx desc bytes,
365 * were byteswapped during upload.)
366 */
367 if (*fw_desc_len > 0) {
368 rx_desc->fw_desc.info0 = **fw_desc;
369 /*
370 * The target is expected to only provide the basic
371 * per-MSDU rx descriptors. Just to be sure, verify
372 * that the target has not attached extension data
373 * (e.g. LRO flow ID).
374 */
375
376 /* or more, if there's extension data */
377 (*fw_desc)++;
378 (*fw_desc_len)--;
379 } else {
380 /*
381 * When an oversized AMSDU happened, FW will lost
382 * some of MSDU status - in this case, the FW
383 * descriptors provided will be less than the
384 * actual MSDUs inside this MPDU. Mark the FW
385 * descriptors so that it will still deliver to
386 * upper stack, if no CRC error for this MPDU.
387 *
388 * FIX THIS - the FW descriptors are actually for
389 * MSDUs in the end of this A-MSDU instead of the
390 * beginning.
391 */
392 rx_desc->fw_desc.info0 = 0;
393 }
394
395 msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
396 & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
397 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
398 msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
399 RX_MSDU_START_INFO0_MSDU_LENGTH);
400 msdu_chained = rx_desc->frag_info.ring2_more_count;
bfa35368 401 msdu_chaining = msdu_chained;
5e3dd157
KV		 402
403 if (msdu_len_invalid)
404 msdu_len = 0;
405
406 skb_trim(msdu, 0);
407 skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
408 msdu_len -= msdu->len;
409
410 /* FIXME: Do chained buffers include htt_rx_desc or not? */
411 while (msdu_chained--) {
412 struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
413
414 dma_unmap_single(htt->ar->dev,
415 ATH10K_SKB_CB(next)->paddr,
416 next->len + skb_tailroom(next),
417 DMA_FROM_DEVICE);
418
75fb2f94
BG		 419 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL,
420 "htt rx chained: ", next->data,
5e3dd157
KV		 421 next->len + skb_tailroom(next));
422
423 skb_trim(next, 0);
424 skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE));
425 msdu_len -= next->len;
426
427 msdu->next = next;
428 msdu = next;
5e3dd157
KV		 429 }
430
5e3dd157
KV		 431 last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
432 RX_MSDU_END_INFO0_LAST_MSDU;
433
434 if (last_msdu) {
435 msdu->next = NULL;
436 break;
437 } else {
438 struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
439 msdu->next = next;
440 msdu = next;
441 }
442 }
443 *tail_msdu = msdu;
444
445 /*
446 * Don't refill the ring yet.
447 *
448 * First, the elements popped here are still in use - it is not
449 * safe to overwrite them until the matching call to
450 * mpdu_desc_list_next. Second, for efficiency it is preferable to
451 * refill the rx ring with 1 PPDU's worth of rx buffers (something
452 * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
453 * (something like 3 buffers). Consequently, we'll rely on the txrx
454 * SW to tell us when it is done pulling all the PPDU's rx buffers
455 * out of the rx ring, and then refill it just once.
456 */
457
458 return msdu_chaining;
459}
460
6e712d42
MK		 461static void ath10k_htt_rx_replenish_task(unsigned long ptr)
462{
463 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
464 ath10k_htt_rx_msdu_buff_replenish(htt);
465}
466
5e3dd157
KV		 467int ath10k_htt_rx_attach(struct ath10k_htt *htt)
468{
469 dma_addr_t paddr;
470 void *vaddr;
471 struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
472
473 htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
474 if (!is_power_of_2(htt->rx_ring.size)) {
475 ath10k_warn("htt rx ring size is not power of 2\n");
476 return -EINVAL;
477 }
478
479 htt->rx_ring.size_mask = htt->rx_ring.size - 1;
480
481 /*
482 * Set the initial value for the level to which the rx ring
483 * should be filled, based on the max throughput and the
484 * worst likely latency for the host to fill the rx ring
485 * with new buffers. In theory, this fill level can be
486 * dynamically adjusted from the initial value set here, to
487 * reflect the actual host latency rather than a
488 * conservative assumption about the host latency.
489 */
490 htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
491
492 htt->rx_ring.netbufs_ring =
493 kmalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
494 GFP_KERNEL);
495 if (!htt->rx_ring.netbufs_ring)
496 goto err_netbuf;
497
498 vaddr = dma_alloc_coherent(htt->ar->dev,
499 (htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring)),
500 &paddr, GFP_DMA);
501 if (!vaddr)
502 goto err_dma_ring;
503
504 htt->rx_ring.paddrs_ring = vaddr;
505 htt->rx_ring.base_paddr = paddr;
506
507 vaddr = dma_alloc_coherent(htt->ar->dev,
508 sizeof(*htt->rx_ring.alloc_idx.vaddr),
509 &paddr, GFP_DMA);
510 if (!vaddr)
511 goto err_dma_idx;
512
513 htt->rx_ring.alloc_idx.vaddr = vaddr;
514 htt->rx_ring.alloc_idx.paddr = paddr;
515 htt->rx_ring.sw_rd_idx.msdu_payld = 0;
516 *htt->rx_ring.alloc_idx.vaddr = 0;
517
518 /* Initialize the Rx refill retry timer */
519 setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
520
521 spin_lock_init(&htt->rx_ring.lock);
522
523 htt->rx_ring.fill_cnt = 0;
524 if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
525 goto err_fill_ring;
526
6e712d42
MK		 527 tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
528 (unsigned long)htt);
529
6c5151a9
MK		 530 skb_queue_head_init(&htt->tx_compl_q);
531 skb_queue_head_init(&htt->rx_compl_q);
532
533 tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
534 (unsigned long)htt);
535
aad0b65f 536 ath10k_dbg(ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
5e3dd157
KV		 537 htt->rx_ring.size, htt->rx_ring.fill_level);
538 return 0;
539
540err_fill_ring:
541 ath10k_htt_rx_ring_free(htt);
542 dma_free_coherent(htt->ar->dev,
543 sizeof(*htt->rx_ring.alloc_idx.vaddr),
544 htt->rx_ring.alloc_idx.vaddr,
545 htt->rx_ring.alloc_idx.paddr);
546err_dma_idx:
547 dma_free_coherent(htt->ar->dev,
548 (htt->rx_ring.size *
549 sizeof(htt->rx_ring.paddrs_ring)),
550 htt->rx_ring.paddrs_ring,
551 htt->rx_ring.base_paddr);
552err_dma_ring:
553 kfree(htt->rx_ring.netbufs_ring);
554err_netbuf:
555 return -ENOMEM;
556}
557
558static int ath10k_htt_rx_crypto_param_len(enum htt_rx_mpdu_encrypt_type type)
559{
560 switch (type) {
561 case HTT_RX_MPDU_ENCRYPT_WEP40:
562 case HTT_RX_MPDU_ENCRYPT_WEP104:
563 return 4;
564 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
565 case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */
566 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
567 case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */
568 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
569 return 8;
570 case HTT_RX_MPDU_ENCRYPT_NONE:
571 return 0;
572 }
573
574 ath10k_warn("unknown encryption type %d\n", type);
575 return 0;
576}
577
578static int ath10k_htt_rx_crypto_tail_len(enum htt_rx_mpdu_encrypt_type type)
579{
580 switch (type) {
581 case HTT_RX_MPDU_ENCRYPT_NONE:
582 case HTT_RX_MPDU_ENCRYPT_WEP40:
583 case HTT_RX_MPDU_ENCRYPT_WEP104:
584 case HTT_RX_MPDU_ENCRYPT_WEP128:
585 case HTT_RX_MPDU_ENCRYPT_WAPI:
586 return 0;
587 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
588 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
589 return 4;
590 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
591 return 8;
592 }
593
594 ath10k_warn("unknown encryption type %d\n", type);
595 return 0;
596}
597
598/* Applies for first msdu in chain, before altering it. */
599static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
600{
601 struct htt_rx_desc *rxd;
602 enum rx_msdu_decap_format fmt;
603
604 rxd = (void *)skb->data - sizeof(*rxd);
605 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
606 RX_MSDU_START_INFO1_DECAP_FORMAT);
607
608 if (fmt == RX_MSDU_DECAP_RAW)
609 return (void *)skb->data;
610 else
611 return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
612}
613
614/* This function only applies for first msdu in an msdu chain */
615static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
616{
617 if (ieee80211_is_data_qos(hdr->frame_control)) {
618 u8 *qc = ieee80211_get_qos_ctl(hdr);
619 if (qc[0] & 0x80)
620 return true;
621 }
622 return false;
623}
624
f6dc2095
MK		 625struct rfc1042_hdr {
626 u8 llc_dsap;
627 u8 llc_ssap;
628 u8 llc_ctrl;
629 u8 snap_oui[3];
630 __be16 snap_type;
631} __packed;
632
633struct amsdu_subframe_hdr {
634 u8 dst[ETH_ALEN];
635 u8 src[ETH_ALEN];
636 __be16 len;
637} __packed;
638
73539b40
JD		 639static const u8 rx_legacy_rate_idx[] = {
640 3, /* 0x00 - 11Mbps */
641 2, /* 0x01 - 5.5Mbps */
642 1, /* 0x02 - 2Mbps */
643 0, /* 0x03 - 1Mbps */
644 3, /* 0x04 - 11Mbps */
645 2, /* 0x05 - 5.5Mbps */
646 1, /* 0x06 - 2Mbps */
647 0, /* 0x07 - 1Mbps */
648 10, /* 0x08 - 48Mbps */
649 8, /* 0x09 - 24Mbps */
650 6, /* 0x0A - 12Mbps */
651 4, /* 0x0B - 6Mbps */
652 11, /* 0x0C - 54Mbps */
653 9, /* 0x0D - 36Mbps */
654 7, /* 0x0E - 18Mbps */
655 5, /* 0x0F - 9Mbps */
656};
657
87326c97 658static void ath10k_htt_rx_h_rates(struct ath10k *ar,
cfadd9ba 659 enum ieee80211_band band,
87326c97 660 u8 info0, u32 info1, u32 info2,
cfadd9ba 661 struct ieee80211_rx_status *status)
73539b40
JD		 662{
663 u8 cck, rate, rate_idx, bw, sgi, mcs, nss;
73539b40
JD		 664 u8 preamble = 0;
665
666 /* Check if valid fields */
667 if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID))
668 return;
669
670 preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE);
671
672 switch (preamble) {
673 case HTT_RX_LEGACY:
674 cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK;
675 rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE);
676 rate_idx = 0;
677
678 if (rate < 0x08 || rate > 0x0F)
679 break;
680
681 switch (band) {
682 case IEEE80211_BAND_2GHZ:
683 if (cck)
684 rate &= ~BIT(3);
685 rate_idx = rx_legacy_rate_idx[rate];
686 break;
687 case IEEE80211_BAND_5GHZ:
688 rate_idx = rx_legacy_rate_idx[rate];
689 /* We are using same rate table registering
690 HW - ath10k_rates[]. In case of 5GHz skip
691 CCK rates, so -4 here */
692 rate_idx -= 4;
693 break;
694 default:
695 break;
696 }
697
698 status->rate_idx = rate_idx;
699 break;
700 case HTT_RX_HT:
701 case HTT_RX_HT_WITH_TXBF:
702 /* HT-SIG - Table 20-11 in info1 and info2 */
703 mcs = info1 & 0x1F;
704 nss = mcs >> 3;
705 bw = (info1 >> 7) & 1;
706 sgi = (info2 >> 7) & 1;
707
708 status->rate_idx = mcs;
709 status->flag |= RX_FLAG_HT;
710 if (sgi)
711 status->flag |= RX_FLAG_SHORT_GI;
712 if (bw)
713 status->flag |= RX_FLAG_40MHZ;
714 break;
715 case HTT_RX_VHT:
716 case HTT_RX_VHT_WITH_TXBF:
717 /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
718 TODO check this */
719 mcs = (info2 >> 4) & 0x0F;
720 nss = ((info1 >> 10) & 0x07) + 1;
721 bw = info1 & 3;
722 sgi = info2 & 1;
723
724 status->rate_idx = mcs;
725 status->vht_nss = nss;
726
727 if (sgi)
728 status->flag |= RX_FLAG_SHORT_GI;
729
730 switch (bw) {
731 /* 20MHZ */
732 case 0:
733 break;
734 /* 40MHZ */
735 case 1:
736 status->flag |= RX_FLAG_40MHZ;
737 break;
738 /* 80MHZ */
739 case 2:
740 status->vht_flag |= RX_VHT_FLAG_80MHZ;
741 }
742
743 status->flag |= RX_FLAG_VHT;
744 break;
745 default:
746 break;
747 }
748}
749
87326c97
JD		 750static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt,
751 struct htt_rx_info *info,
752 enum htt_rx_mpdu_encrypt_type enctype)
753{
754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)info->skb->data;
755
756
757 if (enctype == HTT_RX_MPDU_ENCRYPT_NONE) {
758 info->rx_status.flag &= ~(RX_FLAG_DECRYPTED |
759 RX_FLAG_IV_STRIPPED |
760 RX_FLAG_MMIC_STRIPPED);
761 return;
762 }
763
764 info->rx_status.flag |= RX_FLAG_DECRYPTED |
765 RX_FLAG_IV_STRIPPED |
766 RX_FLAG_MMIC_STRIPPED;
767 hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) &
768 ~IEEE80211_FCTL_PROTECTED);
769}
770
36653f05
JD		 771static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
772 struct ieee80211_rx_status *status)
773{
774 struct ieee80211_channel *ch;
775
776 spin_lock_bh(&ar->data_lock);
777 ch = ar->scan_channel;
778 if (!ch)
779 ch = ar->rx_channel;
780 spin_unlock_bh(&ar->data_lock);
781
782 if (!ch)
783 return false;
784
785 status->band = ch->band;
786 status->freq = ch->center_freq;
787
788 return true;
789}
790
73539b40
JD		 791static void ath10k_process_rx(struct ath10k *ar, struct htt_rx_info *info)
792{
793 struct ieee80211_rx_status *status;
73539b40
JD		 794
795 status = IEEE80211_SKB_RXCB(info->skb);
8f739db0 796 memcpy(status, &info->rx_status, sizeof(*status));
73539b40 797
73539b40
JD		 798 ath10k_dbg(ATH10K_DBG_DATA,
799 "rx skb %p len %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i\n",
800 info->skb,
801 info->skb->len,
802 status->flag == 0 ? "legacy" : "",
803 status->flag & RX_FLAG_HT ? "ht" : "",
804 status->flag & RX_FLAG_VHT ? "vht" : "",
805 status->flag & RX_FLAG_40MHZ ? "40" : "",
806 status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "",
807 status->flag & RX_FLAG_SHORT_GI ? "sgi " : "",
808 status->rate_idx,
809 status->vht_nss,
810 status->freq,
87326c97
JD		 811 status->band, status->flag,
812 !!(status->flag & RX_FLAG_FAILED_FCS_CRC));
73539b40
JD		 813 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
814 info->skb->data, info->skb->len);
815
816 ieee80211_rx(ar->hw, info->skb);
817}
818
d960c369
MK		 819static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr)
820{
821 /* nwifi header is padded to 4 bytes. this fixes 4addr rx */
822 return round_up(ieee80211_hdrlen(hdr->frame_control), 4);
823}
824
f6dc2095
MK		 825static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
826 struct htt_rx_info *info)
5e3dd157
KV		 827{
828 struct htt_rx_desc *rxd;
5e3dd157 829 struct sk_buff *first;
5e3dd157
KV		 830 struct sk_buff *skb = info->skb;
831 enum rx_msdu_decap_format fmt;
832 enum htt_rx_mpdu_encrypt_type enctype;
f6dc2095 833 struct ieee80211_hdr *hdr;
784f69d3 834 u8 hdr_buf[64], addr[ETH_ALEN], *qos;
5e3dd157 835 unsigned int hdr_len;
5e3dd157
KV		 836
837 rxd = (void *)skb->data - sizeof(*rxd);
5e3dd157
KV		 838 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
839 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
840
f6dc2095
MK		 841 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
842 hdr_len = ieee80211_hdrlen(hdr->frame_control);
843 memcpy(hdr_buf, hdr, hdr_len);
844 hdr = (struct ieee80211_hdr *)hdr_buf;
5e3dd157 845
5e3dd157
KV		 846 first = skb;
847 while (skb) {
848 void *decap_hdr;
f6dc2095 849 int len;
5e3dd157
KV		 850
851 rxd = (void *)skb->data - sizeof(*rxd);
852 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
f6dc2095 853 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV		 854 decap_hdr = (void *)rxd->rx_hdr_status;
855
f6dc2095 856 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
5e3dd157 857
f6dc2095
MK		 858 /* First frame in an A-MSDU chain has more decapped data. */
859 if (skb == first) {
860 len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
861 len += round_up(ath10k_htt_rx_crypto_param_len(enctype),
862 4);
863 decap_hdr += len;
5e3dd157
KV		 864 }
865
f6dc2095
MK		 866 switch (fmt) {
867 case RX_MSDU_DECAP_RAW:
e3fbf8d2 868 /* remove trailing FCS */
f6dc2095
MK		 869 skb_trim(skb, skb->len - FCS_LEN);
870 break;
871 case RX_MSDU_DECAP_NATIVE_WIFI:
784f69d3
MK		 872 /* pull decapped header and copy DA */
873 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 874 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
784f69d3
MK		 875 memcpy(addr, ieee80211_get_DA(hdr), ETH_ALEN);
876 skb_pull(skb, hdr_len);
877
878 /* push original 802.11 header */
879 hdr = (struct ieee80211_hdr *)hdr_buf;
880 hdr_len = ieee80211_hdrlen(hdr->frame_control);
881 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
882
883 /* original A-MSDU header has the bit set but we're
884 * not including A-MSDU subframe header */
885 hdr = (struct ieee80211_hdr *)skb->data;
886 qos = ieee80211_get_qos_ctl(hdr);
887 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
888
889 /* original 802.11 header has a different DA */
890 memcpy(ieee80211_get_DA(hdr), addr, ETH_ALEN);
f6dc2095
MK		 891 break;
892 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK		 893 /* strip ethernet header and insert decapped 802.11
894 * header, amsdu subframe header and rfc1042 header */
895
f6dc2095
MK		 896 len = 0;
897 len += sizeof(struct rfc1042_hdr);
898 len += sizeof(struct amsdu_subframe_hdr);
899
900 skb_pull(skb, sizeof(struct ethhdr));
901 memcpy(skb_push(skb, len), decap_hdr, len);
902 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
903 break;
904 case RX_MSDU_DECAP_8023_SNAP_LLC:
e3fbf8d2
MK		 905 /* insert decapped 802.11 header making a singly
906 * A-MSDU */
f6dc2095
MK		 907 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
908 break;
5e3dd157
KV		 909 }
910
f6dc2095 911 info->skb = skb;
87326c97 912 ath10k_htt_rx_h_protected(htt, info, enctype);
5e3dd157 913 skb = skb->next;
f6dc2095 914 info->skb->next = NULL;
5e3dd157 915
652de35e 916 if (skb)
87326c97
JD		 917 info->rx_status.flag |= RX_FLAG_AMSDU_MORE;
918 else
919 info->rx_status.flag &= ~RX_FLAG_AMSDU_MORE;
652de35e 920
f6dc2095
MK		 921 ath10k_process_rx(htt->ar, info);
922 }
5e3dd157 923
f6dc2095
MK		 924 /* FIXME: It might be nice to re-assemble the A-MSDU when there's a
925 * monitor interface active for sniffing purposes. */
5e3dd157
KV		 926}
927
f6dc2095 928static void ath10k_htt_rx_msdu(struct ath10k_htt *htt, struct htt_rx_info *info)
5e3dd157
KV		 929{
930 struct sk_buff *skb = info->skb;
931 struct htt_rx_desc *rxd;
932 struct ieee80211_hdr *hdr;
933 enum rx_msdu_decap_format fmt;
934 enum htt_rx_mpdu_encrypt_type enctype;
e3fbf8d2
MK		 935 int hdr_len;
936 void *rfc1042;
5e3dd157
KV		 937
938 /* This shouldn't happen. If it does than it may be a FW bug. */
939 if (skb->next) {
75fb2f94 940 ath10k_warn("htt rx received chained non A-MSDU frame\n");
5e3dd157
KV		 941 ath10k_htt_rx_free_msdu_chain(skb->next);
942 skb->next = NULL;
943 }
944
945 rxd = (void *)skb->data - sizeof(*rxd);
946 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
947 RX_MSDU_START_INFO1_DECAP_FORMAT);
948 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
949 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
e3fbf8d2
MK		 950 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
951 hdr_len = ieee80211_hdrlen(hdr->frame_control);
5e3dd157 952
f6dc2095
MK		 953 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
954
5e3dd157
KV		 955 switch (fmt) {
956 case RX_MSDU_DECAP_RAW:
957 /* remove trailing FCS */
e3fbf8d2 958 skb_trim(skb, skb->len - FCS_LEN);
5e3dd157
KV		 959 break;
960 case RX_MSDU_DECAP_NATIVE_WIFI:
784f69d3
MK		 961 /* Pull decapped header */
962 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 963 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
784f69d3
MK		 964 skb_pull(skb, hdr_len);
965
966 /* Push original header */
967 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
968 hdr_len = ieee80211_hdrlen(hdr->frame_control);
969 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
5e3dd157
KV		 970 break;
971 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK		 972 /* strip ethernet header and insert decapped 802.11 header and
973 * rfc1042 header */
5e3dd157 974
e3fbf8d2
MK		 975 rfc1042 = hdr;
976 rfc1042 += roundup(hdr_len, 4);
977 rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(enctype), 4);
5e3dd157 978
e3fbf8d2
MK		 979 skb_pull(skb, sizeof(struct ethhdr));
980 memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
981 rfc1042, sizeof(struct rfc1042_hdr));
982 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
983 break;
984 case RX_MSDU_DECAP_8023_SNAP_LLC:
985 /* remove A-MSDU subframe header and insert
986 * decapped 802.11 header. rfc1042 header is already there */
5e3dd157 987
e3fbf8d2
MK		 988 skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
989 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
990 break;
5e3dd157
KV		 991 }
992
993 info->skb = skb;
87326c97 994 ath10k_htt_rx_h_protected(htt, info, enctype);
f6dc2095
MK		 995
996 ath10k_process_rx(htt->ar, info);
5e3dd157
KV		 997}
998
999static bool ath10k_htt_rx_has_decrypt_err(struct sk_buff *skb)
1000{
1001 struct htt_rx_desc *rxd;
1002 u32 flags;
1003
1004 rxd = (void *)skb->data - sizeof(*rxd);
1005 flags = __le32_to_cpu(rxd->attention.flags);
1006
1007 if (flags & RX_ATTENTION_FLAGS_DECRYPT_ERR)
1008 return true;
1009
1010 return false;
1011}
1012
1013static bool ath10k_htt_rx_has_fcs_err(struct sk_buff *skb)
1014{
1015 struct htt_rx_desc *rxd;
1016 u32 flags;
1017
1018 rxd = (void *)skb->data - sizeof(*rxd);
1019 flags = __le32_to_cpu(rxd->attention.flags);
1020
1021 if (flags & RX_ATTENTION_FLAGS_FCS_ERR)
1022 return true;
1023
1024 return false;
1025}
1026
22569400
JD		 1027static bool ath10k_htt_rx_has_mic_err(struct sk_buff *skb)
1028{
1029 struct htt_rx_desc *rxd;
1030 u32 flags;
1031
1032 rxd = (void *)skb->data - sizeof(*rxd);
1033 flags = __le32_to_cpu(rxd->attention.flags);
1034
1035 if (flags & RX_ATTENTION_FLAGS_TKIP_MIC_ERR)
1036 return true;
1037
1038 return false;
1039}
1040
a80ddb00
JD		 1041static bool ath10k_htt_rx_is_mgmt(struct sk_buff *skb)
1042{
1043 struct htt_rx_desc *rxd;
1044 u32 flags;
1045
1046 rxd = (void *)skb->data - sizeof(*rxd);
1047 flags = __le32_to_cpu(rxd->attention.flags);
1048
1049 if (flags & RX_ATTENTION_FLAGS_MGMT_TYPE)
1050 return true;
1051
1052 return false;
1053}
1054
605f81aa
MK		 1055static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
1056{
1057 struct htt_rx_desc *rxd;
1058 u32 flags, info;
1059 bool is_ip4, is_ip6;
1060 bool is_tcp, is_udp;
1061 bool ip_csum_ok, tcpudp_csum_ok;
1062
1063 rxd = (void *)skb->data - sizeof(*rxd);
1064 flags = __le32_to_cpu(rxd->attention.flags);
1065 info = __le32_to_cpu(rxd->msdu_start.info1);
1066
1067 is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
1068 is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
1069 is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
1070 is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
1071 ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
1072 tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
1073
1074 if (!is_ip4 && !is_ip6)
1075 return CHECKSUM_NONE;
1076 if (!is_tcp && !is_udp)
1077 return CHECKSUM_NONE;
1078 if (!ip_csum_ok)
1079 return CHECKSUM_NONE;
1080 if (!tcpudp_csum_ok)
1081 return CHECKSUM_NONE;
1082
1083 return CHECKSUM_UNNECESSARY;
1084}
1085
bfa35368
BG		 1086static int ath10k_unchain_msdu(struct sk_buff *msdu_head)
1087{
1088 struct sk_buff *next = msdu_head->next;
1089 struct sk_buff *to_free = next;
1090 int space;
1091 int total_len = 0;
1092
1093 /* TODO: Might could optimize this by using
1094 * skb_try_coalesce or similar method to
1095 * decrease copying, or maybe get mac80211 to
1096 * provide a way to just receive a list of
1097 * skb?
1098 */
1099
1100 msdu_head->next = NULL;
1101
1102 /* Allocate total length all at once. */
1103 while (next) {
1104 total_len += next->len;
1105 next = next->next;
1106 }
1107
1108 space = total_len - skb_tailroom(msdu_head);
1109 if ((space > 0) &&
1110 (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) {
1111 /* TODO: bump some rx-oom error stat */
1112 /* put it back together so we can free the
1113 * whole list at once.
1114 */
1115 msdu_head->next = to_free;
1116 return -1;
1117 }
1118
1119 /* Walk list again, copying contents into
1120 * msdu_head
1121 */
1122 next = to_free;
1123 while (next) {
1124 skb_copy_from_linear_data(next, skb_put(msdu_head, next->len),
1125 next->len);
1126 next = next->next;
1127 }
1128
1129 /* If here, we have consolidated skb. Free the
1130 * fragments and pass the main skb on up the
1131 * stack.
1132 */
1133 ath10k_htt_rx_free_msdu_chain(to_free);
1134 return 0;
1135}
1136
2acc4eb2
JD		 1137static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
1138 struct sk_buff *head,
87326c97 1139 enum htt_rx_mpdu_status status,
36653f05 1140 bool channel_set)
2acc4eb2 1141{
2acc4eb2
JD		 1142 if (!head) {
1143 ath10k_warn("htt rx no data!\n");
1144 return false;
1145 }
1146
1147 if (head->len == 0) {
1148 ath10k_dbg(ATH10K_DBG_HTT,
1149 "htt rx dropping due to zero-len\n");
1150 return false;
1151 }
1152
1153 if (ath10k_htt_rx_has_decrypt_err(head)) {
1154 ath10k_dbg(ATH10K_DBG_HTT,
1155 "htt rx dropping due to decrypt-err\n");
1156 return false;
1157 }
1158
36653f05
JD		 1159 if (!channel_set) {
1160 ath10k_warn("no channel configured; ignoring frame!\n");
1161 return false;
1162 }
1163
2acc4eb2
JD		 1164 /* Skip mgmt frames while we handle this in WMI */
1165 if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL ||
1166 ath10k_htt_rx_is_mgmt(head)) {
1167 ath10k_dbg(ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
1168 return false;
1169 }
1170
1171 if (status != HTT_RX_IND_MPDU_STATUS_OK &&
1172 status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR &&
1173 status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER &&
1174 !htt->ar->monitor_enabled) {
1175 ath10k_dbg(ATH10K_DBG_HTT,
1176 "htt rx ignoring frame w/ status %d\n",
1177 status);
1178 return false;
1179 }
1180
1181 if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
1182 ath10k_dbg(ATH10K_DBG_HTT,
1183 "htt rx CAC running\n");
1184 return false;
1185 }
1186
1187 return true;
1188}
1189
5e3dd157
KV		 1190static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
1191 struct htt_rx_indication *rx)
1192{
1193 struct htt_rx_info info;
1194 struct htt_rx_indication_mpdu_range *mpdu_ranges;
87326c97 1195 enum htt_rx_mpdu_status status;
5e3dd157
KV		 1196 struct ieee80211_hdr *hdr;
1197 int num_mpdu_ranges;
1198 int fw_desc_len;
1199 u8 *fw_desc;
87326c97 1200 bool channel_set, fcs_err, mic_err;
5e3dd157 1201 int i, j;
5e3dd157 1202
45967089
MK		 1203 lockdep_assert_held(&htt->rx_ring.lock);
1204
5e3dd157
KV		 1205 memset(&info, 0, sizeof(info));
1206
1207 fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
1208 fw_desc = (u8 *)&rx->fw_desc;
1209
1210 num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
1211 HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
1212 mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
1213
e8dc1a96 1214 /* Fill this once, while this is per-ppdu */
87326c97
JD		 1215 info.rx_status.signal = ATH10K_DEFAULT_NOISE_FLOOR;
1216 info.rx_status.signal += rx->ppdu.combined_rssi;
1217
1218 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) {
1219 /* TSF available only in 32-bit */
1220 info.rx_status.mactime =
1221 __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff;
1222 info.rx_status.flag |= RX_FLAG_MACTIME_END;
1223 }
e8dc1a96 1224
36653f05
JD		 1225 channel_set = ath10k_htt_rx_h_channel(htt->ar, &info.rx_status);
1226
87326c97
JD		 1227 if (channel_set) {
1228 ath10k_htt_rx_h_rates(htt->ar, info.rx_status.band,
1229 rx->ppdu.info0,
1230 __le32_to_cpu(rx->ppdu.info1),
1231 __le32_to_cpu(rx->ppdu.info2),
1232 &info.rx_status);
1233 }
e8dc1a96 1234
5e3dd157
KV		 1235 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
1236 rx, sizeof(*rx) +
1237 (sizeof(struct htt_rx_indication_mpdu_range) *
1238 num_mpdu_ranges));
1239
1240 for (i = 0; i < num_mpdu_ranges; i++) {
87326c97 1241 status = mpdu_ranges[i].mpdu_range_status;
5e3dd157
KV		 1242
1243 for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) {
1244 struct sk_buff *msdu_head, *msdu_tail;
5e3dd157
KV		 1245 int msdu_chaining;
1246
1247 msdu_head = NULL;
1248 msdu_tail = NULL;
1249 msdu_chaining = ath10k_htt_rx_amsdu_pop(htt,
1250 &fw_desc,
1251 &fw_desc_len,
1252 &msdu_head,
1253 &msdu_tail);
1254
2acc4eb2 1255 if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head,
87326c97 1256 status,
36653f05 1257 channel_set)) {
e8a50f8b
MP		 1258 ath10k_htt_rx_free_msdu_chain(msdu_head);
1259 continue;
1260 }
1261
bfa35368
BG		 1262 if (msdu_chaining &&
1263 (ath10k_unchain_msdu(msdu_head) < 0)) {
5e3dd157
KV		 1264 ath10k_htt_rx_free_msdu_chain(msdu_head);
1265 continue;
1266 }
1267
1268 info.skb = msdu_head;
c6b56b03 1269
87326c97
JD		 1270 fcs_err = ath10k_htt_rx_has_fcs_err(msdu_head);
1271 if (fcs_err)
1272 info.rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
1273 else
1274 info.rx_status.flag &= ~RX_FLAG_FAILED_FCS_CRC;
1275
1276 mic_err = ath10k_htt_rx_has_mic_err(msdu_head);
1277 if (mic_err)
1278 info.rx_status.flag |= RX_FLAG_MMIC_ERROR;
1279 else
1280 info.rx_status.flag &= ~RX_FLAG_MMIC_ERROR;
1281
1282 if (fcs_err)
c6b56b03
BG		 1283 ath10k_dbg(ATH10K_DBG_HTT,
1284 "htt rx has FCS err\n");
1285
87326c97 1286 if (mic_err)
c6b56b03
BG		 1287 ath10k_dbg(ATH10K_DBG_HTT,
1288 "htt rx has MIC err\n");
1289
5e3dd157
KV		 1290 hdr = ath10k_htt_rx_skb_get_hdr(msdu_head);
1291
1292 if (ath10k_htt_rx_hdr_is_amsdu(hdr))
f6dc2095 1293 ath10k_htt_rx_amsdu(htt, &info);
5e3dd157 1294 else
f6dc2095 1295 ath10k_htt_rx_msdu(htt, &info);
5e3dd157
KV		 1296 }
1297 }
1298
6e712d42 1299 tasklet_schedule(&htt->rx_replenish_task);
5e3dd157
KV		 1300}
1301
1302static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
1303 struct htt_rx_fragment_indication *frag)
1304{
1305 struct sk_buff *msdu_head, *msdu_tail;
87326c97 1306 enum htt_rx_mpdu_encrypt_type enctype;
5e3dd157
KV		 1307 struct htt_rx_desc *rxd;
1308 enum rx_msdu_decap_format fmt;
1309 struct htt_rx_info info = {};
1310 struct ieee80211_hdr *hdr;
1311 int msdu_chaining;
1312 bool tkip_mic_err;
1313 bool decrypt_err;
1314 u8 *fw_desc;
1315 int fw_desc_len, hdrlen, paramlen;
1316 int trim;
1317
1318 fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
1319 fw_desc = (u8 *)frag->fw_msdu_rx_desc;
1320
1321 msdu_head = NULL;
1322 msdu_tail = NULL;
45967089
MK		 1323
1324 spin_lock_bh(&htt->rx_ring.lock);
5e3dd157
KV		 1325 msdu_chaining = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
1326 &msdu_head, &msdu_tail);
45967089 1327 spin_unlock_bh(&htt->rx_ring.lock);
5e3dd157
KV		 1328
1329 ath10k_dbg(ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
1330
1331 if (!msdu_head) {
1332 ath10k_warn("htt rx frag no data\n");
1333 return;
1334 }
1335
1336 if (msdu_chaining || msdu_head != msdu_tail) {
1337 ath10k_warn("aggregation with fragmentation?!\n");
1338 ath10k_htt_rx_free_msdu_chain(msdu_head);
1339 return;
1340 }
1341
1342 /* FIXME: implement signal strength */
1343
1344 hdr = (struct ieee80211_hdr *)msdu_head->data;
1345 rxd = (void *)msdu_head->data - sizeof(*rxd);
1346 tkip_mic_err = !!(__le32_to_cpu(rxd->attention.flags) &
1347 RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
1348 decrypt_err = !!(__le32_to_cpu(rxd->attention.flags) &
1349 RX_ATTENTION_FLAGS_DECRYPT_ERR);
1350 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
1351 RX_MSDU_START_INFO1_DECAP_FORMAT);
1352
1353 if (fmt != RX_MSDU_DECAP_RAW) {
1354 ath10k_warn("we dont support non-raw fragmented rx yet\n");
1355 dev_kfree_skb_any(msdu_head);
1356 goto end;
1357 }
1358
1359 info.skb = msdu_head;
87326c97
JD		 1360 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
1361 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
1362 ath10k_htt_rx_h_protected(htt, &info, enctype);
605f81aa 1363 info.skb->ip_summed = ath10k_htt_rx_get_csum_state(info.skb);
5e3dd157 1364
87326c97 1365 if (tkip_mic_err)
5e3dd157 1366 ath10k_warn("tkip mic error\n");
5e3dd157
KV		 1367
1368 if (decrypt_err) {
1369 ath10k_warn("decryption err in fragmented rx\n");
1370 dev_kfree_skb_any(info.skb);
1371 goto end;
1372 }
1373
87326c97 1374 if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) {
5e3dd157 1375 hdrlen = ieee80211_hdrlen(hdr->frame_control);
87326c97 1376 paramlen = ath10k_htt_rx_crypto_param_len(enctype);
5e3dd157
KV		 1377
1378 /* It is more efficient to move the header than the payload */
1379 memmove((void *)info.skb->data + paramlen,
1380 (void *)info.skb->data,
1381 hdrlen);
1382 skb_pull(info.skb, paramlen);
1383 hdr = (struct ieee80211_hdr *)info.skb->data;
1384 }
1385
1386 /* remove trailing FCS */
1387 trim = 4;
1388
1389 /* remove crypto trailer */
87326c97 1390 trim += ath10k_htt_rx_crypto_tail_len(enctype);
5e3dd157
KV		 1391
1392 /* last fragment of TKIP frags has MIC */
1393 if (!ieee80211_has_morefrags(hdr->frame_control) &&
87326c97 1394 enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
5e3dd157
KV		 1395 trim += 8;
1396
1397 if (trim > info.skb->len) {
1398 ath10k_warn("htt rx fragment: trailer longer than the frame itself? drop\n");
1399 dev_kfree_skb_any(info.skb);
1400 goto end;
1401 }
1402
1403 skb_trim(info.skb, info.skb->len - trim);
1404
75fb2f94 1405 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
5e3dd157
KV		 1406 info.skb->data, info.skb->len);
1407 ath10k_process_rx(htt->ar, &info);
1408
1409end:
1410 if (fw_desc_len > 0) {
1411 ath10k_dbg(ATH10K_DBG_HTT,
1412 "expecting more fragmented rx in one indication %d\n",
1413 fw_desc_len);
1414 }
1415}
1416
6c5151a9
MK		 1417static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
1418 struct sk_buff *skb)
1419{
1420 struct ath10k_htt *htt = &ar->htt;
1421 struct htt_resp *resp = (struct htt_resp *)skb->data;
1422 struct htt_tx_done tx_done = {};
1423 int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS);
1424 __le16 msdu_id;
1425 int i;
1426
45967089
MK		 1427 lockdep_assert_held(&htt->tx_lock);
1428
6c5151a9
MK		 1429 switch (status) {
1430 case HTT_DATA_TX_STATUS_NO_ACK:
1431 tx_done.no_ack = true;
1432 break;
1433 case HTT_DATA_TX_STATUS_OK:
1434 break;
1435 case HTT_DATA_TX_STATUS_DISCARD:
1436 case HTT_DATA_TX_STATUS_POSTPONE:
1437 case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
1438 tx_done.discard = true;
1439 break;
1440 default:
1441 ath10k_warn("unhandled tx completion status %d\n", status);
1442 tx_done.discard = true;
1443 break;
1444 }
1445
1446 ath10k_dbg(ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
1447 resp->data_tx_completion.num_msdus);
1448
1449 for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
1450 msdu_id = resp->data_tx_completion.msdus[i];
1451 tx_done.msdu_id = __le16_to_cpu(msdu_id);
1452 ath10k_txrx_tx_unref(htt, &tx_done);
1453 }
1454}
1455
5e3dd157
KV		 1456void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
1457{
edb8236d 1458 struct ath10k_htt *htt = &ar->htt;
5e3dd157
KV		 1459 struct htt_resp *resp = (struct htt_resp *)skb->data;
1460
1461 /* confirm alignment */
1462 if (!IS_ALIGNED((unsigned long)skb->data, 4))
1463 ath10k_warn("unaligned htt message, expect trouble\n");
1464
75fb2f94 1465 ath10k_dbg(ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
5e3dd157
KV		 1466 resp->hdr.msg_type);
1467 switch (resp->hdr.msg_type) {
1468 case HTT_T2H_MSG_TYPE_VERSION_CONF: {
1469 htt->target_version_major = resp->ver_resp.major;
1470 htt->target_version_minor = resp->ver_resp.minor;
1471 complete(&htt->target_version_received);
1472 break;
1473 }
6c5151a9 1474 case HTT_T2H_MSG_TYPE_RX_IND:
45967089
MK		 1475 spin_lock_bh(&htt->rx_ring.lock);
1476 __skb_queue_tail(&htt->rx_compl_q, skb);
1477 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9
MK		 1478 tasklet_schedule(&htt->txrx_compl_task);
1479 return;
5e3dd157
KV		 1480 case HTT_T2H_MSG_TYPE_PEER_MAP: {
1481 struct htt_peer_map_event ev = {
1482 .vdev_id = resp->peer_map.vdev_id,
1483 .peer_id = __le16_to_cpu(resp->peer_map.peer_id),
1484 };
1485 memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
1486 ath10k_peer_map_event(htt, &ev);
1487 break;
1488 }
1489 case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
1490 struct htt_peer_unmap_event ev = {
1491 .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
1492 };
1493 ath10k_peer_unmap_event(htt, &ev);
1494 break;
1495 }
1496 case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
1497 struct htt_tx_done tx_done = {};
1498 int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
1499
1500 tx_done.msdu_id =
1501 __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
1502
1503 switch (status) {
1504 case HTT_MGMT_TX_STATUS_OK:
1505 break;
1506 case HTT_MGMT_TX_STATUS_RETRY:
1507 tx_done.no_ack = true;
1508 break;
1509 case HTT_MGMT_TX_STATUS_DROP:
1510 tx_done.discard = true;
1511 break;
1512 }
1513
6c5151a9 1514 spin_lock_bh(&htt->tx_lock);
0a89f8a0 1515 ath10k_txrx_tx_unref(htt, &tx_done);
6c5151a9 1516 spin_unlock_bh(&htt->tx_lock);
5e3dd157
KV		 1517 break;
1518 }
6c5151a9
MK		 1519 case HTT_T2H_MSG_TYPE_TX_COMPL_IND:
1520 spin_lock_bh(&htt->tx_lock);
1521 __skb_queue_tail(&htt->tx_compl_q, skb);
1522 spin_unlock_bh(&htt->tx_lock);
1523 tasklet_schedule(&htt->txrx_compl_task);
1524 return;
5e3dd157
KV		 1525 case HTT_T2H_MSG_TYPE_SEC_IND: {
1526 struct ath10k *ar = htt->ar;
1527 struct htt_security_indication *ev = &resp->security_indication;
1528
1529 ath10k_dbg(ATH10K_DBG_HTT,
1530 "sec ind peer_id %d unicast %d type %d\n",
1531 __le16_to_cpu(ev->peer_id),
1532 !!(ev->flags & HTT_SECURITY_IS_UNICAST),
1533 MS(ev->flags, HTT_SECURITY_TYPE));
1534 complete(&ar->install_key_done);
1535 break;
1536 }
1537 case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
1538 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
1539 skb->data, skb->len);
1540 ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
1541 break;
1542 }
1543 case HTT_T2H_MSG_TYPE_TEST:
1544 /* FIX THIS */
1545 break;
5e3dd157 1546 case HTT_T2H_MSG_TYPE_STATS_CONF:
a9bf0506
KV		 1547 trace_ath10k_htt_stats(skb->data, skb->len);
1548 break;
1549 case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
5e3dd157
KV		 1550 case HTT_T2H_MSG_TYPE_RX_ADDBA:
1551 case HTT_T2H_MSG_TYPE_RX_DELBA:
1552 case HTT_T2H_MSG_TYPE_RX_FLUSH:
1553 default:
1554 ath10k_dbg(ATH10K_DBG_HTT, "htt event (%d) not handled\n",
1555 resp->hdr.msg_type);
1556 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
1557 skb->data, skb->len);
1558 break;
1559 };
1560
1561 /* Free the indication buffer */
1562 dev_kfree_skb_any(skb);
1563}
6c5151a9
MK		 1564
1565static void ath10k_htt_txrx_compl_task(unsigned long ptr)
1566{
1567 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
1568 struct htt_resp *resp;
1569 struct sk_buff *skb;
1570
45967089
MK		 1571 spin_lock_bh(&htt->tx_lock);
1572 while ((skb = __skb_dequeue(&htt->tx_compl_q))) {
6c5151a9
MK		 1573 ath10k_htt_rx_frm_tx_compl(htt->ar, skb);
1574 dev_kfree_skb_any(skb);
1575 }
45967089 1576 spin_unlock_bh(&htt->tx_lock);
6c5151a9 1577
45967089
MK		 1578 spin_lock_bh(&htt->rx_ring.lock);
1579 while ((skb = __skb_dequeue(&htt->rx_compl_q))) {
6c5151a9
MK		 1580 resp = (struct htt_resp *)skb->data;
1581 ath10k_htt_rx_handler(htt, &resp->rx_ind);
1582 dev_kfree_skb_any(skb);
1583 }
45967089 1584 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9 1585}
Linux kernel - Deliverables
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