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5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
edb8236d | 18 | #include "core.h" |
5e3dd157 KV |
19 | #include "htc.h" |
20 | #include "htt.h" | |
21 | #include "txrx.h" | |
22 | #include "debug.h" | |
a9bf0506 | 23 | #include "trace.h" |
aa5b4fbc | 24 | #include "mac.h" |
5e3dd157 KV |
25 | |
26 | #include <linux/log2.h> | |
27 | ||
28 | /* slightly larger than one large A-MPDU */ | |
29 | #define HTT_RX_RING_SIZE_MIN 128 | |
30 | ||
31 | /* roughly 20 ms @ 1 Gbps of 1500B MSDUs */ | |
32 | #define HTT_RX_RING_SIZE_MAX 2048 | |
33 | ||
34 | #define HTT_RX_AVG_FRM_BYTES 1000 | |
35 | ||
36 | /* ms, very conservative */ | |
37 | #define HTT_RX_HOST_LATENCY_MAX_MS 20 | |
38 | ||
39 | /* ms, conservative */ | |
40 | #define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10 | |
41 | ||
42 | /* when under memory pressure rx ring refill may fail and needs a retry */ | |
43 | #define HTT_RX_RING_REFILL_RETRY_MS 50 | |
44 | ||
f6dc2095 MK |
45 | |
46 | static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb); | |
6c5151a9 | 47 | static void ath10k_htt_txrx_compl_task(unsigned long ptr); |
f6dc2095 | 48 | |
5e3dd157 KV |
49 | static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt) |
50 | { | |
51 | int size; | |
52 | ||
53 | /* | |
54 | * It is expected that the host CPU will typically be able to | |
55 | * service the rx indication from one A-MPDU before the rx | |
56 | * indication from the subsequent A-MPDU happens, roughly 1-2 ms | |
57 | * later. However, the rx ring should be sized very conservatively, | |
58 | * to accomodate the worst reasonable delay before the host CPU | |
59 | * services a rx indication interrupt. | |
60 | * | |
61 | * The rx ring need not be kept full of empty buffers. In theory, | |
62 | * the htt host SW can dynamically track the low-water mark in the | |
63 | * rx ring, and dynamically adjust the level to which the rx ring | |
64 | * is filled with empty buffers, to dynamically meet the desired | |
65 | * low-water mark. | |
66 | * | |
67 | * In contrast, it's difficult to resize the rx ring itself, once | |
68 | * it's in use. Thus, the ring itself should be sized very | |
69 | * conservatively, while the degree to which the ring is filled | |
70 | * with empty buffers should be sized moderately conservatively. | |
71 | */ | |
72 | ||
73 | /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ | |
74 | size = | |
75 | htt->max_throughput_mbps + | |
76 | 1000 / | |
77 | (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS; | |
78 | ||
79 | if (size < HTT_RX_RING_SIZE_MIN) | |
80 | size = HTT_RX_RING_SIZE_MIN; | |
81 | ||
82 | if (size > HTT_RX_RING_SIZE_MAX) | |
83 | size = HTT_RX_RING_SIZE_MAX; | |
84 | ||
85 | size = roundup_pow_of_two(size); | |
86 | ||
87 | return size; | |
88 | } | |
89 | ||
90 | static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt) | |
91 | { | |
92 | int size; | |
93 | ||
94 | /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ | |
95 | size = | |
96 | htt->max_throughput_mbps * | |
97 | 1000 / | |
98 | (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS; | |
99 | ||
100 | /* | |
101 | * Make sure the fill level is at least 1 less than the ring size. | |
102 | * Leaving 1 element empty allows the SW to easily distinguish | |
103 | * between a full ring vs. an empty ring. | |
104 | */ | |
105 | if (size >= htt->rx_ring.size) | |
106 | size = htt->rx_ring.size - 1; | |
107 | ||
108 | return size; | |
109 | } | |
110 | ||
111 | static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt) | |
112 | { | |
113 | struct sk_buff *skb; | |
114 | struct ath10k_skb_cb *cb; | |
115 | int i; | |
116 | ||
117 | for (i = 0; i < htt->rx_ring.fill_cnt; i++) { | |
118 | skb = htt->rx_ring.netbufs_ring[i]; | |
119 | cb = ATH10K_SKB_CB(skb); | |
120 | dma_unmap_single(htt->ar->dev, cb->paddr, | |
121 | skb->len + skb_tailroom(skb), | |
122 | DMA_FROM_DEVICE); | |
123 | dev_kfree_skb_any(skb); | |
124 | } | |
125 | ||
126 | htt->rx_ring.fill_cnt = 0; | |
127 | } | |
128 | ||
129 | static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) | |
130 | { | |
131 | struct htt_rx_desc *rx_desc; | |
132 | struct sk_buff *skb; | |
133 | dma_addr_t paddr; | |
134 | int ret = 0, idx; | |
135 | ||
136 | idx = __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr)); | |
137 | while (num > 0) { | |
138 | skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN); | |
139 | if (!skb) { | |
140 | ret = -ENOMEM; | |
141 | goto fail; | |
142 | } | |
143 | ||
144 | if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN)) | |
145 | skb_pull(skb, | |
146 | PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) - | |
147 | skb->data); | |
148 | ||
149 | /* Clear rx_desc attention word before posting to Rx ring */ | |
150 | rx_desc = (struct htt_rx_desc *)skb->data; | |
151 | rx_desc->attention.flags = __cpu_to_le32(0); | |
152 | ||
153 | paddr = dma_map_single(htt->ar->dev, skb->data, | |
154 | skb->len + skb_tailroom(skb), | |
155 | DMA_FROM_DEVICE); | |
156 | ||
157 | if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) { | |
158 | dev_kfree_skb_any(skb); | |
159 | ret = -ENOMEM; | |
160 | goto fail; | |
161 | } | |
162 | ||
163 | ATH10K_SKB_CB(skb)->paddr = paddr; | |
164 | htt->rx_ring.netbufs_ring[idx] = skb; | |
165 | htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr); | |
166 | htt->rx_ring.fill_cnt++; | |
167 | ||
168 | num--; | |
169 | idx++; | |
170 | idx &= htt->rx_ring.size_mask; | |
171 | } | |
172 | ||
173 | fail: | |
174 | *(htt->rx_ring.alloc_idx.vaddr) = __cpu_to_le32(idx); | |
175 | return ret; | |
176 | } | |
177 | ||
178 | static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) | |
179 | { | |
180 | lockdep_assert_held(&htt->rx_ring.lock); | |
181 | return __ath10k_htt_rx_ring_fill_n(htt, num); | |
182 | } | |
183 | ||
184 | static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt) | |
185 | { | |
6e712d42 | 186 | int ret, num_deficit, num_to_fill; |
5e3dd157 | 187 | |
6e712d42 MK |
188 | /* Refilling the whole RX ring buffer proves to be a bad idea. The |
189 | * reason is RX may take up significant amount of CPU cycles and starve | |
190 | * other tasks, e.g. TX on an ethernet device while acting as a bridge | |
191 | * with ath10k wlan interface. This ended up with very poor performance | |
192 | * once CPU the host system was overwhelmed with RX on ath10k. | |
193 | * | |
194 | * By limiting the number of refills the replenishing occurs | |
195 | * progressively. This in turns makes use of the fact tasklets are | |
196 | * processed in FIFO order. This means actual RX processing can starve | |
197 | * out refilling. If there's not enough buffers on RX ring FW will not | |
198 | * report RX until it is refilled with enough buffers. This | |
199 | * automatically balances load wrt to CPU power. | |
200 | * | |
201 | * This probably comes at a cost of lower maximum throughput but | |
202 | * improves the avarage and stability. */ | |
5e3dd157 | 203 | spin_lock_bh(&htt->rx_ring.lock); |
6e712d42 MK |
204 | num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt; |
205 | num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit); | |
206 | num_deficit -= num_to_fill; | |
5e3dd157 KV |
207 | ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill); |
208 | if (ret == -ENOMEM) { | |
209 | /* | |
210 | * Failed to fill it to the desired level - | |
211 | * we'll start a timer and try again next time. | |
212 | * As long as enough buffers are left in the ring for | |
213 | * another A-MPDU rx, no special recovery is needed. | |
214 | */ | |
215 | mod_timer(&htt->rx_ring.refill_retry_timer, jiffies + | |
216 | msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS)); | |
6e712d42 MK |
217 | } else if (num_deficit > 0) { |
218 | tasklet_schedule(&htt->rx_replenish_task); | |
5e3dd157 KV |
219 | } |
220 | spin_unlock_bh(&htt->rx_ring.lock); | |
221 | } | |
222 | ||
223 | static void ath10k_htt_rx_ring_refill_retry(unsigned long arg) | |
224 | { | |
225 | struct ath10k_htt *htt = (struct ath10k_htt *)arg; | |
226 | ath10k_htt_rx_msdu_buff_replenish(htt); | |
227 | } | |
228 | ||
3e841fd0 | 229 | static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt) |
5e3dd157 | 230 | { |
3e841fd0 MK |
231 | struct sk_buff *skb; |
232 | int i; | |
233 | ||
234 | for (i = 0; i < htt->rx_ring.size; i++) { | |
235 | skb = htt->rx_ring.netbufs_ring[i]; | |
236 | if (!skb) | |
237 | continue; | |
238 | ||
239 | dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr, | |
240 | skb->len + skb_tailroom(skb), | |
241 | DMA_FROM_DEVICE); | |
242 | dev_kfree_skb_any(skb); | |
243 | htt->rx_ring.netbufs_ring[i] = NULL; | |
244 | } | |
245 | } | |
5e3dd157 | 246 | |
95bf21f9 | 247 | void ath10k_htt_rx_free(struct ath10k_htt *htt) |
3e841fd0 | 248 | { |
5e3dd157 | 249 | del_timer_sync(&htt->rx_ring.refill_retry_timer); |
6e712d42 | 250 | tasklet_kill(&htt->rx_replenish_task); |
6c5151a9 MK |
251 | tasklet_kill(&htt->txrx_compl_task); |
252 | ||
253 | skb_queue_purge(&htt->tx_compl_q); | |
254 | skb_queue_purge(&htt->rx_compl_q); | |
5e3dd157 | 255 | |
3e841fd0 | 256 | ath10k_htt_rx_ring_clean_up(htt); |
5e3dd157 KV |
257 | |
258 | dma_free_coherent(htt->ar->dev, | |
259 | (htt->rx_ring.size * | |
260 | sizeof(htt->rx_ring.paddrs_ring)), | |
261 | htt->rx_ring.paddrs_ring, | |
262 | htt->rx_ring.base_paddr); | |
263 | ||
264 | dma_free_coherent(htt->ar->dev, | |
265 | sizeof(*htt->rx_ring.alloc_idx.vaddr), | |
266 | htt->rx_ring.alloc_idx.vaddr, | |
267 | htt->rx_ring.alloc_idx.paddr); | |
268 | ||
269 | kfree(htt->rx_ring.netbufs_ring); | |
270 | } | |
271 | ||
272 | static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt) | |
273 | { | |
7aa7a72a | 274 | struct ath10k *ar = htt->ar; |
5e3dd157 KV |
275 | int idx; |
276 | struct sk_buff *msdu; | |
277 | ||
45967089 | 278 | lockdep_assert_held(&htt->rx_ring.lock); |
5e3dd157 | 279 | |
8d60ee87 | 280 | if (htt->rx_ring.fill_cnt == 0) { |
7aa7a72a | 281 | ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n"); |
8d60ee87 MK |
282 | return NULL; |
283 | } | |
5e3dd157 KV |
284 | |
285 | idx = htt->rx_ring.sw_rd_idx.msdu_payld; | |
286 | msdu = htt->rx_ring.netbufs_ring[idx]; | |
3e841fd0 | 287 | htt->rx_ring.netbufs_ring[idx] = NULL; |
5e3dd157 KV |
288 | |
289 | idx++; | |
290 | idx &= htt->rx_ring.size_mask; | |
291 | htt->rx_ring.sw_rd_idx.msdu_payld = idx; | |
292 | htt->rx_ring.fill_cnt--; | |
293 | ||
5e3dd157 KV |
294 | return msdu; |
295 | } | |
296 | ||
297 | static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb) | |
298 | { | |
299 | struct sk_buff *next; | |
300 | ||
301 | while (skb) { | |
302 | next = skb->next; | |
303 | dev_kfree_skb_any(skb); | |
304 | skb = next; | |
305 | } | |
306 | } | |
307 | ||
d84dd60f | 308 | /* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */ |
5e3dd157 KV |
309 | static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt, |
310 | u8 **fw_desc, int *fw_desc_len, | |
311 | struct sk_buff **head_msdu, | |
0ccb7a34 JD |
312 | struct sk_buff **tail_msdu, |
313 | u32 *attention) | |
5e3dd157 | 314 | { |
7aa7a72a | 315 | struct ath10k *ar = htt->ar; |
5e3dd157 KV |
316 | int msdu_len, msdu_chaining = 0; |
317 | struct sk_buff *msdu; | |
318 | struct htt_rx_desc *rx_desc; | |
319 | ||
45967089 MK |
320 | lockdep_assert_held(&htt->rx_ring.lock); |
321 | ||
5e3dd157 | 322 | if (htt->rx_confused) { |
7aa7a72a | 323 | ath10k_warn(ar, "htt is confused. refusing rx\n"); |
d84dd60f | 324 | return -1; |
5e3dd157 KV |
325 | } |
326 | ||
327 | msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt); | |
328 | while (msdu) { | |
329 | int last_msdu, msdu_len_invalid, msdu_chained; | |
330 | ||
331 | dma_unmap_single(htt->ar->dev, | |
332 | ATH10K_SKB_CB(msdu)->paddr, | |
333 | msdu->len + skb_tailroom(msdu), | |
334 | DMA_FROM_DEVICE); | |
335 | ||
7aa7a72a | 336 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ", |
5e3dd157 KV |
337 | msdu->data, msdu->len + skb_tailroom(msdu)); |
338 | ||
339 | rx_desc = (struct htt_rx_desc *)msdu->data; | |
340 | ||
341 | /* FIXME: we must report msdu payload since this is what caller | |
342 | * expects now */ | |
343 | skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload)); | |
344 | skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload)); | |
345 | ||
346 | /* | |
347 | * Sanity check - confirm the HW is finished filling in the | |
348 | * rx data. | |
349 | * If the HW and SW are working correctly, then it's guaranteed | |
350 | * that the HW's MAC DMA is done before this point in the SW. | |
351 | * To prevent the case that we handle a stale Rx descriptor, | |
352 | * just assert for now until we have a way to recover. | |
353 | */ | |
354 | if (!(__le32_to_cpu(rx_desc->attention.flags) | |
355 | & RX_ATTENTION_FLAGS_MSDU_DONE)) { | |
356 | ath10k_htt_rx_free_msdu_chain(*head_msdu); | |
357 | *head_msdu = NULL; | |
358 | msdu = NULL; | |
7aa7a72a | 359 | ath10k_err(ar, "htt rx stopped. cannot recover\n"); |
5e3dd157 KV |
360 | htt->rx_confused = true; |
361 | break; | |
362 | } | |
363 | ||
0ccb7a34 JD |
364 | *attention |= __le32_to_cpu(rx_desc->attention.flags) & |
365 | (RX_ATTENTION_FLAGS_TKIP_MIC_ERR | | |
366 | RX_ATTENTION_FLAGS_DECRYPT_ERR | | |
367 | RX_ATTENTION_FLAGS_FCS_ERR | | |
368 | RX_ATTENTION_FLAGS_MGMT_TYPE); | |
5e3dd157 KV |
369 | /* |
370 | * Copy the FW rx descriptor for this MSDU from the rx | |
371 | * indication message into the MSDU's netbuf. HL uses the | |
372 | * same rx indication message definition as LL, and simply | |
373 | * appends new info (fields from the HW rx desc, and the | |
374 | * MSDU payload itself). So, the offset into the rx | |
375 | * indication message only has to account for the standard | |
376 | * offset of the per-MSDU FW rx desc info within the | |
377 | * message, and how many bytes of the per-MSDU FW rx desc | |
378 | * info have already been consumed. (And the endianness of | |
379 | * the host, since for a big-endian host, the rx ind | |
380 | * message contents, including the per-MSDU rx desc bytes, | |
381 | * were byteswapped during upload.) | |
382 | */ | |
383 | if (*fw_desc_len > 0) { | |
384 | rx_desc->fw_desc.info0 = **fw_desc; | |
385 | /* | |
386 | * The target is expected to only provide the basic | |
387 | * per-MSDU rx descriptors. Just to be sure, verify | |
388 | * that the target has not attached extension data | |
389 | * (e.g. LRO flow ID). | |
390 | */ | |
391 | ||
392 | /* or more, if there's extension data */ | |
393 | (*fw_desc)++; | |
394 | (*fw_desc_len)--; | |
395 | } else { | |
396 | /* | |
397 | * When an oversized AMSDU happened, FW will lost | |
398 | * some of MSDU status - in this case, the FW | |
399 | * descriptors provided will be less than the | |
400 | * actual MSDUs inside this MPDU. Mark the FW | |
401 | * descriptors so that it will still deliver to | |
402 | * upper stack, if no CRC error for this MPDU. | |
403 | * | |
404 | * FIX THIS - the FW descriptors are actually for | |
405 | * MSDUs in the end of this A-MSDU instead of the | |
406 | * beginning. | |
407 | */ | |
408 | rx_desc->fw_desc.info0 = 0; | |
409 | } | |
410 | ||
411 | msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags) | |
412 | & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR | | |
413 | RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR)); | |
414 | msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0), | |
415 | RX_MSDU_START_INFO0_MSDU_LENGTH); | |
416 | msdu_chained = rx_desc->frag_info.ring2_more_count; | |
417 | ||
418 | if (msdu_len_invalid) | |
419 | msdu_len = 0; | |
420 | ||
421 | skb_trim(msdu, 0); | |
422 | skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE)); | |
423 | msdu_len -= msdu->len; | |
424 | ||
425 | /* FIXME: Do chained buffers include htt_rx_desc or not? */ | |
426 | while (msdu_chained--) { | |
427 | struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt); | |
428 | ||
429 | dma_unmap_single(htt->ar->dev, | |
430 | ATH10K_SKB_CB(next)->paddr, | |
431 | next->len + skb_tailroom(next), | |
432 | DMA_FROM_DEVICE); | |
433 | ||
7aa7a72a | 434 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, |
75fb2f94 | 435 | "htt rx chained: ", next->data, |
5e3dd157 KV |
436 | next->len + skb_tailroom(next)); |
437 | ||
438 | skb_trim(next, 0); | |
439 | skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE)); | |
440 | msdu_len -= next->len; | |
441 | ||
442 | msdu->next = next; | |
443 | msdu = next; | |
ede9c8e0 | 444 | msdu_chaining = 1; |
5e3dd157 KV |
445 | } |
446 | ||
5e3dd157 KV |
447 | last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) & |
448 | RX_MSDU_END_INFO0_LAST_MSDU; | |
449 | ||
450 | if (last_msdu) { | |
451 | msdu->next = NULL; | |
452 | break; | |
453 | } else { | |
454 | struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt); | |
455 | msdu->next = next; | |
456 | msdu = next; | |
457 | } | |
458 | } | |
459 | *tail_msdu = msdu; | |
460 | ||
d84dd60f JD |
461 | if (*head_msdu == NULL) |
462 | msdu_chaining = -1; | |
463 | ||
5e3dd157 KV |
464 | /* |
465 | * Don't refill the ring yet. | |
466 | * | |
467 | * First, the elements popped here are still in use - it is not | |
468 | * safe to overwrite them until the matching call to | |
469 | * mpdu_desc_list_next. Second, for efficiency it is preferable to | |
470 | * refill the rx ring with 1 PPDU's worth of rx buffers (something | |
471 | * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers | |
472 | * (something like 3 buffers). Consequently, we'll rely on the txrx | |
473 | * SW to tell us when it is done pulling all the PPDU's rx buffers | |
474 | * out of the rx ring, and then refill it just once. | |
475 | */ | |
476 | ||
477 | return msdu_chaining; | |
478 | } | |
479 | ||
6e712d42 MK |
480 | static void ath10k_htt_rx_replenish_task(unsigned long ptr) |
481 | { | |
482 | struct ath10k_htt *htt = (struct ath10k_htt *)ptr; | |
483 | ath10k_htt_rx_msdu_buff_replenish(htt); | |
484 | } | |
485 | ||
95bf21f9 | 486 | int ath10k_htt_rx_alloc(struct ath10k_htt *htt) |
5e3dd157 | 487 | { |
7aa7a72a | 488 | struct ath10k *ar = htt->ar; |
5e3dd157 KV |
489 | dma_addr_t paddr; |
490 | void *vaddr; | |
491 | struct timer_list *timer = &htt->rx_ring.refill_retry_timer; | |
492 | ||
493 | htt->rx_ring.size = ath10k_htt_rx_ring_size(htt); | |
494 | if (!is_power_of_2(htt->rx_ring.size)) { | |
7aa7a72a | 495 | ath10k_warn(ar, "htt rx ring size is not power of 2\n"); |
5e3dd157 KV |
496 | return -EINVAL; |
497 | } | |
498 | ||
499 | htt->rx_ring.size_mask = htt->rx_ring.size - 1; | |
500 | ||
501 | /* | |
502 | * Set the initial value for the level to which the rx ring | |
503 | * should be filled, based on the max throughput and the | |
504 | * worst likely latency for the host to fill the rx ring | |
505 | * with new buffers. In theory, this fill level can be | |
506 | * dynamically adjusted from the initial value set here, to | |
507 | * reflect the actual host latency rather than a | |
508 | * conservative assumption about the host latency. | |
509 | */ | |
510 | htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt); | |
511 | ||
512 | htt->rx_ring.netbufs_ring = | |
3e841fd0 | 513 | kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *), |
5e3dd157 KV |
514 | GFP_KERNEL); |
515 | if (!htt->rx_ring.netbufs_ring) | |
516 | goto err_netbuf; | |
517 | ||
518 | vaddr = dma_alloc_coherent(htt->ar->dev, | |
519 | (htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring)), | |
520 | &paddr, GFP_DMA); | |
521 | if (!vaddr) | |
522 | goto err_dma_ring; | |
523 | ||
524 | htt->rx_ring.paddrs_ring = vaddr; | |
525 | htt->rx_ring.base_paddr = paddr; | |
526 | ||
527 | vaddr = dma_alloc_coherent(htt->ar->dev, | |
528 | sizeof(*htt->rx_ring.alloc_idx.vaddr), | |
529 | &paddr, GFP_DMA); | |
530 | if (!vaddr) | |
531 | goto err_dma_idx; | |
532 | ||
533 | htt->rx_ring.alloc_idx.vaddr = vaddr; | |
534 | htt->rx_ring.alloc_idx.paddr = paddr; | |
535 | htt->rx_ring.sw_rd_idx.msdu_payld = 0; | |
536 | *htt->rx_ring.alloc_idx.vaddr = 0; | |
537 | ||
538 | /* Initialize the Rx refill retry timer */ | |
539 | setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt); | |
540 | ||
541 | spin_lock_init(&htt->rx_ring.lock); | |
542 | ||
543 | htt->rx_ring.fill_cnt = 0; | |
544 | if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level)) | |
545 | goto err_fill_ring; | |
546 | ||
6e712d42 MK |
547 | tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task, |
548 | (unsigned long)htt); | |
549 | ||
6c5151a9 MK |
550 | skb_queue_head_init(&htt->tx_compl_q); |
551 | skb_queue_head_init(&htt->rx_compl_q); | |
552 | ||
553 | tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task, | |
554 | (unsigned long)htt); | |
555 | ||
7aa7a72a | 556 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n", |
5e3dd157 KV |
557 | htt->rx_ring.size, htt->rx_ring.fill_level); |
558 | return 0; | |
559 | ||
560 | err_fill_ring: | |
561 | ath10k_htt_rx_ring_free(htt); | |
562 | dma_free_coherent(htt->ar->dev, | |
563 | sizeof(*htt->rx_ring.alloc_idx.vaddr), | |
564 | htt->rx_ring.alloc_idx.vaddr, | |
565 | htt->rx_ring.alloc_idx.paddr); | |
566 | err_dma_idx: | |
567 | dma_free_coherent(htt->ar->dev, | |
568 | (htt->rx_ring.size * | |
569 | sizeof(htt->rx_ring.paddrs_ring)), | |
570 | htt->rx_ring.paddrs_ring, | |
571 | htt->rx_ring.base_paddr); | |
572 | err_dma_ring: | |
573 | kfree(htt->rx_ring.netbufs_ring); | |
574 | err_netbuf: | |
575 | return -ENOMEM; | |
576 | } | |
577 | ||
7aa7a72a MK |
578 | static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar, |
579 | enum htt_rx_mpdu_encrypt_type type) | |
5e3dd157 KV |
580 | { |
581 | switch (type) { | |
582 | case HTT_RX_MPDU_ENCRYPT_WEP40: | |
583 | case HTT_RX_MPDU_ENCRYPT_WEP104: | |
584 | return 4; | |
585 | case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: | |
586 | case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */ | |
587 | case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: | |
588 | case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */ | |
589 | case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: | |
590 | return 8; | |
591 | case HTT_RX_MPDU_ENCRYPT_NONE: | |
592 | return 0; | |
593 | } | |
594 | ||
7aa7a72a | 595 | ath10k_warn(ar, "unknown encryption type %d\n", type); |
5e3dd157 KV |
596 | return 0; |
597 | } | |
598 | ||
7aa7a72a MK |
599 | static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar, |
600 | enum htt_rx_mpdu_encrypt_type type) | |
5e3dd157 KV |
601 | { |
602 | switch (type) { | |
603 | case HTT_RX_MPDU_ENCRYPT_NONE: | |
604 | case HTT_RX_MPDU_ENCRYPT_WEP40: | |
605 | case HTT_RX_MPDU_ENCRYPT_WEP104: | |
606 | case HTT_RX_MPDU_ENCRYPT_WEP128: | |
607 | case HTT_RX_MPDU_ENCRYPT_WAPI: | |
608 | return 0; | |
609 | case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: | |
610 | case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: | |
611 | return 4; | |
612 | case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: | |
613 | return 8; | |
614 | } | |
615 | ||
7aa7a72a | 616 | ath10k_warn(ar, "unknown encryption type %d\n", type); |
5e3dd157 KV |
617 | return 0; |
618 | } | |
619 | ||
620 | /* Applies for first msdu in chain, before altering it. */ | |
621 | static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb) | |
622 | { | |
623 | struct htt_rx_desc *rxd; | |
624 | enum rx_msdu_decap_format fmt; | |
625 | ||
626 | rxd = (void *)skb->data - sizeof(*rxd); | |
627 | fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), | |
628 | RX_MSDU_START_INFO1_DECAP_FORMAT); | |
629 | ||
630 | if (fmt == RX_MSDU_DECAP_RAW) | |
631 | return (void *)skb->data; | |
632 | else | |
633 | return (void *)skb->data - RX_HTT_HDR_STATUS_LEN; | |
634 | } | |
635 | ||
636 | /* This function only applies for first msdu in an msdu chain */ | |
637 | static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr) | |
638 | { | |
639 | if (ieee80211_is_data_qos(hdr->frame_control)) { | |
640 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
641 | if (qc[0] & 0x80) | |
642 | return true; | |
643 | } | |
644 | return false; | |
645 | } | |
646 | ||
f6dc2095 MK |
647 | struct rfc1042_hdr { |
648 | u8 llc_dsap; | |
649 | u8 llc_ssap; | |
650 | u8 llc_ctrl; | |
651 | u8 snap_oui[3]; | |
652 | __be16 snap_type; | |
653 | } __packed; | |
654 | ||
655 | struct amsdu_subframe_hdr { | |
656 | u8 dst[ETH_ALEN]; | |
657 | u8 src[ETH_ALEN]; | |
658 | __be16 len; | |
659 | } __packed; | |
660 | ||
73539b40 JD |
661 | static const u8 rx_legacy_rate_idx[] = { |
662 | 3, /* 0x00 - 11Mbps */ | |
663 | 2, /* 0x01 - 5.5Mbps */ | |
664 | 1, /* 0x02 - 2Mbps */ | |
665 | 0, /* 0x03 - 1Mbps */ | |
666 | 3, /* 0x04 - 11Mbps */ | |
667 | 2, /* 0x05 - 5.5Mbps */ | |
668 | 1, /* 0x06 - 2Mbps */ | |
669 | 0, /* 0x07 - 1Mbps */ | |
670 | 10, /* 0x08 - 48Mbps */ | |
671 | 8, /* 0x09 - 24Mbps */ | |
672 | 6, /* 0x0A - 12Mbps */ | |
673 | 4, /* 0x0B - 6Mbps */ | |
674 | 11, /* 0x0C - 54Mbps */ | |
675 | 9, /* 0x0D - 36Mbps */ | |
676 | 7, /* 0x0E - 18Mbps */ | |
677 | 5, /* 0x0F - 9Mbps */ | |
678 | }; | |
679 | ||
87326c97 | 680 | static void ath10k_htt_rx_h_rates(struct ath10k *ar, |
cfadd9ba | 681 | enum ieee80211_band band, |
87326c97 | 682 | u8 info0, u32 info1, u32 info2, |
cfadd9ba | 683 | struct ieee80211_rx_status *status) |
73539b40 JD |
684 | { |
685 | u8 cck, rate, rate_idx, bw, sgi, mcs, nss; | |
73539b40 JD |
686 | u8 preamble = 0; |
687 | ||
688 | /* Check if valid fields */ | |
689 | if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID)) | |
690 | return; | |
691 | ||
692 | preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE); | |
693 | ||
694 | switch (preamble) { | |
695 | case HTT_RX_LEGACY: | |
696 | cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK; | |
697 | rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE); | |
698 | rate_idx = 0; | |
699 | ||
700 | if (rate < 0x08 || rate > 0x0F) | |
701 | break; | |
702 | ||
703 | switch (band) { | |
704 | case IEEE80211_BAND_2GHZ: | |
705 | if (cck) | |
706 | rate &= ~BIT(3); | |
707 | rate_idx = rx_legacy_rate_idx[rate]; | |
708 | break; | |
709 | case IEEE80211_BAND_5GHZ: | |
710 | rate_idx = rx_legacy_rate_idx[rate]; | |
711 | /* We are using same rate table registering | |
712 | HW - ath10k_rates[]. In case of 5GHz skip | |
713 | CCK rates, so -4 here */ | |
714 | rate_idx -= 4; | |
715 | break; | |
716 | default: | |
717 | break; | |
718 | } | |
719 | ||
720 | status->rate_idx = rate_idx; | |
721 | break; | |
722 | case HTT_RX_HT: | |
723 | case HTT_RX_HT_WITH_TXBF: | |
724 | /* HT-SIG - Table 20-11 in info1 and info2 */ | |
725 | mcs = info1 & 0x1F; | |
726 | nss = mcs >> 3; | |
727 | bw = (info1 >> 7) & 1; | |
728 | sgi = (info2 >> 7) & 1; | |
729 | ||
730 | status->rate_idx = mcs; | |
731 | status->flag |= RX_FLAG_HT; | |
732 | if (sgi) | |
733 | status->flag |= RX_FLAG_SHORT_GI; | |
734 | if (bw) | |
735 | status->flag |= RX_FLAG_40MHZ; | |
736 | break; | |
737 | case HTT_RX_VHT: | |
738 | case HTT_RX_VHT_WITH_TXBF: | |
739 | /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2 | |
740 | TODO check this */ | |
741 | mcs = (info2 >> 4) & 0x0F; | |
742 | nss = ((info1 >> 10) & 0x07) + 1; | |
743 | bw = info1 & 3; | |
744 | sgi = info2 & 1; | |
745 | ||
746 | status->rate_idx = mcs; | |
747 | status->vht_nss = nss; | |
748 | ||
749 | if (sgi) | |
750 | status->flag |= RX_FLAG_SHORT_GI; | |
751 | ||
752 | switch (bw) { | |
753 | /* 20MHZ */ | |
754 | case 0: | |
755 | break; | |
756 | /* 40MHZ */ | |
757 | case 1: | |
758 | status->flag |= RX_FLAG_40MHZ; | |
759 | break; | |
760 | /* 80MHZ */ | |
761 | case 2: | |
762 | status->vht_flag |= RX_VHT_FLAG_80MHZ; | |
763 | } | |
764 | ||
765 | status->flag |= RX_FLAG_VHT; | |
766 | break; | |
767 | default: | |
768 | break; | |
769 | } | |
770 | } | |
771 | ||
87326c97 | 772 | static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt, |
85f6d7cf JD |
773 | struct ieee80211_rx_status *rx_status, |
774 | struct sk_buff *skb, | |
c071dcb2 MK |
775 | enum htt_rx_mpdu_encrypt_type enctype, |
776 | enum rx_msdu_decap_format fmt, | |
777 | bool dot11frag) | |
87326c97 | 778 | { |
85f6d7cf | 779 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
87326c97 | 780 | |
c071dcb2 MK |
781 | rx_status->flag &= ~(RX_FLAG_DECRYPTED | |
782 | RX_FLAG_IV_STRIPPED | | |
783 | RX_FLAG_MMIC_STRIPPED); | |
87326c97 | 784 | |
c071dcb2 MK |
785 | if (enctype == HTT_RX_MPDU_ENCRYPT_NONE) |
786 | return; | |
787 | ||
788 | /* | |
789 | * There's no explicit rx descriptor flag to indicate whether a given | |
790 | * frame has been decrypted or not. We're forced to use the decap | |
791 | * format as an implicit indication. However fragmentation rx is always | |
792 | * raw and it probably never reports undecrypted raws. | |
793 | * | |
794 | * This makes sure sniffed frames are reported as-is without stripping | |
795 | * the protected flag. | |
796 | */ | |
797 | if (fmt == RX_MSDU_DECAP_RAW && !dot11frag) | |
87326c97 | 798 | return; |
87326c97 | 799 | |
85f6d7cf JD |
800 | rx_status->flag |= RX_FLAG_DECRYPTED | |
801 | RX_FLAG_IV_STRIPPED | | |
802 | RX_FLAG_MMIC_STRIPPED; | |
87326c97 JD |
803 | hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) & |
804 | ~IEEE80211_FCTL_PROTECTED); | |
805 | } | |
806 | ||
36653f05 JD |
807 | static bool ath10k_htt_rx_h_channel(struct ath10k *ar, |
808 | struct ieee80211_rx_status *status) | |
809 | { | |
810 | struct ieee80211_channel *ch; | |
811 | ||
812 | spin_lock_bh(&ar->data_lock); | |
813 | ch = ar->scan_channel; | |
814 | if (!ch) | |
815 | ch = ar->rx_channel; | |
816 | spin_unlock_bh(&ar->data_lock); | |
817 | ||
818 | if (!ch) | |
819 | return false; | |
820 | ||
821 | status->band = ch->band; | |
822 | status->freq = ch->center_freq; | |
823 | ||
824 | return true; | |
825 | } | |
826 | ||
76f5329a JD |
827 | static const char * const tid_to_ac[] = { |
828 | "BE", | |
829 | "BK", | |
830 | "BK", | |
831 | "BE", | |
832 | "VI", | |
833 | "VI", | |
834 | "VO", | |
835 | "VO", | |
836 | }; | |
837 | ||
838 | static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size) | |
839 | { | |
840 | u8 *qc; | |
841 | int tid; | |
842 | ||
843 | if (!ieee80211_is_data_qos(hdr->frame_control)) | |
844 | return ""; | |
845 | ||
846 | qc = ieee80211_get_qos_ctl(hdr); | |
847 | tid = *qc & IEEE80211_QOS_CTL_TID_MASK; | |
848 | if (tid < 8) | |
849 | snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]); | |
850 | else | |
851 | snprintf(out, size, "tid %d", tid); | |
852 | ||
853 | return out; | |
854 | } | |
855 | ||
85f6d7cf JD |
856 | static void ath10k_process_rx(struct ath10k *ar, |
857 | struct ieee80211_rx_status *rx_status, | |
858 | struct sk_buff *skb) | |
73539b40 JD |
859 | { |
860 | struct ieee80211_rx_status *status; | |
76f5329a JD |
861 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
862 | char tid[32]; | |
73539b40 | 863 | |
85f6d7cf JD |
864 | status = IEEE80211_SKB_RXCB(skb); |
865 | *status = *rx_status; | |
73539b40 | 866 | |
7aa7a72a | 867 | ath10k_dbg(ar, ATH10K_DBG_DATA, |
76f5329a | 868 | "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", |
85f6d7cf JD |
869 | skb, |
870 | skb->len, | |
76f5329a JD |
871 | ieee80211_get_SA(hdr), |
872 | ath10k_get_tid(hdr, tid, sizeof(tid)), | |
873 | is_multicast_ether_addr(ieee80211_get_DA(hdr)) ? | |
874 | "mcast" : "ucast", | |
875 | (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4, | |
73539b40 JD |
876 | status->flag == 0 ? "legacy" : "", |
877 | status->flag & RX_FLAG_HT ? "ht" : "", | |
878 | status->flag & RX_FLAG_VHT ? "vht" : "", | |
879 | status->flag & RX_FLAG_40MHZ ? "40" : "", | |
880 | status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "", | |
881 | status->flag & RX_FLAG_SHORT_GI ? "sgi " : "", | |
882 | status->rate_idx, | |
883 | status->vht_nss, | |
884 | status->freq, | |
87326c97 | 885 | status->band, status->flag, |
78433f96 | 886 | !!(status->flag & RX_FLAG_FAILED_FCS_CRC), |
76f5329a JD |
887 | !!(status->flag & RX_FLAG_MMIC_ERROR), |
888 | !!(status->flag & RX_FLAG_AMSDU_MORE)); | |
7aa7a72a | 889 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ", |
85f6d7cf | 890 | skb->data, skb->len); |
73539b40 | 891 | |
85f6d7cf | 892 | ieee80211_rx(ar->hw, skb); |
73539b40 JD |
893 | } |
894 | ||
d960c369 MK |
895 | static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr) |
896 | { | |
897 | /* nwifi header is padded to 4 bytes. this fixes 4addr rx */ | |
898 | return round_up(ieee80211_hdrlen(hdr->frame_control), 4); | |
899 | } | |
900 | ||
f6dc2095 | 901 | static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt, |
85f6d7cf JD |
902 | struct ieee80211_rx_status *rx_status, |
903 | struct sk_buff *skb_in) | |
5e3dd157 | 904 | { |
7aa7a72a | 905 | struct ath10k *ar = htt->ar; |
5e3dd157 | 906 | struct htt_rx_desc *rxd; |
85f6d7cf | 907 | struct sk_buff *skb = skb_in; |
5e3dd157 | 908 | struct sk_buff *first; |
5e3dd157 KV |
909 | enum rx_msdu_decap_format fmt; |
910 | enum htt_rx_mpdu_encrypt_type enctype; | |
f6dc2095 | 911 | struct ieee80211_hdr *hdr; |
72bdeb86 | 912 | u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos; |
5e3dd157 | 913 | unsigned int hdr_len; |
5e3dd157 KV |
914 | |
915 | rxd = (void *)skb->data - sizeof(*rxd); | |
5e3dd157 KV |
916 | enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), |
917 | RX_MPDU_START_INFO0_ENCRYPT_TYPE); | |
918 | ||
f6dc2095 MK |
919 | hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; |
920 | hdr_len = ieee80211_hdrlen(hdr->frame_control); | |
921 | memcpy(hdr_buf, hdr, hdr_len); | |
922 | hdr = (struct ieee80211_hdr *)hdr_buf; | |
5e3dd157 | 923 | |
5e3dd157 KV |
924 | first = skb; |
925 | while (skb) { | |
926 | void *decap_hdr; | |
f6dc2095 | 927 | int len; |
5e3dd157 KV |
928 | |
929 | rxd = (void *)skb->data - sizeof(*rxd); | |
930 | fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), | |
f6dc2095 | 931 | RX_MSDU_START_INFO1_DECAP_FORMAT); |
5e3dd157 KV |
932 | decap_hdr = (void *)rxd->rx_hdr_status; |
933 | ||
f6dc2095 | 934 | skb->ip_summed = ath10k_htt_rx_get_csum_state(skb); |
5e3dd157 | 935 | |
f6dc2095 MK |
936 | /* First frame in an A-MSDU chain has more decapped data. */ |
937 | if (skb == first) { | |
938 | len = round_up(ieee80211_hdrlen(hdr->frame_control), 4); | |
7aa7a72a MK |
939 | len += round_up(ath10k_htt_rx_crypto_param_len(ar, |
940 | enctype), 4); | |
f6dc2095 | 941 | decap_hdr += len; |
5e3dd157 KV |
942 | } |
943 | ||
f6dc2095 MK |
944 | switch (fmt) { |
945 | case RX_MSDU_DECAP_RAW: | |
e3fbf8d2 | 946 | /* remove trailing FCS */ |
f6dc2095 MK |
947 | skb_trim(skb, skb->len - FCS_LEN); |
948 | break; | |
949 | case RX_MSDU_DECAP_NATIVE_WIFI: | |
72bdeb86 | 950 | /* pull decapped header and copy SA & DA */ |
784f69d3 | 951 | hdr = (struct ieee80211_hdr *)skb->data; |
d960c369 | 952 | hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr); |
72bdeb86 MK |
953 | memcpy(da, ieee80211_get_DA(hdr), ETH_ALEN); |
954 | memcpy(sa, ieee80211_get_SA(hdr), ETH_ALEN); | |
784f69d3 MK |
955 | skb_pull(skb, hdr_len); |
956 | ||
957 | /* push original 802.11 header */ | |
958 | hdr = (struct ieee80211_hdr *)hdr_buf; | |
959 | hdr_len = ieee80211_hdrlen(hdr->frame_control); | |
960 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
961 | ||
962 | /* original A-MSDU header has the bit set but we're | |
963 | * not including A-MSDU subframe header */ | |
964 | hdr = (struct ieee80211_hdr *)skb->data; | |
965 | qos = ieee80211_get_qos_ctl(hdr); | |
966 | qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; | |
967 | ||
72bdeb86 MK |
968 | /* original 802.11 header has a different DA and in |
969 | * case of 4addr it may also have different SA | |
970 | */ | |
971 | memcpy(ieee80211_get_DA(hdr), da, ETH_ALEN); | |
972 | memcpy(ieee80211_get_SA(hdr), sa, ETH_ALEN); | |
f6dc2095 MK |
973 | break; |
974 | case RX_MSDU_DECAP_ETHERNET2_DIX: | |
e3fbf8d2 MK |
975 | /* strip ethernet header and insert decapped 802.11 |
976 | * header, amsdu subframe header and rfc1042 header */ | |
977 | ||
f6dc2095 MK |
978 | len = 0; |
979 | len += sizeof(struct rfc1042_hdr); | |
980 | len += sizeof(struct amsdu_subframe_hdr); | |
981 | ||
982 | skb_pull(skb, sizeof(struct ethhdr)); | |
983 | memcpy(skb_push(skb, len), decap_hdr, len); | |
984 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
985 | break; | |
986 | case RX_MSDU_DECAP_8023_SNAP_LLC: | |
e3fbf8d2 MK |
987 | /* insert decapped 802.11 header making a singly |
988 | * A-MSDU */ | |
f6dc2095 MK |
989 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); |
990 | break; | |
5e3dd157 KV |
991 | } |
992 | ||
85f6d7cf | 993 | skb_in = skb; |
c071dcb2 MK |
994 | ath10k_htt_rx_h_protected(htt, rx_status, skb_in, enctype, fmt, |
995 | false); | |
5e3dd157 | 996 | skb = skb->next; |
85f6d7cf | 997 | skb_in->next = NULL; |
5e3dd157 | 998 | |
652de35e | 999 | if (skb) |
85f6d7cf | 1000 | rx_status->flag |= RX_FLAG_AMSDU_MORE; |
87326c97 | 1001 | else |
85f6d7cf | 1002 | rx_status->flag &= ~RX_FLAG_AMSDU_MORE; |
652de35e | 1003 | |
85f6d7cf | 1004 | ath10k_process_rx(htt->ar, rx_status, skb_in); |
f6dc2095 | 1005 | } |
5e3dd157 | 1006 | |
f6dc2095 MK |
1007 | /* FIXME: It might be nice to re-assemble the A-MSDU when there's a |
1008 | * monitor interface active for sniffing purposes. */ | |
5e3dd157 KV |
1009 | } |
1010 | ||
85f6d7cf JD |
1011 | static void ath10k_htt_rx_msdu(struct ath10k_htt *htt, |
1012 | struct ieee80211_rx_status *rx_status, | |
1013 | struct sk_buff *skb) | |
5e3dd157 | 1014 | { |
7aa7a72a | 1015 | struct ath10k *ar = htt->ar; |
5e3dd157 KV |
1016 | struct htt_rx_desc *rxd; |
1017 | struct ieee80211_hdr *hdr; | |
1018 | enum rx_msdu_decap_format fmt; | |
1019 | enum htt_rx_mpdu_encrypt_type enctype; | |
e3fbf8d2 MK |
1020 | int hdr_len; |
1021 | void *rfc1042; | |
5e3dd157 KV |
1022 | |
1023 | /* This shouldn't happen. If it does than it may be a FW bug. */ | |
1024 | if (skb->next) { | |
7aa7a72a | 1025 | ath10k_warn(ar, "htt rx received chained non A-MSDU frame\n"); |
5e3dd157 KV |
1026 | ath10k_htt_rx_free_msdu_chain(skb->next); |
1027 | skb->next = NULL; | |
1028 | } | |
1029 | ||
1030 | rxd = (void *)skb->data - sizeof(*rxd); | |
1031 | fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), | |
1032 | RX_MSDU_START_INFO1_DECAP_FORMAT); | |
1033 | enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), | |
1034 | RX_MPDU_START_INFO0_ENCRYPT_TYPE); | |
e3fbf8d2 MK |
1035 | hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; |
1036 | hdr_len = ieee80211_hdrlen(hdr->frame_control); | |
5e3dd157 | 1037 | |
f6dc2095 MK |
1038 | skb->ip_summed = ath10k_htt_rx_get_csum_state(skb); |
1039 | ||
5e3dd157 KV |
1040 | switch (fmt) { |
1041 | case RX_MSDU_DECAP_RAW: | |
1042 | /* remove trailing FCS */ | |
e3fbf8d2 | 1043 | skb_trim(skb, skb->len - FCS_LEN); |
5e3dd157 KV |
1044 | break; |
1045 | case RX_MSDU_DECAP_NATIVE_WIFI: | |
784f69d3 MK |
1046 | /* Pull decapped header */ |
1047 | hdr = (struct ieee80211_hdr *)skb->data; | |
d960c369 | 1048 | hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr); |
784f69d3 MK |
1049 | skb_pull(skb, hdr_len); |
1050 | ||
1051 | /* Push original header */ | |
1052 | hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; | |
1053 | hdr_len = ieee80211_hdrlen(hdr->frame_control); | |
1054 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
5e3dd157 KV |
1055 | break; |
1056 | case RX_MSDU_DECAP_ETHERNET2_DIX: | |
e3fbf8d2 MK |
1057 | /* strip ethernet header and insert decapped 802.11 header and |
1058 | * rfc1042 header */ | |
5e3dd157 | 1059 | |
e3fbf8d2 MK |
1060 | rfc1042 = hdr; |
1061 | rfc1042 += roundup(hdr_len, 4); | |
7aa7a72a MK |
1062 | rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar, |
1063 | enctype), 4); | |
5e3dd157 | 1064 | |
e3fbf8d2 MK |
1065 | skb_pull(skb, sizeof(struct ethhdr)); |
1066 | memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)), | |
1067 | rfc1042, sizeof(struct rfc1042_hdr)); | |
1068 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
1069 | break; | |
1070 | case RX_MSDU_DECAP_8023_SNAP_LLC: | |
1071 | /* remove A-MSDU subframe header and insert | |
1072 | * decapped 802.11 header. rfc1042 header is already there */ | |
5e3dd157 | 1073 | |
e3fbf8d2 MK |
1074 | skb_pull(skb, sizeof(struct amsdu_subframe_hdr)); |
1075 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
1076 | break; | |
5e3dd157 KV |
1077 | } |
1078 | ||
c071dcb2 | 1079 | ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt, false); |
f6dc2095 | 1080 | |
85f6d7cf | 1081 | ath10k_process_rx(htt->ar, rx_status, skb); |
5e3dd157 KV |
1082 | } |
1083 | ||
605f81aa MK |
1084 | static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb) |
1085 | { | |
1086 | struct htt_rx_desc *rxd; | |
1087 | u32 flags, info; | |
1088 | bool is_ip4, is_ip6; | |
1089 | bool is_tcp, is_udp; | |
1090 | bool ip_csum_ok, tcpudp_csum_ok; | |
1091 | ||
1092 | rxd = (void *)skb->data - sizeof(*rxd); | |
1093 | flags = __le32_to_cpu(rxd->attention.flags); | |
1094 | info = __le32_to_cpu(rxd->msdu_start.info1); | |
1095 | ||
1096 | is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO); | |
1097 | is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO); | |
1098 | is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO); | |
1099 | is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO); | |
1100 | ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL); | |
1101 | tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL); | |
1102 | ||
1103 | if (!is_ip4 && !is_ip6) | |
1104 | return CHECKSUM_NONE; | |
1105 | if (!is_tcp && !is_udp) | |
1106 | return CHECKSUM_NONE; | |
1107 | if (!ip_csum_ok) | |
1108 | return CHECKSUM_NONE; | |
1109 | if (!tcpudp_csum_ok) | |
1110 | return CHECKSUM_NONE; | |
1111 | ||
1112 | return CHECKSUM_UNNECESSARY; | |
1113 | } | |
1114 | ||
bfa35368 BG |
1115 | static int ath10k_unchain_msdu(struct sk_buff *msdu_head) |
1116 | { | |
1117 | struct sk_buff *next = msdu_head->next; | |
1118 | struct sk_buff *to_free = next; | |
1119 | int space; | |
1120 | int total_len = 0; | |
1121 | ||
1122 | /* TODO: Might could optimize this by using | |
1123 | * skb_try_coalesce or similar method to | |
1124 | * decrease copying, or maybe get mac80211 to | |
1125 | * provide a way to just receive a list of | |
1126 | * skb? | |
1127 | */ | |
1128 | ||
1129 | msdu_head->next = NULL; | |
1130 | ||
1131 | /* Allocate total length all at once. */ | |
1132 | while (next) { | |
1133 | total_len += next->len; | |
1134 | next = next->next; | |
1135 | } | |
1136 | ||
1137 | space = total_len - skb_tailroom(msdu_head); | |
1138 | if ((space > 0) && | |
1139 | (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) { | |
1140 | /* TODO: bump some rx-oom error stat */ | |
1141 | /* put it back together so we can free the | |
1142 | * whole list at once. | |
1143 | */ | |
1144 | msdu_head->next = to_free; | |
1145 | return -1; | |
1146 | } | |
1147 | ||
1148 | /* Walk list again, copying contents into | |
1149 | * msdu_head | |
1150 | */ | |
1151 | next = to_free; | |
1152 | while (next) { | |
1153 | skb_copy_from_linear_data(next, skb_put(msdu_head, next->len), | |
1154 | next->len); | |
1155 | next = next->next; | |
1156 | } | |
1157 | ||
1158 | /* If here, we have consolidated skb. Free the | |
1159 | * fragments and pass the main skb on up the | |
1160 | * stack. | |
1161 | */ | |
1162 | ath10k_htt_rx_free_msdu_chain(to_free); | |
1163 | return 0; | |
1164 | } | |
1165 | ||
2acc4eb2 JD |
1166 | static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt, |
1167 | struct sk_buff *head, | |
87326c97 | 1168 | enum htt_rx_mpdu_status status, |
78433f96 JD |
1169 | bool channel_set, |
1170 | u32 attention) | |
2acc4eb2 | 1171 | { |
7aa7a72a MK |
1172 | struct ath10k *ar = htt->ar; |
1173 | ||
2acc4eb2 | 1174 | if (head->len == 0) { |
7aa7a72a | 1175 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
2acc4eb2 JD |
1176 | "htt rx dropping due to zero-len\n"); |
1177 | return false; | |
1178 | } | |
1179 | ||
78433f96 | 1180 | if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) { |
7aa7a72a | 1181 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
2acc4eb2 JD |
1182 | "htt rx dropping due to decrypt-err\n"); |
1183 | return false; | |
1184 | } | |
1185 | ||
36653f05 | 1186 | if (!channel_set) { |
7aa7a72a | 1187 | ath10k_warn(ar, "no channel configured; ignoring frame!\n"); |
36653f05 JD |
1188 | return false; |
1189 | } | |
1190 | ||
2acc4eb2 JD |
1191 | /* Skip mgmt frames while we handle this in WMI */ |
1192 | if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL || | |
78433f96 | 1193 | attention & RX_ATTENTION_FLAGS_MGMT_TYPE) { |
7aa7a72a | 1194 | ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n"); |
2acc4eb2 JD |
1195 | return false; |
1196 | } | |
1197 | ||
1198 | if (status != HTT_RX_IND_MPDU_STATUS_OK && | |
1199 | status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR && | |
1200 | status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER && | |
1bbc0975 | 1201 | !htt->ar->monitor_started) { |
7aa7a72a | 1202 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
2acc4eb2 JD |
1203 | "htt rx ignoring frame w/ status %d\n", |
1204 | status); | |
1205 | return false; | |
1206 | } | |
1207 | ||
1208 | if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) { | |
7aa7a72a | 1209 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
2acc4eb2 JD |
1210 | "htt rx CAC running\n"); |
1211 | return false; | |
1212 | } | |
1213 | ||
1214 | return true; | |
1215 | } | |
1216 | ||
5e3dd157 KV |
1217 | static void ath10k_htt_rx_handler(struct ath10k_htt *htt, |
1218 | struct htt_rx_indication *rx) | |
1219 | { | |
7aa7a72a | 1220 | struct ath10k *ar = htt->ar; |
6df92a3d | 1221 | struct ieee80211_rx_status *rx_status = &htt->rx_status; |
5e3dd157 | 1222 | struct htt_rx_indication_mpdu_range *mpdu_ranges; |
78433f96 | 1223 | struct htt_rx_desc *rxd; |
87326c97 | 1224 | enum htt_rx_mpdu_status status; |
5e3dd157 KV |
1225 | struct ieee80211_hdr *hdr; |
1226 | int num_mpdu_ranges; | |
78433f96 | 1227 | u32 attention; |
5e3dd157 KV |
1228 | int fw_desc_len; |
1229 | u8 *fw_desc; | |
78433f96 | 1230 | bool channel_set; |
5e3dd157 | 1231 | int i, j; |
d84dd60f | 1232 | int ret; |
5e3dd157 | 1233 | |
45967089 MK |
1234 | lockdep_assert_held(&htt->rx_ring.lock); |
1235 | ||
5e3dd157 KV |
1236 | fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes); |
1237 | fw_desc = (u8 *)&rx->fw_desc; | |
1238 | ||
1239 | num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1), | |
1240 | HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES); | |
1241 | mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx); | |
1242 | ||
e8dc1a96 | 1243 | /* Fill this once, while this is per-ppdu */ |
2289188c JD |
1244 | if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) { |
1245 | memset(rx_status, 0, sizeof(*rx_status)); | |
1246 | rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR + | |
1247 | rx->ppdu.combined_rssi; | |
1248 | } | |
87326c97 JD |
1249 | |
1250 | if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) { | |
1251 | /* TSF available only in 32-bit */ | |
6df92a3d JD |
1252 | rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff; |
1253 | rx_status->flag |= RX_FLAG_MACTIME_END; | |
87326c97 | 1254 | } |
e8dc1a96 | 1255 | |
6df92a3d | 1256 | channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status); |
36653f05 | 1257 | |
87326c97 | 1258 | if (channel_set) { |
6df92a3d | 1259 | ath10k_htt_rx_h_rates(htt->ar, rx_status->band, |
87326c97 JD |
1260 | rx->ppdu.info0, |
1261 | __le32_to_cpu(rx->ppdu.info1), | |
1262 | __le32_to_cpu(rx->ppdu.info2), | |
6df92a3d | 1263 | rx_status); |
87326c97 | 1264 | } |
e8dc1a96 | 1265 | |
7aa7a72a | 1266 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ", |
5e3dd157 KV |
1267 | rx, sizeof(*rx) + |
1268 | (sizeof(struct htt_rx_indication_mpdu_range) * | |
1269 | num_mpdu_ranges)); | |
1270 | ||
1271 | for (i = 0; i < num_mpdu_ranges; i++) { | |
87326c97 | 1272 | status = mpdu_ranges[i].mpdu_range_status; |
5e3dd157 KV |
1273 | |
1274 | for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) { | |
1275 | struct sk_buff *msdu_head, *msdu_tail; | |
5e3dd157 | 1276 | |
0ccb7a34 | 1277 | attention = 0; |
5e3dd157 KV |
1278 | msdu_head = NULL; |
1279 | msdu_tail = NULL; | |
d84dd60f JD |
1280 | ret = ath10k_htt_rx_amsdu_pop(htt, |
1281 | &fw_desc, | |
1282 | &fw_desc_len, | |
1283 | &msdu_head, | |
0ccb7a34 JD |
1284 | &msdu_tail, |
1285 | &attention); | |
d84dd60f JD |
1286 | |
1287 | if (ret < 0) { | |
7aa7a72a | 1288 | ath10k_warn(ar, "failed to pop amsdu from htt rx ring %d\n", |
d84dd60f JD |
1289 | ret); |
1290 | ath10k_htt_rx_free_msdu_chain(msdu_head); | |
1291 | continue; | |
1292 | } | |
5e3dd157 | 1293 | |
78433f96 JD |
1294 | rxd = container_of((void *)msdu_head->data, |
1295 | struct htt_rx_desc, | |
1296 | msdu_payload); | |
78433f96 | 1297 | |
2acc4eb2 | 1298 | if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head, |
87326c97 | 1299 | status, |
78433f96 JD |
1300 | channel_set, |
1301 | attention)) { | |
e8a50f8b MP |
1302 | ath10k_htt_rx_free_msdu_chain(msdu_head); |
1303 | continue; | |
1304 | } | |
1305 | ||
d84dd60f JD |
1306 | if (ret > 0 && |
1307 | ath10k_unchain_msdu(msdu_head) < 0) { | |
5e3dd157 KV |
1308 | ath10k_htt_rx_free_msdu_chain(msdu_head); |
1309 | continue; | |
1310 | } | |
1311 | ||
78433f96 | 1312 | if (attention & RX_ATTENTION_FLAGS_FCS_ERR) |
6df92a3d | 1313 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; |
87326c97 | 1314 | else |
6df92a3d | 1315 | rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC; |
87326c97 | 1316 | |
78433f96 | 1317 | if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR) |
6df92a3d | 1318 | rx_status->flag |= RX_FLAG_MMIC_ERROR; |
87326c97 | 1319 | else |
6df92a3d | 1320 | rx_status->flag &= ~RX_FLAG_MMIC_ERROR; |
87326c97 | 1321 | |
5e3dd157 KV |
1322 | hdr = ath10k_htt_rx_skb_get_hdr(msdu_head); |
1323 | ||
1324 | if (ath10k_htt_rx_hdr_is_amsdu(hdr)) | |
6df92a3d | 1325 | ath10k_htt_rx_amsdu(htt, rx_status, msdu_head); |
5e3dd157 | 1326 | else |
6df92a3d | 1327 | ath10k_htt_rx_msdu(htt, rx_status, msdu_head); |
5e3dd157 KV |
1328 | } |
1329 | } | |
1330 | ||
6e712d42 | 1331 | tasklet_schedule(&htt->rx_replenish_task); |
5e3dd157 KV |
1332 | } |
1333 | ||
1334 | static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt, | |
1335 | struct htt_rx_fragment_indication *frag) | |
1336 | { | |
7aa7a72a | 1337 | struct ath10k *ar = htt->ar; |
5e3dd157 | 1338 | struct sk_buff *msdu_head, *msdu_tail; |
87326c97 | 1339 | enum htt_rx_mpdu_encrypt_type enctype; |
5e3dd157 KV |
1340 | struct htt_rx_desc *rxd; |
1341 | enum rx_msdu_decap_format fmt; | |
6df92a3d | 1342 | struct ieee80211_rx_status *rx_status = &htt->rx_status; |
5e3dd157 | 1343 | struct ieee80211_hdr *hdr; |
d84dd60f | 1344 | int ret; |
5e3dd157 KV |
1345 | bool tkip_mic_err; |
1346 | bool decrypt_err; | |
1347 | u8 *fw_desc; | |
1348 | int fw_desc_len, hdrlen, paramlen; | |
1349 | int trim; | |
0ccb7a34 | 1350 | u32 attention = 0; |
5e3dd157 KV |
1351 | |
1352 | fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes); | |
1353 | fw_desc = (u8 *)frag->fw_msdu_rx_desc; | |
1354 | ||
1355 | msdu_head = NULL; | |
1356 | msdu_tail = NULL; | |
45967089 MK |
1357 | |
1358 | spin_lock_bh(&htt->rx_ring.lock); | |
d84dd60f | 1359 | ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len, |
0ccb7a34 JD |
1360 | &msdu_head, &msdu_tail, |
1361 | &attention); | |
45967089 | 1362 | spin_unlock_bh(&htt->rx_ring.lock); |
5e3dd157 | 1363 | |
7aa7a72a | 1364 | ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n"); |
5e3dd157 | 1365 | |
d84dd60f | 1366 | if (ret) { |
7aa7a72a | 1367 | ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n", |
d84dd60f | 1368 | ret); |
5e3dd157 KV |
1369 | ath10k_htt_rx_free_msdu_chain(msdu_head); |
1370 | return; | |
1371 | } | |
1372 | ||
1373 | /* FIXME: implement signal strength */ | |
4b81d177 | 1374 | rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; |
5e3dd157 KV |
1375 | |
1376 | hdr = (struct ieee80211_hdr *)msdu_head->data; | |
1377 | rxd = (void *)msdu_head->data - sizeof(*rxd); | |
0ccb7a34 JD |
1378 | tkip_mic_err = !!(attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR); |
1379 | decrypt_err = !!(attention & RX_ATTENTION_FLAGS_DECRYPT_ERR); | |
5e3dd157 KV |
1380 | fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), |
1381 | RX_MSDU_START_INFO1_DECAP_FORMAT); | |
1382 | ||
1383 | if (fmt != RX_MSDU_DECAP_RAW) { | |
7aa7a72a | 1384 | ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n"); |
5e3dd157 KV |
1385 | dev_kfree_skb_any(msdu_head); |
1386 | goto end; | |
1387 | } | |
1388 | ||
87326c97 JD |
1389 | enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), |
1390 | RX_MPDU_START_INFO0_ENCRYPT_TYPE); | |
c071dcb2 MK |
1391 | ath10k_htt_rx_h_protected(htt, rx_status, msdu_head, enctype, fmt, |
1392 | true); | |
85f6d7cf | 1393 | msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head); |
5e3dd157 | 1394 | |
87326c97 | 1395 | if (tkip_mic_err) |
7aa7a72a | 1396 | ath10k_warn(ar, "tkip mic error\n"); |
5e3dd157 KV |
1397 | |
1398 | if (decrypt_err) { | |
7aa7a72a | 1399 | ath10k_warn(ar, "decryption err in fragmented rx\n"); |
85f6d7cf | 1400 | dev_kfree_skb_any(msdu_head); |
5e3dd157 KV |
1401 | goto end; |
1402 | } | |
1403 | ||
87326c97 | 1404 | if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) { |
5e3dd157 | 1405 | hdrlen = ieee80211_hdrlen(hdr->frame_control); |
7aa7a72a | 1406 | paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype); |
5e3dd157 KV |
1407 | |
1408 | /* It is more efficient to move the header than the payload */ | |
85f6d7cf JD |
1409 | memmove((void *)msdu_head->data + paramlen, |
1410 | (void *)msdu_head->data, | |
5e3dd157 | 1411 | hdrlen); |
85f6d7cf JD |
1412 | skb_pull(msdu_head, paramlen); |
1413 | hdr = (struct ieee80211_hdr *)msdu_head->data; | |
5e3dd157 KV |
1414 | } |
1415 | ||
1416 | /* remove trailing FCS */ | |
1417 | trim = 4; | |
1418 | ||
1419 | /* remove crypto trailer */ | |
7aa7a72a | 1420 | trim += ath10k_htt_rx_crypto_tail_len(ar, enctype); |
5e3dd157 KV |
1421 | |
1422 | /* last fragment of TKIP frags has MIC */ | |
1423 | if (!ieee80211_has_morefrags(hdr->frame_control) && | |
87326c97 | 1424 | enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA) |
5e3dd157 KV |
1425 | trim += 8; |
1426 | ||
85f6d7cf | 1427 | if (trim > msdu_head->len) { |
7aa7a72a | 1428 | ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n"); |
85f6d7cf | 1429 | dev_kfree_skb_any(msdu_head); |
5e3dd157 KV |
1430 | goto end; |
1431 | } | |
1432 | ||
85f6d7cf | 1433 | skb_trim(msdu_head, msdu_head->len - trim); |
5e3dd157 | 1434 | |
7aa7a72a | 1435 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ", |
85f6d7cf | 1436 | msdu_head->data, msdu_head->len); |
6df92a3d | 1437 | ath10k_process_rx(htt->ar, rx_status, msdu_head); |
5e3dd157 KV |
1438 | |
1439 | end: | |
1440 | if (fw_desc_len > 0) { | |
7aa7a72a | 1441 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
5e3dd157 KV |
1442 | "expecting more fragmented rx in one indication %d\n", |
1443 | fw_desc_len); | |
1444 | } | |
1445 | } | |
1446 | ||
6c5151a9 MK |
1447 | static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar, |
1448 | struct sk_buff *skb) | |
1449 | { | |
1450 | struct ath10k_htt *htt = &ar->htt; | |
1451 | struct htt_resp *resp = (struct htt_resp *)skb->data; | |
1452 | struct htt_tx_done tx_done = {}; | |
1453 | int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS); | |
1454 | __le16 msdu_id; | |
1455 | int i; | |
1456 | ||
45967089 MK |
1457 | lockdep_assert_held(&htt->tx_lock); |
1458 | ||
6c5151a9 MK |
1459 | switch (status) { |
1460 | case HTT_DATA_TX_STATUS_NO_ACK: | |
1461 | tx_done.no_ack = true; | |
1462 | break; | |
1463 | case HTT_DATA_TX_STATUS_OK: | |
1464 | break; | |
1465 | case HTT_DATA_TX_STATUS_DISCARD: | |
1466 | case HTT_DATA_TX_STATUS_POSTPONE: | |
1467 | case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL: | |
1468 | tx_done.discard = true; | |
1469 | break; | |
1470 | default: | |
7aa7a72a | 1471 | ath10k_warn(ar, "unhandled tx completion status %d\n", status); |
6c5151a9 MK |
1472 | tx_done.discard = true; |
1473 | break; | |
1474 | } | |
1475 | ||
7aa7a72a | 1476 | ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n", |
6c5151a9 MK |
1477 | resp->data_tx_completion.num_msdus); |
1478 | ||
1479 | for (i = 0; i < resp->data_tx_completion.num_msdus; i++) { | |
1480 | msdu_id = resp->data_tx_completion.msdus[i]; | |
1481 | tx_done.msdu_id = __le16_to_cpu(msdu_id); | |
1482 | ath10k_txrx_tx_unref(htt, &tx_done); | |
1483 | } | |
1484 | } | |
1485 | ||
aa5b4fbc MK |
1486 | static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp) |
1487 | { | |
1488 | struct htt_rx_addba *ev = &resp->rx_addba; | |
1489 | struct ath10k_peer *peer; | |
1490 | struct ath10k_vif *arvif; | |
1491 | u16 info0, tid, peer_id; | |
1492 | ||
1493 | info0 = __le16_to_cpu(ev->info0); | |
1494 | tid = MS(info0, HTT_RX_BA_INFO0_TID); | |
1495 | peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID); | |
1496 | ||
7aa7a72a | 1497 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
aa5b4fbc MK |
1498 | "htt rx addba tid %hu peer_id %hu size %hhu\n", |
1499 | tid, peer_id, ev->window_size); | |
1500 | ||
1501 | spin_lock_bh(&ar->data_lock); | |
1502 | peer = ath10k_peer_find_by_id(ar, peer_id); | |
1503 | if (!peer) { | |
7aa7a72a | 1504 | ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n", |
aa5b4fbc MK |
1505 | peer_id); |
1506 | spin_unlock_bh(&ar->data_lock); | |
1507 | return; | |
1508 | } | |
1509 | ||
1510 | arvif = ath10k_get_arvif(ar, peer->vdev_id); | |
1511 | if (!arvif) { | |
7aa7a72a | 1512 | ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n", |
aa5b4fbc MK |
1513 | peer->vdev_id); |
1514 | spin_unlock_bh(&ar->data_lock); | |
1515 | return; | |
1516 | } | |
1517 | ||
7aa7a72a | 1518 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
aa5b4fbc MK |
1519 | "htt rx start rx ba session sta %pM tid %hu size %hhu\n", |
1520 | peer->addr, tid, ev->window_size); | |
1521 | ||
1522 | ieee80211_start_rx_ba_session_offl(arvif->vif, peer->addr, tid); | |
1523 | spin_unlock_bh(&ar->data_lock); | |
1524 | } | |
1525 | ||
1526 | static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp) | |
1527 | { | |
1528 | struct htt_rx_delba *ev = &resp->rx_delba; | |
1529 | struct ath10k_peer *peer; | |
1530 | struct ath10k_vif *arvif; | |
1531 | u16 info0, tid, peer_id; | |
1532 | ||
1533 | info0 = __le16_to_cpu(ev->info0); | |
1534 | tid = MS(info0, HTT_RX_BA_INFO0_TID); | |
1535 | peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID); | |
1536 | ||
7aa7a72a | 1537 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
aa5b4fbc MK |
1538 | "htt rx delba tid %hu peer_id %hu\n", |
1539 | tid, peer_id); | |
1540 | ||
1541 | spin_lock_bh(&ar->data_lock); | |
1542 | peer = ath10k_peer_find_by_id(ar, peer_id); | |
1543 | if (!peer) { | |
7aa7a72a | 1544 | ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n", |
aa5b4fbc MK |
1545 | peer_id); |
1546 | spin_unlock_bh(&ar->data_lock); | |
1547 | return; | |
1548 | } | |
1549 | ||
1550 | arvif = ath10k_get_arvif(ar, peer->vdev_id); | |
1551 | if (!arvif) { | |
7aa7a72a | 1552 | ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n", |
aa5b4fbc MK |
1553 | peer->vdev_id); |
1554 | spin_unlock_bh(&ar->data_lock); | |
1555 | return; | |
1556 | } | |
1557 | ||
7aa7a72a | 1558 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
aa5b4fbc MK |
1559 | "htt rx stop rx ba session sta %pM tid %hu\n", |
1560 | peer->addr, tid); | |
1561 | ||
1562 | ieee80211_stop_rx_ba_session_offl(arvif->vif, peer->addr, tid); | |
1563 | spin_unlock_bh(&ar->data_lock); | |
1564 | } | |
1565 | ||
5e3dd157 KV |
1566 | void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) |
1567 | { | |
edb8236d | 1568 | struct ath10k_htt *htt = &ar->htt; |
5e3dd157 KV |
1569 | struct htt_resp *resp = (struct htt_resp *)skb->data; |
1570 | ||
1571 | /* confirm alignment */ | |
1572 | if (!IS_ALIGNED((unsigned long)skb->data, 4)) | |
7aa7a72a | 1573 | ath10k_warn(ar, "unaligned htt message, expect trouble\n"); |
5e3dd157 | 1574 | |
7aa7a72a | 1575 | ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n", |
5e3dd157 KV |
1576 | resp->hdr.msg_type); |
1577 | switch (resp->hdr.msg_type) { | |
1578 | case HTT_T2H_MSG_TYPE_VERSION_CONF: { | |
1579 | htt->target_version_major = resp->ver_resp.major; | |
1580 | htt->target_version_minor = resp->ver_resp.minor; | |
1581 | complete(&htt->target_version_received); | |
1582 | break; | |
1583 | } | |
6c5151a9 | 1584 | case HTT_T2H_MSG_TYPE_RX_IND: |
45967089 MK |
1585 | spin_lock_bh(&htt->rx_ring.lock); |
1586 | __skb_queue_tail(&htt->rx_compl_q, skb); | |
1587 | spin_unlock_bh(&htt->rx_ring.lock); | |
6c5151a9 MK |
1588 | tasklet_schedule(&htt->txrx_compl_task); |
1589 | return; | |
5e3dd157 KV |
1590 | case HTT_T2H_MSG_TYPE_PEER_MAP: { |
1591 | struct htt_peer_map_event ev = { | |
1592 | .vdev_id = resp->peer_map.vdev_id, | |
1593 | .peer_id = __le16_to_cpu(resp->peer_map.peer_id), | |
1594 | }; | |
1595 | memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr)); | |
1596 | ath10k_peer_map_event(htt, &ev); | |
1597 | break; | |
1598 | } | |
1599 | case HTT_T2H_MSG_TYPE_PEER_UNMAP: { | |
1600 | struct htt_peer_unmap_event ev = { | |
1601 | .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id), | |
1602 | }; | |
1603 | ath10k_peer_unmap_event(htt, &ev); | |
1604 | break; | |
1605 | } | |
1606 | case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: { | |
1607 | struct htt_tx_done tx_done = {}; | |
1608 | int status = __le32_to_cpu(resp->mgmt_tx_completion.status); | |
1609 | ||
1610 | tx_done.msdu_id = | |
1611 | __le32_to_cpu(resp->mgmt_tx_completion.desc_id); | |
1612 | ||
1613 | switch (status) { | |
1614 | case HTT_MGMT_TX_STATUS_OK: | |
1615 | break; | |
1616 | case HTT_MGMT_TX_STATUS_RETRY: | |
1617 | tx_done.no_ack = true; | |
1618 | break; | |
1619 | case HTT_MGMT_TX_STATUS_DROP: | |
1620 | tx_done.discard = true; | |
1621 | break; | |
1622 | } | |
1623 | ||
6c5151a9 | 1624 | spin_lock_bh(&htt->tx_lock); |
0a89f8a0 | 1625 | ath10k_txrx_tx_unref(htt, &tx_done); |
6c5151a9 | 1626 | spin_unlock_bh(&htt->tx_lock); |
5e3dd157 KV |
1627 | break; |
1628 | } | |
6c5151a9 MK |
1629 | case HTT_T2H_MSG_TYPE_TX_COMPL_IND: |
1630 | spin_lock_bh(&htt->tx_lock); | |
1631 | __skb_queue_tail(&htt->tx_compl_q, skb); | |
1632 | spin_unlock_bh(&htt->tx_lock); | |
1633 | tasklet_schedule(&htt->txrx_compl_task); | |
1634 | return; | |
5e3dd157 KV |
1635 | case HTT_T2H_MSG_TYPE_SEC_IND: { |
1636 | struct ath10k *ar = htt->ar; | |
1637 | struct htt_security_indication *ev = &resp->security_indication; | |
1638 | ||
7aa7a72a | 1639 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
5e3dd157 KV |
1640 | "sec ind peer_id %d unicast %d type %d\n", |
1641 | __le16_to_cpu(ev->peer_id), | |
1642 | !!(ev->flags & HTT_SECURITY_IS_UNICAST), | |
1643 | MS(ev->flags, HTT_SECURITY_TYPE)); | |
1644 | complete(&ar->install_key_done); | |
1645 | break; | |
1646 | } | |
1647 | case HTT_T2H_MSG_TYPE_RX_FRAG_IND: { | |
7aa7a72a | 1648 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", |
5e3dd157 KV |
1649 | skb->data, skb->len); |
1650 | ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind); | |
1651 | break; | |
1652 | } | |
1653 | case HTT_T2H_MSG_TYPE_TEST: | |
1654 | /* FIX THIS */ | |
1655 | break; | |
5e3dd157 | 1656 | case HTT_T2H_MSG_TYPE_STATS_CONF: |
d35a6c18 | 1657 | trace_ath10k_htt_stats(ar, skb->data, skb->len); |
a9bf0506 KV |
1658 | break; |
1659 | case HTT_T2H_MSG_TYPE_TX_INSPECT_IND: | |
708b9bde MK |
1660 | /* Firmware can return tx frames if it's unable to fully |
1661 | * process them and suspects host may be able to fix it. ath10k | |
1662 | * sends all tx frames as already inspected so this shouldn't | |
1663 | * happen unless fw has a bug. | |
1664 | */ | |
7aa7a72a | 1665 | ath10k_warn(ar, "received an unexpected htt tx inspect event\n"); |
708b9bde | 1666 | break; |
5e3dd157 | 1667 | case HTT_T2H_MSG_TYPE_RX_ADDBA: |
aa5b4fbc MK |
1668 | ath10k_htt_rx_addba(ar, resp); |
1669 | break; | |
5e3dd157 | 1670 | case HTT_T2H_MSG_TYPE_RX_DELBA: |
aa5b4fbc MK |
1671 | ath10k_htt_rx_delba(ar, resp); |
1672 | break; | |
1673 | case HTT_T2H_MSG_TYPE_RX_FLUSH: { | |
1674 | /* Ignore this event because mac80211 takes care of Rx | |
1675 | * aggregation reordering. | |
1676 | */ | |
1677 | break; | |
1678 | } | |
5e3dd157 | 1679 | default: |
7aa7a72a | 1680 | ath10k_dbg(ar, ATH10K_DBG_HTT, "htt event (%d) not handled\n", |
5e3dd157 | 1681 | resp->hdr.msg_type); |
7aa7a72a | 1682 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", |
5e3dd157 KV |
1683 | skb->data, skb->len); |
1684 | break; | |
1685 | }; | |
1686 | ||
1687 | /* Free the indication buffer */ | |
1688 | dev_kfree_skb_any(skb); | |
1689 | } | |
6c5151a9 MK |
1690 | |
1691 | static void ath10k_htt_txrx_compl_task(unsigned long ptr) | |
1692 | { | |
1693 | struct ath10k_htt *htt = (struct ath10k_htt *)ptr; | |
1694 | struct htt_resp *resp; | |
1695 | struct sk_buff *skb; | |
1696 | ||
45967089 MK |
1697 | spin_lock_bh(&htt->tx_lock); |
1698 | while ((skb = __skb_dequeue(&htt->tx_compl_q))) { | |
6c5151a9 MK |
1699 | ath10k_htt_rx_frm_tx_compl(htt->ar, skb); |
1700 | dev_kfree_skb_any(skb); | |
1701 | } | |
45967089 | 1702 | spin_unlock_bh(&htt->tx_lock); |
6c5151a9 | 1703 | |
45967089 MK |
1704 | spin_lock_bh(&htt->rx_ring.lock); |
1705 | while ((skb = __skb_dequeue(&htt->rx_compl_q))) { | |
6c5151a9 MK |
1706 | resp = (struct htt_resp *)skb->data; |
1707 | ath10k_htt_rx_handler(htt, &resp->rx_ind); | |
1708 | dev_kfree_skb_any(skb); | |
1709 | } | |
45967089 | 1710 | spin_unlock_bh(&htt->rx_ring.lock); |
6c5151a9 | 1711 | } |