[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / htt_tx.c

/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/etherdevice.h>
#include "htt.h"
#include "mac.h"
#include "hif.h"
#include "txrx.h"
#include "debug.h"

void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
{
	htt->num_pending_tx--;
	if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
		ieee80211_wake_queues(htt->ar->hw);
}

static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
{
	spin_lock_bh(&htt->tx_lock);
	__ath10k_htt_tx_dec_pending(htt);
	spin_unlock_bh(&htt->tx_lock);
}

static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
{
	int ret = 0;

	spin_lock_bh(&htt->tx_lock);

	if (htt->num_pending_tx >= htt->max_num_pending_tx) {
		ret = -EBUSY;
		goto exit;
	}

	htt->num_pending_tx++;
	if (htt->num_pending_tx == htt->max_num_pending_tx)
		ieee80211_stop_queues(htt->ar->hw);

exit:
	spin_unlock_bh(&htt->tx_lock);
	return ret;
}

int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb)
{
	struct ath10k *ar = htt->ar;
	int ret;

	lockdep_assert_held(&htt->tx_lock);

	ret = idr_alloc(&htt->pending_tx, skb, 0, 0x10000, GFP_ATOMIC);

	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret);

	return ret;
}

void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
{
	struct ath10k *ar = htt->ar;

	lockdep_assert_held(&htt->tx_lock);

	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);

	idr_remove(&htt->pending_tx, msdu_id);
}

int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
{
	struct ath10k *ar = htt->ar;

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
		   htt->max_num_pending_tx);

	spin_lock_init(&htt->tx_lock);
	idr_init(&htt->pending_tx);

	htt->tx_pool = dma_pool_create("ath10k htt tx pool", htt->ar->dev,
				       sizeof(struct ath10k_htt_txbuf), 4, 0);
	if (!htt->tx_pool) {
		idr_destroy(&htt->pending_tx);
		return -ENOMEM;
	}

	return 0;
}

static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx)
{
	struct ath10k *ar = ctx;
	struct ath10k_htt *htt = &ar->htt;
	struct htt_tx_done tx_done = {0};

	ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id);

	tx_done.discard = 1;
	tx_done.msdu_id = msdu_id;

	spin_lock_bh(&htt->tx_lock);
	ath10k_txrx_tx_unref(htt, &tx_done);
	spin_unlock_bh(&htt->tx_lock);

	return 0;
}

void ath10k_htt_tx_free(struct ath10k_htt *htt)
{
	idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar);
	idr_destroy(&htt->pending_tx);
	dma_pool_destroy(htt->tx_pool);
}

void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
}

int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
{
	struct ath10k *ar = htt->ar;
	struct sk_buff *skb;
	struct htt_cmd *cmd;
	int len = 0;
	int ret;

	len += sizeof(cmd->hdr);
	len += sizeof(cmd->ver_req);

	skb = ath10k_htc_alloc_skb(ar, len);
	if (!skb)
		return -ENOMEM;

	skb_put(skb, len);
	cmd = (struct htt_cmd *)skb->data;
	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	if (ret) {
		dev_kfree_skb_any(skb);
		return ret;
	}

	return 0;
}

int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
{
	struct ath10k *ar = htt->ar;
	struct htt_stats_req *req;
	struct sk_buff *skb;
	struct htt_cmd *cmd;
	int len = 0, ret;

	len += sizeof(cmd->hdr);
	len += sizeof(cmd->stats_req);

	skb = ath10k_htc_alloc_skb(ar, len);
	if (!skb)
		return -ENOMEM;

	skb_put(skb, len);
	cmd = (struct htt_cmd *)skb->data;
	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;

	req = &cmd->stats_req;

	memset(req, 0, sizeof(*req));

	/* currently we support only max 8 bit masks so no need to worry
	 * about endian support */
	req->upload_types[0] = mask;
	req->reset_types[0] = mask;
	req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
	req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
	req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	if (ret) {
		ath10k_warn(ar, "failed to send htt type stats request: %d",
			    ret);
		dev_kfree_skb_any(skb);
		return ret;
	}

	return 0;
}

int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
{
	struct ath10k *ar = htt->ar;
	struct sk_buff *skb;
	struct htt_cmd *cmd;
	struct htt_rx_ring_setup_ring *ring;
	const int num_rx_ring = 1;
	u16 flags;
	u32 fw_idx;
	int len;
	int ret;

	/*
	 * the HW expects the buffer to be an integral number of 4-byte
	 * "words"
	 */
	BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
	BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);

	len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
	    + (sizeof(*ring) * num_rx_ring);
	skb = ath10k_htc_alloc_skb(ar, len);
	if (!skb)
		return -ENOMEM;

	skb_put(skb, len);

	cmd = (struct htt_cmd *)skb->data;
	ring = &cmd->rx_setup.rings[0];

	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
	cmd->rx_setup.hdr.num_rings = 1;

	/* FIXME: do we need all of this? */
	flags = 0;
	flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
	flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
	flags |= HTT_RX_RING_FLAGS_PPDU_START;
	flags |= HTT_RX_RING_FLAGS_PPDU_END;
	flags |= HTT_RX_RING_FLAGS_MPDU_START;
	flags |= HTT_RX_RING_FLAGS_MPDU_END;
	flags |= HTT_RX_RING_FLAGS_MSDU_START;
	flags |= HTT_RX_RING_FLAGS_MSDU_END;
	flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
	flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
	flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
	flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
	flags |= HTT_RX_RING_FLAGS_CTRL_RX;
	flags |= HTT_RX_RING_FLAGS_MGMT_RX;
	flags |= HTT_RX_RING_FLAGS_NULL_RX;
	flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;

	fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);

	ring->fw_idx_shadow_reg_paddr =
		__cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
	ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
	ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
	ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
	ring->flags = __cpu_to_le16(flags);
	ring->fw_idx_init_val = __cpu_to_le16(fw_idx);

#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)

	ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
	ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
	ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
	ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
	ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
	ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
	ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
	ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
	ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
	ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));

#undef desc_offset

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	if (ret) {
		dev_kfree_skb_any(skb);
		return ret;
	}

	return 0;
}

int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
				u8 max_subfrms_ampdu,
				u8 max_subfrms_amsdu)
{
	struct ath10k *ar = htt->ar;
	struct htt_aggr_conf *aggr_conf;
	struct sk_buff *skb;
	struct htt_cmd *cmd;
	int len;
	int ret;

	/* Firmware defaults are: amsdu = 3 and ampdu = 64 */

	if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
		return -EINVAL;

	if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
		return -EINVAL;

	len = sizeof(cmd->hdr);
	len += sizeof(cmd->aggr_conf);

	skb = ath10k_htc_alloc_skb(ar, len);
	if (!skb)
		return -ENOMEM;

	skb_put(skb, len);
	cmd = (struct htt_cmd *)skb->data;
	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;

	aggr_conf = &cmd->aggr_conf;
	aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
	aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;

	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
		   aggr_conf->max_num_amsdu_subframes,
		   aggr_conf->max_num_ampdu_subframes);

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	if (ret) {
		dev_kfree_skb_any(skb);
		return ret;
	}

	return 0;
}

int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
{
	struct ath10k *ar = htt->ar;
	struct device *dev = ar->dev;
	struct sk_buff *txdesc = NULL;
	struct htt_cmd *cmd;
	struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
	u8 vdev_id = skb_cb->vdev_id;
	int len = 0;
	int msdu_id = -1;
	int res;

	res = ath10k_htt_tx_inc_pending(htt);
	if (res)
		goto err;

	len += sizeof(cmd->hdr);
	len += sizeof(cmd->mgmt_tx);

	spin_lock_bh(&htt->tx_lock);
	res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
	if (res < 0) {
		spin_unlock_bh(&htt->tx_lock);
		goto err_tx_dec;
	}
	msdu_id = res;
	spin_unlock_bh(&htt->tx_lock);

	txdesc = ath10k_htc_alloc_skb(ar, len);
	if (!txdesc) {
		res = -ENOMEM;
		goto err_free_msdu_id;
	}

	skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
				       DMA_TO_DEVICE);
	res = dma_mapping_error(dev, skb_cb->paddr);
	if (res)
		goto err_free_txdesc;

	skb_put(txdesc, len);
	cmd = (struct htt_cmd *)txdesc->data;
	cmd->hdr.msg_type         = HTT_H2T_MSG_TYPE_MGMT_TX;
	cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
	cmd->mgmt_tx.len        = __cpu_to_le32(msdu->len);
	cmd->mgmt_tx.desc_id    = __cpu_to_le32(msdu_id);
	cmd->mgmt_tx.vdev_id    = __cpu_to_le32(vdev_id);
	memcpy(cmd->mgmt_tx.hdr, msdu->data,
	       min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));

	skb_cb->htt.txbuf = NULL;

	res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
	if (res)
		goto err_unmap_msdu;

	return 0;

err_unmap_msdu:
	dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
err_free_txdesc:
	dev_kfree_skb_any(txdesc);
err_free_msdu_id:
	spin_lock_bh(&htt->tx_lock);
	ath10k_htt_tx_free_msdu_id(htt, msdu_id);
	spin_unlock_bh(&htt->tx_lock);
err_tx_dec:
	ath10k_htt_tx_dec_pending(htt);
err:
	return res;
}

int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
{
	struct ath10k *ar = htt->ar;
	struct device *dev = ar->dev;
	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
	struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
	struct ath10k_hif_sg_item sg_items[2];
	struct htt_data_tx_desc_frag *frags;
	u8 vdev_id = skb_cb->vdev_id;
	u8 tid = skb_cb->htt.tid;
	int prefetch_len;
	int res;
	u8 flags0 = 0;
	u16 msdu_id, flags1 = 0;
	dma_addr_t paddr;
	u32 frags_paddr;
	bool use_frags;

	res = ath10k_htt_tx_inc_pending(htt);
	if (res)
		goto err;

	spin_lock_bh(&htt->tx_lock);
	res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
	if (res < 0) {
		spin_unlock_bh(&htt->tx_lock);
		goto err_tx_dec;
	}
	msdu_id = res;
	spin_unlock_bh(&htt->tx_lock);

	prefetch_len = min(htt->prefetch_len, msdu->len);
	prefetch_len = roundup(prefetch_len, 4);

	/* Since HTT 3.0 there is no separate mgmt tx command. However in case
	 * of mgmt tx using TX_FRM there is not tx fragment list. Instead of tx
	 * fragment list host driver specifies directly frame pointer. */
	use_frags = htt->target_version_major < 3 ||
		    !ieee80211_is_mgmt(hdr->frame_control);

	skb_cb->htt.txbuf = dma_pool_alloc(htt->tx_pool, GFP_ATOMIC,
					   &paddr);
	if (!skb_cb->htt.txbuf) {
		res = -ENOMEM;
		goto err_free_msdu_id;
	}
	skb_cb->htt.txbuf_paddr = paddr;

	skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
				       DMA_TO_DEVICE);
	res = dma_mapping_error(dev, skb_cb->paddr);
	if (res)
		goto err_free_txbuf;

	if (likely(use_frags)) {
		frags = skb_cb->htt.txbuf->frags;

		frags[0].paddr = __cpu_to_le32(skb_cb->paddr);
		frags[0].len = __cpu_to_le32(msdu->len);
		frags[1].paddr = 0;
		frags[1].len = 0;

		flags0 |= SM(ATH10K_HW_TXRX_NATIVE_WIFI,
			     HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);

		frags_paddr = skb_cb->htt.txbuf_paddr;
	} else {
		flags0 |= SM(ATH10K_HW_TXRX_MGMT,
			     HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);

		frags_paddr = skb_cb->paddr;
	}

	/* Normally all commands go through HTC which manages tx credits for
	 * each endpoint and notifies when tx is completed.
	 *
	 * HTT endpoint is creditless so there's no need to care about HTC
	 * flags. In that case it is trivial to fill the HTC header here.
	 *
	 * MSDU transmission is considered completed upon HTT event. This
	 * implies no relevant resources can be freed until after the event is
	 * received. That's why HTC tx completion handler itself is ignored by
	 * setting NULL to transfer_context for all sg items.
	 *
	 * There is simply no point in pushing HTT TX_FRM through HTC tx path
	 * as it's a waste of resources. By bypassing HTC it is possible to
	 * avoid extra memory allocations, compress data structures and thus
	 * improve performance. */

	skb_cb->htt.txbuf->htc_hdr.eid = htt->eid;
	skb_cb->htt.txbuf->htc_hdr.len = __cpu_to_le16(
			sizeof(skb_cb->htt.txbuf->cmd_hdr) +
			sizeof(skb_cb->htt.txbuf->cmd_tx) +
			prefetch_len);
	skb_cb->htt.txbuf->htc_hdr.flags = 0;

	if (!ieee80211_has_protected(hdr->frame_control))
		flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;

	flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;

	flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
	flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
	flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
	flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;

	/* Prevent firmware from sending up tx inspection requests. There's
	 * nothing ath10k can do with frames requested for inspection so force
	 * it to simply rely a regular tx completion with discard status.
	 */
	flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;

	skb_cb->htt.txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
	skb_cb->htt.txbuf->cmd_tx.flags0 = flags0;
	skb_cb->htt.txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
	skb_cb->htt.txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
	skb_cb->htt.txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
	skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
	skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le16(HTT_INVALID_PEERID);
	skb_cb->htt.txbuf->cmd_tx.freq = __cpu_to_le16(skb_cb->htt.freq);

	trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
	ath10k_dbg(ar, ATH10K_DBG_HTT,
		   "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n",
		   flags0, flags1, msdu->len, msdu_id, frags_paddr,
		   (u32)skb_cb->paddr, vdev_id, tid, skb_cb->htt.freq);
	ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
			msdu->data, msdu->len);
	trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
	trace_ath10k_tx_payload(ar, msdu->data, msdu->len);

	sg_items[0].transfer_id = 0;
	sg_items[0].transfer_context = NULL;
	sg_items[0].vaddr = &skb_cb->htt.txbuf->htc_hdr;
	sg_items[0].paddr = skb_cb->htt.txbuf_paddr +
			    sizeof(skb_cb->htt.txbuf->frags);
	sg_items[0].len = sizeof(skb_cb->htt.txbuf->htc_hdr) +
			  sizeof(skb_cb->htt.txbuf->cmd_hdr) +
			  sizeof(skb_cb->htt.txbuf->cmd_tx);

	sg_items[1].transfer_id = 0;
	sg_items[1].transfer_context = NULL;
	sg_items[1].vaddr = msdu->data;
	sg_items[1].paddr = skb_cb->paddr;
	sg_items[1].len = prefetch_len;

	res = ath10k_hif_tx_sg(htt->ar,
			       htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
			       sg_items, ARRAY_SIZE(sg_items));
	if (res)
		goto err_unmap_msdu;

	return 0;

err_unmap_msdu:
	dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
err_free_txbuf:
	dma_pool_free(htt->tx_pool,
		      skb_cb->htt.txbuf,
		      skb_cb->htt.txbuf_paddr);
err_free_msdu_id:
	spin_lock_bh(&htt->tx_lock);
	ath10k_htt_tx_free_msdu_id(htt, msdu_id);
	spin_unlock_bh(&htt->tx_lock);
err_tx_dec:
	ath10k_htt_tx_dec_pending(htt);
err:
	return res;
}
Commit	Line	Data
5e3dd157 KV	1	/*
	2	* Copyright (c) 2005-2011 Atheros Communications Inc.
	3	* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
	4	*
	5	* Permission to use, copy, modify, and/or distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*/
	17
	18	#include <linux/etherdevice.h>
	19	#include "htt.h"
	20	#include "mac.h"
	21	#include "hif.h"
	22	#include "txrx.h"
	23	#include "debug.h"
	24
	25	void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
	26	{
	27	htt->num_pending_tx--;
	28	if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
	29	ieee80211_wake_queues(htt->ar->hw);
	30	}
	31
	32	static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
	33	{
	34	spin_lock_bh(&htt->tx_lock);
	35	__ath10k_htt_tx_dec_pending(htt);
	36	spin_unlock_bh(&htt->tx_lock);
	37	}
	38
	39	static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
	40	{
	41	int ret = 0;
	42
	43	spin_lock_bh(&htt->tx_lock);
	44
	45	if (htt->num_pending_tx >= htt->max_num_pending_tx) {
	46	ret = -EBUSY;
	47	goto exit;
	48	}
	49
	50	htt->num_pending_tx++;
	51	if (htt->num_pending_tx == htt->max_num_pending_tx)
	52	ieee80211_stop_queues(htt->ar->hw);
	53
	54	exit:
	55	spin_unlock_bh(&htt->tx_lock);
	56	return ret;
	57	}
	58
89d6d835	59	int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt htt, struct sk_buff skb)
5e3dd157	60	{
7aa7a72a	61	struct ath10k *ar = htt->ar;
89d6d835	62	int ret;
5e3dd157 KV	63
	64	lockdep_assert_held(&htt->tx_lock);
	65
89d6d835 MK	66	ret = idr_alloc(&htt->pending_tx, skb, 0, 0x10000, GFP_ATOMIC);
	67
	68	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret);
5e3dd157	69
89d6d835	70	return ret;
5e3dd157 KV	71	}
	72
	73	void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
	74	{
7aa7a72a MK	75	struct ath10k *ar = htt->ar;
7aa7a72a MK	76
5e3dd157 KV	77	lockdep_assert_held(&htt->tx_lock);
5e3dd157 KV	78
7aa7a72a	79	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
89d6d835 MK	80
89d6d835 MK	81	idr_remove(&htt->pending_tx, msdu_id);
5e3dd157 KV	82	}
5e3dd157 KV	83
95bf21f9	84	int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
5e3dd157	85	{
7aa7a72a MK	86	struct ath10k *ar = htt->ar;
7aa7a72a MK	87
7aa7a72a	88	ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
5e3dd157 KV	89	htt->max_num_pending_tx);
5e3dd157 KV	90
89d6d835 MK	91	spin_lock_init(&htt->tx_lock);
89d6d835 MK	92	idr_init(&htt->pending_tx);
5e3dd157	93
a16942e6 MK	94	htt->tx_pool = dma_pool_create("ath10k htt tx pool", htt->ar->dev,
	95	sizeof(struct ath10k_htt_txbuf), 4, 0);
	96	if (!htt->tx_pool) {
89d6d835	97	idr_destroy(&htt->pending_tx);
a16942e6 MK	98	return -ENOMEM;
	99	}
	100
5e3dd157 KV	101	return 0;
	102	}
	103
89d6d835	104	static int ath10k_htt_tx_clean_up_pending(int msdu_id, void skb, void ctx)
5e3dd157	105	{
89d6d835 MK	106	struct ath10k *ar = ctx;
89d6d835 MK	107	struct ath10k_htt *htt = &ar->htt;
0a89f8a0	108	struct htt_tx_done tx_done = {0};
5e3dd157	109
89d6d835	110	ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id);
5e3dd157	111
89d6d835 MK	112	tx_done.discard = 1;
89d6d835 MK	113	tx_done.msdu_id = msdu_id;
5e3dd157	114
89d6d835 MK	115	spin_lock_bh(&htt->tx_lock);
89d6d835 MK	116	ath10k_txrx_tx_unref(htt, &tx_done);
45967089	117	spin_unlock_bh(&htt->tx_lock);
89d6d835 MK	118
89d6d835 MK	119	return 0;
5e3dd157 KV	120	}
5e3dd157 KV	121
95bf21f9	122	void ath10k_htt_tx_free(struct ath10k_htt *htt)
5e3dd157	123	{
89d6d835 MK	124	idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar);
89d6d835 MK	125	idr_destroy(&htt->pending_tx);
a16942e6	126	dma_pool_destroy(htt->tx_pool);
5e3dd157 KV	127	}
	128
	129	void ath10k_htt_htc_tx_complete(struct ath10k ar, struct sk_buff skb)
	130	{
0a89f8a0	131	dev_kfree_skb_any(skb);
5e3dd157 KV	132	}
	133
	134	int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
	135	{
7aa7a72a	136	struct ath10k *ar = htt->ar;
5e3dd157 KV	137	struct sk_buff *skb;
	138	struct htt_cmd *cmd;
	139	int len = 0;
	140	int ret;
	141
	142	len += sizeof(cmd->hdr);
	143	len += sizeof(cmd->ver_req);
	144
7aa7a72a	145	skb = ath10k_htc_alloc_skb(ar, len);
5e3dd157 KV	146	if (!skb)
	147	return -ENOMEM;
	148
	149	skb_put(skb, len);
	150	cmd = (struct htt_cmd *)skb->data;
	151	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
	152
cd003fad	153	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
5e3dd157 KV	154	if (ret) {
	155	dev_kfree_skb_any(skb);
	156	return ret;
	157	}
	158
	159	return 0;
	160	}
	161
a3d135e5 KV	162	int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
a3d135e5 KV	163	{
7aa7a72a	164	struct ath10k *ar = htt->ar;
a3d135e5 KV	165	struct htt_stats_req *req;
	166	struct sk_buff *skb;
	167	struct htt_cmd *cmd;
	168	int len = 0, ret;
	169
	170	len += sizeof(cmd->hdr);
	171	len += sizeof(cmd->stats_req);
	172
7aa7a72a	173	skb = ath10k_htc_alloc_skb(ar, len);
a3d135e5 KV	174	if (!skb)
	175	return -ENOMEM;
	176
	177	skb_put(skb, len);
	178	cmd = (struct htt_cmd *)skb->data;
	179	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
	180
	181	req = &cmd->stats_req;
	182
	183	memset(req, 0, sizeof(*req));
	184
	185	/* currently we support only max 8 bit masks so no need to worry
	186	* about endian support */
	187	req->upload_types[0] = mask;
	188	req->reset_types[0] = mask;
	189	req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
	190	req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
	191	req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
	192
a3d135e5 KV	193	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
a3d135e5 KV	194	if (ret) {
7aa7a72a MK	195	ath10k_warn(ar, "failed to send htt type stats request: %d",
7aa7a72a MK	196	ret);
a3d135e5 KV	197	dev_kfree_skb_any(skb);
	198	return ret;
	199	}
	200
	201	return 0;
	202	}
	203
5e3dd157 KV	204	int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
5e3dd157 KV	205	{
7aa7a72a	206	struct ath10k *ar = htt->ar;
5e3dd157 KV	207	struct sk_buff *skb;
	208	struct htt_cmd *cmd;
	209	struct htt_rx_ring_setup_ring *ring;
	210	const int num_rx_ring = 1;
	211	u16 flags;
	212	u32 fw_idx;
	213	int len;
	214	int ret;
	215
	216	/*
	217	* the HW expects the buffer to be an integral number of 4-byte
	218	* "words"
	219	*/
	220	BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
	221	BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
	222
	223	len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
	224	+ (sizeof(ring) num_rx_ring);
7aa7a72a	225	skb = ath10k_htc_alloc_skb(ar, len);
5e3dd157 KV	226	if (!skb)
	227	return -ENOMEM;
	228
	229	skb_put(skb, len);
	230
	231	cmd = (struct htt_cmd *)skb->data;
	232	ring = &cmd->rx_setup.rings[0];
	233
	234	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
	235	cmd->rx_setup.hdr.num_rings = 1;
	236
	237	/* FIXME: do we need all of this? */
	238	flags = 0;
	239	flags \|= HTT_RX_RING_FLAGS_MAC80211_HDR;
	240	flags \|= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
	241	flags \|= HTT_RX_RING_FLAGS_PPDU_START;
	242	flags \|= HTT_RX_RING_FLAGS_PPDU_END;
	243	flags \|= HTT_RX_RING_FLAGS_MPDU_START;
	244	flags \|= HTT_RX_RING_FLAGS_MPDU_END;
	245	flags \|= HTT_RX_RING_FLAGS_MSDU_START;
	246	flags \|= HTT_RX_RING_FLAGS_MSDU_END;
	247	flags \|= HTT_RX_RING_FLAGS_RX_ATTENTION;
	248	flags \|= HTT_RX_RING_FLAGS_FRAG_INFO;
	249	flags \|= HTT_RX_RING_FLAGS_UNICAST_RX;
	250	flags \|= HTT_RX_RING_FLAGS_MULTICAST_RX;
	251	flags \|= HTT_RX_RING_FLAGS_CTRL_RX;
	252	flags \|= HTT_RX_RING_FLAGS_MGMT_RX;
	253	flags \|= HTT_RX_RING_FLAGS_NULL_RX;
	254	flags \|= HTT_RX_RING_FLAGS_PHY_DATA_RX;
	255
	256	fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
	257
	258	ring->fw_idx_shadow_reg_paddr =
	259	__cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
	260	ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
	261	ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
	262	ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
	263	ring->flags = __cpu_to_le16(flags);
	264	ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
	265
	266	#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
	267
	268	ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
	269	ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
	270	ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
	271	ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
	272	ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
	273	ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
	274	ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
	275	ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
	276	ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
	277	ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
	278
	279	#undef desc_offset
	280
cd003fad	281	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
5e3dd157 KV	282	if (ret) {
	283	dev_kfree_skb_any(skb);
	284	return ret;
	285	}
	286
	287	return 0;
	288	}
	289
d385623a JD	290	int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
	291	u8 max_subfrms_ampdu,
	292	u8 max_subfrms_amsdu)
	293	{
7aa7a72a	294	struct ath10k *ar = htt->ar;
d385623a JD	295	struct htt_aggr_conf *aggr_conf;
	296	struct sk_buff *skb;
	297	struct htt_cmd *cmd;
	298	int len;
	299	int ret;
	300
	301	/* Firmware defaults are: amsdu = 3 and ampdu = 64 */
	302
	303	if (max_subfrms_ampdu == 0 \|\| max_subfrms_ampdu > 64)
	304	return -EINVAL;
	305
	306	if (max_subfrms_amsdu == 0 \|\| max_subfrms_amsdu > 31)
	307	return -EINVAL;
	308
	309	len = sizeof(cmd->hdr);
	310	len += sizeof(cmd->aggr_conf);
	311
7aa7a72a	312	skb = ath10k_htc_alloc_skb(ar, len);
d385623a JD	313	if (!skb)
	314	return -ENOMEM;
	315
	316	skb_put(skb, len);
	317	cmd = (struct htt_cmd *)skb->data;
	318	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
	319
	320	aggr_conf = &cmd->aggr_conf;
	321	aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
	322	aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
	323
7aa7a72a	324	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
d385623a JD	325	aggr_conf->max_num_amsdu_subframes,
	326	aggr_conf->max_num_ampdu_subframes);
	327
	328	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	329	if (ret) {
	330	dev_kfree_skb_any(skb);
	331	return ret;
	332	}
	333
	334	return 0;
	335	}
	336
5e3dd157 KV	337	int ath10k_htt_mgmt_tx(struct ath10k_htt htt, struct sk_buff msdu)
5e3dd157 KV	338	{
7aa7a72a MK	339	struct ath10k *ar = htt->ar;
7aa7a72a MK	340	struct device *dev = ar->dev;
5e3dd157 KV	341	struct sk_buff *txdesc = NULL;
5e3dd157 KV	342	struct htt_cmd *cmd;
1f8bb151	343	struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
5e00d31a	344	u8 vdev_id = skb_cb->vdev_id;
5e3dd157 KV	345	int len = 0;
	346	int msdu_id = -1;
	347	int res;
	348
5e3dd157 KV	349	res = ath10k_htt_tx_inc_pending(htt);
5e3dd157 KV	350	if (res)
2f3773bc	351	goto err;
5e3dd157 KV	352
	353	len += sizeof(cmd->hdr);
	354	len += sizeof(cmd->mgmt_tx);
	355
5e3dd157	356	spin_lock_bh(&htt->tx_lock);
89d6d835	357	res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
2f3773bc	358	if (res < 0) {
5e3dd157	359	spin_unlock_bh(&htt->tx_lock);
2f3773bc	360	goto err_tx_dec;
5e3dd157	361	}
2f3773bc	362	msdu_id = res;
5e3dd157 KV	363	spin_unlock_bh(&htt->tx_lock);
5e3dd157 KV	364
7aa7a72a	365	txdesc = ath10k_htc_alloc_skb(ar, len);
2f3773bc MK	366	if (!txdesc) {
	367	res = -ENOMEM;
	368	goto err_free_msdu_id;
	369	}
	370
767d34fc MK	371	skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
	372	DMA_TO_DEVICE);
	373	res = dma_mapping_error(dev, skb_cb->paddr);
5e3dd157	374	if (res)
2f3773bc	375	goto err_free_txdesc;
5e3dd157 KV	376
	377	skb_put(txdesc, len);
	378	cmd = (struct htt_cmd *)txdesc->data;
	379	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX;
	380	cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
	381	cmd->mgmt_tx.len = __cpu_to_le32(msdu->len);
	382	cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id);
	383	cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id);
	384	memcpy(cmd->mgmt_tx.hdr, msdu->data,
	385	min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
	386
a16942e6	387	skb_cb->htt.txbuf = NULL;
1f8bb151	388
cd003fad	389	res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
5e3dd157	390	if (res)
2f3773bc	391	goto err_unmap_msdu;
5e3dd157 KV	392
	393	return 0;
	394
2f3773bc	395	err_unmap_msdu:
767d34fc	396	dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
2f3773bc MK	397	err_free_txdesc:
	398	dev_kfree_skb_any(txdesc);
	399	err_free_msdu_id:
	400	spin_lock_bh(&htt->tx_lock);
2f3773bc MK	401	ath10k_htt_tx_free_msdu_id(htt, msdu_id);
	402	spin_unlock_bh(&htt->tx_lock);
	403	err_tx_dec:
5e3dd157	404	ath10k_htt_tx_dec_pending(htt);
2f3773bc	405	err:
5e3dd157 KV	406	return res;
	407	}
	408
	409	int ath10k_htt_tx(struct ath10k_htt htt, struct sk_buff msdu)
	410	{
7aa7a72a MK	411	struct ath10k *ar = htt->ar;
7aa7a72a MK	412	struct device *dev = ar->dev;
5e3dd157	413	struct ieee80211_hdr hdr = (struct ieee80211_hdr )msdu->data;
1f8bb151	414	struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
a16942e6 MK	415	struct ath10k_hif_sg_item sg_items[2];
	416	struct htt_data_tx_desc_frag *frags;
	417	u8 vdev_id = skb_cb->vdev_id;
	418	u8 tid = skb_cb->htt.tid;
	419	int prefetch_len;
5e3dd157	420	int res;
a16942e6 MK	421	u8 flags0 = 0;
	422	u16 msdu_id, flags1 = 0;
	423	dma_addr_t paddr;
	424	u32 frags_paddr;
	425	bool use_frags;
5e3dd157 KV	426
	427	res = ath10k_htt_tx_inc_pending(htt);
	428	if (res)
2f3773bc MK	429	goto err;
	430
	431	spin_lock_bh(&htt->tx_lock);
89d6d835	432	res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
2f3773bc MK	433	if (res < 0) {
	434	spin_unlock_bh(&htt->tx_lock);
	435	goto err_tx_dec;
	436	}
	437	msdu_id = res;
2f3773bc	438	spin_unlock_bh(&htt->tx_lock);
5e3dd157 KV	439
	440	prefetch_len = min(htt->prefetch_len, msdu->len);
	441	prefetch_len = roundup(prefetch_len, 4);
	442
961d4c38 MK	443	/* Since HTT 3.0 there is no separate mgmt tx command. However in case
	444	* of mgmt tx using TX_FRM there is not tx fragment list. Instead of tx
	445	* fragment list host driver specifies directly frame pointer. */
2f3773bc MK	446	use_frags = htt->target_version_major < 3 \|\|
	447	!ieee80211_is_mgmt(hdr->frame_control);
	448
a16942e6 MK	449	skb_cb->htt.txbuf = dma_pool_alloc(htt->tx_pool, GFP_ATOMIC,
a16942e6 MK	450	&paddr);
8be3b692 JL	451	if (!skb_cb->htt.txbuf) {
8be3b692 JL	452	res = -ENOMEM;
a16942e6	453	goto err_free_msdu_id;
8be3b692	454	}
a16942e6	455	skb_cb->htt.txbuf_paddr = paddr;
5e3dd157	456
767d34fc MK	457	skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
	458	DMA_TO_DEVICE);
	459	res = dma_mapping_error(dev, skb_cb->paddr);
5e3dd157	460	if (res)
a16942e6	461	goto err_free_txbuf;
5e3dd157	462
a16942e6 MK	463	if (likely(use_frags)) {
a16942e6 MK	464	frags = skb_cb->htt.txbuf->frags;
5e3dd157	465
a16942e6 MK	466	frags[0].paddr = __cpu_to_le32(skb_cb->paddr);
	467	frags[0].len = __cpu_to_le32(msdu->len);
	468	frags[1].paddr = 0;
	469	frags[1].len = 0;
	470
	471	flags0 \|= SM(ATH10K_HW_TXRX_NATIVE_WIFI,
	472	HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
5e3dd157	473
a16942e6 MK	474	frags_paddr = skb_cb->htt.txbuf_paddr;
	475	} else {
	476	flags0 \|= SM(ATH10K_HW_TXRX_MGMT,
	477	HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
5e3dd157	478
a16942e6 MK	479	frags_paddr = skb_cb->paddr;
	480	}
	481
	482	/* Normally all commands go through HTC which manages tx credits for
	483	* each endpoint and notifies when tx is completed.
	484	*
	485	* HTT endpoint is creditless so there's no need to care about HTC
	486	* flags. In that case it is trivial to fill the HTC header here.
	487	*
	488	* MSDU transmission is considered completed upon HTT event. This
	489	* implies no relevant resources can be freed until after the event is
	490	* received. That's why HTC tx completion handler itself is ignored by
	491	* setting NULL to transfer_context for all sg items.
	492	*
	493	* There is simply no point in pushing HTT TX_FRM through HTC tx path
	494	* as it's a waste of resources. By bypassing HTC it is possible to
	495	* avoid extra memory allocations, compress data structures and thus
	496	* improve performance. */
	497
	498	skb_cb->htt.txbuf->htc_hdr.eid = htt->eid;
	499	skb_cb->htt.txbuf->htc_hdr.len = __cpu_to_le16(
	500	sizeof(skb_cb->htt.txbuf->cmd_hdr) +
	501	sizeof(skb_cb->htt.txbuf->cmd_tx) +
	502	prefetch_len);
	503	skb_cb->htt.txbuf->htc_hdr.flags = 0;
5e3dd157	504
5e3dd157 KV	505	if (!ieee80211_has_protected(hdr->frame_control))
5e3dd157 KV	506	flags0 \|= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
961d4c38	507
a16942e6	508	flags0 \|= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
5e3dd157	509
5e3dd157 KV	510	flags1 \|= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
5e3dd157 KV	511	flags1 \|= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
7c199997 MK	512	flags1 \|= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
7c199997 MK	513	flags1 \|= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
5e3dd157	514
708b9bde MK	515	/* Prevent firmware from sending up tx inspection requests. There's
	516	* nothing ath10k can do with frames requested for inspection so force
	517	* it to simply rely a regular tx completion with discard status.
	518	*/
	519	flags1 \|= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
	520
a16942e6 MK	521	skb_cb->htt.txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
	522	skb_cb->htt.txbuf->cmd_tx.flags0 = flags0;
	523	skb_cb->htt.txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
	524	skb_cb->htt.txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
	525	skb_cb->htt.txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
	526	skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
8d6d3624 MK	527	skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le16(HTT_INVALID_PEERID);
8d6d3624 MK	528	skb_cb->htt.txbuf->cmd_tx.freq = __cpu_to_le16(skb_cb->htt.freq);
a16942e6	529
d1e50f47	530	trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
7aa7a72a	531	ath10k_dbg(ar, ATH10K_DBG_HTT,
8d6d3624	532	"htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n",
a16942e6	533	flags0, flags1, msdu->len, msdu_id, frags_paddr,
8d6d3624	534	(u32)skb_cb->paddr, vdev_id, tid, skb_cb->htt.freq);
7aa7a72a	535	ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
a16942e6	536	msdu->data, msdu->len);
5ce8e7fd RM	537	trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
5ce8e7fd RM	538	trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
5e3dd157	539
a16942e6 MK	540	sg_items[0].transfer_id = 0;
	541	sg_items[0].transfer_context = NULL;
	542	sg_items[0].vaddr = &skb_cb->htt.txbuf->htc_hdr;
	543	sg_items[0].paddr = skb_cb->htt.txbuf_paddr +
	544	sizeof(skb_cb->htt.txbuf->frags);
	545	sg_items[0].len = sizeof(skb_cb->htt.txbuf->htc_hdr) +
	546	sizeof(skb_cb->htt.txbuf->cmd_hdr) +
	547	sizeof(skb_cb->htt.txbuf->cmd_tx);
	548
	549	sg_items[1].transfer_id = 0;
	550	sg_items[1].transfer_context = NULL;
	551	sg_items[1].vaddr = msdu->data;
	552	sg_items[1].paddr = skb_cb->paddr;
	553	sg_items[1].len = prefetch_len;
	554
	555	res = ath10k_hif_tx_sg(htt->ar,
	556	htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
	557	sg_items, ARRAY_SIZE(sg_items));
5e3dd157	558	if (res)
1f8bb151	559	goto err_unmap_msdu;
5e3dd157 KV	560
5e3dd157 KV	561	return 0;
2f3773bc	562
2f3773bc	563	err_unmap_msdu:
767d34fc	564	dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
a16942e6 MK	565	err_free_txbuf:
	566	dma_pool_free(htt->tx_pool,
	567	skb_cb->htt.txbuf,
	568	skb_cb->htt.txbuf_paddr);
2f3773bc MK	569	err_free_msdu_id:
2f3773bc MK	570	spin_lock_bh(&htt->tx_lock);
2f3773bc MK	571	ath10k_htt_tx_free_msdu_id(htt, msdu_id);
	572	spin_unlock_bh(&htt->tx_lock);
	573	err_tx_dec:
5e3dd157	574	ath10k_htt_tx_dec_pending(htt);
2f3773bc	575	err:
5e3dd157 KV	576	return res;
5e3dd157 KV	577	}