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ath10k: don't forget to kill fw error tasklet
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / pci.c
CommitLineData
5e3dd157
KV		 1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/pci.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22
23#include "core.h"
24#include "debug.h"
25
26#include "targaddrs.h"
27#include "bmi.h"
28
29#include "hif.h"
30#include "htc.h"
31
32#include "ce.h"
33#include "pci.h"
34
8cc8df90 35static unsigned int ath10k_target_ps;
5e3dd157
KV		 36module_param(ath10k_target_ps, uint, 0644);
37MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
38
5e3dd157
KV		 39#define QCA988X_2_0_DEVICE_ID (0x003c)
40
41static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
5e3dd157
KV		 42 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
43 {0}
44};
45
46static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
47 u32 *data);
48
49static void ath10k_pci_process_ce(struct ath10k *ar);
50static int ath10k_pci_post_rx(struct ath10k *ar);
87263e5b 51static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
5e3dd157 52 int num);
87263e5b 53static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
5e3dd157 54static void ath10k_pci_stop_ce(struct ath10k *ar);
8c5c5368
MK		 55static void ath10k_pci_device_reset(struct ath10k *ar);
56static int ath10k_pci_reset_target(struct ath10k *ar);
32270b61
MK		 57static int ath10k_pci_start_intr(struct ath10k *ar);
58static void ath10k_pci_stop_intr(struct ath10k *ar);
5e3dd157
KV		 59
60static const struct ce_attr host_ce_config_wlan[] = {
48e9c225
KV		 61 /* CE0: host->target HTC control and raw streams */
62 {
63 .flags = CE_ATTR_FLAGS,
64 .src_nentries = 16,
65 .src_sz_max = 256,
66 .dest_nentries = 0,
67 },
68
69 /* CE1: target->host HTT + HTC control */
70 {
71 .flags = CE_ATTR_FLAGS,
72 .src_nentries = 0,
73 .src_sz_max = 512,
74 .dest_nentries = 512,
75 },
76
77 /* CE2: target->host WMI */
78 {
79 .flags = CE_ATTR_FLAGS,
80 .src_nentries = 0,
81 .src_sz_max = 2048,
82 .dest_nentries = 32,
83 },
84
85 /* CE3: host->target WMI */
86 {
87 .flags = CE_ATTR_FLAGS,
88 .src_nentries = 32,
89 .src_sz_max = 2048,
90 .dest_nentries = 0,
91 },
92
93 /* CE4: host->target HTT */
94 {
95 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
96 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
97 .src_sz_max = 256,
98 .dest_nentries = 0,
99 },
100
101 /* CE5: unused */
102 {
103 .flags = CE_ATTR_FLAGS,
104 .src_nentries = 0,
105 .src_sz_max = 0,
106 .dest_nentries = 0,
107 },
108
109 /* CE6: target autonomous hif_memcpy */
110 {
111 .flags = CE_ATTR_FLAGS,
112 .src_nentries = 0,
113 .src_sz_max = 0,
114 .dest_nentries = 0,
115 },
116
117 /* CE7: ce_diag, the Diagnostic Window */
118 {
119 .flags = CE_ATTR_FLAGS,
120 .src_nentries = 2,
121 .src_sz_max = DIAG_TRANSFER_LIMIT,
122 .dest_nentries = 2,
123 },
5e3dd157
KV		 124};
125
126/* Target firmware's Copy Engine configuration. */
127static const struct ce_pipe_config target_ce_config_wlan[] = {
d88effba
KV		 128 /* CE0: host->target HTC control and raw streams */
129 {
130 .pipenum = 0,
131 .pipedir = PIPEDIR_OUT,
132 .nentries = 32,
133 .nbytes_max = 256,
134 .flags = CE_ATTR_FLAGS,
135 .reserved = 0,
136 },
137
138 /* CE1: target->host HTT + HTC control */
139 {
140 .pipenum = 1,
141 .pipedir = PIPEDIR_IN,
142 .nentries = 32,
143 .nbytes_max = 512,
144 .flags = CE_ATTR_FLAGS,
145 .reserved = 0,
146 },
147
148 /* CE2: target->host WMI */
149 {
150 .pipenum = 2,
151 .pipedir = PIPEDIR_IN,
152 .nentries = 32,
153 .nbytes_max = 2048,
154 .flags = CE_ATTR_FLAGS,
155 .reserved = 0,
156 },
157
158 /* CE3: host->target WMI */
159 {
160 .pipenum = 3,
161 .pipedir = PIPEDIR_OUT,
162 .nentries = 32,
163 .nbytes_max = 2048,
164 .flags = CE_ATTR_FLAGS,
165 .reserved = 0,
166 },
167
168 /* CE4: host->target HTT */
169 {
170 .pipenum = 4,
171 .pipedir = PIPEDIR_OUT,
172 .nentries = 256,
173 .nbytes_max = 256,
174 .flags = CE_ATTR_FLAGS,
175 .reserved = 0,
176 },
177
5e3dd157 178 /* NB: 50% of src nentries, since tx has 2 frags */
d88effba
KV		 179
180 /* CE5: unused */
181 {
182 .pipenum = 5,
183 .pipedir = PIPEDIR_OUT,
184 .nentries = 32,
185 .nbytes_max = 2048,
186 .flags = CE_ATTR_FLAGS,
187 .reserved = 0,
188 },
189
190 /* CE6: Reserved for target autonomous hif_memcpy */
191 {
192 .pipenum = 6,
193 .pipedir = PIPEDIR_INOUT,
194 .nentries = 32,
195 .nbytes_max = 4096,
196 .flags = CE_ATTR_FLAGS,
197 .reserved = 0,
198 },
199
5e3dd157
KV		 200 /* CE7 used only by Host */
201};
202
203/*
204 * Diagnostic read/write access is provided for startup/config/debug usage.
205 * Caller must guarantee proper alignment, when applicable, and single user
206 * at any moment.
207 */
208static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
209 int nbytes)
210{
211 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
212 int ret = 0;
213 u32 buf;
214 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
215 unsigned int id;
216 unsigned int flags;
2aa39115 217 struct ath10k_ce_pipe *ce_diag;
5e3dd157
KV		 218 /* Host buffer address in CE space */
219 u32 ce_data;
220 dma_addr_t ce_data_base = 0;
221 void *data_buf = NULL;
222 int i;
223
224 /*
225 * This code cannot handle reads to non-memory space. Redirect to the
226 * register read fn but preserve the multi word read capability of
227 * this fn
228 */
229 if (address < DRAM_BASE_ADDRESS) {
230 if (!IS_ALIGNED(address, 4) ||
231 !IS_ALIGNED((unsigned long)data, 4))
232 return -EIO;
233
234 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
235 ar, address, (u32 *)data)) == 0)) {
236 nbytes -= sizeof(u32);
237 address += sizeof(u32);
238 data += sizeof(u32);
239 }
240 return ret;
241 }
242
243 ce_diag = ar_pci->ce_diag;
244
245 /*
246 * Allocate a temporary bounce buffer to hold caller's data
247 * to be DMA'ed from Target. This guarantees
248 * 1) 4-byte alignment
249 * 2) Buffer in DMA-able space
250 */
251 orig_nbytes = nbytes;
252 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
253 orig_nbytes,
254 &ce_data_base);
255
256 if (!data_buf) {
257 ret = -ENOMEM;
258 goto done;
259 }
260 memset(data_buf, 0, orig_nbytes);
261
262 remaining_bytes = orig_nbytes;
263 ce_data = ce_data_base;
264 while (remaining_bytes) {
265 nbytes = min_t(unsigned int, remaining_bytes,
266 DIAG_TRANSFER_LIMIT);
267
268 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
269 if (ret != 0)
270 goto done;
271
272 /* Request CE to send from Target(!) address to Host buffer */
273 /*
274 * The address supplied by the caller is in the
275 * Target CPU virtual address space.
276 *
277 * In order to use this address with the diagnostic CE,
278 * convert it from Target CPU virtual address space
279 * to CE address space
280 */
281 ath10k_pci_wake(ar);
282 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
283 address);
284 ath10k_pci_sleep(ar);
285
286 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
287 0);
288 if (ret)
289 goto done;
290
291 i = 0;
292 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
293 &completed_nbytes,
294 &id) != 0) {
295 mdelay(1);
296 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
297 ret = -EBUSY;
298 goto done;
299 }
300 }
301
302 if (nbytes != completed_nbytes) {
303 ret = -EIO;
304 goto done;
305 }
306
307 if (buf != (u32) address) {
308 ret = -EIO;
309 goto done;
310 }
311
312 i = 0;
313 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
314 &completed_nbytes,
315 &id, &flags) != 0) {
316 mdelay(1);
317
318 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
319 ret = -EBUSY;
320 goto done;
321 }
322 }
323
324 if (nbytes != completed_nbytes) {
325 ret = -EIO;
326 goto done;
327 }
328
329 if (buf != ce_data) {
330 ret = -EIO;
331 goto done;
332 }
333
334 remaining_bytes -= nbytes;
335 address += nbytes;
336 ce_data += nbytes;
337 }
338
339done:
340 if (ret == 0) {
341 /* Copy data from allocated DMA buf to caller's buf */
342 WARN_ON_ONCE(orig_nbytes & 3);
343 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
344 ((u32 *)data)[i] =
345 __le32_to_cpu(((__le32 *)data_buf)[i]);
346 }
347 } else
348 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n",
349 __func__, address);
350
351 if (data_buf)
352 pci_free_consistent(ar_pci->pdev, orig_nbytes,
353 data_buf, ce_data_base);
354
355 return ret;
356}
357
358/* Read 4-byte aligned data from Target memory or register */
359static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
360 u32 *data)
361{
362 /* Assume range doesn't cross this boundary */
363 if (address >= DRAM_BASE_ADDRESS)
364 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
365
366 ath10k_pci_wake(ar);
367 *data = ath10k_pci_read32(ar, address);
368 ath10k_pci_sleep(ar);
369 return 0;
370}
371
372static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
373 const void *data, int nbytes)
374{
375 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
376 int ret = 0;
377 u32 buf;
378 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
379 unsigned int id;
380 unsigned int flags;
2aa39115 381 struct ath10k_ce_pipe *ce_diag;
5e3dd157
KV		 382 void *data_buf = NULL;
383 u32 ce_data; /* Host buffer address in CE space */
384 dma_addr_t ce_data_base = 0;
385 int i;
386
387 ce_diag = ar_pci->ce_diag;
388
389 /*
390 * Allocate a temporary bounce buffer to hold caller's data
391 * to be DMA'ed to Target. This guarantees
392 * 1) 4-byte alignment
393 * 2) Buffer in DMA-able space
394 */
395 orig_nbytes = nbytes;
396 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
397 orig_nbytes,
398 &ce_data_base);
399 if (!data_buf) {
400 ret = -ENOMEM;
401 goto done;
402 }
403
404 /* Copy caller's data to allocated DMA buf */
405 WARN_ON_ONCE(orig_nbytes & 3);
406 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
407 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
408
409 /*
410 * The address supplied by the caller is in the
411 * Target CPU virtual address space.
412 *
413 * In order to use this address with the diagnostic CE,
414 * convert it from
415 * Target CPU virtual address space
416 * to
417 * CE address space
418 */
419 ath10k_pci_wake(ar);
420 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
421 ath10k_pci_sleep(ar);
422
423 remaining_bytes = orig_nbytes;
424 ce_data = ce_data_base;
425 while (remaining_bytes) {
426 /* FIXME: check cast */
427 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
428
429 /* Set up to receive directly into Target(!) address */
430 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
431 if (ret != 0)
432 goto done;
433
434 /*
435 * Request CE to send caller-supplied data that
436 * was copied to bounce buffer to Target(!) address.
437 */
438 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
439 nbytes, 0, 0);
440 if (ret != 0)
441 goto done;
442
443 i = 0;
444 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
445 &completed_nbytes,
446 &id) != 0) {
447 mdelay(1);
448
449 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
450 ret = -EBUSY;
451 goto done;
452 }
453 }
454
455 if (nbytes != completed_nbytes) {
456 ret = -EIO;
457 goto done;
458 }
459
460 if (buf != ce_data) {
461 ret = -EIO;
462 goto done;
463 }
464
465 i = 0;
466 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
467 &completed_nbytes,
468 &id, &flags) != 0) {
469 mdelay(1);
470
471 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
472 ret = -EBUSY;
473 goto done;
474 }
475 }
476
477 if (nbytes != completed_nbytes) {
478 ret = -EIO;
479 goto done;
480 }
481
482 if (buf != address) {
483 ret = -EIO;
484 goto done;
485 }
486
487 remaining_bytes -= nbytes;
488 address += nbytes;
489 ce_data += nbytes;
490 }
491
492done:
493 if (data_buf) {
494 pci_free_consistent(ar_pci->pdev, orig_nbytes, data_buf,
495 ce_data_base);
496 }
497
498 if (ret != 0)
499 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n", __func__,
500 address);
501
502 return ret;
503}
504
505/* Write 4B data to Target memory or register */
506static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
507 u32 data)
508{
509 /* Assume range doesn't cross this boundary */
510 if (address >= DRAM_BASE_ADDRESS)
511 return ath10k_pci_diag_write_mem(ar, address, &data,
512 sizeof(u32));
513
514 ath10k_pci_wake(ar);
515 ath10k_pci_write32(ar, address, data);
516 ath10k_pci_sleep(ar);
517 return 0;
518}
519
520static bool ath10k_pci_target_is_awake(struct ath10k *ar)
521{
522 void __iomem *mem = ath10k_pci_priv(ar)->mem;
523 u32 val;
524 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
525 RTC_STATE_ADDRESS);
526 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
527}
528
f3782744 529static int ath10k_pci_wait(struct ath10k *ar)
5e3dd157
KV		 530{
531 int n = 100;
532
533 while (n-- && !ath10k_pci_target_is_awake(ar))
534 msleep(10);
535
f3782744 536 if (n < 0) {
5e3dd157 537 ath10k_warn("Unable to wakeup target\n");
f3782744
KV		 538 return -ETIMEDOUT;
539 }
540
541 return 0;
5e3dd157
KV		 542}
543
3aebe54b 544int ath10k_do_pci_wake(struct ath10k *ar)
5e3dd157
KV		 545{
546 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
547 void __iomem *pci_addr = ar_pci->mem;
548 int tot_delay = 0;
549 int curr_delay = 5;
550
551 if (atomic_read(&ar_pci->keep_awake_count) == 0) {
552 /* Force AWAKE */
553 iowrite32(PCIE_SOC_WAKE_V_MASK,
554 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
555 PCIE_SOC_WAKE_ADDRESS);
556 }
557 atomic_inc(&ar_pci->keep_awake_count);
558
559 if (ar_pci->verified_awake)
3aebe54b 560 return 0;
5e3dd157
KV		 561
562 for (;;) {
563 if (ath10k_pci_target_is_awake(ar)) {
564 ar_pci->verified_awake = true;
3aebe54b 565 return 0;
5e3dd157
KV		 566 }
567
568 if (tot_delay > PCIE_WAKE_TIMEOUT) {
3aebe54b
KV		 569 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
570 PCIE_WAKE_TIMEOUT,
5e3dd157 571 atomic_read(&ar_pci->keep_awake_count));
3aebe54b 572 return -ETIMEDOUT;
5e3dd157
KV		 573 }
574
575 udelay(curr_delay);
576 tot_delay += curr_delay;
577
578 if (curr_delay < 50)
579 curr_delay += 5;
580 }
581}
582
583void ath10k_do_pci_sleep(struct ath10k *ar)
584{
585 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
586 void __iomem *pci_addr = ar_pci->mem;
587
588 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
589 /* Allow sleep */
590 ar_pci->verified_awake = false;
591 iowrite32(PCIE_SOC_WAKE_RESET,
592 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
593 PCIE_SOC_WAKE_ADDRESS);
594 }
595}
596
597/*
598 * FIXME: Handle OOM properly.
599 */
600static inline
87263e5b 601struct ath10k_pci_compl *get_free_compl(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 602{
603 struct ath10k_pci_compl *compl = NULL;
604
605 spin_lock_bh(&pipe_info->pipe_lock);
606 if (list_empty(&pipe_info->compl_free)) {
607 ath10k_warn("Completion buffers are full\n");
608 goto exit;
609 }
610 compl = list_first_entry(&pipe_info->compl_free,
611 struct ath10k_pci_compl, list);
612 list_del(&compl->list);
613exit:
614 spin_unlock_bh(&pipe_info->pipe_lock);
615 return compl;
616}
617
618/* Called by lower (CE) layer when a send to Target completes. */
5440ce25 619static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
5e3dd157
KV		 620{
621 struct ath10k *ar = ce_state->ar;
622 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 623 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
5e3dd157 624 struct ath10k_pci_compl *compl;
5440ce25
MK		 625 void *transfer_context;
626 u32 ce_data;
627 unsigned int nbytes;
628 unsigned int transfer_id;
5e3dd157 629
5440ce25
MK		 630 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
631 &ce_data, &nbytes,
632 &transfer_id) == 0) {
5e3dd157
KV		 633 compl = get_free_compl(pipe_info);
634 if (!compl)
635 break;
636
f9d8fece 637 compl->state = ATH10K_PCI_COMPL_SEND;
5e3dd157
KV		 638 compl->ce_state = ce_state;
639 compl->pipe_info = pipe_info;
aa5c1db4 640 compl->skb = transfer_context;
5e3dd157
KV		 641 compl->nbytes = nbytes;
642 compl->transfer_id = transfer_id;
643 compl->flags = 0;
644
645 /*
646 * Add the completion to the processing queue.
647 */
648 spin_lock_bh(&ar_pci->compl_lock);
649 list_add_tail(&compl->list, &ar_pci->compl_process);
650 spin_unlock_bh(&ar_pci->compl_lock);
5440ce25 651 }
5e3dd157
KV		 652
653 ath10k_pci_process_ce(ar);
654}
655
656/* Called by lower (CE) layer when data is received from the Target. */
5440ce25 657static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
5e3dd157
KV		 658{
659 struct ath10k *ar = ce_state->ar;
660 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 661 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
5e3dd157
KV		 662 struct ath10k_pci_compl *compl;
663 struct sk_buff *skb;
5440ce25
MK		 664 void *transfer_context;
665 u32 ce_data;
666 unsigned int nbytes;
667 unsigned int transfer_id;
668 unsigned int flags;
5e3dd157 669
5440ce25
MK		 670 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
671 &ce_data, &nbytes, &transfer_id,
672 &flags) == 0) {
5e3dd157
KV		 673 compl = get_free_compl(pipe_info);
674 if (!compl)
675 break;
676
f9d8fece 677 compl->state = ATH10K_PCI_COMPL_RECV;
5e3dd157
KV		 678 compl->ce_state = ce_state;
679 compl->pipe_info = pipe_info;
aa5c1db4 680 compl->skb = transfer_context;
5e3dd157
KV		 681 compl->nbytes = nbytes;
682 compl->transfer_id = transfer_id;
683 compl->flags = flags;
684
685 skb = transfer_context;
686 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
687 skb->len + skb_tailroom(skb),
688 DMA_FROM_DEVICE);
689 /*
690 * Add the completion to the processing queue.
691 */
692 spin_lock_bh(&ar_pci->compl_lock);
693 list_add_tail(&compl->list, &ar_pci->compl_process);
694 spin_unlock_bh(&ar_pci->compl_lock);
5440ce25 695 }
5e3dd157
KV		 696
697 ath10k_pci_process_ce(ar);
698}
699
700/* Send the first nbytes bytes of the buffer */
701static int ath10k_pci_hif_send_head(struct ath10k *ar, u8 pipe_id,
702 unsigned int transfer_id,
703 unsigned int bytes, struct sk_buff *nbuf)
704{
705 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(nbuf);
706 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 707 struct ath10k_pci_pipe *pipe_info = &(ar_pci->pipe_info[pipe_id]);
2aa39115 708 struct ath10k_ce_pipe *ce_hdl = pipe_info->ce_hdl;
5e3dd157
KV		 709 unsigned int len;
710 u32 flags = 0;
711 int ret;
712
5e3dd157
KV		 713 len = min(bytes, nbuf->len);
714 bytes -= len;
715
716 if (len & 3)
717 ath10k_warn("skb not aligned to 4-byte boundary (%d)\n", len);
718
719 ath10k_dbg(ATH10K_DBG_PCI,
720 "pci send data vaddr %p paddr 0x%llx len %d as %d bytes\n",
721 nbuf->data, (unsigned long long) skb_cb->paddr,
722 nbuf->len, len);
723 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
724 "ath10k tx: data: ",
725 nbuf->data, nbuf->len);
726
2e761b5a
MK		 727 ret = ath10k_ce_send(ce_hdl, nbuf, skb_cb->paddr, len, transfer_id,
728 flags);
5e3dd157
KV		 729 if (ret)
730 ath10k_warn("CE send failed: %p\n", nbuf);
731
732 return ret;
733}
734
735static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
736{
737 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3efcb3b4 738 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
5e3dd157
KV		 739}
740
741static void ath10k_pci_hif_dump_area(struct ath10k *ar)
742{
743 u32 reg_dump_area = 0;
744 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
745 u32 host_addr;
746 int ret;
747 u32 i;
748
749 ath10k_err("firmware crashed!\n");
750 ath10k_err("hardware name %s version 0x%x\n",
751 ar->hw_params.name, ar->target_version);
752 ath10k_err("firmware version: %u.%u.%u.%u\n", ar->fw_version_major,
753 ar->fw_version_minor, ar->fw_version_release,
754 ar->fw_version_build);
755
756 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
757 if (ath10k_pci_diag_read_mem(ar, host_addr,
758 &reg_dump_area, sizeof(u32)) != 0) {
759 ath10k_warn("could not read hi_failure_state\n");
760 return;
761 }
762
763 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
764
765 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
766 &reg_dump_values[0],
767 REG_DUMP_COUNT_QCA988X * sizeof(u32));
768 if (ret != 0) {
769 ath10k_err("could not dump FW Dump Area\n");
770 return;
771 }
772
773 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
774
775 ath10k_err("target Register Dump\n");
776 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
777 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
778 i,
779 reg_dump_values[i],
780 reg_dump_values[i + 1],
781 reg_dump_values[i + 2],
782 reg_dump_values[i + 3]);
affd3217 783
5e90de86 784 queue_work(ar->workqueue, &ar->restart_work);
5e3dd157
KV		 785}
786
787static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
788 int force)
789{
790 if (!force) {
791 int resources;
792 /*
793 * Decide whether to actually poll for completions, or just
794 * wait for a later chance.
795 * If there seem to be plenty of resources left, then just wait
796 * since checking involves reading a CE register, which is a
797 * relatively expensive operation.
798 */
799 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
800
801 /*
802 * If at least 50% of the total resources are still available,
803 * don't bother checking again yet.
804 */
805 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
806 return;
807 }
808 ath10k_ce_per_engine_service(ar, pipe);
809}
810
e799bbff
MK		 811static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
812 struct ath10k_hif_cb *callbacks)
5e3dd157
KV		 813{
814 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
815
816 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
817
818 memcpy(&ar_pci->msg_callbacks_current, callbacks,
819 sizeof(ar_pci->msg_callbacks_current));
820}
821
822static int ath10k_pci_start_ce(struct ath10k *ar)
823{
824 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115 825 struct ath10k_ce_pipe *ce_diag = ar_pci->ce_diag;
5e3dd157 826 const struct ce_attr *attr;
87263e5b 827 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 828 struct ath10k_pci_compl *compl;
829 int i, pipe_num, completions, disable_interrupts;
830
831 spin_lock_init(&ar_pci->compl_lock);
832 INIT_LIST_HEAD(&ar_pci->compl_process);
833
fad6ed78 834 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157
KV		 835 pipe_info = &ar_pci->pipe_info[pipe_num];
836
837 spin_lock_init(&pipe_info->pipe_lock);
838 INIT_LIST_HEAD(&pipe_info->compl_free);
839
840 /* Handle Diagnostic CE specially */
841 if (pipe_info->ce_hdl == ce_diag)
842 continue;
843
844 attr = &host_ce_config_wlan[pipe_num];
845 completions = 0;
846
847 if (attr->src_nentries) {
848 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
849 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
850 ath10k_pci_ce_send_done,
851 disable_interrupts);
852 completions += attr->src_nentries;
5e3dd157
KV		 853 }
854
855 if (attr->dest_nentries) {
856 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
857 ath10k_pci_ce_recv_data);
858 completions += attr->dest_nentries;
859 }
860
861 if (completions == 0)
862 continue;
863
864 for (i = 0; i < completions; i++) {
ffe5daa8 865 compl = kmalloc(sizeof(*compl), GFP_KERNEL);
5e3dd157
KV		 866 if (!compl) {
867 ath10k_warn("No memory for completion state\n");
868 ath10k_pci_stop_ce(ar);
869 return -ENOMEM;
870 }
871
f9d8fece 872 compl->state = ATH10K_PCI_COMPL_FREE;
5e3dd157
KV		 873 list_add_tail(&compl->list, &pipe_info->compl_free);
874 }
875 }
876
877 return 0;
878}
879
880static void ath10k_pci_stop_ce(struct ath10k *ar)
881{
882 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
883 struct ath10k_pci_compl *compl;
884 struct sk_buff *skb;
885 int i;
886
887 ath10k_ce_disable_interrupts(ar);
888
889 /* Cancel the pending tasklet */
890 tasklet_kill(&ar_pci->intr_tq);
103d4f5e 891 tasklet_kill(&ar_pci->msi_fw_err);
5e3dd157
KV		 892
893 for (i = 0; i < CE_COUNT; i++)
894 tasklet_kill(&ar_pci->pipe_info[i].intr);
895
896 /* Mark pending completions as aborted, so that upper layers free up
897 * their associated resources */
898 spin_lock_bh(&ar_pci->compl_lock);
899 list_for_each_entry(compl, &ar_pci->compl_process, list) {
aa5c1db4 900 skb = compl->skb;
5e3dd157
KV		 901 ATH10K_SKB_CB(skb)->is_aborted = true;
902 }
903 spin_unlock_bh(&ar_pci->compl_lock);
904}
905
906static void ath10k_pci_cleanup_ce(struct ath10k *ar)
907{
908 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
909 struct ath10k_pci_compl *compl, *tmp;
87263e5b 910 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 911 struct sk_buff *netbuf;
912 int pipe_num;
913
914 /* Free pending completions. */
915 spin_lock_bh(&ar_pci->compl_lock);
916 if (!list_empty(&ar_pci->compl_process))
917 ath10k_warn("pending completions still present! possible memory leaks.\n");
918
919 list_for_each_entry_safe(compl, tmp, &ar_pci->compl_process, list) {
920 list_del(&compl->list);
aa5c1db4 921 netbuf = compl->skb;
5e3dd157
KV		 922 dev_kfree_skb_any(netbuf);
923 kfree(compl);
924 }
925 spin_unlock_bh(&ar_pci->compl_lock);
926
927 /* Free unused completions for each pipe. */
fad6ed78 928 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157
KV		 929 pipe_info = &ar_pci->pipe_info[pipe_num];
930
931 spin_lock_bh(&pipe_info->pipe_lock);
932 list_for_each_entry_safe(compl, tmp,
933 &pipe_info->compl_free, list) {
934 list_del(&compl->list);
935 kfree(compl);
936 }
937 spin_unlock_bh(&pipe_info->pipe_lock);
938 }
939}
940
941static void ath10k_pci_process_ce(struct ath10k *ar)
942{
943 struct ath10k_pci *ar_pci = ar->hif.priv;
944 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
945 struct ath10k_pci_compl *compl;
946 struct sk_buff *skb;
947 unsigned int nbytes;
948 int ret, send_done = 0;
949
950 /* Upper layers aren't ready to handle tx/rx completions in parallel so
951 * we must serialize all completion processing. */
952
953 spin_lock_bh(&ar_pci->compl_lock);
954 if (ar_pci->compl_processing) {
955 spin_unlock_bh(&ar_pci->compl_lock);
956 return;
957 }
958 ar_pci->compl_processing = true;
959 spin_unlock_bh(&ar_pci->compl_lock);
960
961 for (;;) {
962 spin_lock_bh(&ar_pci->compl_lock);
963 if (list_empty(&ar_pci->compl_process)) {
964 spin_unlock_bh(&ar_pci->compl_lock);
965 break;
966 }
967 compl = list_first_entry(&ar_pci->compl_process,
968 struct ath10k_pci_compl, list);
969 list_del(&compl->list);
970 spin_unlock_bh(&ar_pci->compl_lock);
971
f9d8fece
MK		 972 switch (compl->state) {
973 case ATH10K_PCI_COMPL_SEND:
5e3dd157 974 cb->tx_completion(ar,
aa5c1db4 975 compl->skb,
5e3dd157
KV		 976 compl->transfer_id);
977 send_done = 1;
f9d8fece
MK		 978 break;
979 case ATH10K_PCI_COMPL_RECV:
5e3dd157
KV		 980 ret = ath10k_pci_post_rx_pipe(compl->pipe_info, 1);
981 if (ret) {
982 ath10k_warn("Unable to post recv buffer for pipe: %d\n",
983 compl->pipe_info->pipe_num);
984 break;
985 }
986
aa5c1db4 987 skb = compl->skb;
5e3dd157
KV		 988 nbytes = compl->nbytes;
989
990 ath10k_dbg(ATH10K_DBG_PCI,
991 "ath10k_pci_ce_recv_data netbuf=%p nbytes=%d\n",
992 skb, nbytes);
993 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
994 "ath10k rx: ", skb->data, nbytes);
995
996 if (skb->len + skb_tailroom(skb) >= nbytes) {
997 skb_trim(skb, 0);
998 skb_put(skb, nbytes);
999 cb->rx_completion(ar, skb,
1000 compl->pipe_info->pipe_num);
1001 } else {
1002 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
1003 nbytes,
1004 skb->len + skb_tailroom(skb));
1005 }
f9d8fece
MK		 1006 break;
1007 case ATH10K_PCI_COMPL_FREE:
1008 ath10k_warn("free completion cannot be processed\n");
1009 break;
1010 default:
1011 ath10k_warn("invalid completion state (%d)\n",
1012 compl->state);
1013 break;
5e3dd157
KV		 1014 }
1015
f9d8fece 1016 compl->state = ATH10K_PCI_COMPL_FREE;
5e3dd157
KV		 1017
1018 /*
1019 * Add completion back to the pipe's free list.
1020 */
1021 spin_lock_bh(&compl->pipe_info->pipe_lock);
1022 list_add_tail(&compl->list, &compl->pipe_info->compl_free);
5e3dd157
KV		 1023 spin_unlock_bh(&compl->pipe_info->pipe_lock);
1024 }
1025
1026 spin_lock_bh(&ar_pci->compl_lock);
1027 ar_pci->compl_processing = false;
1028 spin_unlock_bh(&ar_pci->compl_lock);
1029}
1030
1031/* TODO - temporary mapping while we have too few CE's */
1032static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1033 u16 service_id, u8 *ul_pipe,
1034 u8 *dl_pipe, int *ul_is_polled,
1035 int *dl_is_polled)
1036{
1037 int ret = 0;
1038
1039 /* polling for received messages not supported */
1040 *dl_is_polled = 0;
1041
1042 switch (service_id) {
1043 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1044 /*
1045 * Host->target HTT gets its own pipe, so it can be polled
1046 * while other pipes are interrupt driven.
1047 */
1048 *ul_pipe = 4;
1049 /*
1050 * Use the same target->host pipe for HTC ctrl, HTC raw
1051 * streams, and HTT.
1052 */
1053 *dl_pipe = 1;
1054 break;
1055
1056 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1057 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
1058 /*
1059 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
1060 * HTC_CTRL_RSVD_SVC could share the same pipe as the
1061 * WMI services. So, if another CE is needed, change
1062 * this to *ul_pipe = 3, which frees up CE 0.
1063 */
1064 /* *ul_pipe = 3; */
1065 *ul_pipe = 0;
1066 *dl_pipe = 1;
1067 break;
1068
1069 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
1070 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
1071 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
1072 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
1073
1074 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1075 *ul_pipe = 3;
1076 *dl_pipe = 2;
1077 break;
1078
1079 /* pipe 5 unused */
1080 /* pipe 6 reserved */
1081 /* pipe 7 reserved */
1082
1083 default:
1084 ret = -1;
1085 break;
1086 }
1087 *ul_is_polled =
1088 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1089
1090 return ret;
1091}
1092
1093static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1094 u8 *ul_pipe, u8 *dl_pipe)
1095{
1096 int ul_is_polled, dl_is_polled;
1097
1098 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1099 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1100 ul_pipe,
1101 dl_pipe,
1102 &ul_is_polled,
1103 &dl_is_polled);
1104}
1105
87263e5b 1106static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
5e3dd157
KV		 1107 int num)
1108{
1109 struct ath10k *ar = pipe_info->hif_ce_state;
1110 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115 1111 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
5e3dd157
KV		 1112 struct sk_buff *skb;
1113 dma_addr_t ce_data;
1114 int i, ret = 0;
1115
1116 if (pipe_info->buf_sz == 0)
1117 return 0;
1118
1119 for (i = 0; i < num; i++) {
1120 skb = dev_alloc_skb(pipe_info->buf_sz);
1121 if (!skb) {
1122 ath10k_warn("could not allocate skbuff for pipe %d\n",
1123 num);
1124 ret = -ENOMEM;
1125 goto err;
1126 }
1127
1128 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1129
1130 ce_data = dma_map_single(ar->dev, skb->data,
1131 skb->len + skb_tailroom(skb),
1132 DMA_FROM_DEVICE);
1133
1134 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1135 ath10k_warn("could not dma map skbuff\n");
1136 dev_kfree_skb_any(skb);
1137 ret = -EIO;
1138 goto err;
1139 }
1140
1141 ATH10K_SKB_CB(skb)->paddr = ce_data;
1142
1143 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1144 pipe_info->buf_sz,
1145 PCI_DMA_FROMDEVICE);
1146
1147 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1148 ce_data);
1149 if (ret) {
1150 ath10k_warn("could not enqueue to pipe %d (%d)\n",
1151 num, ret);
1152 goto err;
1153 }
1154 }
1155
1156 return ret;
1157
1158err:
1159 ath10k_pci_rx_pipe_cleanup(pipe_info);
1160 return ret;
1161}
1162
1163static int ath10k_pci_post_rx(struct ath10k *ar)
1164{
1165 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1166 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1167 const struct ce_attr *attr;
1168 int pipe_num, ret = 0;
1169
fad6ed78 1170 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157
KV		 1171 pipe_info = &ar_pci->pipe_info[pipe_num];
1172 attr = &host_ce_config_wlan[pipe_num];
1173
1174 if (attr->dest_nentries == 0)
1175 continue;
1176
1177 ret = ath10k_pci_post_rx_pipe(pipe_info,
1178 attr->dest_nentries - 1);
1179 if (ret) {
1180 ath10k_warn("Unable to replenish recv buffers for pipe: %d\n",
1181 pipe_num);
1182
1183 for (; pipe_num >= 0; pipe_num--) {
1184 pipe_info = &ar_pci->pipe_info[pipe_num];
1185 ath10k_pci_rx_pipe_cleanup(pipe_info);
1186 }
1187 return ret;
1188 }
1189 }
1190
1191 return 0;
1192}
1193
1194static int ath10k_pci_hif_start(struct ath10k *ar)
1195{
1196 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1197 int ret;
1198
1199 ret = ath10k_pci_start_ce(ar);
1200 if (ret) {
1201 ath10k_warn("could not start CE (%d)\n", ret);
1202 return ret;
1203 }
1204
1205 /* Post buffers once to start things off. */
1206 ret = ath10k_pci_post_rx(ar);
1207 if (ret) {
1208 ath10k_warn("could not post rx pipes (%d)\n", ret);
1209 return ret;
1210 }
1211
1212 ar_pci->started = 1;
1213 return 0;
1214}
1215
87263e5b 1216static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 1217{
1218 struct ath10k *ar;
1219 struct ath10k_pci *ar_pci;
2aa39115 1220 struct ath10k_ce_pipe *ce_hdl;
5e3dd157
KV		 1221 u32 buf_sz;
1222 struct sk_buff *netbuf;
1223 u32 ce_data;
1224
1225 buf_sz = pipe_info->buf_sz;
1226
1227 /* Unused Copy Engine */
1228 if (buf_sz == 0)
1229 return;
1230
1231 ar = pipe_info->hif_ce_state;
1232 ar_pci = ath10k_pci_priv(ar);
1233
1234 if (!ar_pci->started)
1235 return;
1236
1237 ce_hdl = pipe_info->ce_hdl;
1238
1239 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1240 &ce_data) == 0) {
1241 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1242 netbuf->len + skb_tailroom(netbuf),
1243 DMA_FROM_DEVICE);
1244 dev_kfree_skb_any(netbuf);
1245 }
1246}
1247
87263e5b 1248static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 1249{
1250 struct ath10k *ar;
1251 struct ath10k_pci *ar_pci;
2aa39115 1252 struct ath10k_ce_pipe *ce_hdl;
5e3dd157
KV		 1253 struct sk_buff *netbuf;
1254 u32 ce_data;
1255 unsigned int nbytes;
1256 unsigned int id;
1257 u32 buf_sz;
1258
1259 buf_sz = pipe_info->buf_sz;
1260
1261 /* Unused Copy Engine */
1262 if (buf_sz == 0)
1263 return;
1264
1265 ar = pipe_info->hif_ce_state;
1266 ar_pci = ath10k_pci_priv(ar);
1267
1268 if (!ar_pci->started)
1269 return;
1270
1271 ce_hdl = pipe_info->ce_hdl;
1272
1273 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1274 &ce_data, &nbytes, &id) == 0) {
e9bb0aa3
KV		 1275 /*
1276 * Indicate the completion to higer layer to free
1277 * the buffer
1278 */
1279 ATH10K_SKB_CB(netbuf)->is_aborted = true;
1280 ar_pci->msg_callbacks_current.tx_completion(ar,
1281 netbuf,
1282 id);
5e3dd157
KV		 1283 }
1284}
1285
1286/*
1287 * Cleanup residual buffers for device shutdown:
1288 * buffers that were enqueued for receive
1289 * buffers that were to be sent
1290 * Note: Buffers that had completed but which were
1291 * not yet processed are on a completion queue. They
1292 * are handled when the completion thread shuts down.
1293 */
1294static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1295{
1296 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1297 int pipe_num;
1298
fad6ed78 1299 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
87263e5b 1300 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1301
1302 pipe_info = &ar_pci->pipe_info[pipe_num];
1303 ath10k_pci_rx_pipe_cleanup(pipe_info);
1304 ath10k_pci_tx_pipe_cleanup(pipe_info);
1305 }
1306}
1307
1308static void ath10k_pci_ce_deinit(struct ath10k *ar)
1309{
1310 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1311 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1312 int pipe_num;
1313
fad6ed78 1314 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157
KV		 1315 pipe_info = &ar_pci->pipe_info[pipe_num];
1316 if (pipe_info->ce_hdl) {
1317 ath10k_ce_deinit(pipe_info->ce_hdl);
1318 pipe_info->ce_hdl = NULL;
1319 pipe_info->buf_sz = 0;
1320 }
1321 }
1322}
1323
32270b61
MK		 1324static void ath10k_pci_disable_irqs(struct ath10k *ar)
1325{
1326 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1327 int i;
1328
1329 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1330 disable_irq(ar_pci->pdev->irq + i);
1331}
1332
5e3dd157
KV		 1333static void ath10k_pci_hif_stop(struct ath10k *ar)
1334{
32270b61
MK		 1335 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1336
5e3dd157
KV		 1337 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
1338
32270b61
MK		 1339 /* Irqs are never explicitly re-enabled. They are implicitly re-enabled
1340 * by ath10k_pci_start_intr(). */
1341 ath10k_pci_disable_irqs(ar);
1342
5e3dd157
KV		 1343 ath10k_pci_stop_ce(ar);
1344
1345 /* At this point, asynchronous threads are stopped, the target should
1346 * not DMA nor interrupt. We process the leftovers and then free
1347 * everything else up. */
1348
1349 ath10k_pci_process_ce(ar);
1350 ath10k_pci_cleanup_ce(ar);
1351 ath10k_pci_buffer_cleanup(ar);
32270b61
MK		 1352
1353 ar_pci->started = 0;
5e3dd157
KV		 1354}
1355
1356static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1357 void *req, u32 req_len,
1358 void *resp, u32 *resp_len)
1359{
1360 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115
MK		 1361 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1362 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1363 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1364 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
5e3dd157
KV		 1365 dma_addr_t req_paddr = 0;
1366 dma_addr_t resp_paddr = 0;
1367 struct bmi_xfer xfer = {};
1368 void *treq, *tresp = NULL;
1369 int ret = 0;
1370
1371 if (resp && !resp_len)
1372 return -EINVAL;
1373
1374 if (resp && resp_len && *resp_len == 0)
1375 return -EINVAL;
1376
1377 treq = kmemdup(req, req_len, GFP_KERNEL);
1378 if (!treq)
1379 return -ENOMEM;
1380
1381 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1382 ret = dma_mapping_error(ar->dev, req_paddr);
1383 if (ret)
1384 goto err_dma;
1385
1386 if (resp && resp_len) {
1387 tresp = kzalloc(*resp_len, GFP_KERNEL);
1388 if (!tresp) {
1389 ret = -ENOMEM;
1390 goto err_req;
1391 }
1392
1393 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1394 DMA_FROM_DEVICE);
1395 ret = dma_mapping_error(ar->dev, resp_paddr);
1396 if (ret)
1397 goto err_req;
1398
1399 xfer.wait_for_resp = true;
1400 xfer.resp_len = 0;
1401
1402 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1403 }
1404
1405 init_completion(&xfer.done);
1406
1407 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1408 if (ret)
1409 goto err_resp;
1410
1411 ret = wait_for_completion_timeout(&xfer.done,
1412 BMI_COMMUNICATION_TIMEOUT_HZ);
1413 if (ret <= 0) {
1414 u32 unused_buffer;
1415 unsigned int unused_nbytes;
1416 unsigned int unused_id;
1417
1418 ret = -ETIMEDOUT;
1419 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1420 &unused_nbytes, &unused_id);
1421 } else {
1422 /* non-zero means we did not time out */
1423 ret = 0;
1424 }
1425
1426err_resp:
1427 if (resp) {
1428 u32 unused_buffer;
1429
1430 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1431 dma_unmap_single(ar->dev, resp_paddr,
1432 *resp_len, DMA_FROM_DEVICE);
1433 }
1434err_req:
1435 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1436
1437 if (ret == 0 && resp_len) {
1438 *resp_len = min(*resp_len, xfer.resp_len);
1439 memcpy(resp, tresp, xfer.resp_len);
1440 }
1441err_dma:
1442 kfree(treq);
1443 kfree(tresp);
1444
1445 return ret;
1446}
1447
5440ce25 1448static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
5e3dd157 1449{
5440ce25
MK		 1450 struct bmi_xfer *xfer;
1451 u32 ce_data;
1452 unsigned int nbytes;
1453 unsigned int transfer_id;
1454
1455 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1456 &nbytes, &transfer_id))
1457 return;
5e3dd157
KV		 1458
1459 if (xfer->wait_for_resp)
1460 return;
1461
1462 complete(&xfer->done);
1463}
1464
5440ce25 1465static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
5e3dd157 1466{
5440ce25
MK		 1467 struct bmi_xfer *xfer;
1468 u32 ce_data;
1469 unsigned int nbytes;
1470 unsigned int transfer_id;
1471 unsigned int flags;
1472
1473 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1474 &nbytes, &transfer_id, &flags))
1475 return;
5e3dd157
KV		 1476
1477 if (!xfer->wait_for_resp) {
1478 ath10k_warn("unexpected: BMI data received; ignoring\n");
1479 return;
1480 }
1481
1482 xfer->resp_len = nbytes;
1483 complete(&xfer->done);
1484}
1485
1486/*
1487 * Map from service/endpoint to Copy Engine.
1488 * This table is derived from the CE_PCI TABLE, above.
1489 * It is passed to the Target at startup for use by firmware.
1490 */
1491static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1492 {
1493 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1494 PIPEDIR_OUT, /* out = UL = host -> target */
1495 3,
1496 },
1497 {
1498 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1499 PIPEDIR_IN, /* in = DL = target -> host */
1500 2,
1501 },
1502 {
1503 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1504 PIPEDIR_OUT, /* out = UL = host -> target */
1505 3,
1506 },
1507 {
1508 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1509 PIPEDIR_IN, /* in = DL = target -> host */
1510 2,
1511 },
1512 {
1513 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1514 PIPEDIR_OUT, /* out = UL = host -> target */
1515 3,
1516 },
1517 {
1518 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1519 PIPEDIR_IN, /* in = DL = target -> host */
1520 2,
1521 },
1522 {
1523 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1524 PIPEDIR_OUT, /* out = UL = host -> target */
1525 3,
1526 },
1527 {
1528 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1529 PIPEDIR_IN, /* in = DL = target -> host */
1530 2,
1531 },
1532 {
1533 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1534 PIPEDIR_OUT, /* out = UL = host -> target */
1535 3,
1536 },
1537 {
1538 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1539 PIPEDIR_IN, /* in = DL = target -> host */
1540 2,
1541 },
1542 {
1543 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1544 PIPEDIR_OUT, /* out = UL = host -> target */
1545 0, /* could be moved to 3 (share with WMI) */
1546 },
1547 {
1548 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1549 PIPEDIR_IN, /* in = DL = target -> host */
1550 1,
1551 },
1552 {
1553 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1554 PIPEDIR_OUT, /* out = UL = host -> target */
1555 0,
1556 },
1557 {
1558 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1559 PIPEDIR_IN, /* in = DL = target -> host */
1560 1,
1561 },
1562 {
1563 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1564 PIPEDIR_OUT, /* out = UL = host -> target */
1565 4,
1566 },
1567 {
1568 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1569 PIPEDIR_IN, /* in = DL = target -> host */
1570 1,
1571 },
1572
1573 /* (Additions here) */
1574
1575 { /* Must be last */
1576 0,
1577 0,
1578 0,
1579 },
1580};
1581
1582/*
1583 * Send an interrupt to the device to wake up the Target CPU
1584 * so it has an opportunity to notice any changed state.
1585 */
1586static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1587{
1588 int ret;
1589 u32 core_ctrl;
1590
1591 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1592 CORE_CTRL_ADDRESS,
1593 &core_ctrl);
1594 if (ret) {
1595 ath10k_warn("Unable to read core ctrl\n");
1596 return ret;
1597 }
1598
1599 /* A_INUM_FIRMWARE interrupt to Target CPU */
1600 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1601
1602 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1603 CORE_CTRL_ADDRESS,
1604 core_ctrl);
1605 if (ret)
1606 ath10k_warn("Unable to set interrupt mask\n");
1607
1608 return ret;
1609}
1610
1611static int ath10k_pci_init_config(struct ath10k *ar)
1612{
1613 u32 interconnect_targ_addr;
1614 u32 pcie_state_targ_addr = 0;
1615 u32 pipe_cfg_targ_addr = 0;
1616 u32 svc_to_pipe_map = 0;
1617 u32 pcie_config_flags = 0;
1618 u32 ealloc_value;
1619 u32 ealloc_targ_addr;
1620 u32 flag2_value;
1621 u32 flag2_targ_addr;
1622 int ret = 0;
1623
1624 /* Download to Target the CE Config and the service-to-CE map */
1625 interconnect_targ_addr =
1626 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1627
1628 /* Supply Target-side CE configuration */
1629 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1630 &pcie_state_targ_addr);
1631 if (ret != 0) {
1632 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1633 return ret;
1634 }
1635
1636 if (pcie_state_targ_addr == 0) {
1637 ret = -EIO;
1638 ath10k_err("Invalid pcie state addr\n");
1639 return ret;
1640 }
1641
1642 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1643 offsetof(struct pcie_state,
1644 pipe_cfg_addr),
1645 &pipe_cfg_targ_addr);
1646 if (ret != 0) {
1647 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1648 return ret;
1649 }
1650
1651 if (pipe_cfg_targ_addr == 0) {
1652 ret = -EIO;
1653 ath10k_err("Invalid pipe cfg addr\n");
1654 return ret;
1655 }
1656
1657 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1658 target_ce_config_wlan,
1659 sizeof(target_ce_config_wlan));
1660
1661 if (ret != 0) {
1662 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1663 return ret;
1664 }
1665
1666 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1667 offsetof(struct pcie_state,
1668 svc_to_pipe_map),
1669 &svc_to_pipe_map);
1670 if (ret != 0) {
1671 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1672 return ret;
1673 }
1674
1675 if (svc_to_pipe_map == 0) {
1676 ret = -EIO;
1677 ath10k_err("Invalid svc_to_pipe map\n");
1678 return ret;
1679 }
1680
1681 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1682 target_service_to_ce_map_wlan,
1683 sizeof(target_service_to_ce_map_wlan));
1684 if (ret != 0) {
1685 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1686 return ret;
1687 }
1688
1689 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1690 offsetof(struct pcie_state,
1691 config_flags),
1692 &pcie_config_flags);
1693 if (ret != 0) {
1694 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1695 return ret;
1696 }
1697
1698 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1699
1700 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1701 offsetof(struct pcie_state, config_flags),
1702 &pcie_config_flags,
1703 sizeof(pcie_config_flags));
1704 if (ret != 0) {
1705 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1706 return ret;
1707 }
1708
1709 /* configure early allocation */
1710 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1711
1712 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1713 if (ret != 0) {
1714 ath10k_err("Faile to get early alloc val: %d\n", ret);
1715 return ret;
1716 }
1717
1718 /* first bank is switched to IRAM */
1719 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1720 HI_EARLY_ALLOC_MAGIC_MASK);
1721 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1722 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1723
1724 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1725 if (ret != 0) {
1726 ath10k_err("Failed to set early alloc val: %d\n", ret);
1727 return ret;
1728 }
1729
1730 /* Tell Target to proceed with initialization */
1731 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1732
1733 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1734 if (ret != 0) {
1735 ath10k_err("Failed to get option val: %d\n", ret);
1736 return ret;
1737 }
1738
1739 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1740
1741 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1742 if (ret != 0) {
1743 ath10k_err("Failed to set option val: %d\n", ret);
1744 return ret;
1745 }
1746
1747 return 0;
1748}
1749
1750
1751
1752static int ath10k_pci_ce_init(struct ath10k *ar)
1753{
1754 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1755 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1756 const struct ce_attr *attr;
1757 int pipe_num;
1758
fad6ed78 1759 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157
KV		 1760 pipe_info = &ar_pci->pipe_info[pipe_num];
1761 pipe_info->pipe_num = pipe_num;
1762 pipe_info->hif_ce_state = ar;
1763 attr = &host_ce_config_wlan[pipe_num];
1764
1765 pipe_info->ce_hdl = ath10k_ce_init(ar, pipe_num, attr);
1766 if (pipe_info->ce_hdl == NULL) {
1767 ath10k_err("Unable to initialize CE for pipe: %d\n",
1768 pipe_num);
1769
1770 /* It is safe to call it here. It checks if ce_hdl is
1771 * valid for each pipe */
1772 ath10k_pci_ce_deinit(ar);
1773 return -1;
1774 }
1775
fad6ed78 1776 if (pipe_num == CE_COUNT - 1) {
5e3dd157
KV		 1777 /*
1778 * Reserve the ultimate CE for
1779 * diagnostic Window support
1780 */
fad6ed78 1781 ar_pci->ce_diag = pipe_info->ce_hdl;
5e3dd157
KV		 1782 continue;
1783 }
1784
1785 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1786 }
1787
1788 /*
1789 * Initially, establish CE completion handlers for use with BMI.
1790 * These are overwritten with generic handlers after we exit BMI phase.
1791 */
1792 pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1793 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
1794 ath10k_pci_bmi_send_done, 0);
1795
1796 pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1797 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
1798 ath10k_pci_bmi_recv_data);
1799
1800 return 0;
1801}
1802
1803static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1804{
1805 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1806 u32 fw_indicator_address, fw_indicator;
1807
1808 ath10k_pci_wake(ar);
1809
1810 fw_indicator_address = ar_pci->fw_indicator_address;
1811 fw_indicator = ath10k_pci_read32(ar, fw_indicator_address);
1812
1813 if (fw_indicator & FW_IND_EVENT_PENDING) {
1814 /* ACK: clear Target-side pending event */
1815 ath10k_pci_write32(ar, fw_indicator_address,
1816 fw_indicator & ~FW_IND_EVENT_PENDING);
1817
1818 if (ar_pci->started) {
1819 ath10k_pci_hif_dump_area(ar);
1820 } else {
1821 /*
1822 * Probable Target failure before we're prepared
1823 * to handle it. Generally unexpected.
1824 */
1825 ath10k_warn("early firmware event indicated\n");
1826 }
1827 }
1828
1829 ath10k_pci_sleep(ar);
1830}
1831
8c5c5368
MK		 1832static int ath10k_pci_hif_power_up(struct ath10k *ar)
1833{
8cc8df90 1834 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
8c5c5368
MK		 1835 int ret;
1836
32270b61
MK		 1837 ret = ath10k_pci_start_intr(ar);
1838 if (ret) {
1839 ath10k_err("could not start interrupt handling (%d)\n", ret);
1840 goto err;
1841 }
1842
8c5c5368
MK		 1843 /*
1844 * Bring the target up cleanly.
1845 *
1846 * The target may be in an undefined state with an AUX-powered Target
1847 * and a Host in WoW mode. If the Host crashes, loses power, or is
1848 * restarted (without unloading the driver) then the Target is left
1849 * (aux) powered and running. On a subsequent driver load, the Target
1850 * is in an unexpected state. We try to catch that here in order to
1851 * reset the Target and retry the probe.
1852 */
1853 ath10k_pci_device_reset(ar);
1854
1855 ret = ath10k_pci_reset_target(ar);
1856 if (ret)
32270b61 1857 goto err_irq;
8c5c5368 1858
8cc8df90 1859 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368 1860 /* Force AWAKE forever */
8c5c5368 1861 ath10k_do_pci_wake(ar);
8c5c5368
MK		 1862
1863 ret = ath10k_pci_ce_init(ar);
1864 if (ret)
1865 goto err_ps;
1866
1867 ret = ath10k_pci_init_config(ar);
1868 if (ret)
1869 goto err_ce;
1870
1871 ret = ath10k_pci_wake_target_cpu(ar);
1872 if (ret) {
1873 ath10k_err("could not wake up target CPU (%d)\n", ret);
1874 goto err_ce;
1875 }
1876
1877 return 0;
1878
1879err_ce:
1880 ath10k_pci_ce_deinit(ar);
1881err_ps:
8cc8df90 1882 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368 1883 ath10k_do_pci_sleep(ar);
32270b61
MK		 1884err_irq:
1885 ath10k_pci_stop_intr(ar);
8c5c5368
MK		 1886err:
1887 return ret;
1888}
1889
1890static void ath10k_pci_hif_power_down(struct ath10k *ar)
1891{
8cc8df90
BM		 1892 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1893
32270b61 1894 ath10k_pci_stop_intr(ar);
8cc8df90 1895
8c5c5368 1896 ath10k_pci_ce_deinit(ar);
8cc8df90 1897 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368
MK		 1898 ath10k_do_pci_sleep(ar);
1899}
1900
8cd13cad
MK		 1901#ifdef CONFIG_PM
1902
1903#define ATH10K_PCI_PM_CONTROL 0x44
1904
1905static int ath10k_pci_hif_suspend(struct ath10k *ar)
1906{
1907 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1908 struct pci_dev *pdev = ar_pci->pdev;
1909 u32 val;
1910
1911 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1912
1913 if ((val & 0x000000ff) != 0x3) {
1914 pci_save_state(pdev);
1915 pci_disable_device(pdev);
1916 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1917 (val & 0xffffff00) | 0x03);
1918 }
1919
1920 return 0;
1921}
1922
1923static int ath10k_pci_hif_resume(struct ath10k *ar)
1924{
1925 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1926 struct pci_dev *pdev = ar_pci->pdev;
1927 u32 val;
1928
1929 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1930
1931 if ((val & 0x000000ff) != 0) {
1932 pci_restore_state(pdev);
1933 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1934 val & 0xffffff00);
1935 /*
1936 * Suspend/Resume resets the PCI configuration space,
1937 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1938 * to keep PCI Tx retries from interfering with C3 CPU state
1939 */
1940 pci_read_config_dword(pdev, 0x40, &val);
1941
1942 if ((val & 0x0000ff00) != 0)
1943 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1944 }
1945
1946 return 0;
1947}
1948#endif
1949
5e3dd157
KV		 1950static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
1951 .send_head = ath10k_pci_hif_send_head,
1952 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
1953 .start = ath10k_pci_hif_start,
1954 .stop = ath10k_pci_hif_stop,
1955 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
1956 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
1957 .send_complete_check = ath10k_pci_hif_send_complete_check,
e799bbff 1958 .set_callbacks = ath10k_pci_hif_set_callbacks,
5e3dd157 1959 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
8c5c5368
MK		 1960 .power_up = ath10k_pci_hif_power_up,
1961 .power_down = ath10k_pci_hif_power_down,
8cd13cad
MK		 1962#ifdef CONFIG_PM
1963 .suspend = ath10k_pci_hif_suspend,
1964 .resume = ath10k_pci_hif_resume,
1965#endif
5e3dd157
KV		 1966};
1967
1968static void ath10k_pci_ce_tasklet(unsigned long ptr)
1969{
87263e5b 1970 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
5e3dd157
KV		 1971 struct ath10k_pci *ar_pci = pipe->ar_pci;
1972
1973 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
1974}
1975
1976static void ath10k_msi_err_tasklet(unsigned long data)
1977{
1978 struct ath10k *ar = (struct ath10k *)data;
1979
1980 ath10k_pci_fw_interrupt_handler(ar);
1981}
1982
1983/*
1984 * Handler for a per-engine interrupt on a PARTICULAR CE.
1985 * This is used in cases where each CE has a private MSI interrupt.
1986 */
1987static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
1988{
1989 struct ath10k *ar = arg;
1990 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1991 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
1992
e5742672 1993 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
5e3dd157
KV		 1994 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
1995 return IRQ_HANDLED;
1996 }
1997
1998 /*
1999 * NOTE: We are able to derive ce_id from irq because we
2000 * use a one-to-one mapping for CE's 0..5.
2001 * CE's 6 & 7 do not use interrupts at all.
2002 *
2003 * This mapping must be kept in sync with the mapping
2004 * used by firmware.
2005 */
2006 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2007 return IRQ_HANDLED;
2008}
2009
2010static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2011{
2012 struct ath10k *ar = arg;
2013 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2014
2015 tasklet_schedule(&ar_pci->msi_fw_err);
2016 return IRQ_HANDLED;
2017}
2018
2019/*
2020 * Top-level interrupt handler for all PCI interrupts from a Target.
2021 * When a block of MSI interrupts is allocated, this top-level handler
2022 * is not used; instead, we directly call the correct sub-handler.
2023 */
2024static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2025{
2026 struct ath10k *ar = arg;
2027 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2028
2029 if (ar_pci->num_msi_intrs == 0) {
2030 /*
2031 * IMPORTANT: INTR_CLR regiser has to be set after
2032 * INTR_ENABLE is set to 0, otherwise interrupt can not be
2033 * really cleared.
2034 */
2035 iowrite32(0, ar_pci->mem +
2036 (SOC_CORE_BASE_ADDRESS |
2037 PCIE_INTR_ENABLE_ADDRESS));
2038 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2039 PCIE_INTR_CE_MASK_ALL,
2040 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2041 PCIE_INTR_CLR_ADDRESS));
2042 /*
2043 * IMPORTANT: this extra read transaction is required to
2044 * flush the posted write buffer.
2045 */
2046 (void) ioread32(ar_pci->mem +
2047 (SOC_CORE_BASE_ADDRESS |
2048 PCIE_INTR_ENABLE_ADDRESS));
2049 }
2050
2051 tasklet_schedule(&ar_pci->intr_tq);
2052
2053 return IRQ_HANDLED;
2054}
2055
2056static void ath10k_pci_tasklet(unsigned long data)
2057{
2058 struct ath10k *ar = (struct ath10k *)data;
2059 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2060
2061 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2062 ath10k_ce_per_engine_service_any(ar);
2063
2064 if (ar_pci->num_msi_intrs == 0) {
2065 /* Enable Legacy PCI line interrupts */
2066 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2067 PCIE_INTR_CE_MASK_ALL,
2068 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2069 PCIE_INTR_ENABLE_ADDRESS));
2070 /*
2071 * IMPORTANT: this extra read transaction is required to
2072 * flush the posted write buffer
2073 */
2074 (void) ioread32(ar_pci->mem +
2075 (SOC_CORE_BASE_ADDRESS |
2076 PCIE_INTR_ENABLE_ADDRESS));
2077 }
2078}
2079
2080static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
2081{
2082 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2083 int ret;
2084 int i;
2085
2086 ret = pci_enable_msi_block(ar_pci->pdev, num);
2087 if (ret)
2088 return ret;
2089
2090 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2091 ath10k_pci_msi_fw_handler,
2092 IRQF_SHARED, "ath10k_pci", ar);
591ecdb8
MK		 2093 if (ret) {
2094 ath10k_warn("request_irq(%d) failed %d\n",
2095 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2096
2097 pci_disable_msi(ar_pci->pdev);
5e3dd157 2098 return ret;
591ecdb8 2099 }
5e3dd157
KV		 2100
2101 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2102 ret = request_irq(ar_pci->pdev->irq + i,
2103 ath10k_pci_per_engine_handler,
2104 IRQF_SHARED, "ath10k_pci", ar);
2105 if (ret) {
2106 ath10k_warn("request_irq(%d) failed %d\n",
2107 ar_pci->pdev->irq + i, ret);
2108
87b1423b
MK		 2109 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2110 free_irq(ar_pci->pdev->irq + i, ar);
5e3dd157 2111
87b1423b 2112 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
5e3dd157
KV		 2113 pci_disable_msi(ar_pci->pdev);
2114 return ret;
2115 }
2116 }
2117
2118 ath10k_info("MSI-X interrupt handling (%d intrs)\n", num);
2119 return 0;
2120}
2121
2122static int ath10k_pci_start_intr_msi(struct ath10k *ar)
2123{
2124 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2125 int ret;
2126
2127 ret = pci_enable_msi(ar_pci->pdev);
2128 if (ret < 0)
2129 return ret;
2130
2131 ret = request_irq(ar_pci->pdev->irq,
2132 ath10k_pci_interrupt_handler,
2133 IRQF_SHARED, "ath10k_pci", ar);
2134 if (ret < 0) {
2135 pci_disable_msi(ar_pci->pdev);
2136 return ret;
2137 }
2138
2139 ath10k_info("MSI interrupt handling\n");
2140 return 0;
2141}
2142
2143static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
2144{
2145 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2146 int ret;
2147
2148 ret = request_irq(ar_pci->pdev->irq,
2149 ath10k_pci_interrupt_handler,
2150 IRQF_SHARED, "ath10k_pci", ar);
2151 if (ret < 0)
2152 return ret;
2153
2154 /*
2155 * Make sure to wake the Target before enabling Legacy
2156 * Interrupt.
2157 */
2158 iowrite32(PCIE_SOC_WAKE_V_MASK,
2159 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2160 PCIE_SOC_WAKE_ADDRESS);
2161
f3782744
KV		 2162 ret = ath10k_pci_wait(ar);
2163 if (ret) {
2164 ath10k_warn("Failed to enable legacy interrupt, target did not wake up: %d\n",
2165 ret);
2166 free_irq(ar_pci->pdev->irq, ar);
2167 return ret;
2168 }
5e3dd157
KV		 2169
2170 /*
2171 * A potential race occurs here: The CORE_BASE write
2172 * depends on target correctly decoding AXI address but
2173 * host won't know when target writes BAR to CORE_CTRL.
2174 * This write might get lost if target has NOT written BAR.
2175 * For now, fix the race by repeating the write in below
2176 * synchronization checking.
2177 */
2178 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2179 PCIE_INTR_CE_MASK_ALL,
2180 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2181 PCIE_INTR_ENABLE_ADDRESS));
2182 iowrite32(PCIE_SOC_WAKE_RESET,
2183 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2184 PCIE_SOC_WAKE_ADDRESS);
2185
2186 ath10k_info("legacy interrupt handling\n");
2187 return 0;
2188}
2189
2190static int ath10k_pci_start_intr(struct ath10k *ar)
2191{
2192 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2193 int num = MSI_NUM_REQUEST;
2194 int ret;
2195 int i;
2196
2197 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
2198 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2199 (unsigned long) ar);
2200
2201 for (i = 0; i < CE_COUNT; i++) {
2202 ar_pci->pipe_info[i].ar_pci = ar_pci;
2203 tasklet_init(&ar_pci->pipe_info[i].intr,
2204 ath10k_pci_ce_tasklet,
2205 (unsigned long)&ar_pci->pipe_info[i]);
2206 }
2207
2208 if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
2209 num = 1;
2210
2211 if (num > 1) {
2212 ret = ath10k_pci_start_intr_msix(ar, num);
2213 if (ret == 0)
2214 goto exit;
2215
2216 ath10k_warn("MSI-X didn't succeed (%d), trying MSI\n", ret);
2217 num = 1;
2218 }
2219
2220 if (num == 1) {
2221 ret = ath10k_pci_start_intr_msi(ar);
2222 if (ret == 0)
2223 goto exit;
2224
2225 ath10k_warn("MSI didn't succeed (%d), trying legacy INTR\n",
2226 ret);
2227 num = 0;
2228 }
2229
2230 ret = ath10k_pci_start_intr_legacy(ar);
f3782744
KV		 2231 if (ret) {
2232 ath10k_warn("Failed to start legacy interrupts: %d\n", ret);
2233 return ret;
2234 }
5e3dd157
KV		 2235
2236exit:
2237 ar_pci->num_msi_intrs = num;
5e3dd157
KV		 2238 return ret;
2239}
2240
2241static void ath10k_pci_stop_intr(struct ath10k *ar)
2242{
2243 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2244 int i;
2245
2246 /* There's at least one interrupt irregardless whether its legacy INTR
2247 * or MSI or MSI-X */
2248 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2249 free_irq(ar_pci->pdev->irq + i, ar);
2250
2251 if (ar_pci->num_msi_intrs > 0)
2252 pci_disable_msi(ar_pci->pdev);
2253}
2254
2255static int ath10k_pci_reset_target(struct ath10k *ar)
2256{
2257 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2258 int wait_limit = 300; /* 3 sec */
f3782744 2259 int ret;
5e3dd157
KV		 2260
2261 /* Wait for Target to finish initialization before we proceed. */
2262 iowrite32(PCIE_SOC_WAKE_V_MASK,
2263 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2264 PCIE_SOC_WAKE_ADDRESS);
2265
f3782744
KV		 2266 ret = ath10k_pci_wait(ar);
2267 if (ret) {
2268 ath10k_warn("Failed to reset target, target did not wake up: %d\n",
2269 ret);
2270 return ret;
2271 }
5e3dd157
KV		 2272
2273 while (wait_limit-- &&
2274 !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
2275 FW_IND_INITIALIZED)) {
2276 if (ar_pci->num_msi_intrs == 0)
2277 /* Fix potential race by repeating CORE_BASE writes */
2278 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2279 PCIE_INTR_CE_MASK_ALL,
2280 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2281 PCIE_INTR_ENABLE_ADDRESS));
2282 mdelay(10);
2283 }
2284
2285 if (wait_limit < 0) {
2286 ath10k_err("Target stalled\n");
2287 iowrite32(PCIE_SOC_WAKE_RESET,
2288 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2289 PCIE_SOC_WAKE_ADDRESS);
2290 return -EIO;
2291 }
2292
2293 iowrite32(PCIE_SOC_WAKE_RESET,
2294 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2295 PCIE_SOC_WAKE_ADDRESS);
2296
2297 return 0;
2298}
2299
7a5fe3f8 2300static void ath10k_pci_device_reset(struct ath10k *ar)
5e3dd157 2301{
5e3dd157
KV		 2302 int i;
2303 u32 val;
2304
2305 if (!SOC_GLOBAL_RESET_ADDRESS)
2306 return;
2307
e479ed43 2308 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
5e3dd157
KV		 2309 PCIE_SOC_WAKE_V_MASK);
2310 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2311 if (ath10k_pci_target_is_awake(ar))
2312 break;
2313 msleep(1);
2314 }
2315
2316 /* Put Target, including PCIe, into RESET. */
e479ed43 2317 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
5e3dd157 2318 val |= 1;
e479ed43 2319 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
5e3dd157
KV		 2320
2321 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
e479ed43 2322 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
5e3dd157
KV		 2323 RTC_STATE_COLD_RESET_MASK)
2324 break;
2325 msleep(1);
2326 }
2327
2328 /* Pull Target, including PCIe, out of RESET. */
2329 val &= ~1;
e479ed43 2330 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
5e3dd157
KV		 2331
2332 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
e479ed43 2333 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
5e3dd157
KV		 2334 RTC_STATE_COLD_RESET_MASK))
2335 break;
2336 msleep(1);
2337 }
2338
e479ed43 2339 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
5e3dd157
KV		 2340}
2341
2342static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2343{
2344 int i;
2345
2346 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2347 if (!test_bit(i, ar_pci->features))
2348 continue;
2349
2350 switch (i) {
2351 case ATH10K_PCI_FEATURE_MSI_X:
24cfade1 2352 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
5e3dd157 2353 break;
8cc8df90 2354 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
24cfade1 2355 ath10k_dbg(ATH10K_DBG_BOOT, "QCA98XX SoC power save enabled\n");
8cc8df90 2356 break;
5e3dd157
KV		 2357 }
2358 }
2359}
2360
2361static int ath10k_pci_probe(struct pci_dev *pdev,
2362 const struct pci_device_id *pci_dev)
2363{
2364 void __iomem *mem;
2365 int ret = 0;
2366 struct ath10k *ar;
2367 struct ath10k_pci *ar_pci;
e01ae68c 2368 u32 lcr_val, chip_id;
5e3dd157
KV		 2369
2370 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2371
2372 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2373 if (ar_pci == NULL)
2374 return -ENOMEM;
2375
2376 ar_pci->pdev = pdev;
2377 ar_pci->dev = &pdev->dev;
2378
2379 switch (pci_dev->device) {
5e3dd157
KV		 2380 case QCA988X_2_0_DEVICE_ID:
2381 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2382 break;
2383 default:
2384 ret = -ENODEV;
2385 ath10k_err("Unkown device ID: %d\n", pci_dev->device);
2386 goto err_ar_pci;
2387 }
2388
8cc8df90
BM		 2389 if (ath10k_target_ps)
2390 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2391
5e3dd157
KV		 2392 ath10k_pci_dump_features(ar_pci);
2393
3a0861ff 2394 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
5e3dd157
KV		 2395 if (!ar) {
2396 ath10k_err("ath10k_core_create failed!\n");
2397 ret = -EINVAL;
2398 goto err_ar_pci;
2399 }
2400
5e3dd157
KV		 2401 ar_pci->ar = ar;
2402 ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS;
2403 atomic_set(&ar_pci->keep_awake_count, 0);
2404
2405 pci_set_drvdata(pdev, ar);
2406
2407 /*
2408 * Without any knowledge of the Host, the Target may have been reset or
2409 * power cycled and its Config Space may no longer reflect the PCI
2410 * address space that was assigned earlier by the PCI infrastructure.
2411 * Refresh it now.
2412 */
2413 ret = pci_assign_resource(pdev, BAR_NUM);
2414 if (ret) {
2415 ath10k_err("cannot assign PCI space: %d\n", ret);
2416 goto err_ar;
2417 }
2418
2419 ret = pci_enable_device(pdev);
2420 if (ret) {
2421 ath10k_err("cannot enable PCI device: %d\n", ret);
2422 goto err_ar;
2423 }
2424
2425 /* Request MMIO resources */
2426 ret = pci_request_region(pdev, BAR_NUM, "ath");
2427 if (ret) {
2428 ath10k_err("PCI MMIO reservation error: %d\n", ret);
2429 goto err_device;
2430 }
2431
2432 /*
2433 * Target structures have a limit of 32 bit DMA pointers.
2434 * DMA pointers can be wider than 32 bits by default on some systems.
2435 */
2436 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2437 if (ret) {
2438 ath10k_err("32-bit DMA not available: %d\n", ret);
2439 goto err_region;
2440 }
2441
2442 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2443 if (ret) {
2444 ath10k_err("cannot enable 32-bit consistent DMA\n");
2445 goto err_region;
2446 }
2447
2448 /* Set bus master bit in PCI_COMMAND to enable DMA */
2449 pci_set_master(pdev);
2450
2451 /*
2452 * Temporary FIX: disable ASPM
2453 * Will be removed after the OTP is programmed
2454 */
2455 pci_read_config_dword(pdev, 0x80, &lcr_val);
2456 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2457
2458 /* Arrange for access to Target SoC registers. */
2459 mem = pci_iomap(pdev, BAR_NUM, 0);
2460 if (!mem) {
2461 ath10k_err("PCI iomap error\n");
2462 ret = -EIO;
2463 goto err_master;
2464 }
2465
2466 ar_pci->mem = mem;
2467
2468 spin_lock_init(&ar_pci->ce_lock);
2469
e01ae68c
KV		 2470 ret = ath10k_do_pci_wake(ar);
2471 if (ret) {
2472 ath10k_err("Failed to get chip id: %d\n", ret);
12eb0879 2473 goto err_iomap;
e01ae68c
KV		 2474 }
2475
233eb97f 2476 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
e01ae68c
KV		 2477
2478 ath10k_do_pci_sleep(ar);
2479
24cfade1
KV		 2480 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2481
e01ae68c 2482 ret = ath10k_core_register(ar, chip_id);
5e3dd157
KV		 2483 if (ret) {
2484 ath10k_err("could not register driver core (%d)\n", ret);
32270b61 2485 goto err_iomap;
5e3dd157
KV		 2486 }
2487
2488 return 0;
2489
5e3dd157
KV		 2490err_iomap:
2491 pci_iounmap(pdev, mem);
2492err_master:
2493 pci_clear_master(pdev);
2494err_region:
2495 pci_release_region(pdev, BAR_NUM);
2496err_device:
2497 pci_disable_device(pdev);
2498err_ar:
5e3dd157
KV		 2499 ath10k_core_destroy(ar);
2500err_ar_pci:
2501 /* call HIF PCI free here */
2502 kfree(ar_pci);
2503
2504 return ret;
2505}
2506
2507static void ath10k_pci_remove(struct pci_dev *pdev)
2508{
2509 struct ath10k *ar = pci_get_drvdata(pdev);
2510 struct ath10k_pci *ar_pci;
2511
2512 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2513
2514 if (!ar)
2515 return;
2516
2517 ar_pci = ath10k_pci_priv(ar);
2518
2519 if (!ar_pci)
2520 return;
2521
2522 tasklet_kill(&ar_pci->msi_fw_err);
2523
2524 ath10k_core_unregister(ar);
5e3dd157 2525
5e3dd157
KV		 2526 pci_iounmap(pdev, ar_pci->mem);
2527 pci_release_region(pdev, BAR_NUM);
2528 pci_clear_master(pdev);
2529 pci_disable_device(pdev);
2530
2531 ath10k_core_destroy(ar);
2532 kfree(ar_pci);
2533}
2534
5e3dd157
KV		 2535MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2536
2537static struct pci_driver ath10k_pci_driver = {
2538 .name = "ath10k_pci",
2539 .id_table = ath10k_pci_id_table,
2540 .probe = ath10k_pci_probe,
2541 .remove = ath10k_pci_remove,
5e3dd157
KV		 2542};
2543
2544static int __init ath10k_pci_init(void)
2545{
2546 int ret;
2547
2548 ret = pci_register_driver(&ath10k_pci_driver);
2549 if (ret)
2550 ath10k_err("pci_register_driver failed [%d]\n", ret);
2551
2552 return ret;
2553}
2554module_init(ath10k_pci_init);
2555
2556static void __exit ath10k_pci_exit(void)
2557{
2558 pci_unregister_driver(&ath10k_pci_driver);
2559}
2560
2561module_exit(ath10k_pci_exit);
2562
2563MODULE_AUTHOR("Qualcomm Atheros");
2564MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2565MODULE_LICENSE("Dual BSD/GPL");
5e3dd157
KV		 2566MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
2567MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_OTP_FILE);
2568MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
Linux kernel - Deliverables
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