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ath10k: retry warm reset a few times
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / pci.c
CommitLineData
5e3dd157
KV		 1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/pci.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
650b91fb 22#include <linux/bitops.h>
5e3dd157
KV		 23
24#include "core.h"
25#include "debug.h"
26
27#include "targaddrs.h"
28#include "bmi.h"
29
30#include "hif.h"
31#include "htc.h"
32
33#include "ce.h"
34#include "pci.h"
35
cfe9c45b
MK		 36enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
40};
41
35098463
KV		 42enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
45};
46
e42c1fbd 47static unsigned int ath10k_pci_target_ps;
cfe9c45b 48static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
35098463 49static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
cfe9c45b 50
e42c1fbd
KV		 51module_param_named(target_ps, ath10k_pci_target_ps, uint, 0644);
52MODULE_PARM_DESC(target_ps, "Enable ath10k Target (SoC) PS option");
5e3dd157 53
cfe9c45b
MK		 54module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
55MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
56
35098463
KV		 57module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
58MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
59
0399eca8
KV		 60/* how long wait to wait for target to initialise, in ms */
61#define ATH10K_PCI_TARGET_WAIT 3000
61c95cea 62#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
0399eca8 63
5e3dd157
KV		 64#define QCA988X_2_0_DEVICE_ID (0x003c)
65
66static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
5e3dd157
KV		 67 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
68 {0}
69};
70
71static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
72 u32 *data);
73
5e3dd157 74static int ath10k_pci_post_rx(struct ath10k *ar);
87263e5b 75static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
5e3dd157 76 int num);
87263e5b 77static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
fc36e3ff
MK		 78static int ath10k_pci_cold_reset(struct ath10k *ar);
79static int ath10k_pci_warm_reset(struct ath10k *ar);
d7fb47f5 80static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
fc15ca13
MK		 81static int ath10k_pci_init_irq(struct ath10k *ar);
82static int ath10k_pci_deinit_irq(struct ath10k *ar);
83static int ath10k_pci_request_irq(struct ath10k *ar);
84static void ath10k_pci_free_irq(struct ath10k *ar);
85622cde
MK		 85static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
86 struct ath10k_ce_pipe *rx_pipe,
87 struct bmi_xfer *xfer);
5e3dd157
KV		 88
89static const struct ce_attr host_ce_config_wlan[] = {
48e9c225
KV		 90 /* CE0: host->target HTC control and raw streams */
91 {
92 .flags = CE_ATTR_FLAGS,
93 .src_nentries = 16,
94 .src_sz_max = 256,
95 .dest_nentries = 0,
96 },
97
98 /* CE1: target->host HTT + HTC control */
99 {
100 .flags = CE_ATTR_FLAGS,
101 .src_nentries = 0,
102 .src_sz_max = 512,
103 .dest_nentries = 512,
104 },
105
106 /* CE2: target->host WMI */
107 {
108 .flags = CE_ATTR_FLAGS,
109 .src_nentries = 0,
110 .src_sz_max = 2048,
111 .dest_nentries = 32,
112 },
113
114 /* CE3: host->target WMI */
115 {
116 .flags = CE_ATTR_FLAGS,
117 .src_nentries = 32,
118 .src_sz_max = 2048,
119 .dest_nentries = 0,
120 },
121
122 /* CE4: host->target HTT */
123 {
124 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
125 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
126 .src_sz_max = 256,
127 .dest_nentries = 0,
128 },
129
130 /* CE5: unused */
131 {
132 .flags = CE_ATTR_FLAGS,
133 .src_nentries = 0,
134 .src_sz_max = 0,
135 .dest_nentries = 0,
136 },
137
138 /* CE6: target autonomous hif_memcpy */
139 {
140 .flags = CE_ATTR_FLAGS,
141 .src_nentries = 0,
142 .src_sz_max = 0,
143 .dest_nentries = 0,
144 },
145
146 /* CE7: ce_diag, the Diagnostic Window */
147 {
148 .flags = CE_ATTR_FLAGS,
149 .src_nentries = 2,
150 .src_sz_max = DIAG_TRANSFER_LIMIT,
151 .dest_nentries = 2,
152 },
5e3dd157
KV		 153};
154
155/* Target firmware's Copy Engine configuration. */
156static const struct ce_pipe_config target_ce_config_wlan[] = {
d88effba
KV		 157 /* CE0: host->target HTC control and raw streams */
158 {
159 .pipenum = 0,
160 .pipedir = PIPEDIR_OUT,
161 .nentries = 32,
162 .nbytes_max = 256,
163 .flags = CE_ATTR_FLAGS,
164 .reserved = 0,
165 },
166
167 /* CE1: target->host HTT + HTC control */
168 {
169 .pipenum = 1,
170 .pipedir = PIPEDIR_IN,
171 .nentries = 32,
172 .nbytes_max = 512,
173 .flags = CE_ATTR_FLAGS,
174 .reserved = 0,
175 },
176
177 /* CE2: target->host WMI */
178 {
179 .pipenum = 2,
180 .pipedir = PIPEDIR_IN,
181 .nentries = 32,
182 .nbytes_max = 2048,
183 .flags = CE_ATTR_FLAGS,
184 .reserved = 0,
185 },
186
187 /* CE3: host->target WMI */
188 {
189 .pipenum = 3,
190 .pipedir = PIPEDIR_OUT,
191 .nentries = 32,
192 .nbytes_max = 2048,
193 .flags = CE_ATTR_FLAGS,
194 .reserved = 0,
195 },
196
197 /* CE4: host->target HTT */
198 {
199 .pipenum = 4,
200 .pipedir = PIPEDIR_OUT,
201 .nentries = 256,
202 .nbytes_max = 256,
203 .flags = CE_ATTR_FLAGS,
204 .reserved = 0,
205 },
206
5e3dd157 207 /* NB: 50% of src nentries, since tx has 2 frags */
d88effba
KV		 208
209 /* CE5: unused */
210 {
211 .pipenum = 5,
212 .pipedir = PIPEDIR_OUT,
213 .nentries = 32,
214 .nbytes_max = 2048,
215 .flags = CE_ATTR_FLAGS,
216 .reserved = 0,
217 },
218
219 /* CE6: Reserved for target autonomous hif_memcpy */
220 {
221 .pipenum = 6,
222 .pipedir = PIPEDIR_INOUT,
223 .nentries = 32,
224 .nbytes_max = 4096,
225 .flags = CE_ATTR_FLAGS,
226 .reserved = 0,
227 },
228
5e3dd157
KV		 229 /* CE7 used only by Host */
230};
231
e539887b
MK		 232static bool ath10k_pci_irq_pending(struct ath10k *ar)
233{
234 u32 cause;
235
236 /* Check if the shared legacy irq is for us */
237 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
238 PCIE_INTR_CAUSE_ADDRESS);
239 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
240 return true;
241
242 return false;
243}
244
2685218b
MK		 245static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
246{
247 /* IMPORTANT: INTR_CLR register has to be set after
248 * INTR_ENABLE is set to 0, otherwise interrupt can not be
249 * really cleared. */
250 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
251 0);
252 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
253 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
254
255 /* IMPORTANT: this extra read transaction is required to
256 * flush the posted write buffer. */
257 (void) ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
258 PCIE_INTR_ENABLE_ADDRESS);
259}
260
261static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
262{
263 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
264 PCIE_INTR_ENABLE_ADDRESS,
265 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
266
267 /* IMPORTANT: this extra read transaction is required to
268 * flush the posted write buffer. */
269 (void) ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
270 PCIE_INTR_ENABLE_ADDRESS);
271}
272
ab977bd0
MK		 273static irqreturn_t ath10k_pci_early_irq_handler(int irq, void *arg)
274{
275 struct ath10k *ar = arg;
276 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
277
278 if (ar_pci->num_msi_intrs == 0) {
279 if (!ath10k_pci_irq_pending(ar))
280 return IRQ_NONE;
281
282 ath10k_pci_disable_and_clear_legacy_irq(ar);
283 }
284
285 tasklet_schedule(&ar_pci->early_irq_tasklet);
286
287 return IRQ_HANDLED;
288}
289
290static int ath10k_pci_request_early_irq(struct ath10k *ar)
291{
292 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
293 int ret;
294
295 /* Regardless whether MSI-X/MSI/legacy irqs have been set up the first
296 * interrupt from irq vector is triggered in all cases for FW
297 * indication/errors */
298 ret = request_irq(ar_pci->pdev->irq, ath10k_pci_early_irq_handler,
299 IRQF_SHARED, "ath10k_pci (early)", ar);
300 if (ret) {
301 ath10k_warn("failed to request early irq: %d\n", ret);
302 return ret;
303 }
304
305 return 0;
306}
307
308static void ath10k_pci_free_early_irq(struct ath10k *ar)
309{
310 free_irq(ath10k_pci_priv(ar)->pdev->irq, ar);
311}
312
5e3dd157
KV		 313/*
314 * Diagnostic read/write access is provided for startup/config/debug usage.
315 * Caller must guarantee proper alignment, when applicable, and single user
316 * at any moment.
317 */
318static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
319 int nbytes)
320{
321 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
322 int ret = 0;
323 u32 buf;
324 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
325 unsigned int id;
326 unsigned int flags;
2aa39115 327 struct ath10k_ce_pipe *ce_diag;
5e3dd157
KV		 328 /* Host buffer address in CE space */
329 u32 ce_data;
330 dma_addr_t ce_data_base = 0;
331 void *data_buf = NULL;
332 int i;
333
334 /*
335 * This code cannot handle reads to non-memory space. Redirect to the
336 * register read fn but preserve the multi word read capability of
337 * this fn
338 */
339 if (address < DRAM_BASE_ADDRESS) {
340 if (!IS_ALIGNED(address, 4) ||
341 !IS_ALIGNED((unsigned long)data, 4))
342 return -EIO;
343
344 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
345 ar, address, (u32 *)data)) == 0)) {
346 nbytes -= sizeof(u32);
347 address += sizeof(u32);
348 data += sizeof(u32);
349 }
350 return ret;
351 }
352
353 ce_diag = ar_pci->ce_diag;
354
355 /*
356 * Allocate a temporary bounce buffer to hold caller's data
357 * to be DMA'ed from Target. This guarantees
358 * 1) 4-byte alignment
359 * 2) Buffer in DMA-able space
360 */
361 orig_nbytes = nbytes;
68c03249
MK		 362 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
363 orig_nbytes,
364 &ce_data_base,
365 GFP_ATOMIC);
5e3dd157
KV		 366
367 if (!data_buf) {
368 ret = -ENOMEM;
369 goto done;
370 }
371 memset(data_buf, 0, orig_nbytes);
372
373 remaining_bytes = orig_nbytes;
374 ce_data = ce_data_base;
375 while (remaining_bytes) {
376 nbytes = min_t(unsigned int, remaining_bytes,
377 DIAG_TRANSFER_LIMIT);
378
379 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
380 if (ret != 0)
381 goto done;
382
383 /* Request CE to send from Target(!) address to Host buffer */
384 /*
385 * The address supplied by the caller is in the
386 * Target CPU virtual address space.
387 *
388 * In order to use this address with the diagnostic CE,
389 * convert it from Target CPU virtual address space
390 * to CE address space
391 */
392 ath10k_pci_wake(ar);
393 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
394 address);
395 ath10k_pci_sleep(ar);
396
397 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
398 0);
399 if (ret)
400 goto done;
401
402 i = 0;
403 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
404 &completed_nbytes,
405 &id) != 0) {
406 mdelay(1);
407 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
408 ret = -EBUSY;
409 goto done;
410 }
411 }
412
413 if (nbytes != completed_nbytes) {
414 ret = -EIO;
415 goto done;
416 }
417
418 if (buf != (u32) address) {
419 ret = -EIO;
420 goto done;
421 }
422
423 i = 0;
424 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
425 &completed_nbytes,
426 &id, &flags) != 0) {
427 mdelay(1);
428
429 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
430 ret = -EBUSY;
431 goto done;
432 }
433 }
434
435 if (nbytes != completed_nbytes) {
436 ret = -EIO;
437 goto done;
438 }
439
440 if (buf != ce_data) {
441 ret = -EIO;
442 goto done;
443 }
444
445 remaining_bytes -= nbytes;
446 address += nbytes;
447 ce_data += nbytes;
448 }
449
450done:
451 if (ret == 0) {
452 /* Copy data from allocated DMA buf to caller's buf */
453 WARN_ON_ONCE(orig_nbytes & 3);
454 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
455 ((u32 *)data)[i] =
456 __le32_to_cpu(((__le32 *)data_buf)[i]);
457 }
458 } else
50f87a67
KV		 459 ath10k_warn("failed to read diag value at 0x%x: %d\n",
460 address, ret);
5e3dd157
KV		 461
462 if (data_buf)
68c03249
MK		 463 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
464 ce_data_base);
5e3dd157
KV		 465
466 return ret;
467}
468
469/* Read 4-byte aligned data from Target memory or register */
470static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
471 u32 *data)
472{
473 /* Assume range doesn't cross this boundary */
474 if (address >= DRAM_BASE_ADDRESS)
475 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
476
477 ath10k_pci_wake(ar);
478 *data = ath10k_pci_read32(ar, address);
479 ath10k_pci_sleep(ar);
480 return 0;
481}
482
483static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
484 const void *data, int nbytes)
485{
486 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
487 int ret = 0;
488 u32 buf;
489 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
490 unsigned int id;
491 unsigned int flags;
2aa39115 492 struct ath10k_ce_pipe *ce_diag;
5e3dd157
KV		 493 void *data_buf = NULL;
494 u32 ce_data; /* Host buffer address in CE space */
495 dma_addr_t ce_data_base = 0;
496 int i;
497
498 ce_diag = ar_pci->ce_diag;
499
500 /*
501 * Allocate a temporary bounce buffer to hold caller's data
502 * to be DMA'ed to Target. This guarantees
503 * 1) 4-byte alignment
504 * 2) Buffer in DMA-able space
505 */
506 orig_nbytes = nbytes;
68c03249
MK		 507 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
508 orig_nbytes,
509 &ce_data_base,
510 GFP_ATOMIC);
5e3dd157
KV		 511 if (!data_buf) {
512 ret = -ENOMEM;
513 goto done;
514 }
515
516 /* Copy caller's data to allocated DMA buf */
517 WARN_ON_ONCE(orig_nbytes & 3);
518 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
519 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
520
521 /*
522 * The address supplied by the caller is in the
523 * Target CPU virtual address space.
524 *
525 * In order to use this address with the diagnostic CE,
526 * convert it from
527 * Target CPU virtual address space
528 * to
529 * CE address space
530 */
531 ath10k_pci_wake(ar);
532 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
533 ath10k_pci_sleep(ar);
534
535 remaining_bytes = orig_nbytes;
536 ce_data = ce_data_base;
537 while (remaining_bytes) {
538 /* FIXME: check cast */
539 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
540
541 /* Set up to receive directly into Target(!) address */
542 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
543 if (ret != 0)
544 goto done;
545
546 /*
547 * Request CE to send caller-supplied data that
548 * was copied to bounce buffer to Target(!) address.
549 */
550 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
551 nbytes, 0, 0);
552 if (ret != 0)
553 goto done;
554
555 i = 0;
556 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
557 &completed_nbytes,
558 &id) != 0) {
559 mdelay(1);
560
561 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
562 ret = -EBUSY;
563 goto done;
564 }
565 }
566
567 if (nbytes != completed_nbytes) {
568 ret = -EIO;
569 goto done;
570 }
571
572 if (buf != ce_data) {
573 ret = -EIO;
574 goto done;
575 }
576
577 i = 0;
578 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
579 &completed_nbytes,
580 &id, &flags) != 0) {
581 mdelay(1);
582
583 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
584 ret = -EBUSY;
585 goto done;
586 }
587 }
588
589 if (nbytes != completed_nbytes) {
590 ret = -EIO;
591 goto done;
592 }
593
594 if (buf != address) {
595 ret = -EIO;
596 goto done;
597 }
598
599 remaining_bytes -= nbytes;
600 address += nbytes;
601 ce_data += nbytes;
602 }
603
604done:
605 if (data_buf) {
68c03249
MK		 606 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
607 ce_data_base);
5e3dd157
KV		 608 }
609
610 if (ret != 0)
50f87a67
KV		 611 ath10k_warn("failed to write diag value at 0x%x: %d\n",
612 address, ret);
5e3dd157
KV		 613
614 return ret;
615}
616
617/* Write 4B data to Target memory or register */
618static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
619 u32 data)
620{
621 /* Assume range doesn't cross this boundary */
622 if (address >= DRAM_BASE_ADDRESS)
623 return ath10k_pci_diag_write_mem(ar, address, &data,
624 sizeof(u32));
625
626 ath10k_pci_wake(ar);
627 ath10k_pci_write32(ar, address, data);
628 ath10k_pci_sleep(ar);
629 return 0;
630}
631
632static bool ath10k_pci_target_is_awake(struct ath10k *ar)
633{
634 void __iomem *mem = ath10k_pci_priv(ar)->mem;
635 u32 val;
636 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
637 RTC_STATE_ADDRESS);
638 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
639}
640
3aebe54b 641int ath10k_do_pci_wake(struct ath10k *ar)
5e3dd157
KV		 642{
643 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
644 void __iomem *pci_addr = ar_pci->mem;
645 int tot_delay = 0;
646 int curr_delay = 5;
647
648 if (atomic_read(&ar_pci->keep_awake_count) == 0) {
649 /* Force AWAKE */
650 iowrite32(PCIE_SOC_WAKE_V_MASK,
651 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
652 PCIE_SOC_WAKE_ADDRESS);
653 }
654 atomic_inc(&ar_pci->keep_awake_count);
655
656 if (ar_pci->verified_awake)
3aebe54b 657 return 0;
5e3dd157
KV		 658
659 for (;;) {
660 if (ath10k_pci_target_is_awake(ar)) {
661 ar_pci->verified_awake = true;
3aebe54b 662 return 0;
5e3dd157
KV		 663 }
664
665 if (tot_delay > PCIE_WAKE_TIMEOUT) {
3aebe54b
KV		 666 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
667 PCIE_WAKE_TIMEOUT,
5e3dd157 668 atomic_read(&ar_pci->keep_awake_count));
3aebe54b 669 return -ETIMEDOUT;
5e3dd157
KV		 670 }
671
672 udelay(curr_delay);
673 tot_delay += curr_delay;
674
675 if (curr_delay < 50)
676 curr_delay += 5;
677 }
678}
679
680void ath10k_do_pci_sleep(struct ath10k *ar)
681{
682 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
683 void __iomem *pci_addr = ar_pci->mem;
684
685 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
686 /* Allow sleep */
687 ar_pci->verified_awake = false;
688 iowrite32(PCIE_SOC_WAKE_RESET,
689 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
690 PCIE_SOC_WAKE_ADDRESS);
691 }
692}
693
5e3dd157 694/* Called by lower (CE) layer when a send to Target completes. */
5440ce25 695static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
5e3dd157
KV		 696{
697 struct ath10k *ar = ce_state->ar;
698 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2f5280da 699 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
5440ce25
MK		 700 void *transfer_context;
701 u32 ce_data;
702 unsigned int nbytes;
703 unsigned int transfer_id;
5e3dd157 704
5440ce25
MK		 705 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
706 &ce_data, &nbytes,
707 &transfer_id) == 0) {
a16942e6 708 /* no need to call tx completion for NULL pointers */
726346fc
MK		 709 if (transfer_context == NULL)
710 continue;
711
2f5280da 712 cb->tx_completion(ar, transfer_context, transfer_id);
5440ce25 713 }
5e3dd157
KV		 714}
715
716/* Called by lower (CE) layer when data is received from the Target. */
5440ce25 717static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
5e3dd157
KV		 718{
719 struct ath10k *ar = ce_state->ar;
720 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 721 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
2f5280da 722 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
5e3dd157 723 struct sk_buff *skb;
5440ce25
MK		 724 void *transfer_context;
725 u32 ce_data;
2f5280da 726 unsigned int nbytes, max_nbytes;
5440ce25
MK		 727 unsigned int transfer_id;
728 unsigned int flags;
2f5280da 729 int err;
5e3dd157 730
5440ce25
MK		 731 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
732 &ce_data, &nbytes, &transfer_id,
733 &flags) == 0) {
2f5280da
MK		 734 err = ath10k_pci_post_rx_pipe(pipe_info, 1);
735 if (unlikely(err)) {
736 /* FIXME: retry */
737 ath10k_warn("failed to replenish CE rx ring %d: %d\n",
738 pipe_info->pipe_num, err);
739 }
5e3dd157
KV		 740
741 skb = transfer_context;
2f5280da 742 max_nbytes = skb->len + skb_tailroom(skb);
5e3dd157 743 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
2f5280da
MK		 744 max_nbytes, DMA_FROM_DEVICE);
745
746 if (unlikely(max_nbytes < nbytes)) {
747 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
748 nbytes, max_nbytes);
749 dev_kfree_skb_any(skb);
750 continue;
751 }
5e3dd157 752
2f5280da
MK		 753 skb_put(skb, nbytes);
754 cb->rx_completion(ar, skb, pipe_info->pipe_num);
755 }
5e3dd157
KV		 756}
757
726346fc
MK		 758static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
759 struct ath10k_hif_sg_item *items, int n_items)
5e3dd157 760{
5e3dd157 761 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
726346fc
MK		 762 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
763 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
764 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
765 unsigned int nentries_mask = src_ring->nentries_mask;
766 unsigned int sw_index = src_ring->sw_index;
767 unsigned int write_index = src_ring->write_index;
768 int err, i;
5e3dd157 769
726346fc 770 spin_lock_bh(&ar_pci->ce_lock);
5e3dd157 771
726346fc
MK		 772 if (unlikely(CE_RING_DELTA(nentries_mask,
773 write_index, sw_index - 1) < n_items)) {
774 err = -ENOBUFS;
775 goto unlock;
776 }
5e3dd157 777
726346fc
MK		 778 for (i = 0; i < n_items - 1; i++) {
779 ath10k_dbg(ATH10K_DBG_PCI,
780 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
781 i, items[i].paddr, items[i].len, n_items);
782 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ",
783 items[i].vaddr, items[i].len);
5e3dd157 784
726346fc
MK		 785 err = ath10k_ce_send_nolock(ce_pipe,
786 items[i].transfer_context,
787 items[i].paddr,
788 items[i].len,
789 items[i].transfer_id,
790 CE_SEND_FLAG_GATHER);
791 if (err)
792 goto unlock;
793 }
794
795 /* `i` is equal to `n_items -1` after for() */
796
797 ath10k_dbg(ATH10K_DBG_PCI,
798 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
799 i, items[i].paddr, items[i].len, n_items);
800 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ",
801 items[i].vaddr, items[i].len);
802
803 err = ath10k_ce_send_nolock(ce_pipe,
804 items[i].transfer_context,
805 items[i].paddr,
806 items[i].len,
807 items[i].transfer_id,
808 0);
809 if (err)
810 goto unlock;
811
812 err = 0;
813unlock:
814 spin_unlock_bh(&ar_pci->ce_lock);
815 return err;
5e3dd157
KV		 816}
817
818static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
819{
820 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
50f87a67
KV		 821
822 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get free queue number\n");
823
3efcb3b4 824 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
5e3dd157
KV		 825}
826
827static void ath10k_pci_hif_dump_area(struct ath10k *ar)
828{
829 u32 reg_dump_area = 0;
830 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
831 u32 host_addr;
832 int ret;
833 u32 i;
834
835 ath10k_err("firmware crashed!\n");
836 ath10k_err("hardware name %s version 0x%x\n",
837 ar->hw_params.name, ar->target_version);
5ba88b39 838 ath10k_err("firmware version: %s\n", ar->hw->wiphy->fw_version);
5e3dd157
KV		 839
840 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
1d2b48d6
MK		 841 ret = ath10k_pci_diag_read_mem(ar, host_addr,
842 &reg_dump_area, sizeof(u32));
843 if (ret) {
844 ath10k_err("failed to read FW dump area address: %d\n", ret);
5e3dd157
KV		 845 return;
846 }
847
848 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
849
850 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
851 &reg_dump_values[0],
852 REG_DUMP_COUNT_QCA988X * sizeof(u32));
853 if (ret != 0) {
1d2b48d6 854 ath10k_err("failed to read FW dump area: %d\n", ret);
5e3dd157
KV		 855 return;
856 }
857
858 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
859
860 ath10k_err("target Register Dump\n");
861 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
862 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
863 i,
864 reg_dump_values[i],
865 reg_dump_values[i + 1],
866 reg_dump_values[i + 2],
867 reg_dump_values[i + 3]);
affd3217 868
5e90de86 869 queue_work(ar->workqueue, &ar->restart_work);
5e3dd157
KV		 870}
871
872static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
873 int force)
874{
50f87a67
KV		 875 ath10k_dbg(ATH10K_DBG_PCI, "pci hif send complete check\n");
876
5e3dd157
KV		 877 if (!force) {
878 int resources;
879 /*
880 * Decide whether to actually poll for completions, or just
881 * wait for a later chance.
882 * If there seem to be plenty of resources left, then just wait
883 * since checking involves reading a CE register, which is a
884 * relatively expensive operation.
885 */
886 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
887
888 /*
889 * If at least 50% of the total resources are still available,
890 * don't bother checking again yet.
891 */
892 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
893 return;
894 }
895 ath10k_ce_per_engine_service(ar, pipe);
896}
897
e799bbff
MK		 898static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
899 struct ath10k_hif_cb *callbacks)
5e3dd157
KV		 900{
901 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
902
50f87a67 903 ath10k_dbg(ATH10K_DBG_PCI, "pci hif set callbacks\n");
5e3dd157
KV		 904
905 memcpy(&ar_pci->msg_callbacks_current, callbacks,
906 sizeof(ar_pci->msg_callbacks_current));
907}
908
c80de12b 909static int ath10k_pci_setup_ce_irq(struct ath10k *ar)
5e3dd157
KV		 910{
911 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
c80de12b
MK		 912 const struct ce_attr *attr;
913 struct ath10k_pci_pipe *pipe_info;
914 int pipe_num, disable_interrupts;
5e3dd157 915
c80de12b
MK		 916 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
917 pipe_info = &ar_pci->pipe_info[pipe_num];
918
919 /* Handle Diagnostic CE specially */
920 if (pipe_info->ce_hdl == ar_pci->ce_diag)
921 continue;
922
923 attr = &host_ce_config_wlan[pipe_num];
924
925 if (attr->src_nentries) {
926 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
927 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
928 ath10k_pci_ce_send_done,
929 disable_interrupts);
930 }
931
932 if (attr->dest_nentries)
933 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
934 ath10k_pci_ce_recv_data);
935 }
936
937 return 0;
938}
939
96a9d0dc 940static void ath10k_pci_kill_tasklet(struct ath10k *ar)
5e3dd157
KV		 941{
942 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 943 int i;
5e3dd157 944
5e3dd157 945 tasklet_kill(&ar_pci->intr_tq);
103d4f5e 946 tasklet_kill(&ar_pci->msi_fw_err);
ab977bd0 947 tasklet_kill(&ar_pci->early_irq_tasklet);
5e3dd157
KV		 948
949 for (i = 0; i < CE_COUNT; i++)
950 tasklet_kill(&ar_pci->pipe_info[i].intr);
96a9d0dc
MK		 951}
952
5e3dd157
KV		 953/* TODO - temporary mapping while we have too few CE's */
954static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
955 u16 service_id, u8 *ul_pipe,
956 u8 *dl_pipe, int *ul_is_polled,
957 int *dl_is_polled)
958{
959 int ret = 0;
960
50f87a67
KV		 961 ath10k_dbg(ATH10K_DBG_PCI, "pci hif map service\n");
962
5e3dd157
KV		 963 /* polling for received messages not supported */
964 *dl_is_polled = 0;
965
966 switch (service_id) {
967 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
968 /*
969 * Host->target HTT gets its own pipe, so it can be polled
970 * while other pipes are interrupt driven.
971 */
972 *ul_pipe = 4;
973 /*
974 * Use the same target->host pipe for HTC ctrl, HTC raw
975 * streams, and HTT.
976 */
977 *dl_pipe = 1;
978 break;
979
980 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
981 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
982 /*
983 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
984 * HTC_CTRL_RSVD_SVC could share the same pipe as the
985 * WMI services. So, if another CE is needed, change
986 * this to *ul_pipe = 3, which frees up CE 0.
987 */
988 /* *ul_pipe = 3; */
989 *ul_pipe = 0;
990 *dl_pipe = 1;
991 break;
992
993 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
994 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
995 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
996 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
997
998 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
999 *ul_pipe = 3;
1000 *dl_pipe = 2;
1001 break;
1002
1003 /* pipe 5 unused */
1004 /* pipe 6 reserved */
1005 /* pipe 7 reserved */
1006
1007 default:
1008 ret = -1;
1009 break;
1010 }
1011 *ul_is_polled =
1012 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1013
1014 return ret;
1015}
1016
1017static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1018 u8 *ul_pipe, u8 *dl_pipe)
1019{
1020 int ul_is_polled, dl_is_polled;
1021
50f87a67
KV		 1022 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get default pipe\n");
1023
5e3dd157
KV		 1024 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1025 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1026 ul_pipe,
1027 dl_pipe,
1028 &ul_is_polled,
1029 &dl_is_polled);
1030}
1031
87263e5b 1032static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
5e3dd157
KV		 1033 int num)
1034{
1035 struct ath10k *ar = pipe_info->hif_ce_state;
1036 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115 1037 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
5e3dd157
KV		 1038 struct sk_buff *skb;
1039 dma_addr_t ce_data;
1040 int i, ret = 0;
1041
1042 if (pipe_info->buf_sz == 0)
1043 return 0;
1044
1045 for (i = 0; i < num; i++) {
1046 skb = dev_alloc_skb(pipe_info->buf_sz);
1047 if (!skb) {
1d2b48d6 1048 ath10k_warn("failed to allocate skbuff for pipe %d\n",
5e3dd157
KV		 1049 num);
1050 ret = -ENOMEM;
1051 goto err;
1052 }
1053
1054 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1055
1056 ce_data = dma_map_single(ar->dev, skb->data,
1057 skb->len + skb_tailroom(skb),
1058 DMA_FROM_DEVICE);
1059
1060 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1d2b48d6 1061 ath10k_warn("failed to DMA map sk_buff\n");
5e3dd157
KV		 1062 dev_kfree_skb_any(skb);
1063 ret = -EIO;
1064 goto err;
1065 }
1066
1067 ATH10K_SKB_CB(skb)->paddr = ce_data;
1068
1069 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1070 pipe_info->buf_sz,
1071 PCI_DMA_FROMDEVICE);
1072
1073 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1074 ce_data);
1075 if (ret) {
1d2b48d6 1076 ath10k_warn("failed to enqueue to pipe %d: %d\n",
5e3dd157
KV		 1077 num, ret);
1078 goto err;
1079 }
1080 }
1081
1082 return ret;
1083
1084err:
1085 ath10k_pci_rx_pipe_cleanup(pipe_info);
1086 return ret;
1087}
1088
1089static int ath10k_pci_post_rx(struct ath10k *ar)
1090{
1091 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1092 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1093 const struct ce_attr *attr;
1094 int pipe_num, ret = 0;
1095
fad6ed78 1096 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157
KV		 1097 pipe_info = &ar_pci->pipe_info[pipe_num];
1098 attr = &host_ce_config_wlan[pipe_num];
1099
1100 if (attr->dest_nentries == 0)
1101 continue;
1102
1103 ret = ath10k_pci_post_rx_pipe(pipe_info,
1104 attr->dest_nentries - 1);
1105 if (ret) {
1d2b48d6
MK		 1106 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1107 pipe_num, ret);
5e3dd157
KV		 1108
1109 for (; pipe_num >= 0; pipe_num--) {
1110 pipe_info = &ar_pci->pipe_info[pipe_num];
1111 ath10k_pci_rx_pipe_cleanup(pipe_info);
1112 }
1113 return ret;
1114 }
1115 }
1116
1117 return 0;
1118}
1119
1120static int ath10k_pci_hif_start(struct ath10k *ar)
1121{
1122 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
ab977bd0 1123 int ret, ret_early;
5e3dd157 1124
50f87a67
KV		 1125 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif start\n");
1126
ab977bd0
MK		 1127 ath10k_pci_free_early_irq(ar);
1128 ath10k_pci_kill_tasklet(ar);
5e3dd157 1129
5d1aa946
MK		 1130 ret = ath10k_pci_request_irq(ar);
1131 if (ret) {
1132 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1133 ret);
2f5280da 1134 goto err_early_irq;
5d1aa946
MK		 1135 }
1136
c80de12b
MK		 1137 ret = ath10k_pci_setup_ce_irq(ar);
1138 if (ret) {
1139 ath10k_warn("failed to setup CE interrupts: %d\n", ret);
5d1aa946 1140 goto err_stop;
5e3dd157
KV		 1141 }
1142
1143 /* Post buffers once to start things off. */
1144 ret = ath10k_pci_post_rx(ar);
1145 if (ret) {
1d2b48d6
MK		 1146 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1147 ret);
5d1aa946 1148 goto err_stop;
5e3dd157
KV		 1149 }
1150
1151 ar_pci->started = 1;
1152 return 0;
c80de12b 1153
5d1aa946
MK		 1154err_stop:
1155 ath10k_ce_disable_interrupts(ar);
1156 ath10k_pci_free_irq(ar);
1157 ath10k_pci_kill_tasklet(ar);
ab977bd0
MK		 1158err_early_irq:
1159 /* Though there should be no interrupts (device was reset)
1160 * power_down() expects the early IRQ to be installed as per the
1161 * driver lifecycle. */
1162 ret_early = ath10k_pci_request_early_irq(ar);
1163 if (ret_early)
1164 ath10k_warn("failed to re-enable early irq: %d\n", ret_early);
1165
c80de12b 1166 return ret;
5e3dd157
KV		 1167}
1168
87263e5b 1169static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 1170{
1171 struct ath10k *ar;
1172 struct ath10k_pci *ar_pci;
2aa39115 1173 struct ath10k_ce_pipe *ce_hdl;
5e3dd157
KV		 1174 u32 buf_sz;
1175 struct sk_buff *netbuf;
1176 u32 ce_data;
1177
1178 buf_sz = pipe_info->buf_sz;
1179
1180 /* Unused Copy Engine */
1181 if (buf_sz == 0)
1182 return;
1183
1184 ar = pipe_info->hif_ce_state;
1185 ar_pci = ath10k_pci_priv(ar);
1186
1187 if (!ar_pci->started)
1188 return;
1189
1190 ce_hdl = pipe_info->ce_hdl;
1191
1192 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1193 &ce_data) == 0) {
1194 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1195 netbuf->len + skb_tailroom(netbuf),
1196 DMA_FROM_DEVICE);
1197 dev_kfree_skb_any(netbuf);
1198 }
1199}
1200
87263e5b 1201static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 1202{
1203 struct ath10k *ar;
1204 struct ath10k_pci *ar_pci;
2aa39115 1205 struct ath10k_ce_pipe *ce_hdl;
5e3dd157
KV		 1206 struct sk_buff *netbuf;
1207 u32 ce_data;
1208 unsigned int nbytes;
1209 unsigned int id;
1210 u32 buf_sz;
1211
1212 buf_sz = pipe_info->buf_sz;
1213
1214 /* Unused Copy Engine */
1215 if (buf_sz == 0)
1216 return;
1217
1218 ar = pipe_info->hif_ce_state;
1219 ar_pci = ath10k_pci_priv(ar);
1220
1221 if (!ar_pci->started)
1222 return;
1223
1224 ce_hdl = pipe_info->ce_hdl;
1225
1226 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1227 &ce_data, &nbytes, &id) == 0) {
a16942e6
MK		 1228 /* no need to call tx completion for NULL pointers */
1229 if (!netbuf)
2415fc16 1230 continue;
2415fc16 1231
e9bb0aa3
KV		 1232 ar_pci->msg_callbacks_current.tx_completion(ar,
1233 netbuf,
1234 id);
5e3dd157
KV		 1235 }
1236}
1237
1238/*
1239 * Cleanup residual buffers for device shutdown:
1240 * buffers that were enqueued for receive
1241 * buffers that were to be sent
1242 * Note: Buffers that had completed but which were
1243 * not yet processed are on a completion queue. They
1244 * are handled when the completion thread shuts down.
1245 */
1246static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1247{
1248 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1249 int pipe_num;
1250
fad6ed78 1251 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
87263e5b 1252 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1253
1254 pipe_info = &ar_pci->pipe_info[pipe_num];
1255 ath10k_pci_rx_pipe_cleanup(pipe_info);
1256 ath10k_pci_tx_pipe_cleanup(pipe_info);
1257 }
1258}
1259
1260static void ath10k_pci_ce_deinit(struct ath10k *ar)
1261{
25d0dbcb 1262 int i;
5e3dd157 1263
25d0dbcb
MK		 1264 for (i = 0; i < CE_COUNT; i++)
1265 ath10k_ce_deinit_pipe(ar, i);
5e3dd157
KV		 1266}
1267
1268static void ath10k_pci_hif_stop(struct ath10k *ar)
1269{
32270b61 1270 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5d1aa946 1271 int ret;
32270b61 1272
50f87a67 1273 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif stop\n");
5e3dd157 1274
5d1aa946
MK		 1275 ret = ath10k_ce_disable_interrupts(ar);
1276 if (ret)
1277 ath10k_warn("failed to disable CE interrupts: %d\n", ret);
32270b61 1278
5d1aa946
MK		 1279 ath10k_pci_free_irq(ar);
1280 ath10k_pci_kill_tasklet(ar);
5e3dd157 1281
ab977bd0
MK		 1282 ret = ath10k_pci_request_early_irq(ar);
1283 if (ret)
1284 ath10k_warn("failed to re-enable early irq: %d\n", ret);
1285
5e3dd157
KV		 1286 /* At this point, asynchronous threads are stopped, the target should
1287 * not DMA nor interrupt. We process the leftovers and then free
1288 * everything else up. */
1289
5e3dd157 1290 ath10k_pci_buffer_cleanup(ar);
32270b61 1291
6a42a47e
MK		 1292 /* Make the sure the device won't access any structures on the host by
1293 * resetting it. The device was fed with PCI CE ringbuffer
1294 * configuration during init. If ringbuffers are freed and the device
1295 * were to access them this could lead to memory corruption on the
1296 * host. */
fc36e3ff 1297 ath10k_pci_warm_reset(ar);
6a42a47e 1298
32270b61 1299 ar_pci->started = 0;
5e3dd157
KV		 1300}
1301
1302static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1303 void *req, u32 req_len,
1304 void *resp, u32 *resp_len)
1305{
1306 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115
MK		 1307 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1308 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1309 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1310 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
5e3dd157
KV		 1311 dma_addr_t req_paddr = 0;
1312 dma_addr_t resp_paddr = 0;
1313 struct bmi_xfer xfer = {};
1314 void *treq, *tresp = NULL;
1315 int ret = 0;
1316
85622cde
MK		 1317 might_sleep();
1318
5e3dd157
KV		 1319 if (resp && !resp_len)
1320 return -EINVAL;
1321
1322 if (resp && resp_len && *resp_len == 0)
1323 return -EINVAL;
1324
1325 treq = kmemdup(req, req_len, GFP_KERNEL);
1326 if (!treq)
1327 return -ENOMEM;
1328
1329 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1330 ret = dma_mapping_error(ar->dev, req_paddr);
1331 if (ret)
1332 goto err_dma;
1333
1334 if (resp && resp_len) {
1335 tresp = kzalloc(*resp_len, GFP_KERNEL);
1336 if (!tresp) {
1337 ret = -ENOMEM;
1338 goto err_req;
1339 }
1340
1341 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1342 DMA_FROM_DEVICE);
1343 ret = dma_mapping_error(ar->dev, resp_paddr);
1344 if (ret)
1345 goto err_req;
1346
1347 xfer.wait_for_resp = true;
1348 xfer.resp_len = 0;
1349
1350 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1351 }
1352
1353 init_completion(&xfer.done);
1354
1355 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1356 if (ret)
1357 goto err_resp;
1358
85622cde
MK		 1359 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1360 if (ret) {
5e3dd157
KV		 1361 u32 unused_buffer;
1362 unsigned int unused_nbytes;
1363 unsigned int unused_id;
1364
5e3dd157
KV		 1365 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1366 &unused_nbytes, &unused_id);
1367 } else {
1368 /* non-zero means we did not time out */
1369 ret = 0;
1370 }
1371
1372err_resp:
1373 if (resp) {
1374 u32 unused_buffer;
1375
1376 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1377 dma_unmap_single(ar->dev, resp_paddr,
1378 *resp_len, DMA_FROM_DEVICE);
1379 }
1380err_req:
1381 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1382
1383 if (ret == 0 && resp_len) {
1384 *resp_len = min(*resp_len, xfer.resp_len);
1385 memcpy(resp, tresp, xfer.resp_len);
1386 }
1387err_dma:
1388 kfree(treq);
1389 kfree(tresp);
1390
1391 return ret;
1392}
1393
5440ce25 1394static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
5e3dd157 1395{
5440ce25
MK		 1396 struct bmi_xfer *xfer;
1397 u32 ce_data;
1398 unsigned int nbytes;
1399 unsigned int transfer_id;
1400
1401 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1402 &nbytes, &transfer_id))
1403 return;
5e3dd157
KV		 1404
1405 if (xfer->wait_for_resp)
1406 return;
1407
1408 complete(&xfer->done);
1409}
1410
5440ce25 1411static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
5e3dd157 1412{
5440ce25
MK		 1413 struct bmi_xfer *xfer;
1414 u32 ce_data;
1415 unsigned int nbytes;
1416 unsigned int transfer_id;
1417 unsigned int flags;
1418
1419 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1420 &nbytes, &transfer_id, &flags))
1421 return;
5e3dd157
KV		 1422
1423 if (!xfer->wait_for_resp) {
1424 ath10k_warn("unexpected: BMI data received; ignoring\n");
1425 return;
1426 }
1427
1428 xfer->resp_len = nbytes;
1429 complete(&xfer->done);
1430}
1431
85622cde
MK		 1432static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1433 struct ath10k_ce_pipe *rx_pipe,
1434 struct bmi_xfer *xfer)
1435{
1436 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1437
1438 while (time_before_eq(jiffies, timeout)) {
1439 ath10k_pci_bmi_send_done(tx_pipe);
1440 ath10k_pci_bmi_recv_data(rx_pipe);
1441
1442 if (completion_done(&xfer->done))
1443 return 0;
1444
1445 schedule();
1446 }
1447
1448 return -ETIMEDOUT;
1449}
1450
5e3dd157
KV		 1451/*
1452 * Map from service/endpoint to Copy Engine.
1453 * This table is derived from the CE_PCI TABLE, above.
1454 * It is passed to the Target at startup for use by firmware.
1455 */
1456static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1457 {
1458 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1459 PIPEDIR_OUT, /* out = UL = host -> target */
1460 3,
1461 },
1462 {
1463 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1464 PIPEDIR_IN, /* in = DL = target -> host */
1465 2,
1466 },
1467 {
1468 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1469 PIPEDIR_OUT, /* out = UL = host -> target */
1470 3,
1471 },
1472 {
1473 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1474 PIPEDIR_IN, /* in = DL = target -> host */
1475 2,
1476 },
1477 {
1478 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1479 PIPEDIR_OUT, /* out = UL = host -> target */
1480 3,
1481 },
1482 {
1483 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1484 PIPEDIR_IN, /* in = DL = target -> host */
1485 2,
1486 },
1487 {
1488 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1489 PIPEDIR_OUT, /* out = UL = host -> target */
1490 3,
1491 },
1492 {
1493 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1494 PIPEDIR_IN, /* in = DL = target -> host */
1495 2,
1496 },
1497 {
1498 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1499 PIPEDIR_OUT, /* out = UL = host -> target */
1500 3,
1501 },
1502 {
1503 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1504 PIPEDIR_IN, /* in = DL = target -> host */
1505 2,
1506 },
1507 {
1508 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1509 PIPEDIR_OUT, /* out = UL = host -> target */
1510 0, /* could be moved to 3 (share with WMI) */
1511 },
1512 {
1513 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1514 PIPEDIR_IN, /* in = DL = target -> host */
1515 1,
1516 },
1517 {
1518 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1519 PIPEDIR_OUT, /* out = UL = host -> target */
1520 0,
1521 },
1522 {
1523 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1524 PIPEDIR_IN, /* in = DL = target -> host */
1525 1,
1526 },
1527 {
1528 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1529 PIPEDIR_OUT, /* out = UL = host -> target */
1530 4,
1531 },
1532 {
1533 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1534 PIPEDIR_IN, /* in = DL = target -> host */
1535 1,
1536 },
1537
1538 /* (Additions here) */
1539
1540 { /* Must be last */
1541 0,
1542 0,
1543 0,
1544 },
1545};
1546
1547/*
1548 * Send an interrupt to the device to wake up the Target CPU
1549 * so it has an opportunity to notice any changed state.
1550 */
1551static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1552{
1553 int ret;
1554 u32 core_ctrl;
1555
1556 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1557 CORE_CTRL_ADDRESS,
1558 &core_ctrl);
1559 if (ret) {
1d2b48d6 1560 ath10k_warn("failed to read core_ctrl: %d\n", ret);
5e3dd157
KV		 1561 return ret;
1562 }
1563
1564 /* A_INUM_FIRMWARE interrupt to Target CPU */
1565 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1566
1567 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1568 CORE_CTRL_ADDRESS,
1569 core_ctrl);
1d2b48d6
MK		 1570 if (ret) {
1571 ath10k_warn("failed to set target CPU interrupt mask: %d\n",
1572 ret);
1573 return ret;
1574 }
5e3dd157 1575
1d2b48d6 1576 return 0;
5e3dd157
KV		 1577}
1578
1579static int ath10k_pci_init_config(struct ath10k *ar)
1580{
1581 u32 interconnect_targ_addr;
1582 u32 pcie_state_targ_addr = 0;
1583 u32 pipe_cfg_targ_addr = 0;
1584 u32 svc_to_pipe_map = 0;
1585 u32 pcie_config_flags = 0;
1586 u32 ealloc_value;
1587 u32 ealloc_targ_addr;
1588 u32 flag2_value;
1589 u32 flag2_targ_addr;
1590 int ret = 0;
1591
1592 /* Download to Target the CE Config and the service-to-CE map */
1593 interconnect_targ_addr =
1594 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1595
1596 /* Supply Target-side CE configuration */
1597 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1598 &pcie_state_targ_addr);
1599 if (ret != 0) {
1600 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1601 return ret;
1602 }
1603
1604 if (pcie_state_targ_addr == 0) {
1605 ret = -EIO;
1606 ath10k_err("Invalid pcie state addr\n");
1607 return ret;
1608 }
1609
1610 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1611 offsetof(struct pcie_state,
1612 pipe_cfg_addr),
1613 &pipe_cfg_targ_addr);
1614 if (ret != 0) {
1615 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1616 return ret;
1617 }
1618
1619 if (pipe_cfg_targ_addr == 0) {
1620 ret = -EIO;
1621 ath10k_err("Invalid pipe cfg addr\n");
1622 return ret;
1623 }
1624
1625 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1626 target_ce_config_wlan,
1627 sizeof(target_ce_config_wlan));
1628
1629 if (ret != 0) {
1630 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1631 return ret;
1632 }
1633
1634 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1635 offsetof(struct pcie_state,
1636 svc_to_pipe_map),
1637 &svc_to_pipe_map);
1638 if (ret != 0) {
1639 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1640 return ret;
1641 }
1642
1643 if (svc_to_pipe_map == 0) {
1644 ret = -EIO;
1645 ath10k_err("Invalid svc_to_pipe map\n");
1646 return ret;
1647 }
1648
1649 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1650 target_service_to_ce_map_wlan,
1651 sizeof(target_service_to_ce_map_wlan));
1652 if (ret != 0) {
1653 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1654 return ret;
1655 }
1656
1657 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1658 offsetof(struct pcie_state,
1659 config_flags),
1660 &pcie_config_flags);
1661 if (ret != 0) {
1662 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1663 return ret;
1664 }
1665
1666 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1667
1668 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1669 offsetof(struct pcie_state, config_flags),
1670 &pcie_config_flags,
1671 sizeof(pcie_config_flags));
1672 if (ret != 0) {
1673 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1674 return ret;
1675 }
1676
1677 /* configure early allocation */
1678 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1679
1680 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1681 if (ret != 0) {
1682 ath10k_err("Faile to get early alloc val: %d\n", ret);
1683 return ret;
1684 }
1685
1686 /* first bank is switched to IRAM */
1687 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1688 HI_EARLY_ALLOC_MAGIC_MASK);
1689 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1690 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1691
1692 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1693 if (ret != 0) {
1694 ath10k_err("Failed to set early alloc val: %d\n", ret);
1695 return ret;
1696 }
1697
1698 /* Tell Target to proceed with initialization */
1699 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1700
1701 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1702 if (ret != 0) {
1703 ath10k_err("Failed to get option val: %d\n", ret);
1704 return ret;
1705 }
1706
1707 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1708
1709 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1710 if (ret != 0) {
1711 ath10k_err("Failed to set option val: %d\n", ret);
1712 return ret;
1713 }
1714
1715 return 0;
1716}
1717
25d0dbcb
MK		 1718static int ath10k_pci_alloc_ce(struct ath10k *ar)
1719{
1720 int i, ret;
1721
1722 for (i = 0; i < CE_COUNT; i++) {
1723 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1724 if (ret) {
1725 ath10k_err("failed to allocate copy engine pipe %d: %d\n",
1726 i, ret);
1727 return ret;
1728 }
1729 }
1730
1731 return 0;
1732}
1733
1734static void ath10k_pci_free_ce(struct ath10k *ar)
1735{
1736 int i;
5e3dd157 1737
25d0dbcb
MK		 1738 for (i = 0; i < CE_COUNT; i++)
1739 ath10k_ce_free_pipe(ar, i);
1740}
5e3dd157
KV		 1741
1742static int ath10k_pci_ce_init(struct ath10k *ar)
1743{
1744 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1745 struct ath10k_pci_pipe *pipe_info;
5e3dd157 1746 const struct ce_attr *attr;
25d0dbcb 1747 int pipe_num, ret;
5e3dd157 1748
fad6ed78 1749 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157 1750 pipe_info = &ar_pci->pipe_info[pipe_num];
25d0dbcb 1751 pipe_info->ce_hdl = &ar_pci->ce_states[pipe_num];
5e3dd157
KV		 1752 pipe_info->pipe_num = pipe_num;
1753 pipe_info->hif_ce_state = ar;
1754 attr = &host_ce_config_wlan[pipe_num];
1755
25d0dbcb
MK		 1756 ret = ath10k_ce_init_pipe(ar, pipe_num, attr);
1757 if (ret) {
1758 ath10k_err("failed to initialize copy engine pipe %d: %d\n",
1759 pipe_num, ret);
1760 return ret;
5e3dd157
KV		 1761 }
1762
fad6ed78 1763 if (pipe_num == CE_COUNT - 1) {
5e3dd157
KV		 1764 /*
1765 * Reserve the ultimate CE for
1766 * diagnostic Window support
1767 */
fad6ed78 1768 ar_pci->ce_diag = pipe_info->ce_hdl;
5e3dd157
KV		 1769 continue;
1770 }
1771
1772 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1773 }
1774
5e3dd157
KV		 1775 return 0;
1776}
1777
1778static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1779{
1780 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
b39712ce 1781 u32 fw_indicator;
5e3dd157
KV		 1782
1783 ath10k_pci_wake(ar);
1784
b39712ce 1785 fw_indicator = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
5e3dd157
KV		 1786
1787 if (fw_indicator & FW_IND_EVENT_PENDING) {
1788 /* ACK: clear Target-side pending event */
b39712ce 1789 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
5e3dd157
KV		 1790 fw_indicator & ~FW_IND_EVENT_PENDING);
1791
1792 if (ar_pci->started) {
1793 ath10k_pci_hif_dump_area(ar);
1794 } else {
1795 /*
1796 * Probable Target failure before we're prepared
1797 * to handle it. Generally unexpected.
1798 */
1799 ath10k_warn("early firmware event indicated\n");
1800 }
1801 }
1802
1803 ath10k_pci_sleep(ar);
1804}
1805
de01357b
MK		 1806/* this function effectively clears target memory controller assert line */
1807static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
1808{
1809 u32 val;
1810
1811 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1812 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1813 val | SOC_RESET_CONTROL_SI0_RST_MASK);
1814 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1815
1816 msleep(10);
1817
1818 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1819 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1820 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
1821 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1822
1823 msleep(10);
1824}
1825
fc36e3ff
MK		 1826static int ath10k_pci_warm_reset(struct ath10k *ar)
1827{
fc36e3ff
MK		 1828 int ret = 0;
1829 u32 val;
1830
50f87a67 1831 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset\n");
fc36e3ff
MK		 1832
1833 ret = ath10k_do_pci_wake(ar);
1834 if (ret) {
1835 ath10k_err("failed to wake up target: %d\n", ret);
1836 return ret;
1837 }
1838
1839 /* debug */
1840 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1841 PCIE_INTR_CAUSE_ADDRESS);
1842 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val);
1843
1844 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1845 CPU_INTR_ADDRESS);
1846 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1847 val);
1848
1849 /* disable pending irqs */
1850 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1851 PCIE_INTR_ENABLE_ADDRESS, 0);
1852
1853 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1854 PCIE_INTR_CLR_ADDRESS, ~0);
1855
1856 msleep(100);
1857
1858 /* clear fw indicator */
b39712ce 1859 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
fc36e3ff
MK		 1860
1861 /* clear target LF timer interrupts */
1862 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1863 SOC_LF_TIMER_CONTROL0_ADDRESS);
1864 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
1865 SOC_LF_TIMER_CONTROL0_ADDRESS,
1866 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
1867
1868 /* reset CE */
1869 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1870 SOC_RESET_CONTROL_ADDRESS);
1871 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1872 val | SOC_RESET_CONTROL_CE_RST_MASK);
1873 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1874 SOC_RESET_CONTROL_ADDRESS);
1875 msleep(10);
1876
1877 /* unreset CE */
1878 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1879 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
1880 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1881 SOC_RESET_CONTROL_ADDRESS);
1882 msleep(10);
1883
de01357b
MK		 1884 ath10k_pci_warm_reset_si0(ar);
1885
fc36e3ff
MK		 1886 /* debug */
1887 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1888 PCIE_INTR_CAUSE_ADDRESS);
1889 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val);
1890
1891 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1892 CPU_INTR_ADDRESS);
1893 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1894 val);
1895
1896 /* CPU warm reset */
1897 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1898 SOC_RESET_CONTROL_ADDRESS);
1899 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1900 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
1901
1902 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1903 SOC_RESET_CONTROL_ADDRESS);
1904 ath10k_dbg(ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n", val);
1905
1906 msleep(100);
1907
1908 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset complete\n");
1909
1910 ath10k_do_pci_sleep(ar);
1911 return ret;
1912}
1913
1914static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
8c5c5368 1915{
8cc8df90 1916 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
95cbb6a8 1917 const char *irq_mode;
8c5c5368
MK		 1918 int ret;
1919
1920 /*
1921 * Bring the target up cleanly.
1922 *
1923 * The target may be in an undefined state with an AUX-powered Target
1924 * and a Host in WoW mode. If the Host crashes, loses power, or is
1925 * restarted (without unloading the driver) then the Target is left
1926 * (aux) powered and running. On a subsequent driver load, the Target
1927 * is in an unexpected state. We try to catch that here in order to
1928 * reset the Target and retry the probe.
1929 */
fc36e3ff
MK		 1930 if (cold_reset)
1931 ret = ath10k_pci_cold_reset(ar);
1932 else
1933 ret = ath10k_pci_warm_reset(ar);
1934
5b2589fc
MK		 1935 if (ret) {
1936 ath10k_err("failed to reset target: %d\n", ret);
98563d5a 1937 goto err;
5b2589fc 1938 }
8c5c5368 1939
8cc8df90 1940 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368 1941 /* Force AWAKE forever */
8c5c5368 1942 ath10k_do_pci_wake(ar);
8c5c5368
MK		 1943
1944 ret = ath10k_pci_ce_init(ar);
1d2b48d6
MK		 1945 if (ret) {
1946 ath10k_err("failed to initialize CE: %d\n", ret);
8c5c5368 1947 goto err_ps;
1d2b48d6 1948 }
8c5c5368 1949
98563d5a
MK		 1950 ret = ath10k_ce_disable_interrupts(ar);
1951 if (ret) {
1952 ath10k_err("failed to disable CE interrupts: %d\n", ret);
8c5c5368 1953 goto err_ce;
98563d5a 1954 }
8c5c5368 1955
fc15ca13 1956 ret = ath10k_pci_init_irq(ar);
8c5c5368 1957 if (ret) {
fc15ca13 1958 ath10k_err("failed to init irqs: %d\n", ret);
8c5c5368
MK		 1959 goto err_ce;
1960 }
1961
ab977bd0
MK		 1962 ret = ath10k_pci_request_early_irq(ar);
1963 if (ret) {
1964 ath10k_err("failed to request early irq: %d\n", ret);
1965 goto err_deinit_irq;
1966 }
1967
98563d5a
MK		 1968 ret = ath10k_pci_wait_for_target_init(ar);
1969 if (ret) {
1970 ath10k_err("failed to wait for target to init: %d\n", ret);
ab977bd0 1971 goto err_free_early_irq;
98563d5a
MK		 1972 }
1973
1974 ret = ath10k_pci_init_config(ar);
1975 if (ret) {
1976 ath10k_err("failed to setup init config: %d\n", ret);
ab977bd0 1977 goto err_free_early_irq;
98563d5a 1978 }
8c5c5368
MK		 1979
1980 ret = ath10k_pci_wake_target_cpu(ar);
1981 if (ret) {
1d2b48d6 1982 ath10k_err("could not wake up target CPU: %d\n", ret);
ab977bd0 1983 goto err_free_early_irq;
8c5c5368
MK		 1984 }
1985
95cbb6a8
KV		 1986 if (ar_pci->num_msi_intrs > 1)
1987 irq_mode = "MSI-X";
1988 else if (ar_pci->num_msi_intrs == 1)
1989 irq_mode = "MSI";
1990 else
1991 irq_mode = "legacy";
1992
650b91fb 1993 if (!test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
78a9cb4c
KV		 1994 ath10k_info("pci irq %s irq_mode %d reset_mode %d\n",
1995 irq_mode, ath10k_pci_irq_mode,
1996 ath10k_pci_reset_mode);
95cbb6a8 1997
8c5c5368
MK		 1998 return 0;
1999
ab977bd0
MK		 2000err_free_early_irq:
2001 ath10k_pci_free_early_irq(ar);
fc15ca13
MK		 2002err_deinit_irq:
2003 ath10k_pci_deinit_irq(ar);
8c5c5368
MK		 2004err_ce:
2005 ath10k_pci_ce_deinit(ar);
fc36e3ff 2006 ath10k_pci_warm_reset(ar);
8c5c5368 2007err_ps:
8cc8df90 2008 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368
MK		 2009 ath10k_do_pci_sleep(ar);
2010err:
2011 return ret;
2012}
2013
61c95cea
MK		 2014static int ath10k_pci_hif_power_up_warm(struct ath10k *ar)
2015{
2016 int i, ret;
2017
2018 /*
2019 * Sometime warm reset succeeds after retries.
2020 *
2021 * FIXME: It might be possible to tune ath10k_pci_warm_reset() to work
2022 * at first try.
2023 */
2024 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2025 ret = __ath10k_pci_hif_power_up(ar, false);
2026 if (ret == 0)
2027 break;
2028
2029 ath10k_warn("failed to warm reset (attempt %d out of %d): %d\n",
2030 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, ret);
2031 }
2032
2033 return ret;
2034}
2035
fc36e3ff
MK		 2036static int ath10k_pci_hif_power_up(struct ath10k *ar)
2037{
2038 int ret;
2039
50f87a67
KV		 2040 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power up\n");
2041
fc36e3ff
MK		 2042 /*
2043 * Hardware CUS232 version 2 has some issues with cold reset and the
2044 * preferred (and safer) way to perform a device reset is through a
2045 * warm reset.
2046 *
61c95cea
MK		 2047 * Warm reset doesn't always work though so fall back to cold reset may
2048 * be necessary.
fc36e3ff 2049 */
61c95cea 2050 ret = ath10k_pci_hif_power_up_warm(ar);
fc36e3ff 2051 if (ret) {
35098463 2052 ath10k_warn("failed to power up target using warm reset: %d\n",
fc36e3ff
MK		 2053 ret);
2054
35098463
KV		 2055 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY)
2056 return ret;
2057
2058 ath10k_warn("trying cold reset\n");
2059
fc36e3ff
MK		 2060 ret = __ath10k_pci_hif_power_up(ar, true);
2061 if (ret) {
2062 ath10k_err("failed to power up target using cold reset too (%d)\n",
2063 ret);
2064 return ret;
2065 }
2066 }
2067
2068 return 0;
2069}
2070
8c5c5368
MK		 2071static void ath10k_pci_hif_power_down(struct ath10k *ar)
2072{
8cc8df90
BM		 2073 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2074
50f87a67
KV		 2075 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power down\n");
2076
ab977bd0
MK		 2077 ath10k_pci_free_early_irq(ar);
2078 ath10k_pci_kill_tasklet(ar);
fc15ca13 2079 ath10k_pci_deinit_irq(ar);
df5e8525 2080 ath10k_pci_ce_deinit(ar);
fc36e3ff 2081 ath10k_pci_warm_reset(ar);
8cc8df90 2082
8cc8df90 2083 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368
MK		 2084 ath10k_do_pci_sleep(ar);
2085}
2086
8cd13cad
MK		 2087#ifdef CONFIG_PM
2088
2089#define ATH10K_PCI_PM_CONTROL 0x44
2090
2091static int ath10k_pci_hif_suspend(struct ath10k *ar)
2092{
2093 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2094 struct pci_dev *pdev = ar_pci->pdev;
2095 u32 val;
2096
2097 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
2098
2099 if ((val & 0x000000ff) != 0x3) {
2100 pci_save_state(pdev);
2101 pci_disable_device(pdev);
2102 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
2103 (val & 0xffffff00) | 0x03);
2104 }
2105
2106 return 0;
2107}
2108
2109static int ath10k_pci_hif_resume(struct ath10k *ar)
2110{
2111 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2112 struct pci_dev *pdev = ar_pci->pdev;
2113 u32 val;
2114
2115 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
2116
2117 if ((val & 0x000000ff) != 0) {
2118 pci_restore_state(pdev);
2119 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
2120 val & 0xffffff00);
2121 /*
2122 * Suspend/Resume resets the PCI configuration space,
2123 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
2124 * to keep PCI Tx retries from interfering with C3 CPU state
2125 */
2126 pci_read_config_dword(pdev, 0x40, &val);
2127
2128 if ((val & 0x0000ff00) != 0)
2129 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2130 }
2131
2132 return 0;
2133}
2134#endif
2135
5e3dd157 2136static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
726346fc 2137 .tx_sg = ath10k_pci_hif_tx_sg,
5e3dd157
KV		 2138 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2139 .start = ath10k_pci_hif_start,
2140 .stop = ath10k_pci_hif_stop,
2141 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2142 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2143 .send_complete_check = ath10k_pci_hif_send_complete_check,
e799bbff 2144 .set_callbacks = ath10k_pci_hif_set_callbacks,
5e3dd157 2145 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
8c5c5368
MK		 2146 .power_up = ath10k_pci_hif_power_up,
2147 .power_down = ath10k_pci_hif_power_down,
8cd13cad
MK		 2148#ifdef CONFIG_PM
2149 .suspend = ath10k_pci_hif_suspend,
2150 .resume = ath10k_pci_hif_resume,
2151#endif
5e3dd157
KV		 2152};
2153
2154static void ath10k_pci_ce_tasklet(unsigned long ptr)
2155{
87263e5b 2156 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
5e3dd157
KV		 2157 struct ath10k_pci *ar_pci = pipe->ar_pci;
2158
2159 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2160}
2161
2162static void ath10k_msi_err_tasklet(unsigned long data)
2163{
2164 struct ath10k *ar = (struct ath10k *)data;
2165
2166 ath10k_pci_fw_interrupt_handler(ar);
2167}
2168
2169/*
2170 * Handler for a per-engine interrupt on a PARTICULAR CE.
2171 * This is used in cases where each CE has a private MSI interrupt.
2172 */
2173static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2174{
2175 struct ath10k *ar = arg;
2176 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2177 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2178
e5742672 2179 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
5e3dd157
KV		 2180 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
2181 return IRQ_HANDLED;
2182 }
2183
2184 /*
2185 * NOTE: We are able to derive ce_id from irq because we
2186 * use a one-to-one mapping for CE's 0..5.
2187 * CE's 6 & 7 do not use interrupts at all.
2188 *
2189 * This mapping must be kept in sync with the mapping
2190 * used by firmware.
2191 */
2192 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2193 return IRQ_HANDLED;
2194}
2195
2196static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2197{
2198 struct ath10k *ar = arg;
2199 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2200
2201 tasklet_schedule(&ar_pci->msi_fw_err);
2202 return IRQ_HANDLED;
2203}
2204
2205/*
2206 * Top-level interrupt handler for all PCI interrupts from a Target.
2207 * When a block of MSI interrupts is allocated, this top-level handler
2208 * is not used; instead, we directly call the correct sub-handler.
2209 */
2210static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2211{
2212 struct ath10k *ar = arg;
2213 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2214
2215 if (ar_pci->num_msi_intrs == 0) {
e539887b
MK		 2216 if (!ath10k_pci_irq_pending(ar))
2217 return IRQ_NONE;
2218
2685218b 2219 ath10k_pci_disable_and_clear_legacy_irq(ar);
5e3dd157
KV		 2220 }
2221
2222 tasklet_schedule(&ar_pci->intr_tq);
2223
2224 return IRQ_HANDLED;
2225}
2226
ab977bd0
MK		 2227static void ath10k_pci_early_irq_tasklet(unsigned long data)
2228{
2229 struct ath10k *ar = (struct ath10k *)data;
ab977bd0
MK		 2230 u32 fw_ind;
2231 int ret;
2232
2233 ret = ath10k_pci_wake(ar);
2234 if (ret) {
2235 ath10k_warn("failed to wake target in early irq tasklet: %d\n",
2236 ret);
2237 return;
2238 }
2239
b39712ce 2240 fw_ind = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
ab977bd0 2241 if (fw_ind & FW_IND_EVENT_PENDING) {
b39712ce 2242 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
ab977bd0
MK		 2243 fw_ind & ~FW_IND_EVENT_PENDING);
2244
2245 /* Some structures are unavailable during early boot or at
2246 * driver teardown so just print that the device has crashed. */
2247 ath10k_warn("device crashed - no diagnostics available\n");
2248 }
2249
2250 ath10k_pci_sleep(ar);
2251 ath10k_pci_enable_legacy_irq(ar);
2252}
2253
5e3dd157
KV		 2254static void ath10k_pci_tasklet(unsigned long data)
2255{
2256 struct ath10k *ar = (struct ath10k *)data;
2257 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2258
2259 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2260 ath10k_ce_per_engine_service_any(ar);
2261
2685218b
MK		 2262 /* Re-enable legacy irq that was disabled in the irq handler */
2263 if (ar_pci->num_msi_intrs == 0)
2264 ath10k_pci_enable_legacy_irq(ar);
5e3dd157
KV		 2265}
2266
fc15ca13 2267static int ath10k_pci_request_irq_msix(struct ath10k *ar)
5e3dd157
KV		 2268{
2269 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
fc15ca13 2270 int ret, i;
5e3dd157
KV		 2271
2272 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2273 ath10k_pci_msi_fw_handler,
2274 IRQF_SHARED, "ath10k_pci", ar);
591ecdb8 2275 if (ret) {
fc15ca13 2276 ath10k_warn("failed to request MSI-X fw irq %d: %d\n",
591ecdb8 2277 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
5e3dd157 2278 return ret;
591ecdb8 2279 }
5e3dd157
KV		 2280
2281 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2282 ret = request_irq(ar_pci->pdev->irq + i,
2283 ath10k_pci_per_engine_handler,
2284 IRQF_SHARED, "ath10k_pci", ar);
2285 if (ret) {
fc15ca13 2286 ath10k_warn("failed to request MSI-X ce irq %d: %d\n",
5e3dd157
KV		 2287 ar_pci->pdev->irq + i, ret);
2288
87b1423b
MK		 2289 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2290 free_irq(ar_pci->pdev->irq + i, ar);
5e3dd157 2291
87b1423b 2292 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
5e3dd157
KV		 2293 return ret;
2294 }
2295 }
2296
5e3dd157
KV		 2297 return 0;
2298}
2299
fc15ca13 2300static int ath10k_pci_request_irq_msi(struct ath10k *ar)
5e3dd157
KV		 2301{
2302 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2303 int ret;
2304
5e3dd157
KV		 2305 ret = request_irq(ar_pci->pdev->irq,
2306 ath10k_pci_interrupt_handler,
2307 IRQF_SHARED, "ath10k_pci", ar);
fc15ca13
MK		 2308 if (ret) {
2309 ath10k_warn("failed to request MSI irq %d: %d\n",
2310 ar_pci->pdev->irq, ret);
5e3dd157
KV		 2311 return ret;
2312 }
2313
5e3dd157
KV		 2314 return 0;
2315}
2316
fc15ca13 2317static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
5e3dd157
KV		 2318{
2319 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2320 int ret;
2321
2322 ret = request_irq(ar_pci->pdev->irq,
2323 ath10k_pci_interrupt_handler,
2324 IRQF_SHARED, "ath10k_pci", ar);
f3782744 2325 if (ret) {
fc15ca13
MK		 2326 ath10k_warn("failed to request legacy irq %d: %d\n",
2327 ar_pci->pdev->irq, ret);
5e3dd157 2328 return ret;
f3782744 2329 }
5e3dd157 2330
5e3dd157
KV		 2331 return 0;
2332}
2333
fc15ca13
MK		 2334static int ath10k_pci_request_irq(struct ath10k *ar)
2335{
2336 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 2337
fc15ca13
MK		 2338 switch (ar_pci->num_msi_intrs) {
2339 case 0:
2340 return ath10k_pci_request_irq_legacy(ar);
2341 case 1:
2342 return ath10k_pci_request_irq_msi(ar);
2343 case MSI_NUM_REQUEST:
2344 return ath10k_pci_request_irq_msix(ar);
2345 }
5e3dd157 2346
fc15ca13
MK		 2347 ath10k_warn("unknown irq configuration upon request\n");
2348 return -EINVAL;
5e3dd157
KV		 2349}
2350
fc15ca13
MK		 2351static void ath10k_pci_free_irq(struct ath10k *ar)
2352{
2353 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2354 int i;
2355
2356 /* There's at least one interrupt irregardless whether its legacy INTR
2357 * or MSI or MSI-X */
2358 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2359 free_irq(ar_pci->pdev->irq + i, ar);
2360}
2361
2362static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
5e3dd157
KV		 2363{
2364 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157
KV		 2365 int i;
2366
fc15ca13 2367 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
5e3dd157 2368 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
fc15ca13 2369 (unsigned long)ar);
ab977bd0
MK		 2370 tasklet_init(&ar_pci->early_irq_tasklet, ath10k_pci_early_irq_tasklet,
2371 (unsigned long)ar);
5e3dd157
KV		 2372
2373 for (i = 0; i < CE_COUNT; i++) {
2374 ar_pci->pipe_info[i].ar_pci = ar_pci;
fc15ca13 2375 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
5e3dd157
KV		 2376 (unsigned long)&ar_pci->pipe_info[i]);
2377 }
fc15ca13
MK		 2378}
2379
2380static int ath10k_pci_init_irq(struct ath10k *ar)
2381{
2382 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
cfe9c45b
MK		 2383 bool msix_supported = test_bit(ATH10K_PCI_FEATURE_MSI_X,
2384 ar_pci->features);
fc15ca13 2385 int ret;
5e3dd157 2386
fc15ca13 2387 ath10k_pci_init_irq_tasklets(ar);
5e3dd157 2388
cfe9c45b
MK		 2389 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO &&
2390 !test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
2391 ath10k_info("limiting irq mode to: %d\n", ath10k_pci_irq_mode);
5e3dd157 2392
fc15ca13 2393 /* Try MSI-X */
cfe9c45b
MK		 2394 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO && msix_supported) {
2395 ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
5ad6867c
AG		 2396 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2397 ar_pci->num_msi_intrs);
2398 if (ret > 0)
cfe9c45b 2399 return 0;
5e3dd157 2400
cfe9c45b 2401 /* fall-through */
5e3dd157
KV		 2402 }
2403
fc15ca13 2404 /* Try MSI */
cfe9c45b
MK		 2405 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2406 ar_pci->num_msi_intrs = 1;
2407 ret = pci_enable_msi(ar_pci->pdev);
5e3dd157 2408 if (ret == 0)
cfe9c45b 2409 return 0;
5e3dd157 2410
cfe9c45b 2411 /* fall-through */
5e3dd157
KV		 2412 }
2413
fc15ca13
MK		 2414 /* Try legacy irq
2415 *
2416 * A potential race occurs here: The CORE_BASE write
2417 * depends on target correctly decoding AXI address but
2418 * host won't know when target writes BAR to CORE_CTRL.
2419 * This write might get lost if target has NOT written BAR.
2420 * For now, fix the race by repeating the write in below
2421 * synchronization checking. */
2422 ar_pci->num_msi_intrs = 0;
5e3dd157 2423
fc15ca13
MK		 2424 ret = ath10k_pci_wake(ar);
2425 if (ret) {
2426 ath10k_warn("failed to wake target: %d\n", ret);
2427 return ret;
5e3dd157
KV		 2428 }
2429
fc15ca13
MK		 2430 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2431 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2432 ath10k_pci_sleep(ar);
2433
2434 return 0;
5e3dd157
KV		 2435}
2436
fc15ca13 2437static int ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
5e3dd157 2438{
fc15ca13 2439 int ret;
5e3dd157 2440
fc15ca13 2441 ret = ath10k_pci_wake(ar);
f3782744 2442 if (ret) {
fc15ca13 2443 ath10k_warn("failed to wake target: %d\n", ret);
f3782744
KV		 2444 return ret;
2445 }
5e3dd157 2446
fc15ca13
MK		 2447 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2448 0);
2449 ath10k_pci_sleep(ar);
2450
2451 return 0;
5e3dd157
KV		 2452}
2453
fc15ca13 2454static int ath10k_pci_deinit_irq(struct ath10k *ar)
5e3dd157
KV		 2455{
2456 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 2457
fc15ca13
MK		 2458 switch (ar_pci->num_msi_intrs) {
2459 case 0:
2460 return ath10k_pci_deinit_irq_legacy(ar);
2461 case 1:
2462 /* fall-through */
2463 case MSI_NUM_REQUEST:
5e3dd157 2464 pci_disable_msi(ar_pci->pdev);
fc15ca13 2465 return 0;
bb8b621a
AG		 2466 default:
2467 pci_disable_msi(ar_pci->pdev);
fc15ca13
MK		 2468 }
2469
2470 ath10k_warn("unknown irq configuration upon deinit\n");
2471 return -EINVAL;
5e3dd157
KV		 2472}
2473
d7fb47f5 2474static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
5e3dd157
KV		 2475{
2476 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
0399eca8 2477 unsigned long timeout;
f3782744 2478 int ret;
0399eca8 2479 u32 val;
5e3dd157 2480
50f87a67
KV		 2481 ath10k_dbg(ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2482
98563d5a 2483 ret = ath10k_pci_wake(ar);
f3782744 2484 if (ret) {
0399eca8 2485 ath10k_err("failed to wake up target for init: %d\n", ret);
f3782744
KV		 2486 return ret;
2487 }
5e3dd157 2488
0399eca8
KV		 2489 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2490
2491 do {
2492 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2493
50f87a67
KV		 2494 ath10k_dbg(ATH10K_DBG_BOOT, "boot target indicator %x\n", val);
2495
0399eca8
KV		 2496 /* target should never return this */
2497 if (val == 0xffffffff)
2498 continue;
2499
7710cd2e
MK		 2500 /* the device has crashed so don't bother trying anymore */
2501 if (val & FW_IND_EVENT_PENDING)
2502 break;
2503
0399eca8
KV		 2504 if (val & FW_IND_INITIALIZED)
2505 break;
2506
5e3dd157
KV		 2507 if (ar_pci->num_msi_intrs == 0)
2508 /* Fix potential race by repeating CORE_BASE writes */
0399eca8
KV		 2509 ath10k_pci_soc_write32(ar, PCIE_INTR_ENABLE_ADDRESS,
2510 PCIE_INTR_FIRMWARE_MASK |
2511 PCIE_INTR_CE_MASK_ALL);
2512
5e3dd157 2513 mdelay(10);
0399eca8 2514 } while (time_before(jiffies, timeout));
5e3dd157 2515
6a4f6e1d
MK		 2516 if (val == 0xffffffff) {
2517 ath10k_err("failed to read device register, device is gone\n");
2518 ret = -EIO;
2519 goto out;
2520 }
2521
7710cd2e
MK		 2522 if (val & FW_IND_EVENT_PENDING) {
2523 ath10k_warn("device has crashed during init\n");
2524 ret = -ECOMM;
2525 goto out;
2526 }
2527
6a4f6e1d 2528 if (!(val & FW_IND_INITIALIZED)) {
0399eca8
KV		 2529 ath10k_err("failed to receive initialized event from target: %08x\n",
2530 val);
2531 ret = -ETIMEDOUT;
5b2589fc 2532 goto out;
5e3dd157
KV		 2533 }
2534
50f87a67
KV		 2535 ath10k_dbg(ATH10K_DBG_BOOT, "boot target initialised\n");
2536
5b2589fc 2537out:
98563d5a 2538 ath10k_pci_sleep(ar);
5b2589fc 2539 return ret;
5e3dd157
KV		 2540}
2541
fc36e3ff 2542static int ath10k_pci_cold_reset(struct ath10k *ar)
5e3dd157 2543{
5b2589fc 2544 int i, ret;
5e3dd157
KV		 2545 u32 val;
2546
50f87a67
KV		 2547 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset\n");
2548
5b2589fc
MK		 2549 ret = ath10k_do_pci_wake(ar);
2550 if (ret) {
2551 ath10k_err("failed to wake up target: %d\n",
2552 ret);
2553 return ret;
5e3dd157
KV		 2554 }
2555
2556 /* Put Target, including PCIe, into RESET. */
e479ed43 2557 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
5e3dd157 2558 val |= 1;
e479ed43 2559 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
5e3dd157
KV		 2560
2561 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
e479ed43 2562 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
5e3dd157
KV		 2563 RTC_STATE_COLD_RESET_MASK)
2564 break;
2565 msleep(1);
2566 }
2567
2568 /* Pull Target, including PCIe, out of RESET. */
2569 val &= ~1;
e479ed43 2570 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
5e3dd157
KV		 2571
2572 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
e479ed43 2573 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
5e3dd157
KV		 2574 RTC_STATE_COLD_RESET_MASK))
2575 break;
2576 msleep(1);
2577 }
2578
5b2589fc 2579 ath10k_do_pci_sleep(ar);
50f87a67
KV		 2580
2581 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset complete\n");
2582
5b2589fc 2583 return 0;
5e3dd157
KV		 2584}
2585
2586static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2587{
2588 int i;
2589
2590 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2591 if (!test_bit(i, ar_pci->features))
2592 continue;
2593
2594 switch (i) {
2595 case ATH10K_PCI_FEATURE_MSI_X:
24cfade1 2596 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
5e3dd157 2597 break;
8cc8df90 2598 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
24cfade1 2599 ath10k_dbg(ATH10K_DBG_BOOT, "QCA98XX SoC power save enabled\n");
8cc8df90 2600 break;
5e3dd157
KV		 2601 }
2602 }
2603}
2604
2605static int ath10k_pci_probe(struct pci_dev *pdev,
2606 const struct pci_device_id *pci_dev)
2607{
2608 void __iomem *mem;
2609 int ret = 0;
2610 struct ath10k *ar;
2611 struct ath10k_pci *ar_pci;
e01ae68c 2612 u32 lcr_val, chip_id;
5e3dd157 2613
50f87a67 2614 ath10k_dbg(ATH10K_DBG_PCI, "pci probe\n");
5e3dd157
KV		 2615
2616 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2617 if (ar_pci == NULL)
2618 return -ENOMEM;
2619
2620 ar_pci->pdev = pdev;
2621 ar_pci->dev = &pdev->dev;
2622
2623 switch (pci_dev->device) {
5e3dd157
KV		 2624 case QCA988X_2_0_DEVICE_ID:
2625 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2626 break;
2627 default:
2628 ret = -ENODEV;
6d3be300 2629 ath10k_err("Unknown device ID: %d\n", pci_dev->device);
5e3dd157
KV		 2630 goto err_ar_pci;
2631 }
2632
e42c1fbd 2633 if (ath10k_pci_target_ps)
8cc8df90
BM		 2634 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2635
5e3dd157
KV		 2636 ath10k_pci_dump_features(ar_pci);
2637
3a0861ff 2638 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
5e3dd157 2639 if (!ar) {
1d2b48d6 2640 ath10k_err("failed to create driver core\n");
5e3dd157
KV		 2641 ret = -EINVAL;
2642 goto err_ar_pci;
2643 }
2644
5e3dd157 2645 ar_pci->ar = ar;
5e3dd157
KV		 2646 atomic_set(&ar_pci->keep_awake_count, 0);
2647
2648 pci_set_drvdata(pdev, ar);
2649
2650 /*
2651 * Without any knowledge of the Host, the Target may have been reset or
2652 * power cycled and its Config Space may no longer reflect the PCI
2653 * address space that was assigned earlier by the PCI infrastructure.
2654 * Refresh it now.
2655 */
2656 ret = pci_assign_resource(pdev, BAR_NUM);
2657 if (ret) {
1d2b48d6 2658 ath10k_err("failed to assign PCI space: %d\n", ret);
5e3dd157
KV		 2659 goto err_ar;
2660 }
2661
2662 ret = pci_enable_device(pdev);
2663 if (ret) {
1d2b48d6 2664 ath10k_err("failed to enable PCI device: %d\n", ret);
5e3dd157
KV		 2665 goto err_ar;
2666 }
2667
2668 /* Request MMIO resources */
2669 ret = pci_request_region(pdev, BAR_NUM, "ath");
2670 if (ret) {
1d2b48d6 2671 ath10k_err("failed to request MMIO region: %d\n", ret);
5e3dd157
KV		 2672 goto err_device;
2673 }
2674
2675 /*
2676 * Target structures have a limit of 32 bit DMA pointers.
2677 * DMA pointers can be wider than 32 bits by default on some systems.
2678 */
2679 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2680 if (ret) {
1d2b48d6 2681 ath10k_err("failed to set DMA mask to 32-bit: %d\n", ret);
5e3dd157
KV		 2682 goto err_region;
2683 }
2684
2685 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2686 if (ret) {
1d2b48d6 2687 ath10k_err("failed to set consistent DMA mask to 32-bit\n");
5e3dd157
KV		 2688 goto err_region;
2689 }
2690
2691 /* Set bus master bit in PCI_COMMAND to enable DMA */
2692 pci_set_master(pdev);
2693
2694 /*
2695 * Temporary FIX: disable ASPM
2696 * Will be removed after the OTP is programmed
2697 */
2698 pci_read_config_dword(pdev, 0x80, &lcr_val);
2699 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2700
2701 /* Arrange for access to Target SoC registers. */
2702 mem = pci_iomap(pdev, BAR_NUM, 0);
2703 if (!mem) {
1d2b48d6 2704 ath10k_err("failed to perform IOMAP for BAR%d\n", BAR_NUM);
5e3dd157
KV		 2705 ret = -EIO;
2706 goto err_master;
2707 }
2708
2709 ar_pci->mem = mem;
2710
2711 spin_lock_init(&ar_pci->ce_lock);
2712
e01ae68c
KV		 2713 ret = ath10k_do_pci_wake(ar);
2714 if (ret) {
2715 ath10k_err("Failed to get chip id: %d\n", ret);
12eb0879 2716 goto err_iomap;
e01ae68c
KV		 2717 }
2718
233eb97f 2719 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
e01ae68c
KV		 2720
2721 ath10k_do_pci_sleep(ar);
2722
25d0dbcb
MK		 2723 ret = ath10k_pci_alloc_ce(ar);
2724 if (ret) {
2725 ath10k_err("failed to allocate copy engine pipes: %d\n", ret);
2726 goto err_iomap;
2727 }
2728
24cfade1
KV		 2729 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2730
e01ae68c 2731 ret = ath10k_core_register(ar, chip_id);
5e3dd157 2732 if (ret) {
1d2b48d6 2733 ath10k_err("failed to register driver core: %d\n", ret);
25d0dbcb 2734 goto err_free_ce;
5e3dd157
KV		 2735 }
2736
2737 return 0;
2738
25d0dbcb
MK		 2739err_free_ce:
2740 ath10k_pci_free_ce(ar);
5e3dd157
KV		 2741err_iomap:
2742 pci_iounmap(pdev, mem);
2743err_master:
2744 pci_clear_master(pdev);
2745err_region:
2746 pci_release_region(pdev, BAR_NUM);
2747err_device:
2748 pci_disable_device(pdev);
2749err_ar:
5e3dd157
KV		 2750 ath10k_core_destroy(ar);
2751err_ar_pci:
2752 /* call HIF PCI free here */
2753 kfree(ar_pci);
2754
2755 return ret;
2756}
2757
2758static void ath10k_pci_remove(struct pci_dev *pdev)
2759{
2760 struct ath10k *ar = pci_get_drvdata(pdev);
2761 struct ath10k_pci *ar_pci;
2762
50f87a67 2763 ath10k_dbg(ATH10K_DBG_PCI, "pci remove\n");
5e3dd157
KV		 2764
2765 if (!ar)
2766 return;
2767
2768 ar_pci = ath10k_pci_priv(ar);
2769
2770 if (!ar_pci)
2771 return;
2772
2773 tasklet_kill(&ar_pci->msi_fw_err);
2774
2775 ath10k_core_unregister(ar);
25d0dbcb 2776 ath10k_pci_free_ce(ar);
5e3dd157 2777
5e3dd157
KV		 2778 pci_iounmap(pdev, ar_pci->mem);
2779 pci_release_region(pdev, BAR_NUM);
2780 pci_clear_master(pdev);
2781 pci_disable_device(pdev);
2782
2783 ath10k_core_destroy(ar);
2784 kfree(ar_pci);
2785}
2786
5e3dd157
KV		 2787MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2788
2789static struct pci_driver ath10k_pci_driver = {
2790 .name = "ath10k_pci",
2791 .id_table = ath10k_pci_id_table,
2792 .probe = ath10k_pci_probe,
2793 .remove = ath10k_pci_remove,
5e3dd157
KV		 2794};
2795
2796static int __init ath10k_pci_init(void)
2797{
2798 int ret;
2799
2800 ret = pci_register_driver(&ath10k_pci_driver);
2801 if (ret)
1d2b48d6 2802 ath10k_err("failed to register PCI driver: %d\n", ret);
5e3dd157
KV		 2803
2804 return ret;
2805}
2806module_init(ath10k_pci_init);
2807
2808static void __exit ath10k_pci_exit(void)
2809{
2810 pci_unregister_driver(&ath10k_pci_driver);
2811}
2812
2813module_exit(ath10k_pci_exit);
2814
2815MODULE_AUTHOR("Qualcomm Atheros");
2816MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2817MODULE_LICENSE("Dual BSD/GPL");
929417cf 2818MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_2_FILE);
5e3dd157 2819MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
Linux kernel - Deliverables
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