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ath10k: remove target soc ps code
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / pci.c
CommitLineData
5e3dd157
KV		 1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/pci.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
650b91fb 22#include <linux/bitops.h>
5e3dd157
KV		 23
24#include "core.h"
25#include "debug.h"
26
27#include "targaddrs.h"
28#include "bmi.h"
29
30#include "hif.h"
31#include "htc.h"
32
33#include "ce.h"
34#include "pci.h"
35
cfe9c45b
MK		 36enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
40};
41
35098463
KV		 42enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
45};
46
cfe9c45b 47static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
35098463 48static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
cfe9c45b 49
cfe9c45b
MK		 50module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
51MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
52
35098463
KV		 53module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
54MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
55
0399eca8
KV		 56/* how long wait to wait for target to initialise, in ms */
57#define ATH10K_PCI_TARGET_WAIT 3000
61c95cea 58#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
0399eca8 59
5e3dd157
KV		 60#define QCA988X_2_0_DEVICE_ID (0x003c)
61
62static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
5e3dd157
KV		 63 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
64 {0}
65};
66
67static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
68 u32 *data);
69
5e3dd157 70static int ath10k_pci_post_rx(struct ath10k *ar);
87263e5b 71static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
5e3dd157 72 int num);
87263e5b 73static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
fc36e3ff
MK		 74static int ath10k_pci_cold_reset(struct ath10k *ar);
75static int ath10k_pci_warm_reset(struct ath10k *ar);
d7fb47f5 76static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
fc15ca13
MK		 77static int ath10k_pci_init_irq(struct ath10k *ar);
78static int ath10k_pci_deinit_irq(struct ath10k *ar);
79static int ath10k_pci_request_irq(struct ath10k *ar);
80static void ath10k_pci_free_irq(struct ath10k *ar);
85622cde
MK		 81static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
82 struct ath10k_ce_pipe *rx_pipe,
83 struct bmi_xfer *xfer);
5e3dd157
KV		 84
85static const struct ce_attr host_ce_config_wlan[] = {
48e9c225
KV		 86 /* CE0: host->target HTC control and raw streams */
87 {
88 .flags = CE_ATTR_FLAGS,
89 .src_nentries = 16,
90 .src_sz_max = 256,
91 .dest_nentries = 0,
92 },
93
94 /* CE1: target->host HTT + HTC control */
95 {
96 .flags = CE_ATTR_FLAGS,
97 .src_nentries = 0,
98 .src_sz_max = 512,
99 .dest_nentries = 512,
100 },
101
102 /* CE2: target->host WMI */
103 {
104 .flags = CE_ATTR_FLAGS,
105 .src_nentries = 0,
106 .src_sz_max = 2048,
107 .dest_nentries = 32,
108 },
109
110 /* CE3: host->target WMI */
111 {
112 .flags = CE_ATTR_FLAGS,
113 .src_nentries = 32,
114 .src_sz_max = 2048,
115 .dest_nentries = 0,
116 },
117
118 /* CE4: host->target HTT */
119 {
120 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
121 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
122 .src_sz_max = 256,
123 .dest_nentries = 0,
124 },
125
126 /* CE5: unused */
127 {
128 .flags = CE_ATTR_FLAGS,
129 .src_nentries = 0,
130 .src_sz_max = 0,
131 .dest_nentries = 0,
132 },
133
134 /* CE6: target autonomous hif_memcpy */
135 {
136 .flags = CE_ATTR_FLAGS,
137 .src_nentries = 0,
138 .src_sz_max = 0,
139 .dest_nentries = 0,
140 },
141
142 /* CE7: ce_diag, the Diagnostic Window */
143 {
144 .flags = CE_ATTR_FLAGS,
145 .src_nentries = 2,
146 .src_sz_max = DIAG_TRANSFER_LIMIT,
147 .dest_nentries = 2,
148 },
5e3dd157
KV		 149};
150
151/* Target firmware's Copy Engine configuration. */
152static const struct ce_pipe_config target_ce_config_wlan[] = {
d88effba
KV		 153 /* CE0: host->target HTC control and raw streams */
154 {
155 .pipenum = 0,
156 .pipedir = PIPEDIR_OUT,
157 .nentries = 32,
158 .nbytes_max = 256,
159 .flags = CE_ATTR_FLAGS,
160 .reserved = 0,
161 },
162
163 /* CE1: target->host HTT + HTC control */
164 {
165 .pipenum = 1,
166 .pipedir = PIPEDIR_IN,
167 .nentries = 32,
168 .nbytes_max = 512,
169 .flags = CE_ATTR_FLAGS,
170 .reserved = 0,
171 },
172
173 /* CE2: target->host WMI */
174 {
175 .pipenum = 2,
176 .pipedir = PIPEDIR_IN,
177 .nentries = 32,
178 .nbytes_max = 2048,
179 .flags = CE_ATTR_FLAGS,
180 .reserved = 0,
181 },
182
183 /* CE3: host->target WMI */
184 {
185 .pipenum = 3,
186 .pipedir = PIPEDIR_OUT,
187 .nentries = 32,
188 .nbytes_max = 2048,
189 .flags = CE_ATTR_FLAGS,
190 .reserved = 0,
191 },
192
193 /* CE4: host->target HTT */
194 {
195 .pipenum = 4,
196 .pipedir = PIPEDIR_OUT,
197 .nentries = 256,
198 .nbytes_max = 256,
199 .flags = CE_ATTR_FLAGS,
200 .reserved = 0,
201 },
202
5e3dd157 203 /* NB: 50% of src nentries, since tx has 2 frags */
d88effba
KV		 204
205 /* CE5: unused */
206 {
207 .pipenum = 5,
208 .pipedir = PIPEDIR_OUT,
209 .nentries = 32,
210 .nbytes_max = 2048,
211 .flags = CE_ATTR_FLAGS,
212 .reserved = 0,
213 },
214
215 /* CE6: Reserved for target autonomous hif_memcpy */
216 {
217 .pipenum = 6,
218 .pipedir = PIPEDIR_INOUT,
219 .nentries = 32,
220 .nbytes_max = 4096,
221 .flags = CE_ATTR_FLAGS,
222 .reserved = 0,
223 },
224
5e3dd157
KV		 225 /* CE7 used only by Host */
226};
227
e539887b
MK		 228static bool ath10k_pci_irq_pending(struct ath10k *ar)
229{
230 u32 cause;
231
232 /* Check if the shared legacy irq is for us */
233 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
234 PCIE_INTR_CAUSE_ADDRESS);
235 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
236 return true;
237
238 return false;
239}
240
2685218b
MK		 241static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
242{
243 /* IMPORTANT: INTR_CLR register has to be set after
244 * INTR_ENABLE is set to 0, otherwise interrupt can not be
245 * really cleared. */
246 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
247 0);
248 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
249 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
250
251 /* IMPORTANT: this extra read transaction is required to
252 * flush the posted write buffer. */
253 (void) ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
254 PCIE_INTR_ENABLE_ADDRESS);
255}
256
257static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
258{
259 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
260 PCIE_INTR_ENABLE_ADDRESS,
261 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
262
263 /* IMPORTANT: this extra read transaction is required to
264 * flush the posted write buffer. */
265 (void) ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
266 PCIE_INTR_ENABLE_ADDRESS);
267}
268
ab977bd0
MK		 269static irqreturn_t ath10k_pci_early_irq_handler(int irq, void *arg)
270{
271 struct ath10k *ar = arg;
272 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
273
274 if (ar_pci->num_msi_intrs == 0) {
275 if (!ath10k_pci_irq_pending(ar))
276 return IRQ_NONE;
277
278 ath10k_pci_disable_and_clear_legacy_irq(ar);
279 }
280
281 tasklet_schedule(&ar_pci->early_irq_tasklet);
282
283 return IRQ_HANDLED;
284}
285
286static int ath10k_pci_request_early_irq(struct ath10k *ar)
287{
288 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
289 int ret;
290
291 /* Regardless whether MSI-X/MSI/legacy irqs have been set up the first
292 * interrupt from irq vector is triggered in all cases for FW
293 * indication/errors */
294 ret = request_irq(ar_pci->pdev->irq, ath10k_pci_early_irq_handler,
295 IRQF_SHARED, "ath10k_pci (early)", ar);
296 if (ret) {
297 ath10k_warn("failed to request early irq: %d\n", ret);
298 return ret;
299 }
300
301 return 0;
302}
303
304static void ath10k_pci_free_early_irq(struct ath10k *ar)
305{
306 free_irq(ath10k_pci_priv(ar)->pdev->irq, ar);
307}
308
5e3dd157
KV		 309/*
310 * Diagnostic read/write access is provided for startup/config/debug usage.
311 * Caller must guarantee proper alignment, when applicable, and single user
312 * at any moment.
313 */
314static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
315 int nbytes)
316{
317 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
318 int ret = 0;
319 u32 buf;
320 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
321 unsigned int id;
322 unsigned int flags;
2aa39115 323 struct ath10k_ce_pipe *ce_diag;
5e3dd157
KV		 324 /* Host buffer address in CE space */
325 u32 ce_data;
326 dma_addr_t ce_data_base = 0;
327 void *data_buf = NULL;
328 int i;
329
330 /*
331 * This code cannot handle reads to non-memory space. Redirect to the
332 * register read fn but preserve the multi word read capability of
333 * this fn
334 */
335 if (address < DRAM_BASE_ADDRESS) {
336 if (!IS_ALIGNED(address, 4) ||
337 !IS_ALIGNED((unsigned long)data, 4))
338 return -EIO;
339
340 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
341 ar, address, (u32 *)data)) == 0)) {
342 nbytes -= sizeof(u32);
343 address += sizeof(u32);
344 data += sizeof(u32);
345 }
346 return ret;
347 }
348
349 ce_diag = ar_pci->ce_diag;
350
351 /*
352 * Allocate a temporary bounce buffer to hold caller's data
353 * to be DMA'ed from Target. This guarantees
354 * 1) 4-byte alignment
355 * 2) Buffer in DMA-able space
356 */
357 orig_nbytes = nbytes;
68c03249
MK		 358 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
359 orig_nbytes,
360 &ce_data_base,
361 GFP_ATOMIC);
5e3dd157
KV		 362
363 if (!data_buf) {
364 ret = -ENOMEM;
365 goto done;
366 }
367 memset(data_buf, 0, orig_nbytes);
368
369 remaining_bytes = orig_nbytes;
370 ce_data = ce_data_base;
371 while (remaining_bytes) {
372 nbytes = min_t(unsigned int, remaining_bytes,
373 DIAG_TRANSFER_LIMIT);
374
375 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
376 if (ret != 0)
377 goto done;
378
379 /* Request CE to send from Target(!) address to Host buffer */
380 /*
381 * The address supplied by the caller is in the
382 * Target CPU virtual address space.
383 *
384 * In order to use this address with the diagnostic CE,
385 * convert it from Target CPU virtual address space
386 * to CE address space
387 */
5e3dd157
KV		 388 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
389 address);
5e3dd157
KV		 390
391 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
392 0);
393 if (ret)
394 goto done;
395
396 i = 0;
397 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
398 &completed_nbytes,
399 &id) != 0) {
400 mdelay(1);
401 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
402 ret = -EBUSY;
403 goto done;
404 }
405 }
406
407 if (nbytes != completed_nbytes) {
408 ret = -EIO;
409 goto done;
410 }
411
412 if (buf != (u32) address) {
413 ret = -EIO;
414 goto done;
415 }
416
417 i = 0;
418 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
419 &completed_nbytes,
420 &id, &flags) != 0) {
421 mdelay(1);
422
423 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
424 ret = -EBUSY;
425 goto done;
426 }
427 }
428
429 if (nbytes != completed_nbytes) {
430 ret = -EIO;
431 goto done;
432 }
433
434 if (buf != ce_data) {
435 ret = -EIO;
436 goto done;
437 }
438
439 remaining_bytes -= nbytes;
440 address += nbytes;
441 ce_data += nbytes;
442 }
443
444done:
445 if (ret == 0) {
446 /* Copy data from allocated DMA buf to caller's buf */
447 WARN_ON_ONCE(orig_nbytes & 3);
448 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
449 ((u32 *)data)[i] =
450 __le32_to_cpu(((__le32 *)data_buf)[i]);
451 }
452 } else
50f87a67
KV		 453 ath10k_warn("failed to read diag value at 0x%x: %d\n",
454 address, ret);
5e3dd157
KV		 455
456 if (data_buf)
68c03249
MK		 457 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
458 ce_data_base);
5e3dd157
KV		 459
460 return ret;
461}
462
463/* Read 4-byte aligned data from Target memory or register */
464static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
465 u32 *data)
466{
467 /* Assume range doesn't cross this boundary */
468 if (address >= DRAM_BASE_ADDRESS)
469 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
470
5e3dd157 471 *data = ath10k_pci_read32(ar, address);
5e3dd157
KV		 472 return 0;
473}
474
475static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
476 const void *data, int nbytes)
477{
478 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
479 int ret = 0;
480 u32 buf;
481 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
482 unsigned int id;
483 unsigned int flags;
2aa39115 484 struct ath10k_ce_pipe *ce_diag;
5e3dd157
KV		 485 void *data_buf = NULL;
486 u32 ce_data; /* Host buffer address in CE space */
487 dma_addr_t ce_data_base = 0;
488 int i;
489
490 ce_diag = ar_pci->ce_diag;
491
492 /*
493 * Allocate a temporary bounce buffer to hold caller's data
494 * to be DMA'ed to Target. This guarantees
495 * 1) 4-byte alignment
496 * 2) Buffer in DMA-able space
497 */
498 orig_nbytes = nbytes;
68c03249
MK		 499 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
500 orig_nbytes,
501 &ce_data_base,
502 GFP_ATOMIC);
5e3dd157
KV		 503 if (!data_buf) {
504 ret = -ENOMEM;
505 goto done;
506 }
507
508 /* Copy caller's data to allocated DMA buf */
509 WARN_ON_ONCE(orig_nbytes & 3);
510 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
511 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
512
513 /*
514 * The address supplied by the caller is in the
515 * Target CPU virtual address space.
516 *
517 * In order to use this address with the diagnostic CE,
518 * convert it from
519 * Target CPU virtual address space
520 * to
521 * CE address space
522 */
5e3dd157 523 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
5e3dd157
KV		 524
525 remaining_bytes = orig_nbytes;
526 ce_data = ce_data_base;
527 while (remaining_bytes) {
528 /* FIXME: check cast */
529 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
530
531 /* Set up to receive directly into Target(!) address */
532 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
533 if (ret != 0)
534 goto done;
535
536 /*
537 * Request CE to send caller-supplied data that
538 * was copied to bounce buffer to Target(!) address.
539 */
540 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
541 nbytes, 0, 0);
542 if (ret != 0)
543 goto done;
544
545 i = 0;
546 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
547 &completed_nbytes,
548 &id) != 0) {
549 mdelay(1);
550
551 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
552 ret = -EBUSY;
553 goto done;
554 }
555 }
556
557 if (nbytes != completed_nbytes) {
558 ret = -EIO;
559 goto done;
560 }
561
562 if (buf != ce_data) {
563 ret = -EIO;
564 goto done;
565 }
566
567 i = 0;
568 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
569 &completed_nbytes,
570 &id, &flags) != 0) {
571 mdelay(1);
572
573 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
574 ret = -EBUSY;
575 goto done;
576 }
577 }
578
579 if (nbytes != completed_nbytes) {
580 ret = -EIO;
581 goto done;
582 }
583
584 if (buf != address) {
585 ret = -EIO;
586 goto done;
587 }
588
589 remaining_bytes -= nbytes;
590 address += nbytes;
591 ce_data += nbytes;
592 }
593
594done:
595 if (data_buf) {
68c03249
MK		 596 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
597 ce_data_base);
5e3dd157
KV		 598 }
599
600 if (ret != 0)
50f87a67
KV		 601 ath10k_warn("failed to write diag value at 0x%x: %d\n",
602 address, ret);
5e3dd157
KV		 603
604 return ret;
605}
606
607/* Write 4B data to Target memory or register */
608static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
609 u32 data)
610{
611 /* Assume range doesn't cross this boundary */
612 if (address >= DRAM_BASE_ADDRESS)
613 return ath10k_pci_diag_write_mem(ar, address, &data,
614 sizeof(u32));
615
5e3dd157 616 ath10k_pci_write32(ar, address, data);
5e3dd157
KV		 617 return 0;
618}
619
c0c378f9 620static bool ath10k_pci_is_awake(struct ath10k *ar)
5e3dd157 621{
c0c378f9
MK		 622 u32 val = ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS);
623
624 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
5e3dd157
KV		 625}
626
c0c378f9 627static int ath10k_pci_wake_wait(struct ath10k *ar)
5e3dd157 628{
5e3dd157
KV		 629 int tot_delay = 0;
630 int curr_delay = 5;
631
c0c378f9
MK		 632 while (tot_delay < PCIE_WAKE_TIMEOUT) {
633 if (ath10k_pci_is_awake(ar))
3aebe54b 634 return 0;
5e3dd157
KV		 635
636 udelay(curr_delay);
637 tot_delay += curr_delay;
638
639 if (curr_delay < 50)
640 curr_delay += 5;
641 }
c0c378f9
MK		 642
643 return -ETIMEDOUT;
5e3dd157
KV		 644}
645
c0c378f9 646static int ath10k_pci_wake(struct ath10k *ar)
5e3dd157 647{
c0c378f9
MK		 648 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
649 PCIE_SOC_WAKE_V_MASK);
650 return ath10k_pci_wake_wait(ar);
651}
5e3dd157 652
c0c378f9
MK		 653static void ath10k_pci_sleep(struct ath10k *ar)
654{
655 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
656 PCIE_SOC_WAKE_RESET);
5e3dd157
KV		 657}
658
5e3dd157 659/* Called by lower (CE) layer when a send to Target completes. */
5440ce25 660static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
5e3dd157
KV		 661{
662 struct ath10k *ar = ce_state->ar;
663 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2f5280da 664 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
5440ce25
MK		 665 void *transfer_context;
666 u32 ce_data;
667 unsigned int nbytes;
668 unsigned int transfer_id;
5e3dd157 669
5440ce25
MK		 670 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
671 &ce_data, &nbytes,
672 &transfer_id) == 0) {
a16942e6 673 /* no need to call tx completion for NULL pointers */
726346fc
MK		 674 if (transfer_context == NULL)
675 continue;
676
2f5280da 677 cb->tx_completion(ar, transfer_context, transfer_id);
5440ce25 678 }
5e3dd157
KV		 679}
680
681/* Called by lower (CE) layer when data is received from the Target. */
5440ce25 682static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
5e3dd157
KV		 683{
684 struct ath10k *ar = ce_state->ar;
685 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 686 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
2f5280da 687 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
5e3dd157 688 struct sk_buff *skb;
5440ce25
MK		 689 void *transfer_context;
690 u32 ce_data;
2f5280da 691 unsigned int nbytes, max_nbytes;
5440ce25
MK		 692 unsigned int transfer_id;
693 unsigned int flags;
c29a380e 694 int err, num_replenish = 0;
5e3dd157 695
5440ce25
MK		 696 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
697 &ce_data, &nbytes, &transfer_id,
698 &flags) == 0) {
c29a380e 699 num_replenish++;
5e3dd157 700 skb = transfer_context;
2f5280da 701 max_nbytes = skb->len + skb_tailroom(skb);
5e3dd157 702 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
2f5280da
MK		 703 max_nbytes, DMA_FROM_DEVICE);
704
705 if (unlikely(max_nbytes < nbytes)) {
706 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
707 nbytes, max_nbytes);
708 dev_kfree_skb_any(skb);
709 continue;
710 }
5e3dd157 711
2f5280da
MK		 712 skb_put(skb, nbytes);
713 cb->rx_completion(ar, skb, pipe_info->pipe_num);
714 }
c29a380e
MK		 715
716 err = ath10k_pci_post_rx_pipe(pipe_info, num_replenish);
717 if (unlikely(err)) {
718 /* FIXME: retry */
719 ath10k_warn("failed to replenish CE rx ring %d (%d bufs): %d\n",
720 pipe_info->pipe_num, num_replenish, err);
721 }
5e3dd157
KV		 722}
723
726346fc
MK		 724static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
725 struct ath10k_hif_sg_item *items, int n_items)
5e3dd157 726{
5e3dd157 727 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
726346fc
MK		 728 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
729 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
730 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
7147a131
MK		 731 unsigned int nentries_mask;
732 unsigned int sw_index;
733 unsigned int write_index;
08b8aa09 734 int err, i = 0;
5e3dd157 735
726346fc 736 spin_lock_bh(&ar_pci->ce_lock);
5e3dd157 737
7147a131
MK		 738 nentries_mask = src_ring->nentries_mask;
739 sw_index = src_ring->sw_index;
740 write_index = src_ring->write_index;
741
726346fc
MK		 742 if (unlikely(CE_RING_DELTA(nentries_mask,
743 write_index, sw_index - 1) < n_items)) {
744 err = -ENOBUFS;
08b8aa09 745 goto err;
726346fc 746 }
5e3dd157 747
726346fc
MK		 748 for (i = 0; i < n_items - 1; i++) {
749 ath10k_dbg(ATH10K_DBG_PCI,
750 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
751 i, items[i].paddr, items[i].len, n_items);
752 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ",
753 items[i].vaddr, items[i].len);
5e3dd157 754
726346fc
MK		 755 err = ath10k_ce_send_nolock(ce_pipe,
756 items[i].transfer_context,
757 items[i].paddr,
758 items[i].len,
759 items[i].transfer_id,
760 CE_SEND_FLAG_GATHER);
761 if (err)
08b8aa09 762 goto err;
726346fc
MK		 763 }
764
765 /* `i` is equal to `n_items -1` after for() */
766
767 ath10k_dbg(ATH10K_DBG_PCI,
768 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
769 i, items[i].paddr, items[i].len, n_items);
770 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ",
771 items[i].vaddr, items[i].len);
772
773 err = ath10k_ce_send_nolock(ce_pipe,
774 items[i].transfer_context,
775 items[i].paddr,
776 items[i].len,
777 items[i].transfer_id,
778 0);
779 if (err)
08b8aa09
MK		 780 goto err;
781
782 spin_unlock_bh(&ar_pci->ce_lock);
783 return 0;
784
785err:
786 for (; i > 0; i--)
787 __ath10k_ce_send_revert(ce_pipe);
726346fc 788
726346fc
MK		 789 spin_unlock_bh(&ar_pci->ce_lock);
790 return err;
5e3dd157
KV		 791}
792
793static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
794{
795 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
50f87a67
KV		 796
797 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get free queue number\n");
798
3efcb3b4 799 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
5e3dd157
KV		 800}
801
802static void ath10k_pci_hif_dump_area(struct ath10k *ar)
803{
804 u32 reg_dump_area = 0;
805 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
806 u32 host_addr;
807 int ret;
808 u32 i;
809
810 ath10k_err("firmware crashed!\n");
811 ath10k_err("hardware name %s version 0x%x\n",
812 ar->hw_params.name, ar->target_version);
5ba88b39 813 ath10k_err("firmware version: %s\n", ar->hw->wiphy->fw_version);
5e3dd157
KV		 814
815 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
1d2b48d6
MK		 816 ret = ath10k_pci_diag_read_mem(ar, host_addr,
817 &reg_dump_area, sizeof(u32));
818 if (ret) {
819 ath10k_err("failed to read FW dump area address: %d\n", ret);
5e3dd157
KV		 820 return;
821 }
822
823 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
824
825 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
826 &reg_dump_values[0],
827 REG_DUMP_COUNT_QCA988X * sizeof(u32));
828 if (ret != 0) {
1d2b48d6 829 ath10k_err("failed to read FW dump area: %d\n", ret);
5e3dd157
KV		 830 return;
831 }
832
833 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
834
835 ath10k_err("target Register Dump\n");
836 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
837 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
838 i,
839 reg_dump_values[i],
840 reg_dump_values[i + 1],
841 reg_dump_values[i + 2],
842 reg_dump_values[i + 3]);
affd3217 843
5e90de86 844 queue_work(ar->workqueue, &ar->restart_work);
5e3dd157
KV		 845}
846
847static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
848 int force)
849{
50f87a67
KV		 850 ath10k_dbg(ATH10K_DBG_PCI, "pci hif send complete check\n");
851
5e3dd157
KV		 852 if (!force) {
853 int resources;
854 /*
855 * Decide whether to actually poll for completions, or just
856 * wait for a later chance.
857 * If there seem to be plenty of resources left, then just wait
858 * since checking involves reading a CE register, which is a
859 * relatively expensive operation.
860 */
861 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
862
863 /*
864 * If at least 50% of the total resources are still available,
865 * don't bother checking again yet.
866 */
867 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
868 return;
869 }
870 ath10k_ce_per_engine_service(ar, pipe);
871}
872
e799bbff
MK		 873static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
874 struct ath10k_hif_cb *callbacks)
5e3dd157
KV		 875{
876 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
877
50f87a67 878 ath10k_dbg(ATH10K_DBG_PCI, "pci hif set callbacks\n");
5e3dd157
KV		 879
880 memcpy(&ar_pci->msg_callbacks_current, callbacks,
881 sizeof(ar_pci->msg_callbacks_current));
882}
883
c80de12b 884static int ath10k_pci_setup_ce_irq(struct ath10k *ar)
5e3dd157
KV		 885{
886 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
c80de12b
MK		 887 const struct ce_attr *attr;
888 struct ath10k_pci_pipe *pipe_info;
889 int pipe_num, disable_interrupts;
5e3dd157 890
c80de12b
MK		 891 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
892 pipe_info = &ar_pci->pipe_info[pipe_num];
893
894 /* Handle Diagnostic CE specially */
895 if (pipe_info->ce_hdl == ar_pci->ce_diag)
896 continue;
897
898 attr = &host_ce_config_wlan[pipe_num];
899
900 if (attr->src_nentries) {
901 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
902 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
903 ath10k_pci_ce_send_done,
904 disable_interrupts);
905 }
906
907 if (attr->dest_nentries)
908 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
909 ath10k_pci_ce_recv_data);
910 }
911
912 return 0;
913}
914
96a9d0dc 915static void ath10k_pci_kill_tasklet(struct ath10k *ar)
5e3dd157
KV		 916{
917 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 918 int i;
5e3dd157 919
5e3dd157 920 tasklet_kill(&ar_pci->intr_tq);
103d4f5e 921 tasklet_kill(&ar_pci->msi_fw_err);
ab977bd0 922 tasklet_kill(&ar_pci->early_irq_tasklet);
5e3dd157
KV		 923
924 for (i = 0; i < CE_COUNT; i++)
925 tasklet_kill(&ar_pci->pipe_info[i].intr);
96a9d0dc
MK		 926}
927
5e3dd157
KV		 928/* TODO - temporary mapping while we have too few CE's */
929static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
930 u16 service_id, u8 *ul_pipe,
931 u8 *dl_pipe, int *ul_is_polled,
932 int *dl_is_polled)
933{
934 int ret = 0;
935
50f87a67
KV		 936 ath10k_dbg(ATH10K_DBG_PCI, "pci hif map service\n");
937
5e3dd157
KV		 938 /* polling for received messages not supported */
939 *dl_is_polled = 0;
940
941 switch (service_id) {
942 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
943 /*
944 * Host->target HTT gets its own pipe, so it can be polled
945 * while other pipes are interrupt driven.
946 */
947 *ul_pipe = 4;
948 /*
949 * Use the same target->host pipe for HTC ctrl, HTC raw
950 * streams, and HTT.
951 */
952 *dl_pipe = 1;
953 break;
954
955 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
956 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
957 /*
958 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
959 * HTC_CTRL_RSVD_SVC could share the same pipe as the
960 * WMI services. So, if another CE is needed, change
961 * this to *ul_pipe = 3, which frees up CE 0.
962 */
963 /* *ul_pipe = 3; */
964 *ul_pipe = 0;
965 *dl_pipe = 1;
966 break;
967
968 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
969 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
970 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
971 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
972
973 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
974 *ul_pipe = 3;
975 *dl_pipe = 2;
976 break;
977
978 /* pipe 5 unused */
979 /* pipe 6 reserved */
980 /* pipe 7 reserved */
981
982 default:
983 ret = -1;
984 break;
985 }
986 *ul_is_polled =
987 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
988
989 return ret;
990}
991
992static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
993 u8 *ul_pipe, u8 *dl_pipe)
994{
995 int ul_is_polled, dl_is_polled;
996
50f87a67
KV		 997 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get default pipe\n");
998
5e3dd157
KV		 999 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1000 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1001 ul_pipe,
1002 dl_pipe,
1003 &ul_is_polled,
1004 &dl_is_polled);
1005}
1006
87263e5b 1007static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
5e3dd157
KV		 1008 int num)
1009{
1010 struct ath10k *ar = pipe_info->hif_ce_state;
1011 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115 1012 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
5e3dd157
KV		 1013 struct sk_buff *skb;
1014 dma_addr_t ce_data;
1015 int i, ret = 0;
1016
1017 if (pipe_info->buf_sz == 0)
1018 return 0;
1019
1020 for (i = 0; i < num; i++) {
1021 skb = dev_alloc_skb(pipe_info->buf_sz);
1022 if (!skb) {
1d2b48d6 1023 ath10k_warn("failed to allocate skbuff for pipe %d\n",
5e3dd157
KV		 1024 num);
1025 ret = -ENOMEM;
1026 goto err;
1027 }
1028
1029 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1030
1031 ce_data = dma_map_single(ar->dev, skb->data,
1032 skb->len + skb_tailroom(skb),
1033 DMA_FROM_DEVICE);
1034
1035 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1d2b48d6 1036 ath10k_warn("failed to DMA map sk_buff\n");
5e3dd157
KV		 1037 dev_kfree_skb_any(skb);
1038 ret = -EIO;
1039 goto err;
1040 }
1041
1042 ATH10K_SKB_CB(skb)->paddr = ce_data;
1043
1044 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1045 pipe_info->buf_sz,
1046 PCI_DMA_FROMDEVICE);
1047
1048 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1049 ce_data);
1050 if (ret) {
1d2b48d6 1051 ath10k_warn("failed to enqueue to pipe %d: %d\n",
5e3dd157
KV		 1052 num, ret);
1053 goto err;
1054 }
1055 }
1056
1057 return ret;
1058
1059err:
1060 ath10k_pci_rx_pipe_cleanup(pipe_info);
1061 return ret;
1062}
1063
1064static int ath10k_pci_post_rx(struct ath10k *ar)
1065{
1066 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1067 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1068 const struct ce_attr *attr;
1069 int pipe_num, ret = 0;
1070
fad6ed78 1071 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157
KV		 1072 pipe_info = &ar_pci->pipe_info[pipe_num];
1073 attr = &host_ce_config_wlan[pipe_num];
1074
1075 if (attr->dest_nentries == 0)
1076 continue;
1077
1078 ret = ath10k_pci_post_rx_pipe(pipe_info,
1079 attr->dest_nentries - 1);
1080 if (ret) {
1d2b48d6
MK		 1081 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1082 pipe_num, ret);
5e3dd157
KV		 1083
1084 for (; pipe_num >= 0; pipe_num--) {
1085 pipe_info = &ar_pci->pipe_info[pipe_num];
1086 ath10k_pci_rx_pipe_cleanup(pipe_info);
1087 }
1088 return ret;
1089 }
1090 }
1091
1092 return 0;
1093}
1094
1095static int ath10k_pci_hif_start(struct ath10k *ar)
1096{
1097 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
ab977bd0 1098 int ret, ret_early;
5e3dd157 1099
50f87a67
KV		 1100 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif start\n");
1101
ab977bd0
MK		 1102 ath10k_pci_free_early_irq(ar);
1103 ath10k_pci_kill_tasklet(ar);
5e3dd157 1104
5d1aa946
MK		 1105 ret = ath10k_pci_request_irq(ar);
1106 if (ret) {
1107 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1108 ret);
2f5280da 1109 goto err_early_irq;
5d1aa946
MK		 1110 }
1111
c80de12b
MK		 1112 ret = ath10k_pci_setup_ce_irq(ar);
1113 if (ret) {
1114 ath10k_warn("failed to setup CE interrupts: %d\n", ret);
5d1aa946 1115 goto err_stop;
5e3dd157
KV		 1116 }
1117
1118 /* Post buffers once to start things off. */
1119 ret = ath10k_pci_post_rx(ar);
1120 if (ret) {
1d2b48d6
MK		 1121 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1122 ret);
5d1aa946 1123 goto err_stop;
5e3dd157
KV		 1124 }
1125
1126 ar_pci->started = 1;
1127 return 0;
c80de12b 1128
5d1aa946
MK		 1129err_stop:
1130 ath10k_ce_disable_interrupts(ar);
1131 ath10k_pci_free_irq(ar);
1132 ath10k_pci_kill_tasklet(ar);
ab977bd0
MK		 1133err_early_irq:
1134 /* Though there should be no interrupts (device was reset)
1135 * power_down() expects the early IRQ to be installed as per the
1136 * driver lifecycle. */
1137 ret_early = ath10k_pci_request_early_irq(ar);
1138 if (ret_early)
1139 ath10k_warn("failed to re-enable early irq: %d\n", ret_early);
1140
c80de12b 1141 return ret;
5e3dd157
KV		 1142}
1143
87263e5b 1144static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 1145{
1146 struct ath10k *ar;
1147 struct ath10k_pci *ar_pci;
2aa39115 1148 struct ath10k_ce_pipe *ce_hdl;
5e3dd157
KV		 1149 u32 buf_sz;
1150 struct sk_buff *netbuf;
1151 u32 ce_data;
1152
1153 buf_sz = pipe_info->buf_sz;
1154
1155 /* Unused Copy Engine */
1156 if (buf_sz == 0)
1157 return;
1158
1159 ar = pipe_info->hif_ce_state;
1160 ar_pci = ath10k_pci_priv(ar);
1161
1162 if (!ar_pci->started)
1163 return;
1164
1165 ce_hdl = pipe_info->ce_hdl;
1166
1167 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1168 &ce_data) == 0) {
1169 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1170 netbuf->len + skb_tailroom(netbuf),
1171 DMA_FROM_DEVICE);
1172 dev_kfree_skb_any(netbuf);
1173 }
1174}
1175
87263e5b 1176static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 1177{
1178 struct ath10k *ar;
1179 struct ath10k_pci *ar_pci;
2aa39115 1180 struct ath10k_ce_pipe *ce_hdl;
5e3dd157
KV		 1181 struct sk_buff *netbuf;
1182 u32 ce_data;
1183 unsigned int nbytes;
1184 unsigned int id;
1185 u32 buf_sz;
1186
1187 buf_sz = pipe_info->buf_sz;
1188
1189 /* Unused Copy Engine */
1190 if (buf_sz == 0)
1191 return;
1192
1193 ar = pipe_info->hif_ce_state;
1194 ar_pci = ath10k_pci_priv(ar);
1195
1196 if (!ar_pci->started)
1197 return;
1198
1199 ce_hdl = pipe_info->ce_hdl;
1200
1201 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1202 &ce_data, &nbytes, &id) == 0) {
a16942e6
MK		 1203 /* no need to call tx completion for NULL pointers */
1204 if (!netbuf)
2415fc16 1205 continue;
2415fc16 1206
e9bb0aa3
KV		 1207 ar_pci->msg_callbacks_current.tx_completion(ar,
1208 netbuf,
1209 id);
5e3dd157
KV		 1210 }
1211}
1212
1213/*
1214 * Cleanup residual buffers for device shutdown:
1215 * buffers that were enqueued for receive
1216 * buffers that were to be sent
1217 * Note: Buffers that had completed but which were
1218 * not yet processed are on a completion queue. They
1219 * are handled when the completion thread shuts down.
1220 */
1221static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1222{
1223 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1224 int pipe_num;
1225
fad6ed78 1226 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
87263e5b 1227 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1228
1229 pipe_info = &ar_pci->pipe_info[pipe_num];
1230 ath10k_pci_rx_pipe_cleanup(pipe_info);
1231 ath10k_pci_tx_pipe_cleanup(pipe_info);
1232 }
1233}
1234
1235static void ath10k_pci_ce_deinit(struct ath10k *ar)
1236{
25d0dbcb 1237 int i;
5e3dd157 1238
25d0dbcb
MK		 1239 for (i = 0; i < CE_COUNT; i++)
1240 ath10k_ce_deinit_pipe(ar, i);
5e3dd157
KV		 1241}
1242
1243static void ath10k_pci_hif_stop(struct ath10k *ar)
1244{
32270b61 1245 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5d1aa946 1246 int ret;
32270b61 1247
50f87a67 1248 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif stop\n");
5e3dd157 1249
f2708bed
MK		 1250 if (WARN_ON(!ar_pci->started))
1251 return;
1252
5d1aa946
MK		 1253 ret = ath10k_ce_disable_interrupts(ar);
1254 if (ret)
1255 ath10k_warn("failed to disable CE interrupts: %d\n", ret);
32270b61 1256
5d1aa946
MK		 1257 ath10k_pci_free_irq(ar);
1258 ath10k_pci_kill_tasklet(ar);
5e3dd157 1259
ab977bd0
MK		 1260 ret = ath10k_pci_request_early_irq(ar);
1261 if (ret)
1262 ath10k_warn("failed to re-enable early irq: %d\n", ret);
1263
5e3dd157
KV		 1264 /* At this point, asynchronous threads are stopped, the target should
1265 * not DMA nor interrupt. We process the leftovers and then free
1266 * everything else up. */
1267
5e3dd157 1268 ath10k_pci_buffer_cleanup(ar);
32270b61 1269
6a42a47e
MK		 1270 /* Make the sure the device won't access any structures on the host by
1271 * resetting it. The device was fed with PCI CE ringbuffer
1272 * configuration during init. If ringbuffers are freed and the device
1273 * were to access them this could lead to memory corruption on the
1274 * host. */
fc36e3ff 1275 ath10k_pci_warm_reset(ar);
6a42a47e 1276
32270b61 1277 ar_pci->started = 0;
5e3dd157
KV		 1278}
1279
1280static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1281 void *req, u32 req_len,
1282 void *resp, u32 *resp_len)
1283{
1284 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115
MK		 1285 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1286 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1287 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1288 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
5e3dd157
KV		 1289 dma_addr_t req_paddr = 0;
1290 dma_addr_t resp_paddr = 0;
1291 struct bmi_xfer xfer = {};
1292 void *treq, *tresp = NULL;
1293 int ret = 0;
1294
85622cde
MK		 1295 might_sleep();
1296
5e3dd157
KV		 1297 if (resp && !resp_len)
1298 return -EINVAL;
1299
1300 if (resp && resp_len && *resp_len == 0)
1301 return -EINVAL;
1302
1303 treq = kmemdup(req, req_len, GFP_KERNEL);
1304 if (!treq)
1305 return -ENOMEM;
1306
1307 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1308 ret = dma_mapping_error(ar->dev, req_paddr);
1309 if (ret)
1310 goto err_dma;
1311
1312 if (resp && resp_len) {
1313 tresp = kzalloc(*resp_len, GFP_KERNEL);
1314 if (!tresp) {
1315 ret = -ENOMEM;
1316 goto err_req;
1317 }
1318
1319 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1320 DMA_FROM_DEVICE);
1321 ret = dma_mapping_error(ar->dev, resp_paddr);
1322 if (ret)
1323 goto err_req;
1324
1325 xfer.wait_for_resp = true;
1326 xfer.resp_len = 0;
1327
1328 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1329 }
1330
5e3dd157
KV		 1331 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1332 if (ret)
1333 goto err_resp;
1334
85622cde
MK		 1335 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1336 if (ret) {
5e3dd157
KV		 1337 u32 unused_buffer;
1338 unsigned int unused_nbytes;
1339 unsigned int unused_id;
1340
5e3dd157
KV		 1341 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1342 &unused_nbytes, &unused_id);
1343 } else {
1344 /* non-zero means we did not time out */
1345 ret = 0;
1346 }
1347
1348err_resp:
1349 if (resp) {
1350 u32 unused_buffer;
1351
1352 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1353 dma_unmap_single(ar->dev, resp_paddr,
1354 *resp_len, DMA_FROM_DEVICE);
1355 }
1356err_req:
1357 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1358
1359 if (ret == 0 && resp_len) {
1360 *resp_len = min(*resp_len, xfer.resp_len);
1361 memcpy(resp, tresp, xfer.resp_len);
1362 }
1363err_dma:
1364 kfree(treq);
1365 kfree(tresp);
1366
1367 return ret;
1368}
1369
5440ce25 1370static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
5e3dd157 1371{
5440ce25
MK		 1372 struct bmi_xfer *xfer;
1373 u32 ce_data;
1374 unsigned int nbytes;
1375 unsigned int transfer_id;
1376
1377 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1378 &nbytes, &transfer_id))
1379 return;
5e3dd157 1380
2374b186 1381 xfer->tx_done = true;
5e3dd157
KV		 1382}
1383
5440ce25 1384static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
5e3dd157 1385{
5440ce25
MK		 1386 struct bmi_xfer *xfer;
1387 u32 ce_data;
1388 unsigned int nbytes;
1389 unsigned int transfer_id;
1390 unsigned int flags;
1391
1392 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1393 &nbytes, &transfer_id, &flags))
1394 return;
5e3dd157
KV		 1395
1396 if (!xfer->wait_for_resp) {
1397 ath10k_warn("unexpected: BMI data received; ignoring\n");
1398 return;
1399 }
1400
1401 xfer->resp_len = nbytes;
2374b186 1402 xfer->rx_done = true;
5e3dd157
KV		 1403}
1404
85622cde
MK		 1405static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1406 struct ath10k_ce_pipe *rx_pipe,
1407 struct bmi_xfer *xfer)
1408{
1409 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1410
1411 while (time_before_eq(jiffies, timeout)) {
1412 ath10k_pci_bmi_send_done(tx_pipe);
1413 ath10k_pci_bmi_recv_data(rx_pipe);
1414
2374b186 1415 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
85622cde
MK		 1416 return 0;
1417
1418 schedule();
1419 }
1420
1421 return -ETIMEDOUT;
1422}
1423
5e3dd157
KV		 1424/*
1425 * Map from service/endpoint to Copy Engine.
1426 * This table is derived from the CE_PCI TABLE, above.
1427 * It is passed to the Target at startup for use by firmware.
1428 */
1429static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1430 {
1431 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1432 PIPEDIR_OUT, /* out = UL = host -> target */
1433 3,
1434 },
1435 {
1436 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1437 PIPEDIR_IN, /* in = DL = target -> host */
1438 2,
1439 },
1440 {
1441 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1442 PIPEDIR_OUT, /* out = UL = host -> target */
1443 3,
1444 },
1445 {
1446 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1447 PIPEDIR_IN, /* in = DL = target -> host */
1448 2,
1449 },
1450 {
1451 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1452 PIPEDIR_OUT, /* out = UL = host -> target */
1453 3,
1454 },
1455 {
1456 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1457 PIPEDIR_IN, /* in = DL = target -> host */
1458 2,
1459 },
1460 {
1461 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1462 PIPEDIR_OUT, /* out = UL = host -> target */
1463 3,
1464 },
1465 {
1466 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1467 PIPEDIR_IN, /* in = DL = target -> host */
1468 2,
1469 },
1470 {
1471 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1472 PIPEDIR_OUT, /* out = UL = host -> target */
1473 3,
1474 },
1475 {
1476 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1477 PIPEDIR_IN, /* in = DL = target -> host */
1478 2,
1479 },
1480 {
1481 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1482 PIPEDIR_OUT, /* out = UL = host -> target */
1483 0, /* could be moved to 3 (share with WMI) */
1484 },
1485 {
1486 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1487 PIPEDIR_IN, /* in = DL = target -> host */
1488 1,
1489 },
1490 {
1491 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1492 PIPEDIR_OUT, /* out = UL = host -> target */
1493 0,
1494 },
1495 {
1496 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1497 PIPEDIR_IN, /* in = DL = target -> host */
1498 1,
1499 },
1500 {
1501 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1502 PIPEDIR_OUT, /* out = UL = host -> target */
1503 4,
1504 },
1505 {
1506 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1507 PIPEDIR_IN, /* in = DL = target -> host */
1508 1,
1509 },
1510
1511 /* (Additions here) */
1512
1513 { /* Must be last */
1514 0,
1515 0,
1516 0,
1517 },
1518};
1519
1520/*
1521 * Send an interrupt to the device to wake up the Target CPU
1522 * so it has an opportunity to notice any changed state.
1523 */
1524static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1525{
1526 int ret;
1527 u32 core_ctrl;
1528
1529 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1530 CORE_CTRL_ADDRESS,
1531 &core_ctrl);
1532 if (ret) {
1d2b48d6 1533 ath10k_warn("failed to read core_ctrl: %d\n", ret);
5e3dd157
KV		 1534 return ret;
1535 }
1536
1537 /* A_INUM_FIRMWARE interrupt to Target CPU */
1538 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1539
1540 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1541 CORE_CTRL_ADDRESS,
1542 core_ctrl);
1d2b48d6
MK		 1543 if (ret) {
1544 ath10k_warn("failed to set target CPU interrupt mask: %d\n",
1545 ret);
1546 return ret;
1547 }
5e3dd157 1548
1d2b48d6 1549 return 0;
5e3dd157
KV		 1550}
1551
1552static int ath10k_pci_init_config(struct ath10k *ar)
1553{
1554 u32 interconnect_targ_addr;
1555 u32 pcie_state_targ_addr = 0;
1556 u32 pipe_cfg_targ_addr = 0;
1557 u32 svc_to_pipe_map = 0;
1558 u32 pcie_config_flags = 0;
1559 u32 ealloc_value;
1560 u32 ealloc_targ_addr;
1561 u32 flag2_value;
1562 u32 flag2_targ_addr;
1563 int ret = 0;
1564
1565 /* Download to Target the CE Config and the service-to-CE map */
1566 interconnect_targ_addr =
1567 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1568
1569 /* Supply Target-side CE configuration */
1570 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1571 &pcie_state_targ_addr);
1572 if (ret != 0) {
1573 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1574 return ret;
1575 }
1576
1577 if (pcie_state_targ_addr == 0) {
1578 ret = -EIO;
1579 ath10k_err("Invalid pcie state addr\n");
1580 return ret;
1581 }
1582
1583 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1584 offsetof(struct pcie_state,
1585 pipe_cfg_addr),
1586 &pipe_cfg_targ_addr);
1587 if (ret != 0) {
1588 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1589 return ret;
1590 }
1591
1592 if (pipe_cfg_targ_addr == 0) {
1593 ret = -EIO;
1594 ath10k_err("Invalid pipe cfg addr\n");
1595 return ret;
1596 }
1597
1598 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1599 target_ce_config_wlan,
1600 sizeof(target_ce_config_wlan));
1601
1602 if (ret != 0) {
1603 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1604 return ret;
1605 }
1606
1607 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1608 offsetof(struct pcie_state,
1609 svc_to_pipe_map),
1610 &svc_to_pipe_map);
1611 if (ret != 0) {
1612 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1613 return ret;
1614 }
1615
1616 if (svc_to_pipe_map == 0) {
1617 ret = -EIO;
1618 ath10k_err("Invalid svc_to_pipe map\n");
1619 return ret;
1620 }
1621
1622 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1623 target_service_to_ce_map_wlan,
1624 sizeof(target_service_to_ce_map_wlan));
1625 if (ret != 0) {
1626 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1627 return ret;
1628 }
1629
1630 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1631 offsetof(struct pcie_state,
1632 config_flags),
1633 &pcie_config_flags);
1634 if (ret != 0) {
1635 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1636 return ret;
1637 }
1638
1639 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1640
1641 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1642 offsetof(struct pcie_state, config_flags),
1643 &pcie_config_flags,
1644 sizeof(pcie_config_flags));
1645 if (ret != 0) {
1646 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1647 return ret;
1648 }
1649
1650 /* configure early allocation */
1651 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1652
1653 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1654 if (ret != 0) {
1655 ath10k_err("Faile to get early alloc val: %d\n", ret);
1656 return ret;
1657 }
1658
1659 /* first bank is switched to IRAM */
1660 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1661 HI_EARLY_ALLOC_MAGIC_MASK);
1662 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1663 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1664
1665 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1666 if (ret != 0) {
1667 ath10k_err("Failed to set early alloc val: %d\n", ret);
1668 return ret;
1669 }
1670
1671 /* Tell Target to proceed with initialization */
1672 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1673
1674 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1675 if (ret != 0) {
1676 ath10k_err("Failed to get option val: %d\n", ret);
1677 return ret;
1678 }
1679
1680 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1681
1682 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1683 if (ret != 0) {
1684 ath10k_err("Failed to set option val: %d\n", ret);
1685 return ret;
1686 }
1687
1688 return 0;
1689}
1690
25d0dbcb
MK		 1691static int ath10k_pci_alloc_ce(struct ath10k *ar)
1692{
1693 int i, ret;
1694
1695 for (i = 0; i < CE_COUNT; i++) {
1696 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1697 if (ret) {
1698 ath10k_err("failed to allocate copy engine pipe %d: %d\n",
1699 i, ret);
1700 return ret;
1701 }
1702 }
1703
1704 return 0;
1705}
1706
1707static void ath10k_pci_free_ce(struct ath10k *ar)
1708{
1709 int i;
5e3dd157 1710
25d0dbcb
MK		 1711 for (i = 0; i < CE_COUNT; i++)
1712 ath10k_ce_free_pipe(ar, i);
1713}
5e3dd157
KV		 1714
1715static int ath10k_pci_ce_init(struct ath10k *ar)
1716{
1717 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1718 struct ath10k_pci_pipe *pipe_info;
5e3dd157 1719 const struct ce_attr *attr;
25d0dbcb 1720 int pipe_num, ret;
5e3dd157 1721
fad6ed78 1722 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157 1723 pipe_info = &ar_pci->pipe_info[pipe_num];
25d0dbcb 1724 pipe_info->ce_hdl = &ar_pci->ce_states[pipe_num];
5e3dd157
KV		 1725 pipe_info->pipe_num = pipe_num;
1726 pipe_info->hif_ce_state = ar;
1727 attr = &host_ce_config_wlan[pipe_num];
1728
25d0dbcb
MK		 1729 ret = ath10k_ce_init_pipe(ar, pipe_num, attr);
1730 if (ret) {
1731 ath10k_err("failed to initialize copy engine pipe %d: %d\n",
1732 pipe_num, ret);
1733 return ret;
5e3dd157
KV		 1734 }
1735
fad6ed78 1736 if (pipe_num == CE_COUNT - 1) {
5e3dd157
KV		 1737 /*
1738 * Reserve the ultimate CE for
1739 * diagnostic Window support
1740 */
fad6ed78 1741 ar_pci->ce_diag = pipe_info->ce_hdl;
5e3dd157
KV		 1742 continue;
1743 }
1744
1745 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1746 }
1747
5e3dd157
KV		 1748 return 0;
1749}
1750
1751static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1752{
1753 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
b39712ce 1754 u32 fw_indicator;
5e3dd157 1755
b39712ce 1756 fw_indicator = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
5e3dd157
KV		 1757
1758 if (fw_indicator & FW_IND_EVENT_PENDING) {
1759 /* ACK: clear Target-side pending event */
b39712ce 1760 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
5e3dd157
KV		 1761 fw_indicator & ~FW_IND_EVENT_PENDING);
1762
1763 if (ar_pci->started) {
1764 ath10k_pci_hif_dump_area(ar);
1765 } else {
1766 /*
1767 * Probable Target failure before we're prepared
1768 * to handle it. Generally unexpected.
1769 */
1770 ath10k_warn("early firmware event indicated\n");
1771 }
1772 }
5e3dd157
KV		 1773}
1774
de01357b
MK		 1775/* this function effectively clears target memory controller assert line */
1776static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
1777{
1778 u32 val;
1779
1780 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1781 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1782 val | SOC_RESET_CONTROL_SI0_RST_MASK);
1783 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1784
1785 msleep(10);
1786
1787 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1788 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1789 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
1790 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1791
1792 msleep(10);
1793}
1794
fc36e3ff
MK		 1795static int ath10k_pci_warm_reset(struct ath10k *ar)
1796{
fc36e3ff
MK		 1797 u32 val;
1798
50f87a67 1799 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset\n");
fc36e3ff 1800
fc36e3ff
MK		 1801 /* debug */
1802 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1803 PCIE_INTR_CAUSE_ADDRESS);
1804 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val);
1805
1806 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1807 CPU_INTR_ADDRESS);
1808 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1809 val);
1810
1811 /* disable pending irqs */
1812 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1813 PCIE_INTR_ENABLE_ADDRESS, 0);
1814
1815 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1816 PCIE_INTR_CLR_ADDRESS, ~0);
1817
1818 msleep(100);
1819
1820 /* clear fw indicator */
b39712ce 1821 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
fc36e3ff
MK		 1822
1823 /* clear target LF timer interrupts */
1824 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1825 SOC_LF_TIMER_CONTROL0_ADDRESS);
1826 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
1827 SOC_LF_TIMER_CONTROL0_ADDRESS,
1828 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
1829
1830 /* reset CE */
1831 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1832 SOC_RESET_CONTROL_ADDRESS);
1833 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1834 val | SOC_RESET_CONTROL_CE_RST_MASK);
1835 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1836 SOC_RESET_CONTROL_ADDRESS);
1837 msleep(10);
1838
1839 /* unreset CE */
1840 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1841 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
1842 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1843 SOC_RESET_CONTROL_ADDRESS);
1844 msleep(10);
1845
de01357b
MK		 1846 ath10k_pci_warm_reset_si0(ar);
1847
fc36e3ff
MK		 1848 /* debug */
1849 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1850 PCIE_INTR_CAUSE_ADDRESS);
1851 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val);
1852
1853 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1854 CPU_INTR_ADDRESS);
1855 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1856 val);
1857
1858 /* CPU warm reset */
1859 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1860 SOC_RESET_CONTROL_ADDRESS);
1861 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1862 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
1863
1864 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1865 SOC_RESET_CONTROL_ADDRESS);
1866 ath10k_dbg(ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n", val);
1867
1868 msleep(100);
1869
1870 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset complete\n");
1871
c0c378f9 1872 return 0;
fc36e3ff
MK		 1873}
1874
1875static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
8c5c5368 1876{
8cc8df90 1877 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
95cbb6a8 1878 const char *irq_mode;
8c5c5368
MK		 1879 int ret;
1880
1881 /*
1882 * Bring the target up cleanly.
1883 *
1884 * The target may be in an undefined state with an AUX-powered Target
1885 * and a Host in WoW mode. If the Host crashes, loses power, or is
1886 * restarted (without unloading the driver) then the Target is left
1887 * (aux) powered and running. On a subsequent driver load, the Target
1888 * is in an unexpected state. We try to catch that here in order to
1889 * reset the Target and retry the probe.
1890 */
fc36e3ff
MK		 1891 if (cold_reset)
1892 ret = ath10k_pci_cold_reset(ar);
1893 else
1894 ret = ath10k_pci_warm_reset(ar);
1895
5b2589fc
MK		 1896 if (ret) {
1897 ath10k_err("failed to reset target: %d\n", ret);
98563d5a 1898 goto err;
5b2589fc 1899 }
8c5c5368 1900
8c5c5368 1901 ret = ath10k_pci_ce_init(ar);
1d2b48d6
MK		 1902 if (ret) {
1903 ath10k_err("failed to initialize CE: %d\n", ret);
c0c378f9 1904 goto err;
1d2b48d6 1905 }
8c5c5368 1906
98563d5a
MK		 1907 ret = ath10k_ce_disable_interrupts(ar);
1908 if (ret) {
1909 ath10k_err("failed to disable CE interrupts: %d\n", ret);
8c5c5368 1910 goto err_ce;
98563d5a 1911 }
8c5c5368 1912
fc15ca13 1913 ret = ath10k_pci_init_irq(ar);
8c5c5368 1914 if (ret) {
fc15ca13 1915 ath10k_err("failed to init irqs: %d\n", ret);
8c5c5368
MK		 1916 goto err_ce;
1917 }
1918
ab977bd0
MK		 1919 ret = ath10k_pci_request_early_irq(ar);
1920 if (ret) {
1921 ath10k_err("failed to request early irq: %d\n", ret);
1922 goto err_deinit_irq;
1923 }
1924
98563d5a
MK		 1925 ret = ath10k_pci_wait_for_target_init(ar);
1926 if (ret) {
1927 ath10k_err("failed to wait for target to init: %d\n", ret);
ab977bd0 1928 goto err_free_early_irq;
98563d5a
MK		 1929 }
1930
1931 ret = ath10k_pci_init_config(ar);
1932 if (ret) {
1933 ath10k_err("failed to setup init config: %d\n", ret);
ab977bd0 1934 goto err_free_early_irq;
98563d5a 1935 }
8c5c5368
MK		 1936
1937 ret = ath10k_pci_wake_target_cpu(ar);
1938 if (ret) {
1d2b48d6 1939 ath10k_err("could not wake up target CPU: %d\n", ret);
ab977bd0 1940 goto err_free_early_irq;
8c5c5368
MK		 1941 }
1942
95cbb6a8
KV		 1943 if (ar_pci->num_msi_intrs > 1)
1944 irq_mode = "MSI-X";
1945 else if (ar_pci->num_msi_intrs == 1)
1946 irq_mode = "MSI";
1947 else
1948 irq_mode = "legacy";
1949
650b91fb 1950 if (!test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
78a9cb4c
KV		 1951 ath10k_info("pci irq %s irq_mode %d reset_mode %d\n",
1952 irq_mode, ath10k_pci_irq_mode,
1953 ath10k_pci_reset_mode);
95cbb6a8 1954
8c5c5368
MK		 1955 return 0;
1956
ab977bd0
MK		 1957err_free_early_irq:
1958 ath10k_pci_free_early_irq(ar);
fc15ca13
MK		 1959err_deinit_irq:
1960 ath10k_pci_deinit_irq(ar);
8c5c5368
MK		 1961err_ce:
1962 ath10k_pci_ce_deinit(ar);
fc36e3ff 1963 ath10k_pci_warm_reset(ar);
8c5c5368
MK		 1964err:
1965 return ret;
1966}
1967
61c95cea
MK		 1968static int ath10k_pci_hif_power_up_warm(struct ath10k *ar)
1969{
1970 int i, ret;
1971
1972 /*
1973 * Sometime warm reset succeeds after retries.
1974 *
1975 * FIXME: It might be possible to tune ath10k_pci_warm_reset() to work
1976 * at first try.
1977 */
1978 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
1979 ret = __ath10k_pci_hif_power_up(ar, false);
1980 if (ret == 0)
1981 break;
1982
1983 ath10k_warn("failed to warm reset (attempt %d out of %d): %d\n",
1984 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, ret);
1985 }
1986
1987 return ret;
1988}
1989
fc36e3ff
MK		 1990static int ath10k_pci_hif_power_up(struct ath10k *ar)
1991{
1992 int ret;
1993
50f87a67
KV		 1994 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power up\n");
1995
fc36e3ff
MK		 1996 /*
1997 * Hardware CUS232 version 2 has some issues with cold reset and the
1998 * preferred (and safer) way to perform a device reset is through a
1999 * warm reset.
2000 *
61c95cea
MK		 2001 * Warm reset doesn't always work though so fall back to cold reset may
2002 * be necessary.
fc36e3ff 2003 */
61c95cea 2004 ret = ath10k_pci_hif_power_up_warm(ar);
fc36e3ff 2005 if (ret) {
35098463 2006 ath10k_warn("failed to power up target using warm reset: %d\n",
fc36e3ff
MK		 2007 ret);
2008
35098463
KV		 2009 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY)
2010 return ret;
2011
2012 ath10k_warn("trying cold reset\n");
2013
fc36e3ff
MK		 2014 ret = __ath10k_pci_hif_power_up(ar, true);
2015 if (ret) {
2016 ath10k_err("failed to power up target using cold reset too (%d)\n",
2017 ret);
2018 return ret;
2019 }
2020 }
2021
2022 return 0;
2023}
2024
8c5c5368
MK		 2025static void ath10k_pci_hif_power_down(struct ath10k *ar)
2026{
50f87a67
KV		 2027 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power down\n");
2028
ab977bd0
MK		 2029 ath10k_pci_free_early_irq(ar);
2030 ath10k_pci_kill_tasklet(ar);
fc15ca13 2031 ath10k_pci_deinit_irq(ar);
df5e8525 2032 ath10k_pci_ce_deinit(ar);
fc36e3ff 2033 ath10k_pci_warm_reset(ar);
8c5c5368
MK		 2034}
2035
8cd13cad
MK		 2036#ifdef CONFIG_PM
2037
2038#define ATH10K_PCI_PM_CONTROL 0x44
2039
2040static int ath10k_pci_hif_suspend(struct ath10k *ar)
2041{
2042 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2043 struct pci_dev *pdev = ar_pci->pdev;
2044 u32 val;
2045
2046 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
2047
2048 if ((val & 0x000000ff) != 0x3) {
2049 pci_save_state(pdev);
2050 pci_disable_device(pdev);
2051 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
2052 (val & 0xffffff00) | 0x03);
2053 }
2054
2055 return 0;
2056}
2057
2058static int ath10k_pci_hif_resume(struct ath10k *ar)
2059{
2060 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2061 struct pci_dev *pdev = ar_pci->pdev;
2062 u32 val;
2063
2064 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
2065
2066 if ((val & 0x000000ff) != 0) {
2067 pci_restore_state(pdev);
2068 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
2069 val & 0xffffff00);
2070 /*
2071 * Suspend/Resume resets the PCI configuration space,
2072 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
2073 * to keep PCI Tx retries from interfering with C3 CPU state
2074 */
2075 pci_read_config_dword(pdev, 0x40, &val);
2076
2077 if ((val & 0x0000ff00) != 0)
2078 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2079 }
2080
2081 return 0;
2082}
2083#endif
2084
5e3dd157 2085static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
726346fc 2086 .tx_sg = ath10k_pci_hif_tx_sg,
5e3dd157
KV		 2087 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2088 .start = ath10k_pci_hif_start,
2089 .stop = ath10k_pci_hif_stop,
2090 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2091 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2092 .send_complete_check = ath10k_pci_hif_send_complete_check,
e799bbff 2093 .set_callbacks = ath10k_pci_hif_set_callbacks,
5e3dd157 2094 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
8c5c5368
MK		 2095 .power_up = ath10k_pci_hif_power_up,
2096 .power_down = ath10k_pci_hif_power_down,
8cd13cad
MK		 2097#ifdef CONFIG_PM
2098 .suspend = ath10k_pci_hif_suspend,
2099 .resume = ath10k_pci_hif_resume,
2100#endif
5e3dd157
KV		 2101};
2102
2103static void ath10k_pci_ce_tasklet(unsigned long ptr)
2104{
87263e5b 2105 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
5e3dd157
KV		 2106 struct ath10k_pci *ar_pci = pipe->ar_pci;
2107
2108 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2109}
2110
2111static void ath10k_msi_err_tasklet(unsigned long data)
2112{
2113 struct ath10k *ar = (struct ath10k *)data;
2114
2115 ath10k_pci_fw_interrupt_handler(ar);
2116}
2117
2118/*
2119 * Handler for a per-engine interrupt on a PARTICULAR CE.
2120 * This is used in cases where each CE has a private MSI interrupt.
2121 */
2122static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2123{
2124 struct ath10k *ar = arg;
2125 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2126 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2127
e5742672 2128 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
5e3dd157
KV		 2129 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
2130 return IRQ_HANDLED;
2131 }
2132
2133 /*
2134 * NOTE: We are able to derive ce_id from irq because we
2135 * use a one-to-one mapping for CE's 0..5.
2136 * CE's 6 & 7 do not use interrupts at all.
2137 *
2138 * This mapping must be kept in sync with the mapping
2139 * used by firmware.
2140 */
2141 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2142 return IRQ_HANDLED;
2143}
2144
2145static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2146{
2147 struct ath10k *ar = arg;
2148 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2149
2150 tasklet_schedule(&ar_pci->msi_fw_err);
2151 return IRQ_HANDLED;
2152}
2153
2154/*
2155 * Top-level interrupt handler for all PCI interrupts from a Target.
2156 * When a block of MSI interrupts is allocated, this top-level handler
2157 * is not used; instead, we directly call the correct sub-handler.
2158 */
2159static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2160{
2161 struct ath10k *ar = arg;
2162 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2163
2164 if (ar_pci->num_msi_intrs == 0) {
e539887b
MK		 2165 if (!ath10k_pci_irq_pending(ar))
2166 return IRQ_NONE;
2167
2685218b 2168 ath10k_pci_disable_and_clear_legacy_irq(ar);
5e3dd157
KV		 2169 }
2170
2171 tasklet_schedule(&ar_pci->intr_tq);
2172
2173 return IRQ_HANDLED;
2174}
2175
ab977bd0
MK		 2176static void ath10k_pci_early_irq_tasklet(unsigned long data)
2177{
2178 struct ath10k *ar = (struct ath10k *)data;
ab977bd0 2179 u32 fw_ind;
ab977bd0 2180
b39712ce 2181 fw_ind = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
ab977bd0 2182 if (fw_ind & FW_IND_EVENT_PENDING) {
b39712ce 2183 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
ab977bd0 2184 fw_ind & ~FW_IND_EVENT_PENDING);
1a4ab28f 2185 ath10k_pci_hif_dump_area(ar);
ab977bd0
MK		 2186 }
2187
ab977bd0
MK		 2188 ath10k_pci_enable_legacy_irq(ar);
2189}
2190
5e3dd157
KV		 2191static void ath10k_pci_tasklet(unsigned long data)
2192{
2193 struct ath10k *ar = (struct ath10k *)data;
2194 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2195
2196 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2197 ath10k_ce_per_engine_service_any(ar);
2198
2685218b
MK		 2199 /* Re-enable legacy irq that was disabled in the irq handler */
2200 if (ar_pci->num_msi_intrs == 0)
2201 ath10k_pci_enable_legacy_irq(ar);
5e3dd157
KV		 2202}
2203
fc15ca13 2204static int ath10k_pci_request_irq_msix(struct ath10k *ar)
5e3dd157
KV		 2205{
2206 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
fc15ca13 2207 int ret, i;
5e3dd157
KV		 2208
2209 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2210 ath10k_pci_msi_fw_handler,
2211 IRQF_SHARED, "ath10k_pci", ar);
591ecdb8 2212 if (ret) {
fc15ca13 2213 ath10k_warn("failed to request MSI-X fw irq %d: %d\n",
591ecdb8 2214 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
5e3dd157 2215 return ret;
591ecdb8 2216 }
5e3dd157
KV		 2217
2218 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2219 ret = request_irq(ar_pci->pdev->irq + i,
2220 ath10k_pci_per_engine_handler,
2221 IRQF_SHARED, "ath10k_pci", ar);
2222 if (ret) {
fc15ca13 2223 ath10k_warn("failed to request MSI-X ce irq %d: %d\n",
5e3dd157
KV		 2224 ar_pci->pdev->irq + i, ret);
2225
87b1423b
MK		 2226 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2227 free_irq(ar_pci->pdev->irq + i, ar);
5e3dd157 2228
87b1423b 2229 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
5e3dd157
KV		 2230 return ret;
2231 }
2232 }
2233
5e3dd157
KV		 2234 return 0;
2235}
2236
fc15ca13 2237static int ath10k_pci_request_irq_msi(struct ath10k *ar)
5e3dd157
KV		 2238{
2239 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2240 int ret;
2241
5e3dd157
KV		 2242 ret = request_irq(ar_pci->pdev->irq,
2243 ath10k_pci_interrupt_handler,
2244 IRQF_SHARED, "ath10k_pci", ar);
fc15ca13
MK		 2245 if (ret) {
2246 ath10k_warn("failed to request MSI irq %d: %d\n",
2247 ar_pci->pdev->irq, ret);
5e3dd157
KV		 2248 return ret;
2249 }
2250
5e3dd157
KV		 2251 return 0;
2252}
2253
fc15ca13 2254static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
5e3dd157
KV		 2255{
2256 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2257 int ret;
2258
2259 ret = request_irq(ar_pci->pdev->irq,
2260 ath10k_pci_interrupt_handler,
2261 IRQF_SHARED, "ath10k_pci", ar);
f3782744 2262 if (ret) {
fc15ca13
MK		 2263 ath10k_warn("failed to request legacy irq %d: %d\n",
2264 ar_pci->pdev->irq, ret);
5e3dd157 2265 return ret;
f3782744 2266 }
5e3dd157 2267
5e3dd157
KV		 2268 return 0;
2269}
2270
fc15ca13
MK		 2271static int ath10k_pci_request_irq(struct ath10k *ar)
2272{
2273 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 2274
fc15ca13
MK		 2275 switch (ar_pci->num_msi_intrs) {
2276 case 0:
2277 return ath10k_pci_request_irq_legacy(ar);
2278 case 1:
2279 return ath10k_pci_request_irq_msi(ar);
2280 case MSI_NUM_REQUEST:
2281 return ath10k_pci_request_irq_msix(ar);
2282 }
5e3dd157 2283
fc15ca13
MK		 2284 ath10k_warn("unknown irq configuration upon request\n");
2285 return -EINVAL;
5e3dd157
KV		 2286}
2287
fc15ca13
MK		 2288static void ath10k_pci_free_irq(struct ath10k *ar)
2289{
2290 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2291 int i;
2292
2293 /* There's at least one interrupt irregardless whether its legacy INTR
2294 * or MSI or MSI-X */
2295 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2296 free_irq(ar_pci->pdev->irq + i, ar);
2297}
2298
2299static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
5e3dd157
KV		 2300{
2301 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157
KV		 2302 int i;
2303
fc15ca13 2304 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
5e3dd157 2305 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
fc15ca13 2306 (unsigned long)ar);
ab977bd0
MK		 2307 tasklet_init(&ar_pci->early_irq_tasklet, ath10k_pci_early_irq_tasklet,
2308 (unsigned long)ar);
5e3dd157
KV		 2309
2310 for (i = 0; i < CE_COUNT; i++) {
2311 ar_pci->pipe_info[i].ar_pci = ar_pci;
fc15ca13 2312 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
5e3dd157
KV		 2313 (unsigned long)&ar_pci->pipe_info[i]);
2314 }
fc15ca13
MK		 2315}
2316
2317static int ath10k_pci_init_irq(struct ath10k *ar)
2318{
2319 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
cfe9c45b
MK		 2320 bool msix_supported = test_bit(ATH10K_PCI_FEATURE_MSI_X,
2321 ar_pci->features);
fc15ca13 2322 int ret;
5e3dd157 2323
fc15ca13 2324 ath10k_pci_init_irq_tasklets(ar);
5e3dd157 2325
cfe9c45b
MK		 2326 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO &&
2327 !test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
2328 ath10k_info("limiting irq mode to: %d\n", ath10k_pci_irq_mode);
5e3dd157 2329
fc15ca13 2330 /* Try MSI-X */
cfe9c45b
MK		 2331 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO && msix_supported) {
2332 ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
5ad6867c
AG		 2333 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2334 ar_pci->num_msi_intrs);
2335 if (ret > 0)
cfe9c45b 2336 return 0;
5e3dd157 2337
cfe9c45b 2338 /* fall-through */
5e3dd157
KV		 2339 }
2340
fc15ca13 2341 /* Try MSI */
cfe9c45b
MK		 2342 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2343 ar_pci->num_msi_intrs = 1;
2344 ret = pci_enable_msi(ar_pci->pdev);
5e3dd157 2345 if (ret == 0)
cfe9c45b 2346 return 0;
5e3dd157 2347
cfe9c45b 2348 /* fall-through */
5e3dd157
KV		 2349 }
2350
fc15ca13
MK		 2351 /* Try legacy irq
2352 *
2353 * A potential race occurs here: The CORE_BASE write
2354 * depends on target correctly decoding AXI address but
2355 * host won't know when target writes BAR to CORE_CTRL.
2356 * This write might get lost if target has NOT written BAR.
2357 * For now, fix the race by repeating the write in below
2358 * synchronization checking. */
2359 ar_pci->num_msi_intrs = 0;
5e3dd157 2360
fc15ca13
MK		 2361 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2362 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
fc15ca13
MK		 2363
2364 return 0;
5e3dd157
KV		 2365}
2366
c0c378f9 2367static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
5e3dd157 2368{
fc15ca13
MK		 2369 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2370 0);
5e3dd157
KV		 2371}
2372
fc15ca13 2373static int ath10k_pci_deinit_irq(struct ath10k *ar)
5e3dd157
KV		 2374{
2375 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 2376
fc15ca13
MK		 2377 switch (ar_pci->num_msi_intrs) {
2378 case 0:
c0c378f9
MK		 2379 ath10k_pci_deinit_irq_legacy(ar);
2380 return 0;
fc15ca13
MK		 2381 case 1:
2382 /* fall-through */
2383 case MSI_NUM_REQUEST:
5e3dd157 2384 pci_disable_msi(ar_pci->pdev);
fc15ca13 2385 return 0;
bb8b621a
AG		 2386 default:
2387 pci_disable_msi(ar_pci->pdev);
fc15ca13
MK		 2388 }
2389
2390 ath10k_warn("unknown irq configuration upon deinit\n");
2391 return -EINVAL;
5e3dd157
KV		 2392}
2393
d7fb47f5 2394static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
5e3dd157
KV		 2395{
2396 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
0399eca8 2397 unsigned long timeout;
0399eca8 2398 u32 val;
5e3dd157 2399
50f87a67
KV		 2400 ath10k_dbg(ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2401
0399eca8
KV		 2402 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2403
2404 do {
2405 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2406
50f87a67
KV		 2407 ath10k_dbg(ATH10K_DBG_BOOT, "boot target indicator %x\n", val);
2408
0399eca8
KV		 2409 /* target should never return this */
2410 if (val == 0xffffffff)
2411 continue;
2412
7710cd2e
MK		 2413 /* the device has crashed so don't bother trying anymore */
2414 if (val & FW_IND_EVENT_PENDING)
2415 break;
2416
0399eca8
KV		 2417 if (val & FW_IND_INITIALIZED)
2418 break;
2419
5e3dd157
KV		 2420 if (ar_pci->num_msi_intrs == 0)
2421 /* Fix potential race by repeating CORE_BASE writes */
0399eca8
KV		 2422 ath10k_pci_soc_write32(ar, PCIE_INTR_ENABLE_ADDRESS,
2423 PCIE_INTR_FIRMWARE_MASK |
2424 PCIE_INTR_CE_MASK_ALL);
2425
5e3dd157 2426 mdelay(10);
0399eca8 2427 } while (time_before(jiffies, timeout));
5e3dd157 2428
6a4f6e1d
MK		 2429 if (val == 0xffffffff) {
2430 ath10k_err("failed to read device register, device is gone\n");
c0c378f9 2431 return -EIO;
6a4f6e1d
MK		 2432 }
2433
7710cd2e
MK		 2434 if (val & FW_IND_EVENT_PENDING) {
2435 ath10k_warn("device has crashed during init\n");
1a4ab28f
MK		 2436 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
2437 val & ~FW_IND_EVENT_PENDING);
2438 ath10k_pci_hif_dump_area(ar);
c0c378f9 2439 return -ECOMM;
7710cd2e
MK		 2440 }
2441
6a4f6e1d 2442 if (!(val & FW_IND_INITIALIZED)) {
0399eca8
KV		 2443 ath10k_err("failed to receive initialized event from target: %08x\n",
2444 val);
c0c378f9 2445 return -ETIMEDOUT;
5e3dd157
KV		 2446 }
2447
50f87a67 2448 ath10k_dbg(ATH10K_DBG_BOOT, "boot target initialised\n");
c0c378f9 2449 return 0;
5e3dd157
KV		 2450}
2451
fc36e3ff 2452static int ath10k_pci_cold_reset(struct ath10k *ar)
5e3dd157 2453{
c0c378f9 2454 int i;
5e3dd157
KV		 2455 u32 val;
2456
50f87a67
KV		 2457 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset\n");
2458
5e3dd157 2459 /* Put Target, including PCIe, into RESET. */
e479ed43 2460 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
5e3dd157 2461 val |= 1;
e479ed43 2462 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
5e3dd157
KV		 2463
2464 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
e479ed43 2465 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
5e3dd157
KV		 2466 RTC_STATE_COLD_RESET_MASK)
2467 break;
2468 msleep(1);
2469 }
2470
2471 /* Pull Target, including PCIe, out of RESET. */
2472 val &= ~1;
e479ed43 2473 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
5e3dd157
KV		 2474
2475 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
e479ed43 2476 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
5e3dd157
KV		 2477 RTC_STATE_COLD_RESET_MASK))
2478 break;
2479 msleep(1);
2480 }
2481
50f87a67
KV		 2482 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset complete\n");
2483
5b2589fc 2484 return 0;
5e3dd157
KV		 2485}
2486
2487static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2488{
2489 int i;
2490
2491 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2492 if (!test_bit(i, ar_pci->features))
2493 continue;
2494
2495 switch (i) {
2496 case ATH10K_PCI_FEATURE_MSI_X:
24cfade1 2497 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
5e3dd157 2498 break;
5e3dd157
KV		 2499 }
2500 }
2501}
2502
2503static int ath10k_pci_probe(struct pci_dev *pdev,
2504 const struct pci_device_id *pci_dev)
2505{
2506 void __iomem *mem;
2507 int ret = 0;
2508 struct ath10k *ar;
2509 struct ath10k_pci *ar_pci;
e01ae68c 2510 u32 lcr_val, chip_id;
5e3dd157 2511
50f87a67 2512 ath10k_dbg(ATH10K_DBG_PCI, "pci probe\n");
5e3dd157 2513
e7b54194
MK		 2514 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev,
2515 &ath10k_pci_hif_ops);
2516 if (!ar) {
2517 ath10k_err("failed to allocate core\n");
5e3dd157 2518 return -ENOMEM;
e7b54194 2519 }
5e3dd157 2520
e7b54194 2521 ar_pci = ath10k_pci_priv(ar);
5e3dd157
KV		 2522 ar_pci->pdev = pdev;
2523 ar_pci->dev = &pdev->dev;
2524
2525 switch (pci_dev->device) {
5e3dd157
KV		 2526 case QCA988X_2_0_DEVICE_ID:
2527 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2528 break;
2529 default:
2530 ret = -ENODEV;
6d3be300 2531 ath10k_err("Unknown device ID: %d\n", pci_dev->device);
e7b54194 2532 goto err_core_destroy;
5e3dd157
KV		 2533 }
2534
2535 ath10k_pci_dump_features(ar_pci);
2536
5e3dd157 2537 ar_pci->ar = ar;
5e3dd157
KV		 2538
2539 pci_set_drvdata(pdev, ar);
2540
5e3dd157
KV		 2541 ret = pci_enable_device(pdev);
2542 if (ret) {
1d2b48d6 2543 ath10k_err("failed to enable PCI device: %d\n", ret);
e7b54194 2544 goto err_core_destroy;
5e3dd157
KV		 2545 }
2546
2547 /* Request MMIO resources */
2548 ret = pci_request_region(pdev, BAR_NUM, "ath");
2549 if (ret) {
1d2b48d6 2550 ath10k_err("failed to request MMIO region: %d\n", ret);
5e3dd157
KV		 2551 goto err_device;
2552 }
2553
2554 /*
2555 * Target structures have a limit of 32 bit DMA pointers.
2556 * DMA pointers can be wider than 32 bits by default on some systems.
2557 */
2558 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2559 if (ret) {
1d2b48d6 2560 ath10k_err("failed to set DMA mask to 32-bit: %d\n", ret);
5e3dd157
KV		 2561 goto err_region;
2562 }
2563
2564 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2565 if (ret) {
1d2b48d6 2566 ath10k_err("failed to set consistent DMA mask to 32-bit\n");
5e3dd157
KV		 2567 goto err_region;
2568 }
2569
2570 /* Set bus master bit in PCI_COMMAND to enable DMA */
2571 pci_set_master(pdev);
2572
2573 /*
2574 * Temporary FIX: disable ASPM
2575 * Will be removed after the OTP is programmed
2576 */
2577 pci_read_config_dword(pdev, 0x80, &lcr_val);
2578 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2579
2580 /* Arrange for access to Target SoC registers. */
2581 mem = pci_iomap(pdev, BAR_NUM, 0);
2582 if (!mem) {
1d2b48d6 2583 ath10k_err("failed to perform IOMAP for BAR%d\n", BAR_NUM);
5e3dd157
KV		 2584 ret = -EIO;
2585 goto err_master;
2586 }
2587
2588 ar_pci->mem = mem;
2589
2590 spin_lock_init(&ar_pci->ce_lock);
2591
c0c378f9 2592 ret = ath10k_pci_wake(ar);
e01ae68c 2593 if (ret) {
c0c378f9 2594 ath10k_err("failed to wake up: %d\n", ret);
12eb0879 2595 goto err_iomap;
e01ae68c
KV		 2596 }
2597
233eb97f 2598 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
c0c378f9
MK		 2599 if (chip_id == 0xffffffff) {
2600 ath10k_err("failed to get chip id\n");
2601 goto err_sleep;
2602 }
e01ae68c 2603
25d0dbcb
MK		 2604 ret = ath10k_pci_alloc_ce(ar);
2605 if (ret) {
2606 ath10k_err("failed to allocate copy engine pipes: %d\n", ret);
c0c378f9 2607 goto err_sleep;
25d0dbcb
MK		 2608 }
2609
24cfade1
KV		 2610 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2611
e01ae68c 2612 ret = ath10k_core_register(ar, chip_id);
5e3dd157 2613 if (ret) {
1d2b48d6 2614 ath10k_err("failed to register driver core: %d\n", ret);
25d0dbcb 2615 goto err_free_ce;
5e3dd157
KV		 2616 }
2617
2618 return 0;
2619
25d0dbcb
MK		 2620err_free_ce:
2621 ath10k_pci_free_ce(ar);
c0c378f9
MK		 2622err_sleep:
2623 ath10k_pci_sleep(ar);
5e3dd157
KV		 2624err_iomap:
2625 pci_iounmap(pdev, mem);
2626err_master:
2627 pci_clear_master(pdev);
2628err_region:
2629 pci_release_region(pdev, BAR_NUM);
2630err_device:
2631 pci_disable_device(pdev);
e7b54194 2632err_core_destroy:
5e3dd157 2633 ath10k_core_destroy(ar);
5e3dd157
KV		 2634
2635 return ret;
2636}
2637
2638static void ath10k_pci_remove(struct pci_dev *pdev)
2639{
2640 struct ath10k *ar = pci_get_drvdata(pdev);
2641 struct ath10k_pci *ar_pci;
2642
50f87a67 2643 ath10k_dbg(ATH10K_DBG_PCI, "pci remove\n");
5e3dd157
KV		 2644
2645 if (!ar)
2646 return;
2647
2648 ar_pci = ath10k_pci_priv(ar);
2649
2650 if (!ar_pci)
2651 return;
2652
5e3dd157 2653 ath10k_core_unregister(ar);
25d0dbcb 2654 ath10k_pci_free_ce(ar);
c0c378f9 2655 ath10k_pci_sleep(ar);
5e3dd157 2656
5e3dd157
KV		 2657 pci_iounmap(pdev, ar_pci->mem);
2658 pci_release_region(pdev, BAR_NUM);
2659 pci_clear_master(pdev);
2660 pci_disable_device(pdev);
2661
2662 ath10k_core_destroy(ar);
5e3dd157
KV		 2663}
2664
5e3dd157
KV		 2665MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2666
2667static struct pci_driver ath10k_pci_driver = {
2668 .name = "ath10k_pci",
2669 .id_table = ath10k_pci_id_table,
2670 .probe = ath10k_pci_probe,
2671 .remove = ath10k_pci_remove,
5e3dd157
KV		 2672};
2673
2674static int __init ath10k_pci_init(void)
2675{
2676 int ret;
2677
2678 ret = pci_register_driver(&ath10k_pci_driver);
2679 if (ret)
1d2b48d6 2680 ath10k_err("failed to register PCI driver: %d\n", ret);
5e3dd157
KV		 2681
2682 return ret;
2683}
2684module_init(ath10k_pci_init);
2685
2686static void __exit ath10k_pci_exit(void)
2687{
2688 pci_unregister_driver(&ath10k_pci_driver);
2689}
2690
2691module_exit(ath10k_pci_exit);
2692
2693MODULE_AUTHOR("Qualcomm Atheros");
2694MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2695MODULE_LICENSE("Dual BSD/GPL");
24c88f78 2696MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_3_FILE);
5e3dd157 2697MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
Linux kernel - Deliverables
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