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ath10k: fix spelling mistake in comments
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / pci.c
CommitLineData
5e3dd157
KV		 1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/pci.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
650b91fb 22#include <linux/bitops.h>
5e3dd157
KV		 23
24#include "core.h"
25#include "debug.h"
26
27#include "targaddrs.h"
28#include "bmi.h"
29
30#include "hif.h"
31#include "htc.h"
32
33#include "ce.h"
34#include "pci.h"
35
cfe9c45b
MK		 36enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
40};
41
35098463
KV		 42enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
45};
46
e42c1fbd 47static unsigned int ath10k_pci_target_ps;
cfe9c45b 48static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
35098463 49static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
cfe9c45b 50
e42c1fbd
KV		 51module_param_named(target_ps, ath10k_pci_target_ps, uint, 0644);
52MODULE_PARM_DESC(target_ps, "Enable ath10k Target (SoC) PS option");
5e3dd157 53
cfe9c45b
MK		 54module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
55MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
56
35098463
KV		 57module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
58MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
59
0399eca8
KV		 60/* how long wait to wait for target to initialise, in ms */
61#define ATH10K_PCI_TARGET_WAIT 3000
62
5e3dd157
KV		 63#define QCA988X_2_0_DEVICE_ID (0x003c)
64
65static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
5e3dd157
KV		 66 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
67 {0}
68};
69
70static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
71 u32 *data);
72
5e3dd157 73static int ath10k_pci_post_rx(struct ath10k *ar);
87263e5b 74static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
5e3dd157 75 int num);
87263e5b 76static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
fc36e3ff
MK		 77static int ath10k_pci_cold_reset(struct ath10k *ar);
78static int ath10k_pci_warm_reset(struct ath10k *ar);
d7fb47f5 79static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
fc15ca13
MK		 80static int ath10k_pci_init_irq(struct ath10k *ar);
81static int ath10k_pci_deinit_irq(struct ath10k *ar);
82static int ath10k_pci_request_irq(struct ath10k *ar);
83static void ath10k_pci_free_irq(struct ath10k *ar);
85622cde
MK		 84static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
85 struct ath10k_ce_pipe *rx_pipe,
86 struct bmi_xfer *xfer);
5e3dd157
KV		 87
88static const struct ce_attr host_ce_config_wlan[] = {
48e9c225
KV		 89 /* CE0: host->target HTC control and raw streams */
90 {
91 .flags = CE_ATTR_FLAGS,
92 .src_nentries = 16,
93 .src_sz_max = 256,
94 .dest_nentries = 0,
95 },
96
97 /* CE1: target->host HTT + HTC control */
98 {
99 .flags = CE_ATTR_FLAGS,
100 .src_nentries = 0,
101 .src_sz_max = 512,
102 .dest_nentries = 512,
103 },
104
105 /* CE2: target->host WMI */
106 {
107 .flags = CE_ATTR_FLAGS,
108 .src_nentries = 0,
109 .src_sz_max = 2048,
110 .dest_nentries = 32,
111 },
112
113 /* CE3: host->target WMI */
114 {
115 .flags = CE_ATTR_FLAGS,
116 .src_nentries = 32,
117 .src_sz_max = 2048,
118 .dest_nentries = 0,
119 },
120
121 /* CE4: host->target HTT */
122 {
123 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
124 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
125 .src_sz_max = 256,
126 .dest_nentries = 0,
127 },
128
129 /* CE5: unused */
130 {
131 .flags = CE_ATTR_FLAGS,
132 .src_nentries = 0,
133 .src_sz_max = 0,
134 .dest_nentries = 0,
135 },
136
137 /* CE6: target autonomous hif_memcpy */
138 {
139 .flags = CE_ATTR_FLAGS,
140 .src_nentries = 0,
141 .src_sz_max = 0,
142 .dest_nentries = 0,
143 },
144
145 /* CE7: ce_diag, the Diagnostic Window */
146 {
147 .flags = CE_ATTR_FLAGS,
148 .src_nentries = 2,
149 .src_sz_max = DIAG_TRANSFER_LIMIT,
150 .dest_nentries = 2,
151 },
5e3dd157
KV		 152};
153
154/* Target firmware's Copy Engine configuration. */
155static const struct ce_pipe_config target_ce_config_wlan[] = {
d88effba
KV		 156 /* CE0: host->target HTC control and raw streams */
157 {
158 .pipenum = 0,
159 .pipedir = PIPEDIR_OUT,
160 .nentries = 32,
161 .nbytes_max = 256,
162 .flags = CE_ATTR_FLAGS,
163 .reserved = 0,
164 },
165
166 /* CE1: target->host HTT + HTC control */
167 {
168 .pipenum = 1,
169 .pipedir = PIPEDIR_IN,
170 .nentries = 32,
171 .nbytes_max = 512,
172 .flags = CE_ATTR_FLAGS,
173 .reserved = 0,
174 },
175
176 /* CE2: target->host WMI */
177 {
178 .pipenum = 2,
179 .pipedir = PIPEDIR_IN,
180 .nentries = 32,
181 .nbytes_max = 2048,
182 .flags = CE_ATTR_FLAGS,
183 .reserved = 0,
184 },
185
186 /* CE3: host->target WMI */
187 {
188 .pipenum = 3,
189 .pipedir = PIPEDIR_OUT,
190 .nentries = 32,
191 .nbytes_max = 2048,
192 .flags = CE_ATTR_FLAGS,
193 .reserved = 0,
194 },
195
196 /* CE4: host->target HTT */
197 {
198 .pipenum = 4,
199 .pipedir = PIPEDIR_OUT,
200 .nentries = 256,
201 .nbytes_max = 256,
202 .flags = CE_ATTR_FLAGS,
203 .reserved = 0,
204 },
205
5e3dd157 206 /* NB: 50% of src nentries, since tx has 2 frags */
d88effba
KV		 207
208 /* CE5: unused */
209 {
210 .pipenum = 5,
211 .pipedir = PIPEDIR_OUT,
212 .nentries = 32,
213 .nbytes_max = 2048,
214 .flags = CE_ATTR_FLAGS,
215 .reserved = 0,
216 },
217
218 /* CE6: Reserved for target autonomous hif_memcpy */
219 {
220 .pipenum = 6,
221 .pipedir = PIPEDIR_INOUT,
222 .nentries = 32,
223 .nbytes_max = 4096,
224 .flags = CE_ATTR_FLAGS,
225 .reserved = 0,
226 },
227
5e3dd157
KV		 228 /* CE7 used only by Host */
229};
230
e539887b
MK		 231static bool ath10k_pci_irq_pending(struct ath10k *ar)
232{
233 u32 cause;
234
235 /* Check if the shared legacy irq is for us */
236 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
237 PCIE_INTR_CAUSE_ADDRESS);
238 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
239 return true;
240
241 return false;
242}
243
2685218b
MK		 244static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
245{
246 /* IMPORTANT: INTR_CLR register has to be set after
247 * INTR_ENABLE is set to 0, otherwise interrupt can not be
248 * really cleared. */
249 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
250 0);
251 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
252 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
253
254 /* IMPORTANT: this extra read transaction is required to
255 * flush the posted write buffer. */
256 (void) ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
257 PCIE_INTR_ENABLE_ADDRESS);
258}
259
260static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
261{
262 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
263 PCIE_INTR_ENABLE_ADDRESS,
264 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
265
266 /* IMPORTANT: this extra read transaction is required to
267 * flush the posted write buffer. */
268 (void) ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
269 PCIE_INTR_ENABLE_ADDRESS);
270}
271
ab977bd0
MK		 272static irqreturn_t ath10k_pci_early_irq_handler(int irq, void *arg)
273{
274 struct ath10k *ar = arg;
275 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
276
277 if (ar_pci->num_msi_intrs == 0) {
278 if (!ath10k_pci_irq_pending(ar))
279 return IRQ_NONE;
280
281 ath10k_pci_disable_and_clear_legacy_irq(ar);
282 }
283
284 tasklet_schedule(&ar_pci->early_irq_tasklet);
285
286 return IRQ_HANDLED;
287}
288
289static int ath10k_pci_request_early_irq(struct ath10k *ar)
290{
291 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
292 int ret;
293
294 /* Regardless whether MSI-X/MSI/legacy irqs have been set up the first
295 * interrupt from irq vector is triggered in all cases for FW
296 * indication/errors */
297 ret = request_irq(ar_pci->pdev->irq, ath10k_pci_early_irq_handler,
298 IRQF_SHARED, "ath10k_pci (early)", ar);
299 if (ret) {
300 ath10k_warn("failed to request early irq: %d\n", ret);
301 return ret;
302 }
303
304 return 0;
305}
306
307static void ath10k_pci_free_early_irq(struct ath10k *ar)
308{
309 free_irq(ath10k_pci_priv(ar)->pdev->irq, ar);
310}
311
5e3dd157
KV		 312/*
313 * Diagnostic read/write access is provided for startup/config/debug usage.
314 * Caller must guarantee proper alignment, when applicable, and single user
315 * at any moment.
316 */
317static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
318 int nbytes)
319{
320 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
321 int ret = 0;
322 u32 buf;
323 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
324 unsigned int id;
325 unsigned int flags;
2aa39115 326 struct ath10k_ce_pipe *ce_diag;
5e3dd157
KV		 327 /* Host buffer address in CE space */
328 u32 ce_data;
329 dma_addr_t ce_data_base = 0;
330 void *data_buf = NULL;
331 int i;
332
333 /*
334 * This code cannot handle reads to non-memory space. Redirect to the
335 * register read fn but preserve the multi word read capability of
336 * this fn
337 */
338 if (address < DRAM_BASE_ADDRESS) {
339 if (!IS_ALIGNED(address, 4) ||
340 !IS_ALIGNED((unsigned long)data, 4))
341 return -EIO;
342
343 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
344 ar, address, (u32 *)data)) == 0)) {
345 nbytes -= sizeof(u32);
346 address += sizeof(u32);
347 data += sizeof(u32);
348 }
349 return ret;
350 }
351
352 ce_diag = ar_pci->ce_diag;
353
354 /*
355 * Allocate a temporary bounce buffer to hold caller's data
356 * to be DMA'ed from Target. This guarantees
357 * 1) 4-byte alignment
358 * 2) Buffer in DMA-able space
359 */
360 orig_nbytes = nbytes;
68c03249
MK		 361 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
362 orig_nbytes,
363 &ce_data_base,
364 GFP_ATOMIC);
5e3dd157
KV		 365
366 if (!data_buf) {
367 ret = -ENOMEM;
368 goto done;
369 }
370 memset(data_buf, 0, orig_nbytes);
371
372 remaining_bytes = orig_nbytes;
373 ce_data = ce_data_base;
374 while (remaining_bytes) {
375 nbytes = min_t(unsigned int, remaining_bytes,
376 DIAG_TRANSFER_LIMIT);
377
378 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
379 if (ret != 0)
380 goto done;
381
382 /* Request CE to send from Target(!) address to Host buffer */
383 /*
384 * The address supplied by the caller is in the
385 * Target CPU virtual address space.
386 *
387 * In order to use this address with the diagnostic CE,
388 * convert it from Target CPU virtual address space
389 * to CE address space
390 */
391 ath10k_pci_wake(ar);
392 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
393 address);
394 ath10k_pci_sleep(ar);
395
396 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
397 0);
398 if (ret)
399 goto done;
400
401 i = 0;
402 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
403 &completed_nbytes,
404 &id) != 0) {
405 mdelay(1);
406 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
407 ret = -EBUSY;
408 goto done;
409 }
410 }
411
412 if (nbytes != completed_nbytes) {
413 ret = -EIO;
414 goto done;
415 }
416
417 if (buf != (u32) address) {
418 ret = -EIO;
419 goto done;
420 }
421
422 i = 0;
423 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
424 &completed_nbytes,
425 &id, &flags) != 0) {
426 mdelay(1);
427
428 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
429 ret = -EBUSY;
430 goto done;
431 }
432 }
433
434 if (nbytes != completed_nbytes) {
435 ret = -EIO;
436 goto done;
437 }
438
439 if (buf != ce_data) {
440 ret = -EIO;
441 goto done;
442 }
443
444 remaining_bytes -= nbytes;
445 address += nbytes;
446 ce_data += nbytes;
447 }
448
449done:
450 if (ret == 0) {
451 /* Copy data from allocated DMA buf to caller's buf */
452 WARN_ON_ONCE(orig_nbytes & 3);
453 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
454 ((u32 *)data)[i] =
455 __le32_to_cpu(((__le32 *)data_buf)[i]);
456 }
457 } else
50f87a67
KV		 458 ath10k_warn("failed to read diag value at 0x%x: %d\n",
459 address, ret);
5e3dd157
KV		 460
461 if (data_buf)
68c03249
MK		 462 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
463 ce_data_base);
5e3dd157
KV		 464
465 return ret;
466}
467
468/* Read 4-byte aligned data from Target memory or register */
469static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
470 u32 *data)
471{
472 /* Assume range doesn't cross this boundary */
473 if (address >= DRAM_BASE_ADDRESS)
474 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
475
476 ath10k_pci_wake(ar);
477 *data = ath10k_pci_read32(ar, address);
478 ath10k_pci_sleep(ar);
479 return 0;
480}
481
482static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
483 const void *data, int nbytes)
484{
485 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
486 int ret = 0;
487 u32 buf;
488 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
489 unsigned int id;
490 unsigned int flags;
2aa39115 491 struct ath10k_ce_pipe *ce_diag;
5e3dd157
KV		 492 void *data_buf = NULL;
493 u32 ce_data; /* Host buffer address in CE space */
494 dma_addr_t ce_data_base = 0;
495 int i;
496
497 ce_diag = ar_pci->ce_diag;
498
499 /*
500 * Allocate a temporary bounce buffer to hold caller's data
501 * to be DMA'ed to Target. This guarantees
502 * 1) 4-byte alignment
503 * 2) Buffer in DMA-able space
504 */
505 orig_nbytes = nbytes;
68c03249
MK		 506 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
507 orig_nbytes,
508 &ce_data_base,
509 GFP_ATOMIC);
5e3dd157
KV		 510 if (!data_buf) {
511 ret = -ENOMEM;
512 goto done;
513 }
514
515 /* Copy caller's data to allocated DMA buf */
516 WARN_ON_ONCE(orig_nbytes & 3);
517 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
518 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
519
520 /*
521 * The address supplied by the caller is in the
522 * Target CPU virtual address space.
523 *
524 * In order to use this address with the diagnostic CE,
525 * convert it from
526 * Target CPU virtual address space
527 * to
528 * CE address space
529 */
530 ath10k_pci_wake(ar);
531 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
532 ath10k_pci_sleep(ar);
533
534 remaining_bytes = orig_nbytes;
535 ce_data = ce_data_base;
536 while (remaining_bytes) {
537 /* FIXME: check cast */
538 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
539
540 /* Set up to receive directly into Target(!) address */
541 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
542 if (ret != 0)
543 goto done;
544
545 /*
546 * Request CE to send caller-supplied data that
547 * was copied to bounce buffer to Target(!) address.
548 */
549 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
550 nbytes, 0, 0);
551 if (ret != 0)
552 goto done;
553
554 i = 0;
555 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
556 &completed_nbytes,
557 &id) != 0) {
558 mdelay(1);
559
560 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
561 ret = -EBUSY;
562 goto done;
563 }
564 }
565
566 if (nbytes != completed_nbytes) {
567 ret = -EIO;
568 goto done;
569 }
570
571 if (buf != ce_data) {
572 ret = -EIO;
573 goto done;
574 }
575
576 i = 0;
577 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
578 &completed_nbytes,
579 &id, &flags) != 0) {
580 mdelay(1);
581
582 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
583 ret = -EBUSY;
584 goto done;
585 }
586 }
587
588 if (nbytes != completed_nbytes) {
589 ret = -EIO;
590 goto done;
591 }
592
593 if (buf != address) {
594 ret = -EIO;
595 goto done;
596 }
597
598 remaining_bytes -= nbytes;
599 address += nbytes;
600 ce_data += nbytes;
601 }
602
603done:
604 if (data_buf) {
68c03249
MK		 605 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
606 ce_data_base);
5e3dd157
KV		 607 }
608
609 if (ret != 0)
50f87a67
KV		 610 ath10k_warn("failed to write diag value at 0x%x: %d\n",
611 address, ret);
5e3dd157
KV		 612
613 return ret;
614}
615
616/* Write 4B data to Target memory or register */
617static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
618 u32 data)
619{
620 /* Assume range doesn't cross this boundary */
621 if (address >= DRAM_BASE_ADDRESS)
622 return ath10k_pci_diag_write_mem(ar, address, &data,
623 sizeof(u32));
624
625 ath10k_pci_wake(ar);
626 ath10k_pci_write32(ar, address, data);
627 ath10k_pci_sleep(ar);
628 return 0;
629}
630
631static bool ath10k_pci_target_is_awake(struct ath10k *ar)
632{
633 void __iomem *mem = ath10k_pci_priv(ar)->mem;
634 u32 val;
635 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
636 RTC_STATE_ADDRESS);
637 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
638}
639
3aebe54b 640int ath10k_do_pci_wake(struct ath10k *ar)
5e3dd157
KV		 641{
642 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
643 void __iomem *pci_addr = ar_pci->mem;
644 int tot_delay = 0;
645 int curr_delay = 5;
646
647 if (atomic_read(&ar_pci->keep_awake_count) == 0) {
648 /* Force AWAKE */
649 iowrite32(PCIE_SOC_WAKE_V_MASK,
650 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
651 PCIE_SOC_WAKE_ADDRESS);
652 }
653 atomic_inc(&ar_pci->keep_awake_count);
654
655 if (ar_pci->verified_awake)
3aebe54b 656 return 0;
5e3dd157
KV		 657
658 for (;;) {
659 if (ath10k_pci_target_is_awake(ar)) {
660 ar_pci->verified_awake = true;
3aebe54b 661 return 0;
5e3dd157
KV		 662 }
663
664 if (tot_delay > PCIE_WAKE_TIMEOUT) {
3aebe54b
KV		 665 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
666 PCIE_WAKE_TIMEOUT,
5e3dd157 667 atomic_read(&ar_pci->keep_awake_count));
3aebe54b 668 return -ETIMEDOUT;
5e3dd157
KV		 669 }
670
671 udelay(curr_delay);
672 tot_delay += curr_delay;
673
674 if (curr_delay < 50)
675 curr_delay += 5;
676 }
677}
678
679void ath10k_do_pci_sleep(struct ath10k *ar)
680{
681 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
682 void __iomem *pci_addr = ar_pci->mem;
683
684 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
685 /* Allow sleep */
686 ar_pci->verified_awake = false;
687 iowrite32(PCIE_SOC_WAKE_RESET,
688 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
689 PCIE_SOC_WAKE_ADDRESS);
690 }
691}
692
5e3dd157 693/* Called by lower (CE) layer when a send to Target completes. */
5440ce25 694static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
5e3dd157
KV		 695{
696 struct ath10k *ar = ce_state->ar;
697 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2f5280da 698 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
5440ce25
MK		 699 void *transfer_context;
700 u32 ce_data;
701 unsigned int nbytes;
702 unsigned int transfer_id;
5e3dd157 703
5440ce25
MK		 704 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
705 &ce_data, &nbytes,
706 &transfer_id) == 0) {
a16942e6 707 /* no need to call tx completion for NULL pointers */
726346fc
MK		 708 if (transfer_context == NULL)
709 continue;
710
2f5280da 711 cb->tx_completion(ar, transfer_context, transfer_id);
5440ce25 712 }
5e3dd157
KV		 713}
714
715/* Called by lower (CE) layer when data is received from the Target. */
5440ce25 716static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
5e3dd157
KV		 717{
718 struct ath10k *ar = ce_state->ar;
719 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 720 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
2f5280da 721 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
5e3dd157 722 struct sk_buff *skb;
5440ce25
MK		 723 void *transfer_context;
724 u32 ce_data;
2f5280da 725 unsigned int nbytes, max_nbytes;
5440ce25
MK		 726 unsigned int transfer_id;
727 unsigned int flags;
2f5280da 728 int err;
5e3dd157 729
5440ce25
MK		 730 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
731 &ce_data, &nbytes, &transfer_id,
732 &flags) == 0) {
2f5280da
MK		 733 err = ath10k_pci_post_rx_pipe(pipe_info, 1);
734 if (unlikely(err)) {
735 /* FIXME: retry */
736 ath10k_warn("failed to replenish CE rx ring %d: %d\n",
737 pipe_info->pipe_num, err);
738 }
5e3dd157
KV		 739
740 skb = transfer_context;
2f5280da 741 max_nbytes = skb->len + skb_tailroom(skb);
5e3dd157 742 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
2f5280da
MK		 743 max_nbytes, DMA_FROM_DEVICE);
744
745 if (unlikely(max_nbytes < nbytes)) {
746 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
747 nbytes, max_nbytes);
748 dev_kfree_skb_any(skb);
749 continue;
750 }
5e3dd157 751
2f5280da
MK		 752 skb_put(skb, nbytes);
753 cb->rx_completion(ar, skb, pipe_info->pipe_num);
754 }
5e3dd157
KV		 755}
756
726346fc
MK		 757static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
758 struct ath10k_hif_sg_item *items, int n_items)
5e3dd157 759{
5e3dd157 760 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
726346fc
MK		 761 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
762 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
763 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
764 unsigned int nentries_mask = src_ring->nentries_mask;
765 unsigned int sw_index = src_ring->sw_index;
766 unsigned int write_index = src_ring->write_index;
767 int err, i;
5e3dd157 768
726346fc 769 spin_lock_bh(&ar_pci->ce_lock);
5e3dd157 770
726346fc
MK		 771 if (unlikely(CE_RING_DELTA(nentries_mask,
772 write_index, sw_index - 1) < n_items)) {
773 err = -ENOBUFS;
774 goto unlock;
775 }
5e3dd157 776
726346fc
MK		 777 for (i = 0; i < n_items - 1; i++) {
778 ath10k_dbg(ATH10K_DBG_PCI,
779 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
780 i, items[i].paddr, items[i].len, n_items);
781 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ",
782 items[i].vaddr, items[i].len);
5e3dd157 783
726346fc
MK		 784 err = ath10k_ce_send_nolock(ce_pipe,
785 items[i].transfer_context,
786 items[i].paddr,
787 items[i].len,
788 items[i].transfer_id,
789 CE_SEND_FLAG_GATHER);
790 if (err)
791 goto unlock;
792 }
793
794 /* `i` is equal to `n_items -1` after for() */
795
796 ath10k_dbg(ATH10K_DBG_PCI,
797 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
798 i, items[i].paddr, items[i].len, n_items);
799 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ",
800 items[i].vaddr, items[i].len);
801
802 err = ath10k_ce_send_nolock(ce_pipe,
803 items[i].transfer_context,
804 items[i].paddr,
805 items[i].len,
806 items[i].transfer_id,
807 0);
808 if (err)
809 goto unlock;
810
811 err = 0;
812unlock:
813 spin_unlock_bh(&ar_pci->ce_lock);
814 return err;
5e3dd157
KV		 815}
816
817static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
818{
819 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
50f87a67
KV		 820
821 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get free queue number\n");
822
3efcb3b4 823 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
5e3dd157
KV		 824}
825
826static void ath10k_pci_hif_dump_area(struct ath10k *ar)
827{
828 u32 reg_dump_area = 0;
829 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
830 u32 host_addr;
831 int ret;
832 u32 i;
833
834 ath10k_err("firmware crashed!\n");
835 ath10k_err("hardware name %s version 0x%x\n",
836 ar->hw_params.name, ar->target_version);
5ba88b39 837 ath10k_err("firmware version: %s\n", ar->hw->wiphy->fw_version);
5e3dd157
KV		 838
839 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
1d2b48d6
MK		 840 ret = ath10k_pci_diag_read_mem(ar, host_addr,
841 &reg_dump_area, sizeof(u32));
842 if (ret) {
843 ath10k_err("failed to read FW dump area address: %d\n", ret);
5e3dd157
KV		 844 return;
845 }
846
847 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
848
849 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
850 &reg_dump_values[0],
851 REG_DUMP_COUNT_QCA988X * sizeof(u32));
852 if (ret != 0) {
1d2b48d6 853 ath10k_err("failed to read FW dump area: %d\n", ret);
5e3dd157
KV		 854 return;
855 }
856
857 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
858
859 ath10k_err("target Register Dump\n");
860 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
861 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
862 i,
863 reg_dump_values[i],
864 reg_dump_values[i + 1],
865 reg_dump_values[i + 2],
866 reg_dump_values[i + 3]);
affd3217 867
5e90de86 868 queue_work(ar->workqueue, &ar->restart_work);
5e3dd157
KV		 869}
870
871static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
872 int force)
873{
50f87a67
KV		 874 ath10k_dbg(ATH10K_DBG_PCI, "pci hif send complete check\n");
875
5e3dd157
KV		 876 if (!force) {
877 int resources;
878 /*
879 * Decide whether to actually poll for completions, or just
880 * wait for a later chance.
881 * If there seem to be plenty of resources left, then just wait
882 * since checking involves reading a CE register, which is a
883 * relatively expensive operation.
884 */
885 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
886
887 /*
888 * If at least 50% of the total resources are still available,
889 * don't bother checking again yet.
890 */
891 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
892 return;
893 }
894 ath10k_ce_per_engine_service(ar, pipe);
895}
896
e799bbff
MK		 897static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
898 struct ath10k_hif_cb *callbacks)
5e3dd157
KV		 899{
900 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
901
50f87a67 902 ath10k_dbg(ATH10K_DBG_PCI, "pci hif set callbacks\n");
5e3dd157
KV		 903
904 memcpy(&ar_pci->msg_callbacks_current, callbacks,
905 sizeof(ar_pci->msg_callbacks_current));
906}
907
c80de12b 908static int ath10k_pci_setup_ce_irq(struct ath10k *ar)
5e3dd157
KV		 909{
910 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
c80de12b
MK		 911 const struct ce_attr *attr;
912 struct ath10k_pci_pipe *pipe_info;
913 int pipe_num, disable_interrupts;
5e3dd157 914
c80de12b
MK		 915 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
916 pipe_info = &ar_pci->pipe_info[pipe_num];
917
918 /* Handle Diagnostic CE specially */
919 if (pipe_info->ce_hdl == ar_pci->ce_diag)
920 continue;
921
922 attr = &host_ce_config_wlan[pipe_num];
923
924 if (attr->src_nentries) {
925 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
926 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
927 ath10k_pci_ce_send_done,
928 disable_interrupts);
929 }
930
931 if (attr->dest_nentries)
932 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
933 ath10k_pci_ce_recv_data);
934 }
935
936 return 0;
937}
938
96a9d0dc 939static void ath10k_pci_kill_tasklet(struct ath10k *ar)
5e3dd157
KV		 940{
941 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 942 int i;
5e3dd157 943
5e3dd157 944 tasklet_kill(&ar_pci->intr_tq);
103d4f5e 945 tasklet_kill(&ar_pci->msi_fw_err);
ab977bd0 946 tasklet_kill(&ar_pci->early_irq_tasklet);
5e3dd157
KV		 947
948 for (i = 0; i < CE_COUNT; i++)
949 tasklet_kill(&ar_pci->pipe_info[i].intr);
96a9d0dc
MK		 950}
951
5e3dd157
KV		 952/* TODO - temporary mapping while we have too few CE's */
953static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
954 u16 service_id, u8 *ul_pipe,
955 u8 *dl_pipe, int *ul_is_polled,
956 int *dl_is_polled)
957{
958 int ret = 0;
959
50f87a67
KV		 960 ath10k_dbg(ATH10K_DBG_PCI, "pci hif map service\n");
961
5e3dd157
KV		 962 /* polling for received messages not supported */
963 *dl_is_polled = 0;
964
965 switch (service_id) {
966 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
967 /*
968 * Host->target HTT gets its own pipe, so it can be polled
969 * while other pipes are interrupt driven.
970 */
971 *ul_pipe = 4;
972 /*
973 * Use the same target->host pipe for HTC ctrl, HTC raw
974 * streams, and HTT.
975 */
976 *dl_pipe = 1;
977 break;
978
979 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
980 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
981 /*
982 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
983 * HTC_CTRL_RSVD_SVC could share the same pipe as the
984 * WMI services. So, if another CE is needed, change
985 * this to *ul_pipe = 3, which frees up CE 0.
986 */
987 /* *ul_pipe = 3; */
988 *ul_pipe = 0;
989 *dl_pipe = 1;
990 break;
991
992 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
993 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
994 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
995 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
996
997 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
998 *ul_pipe = 3;
999 *dl_pipe = 2;
1000 break;
1001
1002 /* pipe 5 unused */
1003 /* pipe 6 reserved */
1004 /* pipe 7 reserved */
1005
1006 default:
1007 ret = -1;
1008 break;
1009 }
1010 *ul_is_polled =
1011 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1012
1013 return ret;
1014}
1015
1016static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1017 u8 *ul_pipe, u8 *dl_pipe)
1018{
1019 int ul_is_polled, dl_is_polled;
1020
50f87a67
KV		 1021 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get default pipe\n");
1022
5e3dd157
KV		 1023 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1024 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1025 ul_pipe,
1026 dl_pipe,
1027 &ul_is_polled,
1028 &dl_is_polled);
1029}
1030
87263e5b 1031static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
5e3dd157
KV		 1032 int num)
1033{
1034 struct ath10k *ar = pipe_info->hif_ce_state;
1035 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115 1036 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
5e3dd157
KV		 1037 struct sk_buff *skb;
1038 dma_addr_t ce_data;
1039 int i, ret = 0;
1040
1041 if (pipe_info->buf_sz == 0)
1042 return 0;
1043
1044 for (i = 0; i < num; i++) {
1045 skb = dev_alloc_skb(pipe_info->buf_sz);
1046 if (!skb) {
1d2b48d6 1047 ath10k_warn("failed to allocate skbuff for pipe %d\n",
5e3dd157
KV		 1048 num);
1049 ret = -ENOMEM;
1050 goto err;
1051 }
1052
1053 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1054
1055 ce_data = dma_map_single(ar->dev, skb->data,
1056 skb->len + skb_tailroom(skb),
1057 DMA_FROM_DEVICE);
1058
1059 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1d2b48d6 1060 ath10k_warn("failed to DMA map sk_buff\n");
5e3dd157
KV		 1061 dev_kfree_skb_any(skb);
1062 ret = -EIO;
1063 goto err;
1064 }
1065
1066 ATH10K_SKB_CB(skb)->paddr = ce_data;
1067
1068 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1069 pipe_info->buf_sz,
1070 PCI_DMA_FROMDEVICE);
1071
1072 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1073 ce_data);
1074 if (ret) {
1d2b48d6 1075 ath10k_warn("failed to enqueue to pipe %d: %d\n",
5e3dd157
KV		 1076 num, ret);
1077 goto err;
1078 }
1079 }
1080
1081 return ret;
1082
1083err:
1084 ath10k_pci_rx_pipe_cleanup(pipe_info);
1085 return ret;
1086}
1087
1088static int ath10k_pci_post_rx(struct ath10k *ar)
1089{
1090 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1091 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1092 const struct ce_attr *attr;
1093 int pipe_num, ret = 0;
1094
fad6ed78 1095 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157
KV		 1096 pipe_info = &ar_pci->pipe_info[pipe_num];
1097 attr = &host_ce_config_wlan[pipe_num];
1098
1099 if (attr->dest_nentries == 0)
1100 continue;
1101
1102 ret = ath10k_pci_post_rx_pipe(pipe_info,
1103 attr->dest_nentries - 1);
1104 if (ret) {
1d2b48d6
MK		 1105 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1106 pipe_num, ret);
5e3dd157
KV		 1107
1108 for (; pipe_num >= 0; pipe_num--) {
1109 pipe_info = &ar_pci->pipe_info[pipe_num];
1110 ath10k_pci_rx_pipe_cleanup(pipe_info);
1111 }
1112 return ret;
1113 }
1114 }
1115
1116 return 0;
1117}
1118
1119static int ath10k_pci_hif_start(struct ath10k *ar)
1120{
1121 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
ab977bd0 1122 int ret, ret_early;
5e3dd157 1123
50f87a67
KV		 1124 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif start\n");
1125
ab977bd0
MK		 1126 ath10k_pci_free_early_irq(ar);
1127 ath10k_pci_kill_tasklet(ar);
5e3dd157 1128
5d1aa946
MK		 1129 ret = ath10k_pci_request_irq(ar);
1130 if (ret) {
1131 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1132 ret);
2f5280da 1133 goto err_early_irq;
5d1aa946
MK		 1134 }
1135
c80de12b
MK		 1136 ret = ath10k_pci_setup_ce_irq(ar);
1137 if (ret) {
1138 ath10k_warn("failed to setup CE interrupts: %d\n", ret);
5d1aa946 1139 goto err_stop;
5e3dd157
KV		 1140 }
1141
1142 /* Post buffers once to start things off. */
1143 ret = ath10k_pci_post_rx(ar);
1144 if (ret) {
1d2b48d6
MK		 1145 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1146 ret);
5d1aa946 1147 goto err_stop;
5e3dd157
KV		 1148 }
1149
1150 ar_pci->started = 1;
1151 return 0;
c80de12b 1152
5d1aa946
MK		 1153err_stop:
1154 ath10k_ce_disable_interrupts(ar);
1155 ath10k_pci_free_irq(ar);
1156 ath10k_pci_kill_tasklet(ar);
ab977bd0
MK		 1157err_early_irq:
1158 /* Though there should be no interrupts (device was reset)
1159 * power_down() expects the early IRQ to be installed as per the
1160 * driver lifecycle. */
1161 ret_early = ath10k_pci_request_early_irq(ar);
1162 if (ret_early)
1163 ath10k_warn("failed to re-enable early irq: %d\n", ret_early);
1164
c80de12b 1165 return ret;
5e3dd157
KV		 1166}
1167
87263e5b 1168static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 1169{
1170 struct ath10k *ar;
1171 struct ath10k_pci *ar_pci;
2aa39115 1172 struct ath10k_ce_pipe *ce_hdl;
5e3dd157
KV		 1173 u32 buf_sz;
1174 struct sk_buff *netbuf;
1175 u32 ce_data;
1176
1177 buf_sz = pipe_info->buf_sz;
1178
1179 /* Unused Copy Engine */
1180 if (buf_sz == 0)
1181 return;
1182
1183 ar = pipe_info->hif_ce_state;
1184 ar_pci = ath10k_pci_priv(ar);
1185
1186 if (!ar_pci->started)
1187 return;
1188
1189 ce_hdl = pipe_info->ce_hdl;
1190
1191 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1192 &ce_data) == 0) {
1193 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1194 netbuf->len + skb_tailroom(netbuf),
1195 DMA_FROM_DEVICE);
1196 dev_kfree_skb_any(netbuf);
1197 }
1198}
1199
87263e5b 1200static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
5e3dd157
KV		 1201{
1202 struct ath10k *ar;
1203 struct ath10k_pci *ar_pci;
2aa39115 1204 struct ath10k_ce_pipe *ce_hdl;
5e3dd157
KV		 1205 struct sk_buff *netbuf;
1206 u32 ce_data;
1207 unsigned int nbytes;
1208 unsigned int id;
1209 u32 buf_sz;
1210
1211 buf_sz = pipe_info->buf_sz;
1212
1213 /* Unused Copy Engine */
1214 if (buf_sz == 0)
1215 return;
1216
1217 ar = pipe_info->hif_ce_state;
1218 ar_pci = ath10k_pci_priv(ar);
1219
1220 if (!ar_pci->started)
1221 return;
1222
1223 ce_hdl = pipe_info->ce_hdl;
1224
1225 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1226 &ce_data, &nbytes, &id) == 0) {
a16942e6
MK		 1227 /* no need to call tx completion for NULL pointers */
1228 if (!netbuf)
2415fc16 1229 continue;
2415fc16 1230
e9bb0aa3
KV		 1231 ar_pci->msg_callbacks_current.tx_completion(ar,
1232 netbuf,
1233 id);
5e3dd157
KV		 1234 }
1235}
1236
1237/*
1238 * Cleanup residual buffers for device shutdown:
1239 * buffers that were enqueued for receive
1240 * buffers that were to be sent
1241 * Note: Buffers that had completed but which were
1242 * not yet processed are on a completion queue. They
1243 * are handled when the completion thread shuts down.
1244 */
1245static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1246{
1247 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1248 int pipe_num;
1249
fad6ed78 1250 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
87263e5b 1251 struct ath10k_pci_pipe *pipe_info;
5e3dd157
KV		 1252
1253 pipe_info = &ar_pci->pipe_info[pipe_num];
1254 ath10k_pci_rx_pipe_cleanup(pipe_info);
1255 ath10k_pci_tx_pipe_cleanup(pipe_info);
1256 }
1257}
1258
1259static void ath10k_pci_ce_deinit(struct ath10k *ar)
1260{
25d0dbcb 1261 int i;
5e3dd157 1262
25d0dbcb
MK		 1263 for (i = 0; i < CE_COUNT; i++)
1264 ath10k_ce_deinit_pipe(ar, i);
5e3dd157
KV		 1265}
1266
1267static void ath10k_pci_hif_stop(struct ath10k *ar)
1268{
32270b61 1269 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5d1aa946 1270 int ret;
32270b61 1271
50f87a67 1272 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif stop\n");
5e3dd157 1273
5d1aa946
MK		 1274 ret = ath10k_ce_disable_interrupts(ar);
1275 if (ret)
1276 ath10k_warn("failed to disable CE interrupts: %d\n", ret);
32270b61 1277
5d1aa946
MK		 1278 ath10k_pci_free_irq(ar);
1279 ath10k_pci_kill_tasklet(ar);
5e3dd157 1280
ab977bd0
MK		 1281 ret = ath10k_pci_request_early_irq(ar);
1282 if (ret)
1283 ath10k_warn("failed to re-enable early irq: %d\n", ret);
1284
5e3dd157
KV		 1285 /* At this point, asynchronous threads are stopped, the target should
1286 * not DMA nor interrupt. We process the leftovers and then free
1287 * everything else up. */
1288
5e3dd157 1289 ath10k_pci_buffer_cleanup(ar);
32270b61 1290
6a42a47e
MK		 1291 /* Make the sure the device won't access any structures on the host by
1292 * resetting it. The device was fed with PCI CE ringbuffer
1293 * configuration during init. If ringbuffers are freed and the device
1294 * were to access them this could lead to memory corruption on the
1295 * host. */
fc36e3ff 1296 ath10k_pci_warm_reset(ar);
6a42a47e 1297
32270b61 1298 ar_pci->started = 0;
5e3dd157
KV		 1299}
1300
1301static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1302 void *req, u32 req_len,
1303 void *resp, u32 *resp_len)
1304{
1305 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2aa39115
MK		 1306 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1307 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1308 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1309 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
5e3dd157
KV		 1310 dma_addr_t req_paddr = 0;
1311 dma_addr_t resp_paddr = 0;
1312 struct bmi_xfer xfer = {};
1313 void *treq, *tresp = NULL;
1314 int ret = 0;
1315
85622cde
MK		 1316 might_sleep();
1317
5e3dd157
KV		 1318 if (resp && !resp_len)
1319 return -EINVAL;
1320
1321 if (resp && resp_len && *resp_len == 0)
1322 return -EINVAL;
1323
1324 treq = kmemdup(req, req_len, GFP_KERNEL);
1325 if (!treq)
1326 return -ENOMEM;
1327
1328 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1329 ret = dma_mapping_error(ar->dev, req_paddr);
1330 if (ret)
1331 goto err_dma;
1332
1333 if (resp && resp_len) {
1334 tresp = kzalloc(*resp_len, GFP_KERNEL);
1335 if (!tresp) {
1336 ret = -ENOMEM;
1337 goto err_req;
1338 }
1339
1340 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1341 DMA_FROM_DEVICE);
1342 ret = dma_mapping_error(ar->dev, resp_paddr);
1343 if (ret)
1344 goto err_req;
1345
1346 xfer.wait_for_resp = true;
1347 xfer.resp_len = 0;
1348
1349 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1350 }
1351
1352 init_completion(&xfer.done);
1353
1354 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1355 if (ret)
1356 goto err_resp;
1357
85622cde
MK		 1358 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1359 if (ret) {
5e3dd157
KV		 1360 u32 unused_buffer;
1361 unsigned int unused_nbytes;
1362 unsigned int unused_id;
1363
5e3dd157
KV		 1364 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1365 &unused_nbytes, &unused_id);
1366 } else {
1367 /* non-zero means we did not time out */
1368 ret = 0;
1369 }
1370
1371err_resp:
1372 if (resp) {
1373 u32 unused_buffer;
1374
1375 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1376 dma_unmap_single(ar->dev, resp_paddr,
1377 *resp_len, DMA_FROM_DEVICE);
1378 }
1379err_req:
1380 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1381
1382 if (ret == 0 && resp_len) {
1383 *resp_len = min(*resp_len, xfer.resp_len);
1384 memcpy(resp, tresp, xfer.resp_len);
1385 }
1386err_dma:
1387 kfree(treq);
1388 kfree(tresp);
1389
1390 return ret;
1391}
1392
5440ce25 1393static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
5e3dd157 1394{
5440ce25
MK		 1395 struct bmi_xfer *xfer;
1396 u32 ce_data;
1397 unsigned int nbytes;
1398 unsigned int transfer_id;
1399
1400 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1401 &nbytes, &transfer_id))
1402 return;
5e3dd157
KV		 1403
1404 if (xfer->wait_for_resp)
1405 return;
1406
1407 complete(&xfer->done);
1408}
1409
5440ce25 1410static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
5e3dd157 1411{
5440ce25
MK		 1412 struct bmi_xfer *xfer;
1413 u32 ce_data;
1414 unsigned int nbytes;
1415 unsigned int transfer_id;
1416 unsigned int flags;
1417
1418 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1419 &nbytes, &transfer_id, &flags))
1420 return;
5e3dd157
KV		 1421
1422 if (!xfer->wait_for_resp) {
1423 ath10k_warn("unexpected: BMI data received; ignoring\n");
1424 return;
1425 }
1426
1427 xfer->resp_len = nbytes;
1428 complete(&xfer->done);
1429}
1430
85622cde
MK		 1431static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1432 struct ath10k_ce_pipe *rx_pipe,
1433 struct bmi_xfer *xfer)
1434{
1435 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1436
1437 while (time_before_eq(jiffies, timeout)) {
1438 ath10k_pci_bmi_send_done(tx_pipe);
1439 ath10k_pci_bmi_recv_data(rx_pipe);
1440
1441 if (completion_done(&xfer->done))
1442 return 0;
1443
1444 schedule();
1445 }
1446
1447 return -ETIMEDOUT;
1448}
1449
5e3dd157
KV		 1450/*
1451 * Map from service/endpoint to Copy Engine.
1452 * This table is derived from the CE_PCI TABLE, above.
1453 * It is passed to the Target at startup for use by firmware.
1454 */
1455static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1456 {
1457 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1458 PIPEDIR_OUT, /* out = UL = host -> target */
1459 3,
1460 },
1461 {
1462 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1463 PIPEDIR_IN, /* in = DL = target -> host */
1464 2,
1465 },
1466 {
1467 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1468 PIPEDIR_OUT, /* out = UL = host -> target */
1469 3,
1470 },
1471 {
1472 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1473 PIPEDIR_IN, /* in = DL = target -> host */
1474 2,
1475 },
1476 {
1477 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1478 PIPEDIR_OUT, /* out = UL = host -> target */
1479 3,
1480 },
1481 {
1482 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1483 PIPEDIR_IN, /* in = DL = target -> host */
1484 2,
1485 },
1486 {
1487 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1488 PIPEDIR_OUT, /* out = UL = host -> target */
1489 3,
1490 },
1491 {
1492 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1493 PIPEDIR_IN, /* in = DL = target -> host */
1494 2,
1495 },
1496 {
1497 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1498 PIPEDIR_OUT, /* out = UL = host -> target */
1499 3,
1500 },
1501 {
1502 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1503 PIPEDIR_IN, /* in = DL = target -> host */
1504 2,
1505 },
1506 {
1507 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1508 PIPEDIR_OUT, /* out = UL = host -> target */
1509 0, /* could be moved to 3 (share with WMI) */
1510 },
1511 {
1512 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1513 PIPEDIR_IN, /* in = DL = target -> host */
1514 1,
1515 },
1516 {
1517 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1518 PIPEDIR_OUT, /* out = UL = host -> target */
1519 0,
1520 },
1521 {
1522 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1523 PIPEDIR_IN, /* in = DL = target -> host */
1524 1,
1525 },
1526 {
1527 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1528 PIPEDIR_OUT, /* out = UL = host -> target */
1529 4,
1530 },
1531 {
1532 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1533 PIPEDIR_IN, /* in = DL = target -> host */
1534 1,
1535 },
1536
1537 /* (Additions here) */
1538
1539 { /* Must be last */
1540 0,
1541 0,
1542 0,
1543 },
1544};
1545
1546/*
1547 * Send an interrupt to the device to wake up the Target CPU
1548 * so it has an opportunity to notice any changed state.
1549 */
1550static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1551{
1552 int ret;
1553 u32 core_ctrl;
1554
1555 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1556 CORE_CTRL_ADDRESS,
1557 &core_ctrl);
1558 if (ret) {
1d2b48d6 1559 ath10k_warn("failed to read core_ctrl: %d\n", ret);
5e3dd157
KV		 1560 return ret;
1561 }
1562
1563 /* A_INUM_FIRMWARE interrupt to Target CPU */
1564 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1565
1566 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1567 CORE_CTRL_ADDRESS,
1568 core_ctrl);
1d2b48d6
MK		 1569 if (ret) {
1570 ath10k_warn("failed to set target CPU interrupt mask: %d\n",
1571 ret);
1572 return ret;
1573 }
5e3dd157 1574
1d2b48d6 1575 return 0;
5e3dd157
KV		 1576}
1577
1578static int ath10k_pci_init_config(struct ath10k *ar)
1579{
1580 u32 interconnect_targ_addr;
1581 u32 pcie_state_targ_addr = 0;
1582 u32 pipe_cfg_targ_addr = 0;
1583 u32 svc_to_pipe_map = 0;
1584 u32 pcie_config_flags = 0;
1585 u32 ealloc_value;
1586 u32 ealloc_targ_addr;
1587 u32 flag2_value;
1588 u32 flag2_targ_addr;
1589 int ret = 0;
1590
1591 /* Download to Target the CE Config and the service-to-CE map */
1592 interconnect_targ_addr =
1593 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1594
1595 /* Supply Target-side CE configuration */
1596 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1597 &pcie_state_targ_addr);
1598 if (ret != 0) {
1599 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1600 return ret;
1601 }
1602
1603 if (pcie_state_targ_addr == 0) {
1604 ret = -EIO;
1605 ath10k_err("Invalid pcie state addr\n");
1606 return ret;
1607 }
1608
1609 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1610 offsetof(struct pcie_state,
1611 pipe_cfg_addr),
1612 &pipe_cfg_targ_addr);
1613 if (ret != 0) {
1614 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1615 return ret;
1616 }
1617
1618 if (pipe_cfg_targ_addr == 0) {
1619 ret = -EIO;
1620 ath10k_err("Invalid pipe cfg addr\n");
1621 return ret;
1622 }
1623
1624 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1625 target_ce_config_wlan,
1626 sizeof(target_ce_config_wlan));
1627
1628 if (ret != 0) {
1629 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1630 return ret;
1631 }
1632
1633 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1634 offsetof(struct pcie_state,
1635 svc_to_pipe_map),
1636 &svc_to_pipe_map);
1637 if (ret != 0) {
1638 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1639 return ret;
1640 }
1641
1642 if (svc_to_pipe_map == 0) {
1643 ret = -EIO;
1644 ath10k_err("Invalid svc_to_pipe map\n");
1645 return ret;
1646 }
1647
1648 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1649 target_service_to_ce_map_wlan,
1650 sizeof(target_service_to_ce_map_wlan));
1651 if (ret != 0) {
1652 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1653 return ret;
1654 }
1655
1656 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1657 offsetof(struct pcie_state,
1658 config_flags),
1659 &pcie_config_flags);
1660 if (ret != 0) {
1661 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1662 return ret;
1663 }
1664
1665 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1666
1667 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1668 offsetof(struct pcie_state, config_flags),
1669 &pcie_config_flags,
1670 sizeof(pcie_config_flags));
1671 if (ret != 0) {
1672 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1673 return ret;
1674 }
1675
1676 /* configure early allocation */
1677 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1678
1679 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1680 if (ret != 0) {
1681 ath10k_err("Faile to get early alloc val: %d\n", ret);
1682 return ret;
1683 }
1684
1685 /* first bank is switched to IRAM */
1686 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1687 HI_EARLY_ALLOC_MAGIC_MASK);
1688 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1689 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1690
1691 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1692 if (ret != 0) {
1693 ath10k_err("Failed to set early alloc val: %d\n", ret);
1694 return ret;
1695 }
1696
1697 /* Tell Target to proceed with initialization */
1698 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1699
1700 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1701 if (ret != 0) {
1702 ath10k_err("Failed to get option val: %d\n", ret);
1703 return ret;
1704 }
1705
1706 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1707
1708 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1709 if (ret != 0) {
1710 ath10k_err("Failed to set option val: %d\n", ret);
1711 return ret;
1712 }
1713
1714 return 0;
1715}
1716
25d0dbcb
MK		 1717static int ath10k_pci_alloc_ce(struct ath10k *ar)
1718{
1719 int i, ret;
1720
1721 for (i = 0; i < CE_COUNT; i++) {
1722 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1723 if (ret) {
1724 ath10k_err("failed to allocate copy engine pipe %d: %d\n",
1725 i, ret);
1726 return ret;
1727 }
1728 }
1729
1730 return 0;
1731}
1732
1733static void ath10k_pci_free_ce(struct ath10k *ar)
1734{
1735 int i;
5e3dd157 1736
25d0dbcb
MK		 1737 for (i = 0; i < CE_COUNT; i++)
1738 ath10k_ce_free_pipe(ar, i);
1739}
5e3dd157
KV		 1740
1741static int ath10k_pci_ce_init(struct ath10k *ar)
1742{
1743 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
87263e5b 1744 struct ath10k_pci_pipe *pipe_info;
5e3dd157 1745 const struct ce_attr *attr;
25d0dbcb 1746 int pipe_num, ret;
5e3dd157 1747
fad6ed78 1748 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
5e3dd157 1749 pipe_info = &ar_pci->pipe_info[pipe_num];
25d0dbcb 1750 pipe_info->ce_hdl = &ar_pci->ce_states[pipe_num];
5e3dd157
KV		 1751 pipe_info->pipe_num = pipe_num;
1752 pipe_info->hif_ce_state = ar;
1753 attr = &host_ce_config_wlan[pipe_num];
1754
25d0dbcb
MK		 1755 ret = ath10k_ce_init_pipe(ar, pipe_num, attr);
1756 if (ret) {
1757 ath10k_err("failed to initialize copy engine pipe %d: %d\n",
1758 pipe_num, ret);
1759 return ret;
5e3dd157
KV		 1760 }
1761
fad6ed78 1762 if (pipe_num == CE_COUNT - 1) {
5e3dd157
KV		 1763 /*
1764 * Reserve the ultimate CE for
1765 * diagnostic Window support
1766 */
fad6ed78 1767 ar_pci->ce_diag = pipe_info->ce_hdl;
5e3dd157
KV		 1768 continue;
1769 }
1770
1771 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1772 }
1773
5e3dd157
KV		 1774 return 0;
1775}
1776
1777static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1778{
1779 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
b39712ce 1780 u32 fw_indicator;
5e3dd157
KV		 1781
1782 ath10k_pci_wake(ar);
1783
b39712ce 1784 fw_indicator = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
5e3dd157
KV		 1785
1786 if (fw_indicator & FW_IND_EVENT_PENDING) {
1787 /* ACK: clear Target-side pending event */
b39712ce 1788 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
5e3dd157
KV		 1789 fw_indicator & ~FW_IND_EVENT_PENDING);
1790
1791 if (ar_pci->started) {
1792 ath10k_pci_hif_dump_area(ar);
1793 } else {
1794 /*
1795 * Probable Target failure before we're prepared
1796 * to handle it. Generally unexpected.
1797 */
1798 ath10k_warn("early firmware event indicated\n");
1799 }
1800 }
1801
1802 ath10k_pci_sleep(ar);
1803}
1804
fc36e3ff
MK		 1805static int ath10k_pci_warm_reset(struct ath10k *ar)
1806{
fc36e3ff
MK		 1807 int ret = 0;
1808 u32 val;
1809
50f87a67 1810 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset\n");
fc36e3ff
MK		 1811
1812 ret = ath10k_do_pci_wake(ar);
1813 if (ret) {
1814 ath10k_err("failed to wake up target: %d\n", ret);
1815 return ret;
1816 }
1817
1818 /* debug */
1819 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1820 PCIE_INTR_CAUSE_ADDRESS);
1821 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val);
1822
1823 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1824 CPU_INTR_ADDRESS);
1825 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1826 val);
1827
1828 /* disable pending irqs */
1829 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1830 PCIE_INTR_ENABLE_ADDRESS, 0);
1831
1832 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1833 PCIE_INTR_CLR_ADDRESS, ~0);
1834
1835 msleep(100);
1836
1837 /* clear fw indicator */
b39712ce 1838 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
fc36e3ff
MK		 1839
1840 /* clear target LF timer interrupts */
1841 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1842 SOC_LF_TIMER_CONTROL0_ADDRESS);
1843 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
1844 SOC_LF_TIMER_CONTROL0_ADDRESS,
1845 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
1846
1847 /* reset CE */
1848 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1849 SOC_RESET_CONTROL_ADDRESS);
1850 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1851 val | SOC_RESET_CONTROL_CE_RST_MASK);
1852 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1853 SOC_RESET_CONTROL_ADDRESS);
1854 msleep(10);
1855
1856 /* unreset CE */
1857 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1858 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
1859 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1860 SOC_RESET_CONTROL_ADDRESS);
1861 msleep(10);
1862
1863 /* debug */
1864 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1865 PCIE_INTR_CAUSE_ADDRESS);
1866 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val);
1867
1868 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1869 CPU_INTR_ADDRESS);
1870 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1871 val);
1872
1873 /* CPU warm reset */
1874 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1875 SOC_RESET_CONTROL_ADDRESS);
1876 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1877 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
1878
1879 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1880 SOC_RESET_CONTROL_ADDRESS);
1881 ath10k_dbg(ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n", val);
1882
1883 msleep(100);
1884
1885 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset complete\n");
1886
1887 ath10k_do_pci_sleep(ar);
1888 return ret;
1889}
1890
1891static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
8c5c5368 1892{
8cc8df90 1893 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
95cbb6a8 1894 const char *irq_mode;
8c5c5368
MK		 1895 int ret;
1896
1897 /*
1898 * Bring the target up cleanly.
1899 *
1900 * The target may be in an undefined state with an AUX-powered Target
1901 * and a Host in WoW mode. If the Host crashes, loses power, or is
1902 * restarted (without unloading the driver) then the Target is left
1903 * (aux) powered and running. On a subsequent driver load, the Target
1904 * is in an unexpected state. We try to catch that here in order to
1905 * reset the Target and retry the probe.
1906 */
fc36e3ff
MK		 1907 if (cold_reset)
1908 ret = ath10k_pci_cold_reset(ar);
1909 else
1910 ret = ath10k_pci_warm_reset(ar);
1911
5b2589fc
MK		 1912 if (ret) {
1913 ath10k_err("failed to reset target: %d\n", ret);
98563d5a 1914 goto err;
5b2589fc 1915 }
8c5c5368 1916
8cc8df90 1917 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368 1918 /* Force AWAKE forever */
8c5c5368 1919 ath10k_do_pci_wake(ar);
8c5c5368
MK		 1920
1921 ret = ath10k_pci_ce_init(ar);
1d2b48d6
MK		 1922 if (ret) {
1923 ath10k_err("failed to initialize CE: %d\n", ret);
8c5c5368 1924 goto err_ps;
1d2b48d6 1925 }
8c5c5368 1926
98563d5a
MK		 1927 ret = ath10k_ce_disable_interrupts(ar);
1928 if (ret) {
1929 ath10k_err("failed to disable CE interrupts: %d\n", ret);
8c5c5368 1930 goto err_ce;
98563d5a 1931 }
8c5c5368 1932
fc15ca13 1933 ret = ath10k_pci_init_irq(ar);
8c5c5368 1934 if (ret) {
fc15ca13 1935 ath10k_err("failed to init irqs: %d\n", ret);
8c5c5368
MK		 1936 goto err_ce;
1937 }
1938
ab977bd0
MK		 1939 ret = ath10k_pci_request_early_irq(ar);
1940 if (ret) {
1941 ath10k_err("failed to request early irq: %d\n", ret);
1942 goto err_deinit_irq;
1943 }
1944
98563d5a
MK		 1945 ret = ath10k_pci_wait_for_target_init(ar);
1946 if (ret) {
1947 ath10k_err("failed to wait for target to init: %d\n", ret);
ab977bd0 1948 goto err_free_early_irq;
98563d5a
MK		 1949 }
1950
1951 ret = ath10k_pci_init_config(ar);
1952 if (ret) {
1953 ath10k_err("failed to setup init config: %d\n", ret);
ab977bd0 1954 goto err_free_early_irq;
98563d5a 1955 }
8c5c5368
MK		 1956
1957 ret = ath10k_pci_wake_target_cpu(ar);
1958 if (ret) {
1d2b48d6 1959 ath10k_err("could not wake up target CPU: %d\n", ret);
ab977bd0 1960 goto err_free_early_irq;
8c5c5368
MK		 1961 }
1962
95cbb6a8
KV		 1963 if (ar_pci->num_msi_intrs > 1)
1964 irq_mode = "MSI-X";
1965 else if (ar_pci->num_msi_intrs == 1)
1966 irq_mode = "MSI";
1967 else
1968 irq_mode = "legacy";
1969
650b91fb 1970 if (!test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
78a9cb4c
KV		 1971 ath10k_info("pci irq %s irq_mode %d reset_mode %d\n",
1972 irq_mode, ath10k_pci_irq_mode,
1973 ath10k_pci_reset_mode);
95cbb6a8 1974
8c5c5368
MK		 1975 return 0;
1976
ab977bd0
MK		 1977err_free_early_irq:
1978 ath10k_pci_free_early_irq(ar);
fc15ca13
MK		 1979err_deinit_irq:
1980 ath10k_pci_deinit_irq(ar);
8c5c5368
MK		 1981err_ce:
1982 ath10k_pci_ce_deinit(ar);
fc36e3ff 1983 ath10k_pci_warm_reset(ar);
8c5c5368 1984err_ps:
8cc8df90 1985 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368
MK		 1986 ath10k_do_pci_sleep(ar);
1987err:
1988 return ret;
1989}
1990
fc36e3ff
MK		 1991static int ath10k_pci_hif_power_up(struct ath10k *ar)
1992{
1993 int ret;
1994
50f87a67
KV		 1995 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power up\n");
1996
fc36e3ff
MK		 1997 /*
1998 * Hardware CUS232 version 2 has some issues with cold reset and the
1999 * preferred (and safer) way to perform a device reset is through a
2000 * warm reset.
2001 *
2002 * Warm reset doesn't always work though (notably after a firmware
2003 * crash) so fall back to cold reset if necessary.
2004 */
2005 ret = __ath10k_pci_hif_power_up(ar, false);
2006 if (ret) {
35098463 2007 ath10k_warn("failed to power up target using warm reset: %d\n",
fc36e3ff
MK		 2008 ret);
2009
35098463
KV		 2010 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY)
2011 return ret;
2012
2013 ath10k_warn("trying cold reset\n");
2014
fc36e3ff
MK		 2015 ret = __ath10k_pci_hif_power_up(ar, true);
2016 if (ret) {
2017 ath10k_err("failed to power up target using cold reset too (%d)\n",
2018 ret);
2019 return ret;
2020 }
2021 }
2022
2023 return 0;
2024}
2025
8c5c5368
MK		 2026static void ath10k_pci_hif_power_down(struct ath10k *ar)
2027{
8cc8df90
BM		 2028 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2029
50f87a67
KV		 2030 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power down\n");
2031
ab977bd0
MK		 2032 ath10k_pci_free_early_irq(ar);
2033 ath10k_pci_kill_tasklet(ar);
fc15ca13 2034 ath10k_pci_deinit_irq(ar);
df5e8525 2035 ath10k_pci_ce_deinit(ar);
fc36e3ff 2036 ath10k_pci_warm_reset(ar);
8cc8df90 2037
8cc8df90 2038 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
8c5c5368
MK		 2039 ath10k_do_pci_sleep(ar);
2040}
2041
8cd13cad
MK		 2042#ifdef CONFIG_PM
2043
2044#define ATH10K_PCI_PM_CONTROL 0x44
2045
2046static int ath10k_pci_hif_suspend(struct ath10k *ar)
2047{
2048 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2049 struct pci_dev *pdev = ar_pci->pdev;
2050 u32 val;
2051
2052 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
2053
2054 if ((val & 0x000000ff) != 0x3) {
2055 pci_save_state(pdev);
2056 pci_disable_device(pdev);
2057 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
2058 (val & 0xffffff00) | 0x03);
2059 }
2060
2061 return 0;
2062}
2063
2064static int ath10k_pci_hif_resume(struct ath10k *ar)
2065{
2066 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2067 struct pci_dev *pdev = ar_pci->pdev;
2068 u32 val;
2069
2070 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
2071
2072 if ((val & 0x000000ff) != 0) {
2073 pci_restore_state(pdev);
2074 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
2075 val & 0xffffff00);
2076 /*
2077 * Suspend/Resume resets the PCI configuration space,
2078 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
2079 * to keep PCI Tx retries from interfering with C3 CPU state
2080 */
2081 pci_read_config_dword(pdev, 0x40, &val);
2082
2083 if ((val & 0x0000ff00) != 0)
2084 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2085 }
2086
2087 return 0;
2088}
2089#endif
2090
5e3dd157 2091static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
726346fc 2092 .tx_sg = ath10k_pci_hif_tx_sg,
5e3dd157
KV		 2093 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2094 .start = ath10k_pci_hif_start,
2095 .stop = ath10k_pci_hif_stop,
2096 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2097 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2098 .send_complete_check = ath10k_pci_hif_send_complete_check,
e799bbff 2099 .set_callbacks = ath10k_pci_hif_set_callbacks,
5e3dd157 2100 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
8c5c5368
MK		 2101 .power_up = ath10k_pci_hif_power_up,
2102 .power_down = ath10k_pci_hif_power_down,
8cd13cad
MK		 2103#ifdef CONFIG_PM
2104 .suspend = ath10k_pci_hif_suspend,
2105 .resume = ath10k_pci_hif_resume,
2106#endif
5e3dd157
KV		 2107};
2108
2109static void ath10k_pci_ce_tasklet(unsigned long ptr)
2110{
87263e5b 2111 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
5e3dd157
KV		 2112 struct ath10k_pci *ar_pci = pipe->ar_pci;
2113
2114 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2115}
2116
2117static void ath10k_msi_err_tasklet(unsigned long data)
2118{
2119 struct ath10k *ar = (struct ath10k *)data;
2120
2121 ath10k_pci_fw_interrupt_handler(ar);
2122}
2123
2124/*
2125 * Handler for a per-engine interrupt on a PARTICULAR CE.
2126 * This is used in cases where each CE has a private MSI interrupt.
2127 */
2128static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2129{
2130 struct ath10k *ar = arg;
2131 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2132 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2133
e5742672 2134 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
5e3dd157
KV		 2135 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
2136 return IRQ_HANDLED;
2137 }
2138
2139 /*
2140 * NOTE: We are able to derive ce_id from irq because we
2141 * use a one-to-one mapping for CE's 0..5.
2142 * CE's 6 & 7 do not use interrupts at all.
2143 *
2144 * This mapping must be kept in sync with the mapping
2145 * used by firmware.
2146 */
2147 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2148 return IRQ_HANDLED;
2149}
2150
2151static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2152{
2153 struct ath10k *ar = arg;
2154 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2155
2156 tasklet_schedule(&ar_pci->msi_fw_err);
2157 return IRQ_HANDLED;
2158}
2159
2160/*
2161 * Top-level interrupt handler for all PCI interrupts from a Target.
2162 * When a block of MSI interrupts is allocated, this top-level handler
2163 * is not used; instead, we directly call the correct sub-handler.
2164 */
2165static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2166{
2167 struct ath10k *ar = arg;
2168 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2169
2170 if (ar_pci->num_msi_intrs == 0) {
e539887b
MK		 2171 if (!ath10k_pci_irq_pending(ar))
2172 return IRQ_NONE;
2173
2685218b 2174 ath10k_pci_disable_and_clear_legacy_irq(ar);
5e3dd157
KV		 2175 }
2176
2177 tasklet_schedule(&ar_pci->intr_tq);
2178
2179 return IRQ_HANDLED;
2180}
2181
ab977bd0
MK		 2182static void ath10k_pci_early_irq_tasklet(unsigned long data)
2183{
2184 struct ath10k *ar = (struct ath10k *)data;
ab977bd0
MK		 2185 u32 fw_ind;
2186 int ret;
2187
2188 ret = ath10k_pci_wake(ar);
2189 if (ret) {
2190 ath10k_warn("failed to wake target in early irq tasklet: %d\n",
2191 ret);
2192 return;
2193 }
2194
b39712ce 2195 fw_ind = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
ab977bd0 2196 if (fw_ind & FW_IND_EVENT_PENDING) {
b39712ce 2197 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
ab977bd0
MK		 2198 fw_ind & ~FW_IND_EVENT_PENDING);
2199
2200 /* Some structures are unavailable during early boot or at
2201 * driver teardown so just print that the device has crashed. */
2202 ath10k_warn("device crashed - no diagnostics available\n");
2203 }
2204
2205 ath10k_pci_sleep(ar);
2206 ath10k_pci_enable_legacy_irq(ar);
2207}
2208
5e3dd157
KV		 2209static void ath10k_pci_tasklet(unsigned long data)
2210{
2211 struct ath10k *ar = (struct ath10k *)data;
2212 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2213
2214 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2215 ath10k_ce_per_engine_service_any(ar);
2216
2685218b
MK		 2217 /* Re-enable legacy irq that was disabled in the irq handler */
2218 if (ar_pci->num_msi_intrs == 0)
2219 ath10k_pci_enable_legacy_irq(ar);
5e3dd157
KV		 2220}
2221
fc15ca13 2222static int ath10k_pci_request_irq_msix(struct ath10k *ar)
5e3dd157
KV		 2223{
2224 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
fc15ca13 2225 int ret, i;
5e3dd157
KV		 2226
2227 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2228 ath10k_pci_msi_fw_handler,
2229 IRQF_SHARED, "ath10k_pci", ar);
591ecdb8 2230 if (ret) {
fc15ca13 2231 ath10k_warn("failed to request MSI-X fw irq %d: %d\n",
591ecdb8 2232 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
5e3dd157 2233 return ret;
591ecdb8 2234 }
5e3dd157
KV		 2235
2236 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2237 ret = request_irq(ar_pci->pdev->irq + i,
2238 ath10k_pci_per_engine_handler,
2239 IRQF_SHARED, "ath10k_pci", ar);
2240 if (ret) {
fc15ca13 2241 ath10k_warn("failed to request MSI-X ce irq %d: %d\n",
5e3dd157
KV		 2242 ar_pci->pdev->irq + i, ret);
2243
87b1423b
MK		 2244 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2245 free_irq(ar_pci->pdev->irq + i, ar);
5e3dd157 2246
87b1423b 2247 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
5e3dd157
KV		 2248 return ret;
2249 }
2250 }
2251
5e3dd157
KV		 2252 return 0;
2253}
2254
fc15ca13 2255static int ath10k_pci_request_irq_msi(struct ath10k *ar)
5e3dd157
KV		 2256{
2257 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2258 int ret;
2259
5e3dd157
KV		 2260 ret = request_irq(ar_pci->pdev->irq,
2261 ath10k_pci_interrupt_handler,
2262 IRQF_SHARED, "ath10k_pci", ar);
fc15ca13
MK		 2263 if (ret) {
2264 ath10k_warn("failed to request MSI irq %d: %d\n",
2265 ar_pci->pdev->irq, ret);
5e3dd157
KV		 2266 return ret;
2267 }
2268
5e3dd157
KV		 2269 return 0;
2270}
2271
fc15ca13 2272static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
5e3dd157
KV		 2273{
2274 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2275 int ret;
2276
2277 ret = request_irq(ar_pci->pdev->irq,
2278 ath10k_pci_interrupt_handler,
2279 IRQF_SHARED, "ath10k_pci", ar);
f3782744 2280 if (ret) {
fc15ca13
MK		 2281 ath10k_warn("failed to request legacy irq %d: %d\n",
2282 ar_pci->pdev->irq, ret);
5e3dd157 2283 return ret;
f3782744 2284 }
5e3dd157 2285
5e3dd157
KV		 2286 return 0;
2287}
2288
fc15ca13
MK		 2289static int ath10k_pci_request_irq(struct ath10k *ar)
2290{
2291 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 2292
fc15ca13
MK		 2293 switch (ar_pci->num_msi_intrs) {
2294 case 0:
2295 return ath10k_pci_request_irq_legacy(ar);
2296 case 1:
2297 return ath10k_pci_request_irq_msi(ar);
2298 case MSI_NUM_REQUEST:
2299 return ath10k_pci_request_irq_msix(ar);
2300 }
5e3dd157 2301
fc15ca13
MK		 2302 ath10k_warn("unknown irq configuration upon request\n");
2303 return -EINVAL;
5e3dd157
KV		 2304}
2305
fc15ca13
MK		 2306static void ath10k_pci_free_irq(struct ath10k *ar)
2307{
2308 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2309 int i;
2310
2311 /* There's at least one interrupt irregardless whether its legacy INTR
2312 * or MSI or MSI-X */
2313 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2314 free_irq(ar_pci->pdev->irq + i, ar);
2315}
2316
2317static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
5e3dd157
KV		 2318{
2319 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157
KV		 2320 int i;
2321
fc15ca13 2322 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
5e3dd157 2323 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
fc15ca13 2324 (unsigned long)ar);
ab977bd0
MK		 2325 tasklet_init(&ar_pci->early_irq_tasklet, ath10k_pci_early_irq_tasklet,
2326 (unsigned long)ar);
5e3dd157
KV		 2327
2328 for (i = 0; i < CE_COUNT; i++) {
2329 ar_pci->pipe_info[i].ar_pci = ar_pci;
fc15ca13 2330 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
5e3dd157
KV		 2331 (unsigned long)&ar_pci->pipe_info[i]);
2332 }
fc15ca13
MK		 2333}
2334
2335static int ath10k_pci_init_irq(struct ath10k *ar)
2336{
2337 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
cfe9c45b
MK		 2338 bool msix_supported = test_bit(ATH10K_PCI_FEATURE_MSI_X,
2339 ar_pci->features);
fc15ca13 2340 int ret;
5e3dd157 2341
fc15ca13 2342 ath10k_pci_init_irq_tasklets(ar);
5e3dd157 2343
cfe9c45b
MK		 2344 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO &&
2345 !test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
2346 ath10k_info("limiting irq mode to: %d\n", ath10k_pci_irq_mode);
5e3dd157 2347
fc15ca13 2348 /* Try MSI-X */
cfe9c45b
MK		 2349 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO && msix_supported) {
2350 ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
5ad6867c
AG		 2351 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2352 ar_pci->num_msi_intrs);
2353 if (ret > 0)
cfe9c45b 2354 return 0;
5e3dd157 2355
cfe9c45b 2356 /* fall-through */
5e3dd157
KV		 2357 }
2358
fc15ca13 2359 /* Try MSI */
cfe9c45b
MK		 2360 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2361 ar_pci->num_msi_intrs = 1;
2362 ret = pci_enable_msi(ar_pci->pdev);
5e3dd157 2363 if (ret == 0)
cfe9c45b 2364 return 0;
5e3dd157 2365
cfe9c45b 2366 /* fall-through */
5e3dd157
KV		 2367 }
2368
fc15ca13
MK		 2369 /* Try legacy irq
2370 *
2371 * A potential race occurs here: The CORE_BASE write
2372 * depends on target correctly decoding AXI address but
2373 * host won't know when target writes BAR to CORE_CTRL.
2374 * This write might get lost if target has NOT written BAR.
2375 * For now, fix the race by repeating the write in below
2376 * synchronization checking. */
2377 ar_pci->num_msi_intrs = 0;
5e3dd157 2378
fc15ca13
MK		 2379 ret = ath10k_pci_wake(ar);
2380 if (ret) {
2381 ath10k_warn("failed to wake target: %d\n", ret);
2382 return ret;
5e3dd157
KV		 2383 }
2384
fc15ca13
MK		 2385 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2386 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2387 ath10k_pci_sleep(ar);
2388
2389 return 0;
5e3dd157
KV		 2390}
2391
fc15ca13 2392static int ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
5e3dd157 2393{
fc15ca13 2394 int ret;
5e3dd157 2395
fc15ca13 2396 ret = ath10k_pci_wake(ar);
f3782744 2397 if (ret) {
fc15ca13 2398 ath10k_warn("failed to wake target: %d\n", ret);
f3782744
KV		 2399 return ret;
2400 }
5e3dd157 2401
fc15ca13
MK		 2402 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2403 0);
2404 ath10k_pci_sleep(ar);
2405
2406 return 0;
5e3dd157
KV		 2407}
2408
fc15ca13 2409static int ath10k_pci_deinit_irq(struct ath10k *ar)
5e3dd157
KV		 2410{
2411 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
5e3dd157 2412
fc15ca13
MK		 2413 switch (ar_pci->num_msi_intrs) {
2414 case 0:
2415 return ath10k_pci_deinit_irq_legacy(ar);
2416 case 1:
2417 /* fall-through */
2418 case MSI_NUM_REQUEST:
5e3dd157 2419 pci_disable_msi(ar_pci->pdev);
fc15ca13 2420 return 0;
bb8b621a
AG		 2421 default:
2422 pci_disable_msi(ar_pci->pdev);
fc15ca13
MK		 2423 }
2424
2425 ath10k_warn("unknown irq configuration upon deinit\n");
2426 return -EINVAL;
5e3dd157
KV		 2427}
2428
d7fb47f5 2429static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
5e3dd157
KV		 2430{
2431 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
0399eca8 2432 unsigned long timeout;
f3782744 2433 int ret;
0399eca8 2434 u32 val;
5e3dd157 2435
50f87a67
KV		 2436 ath10k_dbg(ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2437
98563d5a 2438 ret = ath10k_pci_wake(ar);
f3782744 2439 if (ret) {
0399eca8 2440 ath10k_err("failed to wake up target for init: %d\n", ret);
f3782744
KV		 2441 return ret;
2442 }
5e3dd157 2443
0399eca8
KV		 2444 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2445
2446 do {
2447 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2448
50f87a67
KV		 2449 ath10k_dbg(ATH10K_DBG_BOOT, "boot target indicator %x\n", val);
2450
0399eca8
KV		 2451 /* target should never return this */
2452 if (val == 0xffffffff)
2453 continue;
2454
7710cd2e
MK		 2455 /* the device has crashed so don't bother trying anymore */
2456 if (val & FW_IND_EVENT_PENDING)
2457 break;
2458
0399eca8
KV		 2459 if (val & FW_IND_INITIALIZED)
2460 break;
2461
5e3dd157
KV		 2462 if (ar_pci->num_msi_intrs == 0)
2463 /* Fix potential race by repeating CORE_BASE writes */
0399eca8
KV		 2464 ath10k_pci_soc_write32(ar, PCIE_INTR_ENABLE_ADDRESS,
2465 PCIE_INTR_FIRMWARE_MASK |
2466 PCIE_INTR_CE_MASK_ALL);
2467
5e3dd157 2468 mdelay(10);
0399eca8 2469 } while (time_before(jiffies, timeout));
5e3dd157 2470
6a4f6e1d
MK		 2471 if (val == 0xffffffff) {
2472 ath10k_err("failed to read device register, device is gone\n");
2473 ret = -EIO;
2474 goto out;
2475 }
2476
7710cd2e
MK		 2477 if (val & FW_IND_EVENT_PENDING) {
2478 ath10k_warn("device has crashed during init\n");
2479 ret = -ECOMM;
2480 goto out;
2481 }
2482
6a4f6e1d 2483 if (!(val & FW_IND_INITIALIZED)) {
0399eca8
KV		 2484 ath10k_err("failed to receive initialized event from target: %08x\n",
2485 val);
2486 ret = -ETIMEDOUT;
5b2589fc 2487 goto out;
5e3dd157
KV		 2488 }
2489
50f87a67
KV		 2490 ath10k_dbg(ATH10K_DBG_BOOT, "boot target initialised\n");
2491
5b2589fc 2492out:
98563d5a 2493 ath10k_pci_sleep(ar);
5b2589fc 2494 return ret;
5e3dd157
KV		 2495}
2496
fc36e3ff 2497static int ath10k_pci_cold_reset(struct ath10k *ar)
5e3dd157 2498{
5b2589fc 2499 int i, ret;
5e3dd157
KV		 2500 u32 val;
2501
50f87a67
KV		 2502 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset\n");
2503
5b2589fc
MK		 2504 ret = ath10k_do_pci_wake(ar);
2505 if (ret) {
2506 ath10k_err("failed to wake up target: %d\n",
2507 ret);
2508 return ret;
5e3dd157
KV		 2509 }
2510
2511 /* Put Target, including PCIe, into RESET. */
e479ed43 2512 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
5e3dd157 2513 val |= 1;
e479ed43 2514 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
5e3dd157
KV		 2515
2516 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
e479ed43 2517 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
5e3dd157
KV		 2518 RTC_STATE_COLD_RESET_MASK)
2519 break;
2520 msleep(1);
2521 }
2522
2523 /* Pull Target, including PCIe, out of RESET. */
2524 val &= ~1;
e479ed43 2525 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
5e3dd157
KV		 2526
2527 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
e479ed43 2528 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
5e3dd157
KV		 2529 RTC_STATE_COLD_RESET_MASK))
2530 break;
2531 msleep(1);
2532 }
2533
5b2589fc 2534 ath10k_do_pci_sleep(ar);
50f87a67
KV		 2535
2536 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset complete\n");
2537
5b2589fc 2538 return 0;
5e3dd157
KV		 2539}
2540
2541static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2542{
2543 int i;
2544
2545 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2546 if (!test_bit(i, ar_pci->features))
2547 continue;
2548
2549 switch (i) {
2550 case ATH10K_PCI_FEATURE_MSI_X:
24cfade1 2551 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
5e3dd157 2552 break;
8cc8df90 2553 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
24cfade1 2554 ath10k_dbg(ATH10K_DBG_BOOT, "QCA98XX SoC power save enabled\n");
8cc8df90 2555 break;
5e3dd157
KV		 2556 }
2557 }
2558}
2559
2560static int ath10k_pci_probe(struct pci_dev *pdev,
2561 const struct pci_device_id *pci_dev)
2562{
2563 void __iomem *mem;
2564 int ret = 0;
2565 struct ath10k *ar;
2566 struct ath10k_pci *ar_pci;
e01ae68c 2567 u32 lcr_val, chip_id;
5e3dd157 2568
50f87a67 2569 ath10k_dbg(ATH10K_DBG_PCI, "pci probe\n");
5e3dd157
KV		 2570
2571 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2572 if (ar_pci == NULL)
2573 return -ENOMEM;
2574
2575 ar_pci->pdev = pdev;
2576 ar_pci->dev = &pdev->dev;
2577
2578 switch (pci_dev->device) {
5e3dd157
KV		 2579 case QCA988X_2_0_DEVICE_ID:
2580 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2581 break;
2582 default:
2583 ret = -ENODEV;
6d3be300 2584 ath10k_err("Unknown device ID: %d\n", pci_dev->device);
5e3dd157
KV		 2585 goto err_ar_pci;
2586 }
2587
e42c1fbd 2588 if (ath10k_pci_target_ps)
8cc8df90
BM		 2589 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2590
5e3dd157
KV		 2591 ath10k_pci_dump_features(ar_pci);
2592
3a0861ff 2593 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
5e3dd157 2594 if (!ar) {
1d2b48d6 2595 ath10k_err("failed to create driver core\n");
5e3dd157
KV		 2596 ret = -EINVAL;
2597 goto err_ar_pci;
2598 }
2599
5e3dd157 2600 ar_pci->ar = ar;
5e3dd157
KV		 2601 atomic_set(&ar_pci->keep_awake_count, 0);
2602
2603 pci_set_drvdata(pdev, ar);
2604
2605 /*
2606 * Without any knowledge of the Host, the Target may have been reset or
2607 * power cycled and its Config Space may no longer reflect the PCI
2608 * address space that was assigned earlier by the PCI infrastructure.
2609 * Refresh it now.
2610 */
2611 ret = pci_assign_resource(pdev, BAR_NUM);
2612 if (ret) {
1d2b48d6 2613 ath10k_err("failed to assign PCI space: %d\n", ret);
5e3dd157
KV		 2614 goto err_ar;
2615 }
2616
2617 ret = pci_enable_device(pdev);
2618 if (ret) {
1d2b48d6 2619 ath10k_err("failed to enable PCI device: %d\n", ret);
5e3dd157
KV		 2620 goto err_ar;
2621 }
2622
2623 /* Request MMIO resources */
2624 ret = pci_request_region(pdev, BAR_NUM, "ath");
2625 if (ret) {
1d2b48d6 2626 ath10k_err("failed to request MMIO region: %d\n", ret);
5e3dd157
KV		 2627 goto err_device;
2628 }
2629
2630 /*
2631 * Target structures have a limit of 32 bit DMA pointers.
2632 * DMA pointers can be wider than 32 bits by default on some systems.
2633 */
2634 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2635 if (ret) {
1d2b48d6 2636 ath10k_err("failed to set DMA mask to 32-bit: %d\n", ret);
5e3dd157
KV		 2637 goto err_region;
2638 }
2639
2640 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2641 if (ret) {
1d2b48d6 2642 ath10k_err("failed to set consistent DMA mask to 32-bit\n");
5e3dd157
KV		 2643 goto err_region;
2644 }
2645
2646 /* Set bus master bit in PCI_COMMAND to enable DMA */
2647 pci_set_master(pdev);
2648
2649 /*
2650 * Temporary FIX: disable ASPM
2651 * Will be removed after the OTP is programmed
2652 */
2653 pci_read_config_dword(pdev, 0x80, &lcr_val);
2654 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2655
2656 /* Arrange for access to Target SoC registers. */
2657 mem = pci_iomap(pdev, BAR_NUM, 0);
2658 if (!mem) {
1d2b48d6 2659 ath10k_err("failed to perform IOMAP for BAR%d\n", BAR_NUM);
5e3dd157
KV		 2660 ret = -EIO;
2661 goto err_master;
2662 }
2663
2664 ar_pci->mem = mem;
2665
2666 spin_lock_init(&ar_pci->ce_lock);
2667
e01ae68c
KV		 2668 ret = ath10k_do_pci_wake(ar);
2669 if (ret) {
2670 ath10k_err("Failed to get chip id: %d\n", ret);
12eb0879 2671 goto err_iomap;
e01ae68c
KV		 2672 }
2673
233eb97f 2674 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
e01ae68c
KV		 2675
2676 ath10k_do_pci_sleep(ar);
2677
25d0dbcb
MK		 2678 ret = ath10k_pci_alloc_ce(ar);
2679 if (ret) {
2680 ath10k_err("failed to allocate copy engine pipes: %d\n", ret);
2681 goto err_iomap;
2682 }
2683
24cfade1
KV		 2684 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2685
e01ae68c 2686 ret = ath10k_core_register(ar, chip_id);
5e3dd157 2687 if (ret) {
1d2b48d6 2688 ath10k_err("failed to register driver core: %d\n", ret);
25d0dbcb 2689 goto err_free_ce;
5e3dd157
KV		 2690 }
2691
2692 return 0;
2693
25d0dbcb
MK		 2694err_free_ce:
2695 ath10k_pci_free_ce(ar);
5e3dd157
KV		 2696err_iomap:
2697 pci_iounmap(pdev, mem);
2698err_master:
2699 pci_clear_master(pdev);
2700err_region:
2701 pci_release_region(pdev, BAR_NUM);
2702err_device:
2703 pci_disable_device(pdev);
2704err_ar:
5e3dd157
KV		 2705 ath10k_core_destroy(ar);
2706err_ar_pci:
2707 /* call HIF PCI free here */
2708 kfree(ar_pci);
2709
2710 return ret;
2711}
2712
2713static void ath10k_pci_remove(struct pci_dev *pdev)
2714{
2715 struct ath10k *ar = pci_get_drvdata(pdev);
2716 struct ath10k_pci *ar_pci;
2717
50f87a67 2718 ath10k_dbg(ATH10K_DBG_PCI, "pci remove\n");
5e3dd157
KV		 2719
2720 if (!ar)
2721 return;
2722
2723 ar_pci = ath10k_pci_priv(ar);
2724
2725 if (!ar_pci)
2726 return;
2727
2728 tasklet_kill(&ar_pci->msi_fw_err);
2729
2730 ath10k_core_unregister(ar);
25d0dbcb 2731 ath10k_pci_free_ce(ar);
5e3dd157 2732
5e3dd157
KV		 2733 pci_iounmap(pdev, ar_pci->mem);
2734 pci_release_region(pdev, BAR_NUM);
2735 pci_clear_master(pdev);
2736 pci_disable_device(pdev);
2737
2738 ath10k_core_destroy(ar);
2739 kfree(ar_pci);
2740}
2741
5e3dd157
KV		 2742MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2743
2744static struct pci_driver ath10k_pci_driver = {
2745 .name = "ath10k_pci",
2746 .id_table = ath10k_pci_id_table,
2747 .probe = ath10k_pci_probe,
2748 .remove = ath10k_pci_remove,
5e3dd157
KV		 2749};
2750
2751static int __init ath10k_pci_init(void)
2752{
2753 int ret;
2754
2755 ret = pci_register_driver(&ath10k_pci_driver);
2756 if (ret)
1d2b48d6 2757 ath10k_err("failed to register PCI driver: %d\n", ret);
5e3dd157
KV		 2758
2759 return ret;
2760}
2761module_init(ath10k_pci_init);
2762
2763static void __exit ath10k_pci_exit(void)
2764{
2765 pci_unregister_driver(&ath10k_pci_driver);
2766}
2767
2768module_exit(ath10k_pci_exit);
2769
2770MODULE_AUTHOR("Qualcomm Atheros");
2771MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2772MODULE_LICENSE("Dual BSD/GPL");
929417cf 2773MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_2_FILE);
5e3dd157 2774MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
Linux kernel - Deliverables
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