projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / ath5k.h
CommitLineData
fa1c114f
JS		 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
6a2a0e73 21/* TODO: Clean up channel debugging (doesn't work anyway) and start
c6e387a2 22 * working on reg. control code using all available eeprom information
6a2a0e73 23 * (rev. engineering needed) */
fa1c114f
JS		 24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
e0d687bd 27#include <linux/interrupt.h>
fa1c114f 28#include <linux/types.h>
eef39bef 29#include <linux/average.h>
e0d687bd 30#include <linux/leds.h>
fa1c114f
JS		 31#include <net/mac80211.h>
32
c6e387a2
NK		 33/* RX/TX descriptor hw structs
34 * TODO: Driver part should only see sw structs */
35#include "desc.h"
36
37/* EEPROM structs/offsets
38 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
39 * and clean up common bits, then introduce set/get functions in eeprom.c */
40#include "eeprom.h"
e0d687bd 41#include "debug.h"
db719718 42#include "../ath.h"
e0d687bd 43#include "ani.h"
fa1c114f
JS		 44
45/* PCI IDs */
0a5d3813
PR		 46#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
47#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
48#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
49#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
50#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
51#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
52#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
fa1c114f 53#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
0a5d3813
PR		 54#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
55#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
56#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
57#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
58#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
59#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
60#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
61#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
62#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
63#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
64#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
65#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
66#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
67#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
68#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
69#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
70#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
71#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
72#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
73#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
fa1c114f
JS		 74
75/****************************\
76 GENERIC DRIVER DEFINITIONS
77\****************************/
78
516304b0
JP		 79#define ATH5K_PRINTF(fmt, ...) \
80 pr_warn("%s: " fmt, __func__, ##__VA_ARGS__)
81
227842d1
JP		 82void __printf(3, 4)
83_ath5k_printk(const struct ath5k_hw *ah, const char *level,
84 const char *fmt, ...);
85
516304b0 86#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
227842d1 87 _ath5k_printk(_sc, _level, _fmt, ##__VA_ARGS__)
516304b0
JP		 88
89#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) \
90do { \
91 if (net_ratelimit()) \
92 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
93} while (0)
94
95#define ATH5K_INFO(_sc, _fmt, ...) \
fa1c114f
JS		 96 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
97
516304b0 98#define ATH5K_WARN(_sc, _fmt, ...) \
fa1c114f
JS		 99 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
100
516304b0 101#define ATH5K_ERR(_sc, _fmt, ...) \
fa1c114f
JS		 102 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
103
c6e387a2
NK		 104/*
105 * AR5K REGISTER ACCESS
106 */
107
108/* Some macros to read/write fields */
109
110/* First shift, then mask */
111#define AR5K_REG_SM(_val, _flags) \
112 (((_val) << _flags##_S) & (_flags))
113
114/* First mask, then shift */
115#define AR5K_REG_MS(_val, _flags) \
116 (((_val) & (_flags)) >> _flags##_S)
117
118/* Some registers can hold multiple values of interest. For this
119 * reason when we want to write to these registers we must first
120 * retrieve the values which we do not want to clear (lets call this
121 * old_data) and then set the register with this and our new_value:
122 * ( old_data | new_value) */
123#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
124 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
125 (((_val) << _flags##_S) & (_flags)), _reg)
126
127#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
128 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
129 (_mask)) | (_flags), _reg)
130
131#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
132 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
133
134#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
135 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
136
c6e387a2
NK		 137/* Access QCU registers per queue */
138#define AR5K_REG_READ_Q(ah, _reg, _queue) \
139 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
140
141#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
142 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
143
144#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
145 _reg |= 1 << _queue; \
146} while (0)
147
148#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
149 _reg &= ~(1 << _queue); \
150} while (0)
151
152/* Used while writing initvals */
153#define AR5K_REG_WAIT(_i) do { \
154 if (_i % 64) \
155 udelay(1); \
156} while (0)
157
fa1c114f 158/*
6a2a0e73 159 * Some tunable values (these should be changeable by the user)
c6e387a2 160 * TODO: Make use of them and add more options OR use debug/configfs
fa1c114f
JS		 161 */
162#define AR5K_TUNE_DMA_BEACON_RESP 2
163#define AR5K_TUNE_SW_BEACON_RESP 10
164#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
fa1c114f 165#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
b6127980 166#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
fa1c114f
JS		 167#define AR5K_TUNE_REGISTER_TIMEOUT 20000
168/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
169 * be the max value. */
c6e387a2 170#define AR5K_TUNE_RSSI_THRES 129
fa1c114f
JS		 171/* This must be set when setting the RSSI threshold otherwise it can
172 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
6a2a0e73
PR		 173 * the BMISS_THRES will be seen as 0, seems hardware doesn't keep
174 * track of it. Max value depends on hardware. For AR5210 this is just 7.
fa1c114f 175 * For AR5211+ this seems to be up to 255. */
c6e387a2 176#define AR5K_TUNE_BMISS_THRES 7
fa1c114f
JS		 177#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
178#define AR5K_TUNE_BEACON_INTERVAL 100
179#define AR5K_TUNE_AIFS 2
180#define AR5K_TUNE_AIFS_11B 2
181#define AR5K_TUNE_AIFS_XR 0
182#define AR5K_TUNE_CWMIN 15
183#define AR5K_TUNE_CWMIN_11B 31
184#define AR5K_TUNE_CWMIN_XR 3
185#define AR5K_TUNE_CWMAX 1023
186#define AR5K_TUNE_CWMAX_11B 1023
187#define AR5K_TUNE_CWMAX_XR 7
188#define AR5K_TUNE_NOISE_FLOOR -72
e5e2647f 189#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
8f655dde
NK		 190#define AR5K_TUNE_MAX_TXPOWER 63
191#define AR5K_TUNE_DEFAULT_TXPOWER 25
192#define AR5K_TUNE_TPC_TXPOWER false
ce169aca
NK		 193#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 60000 /* 60 sec */
194#define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT 10000 /* 10 sec */
2111ac0d 195#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
4edd761f
BR		 196#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
197
c6e387a2
NK		 198#define AR5K_INIT_CARR_SENSE_EN 1
199
200/*Swap RX/TX Descriptor for big endian archs*/
201#if defined(__BIG_ENDIAN)
202#define AR5K_INIT_CFG ( \
203 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
204)
205#else
206#define AR5K_INIT_CFG 0x00000000
207#endif
208
209/* Initial values */
e8f055f0 210#define AR5K_INIT_CYCRSSI_THR1 2
eeb8832b 211
76a9f6fd
BR		 212/* Tx retry limit defaults from standard */
213#define AR5K_INIT_RETRY_SHORT 7
214#define AR5K_INIT_RETRY_LONG 4
c6e387a2 215
3017fcab
NK		 216/* Slot time */
217#define AR5K_INIT_SLOT_TIME_TURBO 6
218#define AR5K_INIT_SLOT_TIME_DEFAULT 9
219#define AR5K_INIT_SLOT_TIME_HALF_RATE 13
220#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
221#define AR5K_INIT_SLOT_TIME_B 20
222#define AR5K_SLOT_TIME_MAX 0xffff
223
224/* SIFS */
225#define AR5K_INIT_SIFS_TURBO 6
488a5017 226#define AR5K_INIT_SIFS_DEFAULT_BG 10
3017fcab
NK		 227#define AR5K_INIT_SIFS_DEFAULT_A 16
228#define AR5K_INIT_SIFS_HALF_RATE 32
229#define AR5K_INIT_SIFS_QUARTER_RATE 64
230
61cde037
NK		 231/* Used to calculate tx time for non 5/10/40MHz
232 * operation */
233/* It's preamble time + signal time (16 + 4) */
234#define AR5K_INIT_OFDM_PREAMPLE_TIME 20
235/* Preamble time for 40MHz (turbo) operation (min ?) */
236#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14
237#define AR5K_INIT_OFDM_SYMBOL_TIME 4
238#define AR5K_INIT_OFDM_PLCP_BITS 22
239
c2975602
NK		 240/* Rx latency for 5 and 10MHz operation (max ?) */
241#define AR5K_INIT_RX_LAT_MAX 63
242/* Tx latencies from initvals (5212 only but no problem
243 * because we only tweak them on 5212) */
244#define AR5K_INIT_TX_LAT_A 54
245#define AR5K_INIT_TX_LAT_BG 384
246/* Tx latency for 40MHz (turbo) operation (min ?) */
247#define AR5K_INIT_TX_LAT_MIN 32
b405086b
NK		 248/* Default Tx/Rx latencies (same for 5211)*/
249#define AR5K_INIT_TX_LATENCY_5210 54
250#define AR5K_INIT_RX_LATENCY_5210 29
c2975602
NK		 251
252/* Tx frame to Tx data start delay */
253#define AR5K_INIT_TXF2TXD_START_DEFAULT 14
254#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
255#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
256
b405086b
NK		 257/* We need to increase PHY switch and agc settling time
258 * on turbo mode */
259#define AR5K_SWITCH_SETTLING 5760
260#define AR5K_SWITCH_SETTLING_TURBO 7168
261
262#define AR5K_AGC_SETTLING 28
263/* 38 on 5210 but shouldn't matter */
264#define AR5K_AGC_SETTLING_TURBO 37
c2975602 265
fa1c114f 266
fa1c114f 267
c47faa36
NK		 268/*****************************\
269* GENERIC CHIPSET DEFINITIONS *
270\*****************************/
271
272/**
273 * enum ath5k_version - MAC Chips
274 * @AR5K_AR5210: AR5210 (Crete)
275 * @AR5K_AR5211: AR5211 (Oahu/Maui)
276 * @AR5K_AR5212: AR5212 (Venice) and newer
277 */
fa1c114f
JS		 278enum ath5k_version {
279 AR5K_AR5210 = 0,
280 AR5K_AR5211 = 1,
281 AR5K_AR5212 = 2,
282};
283
c47faa36
NK		 284/**
285 * enum ath5k_radio - PHY Chips
286 * @AR5K_RF5110: RF5110 (Fez)
287 * @AR5K_RF5111: RF5111 (Sombrero)
288 * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)
289 * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
290 * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)
291 * @AR5K_RF2316: RF2315/2316 (Cobra SoC)
292 * @AR5K_RF2317: RF2317 (Spider SoC)
293 * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)
294 */
fa1c114f
JS		 295enum ath5k_radio {
296 AR5K_RF5110 = 0,
297 AR5K_RF5111 = 1,
298 AR5K_RF5112 = 2,
8daeef97
NK		 299 AR5K_RF2413 = 3,
300 AR5K_RF5413 = 4,
1bef016a
NK		 301 AR5K_RF2316 = 5,
302 AR5K_RF2317 = 6,
303 AR5K_RF2425 = 7,
fa1c114f
JS		 304};
305
306/*
307 * Common silicon revision/version values
308 */
309
fa1c114f
JS		 310#define AR5K_SREV_UNKNOWN 0xffff
311
1bef016a
NK		 312#define AR5K_SREV_AR5210 0x00 /* Crete */
313#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
314#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
315#define AR5K_SREV_AR5311B 0x30 /* Spirit */
316#define AR5K_SREV_AR5211 0x40 /* Oahu */
317#define AR5K_SREV_AR5212 0x50 /* Venice */
a0b907ee 318#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */
ca5efbe2 319#define AR5K_SREV_AR5212_V4 0x54 /* ??? */
1bef016a 320#define AR5K_SREV_AR5213 0x55 /* ??? */
a0b907ee
FF		 321#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */
322#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */
1bef016a
NK		 323#define AR5K_SREV_AR5213A 0x59 /* Hainan */
324#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
325#define AR5K_SREV_AR2414 0x70 /* Griffin */
c47faa36
NK		 326#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
327#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
1bef016a 328#define AR5K_SREV_AR5424 0x90 /* Condor */
c47faa36
NK		 329#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
330#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
1bef016a
NK		 331#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
332#define AR5K_SREV_AR5414 0xa0 /* Eagle */
e8f055f0 333#define AR5K_SREV_AR2415 0xb0 /* Talon */
1bef016a
NK		 334#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
335#define AR5K_SREV_AR5418 0xca /* PCI-E */
336#define AR5K_SREV_AR2425 0xe0 /* Swan */
337#define AR5K_SREV_AR2417 0xf0 /* Nala */
fa1c114f
JS		 338
339#define AR5K_SREV_RAD_5110 0x00
340#define AR5K_SREV_RAD_5111 0x10
341#define AR5K_SREV_RAD_5111A 0x15
342#define AR5K_SREV_RAD_2111 0x20
343#define AR5K_SREV_RAD_5112 0x30
344#define AR5K_SREV_RAD_5112A 0x35
e5a4ad0d 345#define AR5K_SREV_RAD_5112B 0x36
fa1c114f
JS		 346#define AR5K_SREV_RAD_2112 0x40
347#define AR5K_SREV_RAD_2112A 0x45
e5a4ad0d 348#define AR5K_SREV_RAD_2112B 0x46
1bef016a
NK		 349#define AR5K_SREV_RAD_2413 0x50
350#define AR5K_SREV_RAD_5413 0x60
e8f055f0 351#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
1bef016a
NK		 352#define AR5K_SREV_RAD_2317 0x80
353#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
354#define AR5K_SREV_RAD_2425 0xa2
355#define AR5K_SREV_RAD_5133 0xc0
356
357#define AR5K_SREV_PHY_5211 0x30
358#define AR5K_SREV_PHY_5212 0x41
8892e4ec 359#define AR5K_SREV_PHY_5212A 0x42
e8f055f0 360#define AR5K_SREV_PHY_5212B 0x43
1bef016a
NK		 361#define AR5K_SREV_PHY_2413 0x45
362#define AR5K_SREV_PHY_5413 0x61
363#define AR5K_SREV_PHY_2425 0x70
fa1c114f 364
fa1c114f
JS		 365/* TODO add support to mac80211 for vendor-specific rates and modes */
366
c47faa36
NK		 367/**
368 * DOC: Atheros XR
369 *
fa1c114f
JS		 370 * Some of this information is based on Documentation from:
371 *
e4bbf2f5 372 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
fa1c114f 373 *
c47faa36
NK		 374 * Atheros' eXtended Range - range enhancing extension is a modulation scheme
375 * that is supposed to double the link distance between an Atheros XR-enabled
376 * client device with an Atheros XR-enabled access point. This is achieved
377 * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
378 * above what the 802.11 specifications demand. In addition, new (proprietary)
379 * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
fa1c114f
JS		 380 *
381 * Please note that can you either use XR or TURBO but you cannot use both,
382 * they are exclusive.
383 *
c47faa36
NK		 384 * Also note that we do not plan to support XR mode at least for now. You can
385 * get a mode similar to XR by using 5MHz bwmode.
fa1c114f 386 */
c47faa36
NK		 387
388
389/**
390 * DOC: Atheros SuperAG
391 *
392 * In addition to XR we have another modulation scheme called TURBO mode
393 * that is supposed to provide a throughput transmission speed up to 40Mbit/s
394 * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
395 * 54Mbit/s 802.11g channels. To use this feature both ends must support it.
fa1c114f
JS		 396 * There is also a distinction between "static" and "dynamic" turbo modes:
397 *
398 * - Static: is the dumb version: devices set to this mode stick to it until
399 * the mode is turned off.
c47faa36 400 *
fa1c114f
JS		 401 * - Dynamic: is the intelligent version, the network decides itself if it
402 * is ok to use turbo. As soon as traffic is detected on adjacent channels
403 * (which would get used in turbo mode), or when a non-turbo station joins
404 * the network, turbo mode won't be used until the situation changes again.
405 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
406 * monitors the used radio band in order to decide whether turbo mode may
407 * be used or not.
408 *
409 * This article claims Super G sticks to bonding of channels 5 and 6 for
410 * USA:
411 *
412 * http://www.pcworld.com/article/id,113428-page,1/article.html
413 *
c47faa36
NK		 414 * The channel bonding seems to be driver specific though.
415 *
416 * In addition to TURBO modes we also have the following features for even
417 * greater speed-up:
fa1c114f
JS		 418 *
419 * - Bursting: allows multiple frames to be sent at once, rather than pausing
420 * after each frame. Bursting is a standards-compliant feature that can be
421 * used with any Access Point.
c47faa36 422 *
fa1c114f
JS		 423 * - Fast frames: increases the amount of information that can be sent per
424 * frame, also resulting in a reduction of transmission overhead. It is a
425 * proprietary feature that needs to be supported by the Access Point.
c47faa36 426 *
fa1c114f
JS		 427 * - Compression: data frames are compressed in real time using a Lempel Ziv
428 * algorithm. This is done transparently. Once this feature is enabled,
429 * compression and decompression takes place inside the chipset, without
430 * putting additional load on the host CPU.
431 *
c47faa36
NK		 432 * As with XR we also don't plan to support SuperAG features for now. You can
433 * get a mode similar to TURBO by using 40MHz bwmode.
fa1c114f 434 */
fa1c114f 435
c47faa36
NK		 436
437/**
438 * enum ath5k_driver_mode - PHY operation mode
439 * @AR5K_MODE_11A: 802.11a
440 * @AR5K_MODE_11B: 802.11b
441 * @AR5K_MODE_11G: 801.11g
442 * @AR5K_MODE_MAX: Used for boundary checks
443 *
444 * Do not change the order here, we use these as
445 * array indices and it also maps EEPROM structures.
446 */
d8ee398d
LR		 447enum ath5k_driver_mode {
448 AR5K_MODE_11A = 0,
8c2b418a
NK		 449 AR5K_MODE_11B = 1,
450 AR5K_MODE_11G = 2,
8c2b418a 451 AR5K_MODE_MAX = 3
fa1c114f
JS		 452};
453
c47faa36
NK		 454/**
455 * enum ath5k_ant_mode - Antenna operation mode
456 * @AR5K_ANTMODE_DEFAULT: Default antenna setup
457 * @AR5K_ANTMODE_FIXED_A: Only antenna A is present
458 * @AR5K_ANTMODE_FIXED_B: Only antenna B is present
459 * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap
460 * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc
461 * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc
462 * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
463 * @AR5K_ANTMODE_MAX: Used for boundary checks
464 *
465 * For more infos on antenna control check out phy.c
466 */
2bed03eb 467enum ath5k_ant_mode {
c47faa36
NK		 468 AR5K_ANTMODE_DEFAULT = 0,
469 AR5K_ANTMODE_FIXED_A = 1,
470 AR5K_ANTMODE_FIXED_B = 2,
471 AR5K_ANTMODE_SINGLE_AP = 3,
472 AR5K_ANTMODE_SECTOR_AP = 4,
473 AR5K_ANTMODE_SECTOR_STA = 5,
474 AR5K_ANTMODE_DEBUG = 6,
2bed03eb
NK		 475 AR5K_ANTMODE_MAX,
476};
477
c47faa36
NK		 478/**
479 * enum ath5k_bw_mode - Bandwidth operation mode
480 * @AR5K_BWMODE_DEFAULT: 20MHz, default operation
481 * @AR5K_BWMODE_5MHZ: Quarter rate
482 * @AR5K_BWMODE_10MHZ: Half rate
483 * @AR5K_BWMODE_40MHZ: Turbo
484 */
fa3d2fee 485enum ath5k_bw_mode {
c47faa36
NK		 486 AR5K_BWMODE_DEFAULT = 0,
487 AR5K_BWMODE_5MHZ = 1,
488 AR5K_BWMODE_10MHZ = 2,
489 AR5K_BWMODE_40MHZ = 3
fa3d2fee 490};
19fd6e55 491
c47faa36
NK		 492
493
fa1c114f
JS		 494/****************\
495 TX DEFINITIONS
496\****************/
497
c47faa36
NK		 498/**
499 * struct ath5k_tx_status - TX Status descriptor
500 * @ts_seqnum: Sequence number
501 * @ts_tstamp: Timestamp
502 * @ts_status: Status code
503 * @ts_final_idx: Final transmission series index
504 * @ts_final_retry: Final retry count
505 * @ts_rssi: RSSI for received ACK
506 * @ts_shortretry: Short retry count
507 * @ts_virtcol: Virtual collision count
508 * @ts_antenna: Antenna used
509 *
510 * TX status descriptor gets filled by the hw
511 * on each transmission attempt.
fa1c114f
JS		 512 */
513struct ath5k_tx_status {
514 u16 ts_seqnum;
515 u16 ts_tstamp;
516 u8 ts_status;
2f7fe870 517 u8 ts_final_idx;
ed895085 518 u8 ts_final_retry;
fa1c114f
JS		 519 s8 ts_rssi;
520 u8 ts_shortretry;
fa1c114f
JS		 521 u8 ts_virtcol;
522 u8 ts_antenna;
523};
524
525#define AR5K_TXSTAT_ALTRATE 0x80
526#define AR5K_TXERR_XRETRY 0x01
527#define AR5K_TXERR_FILT 0x02
528#define AR5K_TXERR_FIFO 0x04
529
530/**
531 * enum ath5k_tx_queue - Queue types used to classify tx queues.
532 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
533 * @AR5K_TX_QUEUE_DATA: A normal data queue
fa1c114f
JS		 534 * @AR5K_TX_QUEUE_BEACON: The beacon queue
535 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
536 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
537 */
538enum ath5k_tx_queue {
539 AR5K_TX_QUEUE_INACTIVE = 0,
540 AR5K_TX_QUEUE_DATA,
fa1c114f
JS		 541 AR5K_TX_QUEUE_BEACON,
542 AR5K_TX_QUEUE_CAB,
543 AR5K_TX_QUEUE_UAPSD,
544};
545
546#define AR5K_NUM_TX_QUEUES 10
547#define AR5K_NUM_TX_QUEUES_NOQCU 2
548
c47faa36
NK		 549/**
550 * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
551 * @AR5K_WME_AC_BK: Background traffic
552 * @AR5K_WME_AC_BE: Best-effort (normal) traffic
553 * @AR5K_WME_AC_VI: Video traffic
554 * @AR5K_WME_AC_VO: Voice traffic
555 *
fa1c114f
JS		 556 * These are the 4 Access Categories as defined in
557 * WME spec. 0 is the lowest priority and 4 is the
558 * highest. Normal data that hasn't been classified
559 * goes to the Best Effort AC.
560 */
561enum ath5k_tx_queue_subtype {
c47faa36
NK		 562 AR5K_WME_AC_BK = 0,
563 AR5K_WME_AC_BE,
564 AR5K_WME_AC_VI,
565 AR5K_WME_AC_VO,
fa1c114f
JS		 566};
567
c47faa36
NK		 568/**
569 * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
570 * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)
571 * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)
572 * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index
573 * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index
574 * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue
575 * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue
576 * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,
c47faa36
NK		 577 *
578 * Each number represents a hw queue. If hw does not support hw queues
b4cfb5d5 579 * (eg 5210) all data goes in one queue.
fa1c114f
JS		 580 */
581enum ath5k_tx_queue_id {
582 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
583 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
c47faa36
NK		 584 AR5K_TX_QUEUE_ID_DATA_MIN = 0,
585 AR5K_TX_QUEUE_ID_DATA_MAX = 3,
b4cfb5d5
NK		 586 AR5K_TX_QUEUE_ID_UAPSD = 7,
587 AR5K_TX_QUEUE_ID_CAB = 8,
588 AR5K_TX_QUEUE_ID_BEACON = 9,
fa1c114f
JS		 589};
590
fa1c114f
JS		 591/*
592 * Flags to set hw queue's parameters...
593 */
594#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
595#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
596#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
597#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
598#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
4c674c60
NK		 599#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
600#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
601#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
602#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
603#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
604#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
605#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
606#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
607#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
fa1c114f 608
c47faa36
NK		 609/**
610 * struct ath5k_txq - Transmit queue state
611 * @qnum: Hardware q number
612 * @link: Link ptr in last TX desc
613 * @q: Transmit queue (&struct list_head)
614 * @lock: Lock on q and link
615 * @setup: Is the queue configured
616 * @txq_len:Number of queued buffers
617 * @txq_max: Max allowed num of queued buffers
618 * @txq_poll_mark: Used to check if queue got stuck
619 * @txq_stuck: Queue stuck counter
620 *
621 * One of these exists for each hardware transmit queue.
622 * Packets sent to us from above are assigned to queues based
623 * on their priority. Not all devices support a complete set
624 * of hardware transmit queues. For those devices the array
625 * sc_ac2q will map multiple priorities to fewer hardware queues
626 * (typically all to one hardware queue).
e0d687bd
PR		 627 */
628struct ath5k_txq {
c47faa36
NK		 629 unsigned int qnum;
630 u32 *link;
631 struct list_head q;
632 spinlock_t lock;
e0d687bd 633 bool setup;
c47faa36
NK		 634 int txq_len;
635 int txq_max;
e0d687bd 636 bool txq_poll_mark;
c47faa36 637 unsigned int txq_stuck;
e0d687bd
PR		 638};
639
c47faa36
NK		 640/**
641 * struct ath5k_txq_info - A struct to hold TX queue's parameters
642 * @tqi_type: One of enum ath5k_tx_queue
643 * @tqi_subtype: One of enum ath5k_tx_queue_subtype
644 * @tqi_flags: TX queue flags (see above)
645 * @tqi_aifs: Arbitrated Inter-frame Space
646 * @tqi_cw_min: Minimum Contention Window
647 * @tqi_cw_max: Maximum Contention Window
648 * @tqi_cbr_period: Constant bit rate period
649 * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled
fa1c114f
JS		 650 */
651struct ath5k_txq_info {
652 enum ath5k_tx_queue tqi_type;
653 enum ath5k_tx_queue_subtype tqi_subtype;
c47faa36
NK		 654 u16 tqi_flags;
655 u8 tqi_aifs;
656 u16 tqi_cw_min;
657 u16 tqi_cw_max;
658 u32 tqi_cbr_period;
fa1c114f
JS		 659 u32 tqi_cbr_overflow_limit;
660 u32 tqi_burst_time;
c47faa36 661 u32 tqi_ready_time;
fa1c114f
JS		 662};
663
c47faa36
NK		 664/**
665 * enum ath5k_pkt_type - Transmit packet types
666 * @AR5K_PKT_TYPE_NORMAL: Normal data
667 * @AR5K_PKT_TYPE_ATIM: ATIM
668 * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
669 * @AR5K_PKT_TYPE_BEACON: Beacon
670 * @AR5K_PKT_TYPE_PROBE_RESP: Probe response
671 * @AR5K_PKT_TYPE_PIFS: PIFS
672 * Used on tx control descriptor
fa1c114f
JS		 673 */
674enum ath5k_pkt_type {
675 AR5K_PKT_TYPE_NORMAL = 0,
676 AR5K_PKT_TYPE_ATIM = 1,
677 AR5K_PKT_TYPE_PSPOLL = 2,
678 AR5K_PKT_TYPE_BEACON = 3,
679 AR5K_PKT_TYPE_PROBE_RESP = 4,
680 AR5K_PKT_TYPE_PIFS = 5,
681};
682
683/*
684 * TX power and TPC settings
685 */
686#define AR5K_TXPOWER_OFDM(_r, _v) ( \
687 ((0 & 1) << ((_v) + 6)) | \
8f655dde 688 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
fa1c114f
JS		 689)
690
691#define AR5K_TXPOWER_CCK(_r, _v) ( \
8f655dde 692 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
fa1c114f
JS		 693)
694
fa1c114f
JS		 695
696
697/****************\
698 RX DEFINITIONS
699\****************/
700
c47faa36
NK		 701/**
702 * struct ath5k_rx_status - RX Status descriptor
703 * @rs_datalen: Data length
704 * @rs_tstamp: Timestamp
705 * @rs_status: Status code
706 * @rs_phyerr: PHY error mask
707 * @rs_rssi: RSSI in 0.5dbm units
708 * @rs_keyix: Index to the key used for decrypting
709 * @rs_rate: Rate used to decode the frame
710 * @rs_antenna: Antenna used to receive the frame
711 * @rs_more: Indicates this is a frame fragment (Fast frames)
fa1c114f
JS		 712 */
713struct ath5k_rx_status {
714 u16 rs_datalen;
715 u16 rs_tstamp;
716 u8 rs_status;
717 u8 rs_phyerr;
718 s8 rs_rssi;
719 u8 rs_keyix;
720 u8 rs_rate;
721 u8 rs_antenna;
722 u8 rs_more;
723};
724
725#define AR5K_RXERR_CRC 0x01
726#define AR5K_RXERR_PHY 0x02
727#define AR5K_RXERR_FIFO 0x04
728#define AR5K_RXERR_DECRYPT 0x08
729#define AR5K_RXERR_MIC 0x10
e4bbf2f5
PR		 730#define AR5K_RXKEYIX_INVALID ((u8) -1)
731#define AR5K_TXKEYIX_INVALID ((u32) -1)
fa1c114f 732
fa1c114f 733
fa1c114f
JS		 734/**************************\
735 BEACON TIMERS DEFINITIONS
736\**************************/
737
738#define AR5K_BEACON_PERIOD 0x0000ffff
739#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
740#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
741
fa1c114f
JS		 742
743/*
744 * TSF to TU conversion:
745 *
746 * TSF is a 64bit value in usec (microseconds).
e535c1ac
BR		 747 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
748 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
fa1c114f
JS		 749 */
750#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
751
752
c47faa36 753
c6e387a2
NK		 754/*******************************\
755 GAIN OPTIMIZATION DEFINITIONS
756\*******************************/
757
c47faa36
NK		 758/**
759 * enum ath5k_rfgain - RF Gain optimization engine state
760 * @AR5K_RFGAIN_INACTIVE: Engine disabled
761 * @AR5K_RFGAIN_ACTIVE: Probe active
762 * @AR5K_RFGAIN_READ_REQUESTED: Probe requested
763 * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change
764 */
c6e387a2
NK		 765enum ath5k_rfgain {
766 AR5K_RFGAIN_INACTIVE = 0,
6f3b414a 767 AR5K_RFGAIN_ACTIVE,
c6e387a2
NK		 768 AR5K_RFGAIN_READ_REQUESTED,
769 AR5K_RFGAIN_NEED_CHANGE,
770};
771
c47faa36
NK		 772/**
773 * struct ath5k_gain - RF Gain optimization engine state data
774 * @g_step_idx: Current step index
775 * @g_current: Current gain
776 * @g_target: Target gain
777 * @g_low: Low gain boundary
778 * @g_high: High gain boundary
779 * @g_f_corr: Gain_F correction
780 * @g_state: One of enum ath5k_rfgain
781 */
c6e387a2 782struct ath5k_gain {
6f3b414a
NK		 783 u8 g_step_idx;
784 u8 g_current;
785 u8 g_target;
786 u8 g_low;
787 u8 g_high;
788 u8 g_f_corr;
789 u8 g_state;
c6e387a2
NK		 790};
791
c47faa36
NK		 792
793
fa1c114f
JS		 794/********************\
795 COMMON DEFINITIONS
796\********************/
797
fa1c114f
JS		 798#define AR5K_SLOT_TIME_9 396
799#define AR5K_SLOT_TIME_20 880
800#define AR5K_SLOT_TIME_MAX 0xffff
801
c47faa36
NK		 802/**
803 * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
804 * @a2_flags: Channel flags (internal)
805 * @a2_athchan: HW channel number (internal)
806 *
807 * This structure is used to map 2GHz channels to
808 * 5GHz Atheros channels on 2111 frequency converter
809 * that comes together with RF5111
c6e387a2 810 * TODO: Clean up
fa1c114f
JS		 811 */
812struct ath5k_athchan_2ghz {
813 u32 a2_flags;
814 u16 a2_athchan;
815};
816
c47faa36
NK		 817/**
818 * enum ath5k_dmasize - DMA size definitions (2^(n+2))
819 * @AR5K_DMASIZE_4B: 4Bytes
820 * @AR5K_DMASIZE_8B: 8Bytes
821 * @AR5K_DMASIZE_16B: 16Bytes
822 * @AR5K_DMASIZE_32B: 32Bytes
823 * @AR5K_DMASIZE_64B: 64Bytes (Default)
824 * @AR5K_DMASIZE_128B: 128Bytes
825 * @AR5K_DMASIZE_256B: 256Bytes
826 * @AR5K_DMASIZE_512B: 512Bytes
827 *
828 * These are used to set DMA burst size on hw
829 *
830 * Note: Some platforms can't handle more than 4Bytes
831 * be careful on embedded boards.
832 */
833enum ath5k_dmasize {
834 AR5K_DMASIZE_4B = 0,
835 AR5K_DMASIZE_8B,
836 AR5K_DMASIZE_16B,
837 AR5K_DMASIZE_32B,
838 AR5K_DMASIZE_64B,
839 AR5K_DMASIZE_128B,
840 AR5K_DMASIZE_256B,
841 AR5K_DMASIZE_512B
842};
843
844
63266a65 845
c6e387a2
NK		 846/******************\
847 RATE DEFINITIONS
848\******************/
fa1c114f 849
fa1c114f 850/**
c47faa36
NK		 851 * DOC: Rate codes
852 *
6a2a0e73 853 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
fa1c114f 854 *
63266a65 855 * The rate code is used to get the RX rate or set the TX rate on the
fa1c114f
JS		 856 * hardware descriptors. It is also used for internal modulation control
857 * and settings.
858 *
c47faa36 859 * This is the hardware rate map we are aware of (html unfriendly):
fa1c114f 860 *
c47faa36
NK		 861 * Rate code Rate (Kbps)
862 * --------- -----------
863 * 0x01 3000 (XR)
864 * 0x02 1000 (XR)
865 * 0x03 250 (XR)
866 * 0x04 - 05 -Reserved-
867 * 0x06 2000 (XR)
868 * 0x07 500 (XR)
869 * 0x08 48000 (OFDM)
870 * 0x09 24000 (OFDM)
871 * 0x0A 12000 (OFDM)
872 * 0x0B 6000 (OFDM)
873 * 0x0C 54000 (OFDM)
874 * 0x0D 36000 (OFDM)
875 * 0x0E 18000 (OFDM)
876 * 0x0F 9000 (OFDM)
877 * 0x10 - 17 -Reserved-
878 * 0x18 11000L (CCK)
879 * 0x19 5500L (CCK)
880 * 0x1A 2000L (CCK)
881 * 0x1B 1000L (CCK)
882 * 0x1C 11000S (CCK)
883 * 0x1D 5500S (CCK)
884 * 0x1E 2000S (CCK)
885 * 0x1F -Reserved-
fa1c114f 886 *
c47faa36 887 * "S" indicates CCK rates with short preamble and "L" with long preamble.
fa1c114f 888 *
63266a65 889 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
c47faa36 890 * lowest 4 bits, so they are the same as above with a 0xF mask.
63266a65
BR		 891 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
892 * We handle this in ath5k_setup_bands().
fa1c114f 893 */
63266a65 894#define AR5K_MAX_RATES 32
fa1c114f 895
63266a65
BR		 896/* B */
897#define ATH5K_RATE_CODE_1M 0x1B
898#define ATH5K_RATE_CODE_2M 0x1A
899#define ATH5K_RATE_CODE_5_5M 0x19
900#define ATH5K_RATE_CODE_11M 0x18
901/* A and G */
902#define ATH5K_RATE_CODE_6M 0x0B
903#define ATH5K_RATE_CODE_9M 0x0F
904#define ATH5K_RATE_CODE_12M 0x0A
905#define ATH5K_RATE_CODE_18M 0x0E
906#define ATH5K_RATE_CODE_24M 0x09
907#define ATH5K_RATE_CODE_36M 0x0D
908#define ATH5K_RATE_CODE_48M 0x08
909#define ATH5K_RATE_CODE_54M 0x0C
fa1c114f 910
c47faa36
NK		 911/* Adding this flag to rate_code on B rates
912 * enables short preamble */
c6e387a2 913#define AR5K_SET_SHORT_PREAMBLE 0x04
fa1c114f
JS		 914
915/*
916 * Crypto definitions
917 */
918
919#define AR5K_KEYCACHE_SIZE 8
eb939922 920extern bool ath5k_modparam_nohwcrypt;
fa1c114f
JS		 921
922/***********************\
923 HW RELATED DEFINITIONS
924\***********************/
925
926/*
927 * Misc definitions
928 */
e4bbf2f5 929#define AR5K_RSSI_EP_MULTIPLIER (1 << 7)
fa1c114f
JS		 930
931#define AR5K_ASSERT_ENTRY(_e, _s) do { \
932 if (_e >= _s) \
fdd55d14 933 return false; \
fa1c114f
JS		 934} while (0)
935
fa1c114f
JS		 936/*
937 * Hardware interrupt abstraction
938 */
939
940/**
941 * enum ath5k_int - Hardware interrupt masks helpers
c47faa36
NK		 942 * @AR5K_INT_RXOK: Frame successfully received
943 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor
944 * @AR5K_INT_RXERR: Frame reception failed
945 * @AR5K_INT_RXNOFRM: No frame received within a specified time period
946 * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors
947 * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is
948 * not always fatal, on some chips we can continue operation
949 * without resetting the card, that's why %AR5K_INT_FATAL is not
950 * common for all chips.
951 * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts
952 *
953 * @AR5K_INT_TXOK: Frame transmission success
954 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor
955 * @AR5K_INT_TXERR: Frame transmission failure
956 * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The
957 * Queue Control Unit (QCU) signals an EOL interrupt only if a
958 * descriptor's LinkPtr is NULL. For more details, refer to:
959 * "http://www.freepatentsonline.com/20030225739.html"
960 * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period
961 * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should
962 * increase the TX trigger threshold.
963 * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts
fa1c114f 964 *
2111ac0d 965 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
c47faa36
NK		 966 * one of the PHY error counters reached the maximum value and
967 * should be read and cleared.
968 * @AR5K_INT_SWI: Software triggered interrupt.
fa1c114f 969 * @AR5K_INT_RXPHY: RX PHY Error
4c674c60 970 * @AR5K_INT_RXKCM: RX Key cache miss
fa1c114f 971 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
c47faa36
NK		 972 * beacon that must be handled in software. The alternative is if
973 * you have VEOL support, in that case you let the hardware deal
974 * with things.
975 * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold
fa1c114f 976 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
c47faa36
NK		 977 * beacons from the AP have associated with, we should probably
978 * try to reassociate. When in IBSS mode this might mean we have
979 * not received any beacons from any local stations. Note that
980 * every station in an IBSS schedules to send beacons at the
981 * Target Beacon Transmission Time (TBTT) with a random backoff.
982 * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.
983 * @AR5K_INT_TIM: Beacon with local station's TIM bit set
984 * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received
985 * @AR5K_INT_DTIM_SYNC: DTIM sync lost
986 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to
987 * our GPIO pins.
988 * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting
989 * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got
990 * nothing or an incomplete CAB frame sequence.
991 * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired
992 * @AR5K_INT_QCBRURN: A queue got triggered wile empty
993 * @AR5K_INT_QTRIG: A queue got triggered
994 *
995 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA
996 * errors. Indicates we need to reset the card.
4c674c60 997 * @AR5K_INT_GLOBAL: Used to clear and set the IER
c47faa36
NK		 998 * @AR5K_INT_NOCARD: Signals the card has been removed
999 * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same
1000 * bit value
fa1c114f
JS		 1001 *
1002 * These are mapped to take advantage of some common bits
1003 * between the MACs, to be able to set intr properties
1004 * easier. Some of them are not used yet inside hw.c. Most map
6a2a0e73 1005 * to the respective hw interrupt value as they are common among different
fa1c114f
JS		 1006 * MACs.
1007 */
1008enum ath5k_int {
4c674c60 1009 AR5K_INT_RXOK = 0x00000001,
fa1c114f 1010 AR5K_INT_RXDESC = 0x00000002,
4c674c60 1011 AR5K_INT_RXERR = 0x00000004,
fa1c114f
JS		 1012 AR5K_INT_RXNOFRM = 0x00000008,
1013 AR5K_INT_RXEOL = 0x00000010,
1014 AR5K_INT_RXORN = 0x00000020,
4c674c60 1015 AR5K_INT_TXOK = 0x00000040,
fa1c114f 1016 AR5K_INT_TXDESC = 0x00000080,
4c674c60
NK		 1017 AR5K_INT_TXERR = 0x00000100,
1018 AR5K_INT_TXNOFRM = 0x00000200,
1019 AR5K_INT_TXEOL = 0x00000400,
fa1c114f
JS		 1020 AR5K_INT_TXURN = 0x00000800,
1021 AR5K_INT_MIB = 0x00001000,
4c674c60 1022 AR5K_INT_SWI = 0x00002000,
fa1c114f
JS		 1023 AR5K_INT_RXPHY = 0x00004000,
1024 AR5K_INT_RXKCM = 0x00008000,
1025 AR5K_INT_SWBA = 0x00010000,
4c674c60 1026 AR5K_INT_BRSSI = 0x00020000,
fa1c114f 1027 AR5K_INT_BMISS = 0x00040000,
4c674c60
NK		 1028 AR5K_INT_FATAL = 0x00080000, /* Non common */
1029 AR5K_INT_BNR = 0x00100000, /* Non common */
1030 AR5K_INT_TIM = 0x00200000, /* Non common */
1031 AR5K_INT_DTIM = 0x00400000, /* Non common */
1032 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
1033 AR5K_INT_GPIO = 0x01000000,
1034 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
1035 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
c47faa36
NK		 1036 AR5K_INT_QCBRORN = 0x08000000, /* Non common */
1037 AR5K_INT_QCBRURN = 0x10000000, /* Non common */
1038 AR5K_INT_QTRIG = 0x20000000, /* Non common */
4c674c60
NK		 1039 AR5K_INT_GLOBAL = 0x80000000,
1040
c266c71a
FF		 1041 AR5K_INT_TX_ALL = AR5K_INT_TXOK
1042 | AR5K_INT_TXDESC
1043 | AR5K_INT_TXERR
fea94807 1044 | AR5K_INT_TXNOFRM
c266c71a
FF		 1045 | AR5K_INT_TXEOL
1046 | AR5K_INT_TXURN,
1047
1048 AR5K_INT_RX_ALL = AR5K_INT_RXOK
1049 | AR5K_INT_RXDESC
1050 | AR5K_INT_RXERR
1051 | AR5K_INT_RXNOFRM
1052 | AR5K_INT_RXEOL
1053 | AR5K_INT_RXORN,
1054
4c674c60
NK		 1055 AR5K_INT_COMMON = AR5K_INT_RXOK
1056 | AR5K_INT_RXDESC
1057 | AR5K_INT_RXERR
1058 | AR5K_INT_RXNOFRM
1059 | AR5K_INT_RXEOL
1060 | AR5K_INT_RXORN
1061 | AR5K_INT_TXOK
1062 | AR5K_INT_TXDESC
1063 | AR5K_INT_TXERR
1064 | AR5K_INT_TXNOFRM
1065 | AR5K_INT_TXEOL
1066 | AR5K_INT_TXURN
1067 | AR5K_INT_MIB
1068 | AR5K_INT_SWI
1069 | AR5K_INT_RXPHY
1070 | AR5K_INT_RXKCM
1071 | AR5K_INT_SWBA
1072 | AR5K_INT_BRSSI
1073 | AR5K_INT_BMISS
1074 | AR5K_INT_GPIO
1075 | AR5K_INT_GLOBAL,
1076
fa1c114f
JS		 1077 AR5K_INT_NOCARD = 0xffffffff
1078};
1079
c47faa36
NK		 1080/**
1081 * enum ath5k_calibration_mask - Mask which calibration is active at the moment
1082 * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)
1083 * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)
1084 * @AR5K_CALIBRATION_NF: Noise Floor calibration
1085 * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity
1086 */
e65e1d77
BR		 1087enum ath5k_calibration_mask {
1088 AR5K_CALIBRATION_FULL = 0x01,
1089 AR5K_CALIBRATION_SHORT = 0x02,
ce169aca
NK		 1090 AR5K_CALIBRATION_NF = 0x04,
1091 AR5K_CALIBRATION_ANI = 0x08,
6e220662
NK		 1092};
1093
c47faa36
NK		 1094/**
1095 * enum ath5k_power_mode - Power management modes
1096 * @AR5K_PM_UNDEFINED: Undefined
1097 * @AR5K_PM_AUTO: Allow card to sleep if possible
1098 * @AR5K_PM_AWAKE: Force card to wake up
1099 * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)
1100 * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration
1101 *
1102 * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO
1103 * are also known to have problems on some cards. This is not a big
1104 * problem though because we can have almost the same effect as
1105 * FULL_SLEEP by putting card on warm reset (it's almost powered down).
fa1c114f
JS		 1106 */
1107enum ath5k_power_mode {
1108 AR5K_PM_UNDEFINED = 0,
1109 AR5K_PM_AUTO,
1110 AR5K_PM_AWAKE,
1111 AR5K_PM_FULL_SLEEP,
1112 AR5K_PM_NETWORK_SLEEP,
1113};
1114
1115/*
1116 * These match net80211 definitions (not used in
c6e387a2
NK		 1117 * mac80211).
1118 * TODO: Clean this up
fa1c114f
JS		 1119 */
1120#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
1121#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
1122#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
1123#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
1124#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
1125
1126/* GPIO-controlled software LED */
1127#define AR5K_SOFTLED_PIN 0
1128#define AR5K_SOFTLED_ON 0
1129#define AR5K_SOFTLED_OFF 1
1130
400ec45a
LR		 1131
1132/* XXX: we *may* move cap_range stuff to struct wiphy */
fa1c114f
JS		 1133struct ath5k_capabilities {
1134 /*
1135 * Supported PHY modes
32c25464 1136 * (ie. AR5K_MODE_11A, AR5K_MODE_11B, ...)
fa1c114f 1137 */
d8ee398d 1138 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
fa1c114f
JS		 1139
1140 /*
1141 * Frequency range (without regulation restrictions)
1142 */
1143 struct {
1144 u16 range_2ghz_min;
1145 u16 range_2ghz_max;
1146 u16 range_5ghz_min;
1147 u16 range_5ghz_max;
1148 } cap_range;
1149
fa1c114f
JS		 1150 /*
1151 * Values stored in the EEPROM (some of them...)
1152 */
1153 struct ath5k_eeprom_info cap_eeprom;
1154
1155 /*
1156 * Queue information
1157 */
1158 struct {
1159 u8 q_tx_num;
1160 } cap_queues;
a8c944f8
BR		 1161
1162 bool cap_has_phyerr_counters;
86f62d9b
NK		 1163 bool cap_has_mrr_support;
1164 bool cap_needs_2GHz_ovr;
fa1c114f
JS		 1165};
1166
e5e2647f
BC		 1167/* size of noise floor history (keep it a power of two) */
1168#define ATH5K_NF_CAL_HIST_MAX 8
d2c7f773 1169struct ath5k_nfcal_hist {
e5e2647f
BC		 1170 s16 index; /* current index into nfval */
1171 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1172};
1173
e0d687bd
PR		 1174#define ATH5K_LED_MAX_NAME_LEN 31
1175
1176/*
1177 * State for LED triggers
1178 */
1179struct ath5k_led {
1180 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
1181 struct ath5k_hw *ah; /* driver state */
1182 struct led_classdev led_dev; /* led classdev */
1183};
1184
1185/* Rfkill */
1186struct ath5k_rfkill {
1187 /* GPIO PIN for rfkill */
1188 u16 gpio;
1189 /* polarity of rfkill GPIO PIN */
1190 bool polarity;
1191 /* RFKILL toggle tasklet */
1192 struct tasklet_struct toggleq;
1193};
1194
1195/* statistics */
1196struct ath5k_statistics {
1197 /* antenna use */
1198 unsigned int antenna_rx[5]; /* frames count per antenna RX */
1199 unsigned int antenna_tx[5]; /* frames count per antenna TX */
1200
1201 /* frame errors */
1202 unsigned int rx_all_count; /* all RX frames, including errors */
1203 unsigned int tx_all_count; /* all TX frames, including errors */
1204 unsigned int rx_bytes_count; /* all RX bytes, including errored pkts
1205 * and the MAC headers for each packet
1206 */
1207 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
1208 * and the MAC headers and padding for
1209 * each packet.
1210 */
1211 unsigned int rxerr_crc;
1212 unsigned int rxerr_phy;
1213 unsigned int rxerr_phy_code[32];
1214 unsigned int rxerr_fifo;
1215 unsigned int rxerr_decrypt;
1216 unsigned int rxerr_mic;
1217 unsigned int rxerr_proc;
1218 unsigned int rxerr_jumbo;
1219 unsigned int txerr_retry;
1220 unsigned int txerr_fifo;
1221 unsigned int txerr_filt;
1222
1223 /* MIB counters */
1224 unsigned int ack_fail;
1225 unsigned int rts_fail;
1226 unsigned int rts_ok;
1227 unsigned int fcs_error;
1228 unsigned int beacons;
1229
1230 unsigned int mib_intr;
1231 unsigned int rxorn_intr;
1232 unsigned int rxeol_intr;
1233};
fa1c114f
JS		 1234
1235/*
1236 * Misc defines
1237 */
1238
1239#define AR5K_MAX_GPIO 10
1240#define AR5K_MAX_RF_BANKS 8
1241
e0d687bd
PR		 1242#if CHAN_DEBUG
1243#define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
1244#else
1245#define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
1246#endif
1247
1248#define ATH_RXBUF 40 /* number of RX buffers */
1249#define ATH_TXBUF 200 /* number of TX buffers */
1250#define ATH_BCBUF 4 /* number of beacon buffers */
1251#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
1252#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
1253
1254/* Driver state associated with an instance of a device */
fa1c114f 1255struct ath5k_hw {
db719718 1256 struct ath_common common;
fa1c114f 1257
e0d687bd
PR		 1258 struct pci_dev *pdev;
1259 struct device *dev; /* for dma mapping */
1260 int irq;
1261 u16 devid;
1262 void __iomem *iobase; /* address of the device */
1263 struct mutex lock; /* dev-level lock */
1264 struct ieee80211_hw *hw; /* IEEE 802.11 common */
1265 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1266 struct ieee80211_channel channels[ATH_CHAN_MAX];
1267 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1268 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1269 enum nl80211_iftype opmode;
1270
1271#ifdef CONFIG_ATH5K_DEBUG
1272 struct ath5k_dbg_info debug; /* debug info */
1273#endif /* CONFIG_ATH5K_DEBUG */
1274
1275 struct ath5k_buf *bufptr; /* allocated buffer ptr */
1276 struct ath5k_desc *desc; /* TX/RX descriptors */
1277 dma_addr_t desc_daddr; /* DMA (physical) address */
1278 size_t desc_len; /* size of TX/RX descriptors */
1279
86f62d9b 1280 DECLARE_BITMAP(status, 4);
e0d687bd 1281#define ATH_STAT_INVALID 0 /* disable hardware accesses */
86f62d9b
NK		 1282#define ATH_STAT_PROMISC 1
1283#define ATH_STAT_LEDSOFT 2 /* enable LED gpio status */
1284#define ATH_STAT_STARTED 3 /* opened & irqs enabled */
e0d687bd
PR		 1285
1286 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
1287 struct ieee80211_channel *curchan; /* current h/w channel */
1288
1289 u16 nvifs;
1290
1291 enum ath5k_int imask; /* interrupt mask copy */
1292
1293 spinlock_t irqlock;
1294 bool rx_pending; /* rx tasklet pending */
1295 bool tx_pending; /* tx tasklet pending */
1296
e0d687bd
PR		 1297 u8 bssidmask[ETH_ALEN];
1298
1299 unsigned int led_pin, /* GPIO pin for driving LED */
1300 led_on; /* pin setting for LED on */
1301
1302 struct work_struct reset_work; /* deferred chip reset */
ce169aca 1303 struct work_struct calib_work; /* deferred phy calibration */
e0d687bd 1304
e0d687bd
PR		 1305 struct list_head rxbuf; /* receive buffer */
1306 spinlock_t rxbuflock;
1307 u32 *rxlink; /* link ptr in last RX desc */
1308 struct tasklet_struct rxtq; /* rx intr tasklet */
1309 struct ath5k_led rx_led; /* rx led */
1310
1311 struct list_head txbuf; /* transmit buffer */
1312 spinlock_t txbuflock;
1313 unsigned int txbuf_len; /* buf count in txbuf list */
1314 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
1315 struct tasklet_struct txtq; /* tx intr tasklet */
1316 struct ath5k_led tx_led; /* tx led */
1317
1318 struct ath5k_rfkill rf_kill;
1319
e0d687bd
PR		 1320 spinlock_t block; /* protects beacon */
1321 struct tasklet_struct beacontq; /* beacon intr tasklet */
1322 struct list_head bcbuf; /* beacon buffer */
1323 struct ieee80211_vif *bslot[ATH_BCBUF];
1324 u16 num_ap_vifs;
1325 u16 num_adhoc_vifs;
da473b61 1326 u16 num_mesh_vifs;
e0d687bd
PR		 1327 unsigned int bhalq, /* SW q for outgoing beacons */
1328 bmisscount, /* missed beacon transmits */
1329 bintval, /* beacon interval in TU */
1330 bsent;
1331 unsigned int nexttbtt; /* next beacon time in TU */
1332 struct ath5k_txq *cabq; /* content after beacon */
1333
e0d687bd
PR		 1334 bool assoc; /* associate state */
1335 bool enable_beacon; /* true if beacons are on */
1336
1337 struct ath5k_statistics stats;
1338
1339 struct ath5k_ani_state ani_state;
1340 struct tasklet_struct ani_tasklet; /* ANI calibration */
1341
1342 struct delayed_work tx_complete_work;
1343
1344 struct survey_info survey; /* collected survey info */
fa1c114f
JS		 1345
1346 enum ath5k_int ah_imr;
1347
46026e8f 1348 struct ieee80211_channel *ah_current_channel;
ce169aca 1349 bool ah_iq_cal_needed;
fa1c114f 1350 bool ah_single_chip;
fa1c114f 1351
46026e8f
BC		 1352 enum ath5k_version ah_version;
1353 enum ath5k_radio ah_radio;
fa1c114f
JS		 1354 u32 ah_mac_srev;
1355 u16 ah_mac_version;
fa1c114f
JS		 1356 u16 ah_phy_revision;
1357 u16 ah_radio_5ghz_revision;
1358 u16 ah_radio_2ghz_revision;
1359
fa1c114f
JS		 1360#define ah_modes ah_capabilities.cap_mode
1361#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1362
76a9f6fd
BR		 1363 u8 ah_retry_long;
1364 u8 ah_retry_short;
1365
6340211c
FF		 1366 u32 ah_use_32khz_clock;
1367
6e08d228 1368 u8 ah_coverage_class;
61cde037 1369 bool ah_ack_bitrate_high;
fa3d2fee 1370 u8 ah_bwmode;
b1ad1b6f 1371 bool ah_short_slot;
fa1c114f 1372
2bed03eb
NK		 1373 /* Antenna Control */
1374 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1375 u8 ah_ant_mode;
1376 u8 ah_tx_ant;
1377 u8 ah_def_ant;
fa1c114f 1378
fa1c114f
JS		 1379 struct ath5k_capabilities ah_capabilities;
1380
1381 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1382 u32 ah_txq_status;
1383 u32 ah_txq_imr_txok;
1384 u32 ah_txq_imr_txerr;
1385 u32 ah_txq_imr_txurn;
1386 u32 ah_txq_imr_txdesc;
1387 u32 ah_txq_imr_txeol;
4c674c60
NK		 1388 u32 ah_txq_imr_cbrorn;
1389 u32 ah_txq_imr_cbrurn;
1390 u32 ah_txq_imr_qtrig;
1391 u32 ah_txq_imr_nofrm;
7ff7c82e
NK		 1392
1393 u32 ah_txq_isr_txok_all;
1394 u32 ah_txq_isr_txurn;
1395 u32 ah_txq_isr_qcborn;
1396 u32 ah_txq_isr_qcburn;
1397 u32 ah_txq_isr_qtrig;
1398
fa1c114f
JS		 1399 u32 *ah_rf_banks;
1400 size_t ah_rf_banks_size;
8892e4ec 1401 size_t ah_rf_regs_count;
fa1c114f 1402 struct ath5k_gain ah_gain;
8892e4ec 1403 u8 ah_offset[AR5K_MAX_RF_BANKS];
fa1c114f 1404
8f655dde 1405
fa1c114f 1406 struct {
8f655dde
NK		 1407 /* Temporary tables used for interpolation */
1408 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1409 [AR5K_EEPROM_POWER_TABLE_SIZE];
1410 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1411 [AR5K_EEPROM_POWER_TABLE_SIZE];
1412 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1413 u16 txp_rates_power_table[AR5K_MAX_RATES];
1414 u8 txp_min_idx;
fa1c114f 1415 bool txp_tpc;
8f655dde
NK		 1416 /* Values in 0.25dB units */
1417 s16 txp_min_pwr;
1418 s16 txp_max_pwr;
51f00622 1419 s16 txp_cur_pwr;
a0823810 1420 /* Values in 0.5dB units */
8f655dde 1421 s16 txp_offset;
fa1c114f 1422 s16 txp_ofdm;
8f655dde 1423 s16 txp_cck_ofdm_gainf_delta;
a0823810
NK		 1424 /* Value in dB units */
1425 s16 txp_cck_ofdm_pwr_delta;
26c7fc43 1426 bool txp_setup;
987af54f 1427 int txp_requested; /* Requested tx power in dBm */
fa1c114f
JS		 1428 } ah_txpower;
1429
e5e2647f
BC		 1430 struct ath5k_nfcal_hist ah_nfcal_hist;
1431
b4ea449d 1432 /* average beacon RSSI in our BSS (used by ANI) */
eef39bef 1433 struct ewma ah_beacon_rssi_avg;
b4ea449d 1434
fa1c114f
JS		 1435 /* noise floor from last periodic calibration */
1436 s32 ah_noise_floor;
1437
6e220662 1438 /* Calibration timestamp */
a9167f96 1439 unsigned long ah_cal_next_full;
ce169aca 1440 unsigned long ah_cal_next_short;
2111ac0d 1441 unsigned long ah_cal_next_ani;
6e220662 1442
e65e1d77
BR		 1443 /* Calibration mask */
1444 u8 ah_cal_mask;
6e220662 1445
fa1c114f
JS		 1446 /*
1447 * Function pointers
1448 */
1449 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
8127fbdc 1450 unsigned int, unsigned int, int, enum ath5k_pkt_type,
fa1c114f 1451 unsigned int, unsigned int, unsigned int, unsigned int,
8127fbdc 1452 unsigned int, unsigned int, unsigned int, unsigned int);
b47f407b
BR		 1453 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1454 struct ath5k_tx_status *);
1455 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1456 struct ath5k_rx_status *);
fa1c114f
JS		 1457};
1458
0cb9e06b
FF		 1459struct ath_bus_ops {
1460 enum ath_bus_type ath_bus_type;
1461 void (*read_cachesize)(struct ath_common *common, int *csz);
1462 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
fa9bfd61 1463 int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
0cb9e06b
FF		 1464};
1465
fa1c114f
JS		 1466/*
1467 * Prototypes
1468 */
e5b046d8 1469extern const struct ieee80211_ops ath5k_hw_ops;
fa1c114f 1470
132b1c3e 1471/* Initialization and detach functions */
e0d687bd 1472int ath5k_hw_init(struct ath5k_hw *ah);
132b1c3e 1473void ath5k_hw_deinit(struct ath5k_hw *ah);
c6e387a2 1474
e0d687bd
PR		 1475int ath5k_sysfs_register(struct ath5k_hw *ah);
1476void ath5k_sysfs_unregister(struct ath5k_hw *ah);
40ca22ea 1477
e7aecd32 1478/*Chip id helper functions */
e7aecd32 1479int ath5k_hw_read_srev(struct ath5k_hw *ah);
9320b5c4 1480
0ed4548f 1481/* LED functions */
e0d687bd
PR		 1482int ath5k_init_leds(struct ath5k_hw *ah);
1483void ath5k_led_enable(struct ath5k_hw *ah);
1484void ath5k_led_off(struct ath5k_hw *ah);
1485void ath5k_unregister_leds(struct ath5k_hw *ah);
0ed4548f 1486
9320b5c4 1487
fa1c114f 1488/* Reset Functions */
32c25464 1489int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel);
a25d1e4c
PR		 1490int ath5k_hw_on_hold(struct ath5k_hw *ah);
1491int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
8aec7af9 1492 struct ieee80211_channel *channel, bool fast, bool skip_pcu);
ec182d97
PR		 1493int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1494 bool is_set);
fa1c114f 1495/* Power management functions */
c6e387a2 1496
9320b5c4
NK		 1497
1498/* Clock rate related functions */
1499unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1500unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1501void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1502
1503
fa1c114f 1504/* DMA Related Functions */
a25d1e4c 1505void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
a25d1e4c 1506u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
e8325ed8 1507int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
a25d1e4c 1508int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
14fae2d4 1509int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
a25d1e4c
PR		 1510u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1511int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
c6e387a2 1512 u32 phys_addr);
a25d1e4c 1513int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
fa1c114f 1514/* Interrupt handling */
a25d1e4c
PR		 1515bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1516int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1517enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
495391d7 1518void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
d41174fa 1519/* Init/Stop functions */
9320b5c4 1520void ath5k_hw_dma_init(struct ath5k_hw *ah);
d41174fa 1521int ath5k_hw_dma_stop(struct ath5k_hw *ah);
c6e387a2 1522
fa1c114f 1523/* EEPROM access functions */
a25d1e4c
PR		 1524int ath5k_eeprom_init(struct ath5k_hw *ah);
1525void ath5k_eeprom_detach(struct ath5k_hw *ah);
c6e387a2 1526
9320b5c4 1527
fa1c114f 1528/* Protocol Control Unit Functions */
eeb8832b 1529/* Helpers */
4ee73f33 1530int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum ieee80211_band band,
a27049e2 1531 int len, struct ieee80211_rate *rate, bool shortpre);
71ba1c30 1532unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
eeb8832b 1533unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
f5cbc8ba 1534int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
a25d1e4c 1535void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
9320b5c4 1536/* RX filter control*/
a25d1e4c 1537int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
418de6d9 1538void ath5k_hw_set_bssid(struct ath5k_hw *ah);
a25d1e4c 1539void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
a25d1e4c
PR		 1540void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1541u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1542void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
9320b5c4
NK		 1543/* Receive (DRU) start/stop functions */
1544void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1545void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
c6e387a2 1546/* Beacon control functions */
a25d1e4c
PR		 1547u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1548void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1549void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
c47faa36
NK		 1550void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
1551 u32 interval);
7f896126 1552bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
9320b5c4 1553/* Init function */
c47faa36 1554void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
c6e387a2 1555
fa1c114f 1556/* Queue Control Unit, DFS Control Unit Functions */
a25d1e4c
PR		 1557int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1558 struct ath5k_txq_info *queue_info);
1559int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1560 const struct ath5k_txq_info *queue_info);
1561int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1562 enum ath5k_tx_queue queue_type,
1563 struct ath5k_txq_info *queue_info);
76a9f6fd
BR		 1564void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
1565 unsigned int queue);
a25d1e4c
PR		 1566u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1567void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1568int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
eeb8832b 1569int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
9320b5c4
NK		 1570/* Init function */
1571int ath5k_hw_init_queues(struct ath5k_hw *ah);
c6e387a2 1572
fa1c114f 1573/* Hardware Descriptor Functions */
a25d1e4c 1574int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
a6668193
BR		 1575int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1576 u32 size, unsigned int flags);
1577int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1578 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1579 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
c6e387a2 1580
9320b5c4 1581
fa1c114f 1582/* GPIO Functions */
a25d1e4c
PR		 1583void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1584int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1585int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1586u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1587int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1588void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1589 u32 interrupt_level);
c6e387a2 1590
9320b5c4
NK		 1591
1592/* RFkill Functions */
a25d1e4c
PR		 1593void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1594void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
e6a3b616 1595
9320b5c4
NK		 1596
1597/* Misc functions TODO: Cleanup */
c6e387a2 1598int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
a25d1e4c
PR		 1599int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1600int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
fa1c114f 1601
9320b5c4 1602
fa1c114f 1603/* Initial register settings functions */
a25d1e4c 1604int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
c6e387a2 1605
9320b5c4
NK		 1606
1607/* PHY functions */
1608/* Misc PHY functions */
32c25464 1609u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band);
9320b5c4
NK		 1610int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1611/* Gain_F optimization */
a25d1e4c
PR		 1612enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1613int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
fa1c114f 1614/* PHY/RF channel functions */
32c25464 1615bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel);
fa1c114f 1616/* PHY calibration */
e5e2647f 1617void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
a25d1e4c
PR		 1618int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1619 struct ieee80211_channel *channel);
9e04a7eb 1620void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
57e6c56d
NK		 1621/* Spur mitigation */
1622bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
a25d1e4c 1623 struct ieee80211_channel *channel);
2bed03eb 1624/* Antenna control */
a25d1e4c 1625void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
0ca74027 1626void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
fa1c114f 1627/* TX power setup */
a25d1e4c 1628int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
9320b5c4
NK		 1629/* Init function */
1630int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
0207c0c5 1631 u8 mode, bool fast);
fa1c114f 1632
c6e387a2 1633/*
6a2a0e73 1634 * Functions used internally
c6e387a2
NK		 1635 */
1636
e5aa8474
LR		 1637static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1638{
0a5d3813 1639 return &ah->common;
e5aa8474
LR		 1640}
1641
1642static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1643{
0a5d3813 1644 return &(ath5k_hw_common(ah)->regulatory);
e5aa8474
LR		 1645}
1646
a0b907ee
FF		 1647#ifdef CONFIG_ATHEROS_AR231X
1648#define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000)
1649
1650static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
1651{
1652 /* On AR2315 and AR2317 the PCI clock domain registers
1653 * are outside of the WMAC register space */
1654 if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
e4bbf2f5 1655 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
a0b907ee
FF		 1656 return AR5K_AR2315_PCI_BASE + reg;
1657
e0d687bd 1658 return ah->iobase + reg;
a0b907ee
FF		 1659}
1660
1661static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1662{
cede8b64 1663 return ioread32(ath5k_ahb_reg(ah, reg));
a0b907ee
FF		 1664}
1665
1666static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1667{
cede8b64 1668 iowrite32(val, ath5k_ahb_reg(ah, reg));
a0b907ee
FF		 1669}
1670
1671#else
1672
fa1c114f
JS		 1673static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1674{
e0d687bd 1675 return ioread32(ah->iobase + reg);
fa1c114f
JS		 1676}
1677
1678static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1679{
e0d687bd 1680 iowrite32(val, ah->iobase + reg);
fa1c114f
JS		 1681}
1682
a0b907ee
FF		 1683#endif
1684
1685static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
1686{
1687 return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
1688}
1689
132b1c3e
FF		 1690static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
1691{
1692 common->bus_ops->read_cachesize(common, csz);
1693}
1694
4aa5d783
FF		 1695static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
1696{
1697 struct ath_common *common = ath5k_hw_common(ah);
1698 return common->bus_ops->eeprom_read(common, off, data);
1699}
1700
c6e387a2
NK		 1701static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1702{
1703 u32 retval = 0, bit, i;
1704
1705 for (i = 0; i < bits; i++) {
1706 bit = (val >> i) & 1;
1707 retval = (retval << 1) | bit;
1708 }
1709
1710 return retval;
1711}
1712
fa1c114f 1713#endif
Linux kernel - Deliverables
This page took 0.870096 seconds and 5 git commands to generate.