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mac80211: make tx() operation return void
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / ath5k.h
CommitLineData
fa1c114f
JS		 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
c6e387a2
NK		 21/* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
fa1c114f
JS		 24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/types.h>
eef39bef 28#include <linux/average.h>
fa1c114f
JS		 29#include <net/mac80211.h>
30
c6e387a2
NK		 31/* RX/TX descriptor hw structs
32 * TODO: Driver part should only see sw structs */
33#include "desc.h"
34
35/* EEPROM structs/offsets
36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
37 * and clean up common bits, then introduce set/get functions in eeprom.c */
38#include "eeprom.h"
db719718 39#include "../ath.h"
fa1c114f
JS		 40
41/* PCI IDs */
42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
70
71/****************************\
72 GENERIC DRIVER DEFINITIONS
73\****************************/
74
75#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
76
77#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
78 printk(_level "ath5k %s: " _fmt, \
79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
80 ##__VA_ARGS__)
81
82#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
83 if (net_ratelimit()) \
84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
85 } while (0)
86
87#define ATH5K_INFO(_sc, _fmt, ...) \
88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
89
90#define ATH5K_WARN(_sc, _fmt, ...) \
91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
92
93#define ATH5K_ERR(_sc, _fmt, ...) \
94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
95
c6e387a2
NK		 96/*
97 * AR5K REGISTER ACCESS
98 */
99
100/* Some macros to read/write fields */
101
102/* First shift, then mask */
103#define AR5K_REG_SM(_val, _flags) \
104 (((_val) << _flags##_S) & (_flags))
105
106/* First mask, then shift */
107#define AR5K_REG_MS(_val, _flags) \
108 (((_val) & (_flags)) >> _flags##_S)
109
110/* Some registers can hold multiple values of interest. For this
111 * reason when we want to write to these registers we must first
112 * retrieve the values which we do not want to clear (lets call this
113 * old_data) and then set the register with this and our new_value:
114 * ( old_data | new_value) */
115#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
117 (((_val) << _flags##_S) & (_flags)), _reg)
118
119#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
121 (_mask)) | (_flags), _reg)
122
123#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
125
126#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
128
129/* Access to PHY registers */
130#define AR5K_PHY_READ(ah, _reg) \
131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
132
133#define AR5K_PHY_WRITE(ah, _reg, _val) \
134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
135
136/* Access QCU registers per queue */
137#define AR5K_REG_READ_Q(ah, _reg, _queue) \
138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
139
140#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
141 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
142
143#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
144 _reg |= 1 << _queue; \
145} while (0)
146
147#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
148 _reg &= ~(1 << _queue); \
149} while (0)
150
151/* Used while writing initvals */
152#define AR5K_REG_WAIT(_i) do { \
153 if (_i % 64) \
154 udelay(1); \
155} while (0)
156
fa1c114f
JS		 157/*
158 * Some tuneable values (these should be changeable by the user)
c6e387a2 159 * TODO: Make use of them and add more options OR use debug/configfs
fa1c114f
JS		 160 */
161#define AR5K_TUNE_DMA_BEACON_RESP 2
162#define AR5K_TUNE_SW_BEACON_RESP 10
163#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
164#define AR5K_TUNE_RADAR_ALERT false
165#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
b6127980 166#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
fa1c114f
JS		 167#define AR5K_TUNE_REGISTER_TIMEOUT 20000
168/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
169 * be the max value. */
c6e387a2 170#define AR5K_TUNE_RSSI_THRES 129
fa1c114f
JS		 171/* This must be set when setting the RSSI threshold otherwise it can
172 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
173 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
174 * track of it. Max value depends on harware. For AR5210 this is just 7.
175 * For AR5211+ this seems to be up to 255. */
c6e387a2 176#define AR5K_TUNE_BMISS_THRES 7
fa1c114f
JS		 177#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
178#define AR5K_TUNE_BEACON_INTERVAL 100
179#define AR5K_TUNE_AIFS 2
180#define AR5K_TUNE_AIFS_11B 2
181#define AR5K_TUNE_AIFS_XR 0
182#define AR5K_TUNE_CWMIN 15
183#define AR5K_TUNE_CWMIN_11B 31
184#define AR5K_TUNE_CWMIN_XR 3
185#define AR5K_TUNE_CWMAX 1023
186#define AR5K_TUNE_CWMAX_11B 1023
187#define AR5K_TUNE_CWMAX_XR 7
188#define AR5K_TUNE_NOISE_FLOOR -72
e5e2647f 189#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
8f655dde
NK		 190#define AR5K_TUNE_MAX_TXPOWER 63
191#define AR5K_TUNE_DEFAULT_TXPOWER 25
192#define AR5K_TUNE_TPC_TXPOWER false
1063b176 193#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */
2111ac0d 194#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
afe86286 195#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */
fa1c114f 196
4edd761f
BR		 197#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
198
c6e387a2
NK		 199#define AR5K_INIT_CARR_SENSE_EN 1
200
201/*Swap RX/TX Descriptor for big endian archs*/
202#if defined(__BIG_ENDIAN)
203#define AR5K_INIT_CFG ( \
204 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
205)
206#else
207#define AR5K_INIT_CFG 0x00000000
208#endif
209
210/* Initial values */
e8f055f0 211#define AR5K_INIT_CYCRSSI_THR1 2
eeb8832b 212
76a9f6fd
BR		 213/* Tx retry limit defaults from standard */
214#define AR5K_INIT_RETRY_SHORT 7
215#define AR5K_INIT_RETRY_LONG 4
c6e387a2 216
3017fcab
NK		 217/* Slot time */
218#define AR5K_INIT_SLOT_TIME_TURBO 6
219#define AR5K_INIT_SLOT_TIME_DEFAULT 9
220#define AR5K_INIT_SLOT_TIME_HALF_RATE 13
221#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
222#define AR5K_INIT_SLOT_TIME_B 20
223#define AR5K_SLOT_TIME_MAX 0xffff
224
225/* SIFS */
226#define AR5K_INIT_SIFS_TURBO 6
227/* XXX: 8 from initvals 10 from standard */
228#define AR5K_INIT_SIFS_DEFAULT_BG 8
229#define AR5K_INIT_SIFS_DEFAULT_A 16
230#define AR5K_INIT_SIFS_HALF_RATE 32
231#define AR5K_INIT_SIFS_QUARTER_RATE 64
232
61cde037
NK		 233/* Used to calculate tx time for non 5/10/40MHz
234 * operation */
235/* It's preamble time + signal time (16 + 4) */
236#define AR5K_INIT_OFDM_PREAMPLE_TIME 20
237/* Preamble time for 40MHz (turbo) operation (min ?) */
238#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14
239#define AR5K_INIT_OFDM_SYMBOL_TIME 4
240#define AR5K_INIT_OFDM_PLCP_BITS 22
241
c2975602
NK		 242/* Rx latency for 5 and 10MHz operation (max ?) */
243#define AR5K_INIT_RX_LAT_MAX 63
244/* Tx latencies from initvals (5212 only but no problem
245 * because we only tweak them on 5212) */
246#define AR5K_INIT_TX_LAT_A 54
247#define AR5K_INIT_TX_LAT_BG 384
248/* Tx latency for 40MHz (turbo) operation (min ?) */
249#define AR5K_INIT_TX_LAT_MIN 32
b405086b
NK		 250/* Default Tx/Rx latencies (same for 5211)*/
251#define AR5K_INIT_TX_LATENCY_5210 54
252#define AR5K_INIT_RX_LATENCY_5210 29
c2975602
NK		 253
254/* Tx frame to Tx data start delay */
255#define AR5K_INIT_TXF2TXD_START_DEFAULT 14
256#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
257#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
258
b405086b
NK		 259/* We need to increase PHY switch and agc settling time
260 * on turbo mode */
261#define AR5K_SWITCH_SETTLING 5760
262#define AR5K_SWITCH_SETTLING_TURBO 7168
263
264#define AR5K_AGC_SETTLING 28
265/* 38 on 5210 but shouldn't matter */
266#define AR5K_AGC_SETTLING_TURBO 37
c2975602 267
fa1c114f
JS		 268
269/* GENERIC CHIPSET DEFINITIONS */
270
271/* MAC Chips */
272enum ath5k_version {
273 AR5K_AR5210 = 0,
274 AR5K_AR5211 = 1,
275 AR5K_AR5212 = 2,
276};
277
278/* PHY Chips */
279enum ath5k_radio {
280 AR5K_RF5110 = 0,
281 AR5K_RF5111 = 1,
282 AR5K_RF5112 = 2,
8daeef97
NK		 283 AR5K_RF2413 = 3,
284 AR5K_RF5413 = 4,
1bef016a
NK		 285 AR5K_RF2316 = 5,
286 AR5K_RF2317 = 6,
287 AR5K_RF2425 = 7,
fa1c114f
JS		 288};
289
290/*
291 * Common silicon revision/version values
292 */
293
294enum ath5k_srev_type {
1bef016a 295 AR5K_VERSION_MAC,
fa1c114f
JS		 296 AR5K_VERSION_RAD,
297};
298
299struct ath5k_srev_name {
300 const char *sr_name;
301 enum ath5k_srev_type sr_type;
302 u_int sr_val;
303};
304
305#define AR5K_SREV_UNKNOWN 0xffff
306
1bef016a
NK		 307#define AR5K_SREV_AR5210 0x00 /* Crete */
308#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
309#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
310#define AR5K_SREV_AR5311B 0x30 /* Spirit */
311#define AR5K_SREV_AR5211 0x40 /* Oahu */
312#define AR5K_SREV_AR5212 0x50 /* Venice */
a0b907ee 313#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */
ca5efbe2 314#define AR5K_SREV_AR5212_V4 0x54 /* ??? */
1bef016a 315#define AR5K_SREV_AR5213 0x55 /* ??? */
a0b907ee
FF		 316#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */
317#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */
1bef016a
NK		 318#define AR5K_SREV_AR5213A 0x59 /* Hainan */
319#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
320#define AR5K_SREV_AR2414 0x70 /* Griffin */
a0b907ee
FF		 321#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
322#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
1bef016a 323#define AR5K_SREV_AR5424 0x90 /* Condor */
a0b907ee
FF		 324#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
325#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
1bef016a
NK		 326#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
327#define AR5K_SREV_AR5414 0xa0 /* Eagle */
e8f055f0 328#define AR5K_SREV_AR2415 0xb0 /* Talon */
1bef016a
NK		 329#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
330#define AR5K_SREV_AR5418 0xca /* PCI-E */
331#define AR5K_SREV_AR2425 0xe0 /* Swan */
332#define AR5K_SREV_AR2417 0xf0 /* Nala */
fa1c114f
JS		 333
334#define AR5K_SREV_RAD_5110 0x00
335#define AR5K_SREV_RAD_5111 0x10
336#define AR5K_SREV_RAD_5111A 0x15
337#define AR5K_SREV_RAD_2111 0x20
338#define AR5K_SREV_RAD_5112 0x30
339#define AR5K_SREV_RAD_5112A 0x35
e5a4ad0d 340#define AR5K_SREV_RAD_5112B 0x36
fa1c114f
JS		 341#define AR5K_SREV_RAD_2112 0x40
342#define AR5K_SREV_RAD_2112A 0x45
e5a4ad0d 343#define AR5K_SREV_RAD_2112B 0x46
1bef016a
NK		 344#define AR5K_SREV_RAD_2413 0x50
345#define AR5K_SREV_RAD_5413 0x60
e8f055f0 346#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
1bef016a
NK		 347#define AR5K_SREV_RAD_2317 0x80
348#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
349#define AR5K_SREV_RAD_2425 0xa2
350#define AR5K_SREV_RAD_5133 0xc0
351
352#define AR5K_SREV_PHY_5211 0x30
353#define AR5K_SREV_PHY_5212 0x41
8892e4ec 354#define AR5K_SREV_PHY_5212A 0x42
e8f055f0 355#define AR5K_SREV_PHY_5212B 0x43
1bef016a
NK		 356#define AR5K_SREV_PHY_2413 0x45
357#define AR5K_SREV_PHY_5413 0x61
358#define AR5K_SREV_PHY_2425 0x70
fa1c114f 359
fa1c114f
JS		 360/* TODO add support to mac80211 for vendor-specific rates and modes */
361
362/*
363 * Some of this information is based on Documentation from:
364 *
631dd1a8 365 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
fa1c114f
JS		 366 *
367 * Modulation for Atheros' eXtended Range - range enhancing extension that is
368 * supposed to double the distance an Atheros client device can keep a
369 * connection with an Atheros access point. This is achieved by increasing
370 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
371 * the 802.11 specifications demand. In addition, new (proprietary) data rates
372 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
373 *
374 * Please note that can you either use XR or TURBO but you cannot use both,
375 * they are exclusive.
376 *
377 */
378#define MODULATION_XR 0x00000200
379/*
380 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
381 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
382 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
383 * channels. To use this feature your Access Point must also suport it.
384 * There is also a distinction between "static" and "dynamic" turbo modes:
385 *
386 * - Static: is the dumb version: devices set to this mode stick to it until
387 * the mode is turned off.
388 * - Dynamic: is the intelligent version, the network decides itself if it
389 * is ok to use turbo. As soon as traffic is detected on adjacent channels
390 * (which would get used in turbo mode), or when a non-turbo station joins
391 * the network, turbo mode won't be used until the situation changes again.
392 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
393 * monitors the used radio band in order to decide whether turbo mode may
394 * be used or not.
395 *
396 * This article claims Super G sticks to bonding of channels 5 and 6 for
397 * USA:
398 *
399 * http://www.pcworld.com/article/id,113428-page,1/article.html
400 *
401 * The channel bonding seems to be driver specific though. In addition to
402 * deciding what channels will be used, these "Turbo" modes are accomplished
403 * by also enabling the following features:
404 *
405 * - Bursting: allows multiple frames to be sent at once, rather than pausing
406 * after each frame. Bursting is a standards-compliant feature that can be
407 * used with any Access Point.
408 * - Fast frames: increases the amount of information that can be sent per
409 * frame, also resulting in a reduction of transmission overhead. It is a
410 * proprietary feature that needs to be supported by the Access Point.
411 * - Compression: data frames are compressed in real time using a Lempel Ziv
412 * algorithm. This is done transparently. Once this feature is enabled,
413 * compression and decompression takes place inside the chipset, without
414 * putting additional load on the host CPU.
415 *
416 */
417#define MODULATION_TURBO 0x00000080
418
d8ee398d
LR		 419enum ath5k_driver_mode {
420 AR5K_MODE_11A = 0,
8c2b418a
NK		 421 AR5K_MODE_11B = 1,
422 AR5K_MODE_11G = 2,
d8ee398d 423 AR5K_MODE_XR = 0,
8c2b418a 424 AR5K_MODE_MAX = 3
fa1c114f
JS		 425};
426
2bed03eb
NK		 427enum ath5k_ant_mode {
428 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */
429 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */
430 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */
431 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */
432 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */
433 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */
434 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */
435 AR5K_ANTMODE_MAX,
436};
437
fa3d2fee
NK		 438enum ath5k_bw_mode {
439 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */
440 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */
441 AR5K_BWMODE_10MHZ = 2, /* Half rate */
442 AR5K_BWMODE_40MHZ = 3 /* Turbo */
443};
19fd6e55 444
fa1c114f
JS		 445/****************\
446 TX DEFINITIONS
447\****************/
448
449/*
c6e387a2 450 * TX Status descriptor
fa1c114f
JS		 451 */
452struct ath5k_tx_status {
453 u16 ts_seqnum;
454 u16 ts_tstamp;
455 u8 ts_status;
2f7fe870
FF		 456 u8 ts_rate[4];
457 u8 ts_retry[4];
458 u8 ts_final_idx;
fa1c114f
JS		 459 s8 ts_rssi;
460 u8 ts_shortretry;
461 u8 ts_longretry;
462 u8 ts_virtcol;
463 u8 ts_antenna;
464};
465
466#define AR5K_TXSTAT_ALTRATE 0x80
467#define AR5K_TXERR_XRETRY 0x01
468#define AR5K_TXERR_FILT 0x02
469#define AR5K_TXERR_FIFO 0x04
470
471/**
472 * enum ath5k_tx_queue - Queue types used to classify tx queues.
473 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
474 * @AR5K_TX_QUEUE_DATA: A normal data queue
475 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
476 * @AR5K_TX_QUEUE_BEACON: The beacon queue
477 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
478 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
479 */
480enum ath5k_tx_queue {
481 AR5K_TX_QUEUE_INACTIVE = 0,
482 AR5K_TX_QUEUE_DATA,
483 AR5K_TX_QUEUE_XR_DATA,
484 AR5K_TX_QUEUE_BEACON,
485 AR5K_TX_QUEUE_CAB,
486 AR5K_TX_QUEUE_UAPSD,
487};
488
489#define AR5K_NUM_TX_QUEUES 10
490#define AR5K_NUM_TX_QUEUES_NOQCU 2
491
492/*
493 * Queue syb-types to classify normal data queues.
494 * These are the 4 Access Categories as defined in
495 * WME spec. 0 is the lowest priority and 4 is the
496 * highest. Normal data that hasn't been classified
497 * goes to the Best Effort AC.
498 */
499enum ath5k_tx_queue_subtype {
500 AR5K_WME_AC_BK = 0, /*Background traffic*/
501 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
502 AR5K_WME_AC_VI, /*Video traffic*/
503 AR5K_WME_AC_VO, /*Voice traffic*/
504};
505
506/*
507 * Queue ID numbers as returned by the hw functions, each number
508 * represents a hw queue. If hw does not support hw queues
509 * (eg 5210) all data goes in one queue. These match
510 * d80211 definitions (net80211/MadWiFi don't use them).
511 */
512enum ath5k_tx_queue_id {
513 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
514 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
515 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
516 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
517 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
518 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
519 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
520 AR5K_TX_QUEUE_ID_UAPSD = 8,
521 AR5K_TX_QUEUE_ID_XR_DATA = 9,
522};
523
fa1c114f
JS		 524/*
525 * Flags to set hw queue's parameters...
526 */
527#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
528#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
529#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
530#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
531#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
4c674c60
NK		 532#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
533#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
534#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
535#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
536#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
537#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
538#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
539#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
540#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
fa1c114f
JS		 541
542/*
543 * A struct to hold tx queue's parameters
544 */
545struct ath5k_txq_info {
546 enum ath5k_tx_queue tqi_type;
547 enum ath5k_tx_queue_subtype tqi_subtype;
548 u16 tqi_flags; /* Tx queue flags (see above) */
de8af455
BR		 549 u8 tqi_aifs; /* Arbitrated Interframe Space */
550 u16 tqi_cw_min; /* Minimum Contention Window */
551 u16 tqi_cw_max; /* Maximum Contention Window */
fa1c114f
JS		 552 u32 tqi_cbr_period; /* Constant bit rate period */
553 u32 tqi_cbr_overflow_limit;
554 u32 tqi_burst_time;
a951ae21 555 u32 tqi_ready_time; /* Time queue waits after an event */
fa1c114f
JS		 556};
557
558/*
559 * Transmit packet types.
c6e387a2 560 * used on tx control descriptor
fa1c114f
JS		 561 */
562enum ath5k_pkt_type {
563 AR5K_PKT_TYPE_NORMAL = 0,
564 AR5K_PKT_TYPE_ATIM = 1,
565 AR5K_PKT_TYPE_PSPOLL = 2,
566 AR5K_PKT_TYPE_BEACON = 3,
567 AR5K_PKT_TYPE_PROBE_RESP = 4,
568 AR5K_PKT_TYPE_PIFS = 5,
569};
570
571/*
572 * TX power and TPC settings
573 */
574#define AR5K_TXPOWER_OFDM(_r, _v) ( \
575 ((0 & 1) << ((_v) + 6)) | \
8f655dde 576 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
fa1c114f
JS		 577)
578
579#define AR5K_TXPOWER_CCK(_r, _v) ( \
8f655dde 580 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
fa1c114f
JS		 581)
582
583/*
beade636 584 * DMA size definitions (2^(n+2))
fa1c114f
JS		 585 */
586enum ath5k_dmasize {
587 AR5K_DMASIZE_4B = 0,
588 AR5K_DMASIZE_8B,
589 AR5K_DMASIZE_16B,
590 AR5K_DMASIZE_32B,
591 AR5K_DMASIZE_64B,
592 AR5K_DMASIZE_128B,
593 AR5K_DMASIZE_256B,
594 AR5K_DMASIZE_512B
595};
596
597
598/****************\
599 RX DEFINITIONS
600\****************/
601
602/*
c6e387a2 603 * RX Status descriptor
fa1c114f
JS		 604 */
605struct ath5k_rx_status {
606 u16 rs_datalen;
607 u16 rs_tstamp;
608 u8 rs_status;
609 u8 rs_phyerr;
610 s8 rs_rssi;
611 u8 rs_keyix;
612 u8 rs_rate;
613 u8 rs_antenna;
614 u8 rs_more;
615};
616
617#define AR5K_RXERR_CRC 0x01
618#define AR5K_RXERR_PHY 0x02
619#define AR5K_RXERR_FIFO 0x04
620#define AR5K_RXERR_DECRYPT 0x08
621#define AR5K_RXERR_MIC 0x10
622#define AR5K_RXKEYIX_INVALID ((u8) - 1)
623#define AR5K_TXKEYIX_INVALID ((u32) - 1)
624
fa1c114f 625
fa1c114f
JS		 626/**************************\
627 BEACON TIMERS DEFINITIONS
628\**************************/
629
630#define AR5K_BEACON_PERIOD 0x0000ffff
631#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
632#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
633
fa1c114f
JS		 634
635/*
636 * TSF to TU conversion:
637 *
638 * TSF is a 64bit value in usec (microseconds).
e535c1ac
BR		 639 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
640 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
fa1c114f
JS		 641 */
642#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
643
644
c6e387a2
NK		 645/*******************************\
646 GAIN OPTIMIZATION DEFINITIONS
647\*******************************/
648
649enum ath5k_rfgain {
650 AR5K_RFGAIN_INACTIVE = 0,
6f3b414a 651 AR5K_RFGAIN_ACTIVE,
c6e387a2
NK		 652 AR5K_RFGAIN_READ_REQUESTED,
653 AR5K_RFGAIN_NEED_CHANGE,
654};
655
c6e387a2 656struct ath5k_gain {
6f3b414a
NK		 657 u8 g_step_idx;
658 u8 g_current;
659 u8 g_target;
660 u8 g_low;
661 u8 g_high;
662 u8 g_f_corr;
663 u8 g_state;
c6e387a2
NK		 664};
665
fa1c114f
JS		 666/********************\
667 COMMON DEFINITIONS
668\********************/
669
fa1c114f
JS		 670#define AR5K_SLOT_TIME_9 396
671#define AR5K_SLOT_TIME_20 880
672#define AR5K_SLOT_TIME_MAX 0xffff
673
674/* channel_flags */
675#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
fa1c114f
JS		 676#define CHANNEL_CCK 0x0020 /* CCK channel */
677#define CHANNEL_OFDM 0x0040 /* OFDM channel */
678#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
679#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
680#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
681#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
682#define CHANNEL_XR 0x0800 /* XR channel */
683
684#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
685#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
686#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
fa1c114f
JS		 687#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
688
acb091d6 689#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ)
fa1c114f 690
fa1c114f
JS		 691#define CHANNEL_MODES CHANNEL_ALL
692
693/*
c6e387a2
NK		 694 * Used internaly for reset_tx_queue).
695 * Also see struct struct ieee80211_channel.
fa1c114f 696 */
46026e8f
BC		 697#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
698#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
fa1c114f
JS		 699
700/*
c6e387a2 701 * The following structure is used to map 2GHz channels to
fa1c114f 702 * 5GHz Atheros channels.
c6e387a2 703 * TODO: Clean up
fa1c114f
JS		 704 */
705struct ath5k_athchan_2ghz {
706 u32 a2_flags;
707 u16 a2_athchan;
708};
709
63266a65 710
c6e387a2
NK		 711/******************\
712 RATE DEFINITIONS
713\******************/
fa1c114f 714
fa1c114f 715/**
63266a65 716 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
fa1c114f 717 *
63266a65 718 * The rate code is used to get the RX rate or set the TX rate on the
fa1c114f
JS		 719 * hardware descriptors. It is also used for internal modulation control
720 * and settings.
721 *
63266a65 722 * This is the hardware rate map we are aware of:
fa1c114f 723 *
63266a65 724 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
fa1c114f
JS		 725 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
726 *
63266a65 727 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
fa1c114f
JS		 728 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
729 *
730 * rate_code 17 18 19 20 21 22 23 24
731 * rate_kbps ? ? ? ? ? ? ? 11000
732 *
733 * rate_code 25 26 27 28 29 30 31 32
63266a65
BR		 734 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
735 *
736 * "S" indicates CCK rates with short preamble.
fa1c114f 737 *
63266a65
BR		 738 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
739 * lowest 4 bits, so they are the same as below with a 0xF mask.
740 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
741 * We handle this in ath5k_setup_bands().
fa1c114f 742 */
63266a65 743#define AR5K_MAX_RATES 32
fa1c114f 744
63266a65
BR		 745/* B */
746#define ATH5K_RATE_CODE_1M 0x1B
747#define ATH5K_RATE_CODE_2M 0x1A
748#define ATH5K_RATE_CODE_5_5M 0x19
749#define ATH5K_RATE_CODE_11M 0x18
750/* A and G */
751#define ATH5K_RATE_CODE_6M 0x0B
752#define ATH5K_RATE_CODE_9M 0x0F
753#define ATH5K_RATE_CODE_12M 0x0A
754#define ATH5K_RATE_CODE_18M 0x0E
755#define ATH5K_RATE_CODE_24M 0x09
756#define ATH5K_RATE_CODE_36M 0x0D
757#define ATH5K_RATE_CODE_48M 0x08
758#define ATH5K_RATE_CODE_54M 0x0C
759/* XR */
760#define ATH5K_RATE_CODE_XR_500K 0x07
761#define ATH5K_RATE_CODE_XR_1M 0x02
762#define ATH5K_RATE_CODE_XR_2M 0x06
763#define ATH5K_RATE_CODE_XR_3M 0x01
fa1c114f 764
c6e387a2
NK		 765/* adding this flag to rate_code enables short preamble */
766#define AR5K_SET_SHORT_PREAMBLE 0x04
fa1c114f
JS		 767
768/*
769 * Crypto definitions
770 */
771
772#define AR5K_KEYCACHE_SIZE 8
773
774/***********************\
775 HW RELATED DEFINITIONS
776\***********************/
777
778/*
779 * Misc definitions
780 */
781#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
782
783#define AR5K_ASSERT_ENTRY(_e, _s) do { \
784 if (_e >= _s) \
785 return (false); \
786} while (0)
787
fa1c114f
JS		 788/*
789 * Hardware interrupt abstraction
790 */
791
792/**
793 * enum ath5k_int - Hardware interrupt masks helpers
794 *
795 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
796 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
797 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
798 * @AR5K_INT_RXNOFRM: No frame received (?)
799 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
800 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
801 * LinkPtr is NULL. For more details, refer to:
802 * http://www.freepatentsonline.com/20030225739.html
803 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
804 * Note that Rx overrun is not always fatal, on some chips we can continue
805 * operation without reseting the card, that's why int_fatal is not
806 * common for all chips.
807 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
808 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
809 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
810 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
811 * We currently do increments on interrupt by
812 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
2111ac0d
BR		 813 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
814 * one of the PHY error counters reached the maximum value and should be
815 * read and cleared.
fa1c114f 816 * @AR5K_INT_RXPHY: RX PHY Error
4c674c60 817 * @AR5K_INT_RXKCM: RX Key cache miss
fa1c114f
JS		 818 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
819 * beacon that must be handled in software. The alternative is if you
820 * have VEOL support, in that case you let the hardware deal with things.
821 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
822 * beacons from the AP have associated with, we should probably try to
823 * reassociate. When in IBSS mode this might mean we have not received
824 * any beacons from any local stations. Note that every station in an
825 * IBSS schedules to send beacons at the Target Beacon Transmission Time
826 * (TBTT) with a random backoff.
827 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
828 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
829 * until properly handled
830 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
831 * errors. These types of errors we can enable seem to be of type
832 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
4c674c60 833 * @AR5K_INT_GLOBAL: Used to clear and set the IER
fa1c114f
JS		 834 * @AR5K_INT_NOCARD: signals the card has been removed
835 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
836 * bit value
837 *
838 * These are mapped to take advantage of some common bits
839 * between the MACs, to be able to set intr properties
840 * easier. Some of them are not used yet inside hw.c. Most map
841 * to the respective hw interrupt value as they are common amogst different
842 * MACs.
843 */
844enum ath5k_int {
4c674c60 845 AR5K_INT_RXOK = 0x00000001,
fa1c114f 846 AR5K_INT_RXDESC = 0x00000002,
4c674c60 847 AR5K_INT_RXERR = 0x00000004,
fa1c114f
JS		 848 AR5K_INT_RXNOFRM = 0x00000008,
849 AR5K_INT_RXEOL = 0x00000010,
850 AR5K_INT_RXORN = 0x00000020,
4c674c60 851 AR5K_INT_TXOK = 0x00000040,
fa1c114f 852 AR5K_INT_TXDESC = 0x00000080,
4c674c60
NK		 853 AR5K_INT_TXERR = 0x00000100,
854 AR5K_INT_TXNOFRM = 0x00000200,
855 AR5K_INT_TXEOL = 0x00000400,
fa1c114f
JS		 856 AR5K_INT_TXURN = 0x00000800,
857 AR5K_INT_MIB = 0x00001000,
4c674c60 858 AR5K_INT_SWI = 0x00002000,
fa1c114f
JS		 859 AR5K_INT_RXPHY = 0x00004000,
860 AR5K_INT_RXKCM = 0x00008000,
861 AR5K_INT_SWBA = 0x00010000,
4c674c60 862 AR5K_INT_BRSSI = 0x00020000,
fa1c114f 863 AR5K_INT_BMISS = 0x00040000,
4c674c60
NK		 864 AR5K_INT_FATAL = 0x00080000, /* Non common */
865 AR5K_INT_BNR = 0x00100000, /* Non common */
866 AR5K_INT_TIM = 0x00200000, /* Non common */
867 AR5K_INT_DTIM = 0x00400000, /* Non common */
868 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
869 AR5K_INT_GPIO = 0x01000000,
870 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
871 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
872 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
873 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
874 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
875 AR5K_INT_QTRIG = 0x40000000, /* Non common */
876 AR5K_INT_GLOBAL = 0x80000000,
877
878 AR5K_INT_COMMON = AR5K_INT_RXOK
879 | AR5K_INT_RXDESC
880 | AR5K_INT_RXERR
881 | AR5K_INT_RXNOFRM
882 | AR5K_INT_RXEOL
883 | AR5K_INT_RXORN
884 | AR5K_INT_TXOK
885 | AR5K_INT_TXDESC
886 | AR5K_INT_TXERR
887 | AR5K_INT_TXNOFRM
888 | AR5K_INT_TXEOL
889 | AR5K_INT_TXURN
890 | AR5K_INT_MIB
891 | AR5K_INT_SWI
892 | AR5K_INT_RXPHY
893 | AR5K_INT_RXKCM
894 | AR5K_INT_SWBA
895 | AR5K_INT_BRSSI
896 | AR5K_INT_BMISS
897 | AR5K_INT_GPIO
898 | AR5K_INT_GLOBAL,
899
fa1c114f
JS		 900 AR5K_INT_NOCARD = 0xffffffff
901};
902
e65e1d77
BR		 903/* mask which calibration is active at the moment */
904enum ath5k_calibration_mask {
905 AR5K_CALIBRATION_FULL = 0x01,
906 AR5K_CALIBRATION_SHORT = 0x02,
2111ac0d 907 AR5K_CALIBRATION_ANI = 0x04,
6e220662
NK		 908};
909
fa1c114f
JS		 910/*
911 * Power management
912 */
913enum ath5k_power_mode {
914 AR5K_PM_UNDEFINED = 0,
915 AR5K_PM_AUTO,
916 AR5K_PM_AWAKE,
917 AR5K_PM_FULL_SLEEP,
918 AR5K_PM_NETWORK_SLEEP,
919};
920
921/*
922 * These match net80211 definitions (not used in
c6e387a2
NK		 923 * mac80211).
924 * TODO: Clean this up
fa1c114f
JS		 925 */
926#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
927#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
928#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
929#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
930#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
931
932/* GPIO-controlled software LED */
933#define AR5K_SOFTLED_PIN 0
934#define AR5K_SOFTLED_ON 0
935#define AR5K_SOFTLED_OFF 1
936
937/*
938 * Chipset capabilities -see ath5k_hw_get_capability-
939 * get_capability function is not yet fully implemented
c6e387a2
NK		 940 * in ath5k so most of these don't work yet...
941 * TODO: Implement these & merge with _TUNE_ stuff above
fa1c114f
JS		 942 */
943enum ath5k_capability_type {
944 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
945 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
946 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
947 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
948 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
949 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
950 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
951 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
952 AR5K_CAP_BURST = 9, /* Supports packet bursting */
953 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
954 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
955 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
956 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
957 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
958 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
959 AR5K_CAP_XR = 16, /* Supports XR mode */
960 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
961 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
962 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
963 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
964};
965
400ec45a
LR		 966
967/* XXX: we *may* move cap_range stuff to struct wiphy */
fa1c114f
JS		 968struct ath5k_capabilities {
969 /*
970 * Supported PHY modes
971 * (ie. CHANNEL_A, CHANNEL_B, ...)
972 */
d8ee398d 973 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
fa1c114f
JS		 974
975 /*
976 * Frequency range (without regulation restrictions)
977 */
978 struct {
979 u16 range_2ghz_min;
980 u16 range_2ghz_max;
981 u16 range_5ghz_min;
982 u16 range_5ghz_max;
983 } cap_range;
984
fa1c114f
JS		 985 /*
986 * Values stored in the EEPROM (some of them...)
987 */
988 struct ath5k_eeprom_info cap_eeprom;
989
990 /*
991 * Queue information
992 */
993 struct {
994 u8 q_tx_num;
995 } cap_queues;
a8c944f8
BR		 996
997 bool cap_has_phyerr_counters;
fa1c114f
JS		 998};
999
e5e2647f
BC		 1000/* size of noise floor history (keep it a power of two) */
1001#define ATH5K_NF_CAL_HIST_MAX 8
1002struct ath5k_nfcal_hist
1003{
1004 s16 index; /* current index into nfval */
1005 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1006};
1007
b4ea449d
BR		 1008/**
1009 * struct avg_val - Helper structure for average calculation
1010 * @avg: contains the actual average value
1011 * @avg_weight: is used internally during calculation to prevent rounding errors
1012 */
1013struct ath5k_avg_val {
1014 int avg;
1015 int avg_weight;
1016};
fa1c114f
JS		 1017
1018/***************************************\
1019 HARDWARE ABSTRACTION LAYER STRUCTURE
1020\***************************************/
1021
1022/*
1023 * Misc defines
1024 */
1025
1026#define AR5K_MAX_GPIO 10
1027#define AR5K_MAX_RF_BANKS 8
1028
c6e387a2 1029/* TODO: Clean up and merge with ath5k_softc */
fa1c114f 1030struct ath5k_hw {
db719718 1031 struct ath_common common;
fa1c114f
JS		 1032
1033 struct ath5k_softc *ah_sc;
1034 void __iomem *ah_iobase;
1035
1036 enum ath5k_int ah_imr;
1037
46026e8f 1038 struct ieee80211_channel *ah_current_channel;
fa1c114f 1039 bool ah_calibration;
fa1c114f 1040 bool ah_single_chip;
fa1c114f 1041
46026e8f
BC		 1042 enum ath5k_version ah_version;
1043 enum ath5k_radio ah_radio;
1044 u32 ah_phy;
fa1c114f
JS		 1045 u32 ah_mac_srev;
1046 u16 ah_mac_version;
e7aecd32 1047 u16 ah_mac_revision;
fa1c114f
JS		 1048 u16 ah_phy_revision;
1049 u16 ah_radio_5ghz_revision;
1050 u16 ah_radio_2ghz_revision;
1051
fa1c114f
JS		 1052#define ah_modes ah_capabilities.cap_mode
1053#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1054
76a9f6fd
BR		 1055 u8 ah_retry_long;
1056 u8 ah_retry_short;
1057
6e08d228 1058 u8 ah_coverage_class;
61cde037 1059 bool ah_ack_bitrate_high;
fa3d2fee 1060 u8 ah_bwmode;
fa1c114f 1061
2bed03eb
NK		 1062 /* Antenna Control */
1063 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1064 u8 ah_ant_mode;
1065 u8 ah_tx_ant;
1066 u8 ah_def_ant;
fa1c114f 1067
fa1c114f
JS		 1068 struct ath5k_capabilities ah_capabilities;
1069
1070 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1071 u32 ah_txq_status;
1072 u32 ah_txq_imr_txok;
1073 u32 ah_txq_imr_txerr;
1074 u32 ah_txq_imr_txurn;
1075 u32 ah_txq_imr_txdesc;
1076 u32 ah_txq_imr_txeol;
4c674c60
NK		 1077 u32 ah_txq_imr_cbrorn;
1078 u32 ah_txq_imr_cbrurn;
1079 u32 ah_txq_imr_qtrig;
1080 u32 ah_txq_imr_nofrm;
1081 u32 ah_txq_isr;
fa1c114f
JS		 1082 u32 *ah_rf_banks;
1083 size_t ah_rf_banks_size;
8892e4ec 1084 size_t ah_rf_regs_count;
fa1c114f 1085 struct ath5k_gain ah_gain;
8892e4ec 1086 u8 ah_offset[AR5K_MAX_RF_BANKS];
fa1c114f 1087
8f655dde 1088
fa1c114f 1089 struct {
8f655dde
NK		 1090 /* Temporary tables used for interpolation */
1091 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1092 [AR5K_EEPROM_POWER_TABLE_SIZE];
1093 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1094 [AR5K_EEPROM_POWER_TABLE_SIZE];
1095 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1096 u16 txp_rates_power_table[AR5K_MAX_RATES];
1097 u8 txp_min_idx;
fa1c114f 1098 bool txp_tpc;
8f655dde
NK		 1099 /* Values in 0.25dB units */
1100 s16 txp_min_pwr;
1101 s16 txp_max_pwr;
51f00622 1102 s16 txp_cur_pwr;
a0823810 1103 /* Values in 0.5dB units */
8f655dde 1104 s16 txp_offset;
fa1c114f 1105 s16 txp_ofdm;
8f655dde 1106 s16 txp_cck_ofdm_gainf_delta;
a0823810
NK		 1107 /* Value in dB units */
1108 s16 txp_cck_ofdm_pwr_delta;
26c7fc43 1109 bool txp_setup;
fa1c114f
JS		 1110 } ah_txpower;
1111
1112 struct {
1113 bool r_enabled;
1114 int r_last_alert;
1115 struct ieee80211_channel r_last_channel;
1116 } ah_radar;
1117
e5e2647f
BC		 1118 struct ath5k_nfcal_hist ah_nfcal_hist;
1119
b4ea449d 1120 /* average beacon RSSI in our BSS (used by ANI) */
eef39bef 1121 struct ewma ah_beacon_rssi_avg;
b4ea449d 1122
fa1c114f
JS		 1123 /* noise floor from last periodic calibration */
1124 s32 ah_noise_floor;
1125
6e220662 1126 /* Calibration timestamp */
a9167f96 1127 unsigned long ah_cal_next_full;
2111ac0d 1128 unsigned long ah_cal_next_ani;
afe86286 1129 unsigned long ah_cal_next_nf;
6e220662 1130
e65e1d77
BR		 1131 /* Calibration mask */
1132 u8 ah_cal_mask;
6e220662 1133
fa1c114f
JS		 1134 /*
1135 * Function pointers
1136 */
1137 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
8127fbdc 1138 unsigned int, unsigned int, int, enum ath5k_pkt_type,
fa1c114f 1139 unsigned int, unsigned int, unsigned int, unsigned int,
8127fbdc 1140 unsigned int, unsigned int, unsigned int, unsigned int);
b47f407b
BR		 1141 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1142 struct ath5k_tx_status *);
1143 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1144 struct ath5k_rx_status *);
fa1c114f
JS		 1145};
1146
1147/*
1148 * Prototypes
1149 */
e5b046d8 1150extern const struct ieee80211_ops ath5k_hw_ops;
fa1c114f 1151
132b1c3e
FF		 1152/* Initialization and detach functions */
1153int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops);
1154void ath5k_deinit_softc(struct ath5k_softc *sc);
1155int ath5k_hw_init(struct ath5k_softc *sc);
1156void ath5k_hw_deinit(struct ath5k_hw *ah);
c6e387a2 1157
40ca22ea
BR		 1158int ath5k_sysfs_register(struct ath5k_softc *sc);
1159void ath5k_sysfs_unregister(struct ath5k_softc *sc);
1160
12873372
BC		 1161/* base.c */
1162struct ath5k_buf;
1163struct ath5k_txq;
1164
1165void set_beacon_filter(struct ieee80211_hw *hw, bool enable);
1166bool ath_any_vif_assoc(struct ath5k_softc *sc);
7bb45683
JB		 1167void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1168 struct ath5k_txq *txq);
12873372
BC		 1169int ath5k_init_hw(struct ath5k_softc *sc);
1170int ath5k_stop_hw(struct ath5k_softc *sc);
1171void ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif);
1172void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
1173 struct ieee80211_vif *vif);
1174int ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan);
1175void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
1176int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1177void ath5k_beacon_config(struct ath5k_softc *sc);
1178void ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf);
1179void ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf);
1180
e7aecd32 1181/*Chip id helper functions */
e5b046d8 1182const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
e7aecd32 1183int ath5k_hw_read_srev(struct ath5k_hw *ah);
9320b5c4 1184
0ed4548f 1185/* LED functions */
a25d1e4c
PR		 1186int ath5k_init_leds(struct ath5k_softc *sc);
1187void ath5k_led_enable(struct ath5k_softc *sc);
1188void ath5k_led_off(struct ath5k_softc *sc);
1189void ath5k_unregister_leds(struct ath5k_softc *sc);
0ed4548f 1190
9320b5c4 1191
fa1c114f 1192/* Reset Functions */
a25d1e4c
PR		 1193int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1194int ath5k_hw_on_hold(struct ath5k_hw *ah);
1195int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
8aec7af9 1196 struct ieee80211_channel *channel, bool fast, bool skip_pcu);
ec182d97
PR		 1197int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1198 bool is_set);
fa1c114f 1199/* Power management functions */
c6e387a2 1200
9320b5c4
NK		 1201
1202/* Clock rate related functions */
1203unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1204unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1205void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1206
1207
fa1c114f 1208/* DMA Related Functions */
a25d1e4c 1209void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
a25d1e4c 1210u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
e8325ed8 1211int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
a25d1e4c 1212int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
14fae2d4 1213int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
a25d1e4c
PR		 1214u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1215int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
c6e387a2 1216 u32 phys_addr);
a25d1e4c 1217int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
fa1c114f 1218/* Interrupt handling */
a25d1e4c
PR		 1219bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1220int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1221enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
495391d7 1222void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
d41174fa 1223/* Init/Stop functions */
9320b5c4 1224void ath5k_hw_dma_init(struct ath5k_hw *ah);
d41174fa 1225int ath5k_hw_dma_stop(struct ath5k_hw *ah);
c6e387a2 1226
fa1c114f 1227/* EEPROM access functions */
a25d1e4c
PR		 1228int ath5k_eeprom_init(struct ath5k_hw *ah);
1229void ath5k_eeprom_detach(struct ath5k_hw *ah);
1230int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
c6e387a2 1231
9320b5c4 1232
fa1c114f 1233/* Protocol Control Unit Functions */
eeb8832b
NK		 1234/* Helpers */
1235int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
1236 int len, struct ieee80211_rate *rate);
71ba1c30 1237unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
eeb8832b 1238unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
ccfe5552 1239extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
a25d1e4c 1240void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
9320b5c4 1241/* RX filter control*/
a25d1e4c 1242int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
418de6d9 1243void ath5k_hw_set_bssid(struct ath5k_hw *ah);
a25d1e4c 1244void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
a25d1e4c
PR		 1245void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1246u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1247void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
9320b5c4
NK		 1248/* Receive (DRU) start/stop functions */
1249void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1250void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
c6e387a2 1251/* Beacon control functions */
a25d1e4c
PR		 1252u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1253void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1254void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1255void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
7f896126 1256bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
9320b5c4
NK		 1257/* Init function */
1258void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1259 u8 mode);
c6e387a2 1260
fa1c114f 1261/* Queue Control Unit, DFS Control Unit Functions */
a25d1e4c
PR		 1262int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1263 struct ath5k_txq_info *queue_info);
1264int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1265 const struct ath5k_txq_info *queue_info);
1266int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1267 enum ath5k_tx_queue queue_type,
1268 struct ath5k_txq_info *queue_info);
76a9f6fd
BR		 1269void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
1270 unsigned int queue);
a25d1e4c
PR		 1271u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1272void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1273int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
eeb8832b 1274int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
9320b5c4
NK		 1275/* Init function */
1276int ath5k_hw_init_queues(struct ath5k_hw *ah);
c6e387a2 1277
fa1c114f 1278/* Hardware Descriptor Functions */
a25d1e4c 1279int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
a6668193
BR		 1280int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1281 u32 size, unsigned int flags);
1282int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1283 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1284 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
c6e387a2 1285
9320b5c4 1286
fa1c114f 1287/* GPIO Functions */
a25d1e4c
PR		 1288void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1289int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1290int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1291u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1292int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1293void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1294 u32 interrupt_level);
c6e387a2 1295
9320b5c4
NK		 1296
1297/* RFkill Functions */
a25d1e4c
PR		 1298void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1299void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
e6a3b616 1300
9320b5c4
NK		 1301
1302/* Misc functions TODO: Cleanup */
c6e387a2 1303int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
a25d1e4c
PR		 1304int ath5k_hw_get_capability(struct ath5k_hw *ah,
1305 enum ath5k_capability_type cap_type, u32 capability,
1306 u32 *result);
1307int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1308int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
fa1c114f 1309
9320b5c4 1310
fa1c114f 1311/* Initial register settings functions */
a25d1e4c 1312int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
c6e387a2 1313
9320b5c4
NK		 1314
1315/* PHY functions */
1316/* Misc PHY functions */
1317u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1318int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1319/* Gain_F optimization */
a25d1e4c
PR		 1320enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1321int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
fa1c114f 1322/* PHY/RF channel functions */
a25d1e4c 1323bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
fa1c114f 1324/* PHY calibration */
e5e2647f 1325void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
a25d1e4c
PR		 1326int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1327 struct ieee80211_channel *channel);
9e04a7eb 1328void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
57e6c56d
NK		 1329/* Spur mitigation */
1330bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
a25d1e4c 1331 struct ieee80211_channel *channel);
2bed03eb 1332/* Antenna control */
a25d1e4c 1333void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
0ca74027 1334void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
fa1c114f 1335/* TX power setup */
a25d1e4c 1336int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
9320b5c4
NK		 1337/* Init function */
1338int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
0207c0c5 1339 u8 mode, bool fast);
fa1c114f 1340
c6e387a2
NK		 1341/*
1342 * Functions used internaly
1343 */
1344
e5aa8474
LR		 1345static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1346{
1347 return &ah->common;
1348}
1349
1350static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1351{
1352 return &(ath5k_hw_common(ah)->regulatory);
1353}
1354
a0b907ee
FF		 1355#ifdef CONFIG_ATHEROS_AR231X
1356#define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000)
1357
1358static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
1359{
1360 /* On AR2315 and AR2317 the PCI clock domain registers
1361 * are outside of the WMAC register space */
1362 if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
1363 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
1364 return AR5K_AR2315_PCI_BASE + reg;
1365
1366 return ah->ah_iobase + reg;
1367}
1368
1369static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1370{
1371 return __raw_readl(ath5k_ahb_reg(ah, reg));
1372}
1373
1374static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1375{
1376 __raw_writel(val, ath5k_ahb_reg(ah, reg));
1377}
1378
1379#else
1380
fa1c114f
JS		 1381static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1382{
1383 return ioread32(ah->ah_iobase + reg);
1384}
1385
1386static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1387{
1388 iowrite32(val, ah->ah_iobase + reg);
1389}
1390
a0b907ee
FF		 1391#endif
1392
1393static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
1394{
1395 return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
1396}
1397
132b1c3e
FF		 1398static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
1399{
1400 common->bus_ops->read_cachesize(common, csz);
1401}
1402
4aa5d783
FF		 1403static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
1404{
1405 struct ath_common *common = ath5k_hw_common(ah);
1406 return common->bus_ops->eeprom_read(common, off, data);
1407}
1408
c6e387a2
NK		 1409static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1410{
1411 u32 retval = 0, bit, i;
1412
1413 for (i = 0; i < bits; i++) {
1414 bit = (val >> i) & 1;
1415 retval = (retval << 1) | bit;
1416 }
1417
1418 return retval;
1419}
1420
fa1c114f 1421#endif
Linux kernel - Deliverables
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