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ath5k: Rename ath5k_copy_channels
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
18cb6e32
JL		 64int ath5k_modparam_nohwcrypt;
65module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 66MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 67
42639fcd 68static int modparam_all_channels;
46802a4f 69module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 70MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
fa1c114f
JS		 72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 78
132b1c3e 79static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 80static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
81 bool skip_pcu);
cd2c5486
BR		 82int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
83void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f 84
fa1c114f 85/* Known SREVs */
2c91108c 86static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 87#ifdef CONFIG_ATHEROS_AR231X
88 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
89 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
90 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
91 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
92 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
93 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
94 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
95#else
1bef016a
NK		 96 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
97 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
98 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
99 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
100 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
101 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
102 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
103 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
104 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
105 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
106 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
107 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
108 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
109 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
110 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
111 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
112 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
113 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 114#endif
1bef016a 115 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 116 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
117 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 118 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 119 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
120 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
121 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 122 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 123 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
124 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 125 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
126 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
127 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 128 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 129 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 130#ifdef CONFIG_ATHEROS_AR231X
131 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
132 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
133#endif
fa1c114f
JS		 134 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
135};
136
2c91108c 137static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 138 { .bitrate = 10,
139 .hw_value = ATH5K_RATE_CODE_1M, },
140 { .bitrate = 20,
141 .hw_value = ATH5K_RATE_CODE_2M,
142 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
143 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
144 { .bitrate = 55,
145 .hw_value = ATH5K_RATE_CODE_5_5M,
146 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
147 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
148 { .bitrate = 110,
149 .hw_value = ATH5K_RATE_CODE_11M,
150 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 60,
153 .hw_value = ATH5K_RATE_CODE_6M,
154 .flags = 0 },
155 { .bitrate = 90,
156 .hw_value = ATH5K_RATE_CODE_9M,
157 .flags = 0 },
158 { .bitrate = 120,
159 .hw_value = ATH5K_RATE_CODE_12M,
160 .flags = 0 },
161 { .bitrate = 180,
162 .hw_value = ATH5K_RATE_CODE_18M,
163 .flags = 0 },
164 { .bitrate = 240,
165 .hw_value = ATH5K_RATE_CODE_24M,
166 .flags = 0 },
167 { .bitrate = 360,
168 .hw_value = ATH5K_RATE_CODE_36M,
169 .flags = 0 },
170 { .bitrate = 480,
171 .hw_value = ATH5K_RATE_CODE_48M,
172 .flags = 0 },
173 { .bitrate = 540,
174 .hw_value = ATH5K_RATE_CODE_54M,
175 .flags = 0 },
176 /* XR missing */
177};
178
fa1c114f
JS		 179static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
180{
181 u64 tsf = ath5k_hw_get_tsf64(ah);
182
183 if ((tsf & 0x7fff) < rstamp)
184 tsf -= 0x8000;
185
186 return (tsf & ~0x7fff) | rstamp;
187}
188
e5b046d8 189const char *
fa1c114f
JS		 190ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
191{
192 const char *name = "xxxxx";
193 unsigned int i;
194
195 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
196 if (srev_names[i].sr_type != type)
197 continue;
75d0edb8
NK		 198
199 if ((val & 0xf0) == srev_names[i].sr_val)
200 name = srev_names[i].sr_name;
201
202 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 203 name = srev_names[i].sr_name;
204 break;
205 }
206 }
207
208 return name;
209}
e5aa8474
LR		 210static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
211{
212 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
213 return ath5k_hw_reg_read(ah, reg_offset);
214}
215
216static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
217{
218 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
219 ath5k_hw_reg_write(ah, val, reg_offset);
220}
221
222static const struct ath_ops ath5k_common_ops = {
223 .read = ath5k_ioread32,
224 .write = ath5k_iowrite32,
225};
fa1c114f 226
8a63facc
BC		 227/***********************\
228* Driver Initialization *
229\***********************/
230
231static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 232{
8a63facc
BC		 233 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
234 struct ath5k_softc *sc = hw->priv;
235 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 236
8a63facc
BC		 237 return ath_reg_notifier_apply(wiphy, request, regulatory);
238}
6ccf15a1 239
8a63facc
BC		 240/********************\
241* Channel/mode setup *
242\********************/
fa1c114f 243
8a63facc
BC		 244/*
245 * Returns true for the channel numbers used without all_channels modparam.
246 */
247static bool ath5k_is_standard_channel(short chan)
248{
249 return ((chan <= 14) ||
250 /* UNII 1,2 */
251 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
252 /* midband */
253 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
254 /* UNII-3 */
255 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
256}
fa1c114f 257
8a63facc 258static unsigned int
08105690 259ath5k_setup_channels(struct ath5k_hw *ah,
8a63facc
BC		 260 struct ieee80211_channel *channels,
261 unsigned int mode,
262 unsigned int max)
263{
264 unsigned int i, count, size, chfreq, freq, ch;
90c02d72 265 enum ieee80211_band band;
fa1c114f 266
8a63facc
BC		 267 if (!test_bit(mode, ah->ah_modes))
268 return 0;
fa1c114f 269
8a63facc
BC		 270 switch (mode) {
271 case AR5K_MODE_11A:
8a63facc
BC		 272 /* 1..220, but 2GHz frequencies are filtered by check_channel */
273 size = 220 ;
274 chfreq = CHANNEL_5GHZ;
90c02d72 275 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 276 break;
277 case AR5K_MODE_11B:
278 case AR5K_MODE_11G:
8a63facc
BC		 279 size = 26;
280 chfreq = CHANNEL_2GHZ;
90c02d72 281 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 282 break;
283 default:
284 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
285 return 0;
fa1c114f
JS		 286 }
287
8a63facc
BC		 288 for (i = 0, count = 0; i < size && max > 0; i++) {
289 ch = i + 1 ;
90c02d72
BR		 290 freq = ieee80211_channel_to_frequency(ch, band);
291
292 if (freq == 0) /* mapping failed - not a standard channel */
293 continue;
fa1c114f 294
8a63facc
BC		 295 /* Check if channel is supported by the chipset */
296 if (!ath5k_channel_ok(ah, freq, chfreq))
297 continue;
f59ac048 298
8a63facc
BC		 299 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
300 continue;
f59ac048 301
8a63facc
BC		 302 /* Write channel info and increment counter */
303 channels[count].center_freq = freq;
90c02d72 304 channels[count].band = band;
8a63facc
BC		 305 switch (mode) {
306 case AR5K_MODE_11A:
307 case AR5K_MODE_11G:
308 channels[count].hw_value = chfreq | CHANNEL_OFDM;
309 break;
8a63facc
BC		 310 case AR5K_MODE_11B:
311 channels[count].hw_value = CHANNEL_B;
312 }
fa1c114f 313
8a63facc
BC		 314 count++;
315 max--;
316 }
fa1c114f 317
8a63facc
BC		 318 return count;
319}
fa1c114f 320
8a63facc
BC		 321static void
322ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
323{
324 u8 i;
fa1c114f 325
8a63facc
BC		 326 for (i = 0; i < AR5K_MAX_RATES; i++)
327 sc->rate_idx[b->band][i] = -1;
fa1c114f 328
8a63facc
BC		 329 for (i = 0; i < b->n_bitrates; i++) {
330 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
331 if (b->bitrates[i].hw_value_short)
332 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 333 }
8a63facc 334}
fa1c114f 335
8a63facc
BC		 336static int
337ath5k_setup_bands(struct ieee80211_hw *hw)
338{
339 struct ath5k_softc *sc = hw->priv;
340 struct ath5k_hw *ah = sc->ah;
341 struct ieee80211_supported_band *sband;
342 int max_c, count_c = 0;
343 int i;
fa1c114f 344
8a63facc
BC		 345 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
346 max_c = ARRAY_SIZE(sc->channels);
db719718 347
8a63facc
BC		 348 /* 2GHz band */
349 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
350 sband->band = IEEE80211_BAND_2GHZ;
351 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 352
8a63facc
BC		 353 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
354 /* G mode */
355 memcpy(sband->bitrates, &ath5k_rates[0],
356 sizeof(struct ieee80211_rate) * 12);
357 sband->n_bitrates = 12;
2f7fe870 358
8a63facc 359 sband->channels = sc->channels;
08105690 360 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 361 AR5K_MODE_11G, max_c);
fa1c114f 362
8a63facc
BC		 363 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
364 count_c = sband->n_channels;
365 max_c -= count_c;
366 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
367 /* B mode */
368 memcpy(sband->bitrates, &ath5k_rates[0],
369 sizeof(struct ieee80211_rate) * 4);
370 sband->n_bitrates = 4;
fa1c114f 371
8a63facc
BC		 372 /* 5211 only supports B rates and uses 4bit rate codes
373 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
374 * fix them up here:
375 */
376 if (ah->ah_version == AR5K_AR5211) {
377 for (i = 0; i < 4; i++) {
378 sband->bitrates[i].hw_value =
379 sband->bitrates[i].hw_value & 0xF;
380 sband->bitrates[i].hw_value_short =
381 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 382 }
383 }
fa1c114f 384
8a63facc 385 sband->channels = sc->channels;
08105690 386 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 387 AR5K_MODE_11B, max_c);
fa1c114f 388
8a63facc
BC		 389 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
390 count_c = sband->n_channels;
391 max_c -= count_c;
392 }
393 ath5k_setup_rate_idx(sc, sband);
fa1c114f 394
8a63facc
BC		 395 /* 5GHz band, A mode */
396 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
397 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
398 sband->band = IEEE80211_BAND_5GHZ;
399 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 400
8a63facc
BC		 401 memcpy(sband->bitrates, &ath5k_rates[4],
402 sizeof(struct ieee80211_rate) * 8);
403 sband->n_bitrates = 8;
fa1c114f 404
8a63facc 405 sband->channels = &sc->channels[count_c];
08105690 406 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 407 AR5K_MODE_11A, max_c);
fa1c114f 408
8a63facc
BC		 409 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
410 }
411 ath5k_setup_rate_idx(sc, sband);
412
413 ath5k_debug_dump_bands(sc);
fa1c114f 414
fa1c114f
JS		 415 return 0;
416}
417
8a63facc
BC		 418/*
419 * Set/change channels. We always reset the chip.
420 * To accomplish this we must first cleanup any pending DMA,
421 * then restart stuff after a la ath5k_init.
422 *
423 * Called with sc->lock.
424 */
cd2c5486 425int
8a63facc
BC		 426ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
427{
428 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
429 "channel set, resetting (%u -> %u MHz)\n",
430 sc->curchan->center_freq, chan->center_freq);
431
8451d22d 432 /*
8a63facc
BC		 433 * To switch channels clear any pending DMA operations;
434 * wait long enough for the RX fifo to drain, reset the
435 * hardware at the new frequency, and then re-enable
436 * the relevant bits of the h/w.
8451d22d 437 */
8aec7af9 438 return ath5k_reset(sc, chan, true);
fa1c114f 439}
fa1c114f 440
8a63facc
BC		 441static void
442ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 443{
8a63facc 444 sc->curmode = mode;
f769c36b 445
8a63facc
BC		 446 if (mode == AR5K_MODE_11A) {
447 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
448 } else {
449 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
450 }
f769c36b
BC		 451}
452
b1ae1edf
BG		 453struct ath_vif_iter_data {
454 const u8 *hw_macaddr;
455 u8 mask[ETH_ALEN];
456 u8 active_mac[ETH_ALEN]; /* first active MAC */
457 bool need_set_hw_addr;
458 bool found_active;
459 bool any_assoc;
62c58fb4 460 enum nl80211_iftype opmode;
b1ae1edf
BG		 461};
462
463static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
464{
465 struct ath_vif_iter_data *iter_data = data;
466 int i;
62c58fb4 467 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 468
469 if (iter_data->hw_macaddr)
470 for (i = 0; i < ETH_ALEN; i++)
471 iter_data->mask[i] &=
472 ~(iter_data->hw_macaddr[i] ^ mac[i]);
473
474 if (!iter_data->found_active) {
475 iter_data->found_active = true;
476 memcpy(iter_data->active_mac, mac, ETH_ALEN);
477 }
478
479 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
480 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
481 iter_data->need_set_hw_addr = false;
482
483 if (!iter_data->any_assoc) {
b1ae1edf
BG		 484 if (avf->assoc)
485 iter_data->any_assoc = true;
486 }
62c58fb4
BG		 487
488 /* Calculate combined mode - when APs are active, operate in AP mode.
489 * Otherwise use the mode of the new interface. This can currently
490 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 491 * interfaces is allowed.
62c58fb4
BG		 492 */
493 if (avf->opmode == NL80211_IFTYPE_AP)
494 iter_data->opmode = NL80211_IFTYPE_AP;
495 else
496 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
497 iter_data->opmode = avf->opmode;
b1ae1edf
BG		 498}
499
cd2c5486
BR		 500void
501ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
502 struct ieee80211_vif *vif)
b1ae1edf
BG		 503{
504 struct ath_common *common = ath5k_hw_common(sc->ah);
505 struct ath_vif_iter_data iter_data;
506
507 /*
508 * Use the hardware MAC address as reference, the hardware uses it
509 * together with the BSSID mask when matching addresses.
510 */
511 iter_data.hw_macaddr = common->macaddr;
512 memset(&iter_data.mask, 0xff, ETH_ALEN);
513 iter_data.found_active = false;
514 iter_data.need_set_hw_addr = true;
62c58fb4 515 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
b1ae1edf
BG		 516
517 if (vif)
518 ath_vif_iter(&iter_data, vif->addr, vif);
519
520 /* Get list of all active MAC addresses */
521 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
522 &iter_data);
523 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
524
62c58fb4
BG		 525 sc->opmode = iter_data.opmode;
526 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
527 /* Nothing active, default to station mode */
528 sc->opmode = NL80211_IFTYPE_STATION;
529
7afbb2f0
BG		 530 ath5k_hw_set_opmode(sc->ah, sc->opmode);
531 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
532 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 533
b1ae1edf
BG		 534 if (iter_data.need_set_hw_addr && iter_data.found_active)
535 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
536
62c58fb4
BG		 537 if (ath5k_hw_hasbssidmask(sc->ah))
538 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf
BG		 539}
540
cd2c5486 541void
b1ae1edf 542ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
fa1c114f 543{
fa1c114f 544 struct ath5k_hw *ah = sc->ah;
8a63facc 545 u32 rfilt;
fa1c114f 546
8a63facc
BC		 547 /* configure rx filter */
548 rfilt = sc->filter_flags;
549 ath5k_hw_set_rx_filter(ah, rfilt);
8a63facc 550 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
62c58fb4
BG		 551
552 ath5k_update_bssid_mask_and_opmode(sc, vif);
8a63facc 553}
fa1c114f 554
8a63facc
BC		 555static inline int
556ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
557{
558 int rix;
fa1c114f 559
8a63facc
BC		 560 /* return base rate on errors */
561 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
562 "hw_rix out of bounds: %x\n", hw_rix))
563 return 0;
564
565 rix = sc->rate_idx[sc->curband->band][hw_rix];
566 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
567 rix = 0;
568
569 return rix;
570}
571
572/***************\
573* Buffers setup *
574\***************/
575
576static
577struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
578{
579 struct ath_common *common = ath5k_hw_common(sc->ah);
580 struct sk_buff *skb;
fa1c114f
JS		 581
582 /*
8a63facc
BC		 583 * Allocate buffer with headroom_needed space for the
584 * fake physical layer header at the start.
fa1c114f 585 */
8a63facc
BC		 586 skb = ath_rxbuf_alloc(common,
587 common->rx_bufsize,
588 GFP_ATOMIC);
fa1c114f 589
8a63facc
BC		 590 if (!skb) {
591 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
592 common->rx_bufsize);
593 return NULL;
fa1c114f
JS		 594 }
595
aeae4ac9 596 *skb_addr = dma_map_single(sc->dev,
8a63facc 597 skb->data, common->rx_bufsize,
aeae4ac9
FF		 598 DMA_FROM_DEVICE);
599
600 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 601 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
602 dev_kfree_skb(skb);
603 return NULL;
0e149cf5 604 }
8a63facc
BC		 605 return skb;
606}
0e149cf5 607
8a63facc
BC		 608static int
609ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
610{
611 struct ath5k_hw *ah = sc->ah;
612 struct sk_buff *skb = bf->skb;
613 struct ath5k_desc *ds;
614 int ret;
fa1c114f 615
8a63facc
BC		 616 if (!skb) {
617 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
618 if (!skb)
619 return -ENOMEM;
620 bf->skb = skb;
f769c36b
BC		 621 }
622
8a63facc
BC		 623 /*
624 * Setup descriptors. For receive we always terminate
625 * the descriptor list with a self-linked entry so we'll
626 * not get overrun under high load (as can happen with a
627 * 5212 when ANI processing enables PHY error frames).
628 *
629 * To ensure the last descriptor is self-linked we create
630 * each descriptor as self-linked and add it to the end. As
631 * each additional descriptor is added the previous self-linked
632 * entry is "fixed" naturally. This should be safe even
633 * if DMA is happening. When processing RX interrupts we
634 * never remove/process the last, self-linked, entry on the
635 * descriptor list. This ensures the hardware always has
636 * someplace to write a new frame.
637 */
638 ds = bf->desc;
639 ds->ds_link = bf->daddr; /* link to self */
640 ds->ds_data = bf->skbaddr;
641 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 642 if (ret) {
8a63facc
BC		 643 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
644 return ret;
fa1c114f
JS		 645 }
646
8a63facc
BC		 647 if (sc->rxlink != NULL)
648 *sc->rxlink = bf->daddr;
649 sc->rxlink = &ds->ds_link;
fa1c114f 650 return 0;
fa1c114f
JS		 651}
652
8a63facc 653static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 654{
8a63facc
BC		 655 struct ieee80211_hdr *hdr;
656 enum ath5k_pkt_type htype;
657 __le16 fc;
fa1c114f 658
8a63facc
BC		 659 hdr = (struct ieee80211_hdr *)skb->data;
660 fc = hdr->frame_control;
fa1c114f 661
8a63facc
BC		 662 if (ieee80211_is_beacon(fc))
663 htype = AR5K_PKT_TYPE_BEACON;
664 else if (ieee80211_is_probe_resp(fc))
665 htype = AR5K_PKT_TYPE_PROBE_RESP;
666 else if (ieee80211_is_atim(fc))
667 htype = AR5K_PKT_TYPE_ATIM;
668 else if (ieee80211_is_pspoll(fc))
669 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 670 else
8a63facc 671 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 672
8a63facc 673 return htype;
42639fcd
BC		 674}
675
8a63facc
BC		 676static int
677ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
678 struct ath5k_txq *txq, int padsize)
fa1c114f 679{
8a63facc
BC		 680 struct ath5k_hw *ah = sc->ah;
681 struct ath5k_desc *ds = bf->desc;
682 struct sk_buff *skb = bf->skb;
683 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
684 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
685 struct ieee80211_rate *rate;
686 unsigned int mrr_rate[3], mrr_tries[3];
687 int i, ret;
688 u16 hw_rate;
689 u16 cts_rate = 0;
690 u16 duration = 0;
691 u8 rc_flags;
fa1c114f 692
8a63facc 693 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 694
8a63facc 695 /* XXX endianness */
aeae4ac9
FF		 696 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
697 DMA_TO_DEVICE);
fa1c114f 698
8a63facc 699 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 700 if (!rate) {
701 ret = -EINVAL;
702 goto err_unmap;
703 }
fa1c114f 704
8a63facc
BC		 705 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
706 flags |= AR5K_TXDESC_NOACK;
fa1c114f 707
8a63facc
BC		 708 rc_flags = info->control.rates[0].flags;
709 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
710 rate->hw_value_short : rate->hw_value;
42639fcd 711
8a63facc
BC		 712 pktlen = skb->len;
713
714 /* FIXME: If we are in g mode and rate is a CCK rate
715 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
716 * from tx power (value is in dB units already) */
717 if (info->control.hw_key) {
718 keyidx = info->control.hw_key->hw_key_idx;
719 pktlen += info->control.hw_key->icv_len;
720 }
721 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
722 flags |= AR5K_TXDESC_RTSENA;
723 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
724 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 725 info->control.vif, pktlen, info));
8a63facc
BC		 726 }
727 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
728 flags |= AR5K_TXDESC_CTSENA;
729 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
730 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 731 info->control.vif, pktlen, info));
8a63facc
BC		 732 }
733 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
734 ieee80211_get_hdrlen_from_skb(skb), padsize,
735 get_hw_packet_type(skb),
736 (sc->power_level * 2),
737 hw_rate,
738 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
739 cts_rate, duration);
740 if (ret)
741 goto err_unmap;
742
743 memset(mrr_rate, 0, sizeof(mrr_rate));
744 memset(mrr_tries, 0, sizeof(mrr_tries));
745 for (i = 0; i < 3; i++) {
746 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
747 if (!rate)
400ec45a 748 break;
fa1c114f 749
8a63facc
BC		 750 mrr_rate[i] = rate->hw_value;
751 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 752 }
753
8a63facc
BC		 754 ath5k_hw_setup_mrr_tx_desc(ah, ds,
755 mrr_rate[0], mrr_tries[0],
756 mrr_rate[1], mrr_tries[1],
757 mrr_rate[2], mrr_tries[2]);
fa1c114f 758
8a63facc
BC		 759 ds->ds_link = 0;
760 ds->ds_data = bf->skbaddr;
63266a65 761
8a63facc
BC		 762 spin_lock_bh(&txq->lock);
763 list_add_tail(&bf->list, &txq->q);
925e0b06 764 txq->txq_len++;
8a63facc
BC		 765 if (txq->link == NULL) /* is this first packet? */
766 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
767 else /* no, so only link it */
768 *txq->link = bf->daddr;
63266a65 769
8a63facc
BC		 770 txq->link = &ds->ds_link;
771 ath5k_hw_start_tx_dma(ah, txq->qnum);
772 mmiowb();
773 spin_unlock_bh(&txq->lock);
774
775 return 0;
776err_unmap:
aeae4ac9 777 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 778 return ret;
63266a65
BR		 779}
780
8a63facc
BC		 781/*******************\
782* Descriptors setup *
783\*******************/
784
d8ee398d 785static int
aeae4ac9 786ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 787{
8a63facc
BC		 788 struct ath5k_desc *ds;
789 struct ath5k_buf *bf;
790 dma_addr_t da;
791 unsigned int i;
792 int ret;
d8ee398d 793
8a63facc
BC		 794 /* allocate descriptors */
795 sc->desc_len = sizeof(struct ath5k_desc) *
796 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 797
798 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
799 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 800 if (sc->desc == NULL) {
801 ATH5K_ERR(sc, "can't allocate descriptors\n");
802 ret = -ENOMEM;
803 goto err;
804 }
805 ds = sc->desc;
806 da = sc->desc_daddr;
807 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
808 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 809
8a63facc
BC		 810 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
811 sizeof(struct ath5k_buf), GFP_KERNEL);
812 if (bf == NULL) {
813 ATH5K_ERR(sc, "can't allocate bufptr\n");
814 ret = -ENOMEM;
815 goto err_free;
816 }
817 sc->bufptr = bf;
fa1c114f 818
8a63facc
BC		 819 INIT_LIST_HEAD(&sc->rxbuf);
820 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
821 bf->desc = ds;
822 bf->daddr = da;
823 list_add_tail(&bf->list, &sc->rxbuf);
824 }
d8ee398d 825
8a63facc
BC		 826 INIT_LIST_HEAD(&sc->txbuf);
827 sc->txbuf_len = ATH_TXBUF;
828 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
829 da += sizeof(*ds)) {
830 bf->desc = ds;
831 bf->daddr = da;
832 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 833 }
834
b1ae1edf
BG		 835 /* beacon buffers */
836 INIT_LIST_HEAD(&sc->bcbuf);
837 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
838 bf->desc = ds;
839 bf->daddr = da;
840 list_add_tail(&bf->list, &sc->bcbuf);
841 }
fa1c114f 842
8a63facc
BC		 843 return 0;
844err_free:
aeae4ac9 845 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 846err:
847 sc->desc = NULL;
848 return ret;
849}
fa1c114f 850
cd2c5486
BR		 851void
852ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
853{
854 BUG_ON(!bf);
855 if (!bf->skb)
856 return;
857 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
858 DMA_TO_DEVICE);
859 dev_kfree_skb_any(bf->skb);
860 bf->skb = NULL;
861 bf->skbaddr = 0;
862 bf->desc->ds_data = 0;
863}
864
865void
866ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
867{
868 struct ath5k_hw *ah = sc->ah;
869 struct ath_common *common = ath5k_hw_common(ah);
870
871 BUG_ON(!bf);
872 if (!bf->skb)
873 return;
874 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
875 DMA_FROM_DEVICE);
876 dev_kfree_skb_any(bf->skb);
877 bf->skb = NULL;
878 bf->skbaddr = 0;
879 bf->desc->ds_data = 0;
880}
881
8a63facc 882static void
aeae4ac9 883ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 884{
885 struct ath5k_buf *bf;
d8ee398d 886
8a63facc
BC		 887 list_for_each_entry(bf, &sc->txbuf, list)
888 ath5k_txbuf_free_skb(sc, bf);
889 list_for_each_entry(bf, &sc->rxbuf, list)
890 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 891 list_for_each_entry(bf, &sc->bcbuf, list)
892 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 893
8a63facc 894 /* Free memory associated with all descriptors */
aeae4ac9 895 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 896 sc->desc = NULL;
897 sc->desc_daddr = 0;
d8ee398d 898
8a63facc
BC		 899 kfree(sc->bufptr);
900 sc->bufptr = NULL;
fa1c114f
JS		 901}
902
8a63facc
BC		 903
904/**************\
905* Queues setup *
906\**************/
907
908static struct ath5k_txq *
909ath5k_txq_setup(struct ath5k_softc *sc,
910 int qtype, int subtype)
fa1c114f 911{
8a63facc
BC		 912 struct ath5k_hw *ah = sc->ah;
913 struct ath5k_txq *txq;
914 struct ath5k_txq_info qi = {
915 .tqi_subtype = subtype,
de8af455
BR		 916 /* XXX: default values not correct for B and XR channels,
917 * but who cares? */
918 .tqi_aifs = AR5K_TUNE_AIFS,
919 .tqi_cw_min = AR5K_TUNE_CWMIN,
920 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 921 };
922 int qnum;
d8ee398d 923
e30eb4ab 924 /*
8a63facc
BC		 925 * Enable interrupts only for EOL and DESC conditions.
926 * We mark tx descriptors to receive a DESC interrupt
927 * when a tx queue gets deep; otherwise we wait for the
928 * EOL to reap descriptors. Note that this is done to
929 * reduce interrupt load and this only defers reaping
930 * descriptors, never transmitting frames. Aside from
931 * reducing interrupts this also permits more concurrency.
932 * The only potential downside is if the tx queue backs
933 * up in which case the top half of the kernel may backup
934 * due to a lack of tx descriptors.
e30eb4ab 935 */
8a63facc
BC		 936 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
937 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
938 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
939 if (qnum < 0) {
940 /*
941 * NB: don't print a message, this happens
942 * normally on parts with too few tx queues
943 */
944 return ERR_PTR(qnum);
945 }
946 if (qnum >= ARRAY_SIZE(sc->txqs)) {
947 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
948 qnum, ARRAY_SIZE(sc->txqs));
949 ath5k_hw_release_tx_queue(ah, qnum);
950 return ERR_PTR(-EINVAL);
951 }
952 txq = &sc->txqs[qnum];
953 if (!txq->setup) {
954 txq->qnum = qnum;
955 txq->link = NULL;
956 INIT_LIST_HEAD(&txq->q);
957 spin_lock_init(&txq->lock);
958 txq->setup = true;
925e0b06 959 txq->txq_len = 0;
4edd761f 960 txq->txq_poll_mark = false;
923e5b3d 961 txq->txq_stuck = 0;
8a63facc
BC		 962 }
963 return &sc->txqs[qnum];
fa1c114f
JS		 964}
965
8a63facc
BC		 966static int
967ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 968{
8a63facc 969 struct ath5k_txq_info qi = {
de8af455
BR		 970 /* XXX: default values not correct for B and XR channels,
971 * but who cares? */
972 .tqi_aifs = AR5K_TUNE_AIFS,
973 .tqi_cw_min = AR5K_TUNE_CWMIN,
974 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 975 /* NB: for dynamic turbo, don't enable any other interrupts */
976 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
977 };
d8ee398d 978
8a63facc 979 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 980}
981
8a63facc
BC		 982static int
983ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 984{
985 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 986 struct ath5k_txq_info qi;
987 int ret;
fa1c114f 988
8a63facc
BC		 989 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
990 if (ret)
991 goto err;
fa1c114f 992
8a63facc
BC		 993 if (sc->opmode == NL80211_IFTYPE_AP ||
994 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
995 /*
996 * Always burst out beacon and CAB traffic
997 * (aifs = cwmin = cwmax = 0)
998 */
999 qi.tqi_aifs = 0;
1000 qi.tqi_cw_min = 0;
1001 qi.tqi_cw_max = 0;
1002 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1003 /*
1004 * Adhoc mode; backoff between 0 and (2 * cw_min).
1005 */
1006 qi.tqi_aifs = 0;
1007 qi.tqi_cw_min = 0;
de8af455 1008 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 1009 }
fa1c114f 1010
8a63facc
BC		 1011 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1012 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1013 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1014
8a63facc
BC		 1015 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1016 if (ret) {
1017 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1018 "hardware queue!\n", __func__);
1019 goto err;
1020 }
1021 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1022 if (ret)
1023 goto err;
b7266047 1024
8a63facc
BC		 1025 /* reconfigure cabq with ready time to 80% of beacon_interval */
1026 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1027 if (ret)
1028 goto err;
b7266047 1029
8a63facc
BC		 1030 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1031 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1032 if (ret)
1033 goto err;
b7266047 1034
8a63facc
BC		 1035 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1036err:
1037 return ret;
d8ee398d
LR		 1038}
1039
80dac9ee
NK		 1040/**
1041 * ath5k_drain_tx_buffs - Empty tx buffers
1042 *
1043 * @sc The &struct ath5k_softc
1044 *
1045 * Empty tx buffers from all queues in preparation
1046 * of a reset or during shutdown.
1047 *
1048 * NB: this assumes output has been stopped and
1049 * we do not need to block ath5k_tx_tasklet
1050 */
8a63facc 1051static void
80dac9ee 1052ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1053{
80dac9ee 1054 struct ath5k_txq *txq;
8a63facc 1055 struct ath5k_buf *bf, *bf0;
80dac9ee 1056 int i;
b6ea0356 1057
80dac9ee
NK		 1058 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1059 if (sc->txqs[i].setup) {
1060 txq = &sc->txqs[i];
1061 spin_lock_bh(&txq->lock);
1062 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1063 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1064
80dac9ee 1065 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1066
80dac9ee
NK		 1067 spin_lock_bh(&sc->txbuflock);
1068 list_move_tail(&bf->list, &sc->txbuf);
1069 sc->txbuf_len++;
1070 txq->txq_len--;
1071 spin_unlock_bh(&sc->txbuflock);
8a63facc 1072 }
80dac9ee
NK		 1073 txq->link = NULL;
1074 txq->txq_poll_mark = false;
1075 spin_unlock_bh(&txq->lock);
1076 }
0452d4a5 1077 }
fa1c114f
JS		 1078}
1079
8a63facc
BC		 1080static void
1081ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1082{
8a63facc
BC		 1083 struct ath5k_txq *txq = sc->txqs;
1084 unsigned int i;
2ac2927a 1085
8a63facc
BC		 1086 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1087 if (txq->setup) {
1088 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1089 txq->setup = false;
1090 }
1091}
2ac2927a 1092
2ac2927a 1093
8a63facc
BC		 1094/*************\
1095* RX Handling *
1096\*************/
2ac2927a 1097
8a63facc
BC		 1098/*
1099 * Enable the receive h/w following a reset.
1100 */
fa1c114f 1101static int
8a63facc 1102ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1103{
1104 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1105 struct ath_common *common = ath5k_hw_common(ah);
1106 struct ath5k_buf *bf;
1107 int ret;
fa1c114f 1108
8a63facc 1109 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1110
8a63facc
BC		 1111 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1112 common->cachelsz, common->rx_bufsize);
2f7fe870 1113
8a63facc
BC		 1114 spin_lock_bh(&sc->rxbuflock);
1115 sc->rxlink = NULL;
1116 list_for_each_entry(bf, &sc->rxbuf, list) {
1117 ret = ath5k_rxbuf_setup(sc, bf);
1118 if (ret != 0) {
1119 spin_unlock_bh(&sc->rxbuflock);
1120 goto err;
1121 }
2f7fe870 1122 }
8a63facc
BC		 1123 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1124 ath5k_hw_set_rxdp(ah, bf->daddr);
1125 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1126
8a63facc 1127 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
b1ae1edf 1128 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
8a63facc 1129 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1130
1131 return 0;
8a63facc 1132err:
fa1c114f
JS		 1133 return ret;
1134}
1135
8a63facc 1136/*
80dac9ee
NK		 1137 * Disable the receive logic on PCU (DRU)
1138 * In preparation for a shutdown.
1139 *
1140 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1141 * does.
8a63facc
BC		 1142 */
1143static void
1144ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1145{
8a63facc 1146 struct ath5k_hw *ah = sc->ah;
fa1c114f 1147
8a63facc 1148 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1149 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1150
8a63facc
BC		 1151 ath5k_debug_printrxbuffs(sc, ah);
1152}
fa1c114f 1153
8a63facc
BC		 1154static unsigned int
1155ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1156 struct ath5k_rx_status *rs)
1157{
1158 struct ath5k_hw *ah = sc->ah;
1159 struct ath_common *common = ath5k_hw_common(ah);
1160 struct ieee80211_hdr *hdr = (void *)skb->data;
1161 unsigned int keyix, hlen;
fa1c114f 1162
8a63facc
BC		 1163 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1164 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1165 return RX_FLAG_DECRYPTED;
fa1c114f 1166
8a63facc
BC		 1167 /* Apparently when a default key is used to decrypt the packet
1168 the hw does not set the index used to decrypt. In such cases
1169 get the index from the packet. */
1170 hlen = ieee80211_hdrlen(hdr->frame_control);
1171 if (ieee80211_has_protected(hdr->frame_control) &&
1172 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1173 skb->len >= hlen + 4) {
1174 keyix = skb->data[hlen + 3] >> 6;
1175
1176 if (test_bit(keyix, common->keymap))
1177 return RX_FLAG_DECRYPTED;
1178 }
fa1c114f
JS		 1179
1180 return 0;
fa1c114f
JS		 1181}
1182
8a63facc 1183
fa1c114f 1184static void
8a63facc
BC		 1185ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1186 struct ieee80211_rx_status *rxs)
fa1c114f 1187{
8a63facc
BC		 1188 struct ath_common *common = ath5k_hw_common(sc->ah);
1189 u64 tsf, bc_tstamp;
1190 u32 hw_tu;
1191 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1192
8a63facc
BC		 1193 if (ieee80211_is_beacon(mgmt->frame_control) &&
1194 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1195 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1196 /*
1197 * Received an IBSS beacon with the same BSSID. Hardware *must*
1198 * have updated the local TSF. We have to work around various
1199 * hardware bugs, though...
1200 */
1201 tsf = ath5k_hw_get_tsf64(sc->ah);
1202 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1203 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1204
8a63facc
BC		 1205 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1206 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1207 (unsigned long long)bc_tstamp,
1208 (unsigned long long)rxs->mactime,
1209 (unsigned long long)(rxs->mactime - bc_tstamp),
1210 (unsigned long long)tsf);
fa1c114f 1211
8a63facc
BC		 1212 /*
1213 * Sometimes the HW will give us a wrong tstamp in the rx
1214 * status, causing the timestamp extension to go wrong.
1215 * (This seems to happen especially with beacon frames bigger
1216 * than 78 byte (incl. FCS))
1217 * But we know that the receive timestamp must be later than the
1218 * timestamp of the beacon since HW must have synced to that.
1219 *
1220 * NOTE: here we assume mactime to be after the frame was
1221 * received, not like mac80211 which defines it at the start.
1222 */
1223 if (bc_tstamp > rxs->mactime) {
1224 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1225 "fixing mactime from %llx to %llx\n",
1226 (unsigned long long)rxs->mactime,
1227 (unsigned long long)tsf);
1228 rxs->mactime = tsf;
1229 }
fa1c114f 1230
8a63facc
BC		 1231 /*
1232 * Local TSF might have moved higher than our beacon timers,
1233 * in that case we have to update them to continue sending
1234 * beacons. This also takes care of synchronizing beacon sending
1235 * times with other stations.
1236 */
1237 if (hw_tu >= sc->nexttbtt)
1238 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1239
1240 /* Check if the beacon timers are still correct, because a TSF
1241 * update might have created a window between them - for a
1242 * longer description see the comment of this function: */
1243 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1244 ath5k_beacon_update_timers(sc, bc_tstamp);
1245 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1246 "fixed beacon timers after beacon receive\n");
1247 }
8a63facc
BC		 1248 }
1249}
fa1c114f 1250
8a63facc
BC		 1251static void
1252ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1253{
1254 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1255 struct ath5k_hw *ah = sc->ah;
1256 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1257
8a63facc
BC		 1258 /* only beacons from our BSSID */
1259 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1260 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1261 return;
fa1c114f 1262
eef39bef 1263 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1264
8a63facc
BC		 1265 /* in IBSS mode we should keep RSSI statistics per neighbour */
1266 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1267}
fa1c114f 1268
8a63facc
BC		 1269/*
1270 * Compute padding position. skb must contain an IEEE 802.11 frame
1271 */
1272static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1273{
8a63facc
BC		 1274 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1275 __le16 frame_control = hdr->frame_control;
1276 int padpos = 24;
fa1c114f 1277
8a63facc
BC		 1278 if (ieee80211_has_a4(frame_control)) {
1279 padpos += ETH_ALEN;
fa1c114f 1280 }
8a63facc
BC		 1281 if (ieee80211_is_data_qos(frame_control)) {
1282 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1283 }
8a63facc
BC		 1284
1285 return padpos;
fa1c114f
JS		 1286}
1287
8a63facc
BC		 1288/*
1289 * This function expects an 802.11 frame and returns the number of
1290 * bytes added, or -1 if we don't have enough header room.
1291 */
1292static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1293{
8a63facc
BC		 1294 int padpos = ath5k_common_padpos(skb);
1295 int padsize = padpos & 3;
fa1c114f 1296
8a63facc 1297 if (padsize && skb->len>padpos) {
fa1c114f 1298
8a63facc
BC		 1299 if (skb_headroom(skb) < padsize)
1300 return -1;
fa1c114f 1301
8a63facc
BC		 1302 skb_push(skb, padsize);
1303 memmove(skb->data, skb->data+padsize, padpos);
1304 return padsize;
1305 }
a951ae21 1306
8a63facc
BC		 1307 return 0;
1308}
fa1c114f 1309
8a63facc
BC		 1310/*
1311 * The MAC header is padded to have 32-bit boundary if the
1312 * packet payload is non-zero. The general calculation for
1313 * padsize would take into account odd header lengths:
1314 * padsize = 4 - (hdrlen & 3); however, since only
1315 * even-length headers are used, padding can only be 0 or 2
1316 * bytes and we can optimize this a bit. We must not try to
1317 * remove padding from short control frames that do not have a
1318 * payload.
1319 *
1320 * This function expects an 802.11 frame and returns the number of
1321 * bytes removed.
1322 */
1323static int ath5k_remove_padding(struct sk_buff *skb)
1324{
1325 int padpos = ath5k_common_padpos(skb);
1326 int padsize = padpos & 3;
6d91e1d8 1327
8a63facc
BC		 1328 if (padsize && skb->len>=padpos+padsize) {
1329 memmove(skb->data + padsize, skb->data, padpos);
1330 skb_pull(skb, padsize);
1331 return padsize;
fa1c114f 1332 }
a951ae21 1333
8a63facc 1334 return 0;
fa1c114f
JS		 1335}
1336
1337static void
8a63facc
BC		 1338ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1339 struct ath5k_rx_status *rs)
fa1c114f 1340{
8a63facc
BC		 1341 struct ieee80211_rx_status *rxs;
1342
1343 ath5k_remove_padding(skb);
1344
1345 rxs = IEEE80211_SKB_RXCB(skb);
1346
1347 rxs->flag = 0;
1348 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1349 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1350
1351 /*
8a63facc
BC		 1352 * always extend the mac timestamp, since this information is
1353 * also needed for proper IBSS merging.
1354 *
1355 * XXX: it might be too late to do it here, since rs_tstamp is
1356 * 15bit only. that means TSF extension has to be done within
1357 * 32768usec (about 32ms). it might be necessary to move this to
1358 * the interrupt handler, like it is done in madwifi.
1359 *
1360 * Unfortunately we don't know when the hardware takes the rx
1361 * timestamp (beginning of phy frame, data frame, end of rx?).
1362 * The only thing we know is that it is hardware specific...
1363 * On AR5213 it seems the rx timestamp is at the end of the
1364 * frame, but i'm not sure.
1365 *
1366 * NOTE: mac80211 defines mactime at the beginning of the first
1367 * data symbol. Since we don't have any time references it's
1368 * impossible to comply to that. This affects IBSS merge only
1369 * right now, so it's not too bad...
fa1c114f 1370 */
8a63facc
BC		 1371 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1372 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1373
8a63facc
BC		 1374 rxs->freq = sc->curchan->center_freq;
1375 rxs->band = sc->curband->band;
fa1c114f 1376
8a63facc 1377 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1378
8a63facc 1379 rxs->antenna = rs->rs_antenna;
fa1c114f 1380
8a63facc
BC		 1381 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1382 sc->stats.antenna_rx[rs->rs_antenna]++;
1383 else
1384 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1385
8a63facc
BC		 1386 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1387 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1388
8a63facc
BC		 1389 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1390 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1391 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1392
8a63facc 1393 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1394
8a63facc 1395 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1396
8a63facc
BC		 1397 /* check beacons in IBSS mode */
1398 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1399 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1400
8a63facc
BC		 1401 ieee80211_rx(sc->hw, skb);
1402}
fa1c114f 1403
8a63facc
BC		 1404/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1405 *
1406 * Check if we want to further process this frame or not. Also update
1407 * statistics. Return true if we want this frame, false if not.
fa1c114f 1408 */
8a63facc
BC		 1409static bool
1410ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1411{
8a63facc 1412 sc->stats.rx_all_count++;
b72acddb 1413 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1414
8a63facc
BC		 1415 if (unlikely(rs->rs_status)) {
1416 if (rs->rs_status & AR5K_RXERR_CRC)
1417 sc->stats.rxerr_crc++;
1418 if (rs->rs_status & AR5K_RXERR_FIFO)
1419 sc->stats.rxerr_fifo++;
1420 if (rs->rs_status & AR5K_RXERR_PHY) {
1421 sc->stats.rxerr_phy++;
1422 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1423 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1424 return false;
1425 }
1426 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1427 /*
1428 * Decrypt error. If the error occurred
1429 * because there was no hardware key, then
1430 * let the frame through so the upper layers
1431 * can process it. This is necessary for 5210
1432 * parts which have no way to setup a ``clear''
1433 * key cache entry.
1434 *
1435 * XXX do key cache faulting
1436 */
1437 sc->stats.rxerr_decrypt++;
1438 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1439 !(rs->rs_status & AR5K_RXERR_CRC))
1440 return true;
1441 }
1442 if (rs->rs_status & AR5K_RXERR_MIC) {
1443 sc->stats.rxerr_mic++;
1444 return true;
fa1c114f 1445 }
fa1c114f 1446
8a63facc
BC		 1447 /* reject any frames with non-crypto errors */
1448 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1449 return false;
1450 }
fa1c114f 1451
8a63facc
BC		 1452 if (unlikely(rs->rs_more)) {
1453 sc->stats.rxerr_jumbo++;
1454 return false;
1455 }
1456 return true;
fa1c114f
JS		 1457}
1458
fa1c114f 1459static void
8a63facc 1460ath5k_tasklet_rx(unsigned long data)
fa1c114f 1461{
8a63facc
BC		 1462 struct ath5k_rx_status rs = {};
1463 struct sk_buff *skb, *next_skb;
1464 dma_addr_t next_skb_addr;
1465 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1466 struct ath5k_hw *ah = sc->ah;
1467 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1468 struct ath5k_buf *bf;
1469 struct ath5k_desc *ds;
1470 int ret;
fa1c114f 1471
8a63facc
BC		 1472 spin_lock(&sc->rxbuflock);
1473 if (list_empty(&sc->rxbuf)) {
1474 ATH5K_WARN(sc, "empty rx buf pool\n");
1475 goto unlock;
1476 }
1477 do {
1478 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1479 BUG_ON(bf->skb == NULL);
1480 skb = bf->skb;
1481 ds = bf->desc;
fa1c114f 1482
8a63facc
BC		 1483 /* bail if HW is still using self-linked descriptor */
1484 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1485 break;
fa1c114f 1486
8a63facc
BC		 1487 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1488 if (unlikely(ret == -EINPROGRESS))
1489 break;
1490 else if (unlikely(ret)) {
1491 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1492 sc->stats.rxerr_proc++;
1493 break;
1494 }
fa1c114f 1495
8a63facc
BC		 1496 if (ath5k_receive_frame_ok(sc, &rs)) {
1497 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1498
8a63facc
BC		 1499 /*
1500 * If we can't replace bf->skb with a new skb under
1501 * memory pressure, just skip this packet
1502 */
1503 if (!next_skb)
1504 goto next;
036cd1ec 1505
aeae4ac9 1506 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1507 common->rx_bufsize,
aeae4ac9 1508 DMA_FROM_DEVICE);
036cd1ec 1509
8a63facc 1510 skb_put(skb, rs.rs_datalen);
6ba81c2c 1511
8a63facc 1512 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1513
8a63facc
BC		 1514 bf->skb = next_skb;
1515 bf->skbaddr = next_skb_addr;
036cd1ec 1516 }
8a63facc
BC		 1517next:
1518 list_move_tail(&bf->list, &sc->rxbuf);
1519 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1520unlock:
1521 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1522}
1523
b4ea449d 1524
8a63facc
BC		 1525/*************\
1526* TX Handling *
1527\*************/
b4ea449d 1528
cd2c5486
BR		 1529int
1530ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1531 struct ath5k_txq *txq)
8a63facc
BC		 1532{
1533 struct ath5k_softc *sc = hw->priv;
1534 struct ath5k_buf *bf;
1535 unsigned long flags;
1536 int padsize;
b4ea449d 1537
8a63facc 1538 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
b4ea449d 1539
8a63facc
BC		 1540 /*
1541 * The hardware expects the header padded to 4 byte boundaries.
1542 * If this is not the case, we add the padding after the header.
1543 */
1544 padsize = ath5k_add_padding(skb);
1545 if (padsize < 0) {
1546 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1547 " headroom to pad");
1548 goto drop_packet;
1549 }
8127fbdc 1550
925e0b06
BR		 1551 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1552 ieee80211_stop_queue(hw, txq->qnum);
1553
8a63facc
BC		 1554 spin_lock_irqsave(&sc->txbuflock, flags);
1555 if (list_empty(&sc->txbuf)) {
1556 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1557 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1558 ieee80211_stop_queues(hw);
8a63facc 1559 goto drop_packet;
8127fbdc 1560 }
8a63facc
BC		 1561 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1562 list_del(&bf->list);
1563 sc->txbuf_len--;
1564 if (list_empty(&sc->txbuf))
1565 ieee80211_stop_queues(hw);
1566 spin_unlock_irqrestore(&sc->txbuflock, flags);
1567
1568 bf->skb = skb;
1569
1570 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1571 bf->skb = NULL;
1572 spin_lock_irqsave(&sc->txbuflock, flags);
1573 list_add_tail(&bf->list, &sc->txbuf);
1574 sc->txbuf_len++;
1575 spin_unlock_irqrestore(&sc->txbuflock, flags);
1576 goto drop_packet;
8127fbdc 1577 }
8a63facc 1578 return NETDEV_TX_OK;
8127fbdc 1579
8a63facc
BC		 1580drop_packet:
1581 dev_kfree_skb_any(skb);
1582 return NETDEV_TX_OK;
8127fbdc
BP		 1583}
1584
1440401e
BR		 1585static void
1586ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1587 struct ath5k_tx_status *ts)
1588{
1589 struct ieee80211_tx_info *info;
1590 int i;
1591
1592 sc->stats.tx_all_count++;
b72acddb 1593 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1594 info = IEEE80211_SKB_CB(skb);
1595
1596 ieee80211_tx_info_clear_status(info);
1597 for (i = 0; i < 4; i++) {
1598 struct ieee80211_tx_rate *r =
1599 &info->status.rates[i];
1600
1601 if (ts->ts_rate[i]) {
1602 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1603 r->count = ts->ts_retry[i];
1604 } else {
1605 r->idx = -1;
1606 r->count = 0;
1607 }
1608 }
1609
1610 /* count the successful attempt as well */
1611 info->status.rates[ts->ts_final_idx].count++;
1612
1613 if (unlikely(ts->ts_status)) {
1614 sc->stats.ack_fail++;
1615 if (ts->ts_status & AR5K_TXERR_FILT) {
1616 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1617 sc->stats.txerr_filt++;
1618 }
1619 if (ts->ts_status & AR5K_TXERR_XRETRY)
1620 sc->stats.txerr_retry++;
1621 if (ts->ts_status & AR5K_TXERR_FIFO)
1622 sc->stats.txerr_fifo++;
1623 } else {
1624 info->flags |= IEEE80211_TX_STAT_ACK;
1625 info->status.ack_signal = ts->ts_rssi;
1626 }
1627
1628 /*
1629 * Remove MAC header padding before giving the frame
1630 * back to mac80211.
1631 */
1632 ath5k_remove_padding(skb);
1633
1634 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1635 sc->stats.antenna_tx[ts->ts_antenna]++;
1636 else
1637 sc->stats.antenna_tx[0]++; /* invalid */
1638
1639 ieee80211_tx_status(sc->hw, skb);
1640}
8a63facc
BC		 1641
1642static void
1643ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1644{
8a63facc
BC		 1645 struct ath5k_tx_status ts = {};
1646 struct ath5k_buf *bf, *bf0;
1647 struct ath5k_desc *ds;
1648 struct sk_buff *skb;
1440401e 1649 int ret;
8127fbdc 1650
8a63facc
BC		 1651 spin_lock(&txq->lock);
1652 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1653
1654 txq->txq_poll_mark = false;
1655
1656 /* skb might already have been processed last time. */
1657 if (bf->skb != NULL) {
1658 ds = bf->desc;
1659
1660 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1661 if (unlikely(ret == -EINPROGRESS))
1662 break;
1663 else if (unlikely(ret)) {
1664 ATH5K_ERR(sc,
1665 "error %d while processing "
1666 "queue %u\n", ret, txq->qnum);
1667 break;
1668 }
1669
1670 skb = bf->skb;
1671 bf->skb = NULL;
aeae4ac9
FF		 1672
1673 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1674 DMA_TO_DEVICE);
23413296
BR		 1675 ath5k_tx_frame_completed(sc, skb, &ts);
1676 }
8127fbdc 1677
8a63facc
BC		 1678 /*
1679 * It's possible that the hardware can say the buffer is
1680 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1681 * host memory and moved on.
1682 * Always keep the last descriptor to avoid HW races...
8a63facc 1683 */
23413296
BR		 1684 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1685 spin_lock(&sc->txbuflock);
1686 list_move_tail(&bf->list, &sc->txbuf);
1687 sc->txbuf_len++;
1688 txq->txq_len--;
1689 spin_unlock(&sc->txbuflock);
8a63facc 1690 }
fa1c114f 1691 }
fa1c114f 1692 spin_unlock(&txq->lock);
4198a8d0 1693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1694 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1695}
1696
1697static void
1698ath5k_tasklet_tx(unsigned long data)
1699{
8784d2ee 1700 int i;
fa1c114f
JS		 1701 struct ath5k_softc *sc = (void *)data;
1702
8784d2ee
BC		 1703 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1704 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1705 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1706}
1707
1708
fa1c114f
JS		 1709/*****************\
1710* Beacon handling *
1711\*****************/
1712
1713/*
1714 * Setup the beacon frame for transmit.
1715 */
1716static int
e039fa4a 1717ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1718{
1719 struct sk_buff *skb = bf->skb;
a888d52d 1720 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1721 struct ath5k_hw *ah = sc->ah;
1722 struct ath5k_desc *ds;
2bed03eb
NK		 1723 int ret = 0;
1724 u8 antenna;
fa1c114f 1725 u32 flags;
8127fbdc 1726 const int padsize = 0;
fa1c114f 1727
aeae4ac9
FF		 1728 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1729 DMA_TO_DEVICE);
fa1c114f
JS		 1730 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1731 "skbaddr %llx\n", skb, skb->data, skb->len,
1732 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1733
1734 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1735 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1736 return -EIO;
1737 }
1738
1739 ds = bf->desc;
2bed03eb 1740 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1741
1742 flags = AR5K_TXDESC_NOACK;
05c914fe 1743 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1744 ds->ds_link = bf->daddr; /* self-linked */
1745 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1746 } else
fa1c114f 1747 ds->ds_link = 0;
2bed03eb
NK		 1748
1749 /*
1750 * If we use multiple antennas on AP and use
1751 * the Sectored AP scenario, switch antenna every
1752 * 4 beacons to make sure everybody hears our AP.
1753 * When a client tries to associate, hw will keep
1754 * track of the tx antenna to be used for this client
1755 * automaticaly, based on ACKed packets.
1756 *
1757 * Note: AP still listens and transmits RTS on the
1758 * default antenna which is supposed to be an omni.
1759 *
1760 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1761 * multiple antennas (1 omni -- the default -- and 14
1762 * sectors), so if we choose to actually support this
1763 * mode, we need to allow the user to set how many antennas
1764 * we have and tweak the code below to send beacons
1765 * on all of them.
2bed03eb
NK		 1766 */
1767 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1768 antenna = sc->bsent & 4 ? 2 : 1;
1769
fa1c114f 1770
8f655dde
NK		 1771 /* FIXME: If we are in g mode and rate is a CCK rate
1772 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1773 * from tx power (value is in dB units already) */
fa1c114f 1774 ds->ds_data = bf->skbaddr;
281c56dd 1775 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1776 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1777 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1778 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1779 1, AR5K_TXKEYIX_INVALID,
400ec45a 1780 antenna, flags, 0, 0);
fa1c114f
JS		 1781 if (ret)
1782 goto err_unmap;
1783
1784 return 0;
1785err_unmap:
aeae4ac9 1786 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1787 return ret;
1788}
1789
8a63facc
BC		 1790/*
1791 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1792 * this is called only once at config_bss time, for AP we do it every
1793 * SWBA interrupt so that the TIM will reflect buffered frames.
1794 *
1795 * Called with the beacon lock.
1796 */
cd2c5486 1797int
8a63facc
BC		 1798ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1799{
1800 int ret;
1801 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1802 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1803 struct sk_buff *skb;
1804
1805 if (WARN_ON(!vif)) {
1806 ret = -EINVAL;
1807 goto out;
1808 }
1809
1810 skb = ieee80211_beacon_get(hw, vif);
1811
1812 if (!skb) {
1813 ret = -ENOMEM;
1814 goto out;
1815 }
1816
1817 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1818
b1ae1edf
BG		 1819 ath5k_txbuf_free_skb(sc, avf->bbuf);
1820 avf->bbuf->skb = skb;
1821 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1822 if (ret)
b1ae1edf 1823 avf->bbuf->skb = NULL;
8a63facc
BC		 1824out:
1825 return ret;
1826}
1827
fa1c114f
JS		 1828/*
1829 * Transmit a beacon frame at SWBA. Dynamic updates to the
1830 * frame contents are done as needed and the slot time is
1831 * also adjusted based on current state.
1832 *
5faaff74
BC		 1833 * This is called from software irq context (beacontq tasklets)
1834 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1835 */
1836static void
1837ath5k_beacon_send(struct ath5k_softc *sc)
1838{
fa1c114f 1839 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1840 struct ieee80211_vif *vif;
1841 struct ath5k_vif *avf;
1842 struct ath5k_buf *bf;
cec8db23 1843 struct sk_buff *skb;
fa1c114f 1844
be9b7259 1845 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1846
fa1c114f
JS		 1847 /*
1848 * Check if the previous beacon has gone out. If
a180a130 1849 * not, don't don't try to post another: skip this
fa1c114f
JS		 1850 * period and wait for the next. Missed beacons
1851 * indicate a problem and should not occur. If we
1852 * miss too many consecutive beacons reset the device.
1853 */
1854 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1855 sc->bmisscount++;
be9b7259 1856 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1857 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1858 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1859 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1860 "stuck beacon time (%u missed)\n",
1861 sc->bmisscount);
8d67a031
BR		 1862 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1863 "stuck beacon, resetting\n");
5faaff74 1864 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1865 }
1866 return;
1867 }
1868 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1869 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1870 "resume beacon xmit after %u misses\n",
1871 sc->bmisscount);
1872 sc->bmisscount = 0;
1873 }
1874
b93996cf
JC		 1875 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1876 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1877 u64 tsf = ath5k_hw_get_tsf64(ah);
1878 u32 tsftu = TSF_TO_TU(tsf);
1879 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1880 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1881 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1882 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1883 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1884 } else /* only one interface */
1885 vif = sc->bslot[0];
1886
1887 if (!vif)
1888 return;
1889
1890 avf = (void *)vif->drv_priv;
1891 bf = avf->bbuf;
1892 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1893 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1894 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1895 return;
1896 }
1897
fa1c114f
JS		 1898 /*
1899 * Stop any current dma and put the new frame on the queue.
1900 * This should never fail since we check above that no frames
1901 * are still pending on the queue.
1902 */
14fae2d4 1903 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1904 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1905 /* NB: hw still stops DMA, so proceed */
1906 }
fa1c114f 1907
d82b577b
JC		 1908 /* refresh the beacon for AP or MESH mode */
1909 if (sc->opmode == NL80211_IFTYPE_AP ||
1910 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1911 ath5k_beacon_update(sc->hw, vif);
1071db86 1912
c6e387a2
NK		 1913 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1914 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1915 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1916 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1917
b1ae1edf 1918 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1919 while (skb) {
1920 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1921 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1922 }
1923
fa1c114f
JS		 1924 sc->bsent++;
1925}
1926
9804b98d
BR		 1927/**
1928 * ath5k_beacon_update_timers - update beacon timers
1929 *
1930 * @sc: struct ath5k_softc pointer we are operating on
1931 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1932 * beacon timer update based on the current HW TSF.
1933 *
1934 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1935 * of a received beacon or the current local hardware TSF and write it to the
1936 * beacon timer registers.
1937 *
1938 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1939 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1940 * when we otherwise know we have to update the timers, but we keep it in this
1941 * function to have it all together in one place.
1942 */
cd2c5486 1943void
9804b98d 1944ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1945{
1946 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1947 u32 nexttbtt, intval, hw_tu, bc_tu;
1948 u64 hw_tsf;
fa1c114f
JS		 1949
1950 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1951 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1952 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1953 if (intval < 15)
1954 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1955 intval);
1956 }
fa1c114f
JS		 1957 if (WARN_ON(!intval))
1958 return;
1959
9804b98d
BR		 1960 /* beacon TSF converted to TU */
1961 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1962
9804b98d
BR		 1963 /* current TSF converted to TU */
1964 hw_tsf = ath5k_hw_get_tsf64(ah);
1965 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1966
11f21df3
BR		 1967#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1968 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1969 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1970 * configuration we need to make sure it is bigger than that. */
1971
9804b98d
BR		 1972 if (bc_tsf == -1) {
1973 /*
1974 * no beacons received, called internally.
1975 * just need to refresh timers based on HW TSF.
1976 */
1977 nexttbtt = roundup(hw_tu + FUDGE, intval);
1978 } else if (bc_tsf == 0) {
1979 /*
1980 * no beacon received, probably called by ath5k_reset_tsf().
1981 * reset TSF to start with 0.
1982 */
1983 nexttbtt = intval;
1984 intval |= AR5K_BEACON_RESET_TSF;
1985 } else if (bc_tsf > hw_tsf) {
1986 /*
1987 * beacon received, SW merge happend but HW TSF not yet updated.
1988 * not possible to reconfigure timers yet, but next time we
1989 * receive a beacon with the same BSSID, the hardware will
1990 * automatically update the TSF and then we need to reconfigure
1991 * the timers.
1992 */
1993 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1994 "need to wait for HW TSF sync\n");
1995 return;
1996 } else {
1997 /*
1998 * most important case for beacon synchronization between STA.
1999 *
2000 * beacon received and HW TSF has been already updated by HW.
2001 * update next TBTT based on the TSF of the beacon, but make
2002 * sure it is ahead of our local TSF timer.
2003 */
2004 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2005 }
2006#undef FUDGE
fa1c114f 2007
036cd1ec
BR		 2008 sc->nexttbtt = nexttbtt;
2009
fa1c114f 2010 intval |= AR5K_BEACON_ENA;
fa1c114f 2011 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2012
2013 /*
2014 * debugging output last in order to preserve the time critical aspect
2015 * of this function
2016 */
2017 if (bc_tsf == -1)
2018 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2019 "reconfigured timers based on HW TSF\n");
2020 else if (bc_tsf == 0)
2021 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2022 "reset HW TSF and timers\n");
2023 else
2024 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2025 "updated timers based on beacon TSF\n");
2026
2027 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2028 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2029 (unsigned long long) bc_tsf,
2030 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2031 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2032 intval & AR5K_BEACON_PERIOD,
2033 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2034 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2035}
2036
036cd1ec
BR		 2037/**
2038 * ath5k_beacon_config - Configure the beacon queues and interrupts
2039 *
2040 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2041 *
036cd1ec 2042 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2043 * interrupts to detect TSF updates only.
fa1c114f 2044 */
cd2c5486 2045void
fa1c114f
JS		 2046ath5k_beacon_config(struct ath5k_softc *sc)
2047{
2048 struct ath5k_hw *ah = sc->ah;
b5f03956 2049 unsigned long flags;
fa1c114f 2050
21800491 2051 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2052 sc->bmisscount = 0;
dc1968e7 2053 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2054
21800491 2055 if (sc->enable_beacon) {
fa1c114f 2056 /*
036cd1ec
BR		 2057 * In IBSS mode we use a self-linked tx descriptor and let the
2058 * hardware send the beacons automatically. We have to load it
fa1c114f 2059 * only once here.
036cd1ec 2060 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2061 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2062 */
2063 ath5k_beaconq_config(sc);
fa1c114f 2064
036cd1ec
BR		 2065 sc->imask |= AR5K_INT_SWBA;
2066
da966bca 2067 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2068 if (ath5k_hw_hasveol(ah))
da966bca 2069 ath5k_beacon_send(sc);
da966bca
JS		 2070 } else
2071 ath5k_beacon_update_timers(sc, -1);
21800491 2072 } else {
14fae2d4 2073 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2074 }
fa1c114f 2075
c6e387a2 2076 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2077 mmiowb();
2078 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2079}
2080
428cbd4f
NK		 2081static void ath5k_tasklet_beacon(unsigned long data)
2082{
2083 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2084
2085 /*
2086 * Software beacon alert--time to send a beacon.
2087 *
2088 * In IBSS mode we use this interrupt just to
2089 * keep track of the next TBTT (target beacon
2090 * transmission time) in order to detect wether
2091 * automatic TSF updates happened.
2092 */
2093 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2094 /* XXX: only if VEOL suppported */
2095 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2096 sc->nexttbtt += sc->bintval;
2097 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2098 "SWBA nexttbtt: %x hw_tu: %x "
2099 "TSF: %llx\n",
2100 sc->nexttbtt,
2101 TSF_TO_TU(tsf),
2102 (unsigned long long) tsf);
2103 } else {
2104 spin_lock(&sc->block);
2105 ath5k_beacon_send(sc);
2106 spin_unlock(&sc->block);
2107 }
2108}
2109
fa1c114f
JS		 2110
2111/********************\
2112* Interrupt handling *
2113\********************/
2114
6a8a3f6b
BR		 2115static void
2116ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2117{
2111ac0d
BR		 2118 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2119 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2120 /* run ANI only when full calibration is not active */
2121 ah->ah_cal_next_ani = jiffies +
2122 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2123 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2124
2125 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2126 ah->ah_cal_next_full = jiffies +
2127 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2128 tasklet_schedule(&ah->ah_sc->calib);
2129 }
2130 /* we could use SWI to generate enough interrupts to meet our
2131 * calibration interval requirements, if necessary:
2132 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2133}
2134
132b1c3e 2135irqreturn_t
fa1c114f
JS		 2136ath5k_intr(int irq, void *dev_id)
2137{
2138 struct ath5k_softc *sc = dev_id;
2139 struct ath5k_hw *ah = sc->ah;
2140 enum ath5k_int status;
2141 unsigned int counter = 1000;
2142
2143 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2144 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2145 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2146 return IRQ_NONE;
2147
2148 do {
fa1c114f
JS		 2149 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2150 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2151 status, sc->imask);
fa1c114f
JS		 2152 if (unlikely(status & AR5K_INT_FATAL)) {
2153 /*
2154 * Fatal errors are unrecoverable.
2155 * Typically these are caused by DMA errors.
2156 */
8d67a031
BR		 2157 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2158 "fatal int, resetting\n");
5faaff74 2159 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2160 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2161 /*
2162 * Receive buffers are full. Either the bus is busy or
2163 * the CPU is not fast enough to process all received
2164 * frames.
2165 * Older chipsets need a reset to come out of this
2166 * condition, but we treat it as RX for newer chips.
2167 * We don't know exactly which versions need a reset -
2168 * this guess is copied from the HAL.
2169 */
2170 sc->stats.rxorn_intr++;
8d67a031
BR		 2171 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2172 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2173 "rx overrun, resetting\n");
5faaff74 2174 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2175 }
87d77c4e
BR		 2176 else
2177 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2178 } else {
2179 if (status & AR5K_INT_SWBA) {
56d2ac76 2180 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2181 }
2182 if (status & AR5K_INT_RXEOL) {
2183 /*
2184 * NB: the hardware should re-read the link when
2185 * RXE bit is written, but it doesn't work at
2186 * least on older hardware revs.
2187 */
b3f194e5 2188 sc->stats.rxeol_intr++;
fa1c114f
JS		 2189 }
2190 if (status & AR5K_INT_TXURN) {
2191 /* bump tx trigger level */
2192 ath5k_hw_update_tx_triglevel(ah, true);
2193 }
4c674c60 2194 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2195 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2196 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2197 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2198 tasklet_schedule(&sc->txtq);
2199 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2200 /* TODO */
fa1c114f
JS		 2201 }
2202 if (status & AR5K_INT_MIB) {
2111ac0d 2203 sc->stats.mib_intr++;
495391d7 2204 ath5k_hw_update_mib_counters(ah);
2111ac0d 2205 ath5k_ani_mib_intr(ah);
fa1c114f 2206 }
e6a3b616 2207 if (status & AR5K_INT_GPIO)
e6a3b616 2208 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2209
fa1c114f 2210 }
4cebb34c
FF		 2211
2212 if (ath5k_get_bus_type(ah) == ATH_AHB)
2213 break;
2214
2516baa6 2215 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2216
2217 if (unlikely(!counter))
2218 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2219
6a8a3f6b 2220 ath5k_intr_calibration_poll(ah);
6e220662 2221
fa1c114f
JS		 2222 return IRQ_HANDLED;
2223}
2224
fa1c114f
JS		 2225/*
2226 * Periodically recalibrate the PHY to account
2227 * for temperature/environment changes.
2228 */
2229static void
6e220662 2230ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2231{
2232 struct ath5k_softc *sc = (void *)data;
2233 struct ath5k_hw *ah = sc->ah;
2234
6e220662 2235 /* Only full calibration for now */
e65e1d77 2236 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2237
fa1c114f 2238 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2239 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2240 sc->curchan->hw_value);
fa1c114f 2241
6f3b414a 2242 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2243 /*
2244 * Rfgain is out of bounds, reset the chip
2245 * to load new gain values.
2246 */
2247 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2248 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2249 }
2250 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2251 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2252 ieee80211_frequency_to_channel(
2253 sc->curchan->center_freq));
fa1c114f 2254
0e8e02dd 2255 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2256 * doesn't.
2257 * TODO: We should stop TX here, so that it doesn't interfere.
2258 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2259 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2260 ah->ah_cal_next_nf = jiffies +
2261 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2262 ath5k_hw_update_noise_floor(ah);
afe86286 2263 }
6e220662 2264
e65e1d77 2265 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2266}
2267
2268
2111ac0d
BR		 2269static void
2270ath5k_tasklet_ani(unsigned long data)
2271{
2272 struct ath5k_softc *sc = (void *)data;
2273 struct ath5k_hw *ah = sc->ah;
2274
2275 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2276 ath5k_ani_calibration(ah);
2277 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2278}
2279
2280
4edd761f
BR		 2281static void
2282ath5k_tx_complete_poll_work(struct work_struct *work)
2283{
2284 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2285 tx_complete_work.work);
2286 struct ath5k_txq *txq;
2287 int i;
2288 bool needreset = false;
2289
2290 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2291 if (sc->txqs[i].setup) {
2292 txq = &sc->txqs[i];
2293 spin_lock_bh(&txq->lock);
23413296 2294 if (txq->txq_len > 1) {
4edd761f
BR		 2295 if (txq->txq_poll_mark) {
2296 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2297 "TX queue stuck %d\n",
2298 txq->qnum);
2299 needreset = true;
923e5b3d 2300 txq->txq_stuck++;
4edd761f
BR		 2301 spin_unlock_bh(&txq->lock);
2302 break;
2303 } else {
2304 txq->txq_poll_mark = true;
2305 }
2306 }
2307 spin_unlock_bh(&txq->lock);
2308 }
2309 }
2310
2311 if (needreset) {
2312 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2313 "TX queues stuck, resetting\n");
8aec7af9 2314 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2315 }
2316
2317 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2318 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2319}
2320
2321
8a63facc
BC		 2322/*************************\
2323* Initialization routines *
2324\*************************/
fa1c114f 2325
132b1c3e
FF		 2326int
2327ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2328{
2329 struct ieee80211_hw *hw = sc->hw;
2330 struct ath_common *common;
2331 int ret;
2332 int csz;
2333
2334 /* Initialize driver private data */
2335 SET_IEEE80211_DEV(hw, sc->dev);
2336 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2337 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2338 IEEE80211_HW_SIGNAL_DBM |
2339 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2340
2341 hw->wiphy->interface_modes =
2342 BIT(NL80211_IFTYPE_AP) |
2343 BIT(NL80211_IFTYPE_STATION) |
2344 BIT(NL80211_IFTYPE_ADHOC) |
2345 BIT(NL80211_IFTYPE_MESH_POINT);
2346
3de135db
BR		 2347 /* both antennas can be configured as RX or TX */
2348 hw->wiphy->available_antennas_tx = 0x3;
2349 hw->wiphy->available_antennas_rx = 0x3;
2350
132b1c3e
FF		 2351 hw->extra_tx_headroom = 2;
2352 hw->channel_change_time = 5000;
2353
2354 /*
2355 * Mark the device as detached to avoid processing
2356 * interrupts until setup is complete.
2357 */
2358 __set_bit(ATH_STAT_INVALID, sc->status);
2359
2360 sc->opmode = NL80211_IFTYPE_STATION;
2361 sc->bintval = 1000;
2362 mutex_init(&sc->lock);
2363 spin_lock_init(&sc->rxbuflock);
2364 spin_lock_init(&sc->txbuflock);
2365 spin_lock_init(&sc->block);
2366
2367
2368 /* Setup interrupt handler */
2369 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2370 if (ret) {
2371 ATH5K_ERR(sc, "request_irq failed\n");
2372 goto err;
2373 }
2374
2375 /* If we passed the test, malloc an ath5k_hw struct */
2376 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2377 if (!sc->ah) {
2378 ret = -ENOMEM;
2379 ATH5K_ERR(sc, "out of memory\n");
2380 goto err_irq;
2381 }
2382
2383 sc->ah->ah_sc = sc;
2384 sc->ah->ah_iobase = sc->iobase;
2385 common = ath5k_hw_common(sc->ah);
2386 common->ops = &ath5k_common_ops;
2387 common->bus_ops = bus_ops;
2388 common->ah = sc->ah;
2389 common->hw = hw;
2390 common->priv = sc;
2391
2392 /*
2393 * Cache line size is used to size and align various
2394 * structures used to communicate with the hardware.
2395 */
2396 ath5k_read_cachesize(common, &csz);
2397 common->cachelsz = csz << 2; /* convert to bytes */
2398
2399 spin_lock_init(&common->cc_lock);
2400
2401 /* Initialize device */
2402 ret = ath5k_hw_init(sc);
2403 if (ret)
2404 goto err_free_ah;
2405
2406 /* set up multi-rate retry capabilities */
2407 if (sc->ah->ah_version == AR5K_AR5212) {
2408 hw->max_rates = 4;
2409 hw->max_rate_tries = 11;
2410 }
2411
2412 hw->vif_data_size = sizeof(struct ath5k_vif);
2413
2414 /* Finish private driver data initialization */
2415 ret = ath5k_init(hw);
2416 if (ret)
2417 goto err_ah;
2418
2419 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2420 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2421 sc->ah->ah_mac_srev,
2422 sc->ah->ah_phy_revision);
2423
2424 if (!sc->ah->ah_single_chip) {
2425 /* Single chip radio (!RF5111) */
2426 if (sc->ah->ah_radio_5ghz_revision &&
2427 !sc->ah->ah_radio_2ghz_revision) {
2428 /* No 5GHz support -> report 2GHz radio */
2429 if (!test_bit(AR5K_MODE_11A,
2430 sc->ah->ah_capabilities.cap_mode)) {
2431 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2432 ath5k_chip_name(AR5K_VERSION_RAD,
2433 sc->ah->ah_radio_5ghz_revision),
2434 sc->ah->ah_radio_5ghz_revision);
2435 /* No 2GHz support (5110 and some
2436 * 5Ghz only cards) -> report 5Ghz radio */
2437 } else if (!test_bit(AR5K_MODE_11B,
2438 sc->ah->ah_capabilities.cap_mode)) {
2439 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2440 ath5k_chip_name(AR5K_VERSION_RAD,
2441 sc->ah->ah_radio_5ghz_revision),
2442 sc->ah->ah_radio_5ghz_revision);
2443 /* Multiband radio */
2444 } else {
2445 ATH5K_INFO(sc, "RF%s multiband radio found"
2446 " (0x%x)\n",
2447 ath5k_chip_name(AR5K_VERSION_RAD,
2448 sc->ah->ah_radio_5ghz_revision),
2449 sc->ah->ah_radio_5ghz_revision);
2450 }
2451 }
2452 /* Multi chip radio (RF5111 - RF2111) ->
2453 * report both 2GHz/5GHz radios */
2454 else if (sc->ah->ah_radio_5ghz_revision &&
2455 sc->ah->ah_radio_2ghz_revision){
2456 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2457 ath5k_chip_name(AR5K_VERSION_RAD,
2458 sc->ah->ah_radio_5ghz_revision),
2459 sc->ah->ah_radio_5ghz_revision);
2460 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2461 ath5k_chip_name(AR5K_VERSION_RAD,
2462 sc->ah->ah_radio_2ghz_revision),
2463 sc->ah->ah_radio_2ghz_revision);
2464 }
2465 }
2466
2467 ath5k_debug_init_device(sc);
2468
2469 /* ready to process interrupts */
2470 __clear_bit(ATH_STAT_INVALID, sc->status);
2471
2472 return 0;
2473err_ah:
2474 ath5k_hw_deinit(sc->ah);
2475err_free_ah:
2476 kfree(sc->ah);
2477err_irq:
2478 free_irq(sc->irq, sc);
2479err:
2480 return ret;
2481}
2482
fa1c114f 2483static int
8a63facc 2484ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2485{
8a63facc 2486 struct ath5k_hw *ah = sc->ah;
cec8db23 2487
8a63facc
BC		 2488 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2489 test_bit(ATH_STAT_INVALID, sc->status));
2490
2491 /*
2492 * Shutdown the hardware and driver:
2493 * stop output from above
2494 * disable interrupts
2495 * turn off timers
2496 * turn off the radio
2497 * clear transmit machinery
2498 * clear receive machinery
2499 * drain and release tx queues
2500 * reclaim beacon resources
2501 * power down hardware
2502 *
2503 * Note that some of this work is not possible if the
2504 * hardware is gone (invalid).
2505 */
2506 ieee80211_stop_queues(sc->hw);
2507
2508 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2509 ath5k_led_off(sc);
2510 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2511 synchronize_irq(sc->irq);
8a63facc 2512 ath5k_rx_stop(sc);
80dac9ee
NK		 2513 ath5k_hw_dma_stop(ah);
2514 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2515 ath5k_hw_phy_disable(ah);
2516 }
2517
2518 return 0;
cec8db23
BC		 2519}
2520
cd2c5486 2521int
132b1c3e 2522ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2523{
8a63facc
BC		 2524 struct ath5k_hw *ah = sc->ah;
2525 struct ath_common *common = ath5k_hw_common(ah);
2526 int ret, i;
fa1c114f 2527
8a63facc
BC		 2528 mutex_lock(&sc->lock);
2529
2530 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2531
fa1c114f 2532 /*
8a63facc
BC		 2533 * Stop anything previously setup. This is safe
2534 * no matter this is the first time through or not.
fa1c114f 2535 */
8a63facc 2536 ath5k_stop_locked(sc);
fa1c114f 2537
8a63facc
BC		 2538 /*
2539 * The basic interface to setting the hardware in a good
2540 * state is ``reset''. On return the hardware is known to
2541 * be powered up and with interrupts disabled. This must
2542 * be followed by initialization of the appropriate bits
2543 * and then setup of the interrupt mask.
2544 */
2545 sc->curchan = sc->hw->conf.channel;
2546 sc->curband = &sc->sbands[sc->curchan->band];
2547 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2548 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2549 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2550
8aec7af9 2551 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2552 if (ret)
2553 goto done;
fa1c114f 2554
8a63facc
BC		 2555 ath5k_rfkill_hw_start(ah);
2556
2557 /*
2558 * Reset the key cache since some parts do not reset the
2559 * contents on initial power up or resume from suspend.
2560 */
2561 for (i = 0; i < common->keymax; i++)
2562 ath_hw_keyreset(common, (u16) i);
2563
61cde037
NK		 2564 /* Use higher rates for acks instead of base
2565 * rate */
2566 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2567
2568 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2569 sc->bslot[i] = NULL;
2570
8a63facc
BC		 2571 ret = 0;
2572done:
2573 mmiowb();
2574 mutex_unlock(&sc->lock);
4edd761f
BR		 2575
2576 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2577 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2578
8a63facc
BC		 2579 return ret;
2580}
2581
2582static void stop_tasklets(struct ath5k_softc *sc)
2583{
2584 tasklet_kill(&sc->rxtq);
2585 tasklet_kill(&sc->txtq);
2586 tasklet_kill(&sc->calib);
2587 tasklet_kill(&sc->beacontq);
2588 tasklet_kill(&sc->ani_tasklet);
2589}
2590
2591/*
2592 * Stop the device, grabbing the top-level lock to protect
2593 * against concurrent entry through ath5k_init (which can happen
2594 * if another thread does a system call and the thread doing the
2595 * stop is preempted).
2596 */
cd2c5486 2597int
8a63facc
BC		 2598ath5k_stop_hw(struct ath5k_softc *sc)
2599{
2600 int ret;
2601
2602 mutex_lock(&sc->lock);
2603 ret = ath5k_stop_locked(sc);
2604 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2605 /*
2606 * Don't set the card in full sleep mode!
2607 *
2608 * a) When the device is in this state it must be carefully
2609 * woken up or references to registers in the PCI clock
2610 * domain may freeze the bus (and system). This varies
2611 * by chip and is mostly an issue with newer parts
2612 * (madwifi sources mentioned srev >= 0x78) that go to
2613 * sleep more quickly.
2614 *
2615 * b) On older chips full sleep results a weird behaviour
2616 * during wakeup. I tested various cards with srev < 0x78
2617 * and they don't wake up after module reload, a second
2618 * module reload is needed to bring the card up again.
2619 *
2620 * Until we figure out what's going on don't enable
2621 * full chip reset on any chip (this is what Legacy HAL
2622 * and Sam's HAL do anyway). Instead Perform a full reset
2623 * on the device (same as initial state after attach) and
2624 * leave it idle (keep MAC/BB on warm reset) */
2625 ret = ath5k_hw_on_hold(sc->ah);
2626
2627 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2628 "putting device to sleep\n");
fa1c114f
JS		 2629 }
2630
8a63facc
BC		 2631 mmiowb();
2632 mutex_unlock(&sc->lock);
2633
2634 stop_tasklets(sc);
2635
4edd761f
BR		 2636 cancel_delayed_work_sync(&sc->tx_complete_work);
2637
8a63facc
BC		 2638 ath5k_rfkill_hw_stop(sc->ah);
2639
2640 return ret;
fa1c114f
JS		 2641}
2642
209d889b
BC		 2643/*
2644 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2645 * and change to the given channel.
5faaff74
BC		 2646 *
2647 * This should be called with sc->lock.
209d889b 2648 */
fa1c114f 2649static int
8aec7af9
NK		 2650ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2651 bool skip_pcu)
fa1c114f 2652{
fa1c114f 2653 struct ath5k_hw *ah = sc->ah;
f15a4bb2 2654 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2655 int ret, ani_mode;
fa1c114f
JS		 2656
2657 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2658
450464de 2659 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2660 synchronize_irq(sc->irq);
450464de
BC		 2661 stop_tasklets(sc);
2662
344b54b9
NK		 2663 /* Save ani mode and disable ANI durring
2664 * reset. If we don't we might get false
2665 * PHY error interrupts. */
2666 ani_mode = ah->ah_sc->ani_state.ani_mode;
2667 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2668
19252ecb
NK		 2669 /* We are going to empty hw queues
2670 * so we should also free any remaining
2671 * tx buffers */
2672 ath5k_drain_tx_buffs(sc);
209d889b 2673 if (chan) {
209d889b
BC		 2674 sc->curchan = chan;
2675 sc->curband = &sc->sbands[chan->band];
d7dc1003 2676 }
8aec7af9
NK		 2677 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2678 skip_pcu);
d7dc1003 2679 if (ret) {
fa1c114f
JS		 2680 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2681 goto err;
2682 }
d7dc1003 2683
fa1c114f 2684 ret = ath5k_rx_start(sc);
d7dc1003 2685 if (ret) {
fa1c114f
JS		 2686 ATH5K_ERR(sc, "can't start recv logic\n");
2687 goto err;
2688 }
d7dc1003 2689
344b54b9 2690 ath5k_ani_init(ah, ani_mode);
2111ac0d 2691
ac559526
BR		 2692 ah->ah_cal_next_full = jiffies;
2693 ah->ah_cal_next_ani = jiffies;
afe86286 2694 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2695 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2696
f15a4bb2
BR		 2697 /* clear survey data and cycle counters */
2698 memset(&sc->survey, 0, sizeof(sc->survey));
bb007554 2699 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2700 ath_hw_cycle_counters_update(common);
2701 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2702 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2703 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2704
fa1c114f 2705 /*
d7dc1003
JS		 2706 * Change channels and update the h/w rate map if we're switching;
2707 * e.g. 11a to 11b/g.
2708 *
2709 * We may be doing a reset in response to an ioctl that changes the
2710 * channel so update any state that might change as a result.
fa1c114f
JS		 2711 *
2712 * XXX needed?
2713 */
2714/* ath5k_chan_change(sc, c); */
fa1c114f 2715
d7dc1003
JS		 2716 ath5k_beacon_config(sc);
2717 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2718
397f385b
BR		 2719 ieee80211_wake_queues(sc->hw);
2720
fa1c114f
JS		 2721 return 0;
2722err:
2723 return ret;
2724}
2725
5faaff74
BC		 2726static void ath5k_reset_work(struct work_struct *work)
2727{
2728 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2729 reset_work);
2730
2731 mutex_lock(&sc->lock);
8aec7af9 2732 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2733 mutex_unlock(&sc->lock);
2734}
2735
8a63facc 2736static int
132b1c3e 2737ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2738{
132b1c3e 2739
fa1c114f 2740 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2741 struct ath5k_hw *ah = sc->ah;
2742 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2743 struct ath5k_txq *txq;
8a63facc 2744 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2745 int ret;
2746
fa1c114f 2747
8a63facc
BC		 2748 /*
2749 * Check if the MAC has multi-rate retry support.
2750 * We do this by trying to setup a fake extended
2751 * descriptor. MACs that don't have support will
2752 * return false w/o doing anything. MACs that do
2753 * support it will return true w/o doing anything.
2754 */
2755 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2756
8a63facc
BC		 2757 if (ret < 0)
2758 goto err;
2759 if (ret > 0)
2760 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2761
8a63facc
BC		 2762 /*
2763 * Collect the channel list. The 802.11 layer
2764 * is resposible for filtering this list based
2765 * on settings like the phy mode and regulatory
2766 * domain restrictions.
2767 */
2768 ret = ath5k_setup_bands(hw);
2769 if (ret) {
2770 ATH5K_ERR(sc, "can't get channels\n");
2771 goto err;
2772 }
67d2e2df 2773
8a63facc
BC		 2774 /* NB: setup here so ath5k_rate_update is happy */
2775 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2776 ath5k_setcurmode(sc, AR5K_MODE_11A);
2777 else
2778 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2779
8a63facc
BC		 2780 /*
2781 * Allocate tx+rx descriptors and populate the lists.
2782 */
aeae4ac9 2783 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2784 if (ret) {
2785 ATH5K_ERR(sc, "can't allocate descriptors\n");
2786 goto err;
2787 }
fa1c114f 2788
8a63facc
BC		 2789 /*
2790 * Allocate hardware transmit queues: one queue for
2791 * beacon frames and one data queue for each QoS
2792 * priority. Note that hw functions handle resetting
2793 * these queues at the needed time.
2794 */
2795 ret = ath5k_beaconq_setup(ah);
2796 if (ret < 0) {
2797 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2798 goto err_desc;
2799 }
2800 sc->bhalq = ret;
2801 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2802 if (IS_ERR(sc->cabq)) {
2803 ATH5K_ERR(sc, "can't setup cab queue\n");
2804 ret = PTR_ERR(sc->cabq);
2805 goto err_bhal;
2806 }
fa1c114f 2807
22d8d9f8
BR		 2808 /* 5211 and 5212 usually support 10 queues but we better rely on the
2809 * capability information */
2810 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2811 /* This order matches mac80211's queue priority, so we can
2812 * directly use the mac80211 queue number without any mapping */
2813 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2814 if (IS_ERR(txq)) {
2815 ATH5K_ERR(sc, "can't setup xmit queue\n");
2816 ret = PTR_ERR(txq);
2817 goto err_queues;
2818 }
2819 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2820 if (IS_ERR(txq)) {
2821 ATH5K_ERR(sc, "can't setup xmit queue\n");
2822 ret = PTR_ERR(txq);
2823 goto err_queues;
2824 }
2825 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2826 if (IS_ERR(txq)) {
2827 ATH5K_ERR(sc, "can't setup xmit queue\n");
2828 ret = PTR_ERR(txq);
2829 goto err_queues;
2830 }
2831 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2832 if (IS_ERR(txq)) {
2833 ATH5K_ERR(sc, "can't setup xmit queue\n");
2834 ret = PTR_ERR(txq);
2835 goto err_queues;
2836 }
2837 hw->queues = 4;
2838 } else {
2839 /* older hardware (5210) can only support one data queue */
2840 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2841 if (IS_ERR(txq)) {
2842 ATH5K_ERR(sc, "can't setup xmit queue\n");
2843 ret = PTR_ERR(txq);
2844 goto err_queues;
2845 }
2846 hw->queues = 1;
2847 }
fa1c114f 2848
8a63facc
BC		 2849 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2850 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2851 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2852 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2853 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2854
8a63facc 2855 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2856 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2857
8a63facc
BC		 2858 ret = ath5k_eeprom_read_mac(ah, mac);
2859 if (ret) {
aeae4ac9 2860 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2861 goto err_queues;
e30eb4ab 2862 }
2bed03eb 2863
8a63facc 2864 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2865 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2866 /* All MAC address bits matter for ACKs */
62c58fb4 2867 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2868
2869 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2870 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2871 if (ret) {
2872 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2873 goto err_queues;
2874 }
2875
2876 ret = ieee80211_register_hw(hw);
2877 if (ret) {
2878 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2879 goto err_queues;
2880 }
2881
2882 if (!ath_is_world_regd(regulatory))
2883 regulatory_hint(hw->wiphy, regulatory->alpha2);
2884
2885 ath5k_init_leds(sc);
2886
2887 ath5k_sysfs_register(sc);
2888
2889 return 0;
2890err_queues:
2891 ath5k_txq_release(sc);
2892err_bhal:
2893 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2894err_desc:
aeae4ac9 2895 ath5k_desc_free(sc);
8a63facc
BC		 2896err:
2897 return ret;
2898}
2899
132b1c3e
FF		 2900void
2901ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2902{
132b1c3e 2903 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2904
2905 /*
2906 * NB: the order of these is important:
2907 * o call the 802.11 layer before detaching ath5k_hw to
2908 * ensure callbacks into the driver to delete global
2909 * key cache entries can be handled
2910 * o reclaim the tx queue data structures after calling
2911 * the 802.11 layer as we'll get called back to reclaim
2912 * node state and potentially want to use them
2913 * o to cleanup the tx queues the hal is called, so detach
2914 * it last
2915 * XXX: ??? detach ath5k_hw ???
2916 * Other than that, it's straightforward...
2917 */
132b1c3e 2918 ath5k_debug_finish_device(sc);
8a63facc 2919 ieee80211_unregister_hw(hw);
aeae4ac9 2920 ath5k_desc_free(sc);
8a63facc
BC		 2921 ath5k_txq_release(sc);
2922 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2923 ath5k_unregister_leds(sc);
2924
2925 ath5k_sysfs_unregister(sc);
2926 /*
2927 * NB: can't reclaim these until after ieee80211_ifdetach
2928 * returns because we'll get called back to reclaim node
2929 * state and potentially want to use them.
2930 */
132b1c3e
FF		 2931 ath5k_hw_deinit(sc->ah);
2932 free_irq(sc->irq, sc);
8a63facc
BC		 2933}
2934
cd2c5486
BR		 2935bool
2936ath_any_vif_assoc(struct ath5k_softc *sc)
b1ae1edf
BG		 2937{
2938 struct ath_vif_iter_data iter_data;
2939 iter_data.hw_macaddr = NULL;
2940 iter_data.any_assoc = false;
2941 iter_data.need_set_hw_addr = false;
2942 iter_data.found_active = true;
2943
2944 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
2945 &iter_data);
2946 return iter_data.any_assoc;
2947}
2948
cd2c5486 2949void
8a63facc
BC		 2950set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2951{
2952 struct ath5k_softc *sc = hw->priv;
2953 struct ath5k_hw *ah = sc->ah;
2954 u32 rfilt;
2955 rfilt = ath5k_hw_get_rx_filter(ah);
2956 if (enable)
2957 rfilt |= AR5K_RX_FILTER_BEACON;
2958 else
2959 rfilt &= ~AR5K_RX_FILTER_BEACON;
2960 ath5k_hw_set_rx_filter(ah, rfilt);
2961 sc->filter_flags = rfilt;
2962}
Linux kernel - Deliverables
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