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ath5k: Always free tx buffers before reset
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
62c58fb4 63#include "../debug.h"
fa1c114f 64
9ad9a26e 65static int modparam_nohwcrypt;
46802a4f 66module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 67MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 68
42639fcd 69static int modparam_all_channels;
46802a4f 70module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 71MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
72
fa1c114f
JS		 73/* Module info */
74MODULE_AUTHOR("Jiri Slaby");
75MODULE_AUTHOR("Nick Kossifidis");
76MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 79MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f 80
132b1c3e 81static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 82static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
83 bool skip_pcu);
8a63facc
BC		 84static int ath5k_beacon_update(struct ieee80211_hw *hw,
85 struct ieee80211_vif *vif);
86static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f 87
fa1c114f 88/* Known SREVs */
2c91108c 89static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 90#ifdef CONFIG_ATHEROS_AR231X
91 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
92 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
93 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
94 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
95 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
96 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
97 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
98#else
1bef016a
NK		 99 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
100 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
101 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
102 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
103 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
104 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
105 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
106 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
107 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
108 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
109 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
110 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
111 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
112 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
113 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
114 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
115 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
116 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 117#endif
1bef016a 118 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 119 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
120 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 121 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 122 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
123 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
124 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 125 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 128 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
129 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
130 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 131 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 133#ifdef CONFIG_ATHEROS_AR231X
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
136#endif
fa1c114f
JS		 137 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
138};
139
2c91108c 140static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 141 { .bitrate = 10,
142 .hw_value = ATH5K_RATE_CODE_1M, },
143 { .bitrate = 20,
144 .hw_value = ATH5K_RATE_CODE_2M,
145 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
146 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
147 { .bitrate = 55,
148 .hw_value = ATH5K_RATE_CODE_5_5M,
149 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
150 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
151 { .bitrate = 110,
152 .hw_value = ATH5K_RATE_CODE_11M,
153 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
155 { .bitrate = 60,
156 .hw_value = ATH5K_RATE_CODE_6M,
157 .flags = 0 },
158 { .bitrate = 90,
159 .hw_value = ATH5K_RATE_CODE_9M,
160 .flags = 0 },
161 { .bitrate = 120,
162 .hw_value = ATH5K_RATE_CODE_12M,
163 .flags = 0 },
164 { .bitrate = 180,
165 .hw_value = ATH5K_RATE_CODE_18M,
166 .flags = 0 },
167 { .bitrate = 240,
168 .hw_value = ATH5K_RATE_CODE_24M,
169 .flags = 0 },
170 { .bitrate = 360,
171 .hw_value = ATH5K_RATE_CODE_36M,
172 .flags = 0 },
173 { .bitrate = 480,
174 .hw_value = ATH5K_RATE_CODE_48M,
175 .flags = 0 },
176 { .bitrate = 540,
177 .hw_value = ATH5K_RATE_CODE_54M,
178 .flags = 0 },
179 /* XR missing */
180};
181
9e4e43f2 182static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 183 struct ath5k_buf *bf)
184{
185 BUG_ON(!bf);
186 if (!bf->skb)
187 return;
aeae4ac9
FF		 188 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
189 DMA_TO_DEVICE);
00482973 190 dev_kfree_skb_any(bf->skb);
fa1c114f 191 bf->skb = NULL;
39d63f2a
BR		 192 bf->skbaddr = 0;
193 bf->desc->ds_data = 0;
fa1c114f
JS		 194}
195
9e4e43f2 196static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 197 struct ath5k_buf *bf)
198{
cc861f74
LR		 199 struct ath5k_hw *ah = sc->ah;
200 struct ath_common *common = ath5k_hw_common(ah);
201
a6c8d375
FF		 202 BUG_ON(!bf);
203 if (!bf->skb)
204 return;
aeae4ac9
FF		 205 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
206 DMA_FROM_DEVICE);
a6c8d375
FF		 207 dev_kfree_skb_any(bf->skb);
208 bf->skb = NULL;
39d63f2a
BR		 209 bf->skbaddr = 0;
210 bf->desc->ds_data = 0;
a6c8d375
FF		 211}
212
213
fa1c114f
JS		 214static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
215{
216 u64 tsf = ath5k_hw_get_tsf64(ah);
217
218 if ((tsf & 0x7fff) < rstamp)
219 tsf -= 0x8000;
220
221 return (tsf & ~0x7fff) | rstamp;
222}
223
e5b046d8 224const char *
fa1c114f
JS		 225ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
226{
227 const char *name = "xxxxx";
228 unsigned int i;
229
230 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
231 if (srev_names[i].sr_type != type)
232 continue;
75d0edb8
NK		 233
234 if ((val & 0xf0) == srev_names[i].sr_val)
235 name = srev_names[i].sr_name;
236
237 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 238 name = srev_names[i].sr_name;
239 break;
240 }
241 }
242
243 return name;
244}
e5aa8474
LR		 245static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
246{
247 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
248 return ath5k_hw_reg_read(ah, reg_offset);
249}
250
251static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
252{
253 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
254 ath5k_hw_reg_write(ah, val, reg_offset);
255}
256
257static const struct ath_ops ath5k_common_ops = {
258 .read = ath5k_ioread32,
259 .write = ath5k_iowrite32,
260};
fa1c114f 261
8a63facc
BC		 262/***********************\
263* Driver Initialization *
264\***********************/
265
266static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 267{
8a63facc
BC		 268 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
269 struct ath5k_softc *sc = hw->priv;
270 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 271
8a63facc
BC		 272 return ath_reg_notifier_apply(wiphy, request, regulatory);
273}
6ccf15a1 274
8a63facc
BC		 275/********************\
276* Channel/mode setup *
277\********************/
fa1c114f 278
8a63facc
BC		 279/*
280 * Convert IEEE channel number to MHz frequency.
281 */
282static inline short
283ath5k_ieee2mhz(short chan)
284{
285 if (chan <= 14 || chan >= 27)
286 return ieee80211chan2mhz(chan);
287 else
288 return 2212 + chan * 20;
289}
fa1c114f 290
8a63facc
BC		 291/*
292 * Returns true for the channel numbers used without all_channels modparam.
293 */
294static bool ath5k_is_standard_channel(short chan)
295{
296 return ((chan <= 14) ||
297 /* UNII 1,2 */
298 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
299 /* midband */
300 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
301 /* UNII-3 */
302 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
303}
fa1c114f 304
8a63facc
BC		 305static unsigned int
306ath5k_copy_channels(struct ath5k_hw *ah,
307 struct ieee80211_channel *channels,
308 unsigned int mode,
309 unsigned int max)
310{
311 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f 312
8a63facc
BC		 313 if (!test_bit(mode, ah->ah_modes))
314 return 0;
fa1c114f 315
8a63facc
BC		 316 switch (mode) {
317 case AR5K_MODE_11A:
8a63facc
BC		 318 /* 1..220, but 2GHz frequencies are filtered by check_channel */
319 size = 220 ;
320 chfreq = CHANNEL_5GHZ;
321 break;
322 case AR5K_MODE_11B:
323 case AR5K_MODE_11G:
8a63facc
BC		 324 size = 26;
325 chfreq = CHANNEL_2GHZ;
326 break;
327 default:
328 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
329 return 0;
fa1c114f
JS		 330 }
331
8a63facc
BC		 332 for (i = 0, count = 0; i < size && max > 0; i++) {
333 ch = i + 1 ;
334 freq = ath5k_ieee2mhz(ch);
fa1c114f 335
8a63facc
BC		 336 /* Check if channel is supported by the chipset */
337 if (!ath5k_channel_ok(ah, freq, chfreq))
338 continue;
f59ac048 339
8a63facc
BC		 340 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
341 continue;
f59ac048 342
8a63facc
BC		 343 /* Write channel info and increment counter */
344 channels[count].center_freq = freq;
345 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
346 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
347 switch (mode) {
348 case AR5K_MODE_11A:
349 case AR5K_MODE_11G:
350 channels[count].hw_value = chfreq | CHANNEL_OFDM;
351 break;
8a63facc
BC		 352 case AR5K_MODE_11B:
353 channels[count].hw_value = CHANNEL_B;
354 }
fa1c114f 355
8a63facc
BC		 356 count++;
357 max--;
358 }
fa1c114f 359
8a63facc
BC		 360 return count;
361}
fa1c114f 362
8a63facc
BC		 363static void
364ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
365{
366 u8 i;
fa1c114f 367
8a63facc
BC		 368 for (i = 0; i < AR5K_MAX_RATES; i++)
369 sc->rate_idx[b->band][i] = -1;
fa1c114f 370
8a63facc
BC		 371 for (i = 0; i < b->n_bitrates; i++) {
372 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
373 if (b->bitrates[i].hw_value_short)
374 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 375 }
8a63facc 376}
fa1c114f 377
8a63facc
BC		 378static int
379ath5k_setup_bands(struct ieee80211_hw *hw)
380{
381 struct ath5k_softc *sc = hw->priv;
382 struct ath5k_hw *ah = sc->ah;
383 struct ieee80211_supported_band *sband;
384 int max_c, count_c = 0;
385 int i;
fa1c114f 386
8a63facc
BC		 387 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
388 max_c = ARRAY_SIZE(sc->channels);
db719718 389
8a63facc
BC		 390 /* 2GHz band */
391 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
392 sband->band = IEEE80211_BAND_2GHZ;
393 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 394
8a63facc
BC		 395 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
396 /* G mode */
397 memcpy(sband->bitrates, &ath5k_rates[0],
398 sizeof(struct ieee80211_rate) * 12);
399 sband->n_bitrates = 12;
2f7fe870 400
8a63facc
BC		 401 sband->channels = sc->channels;
402 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
403 AR5K_MODE_11G, max_c);
fa1c114f 404
8a63facc
BC		 405 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
406 count_c = sband->n_channels;
407 max_c -= count_c;
408 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
409 /* B mode */
410 memcpy(sband->bitrates, &ath5k_rates[0],
411 sizeof(struct ieee80211_rate) * 4);
412 sband->n_bitrates = 4;
fa1c114f 413
8a63facc
BC		 414 /* 5211 only supports B rates and uses 4bit rate codes
415 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
416 * fix them up here:
417 */
418 if (ah->ah_version == AR5K_AR5211) {
419 for (i = 0; i < 4; i++) {
420 sband->bitrates[i].hw_value =
421 sband->bitrates[i].hw_value & 0xF;
422 sband->bitrates[i].hw_value_short =
423 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 424 }
425 }
fa1c114f 426
8a63facc
BC		 427 sband->channels = sc->channels;
428 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
429 AR5K_MODE_11B, max_c);
fa1c114f 430
8a63facc
BC		 431 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
432 count_c = sband->n_channels;
433 max_c -= count_c;
434 }
435 ath5k_setup_rate_idx(sc, sband);
fa1c114f 436
8a63facc
BC		 437 /* 5GHz band, A mode */
438 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
439 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
440 sband->band = IEEE80211_BAND_5GHZ;
441 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 442
8a63facc
BC		 443 memcpy(sband->bitrates, &ath5k_rates[4],
444 sizeof(struct ieee80211_rate) * 8);
445 sband->n_bitrates = 8;
fa1c114f 446
8a63facc
BC		 447 sband->channels = &sc->channels[count_c];
448 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
449 AR5K_MODE_11A, max_c);
fa1c114f 450
8a63facc
BC		 451 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
452 }
453 ath5k_setup_rate_idx(sc, sband);
454
455 ath5k_debug_dump_bands(sc);
fa1c114f 456
fa1c114f
JS		 457 return 0;
458}
459
8a63facc
BC		 460/*
461 * Set/change channels. We always reset the chip.
462 * To accomplish this we must first cleanup any pending DMA,
463 * then restart stuff after a la ath5k_init.
464 *
465 * Called with sc->lock.
466 */
467static int
468ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
469{
470 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
471 "channel set, resetting (%u -> %u MHz)\n",
472 sc->curchan->center_freq, chan->center_freq);
473
8451d22d 474 /*
8a63facc
BC		 475 * To switch channels clear any pending DMA operations;
476 * wait long enough for the RX fifo to drain, reset the
477 * hardware at the new frequency, and then re-enable
478 * the relevant bits of the h/w.
8451d22d 479 */
8aec7af9 480 return ath5k_reset(sc, chan, true);
fa1c114f 481}
fa1c114f 482
8a63facc
BC		 483static void
484ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 485{
8a63facc 486 sc->curmode = mode;
f769c36b 487
8a63facc
BC		 488 if (mode == AR5K_MODE_11A) {
489 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
490 } else {
491 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
492 }
f769c36b
BC		 493}
494
b1ae1edf
BG		 495struct ath_vif_iter_data {
496 const u8 *hw_macaddr;
497 u8 mask[ETH_ALEN];
498 u8 active_mac[ETH_ALEN]; /* first active MAC */
499 bool need_set_hw_addr;
500 bool found_active;
501 bool any_assoc;
62c58fb4 502 enum nl80211_iftype opmode;
b1ae1edf
BG		 503};
504
505static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
506{
507 struct ath_vif_iter_data *iter_data = data;
508 int i;
62c58fb4 509 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 510
511 if (iter_data->hw_macaddr)
512 for (i = 0; i < ETH_ALEN; i++)
513 iter_data->mask[i] &=
514 ~(iter_data->hw_macaddr[i] ^ mac[i]);
515
516 if (!iter_data->found_active) {
517 iter_data->found_active = true;
518 memcpy(iter_data->active_mac, mac, ETH_ALEN);
519 }
520
521 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
522 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
523 iter_data->need_set_hw_addr = false;
524
525 if (!iter_data->any_assoc) {
b1ae1edf
BG		 526 if (avf->assoc)
527 iter_data->any_assoc = true;
528 }
62c58fb4
BG		 529
530 /* Calculate combined mode - when APs are active, operate in AP mode.
531 * Otherwise use the mode of the new interface. This can currently
532 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 533 * interfaces is allowed.
62c58fb4
BG		 534 */
535 if (avf->opmode == NL80211_IFTYPE_AP)
536 iter_data->opmode = NL80211_IFTYPE_AP;
537 else
538 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
539 iter_data->opmode = avf->opmode;
b1ae1edf
BG		 540}
541
14fb7c17
LR		 542static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
543 struct ieee80211_vif *vif)
b1ae1edf
BG		 544{
545 struct ath_common *common = ath5k_hw_common(sc->ah);
546 struct ath_vif_iter_data iter_data;
547
548 /*
549 * Use the hardware MAC address as reference, the hardware uses it
550 * together with the BSSID mask when matching addresses.
551 */
552 iter_data.hw_macaddr = common->macaddr;
553 memset(&iter_data.mask, 0xff, ETH_ALEN);
554 iter_data.found_active = false;
555 iter_data.need_set_hw_addr = true;
62c58fb4 556 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
b1ae1edf
BG		 557
558 if (vif)
559 ath_vif_iter(&iter_data, vif->addr, vif);
560
561 /* Get list of all active MAC addresses */
562 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
563 &iter_data);
564 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
565
62c58fb4
BG		 566 sc->opmode = iter_data.opmode;
567 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
568 /* Nothing active, default to station mode */
569 sc->opmode = NL80211_IFTYPE_STATION;
570
7afbb2f0
BG		 571 ath5k_hw_set_opmode(sc->ah, sc->opmode);
572 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
573 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 574
b1ae1edf
BG		 575 if (iter_data.need_set_hw_addr && iter_data.found_active)
576 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
577
62c58fb4
BG		 578 if (ath5k_hw_hasbssidmask(sc->ah))
579 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf
BG		 580}
581
8a63facc 582static void
b1ae1edf 583ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
fa1c114f 584{
fa1c114f 585 struct ath5k_hw *ah = sc->ah;
8a63facc 586 u32 rfilt;
fa1c114f 587
8a63facc
BC		 588 /* configure rx filter */
589 rfilt = sc->filter_flags;
590 ath5k_hw_set_rx_filter(ah, rfilt);
8a63facc 591 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
62c58fb4
BG		 592
593 ath5k_update_bssid_mask_and_opmode(sc, vif);
8a63facc 594}
fa1c114f 595
8a63facc
BC		 596static inline int
597ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
598{
599 int rix;
fa1c114f 600
8a63facc
BC		 601 /* return base rate on errors */
602 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
603 "hw_rix out of bounds: %x\n", hw_rix))
604 return 0;
605
606 rix = sc->rate_idx[sc->curband->band][hw_rix];
607 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
608 rix = 0;
609
610 return rix;
611}
612
613/***************\
614* Buffers setup *
615\***************/
616
617static
618struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
619{
620 struct ath_common *common = ath5k_hw_common(sc->ah);
621 struct sk_buff *skb;
fa1c114f
JS		 622
623 /*
8a63facc
BC		 624 * Allocate buffer with headroom_needed space for the
625 * fake physical layer header at the start.
fa1c114f 626 */
8a63facc
BC		 627 skb = ath_rxbuf_alloc(common,
628 common->rx_bufsize,
629 GFP_ATOMIC);
fa1c114f 630
8a63facc
BC		 631 if (!skb) {
632 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
633 common->rx_bufsize);
634 return NULL;
fa1c114f
JS		 635 }
636
aeae4ac9 637 *skb_addr = dma_map_single(sc->dev,
8a63facc 638 skb->data, common->rx_bufsize,
aeae4ac9
FF		 639 DMA_FROM_DEVICE);
640
641 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 642 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
643 dev_kfree_skb(skb);
644 return NULL;
0e149cf5 645 }
8a63facc
BC		 646 return skb;
647}
0e149cf5 648
8a63facc
BC		 649static int
650ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
651{
652 struct ath5k_hw *ah = sc->ah;
653 struct sk_buff *skb = bf->skb;
654 struct ath5k_desc *ds;
655 int ret;
fa1c114f 656
8a63facc
BC		 657 if (!skb) {
658 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
659 if (!skb)
660 return -ENOMEM;
661 bf->skb = skb;
f769c36b
BC		 662 }
663
8a63facc
BC		 664 /*
665 * Setup descriptors. For receive we always terminate
666 * the descriptor list with a self-linked entry so we'll
667 * not get overrun under high load (as can happen with a
668 * 5212 when ANI processing enables PHY error frames).
669 *
670 * To ensure the last descriptor is self-linked we create
671 * each descriptor as self-linked and add it to the end. As
672 * each additional descriptor is added the previous self-linked
673 * entry is "fixed" naturally. This should be safe even
674 * if DMA is happening. When processing RX interrupts we
675 * never remove/process the last, self-linked, entry on the
676 * descriptor list. This ensures the hardware always has
677 * someplace to write a new frame.
678 */
679 ds = bf->desc;
680 ds->ds_link = bf->daddr; /* link to self */
681 ds->ds_data = bf->skbaddr;
682 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 683 if (ret) {
8a63facc
BC		 684 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
685 return ret;
fa1c114f
JS		 686 }
687
8a63facc
BC		 688 if (sc->rxlink != NULL)
689 *sc->rxlink = bf->daddr;
690 sc->rxlink = &ds->ds_link;
fa1c114f 691 return 0;
fa1c114f
JS		 692}
693
8a63facc 694static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 695{
8a63facc
BC		 696 struct ieee80211_hdr *hdr;
697 enum ath5k_pkt_type htype;
698 __le16 fc;
fa1c114f 699
8a63facc
BC		 700 hdr = (struct ieee80211_hdr *)skb->data;
701 fc = hdr->frame_control;
fa1c114f 702
8a63facc
BC		 703 if (ieee80211_is_beacon(fc))
704 htype = AR5K_PKT_TYPE_BEACON;
705 else if (ieee80211_is_probe_resp(fc))
706 htype = AR5K_PKT_TYPE_PROBE_RESP;
707 else if (ieee80211_is_atim(fc))
708 htype = AR5K_PKT_TYPE_ATIM;
709 else if (ieee80211_is_pspoll(fc))
710 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 711 else
8a63facc 712 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 713
8a63facc 714 return htype;
42639fcd
BC		 715}
716
8a63facc
BC		 717static int
718ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
719 struct ath5k_txq *txq, int padsize)
fa1c114f 720{
8a63facc
BC		 721 struct ath5k_hw *ah = sc->ah;
722 struct ath5k_desc *ds = bf->desc;
723 struct sk_buff *skb = bf->skb;
724 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
725 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
726 struct ieee80211_rate *rate;
727 unsigned int mrr_rate[3], mrr_tries[3];
728 int i, ret;
729 u16 hw_rate;
730 u16 cts_rate = 0;
731 u16 duration = 0;
732 u8 rc_flags;
fa1c114f 733
8a63facc 734 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 735
8a63facc 736 /* XXX endianness */
aeae4ac9
FF		 737 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
738 DMA_TO_DEVICE);
fa1c114f 739
8a63facc 740 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 741 if (!rate) {
742 ret = -EINVAL;
743 goto err_unmap;
744 }
fa1c114f 745
8a63facc
BC		 746 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
747 flags |= AR5K_TXDESC_NOACK;
fa1c114f 748
8a63facc
BC		 749 rc_flags = info->control.rates[0].flags;
750 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
751 rate->hw_value_short : rate->hw_value;
42639fcd 752
8a63facc
BC		 753 pktlen = skb->len;
754
755 /* FIXME: If we are in g mode and rate is a CCK rate
756 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
757 * from tx power (value is in dB units already) */
758 if (info->control.hw_key) {
759 keyidx = info->control.hw_key->hw_key_idx;
760 pktlen += info->control.hw_key->icv_len;
761 }
762 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
763 flags |= AR5K_TXDESC_RTSENA;
764 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
765 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 766 info->control.vif, pktlen, info));
8a63facc
BC		 767 }
768 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
769 flags |= AR5K_TXDESC_CTSENA;
770 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
771 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 772 info->control.vif, pktlen, info));
8a63facc
BC		 773 }
774 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
775 ieee80211_get_hdrlen_from_skb(skb), padsize,
776 get_hw_packet_type(skb),
777 (sc->power_level * 2),
778 hw_rate,
779 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
780 cts_rate, duration);
781 if (ret)
782 goto err_unmap;
783
784 memset(mrr_rate, 0, sizeof(mrr_rate));
785 memset(mrr_tries, 0, sizeof(mrr_tries));
786 for (i = 0; i < 3; i++) {
787 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
788 if (!rate)
400ec45a 789 break;
fa1c114f 790
8a63facc
BC		 791 mrr_rate[i] = rate->hw_value;
792 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 793 }
794
8a63facc
BC		 795 ath5k_hw_setup_mrr_tx_desc(ah, ds,
796 mrr_rate[0], mrr_tries[0],
797 mrr_rate[1], mrr_tries[1],
798 mrr_rate[2], mrr_tries[2]);
fa1c114f 799
8a63facc
BC		 800 ds->ds_link = 0;
801 ds->ds_data = bf->skbaddr;
63266a65 802
8a63facc
BC		 803 spin_lock_bh(&txq->lock);
804 list_add_tail(&bf->list, &txq->q);
925e0b06 805 txq->txq_len++;
8a63facc
BC		 806 if (txq->link == NULL) /* is this first packet? */
807 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
808 else /* no, so only link it */
809 *txq->link = bf->daddr;
63266a65 810
8a63facc
BC		 811 txq->link = &ds->ds_link;
812 ath5k_hw_start_tx_dma(ah, txq->qnum);
813 mmiowb();
814 spin_unlock_bh(&txq->lock);
815
816 return 0;
817err_unmap:
aeae4ac9 818 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 819 return ret;
63266a65
BR		 820}
821
8a63facc
BC		 822/*******************\
823* Descriptors setup *
824\*******************/
825
d8ee398d 826static int
aeae4ac9 827ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 828{
8a63facc
BC		 829 struct ath5k_desc *ds;
830 struct ath5k_buf *bf;
831 dma_addr_t da;
832 unsigned int i;
833 int ret;
d8ee398d 834
8a63facc
BC		 835 /* allocate descriptors */
836 sc->desc_len = sizeof(struct ath5k_desc) *
837 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 838
839 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
840 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 841 if (sc->desc == NULL) {
842 ATH5K_ERR(sc, "can't allocate descriptors\n");
843 ret = -ENOMEM;
844 goto err;
845 }
846 ds = sc->desc;
847 da = sc->desc_daddr;
848 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
849 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 850
8a63facc
BC		 851 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
852 sizeof(struct ath5k_buf), GFP_KERNEL);
853 if (bf == NULL) {
854 ATH5K_ERR(sc, "can't allocate bufptr\n");
855 ret = -ENOMEM;
856 goto err_free;
857 }
858 sc->bufptr = bf;
fa1c114f 859
8a63facc
BC		 860 INIT_LIST_HEAD(&sc->rxbuf);
861 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
862 bf->desc = ds;
863 bf->daddr = da;
864 list_add_tail(&bf->list, &sc->rxbuf);
865 }
d8ee398d 866
8a63facc
BC		 867 INIT_LIST_HEAD(&sc->txbuf);
868 sc->txbuf_len = ATH_TXBUF;
869 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
870 da += sizeof(*ds)) {
871 bf->desc = ds;
872 bf->daddr = da;
873 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 874 }
875
b1ae1edf
BG		 876 /* beacon buffers */
877 INIT_LIST_HEAD(&sc->bcbuf);
878 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
879 bf->desc = ds;
880 bf->daddr = da;
881 list_add_tail(&bf->list, &sc->bcbuf);
882 }
fa1c114f 883
8a63facc
BC		 884 return 0;
885err_free:
aeae4ac9 886 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 887err:
888 sc->desc = NULL;
889 return ret;
890}
fa1c114f 891
8a63facc 892static void
aeae4ac9 893ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 894{
895 struct ath5k_buf *bf;
d8ee398d 896
8a63facc
BC		 897 list_for_each_entry(bf, &sc->txbuf, list)
898 ath5k_txbuf_free_skb(sc, bf);
899 list_for_each_entry(bf, &sc->rxbuf, list)
900 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 901 list_for_each_entry(bf, &sc->bcbuf, list)
902 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 903
8a63facc 904 /* Free memory associated with all descriptors */
aeae4ac9 905 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 906 sc->desc = NULL;
907 sc->desc_daddr = 0;
d8ee398d 908
8a63facc
BC		 909 kfree(sc->bufptr);
910 sc->bufptr = NULL;
fa1c114f
JS		 911}
912
8a63facc
BC		 913
914/**************\
915* Queues setup *
916\**************/
917
918static struct ath5k_txq *
919ath5k_txq_setup(struct ath5k_softc *sc,
920 int qtype, int subtype)
fa1c114f 921{
8a63facc
BC		 922 struct ath5k_hw *ah = sc->ah;
923 struct ath5k_txq *txq;
924 struct ath5k_txq_info qi = {
925 .tqi_subtype = subtype,
de8af455
BR		 926 /* XXX: default values not correct for B and XR channels,
927 * but who cares? */
928 .tqi_aifs = AR5K_TUNE_AIFS,
929 .tqi_cw_min = AR5K_TUNE_CWMIN,
930 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 931 };
932 int qnum;
d8ee398d 933
e30eb4ab 934 /*
8a63facc
BC		 935 * Enable interrupts only for EOL and DESC conditions.
936 * We mark tx descriptors to receive a DESC interrupt
937 * when a tx queue gets deep; otherwise we wait for the
938 * EOL to reap descriptors. Note that this is done to
939 * reduce interrupt load and this only defers reaping
940 * descriptors, never transmitting frames. Aside from
941 * reducing interrupts this also permits more concurrency.
942 * The only potential downside is if the tx queue backs
943 * up in which case the top half of the kernel may backup
944 * due to a lack of tx descriptors.
e30eb4ab 945 */
8a63facc
BC		 946 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
947 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
948 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
949 if (qnum < 0) {
950 /*
951 * NB: don't print a message, this happens
952 * normally on parts with too few tx queues
953 */
954 return ERR_PTR(qnum);
955 }
956 if (qnum >= ARRAY_SIZE(sc->txqs)) {
957 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
958 qnum, ARRAY_SIZE(sc->txqs));
959 ath5k_hw_release_tx_queue(ah, qnum);
960 return ERR_PTR(-EINVAL);
961 }
962 txq = &sc->txqs[qnum];
963 if (!txq->setup) {
964 txq->qnum = qnum;
965 txq->link = NULL;
966 INIT_LIST_HEAD(&txq->q);
967 spin_lock_init(&txq->lock);
968 txq->setup = true;
925e0b06 969 txq->txq_len = 0;
4edd761f 970 txq->txq_poll_mark = false;
923e5b3d 971 txq->txq_stuck = 0;
8a63facc
BC		 972 }
973 return &sc->txqs[qnum];
fa1c114f
JS		 974}
975
8a63facc
BC		 976static int
977ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 978{
8a63facc 979 struct ath5k_txq_info qi = {
de8af455
BR		 980 /* XXX: default values not correct for B and XR channels,
981 * but who cares? */
982 .tqi_aifs = AR5K_TUNE_AIFS,
983 .tqi_cw_min = AR5K_TUNE_CWMIN,
984 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 985 /* NB: for dynamic turbo, don't enable any other interrupts */
986 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
987 };
d8ee398d 988
8a63facc 989 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 990}
991
8a63facc
BC		 992static int
993ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 994{
995 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 996 struct ath5k_txq_info qi;
997 int ret;
fa1c114f 998
8a63facc
BC		 999 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1000 if (ret)
1001 goto err;
fa1c114f 1002
8a63facc
BC		 1003 if (sc->opmode == NL80211_IFTYPE_AP ||
1004 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1005 /*
1006 * Always burst out beacon and CAB traffic
1007 * (aifs = cwmin = cwmax = 0)
1008 */
1009 qi.tqi_aifs = 0;
1010 qi.tqi_cw_min = 0;
1011 qi.tqi_cw_max = 0;
1012 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1013 /*
1014 * Adhoc mode; backoff between 0 and (2 * cw_min).
1015 */
1016 qi.tqi_aifs = 0;
1017 qi.tqi_cw_min = 0;
de8af455 1018 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 1019 }
fa1c114f 1020
8a63facc
BC		 1021 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1022 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1023 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1024
8a63facc
BC		 1025 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1026 if (ret) {
1027 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1028 "hardware queue!\n", __func__);
1029 goto err;
1030 }
1031 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1032 if (ret)
1033 goto err;
b7266047 1034
8a63facc
BC		 1035 /* reconfigure cabq with ready time to 80% of beacon_interval */
1036 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1037 if (ret)
1038 goto err;
b7266047 1039
8a63facc
BC		 1040 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1041 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1042 if (ret)
1043 goto err;
b7266047 1044
8a63facc
BC		 1045 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1046err:
1047 return ret;
d8ee398d
LR		 1048}
1049
80dac9ee
NK		 1050/**
1051 * ath5k_drain_tx_buffs - Empty tx buffers
1052 *
1053 * @sc The &struct ath5k_softc
1054 *
1055 * Empty tx buffers from all queues in preparation
1056 * of a reset or during shutdown.
1057 *
1058 * NB: this assumes output has been stopped and
1059 * we do not need to block ath5k_tx_tasklet
1060 */
8a63facc 1061static void
80dac9ee 1062ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1063{
80dac9ee 1064 struct ath5k_txq *txq;
8a63facc 1065 struct ath5k_buf *bf, *bf0;
80dac9ee 1066 int i;
b6ea0356 1067
80dac9ee
NK		 1068 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1069 if (sc->txqs[i].setup) {
1070 txq = &sc->txqs[i];
1071 spin_lock_bh(&txq->lock);
1072 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1073 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1074
80dac9ee 1075 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1076
80dac9ee
NK		 1077 spin_lock_bh(&sc->txbuflock);
1078 list_move_tail(&bf->list, &sc->txbuf);
1079 sc->txbuf_len++;
1080 txq->txq_len--;
1081 spin_unlock_bh(&sc->txbuflock);
8a63facc 1082 }
80dac9ee
NK		 1083 txq->link = NULL;
1084 txq->txq_poll_mark = false;
1085 spin_unlock_bh(&txq->lock);
1086 }
0452d4a5 1087 }
fa1c114f
JS		 1088}
1089
8a63facc
BC		 1090static void
1091ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1092{
8a63facc
BC		 1093 struct ath5k_txq *txq = sc->txqs;
1094 unsigned int i;
2ac2927a 1095
8a63facc
BC		 1096 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1097 if (txq->setup) {
1098 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1099 txq->setup = false;
1100 }
1101}
2ac2927a 1102
2ac2927a 1103
8a63facc
BC		 1104/*************\
1105* RX Handling *
1106\*************/
2ac2927a 1107
8a63facc
BC		 1108/*
1109 * Enable the receive h/w following a reset.
1110 */
fa1c114f 1111static int
8a63facc 1112ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1113{
1114 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1115 struct ath_common *common = ath5k_hw_common(ah);
1116 struct ath5k_buf *bf;
1117 int ret;
fa1c114f 1118
8a63facc 1119 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1120
8a63facc
BC		 1121 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1122 common->cachelsz, common->rx_bufsize);
2f7fe870 1123
8a63facc
BC		 1124 spin_lock_bh(&sc->rxbuflock);
1125 sc->rxlink = NULL;
1126 list_for_each_entry(bf, &sc->rxbuf, list) {
1127 ret = ath5k_rxbuf_setup(sc, bf);
1128 if (ret != 0) {
1129 spin_unlock_bh(&sc->rxbuflock);
1130 goto err;
1131 }
2f7fe870 1132 }
8a63facc
BC		 1133 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1134 ath5k_hw_set_rxdp(ah, bf->daddr);
1135 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1136
8a63facc 1137 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
b1ae1edf 1138 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
8a63facc 1139 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1140
1141 return 0;
8a63facc 1142err:
fa1c114f
JS		 1143 return ret;
1144}
1145
8a63facc 1146/*
80dac9ee
NK		 1147 * Disable the receive logic on PCU (DRU)
1148 * In preparation for a shutdown.
1149 *
1150 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1151 * does.
8a63facc
BC		 1152 */
1153static void
1154ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1155{
8a63facc 1156 struct ath5k_hw *ah = sc->ah;
fa1c114f 1157
8a63facc 1158 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1159 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1160
8a63facc
BC		 1161 ath5k_debug_printrxbuffs(sc, ah);
1162}
fa1c114f 1163
8a63facc
BC		 1164static unsigned int
1165ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1166 struct ath5k_rx_status *rs)
1167{
1168 struct ath5k_hw *ah = sc->ah;
1169 struct ath_common *common = ath5k_hw_common(ah);
1170 struct ieee80211_hdr *hdr = (void *)skb->data;
1171 unsigned int keyix, hlen;
fa1c114f 1172
8a63facc
BC		 1173 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1174 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1175 return RX_FLAG_DECRYPTED;
fa1c114f 1176
8a63facc
BC		 1177 /* Apparently when a default key is used to decrypt the packet
1178 the hw does not set the index used to decrypt. In such cases
1179 get the index from the packet. */
1180 hlen = ieee80211_hdrlen(hdr->frame_control);
1181 if (ieee80211_has_protected(hdr->frame_control) &&
1182 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1183 skb->len >= hlen + 4) {
1184 keyix = skb->data[hlen + 3] >> 6;
1185
1186 if (test_bit(keyix, common->keymap))
1187 return RX_FLAG_DECRYPTED;
1188 }
fa1c114f
JS		 1189
1190 return 0;
fa1c114f
JS		 1191}
1192
8a63facc 1193
fa1c114f 1194static void
8a63facc
BC		 1195ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1196 struct ieee80211_rx_status *rxs)
fa1c114f 1197{
8a63facc
BC		 1198 struct ath_common *common = ath5k_hw_common(sc->ah);
1199 u64 tsf, bc_tstamp;
1200 u32 hw_tu;
1201 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1202
8a63facc
BC		 1203 if (ieee80211_is_beacon(mgmt->frame_control) &&
1204 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1205 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1206 /*
1207 * Received an IBSS beacon with the same BSSID. Hardware *must*
1208 * have updated the local TSF. We have to work around various
1209 * hardware bugs, though...
1210 */
1211 tsf = ath5k_hw_get_tsf64(sc->ah);
1212 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1213 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1214
8a63facc
BC		 1215 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1216 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1217 (unsigned long long)bc_tstamp,
1218 (unsigned long long)rxs->mactime,
1219 (unsigned long long)(rxs->mactime - bc_tstamp),
1220 (unsigned long long)tsf);
fa1c114f 1221
8a63facc
BC		 1222 /*
1223 * Sometimes the HW will give us a wrong tstamp in the rx
1224 * status, causing the timestamp extension to go wrong.
1225 * (This seems to happen especially with beacon frames bigger
1226 * than 78 byte (incl. FCS))
1227 * But we know that the receive timestamp must be later than the
1228 * timestamp of the beacon since HW must have synced to that.
1229 *
1230 * NOTE: here we assume mactime to be after the frame was
1231 * received, not like mac80211 which defines it at the start.
1232 */
1233 if (bc_tstamp > rxs->mactime) {
1234 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1235 "fixing mactime from %llx to %llx\n",
1236 (unsigned long long)rxs->mactime,
1237 (unsigned long long)tsf);
1238 rxs->mactime = tsf;
1239 }
fa1c114f 1240
8a63facc
BC		 1241 /*
1242 * Local TSF might have moved higher than our beacon timers,
1243 * in that case we have to update them to continue sending
1244 * beacons. This also takes care of synchronizing beacon sending
1245 * times with other stations.
1246 */
1247 if (hw_tu >= sc->nexttbtt)
1248 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1249
1250 /* Check if the beacon timers are still correct, because a TSF
1251 * update might have created a window between them - for a
1252 * longer description see the comment of this function: */
1253 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1254 ath5k_beacon_update_timers(sc, bc_tstamp);
1255 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1256 "fixed beacon timers after beacon receive\n");
1257 }
8a63facc
BC		 1258 }
1259}
fa1c114f 1260
8a63facc
BC		 1261static void
1262ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1263{
1264 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1265 struct ath5k_hw *ah = sc->ah;
1266 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1267
8a63facc
BC		 1268 /* only beacons from our BSSID */
1269 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1270 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1271 return;
fa1c114f 1272
eef39bef 1273 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1274
8a63facc
BC		 1275 /* in IBSS mode we should keep RSSI statistics per neighbour */
1276 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1277}
fa1c114f 1278
8a63facc
BC		 1279/*
1280 * Compute padding position. skb must contain an IEEE 802.11 frame
1281 */
1282static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1283{
8a63facc
BC		 1284 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1285 __le16 frame_control = hdr->frame_control;
1286 int padpos = 24;
fa1c114f 1287
8a63facc
BC		 1288 if (ieee80211_has_a4(frame_control)) {
1289 padpos += ETH_ALEN;
fa1c114f 1290 }
8a63facc
BC		 1291 if (ieee80211_is_data_qos(frame_control)) {
1292 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1293 }
8a63facc
BC		 1294
1295 return padpos;
fa1c114f
JS		 1296}
1297
8a63facc
BC		 1298/*
1299 * This function expects an 802.11 frame and returns the number of
1300 * bytes added, or -1 if we don't have enough header room.
1301 */
1302static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1303{
8a63facc
BC		 1304 int padpos = ath5k_common_padpos(skb);
1305 int padsize = padpos & 3;
fa1c114f 1306
8a63facc 1307 if (padsize && skb->len>padpos) {
fa1c114f 1308
8a63facc
BC		 1309 if (skb_headroom(skb) < padsize)
1310 return -1;
fa1c114f 1311
8a63facc
BC		 1312 skb_push(skb, padsize);
1313 memmove(skb->data, skb->data+padsize, padpos);
1314 return padsize;
1315 }
a951ae21 1316
8a63facc
BC		 1317 return 0;
1318}
fa1c114f 1319
8a63facc
BC		 1320/*
1321 * The MAC header is padded to have 32-bit boundary if the
1322 * packet payload is non-zero. The general calculation for
1323 * padsize would take into account odd header lengths:
1324 * padsize = 4 - (hdrlen & 3); however, since only
1325 * even-length headers are used, padding can only be 0 or 2
1326 * bytes and we can optimize this a bit. We must not try to
1327 * remove padding from short control frames that do not have a
1328 * payload.
1329 *
1330 * This function expects an 802.11 frame and returns the number of
1331 * bytes removed.
1332 */
1333static int ath5k_remove_padding(struct sk_buff *skb)
1334{
1335 int padpos = ath5k_common_padpos(skb);
1336 int padsize = padpos & 3;
6d91e1d8 1337
8a63facc
BC		 1338 if (padsize && skb->len>=padpos+padsize) {
1339 memmove(skb->data + padsize, skb->data, padpos);
1340 skb_pull(skb, padsize);
1341 return padsize;
fa1c114f 1342 }
a951ae21 1343
8a63facc 1344 return 0;
fa1c114f
JS		 1345}
1346
1347static void
8a63facc
BC		 1348ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1349 struct ath5k_rx_status *rs)
fa1c114f 1350{
8a63facc
BC		 1351 struct ieee80211_rx_status *rxs;
1352
1353 ath5k_remove_padding(skb);
1354
1355 rxs = IEEE80211_SKB_RXCB(skb);
1356
1357 rxs->flag = 0;
1358 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1359 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1360
1361 /*
8a63facc
BC		 1362 * always extend the mac timestamp, since this information is
1363 * also needed for proper IBSS merging.
1364 *
1365 * XXX: it might be too late to do it here, since rs_tstamp is
1366 * 15bit only. that means TSF extension has to be done within
1367 * 32768usec (about 32ms). it might be necessary to move this to
1368 * the interrupt handler, like it is done in madwifi.
1369 *
1370 * Unfortunately we don't know when the hardware takes the rx
1371 * timestamp (beginning of phy frame, data frame, end of rx?).
1372 * The only thing we know is that it is hardware specific...
1373 * On AR5213 it seems the rx timestamp is at the end of the
1374 * frame, but i'm not sure.
1375 *
1376 * NOTE: mac80211 defines mactime at the beginning of the first
1377 * data symbol. Since we don't have any time references it's
1378 * impossible to comply to that. This affects IBSS merge only
1379 * right now, so it's not too bad...
fa1c114f 1380 */
8a63facc
BC		 1381 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1382 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1383
8a63facc
BC		 1384 rxs->freq = sc->curchan->center_freq;
1385 rxs->band = sc->curband->band;
fa1c114f 1386
8a63facc 1387 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1388
8a63facc 1389 rxs->antenna = rs->rs_antenna;
fa1c114f 1390
8a63facc
BC		 1391 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1392 sc->stats.antenna_rx[rs->rs_antenna]++;
1393 else
1394 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1395
8a63facc
BC		 1396 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1397 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1398
8a63facc
BC		 1399 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1400 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1401 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1402
8a63facc 1403 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1404
8a63facc 1405 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1406
8a63facc
BC		 1407 /* check beacons in IBSS mode */
1408 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1409 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1410
8a63facc
BC		 1411 ieee80211_rx(sc->hw, skb);
1412}
fa1c114f 1413
8a63facc
BC		 1414/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1415 *
1416 * Check if we want to further process this frame or not. Also update
1417 * statistics. Return true if we want this frame, false if not.
fa1c114f 1418 */
8a63facc
BC		 1419static bool
1420ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1421{
8a63facc 1422 sc->stats.rx_all_count++;
b72acddb 1423 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1424
8a63facc
BC		 1425 if (unlikely(rs->rs_status)) {
1426 if (rs->rs_status & AR5K_RXERR_CRC)
1427 sc->stats.rxerr_crc++;
1428 if (rs->rs_status & AR5K_RXERR_FIFO)
1429 sc->stats.rxerr_fifo++;
1430 if (rs->rs_status & AR5K_RXERR_PHY) {
1431 sc->stats.rxerr_phy++;
1432 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1433 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1434 return false;
1435 }
1436 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1437 /*
1438 * Decrypt error. If the error occurred
1439 * because there was no hardware key, then
1440 * let the frame through so the upper layers
1441 * can process it. This is necessary for 5210
1442 * parts which have no way to setup a ``clear''
1443 * key cache entry.
1444 *
1445 * XXX do key cache faulting
1446 */
1447 sc->stats.rxerr_decrypt++;
1448 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1449 !(rs->rs_status & AR5K_RXERR_CRC))
1450 return true;
1451 }
1452 if (rs->rs_status & AR5K_RXERR_MIC) {
1453 sc->stats.rxerr_mic++;
1454 return true;
fa1c114f 1455 }
fa1c114f 1456
8a63facc
BC		 1457 /* reject any frames with non-crypto errors */
1458 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1459 return false;
1460 }
fa1c114f 1461
8a63facc
BC		 1462 if (unlikely(rs->rs_more)) {
1463 sc->stats.rxerr_jumbo++;
1464 return false;
1465 }
1466 return true;
fa1c114f
JS		 1467}
1468
fa1c114f 1469static void
8a63facc 1470ath5k_tasklet_rx(unsigned long data)
fa1c114f 1471{
8a63facc
BC		 1472 struct ath5k_rx_status rs = {};
1473 struct sk_buff *skb, *next_skb;
1474 dma_addr_t next_skb_addr;
1475 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1476 struct ath5k_hw *ah = sc->ah;
1477 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1478 struct ath5k_buf *bf;
1479 struct ath5k_desc *ds;
1480 int ret;
fa1c114f 1481
8a63facc
BC		 1482 spin_lock(&sc->rxbuflock);
1483 if (list_empty(&sc->rxbuf)) {
1484 ATH5K_WARN(sc, "empty rx buf pool\n");
1485 goto unlock;
1486 }
1487 do {
1488 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1489 BUG_ON(bf->skb == NULL);
1490 skb = bf->skb;
1491 ds = bf->desc;
fa1c114f 1492
8a63facc
BC		 1493 /* bail if HW is still using self-linked descriptor */
1494 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1495 break;
fa1c114f 1496
8a63facc
BC		 1497 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1498 if (unlikely(ret == -EINPROGRESS))
1499 break;
1500 else if (unlikely(ret)) {
1501 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1502 sc->stats.rxerr_proc++;
1503 break;
1504 }
fa1c114f 1505
8a63facc
BC		 1506 if (ath5k_receive_frame_ok(sc, &rs)) {
1507 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1508
8a63facc
BC		 1509 /*
1510 * If we can't replace bf->skb with a new skb under
1511 * memory pressure, just skip this packet
1512 */
1513 if (!next_skb)
1514 goto next;
036cd1ec 1515
aeae4ac9 1516 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1517 common->rx_bufsize,
aeae4ac9 1518 DMA_FROM_DEVICE);
036cd1ec 1519
8a63facc 1520 skb_put(skb, rs.rs_datalen);
6ba81c2c 1521
8a63facc 1522 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1523
8a63facc
BC		 1524 bf->skb = next_skb;
1525 bf->skbaddr = next_skb_addr;
036cd1ec 1526 }
8a63facc
BC		 1527next:
1528 list_move_tail(&bf->list, &sc->rxbuf);
1529 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1530unlock:
1531 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1532}
1533
b4ea449d 1534
8a63facc
BC		 1535/*************\
1536* TX Handling *
1537\*************/
b4ea449d 1538
8a63facc
BC		 1539static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1540 struct ath5k_txq *txq)
1541{
1542 struct ath5k_softc *sc = hw->priv;
1543 struct ath5k_buf *bf;
1544 unsigned long flags;
1545 int padsize;
b4ea449d 1546
8a63facc 1547 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
b4ea449d 1548
8a63facc
BC		 1549 /*
1550 * The hardware expects the header padded to 4 byte boundaries.
1551 * If this is not the case, we add the padding after the header.
1552 */
1553 padsize = ath5k_add_padding(skb);
1554 if (padsize < 0) {
1555 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1556 " headroom to pad");
1557 goto drop_packet;
1558 }
8127fbdc 1559
925e0b06
BR		 1560 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1561 ieee80211_stop_queue(hw, txq->qnum);
1562
8a63facc
BC		 1563 spin_lock_irqsave(&sc->txbuflock, flags);
1564 if (list_empty(&sc->txbuf)) {
1565 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1566 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1567 ieee80211_stop_queues(hw);
8a63facc 1568 goto drop_packet;
8127fbdc 1569 }
8a63facc
BC		 1570 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1571 list_del(&bf->list);
1572 sc->txbuf_len--;
1573 if (list_empty(&sc->txbuf))
1574 ieee80211_stop_queues(hw);
1575 spin_unlock_irqrestore(&sc->txbuflock, flags);
1576
1577 bf->skb = skb;
1578
1579 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1580 bf->skb = NULL;
1581 spin_lock_irqsave(&sc->txbuflock, flags);
1582 list_add_tail(&bf->list, &sc->txbuf);
1583 sc->txbuf_len++;
1584 spin_unlock_irqrestore(&sc->txbuflock, flags);
1585 goto drop_packet;
8127fbdc 1586 }
8a63facc 1587 return NETDEV_TX_OK;
8127fbdc 1588
8a63facc
BC		 1589drop_packet:
1590 dev_kfree_skb_any(skb);
1591 return NETDEV_TX_OK;
8127fbdc
BP		 1592}
1593
1440401e
BR		 1594static void
1595ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1596 struct ath5k_tx_status *ts)
1597{
1598 struct ieee80211_tx_info *info;
1599 int i;
1600
1601 sc->stats.tx_all_count++;
b72acddb 1602 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1603 info = IEEE80211_SKB_CB(skb);
1604
1605 ieee80211_tx_info_clear_status(info);
1606 for (i = 0; i < 4; i++) {
1607 struct ieee80211_tx_rate *r =
1608 &info->status.rates[i];
1609
1610 if (ts->ts_rate[i]) {
1611 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1612 r->count = ts->ts_retry[i];
1613 } else {
1614 r->idx = -1;
1615 r->count = 0;
1616 }
1617 }
1618
1619 /* count the successful attempt as well */
1620 info->status.rates[ts->ts_final_idx].count++;
1621
1622 if (unlikely(ts->ts_status)) {
1623 sc->stats.ack_fail++;
1624 if (ts->ts_status & AR5K_TXERR_FILT) {
1625 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1626 sc->stats.txerr_filt++;
1627 }
1628 if (ts->ts_status & AR5K_TXERR_XRETRY)
1629 sc->stats.txerr_retry++;
1630 if (ts->ts_status & AR5K_TXERR_FIFO)
1631 sc->stats.txerr_fifo++;
1632 } else {
1633 info->flags |= IEEE80211_TX_STAT_ACK;
1634 info->status.ack_signal = ts->ts_rssi;
1635 }
1636
1637 /*
1638 * Remove MAC header padding before giving the frame
1639 * back to mac80211.
1640 */
1641 ath5k_remove_padding(skb);
1642
1643 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1644 sc->stats.antenna_tx[ts->ts_antenna]++;
1645 else
1646 sc->stats.antenna_tx[0]++; /* invalid */
1647
1648 ieee80211_tx_status(sc->hw, skb);
1649}
8a63facc
BC		 1650
1651static void
1652ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1653{
8a63facc
BC		 1654 struct ath5k_tx_status ts = {};
1655 struct ath5k_buf *bf, *bf0;
1656 struct ath5k_desc *ds;
1657 struct sk_buff *skb;
1440401e 1658 int ret;
8127fbdc 1659
8a63facc
BC		 1660 spin_lock(&txq->lock);
1661 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1662
1663 txq->txq_poll_mark = false;
1664
1665 /* skb might already have been processed last time. */
1666 if (bf->skb != NULL) {
1667 ds = bf->desc;
1668
1669 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1670 if (unlikely(ret == -EINPROGRESS))
1671 break;
1672 else if (unlikely(ret)) {
1673 ATH5K_ERR(sc,
1674 "error %d while processing "
1675 "queue %u\n", ret, txq->qnum);
1676 break;
1677 }
1678
1679 skb = bf->skb;
1680 bf->skb = NULL;
aeae4ac9
FF		 1681
1682 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1683 DMA_TO_DEVICE);
23413296
BR		 1684 ath5k_tx_frame_completed(sc, skb, &ts);
1685 }
8127fbdc 1686
8a63facc
BC		 1687 /*
1688 * It's possible that the hardware can say the buffer is
1689 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1690 * host memory and moved on.
1691 * Always keep the last descriptor to avoid HW races...
8a63facc 1692 */
23413296
BR		 1693 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1694 spin_lock(&sc->txbuflock);
1695 list_move_tail(&bf->list, &sc->txbuf);
1696 sc->txbuf_len++;
1697 txq->txq_len--;
1698 spin_unlock(&sc->txbuflock);
8a63facc 1699 }
fa1c114f 1700 }
fa1c114f 1701 spin_unlock(&txq->lock);
4198a8d0 1702 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1703 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1704}
1705
1706static void
1707ath5k_tasklet_tx(unsigned long data)
1708{
8784d2ee 1709 int i;
fa1c114f
JS		 1710 struct ath5k_softc *sc = (void *)data;
1711
8784d2ee
BC		 1712 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1713 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1714 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1715}
1716
1717
fa1c114f
JS		 1718/*****************\
1719* Beacon handling *
1720\*****************/
1721
1722/*
1723 * Setup the beacon frame for transmit.
1724 */
1725static int
e039fa4a 1726ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1727{
1728 struct sk_buff *skb = bf->skb;
a888d52d 1729 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1730 struct ath5k_hw *ah = sc->ah;
1731 struct ath5k_desc *ds;
2bed03eb
NK		 1732 int ret = 0;
1733 u8 antenna;
fa1c114f 1734 u32 flags;
8127fbdc 1735 const int padsize = 0;
fa1c114f 1736
aeae4ac9
FF		 1737 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1738 DMA_TO_DEVICE);
fa1c114f
JS		 1739 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1740 "skbaddr %llx\n", skb, skb->data, skb->len,
1741 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1742
1743 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1744 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1745 return -EIO;
1746 }
1747
1748 ds = bf->desc;
2bed03eb 1749 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1750
1751 flags = AR5K_TXDESC_NOACK;
05c914fe 1752 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1753 ds->ds_link = bf->daddr; /* self-linked */
1754 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1755 } else
fa1c114f 1756 ds->ds_link = 0;
2bed03eb
NK		 1757
1758 /*
1759 * If we use multiple antennas on AP and use
1760 * the Sectored AP scenario, switch antenna every
1761 * 4 beacons to make sure everybody hears our AP.
1762 * When a client tries to associate, hw will keep
1763 * track of the tx antenna to be used for this client
1764 * automaticaly, based on ACKed packets.
1765 *
1766 * Note: AP still listens and transmits RTS on the
1767 * default antenna which is supposed to be an omni.
1768 *
1769 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1770 * multiple antennas (1 omni -- the default -- and 14
1771 * sectors), so if we choose to actually support this
1772 * mode, we need to allow the user to set how many antennas
1773 * we have and tweak the code below to send beacons
1774 * on all of them.
2bed03eb
NK		 1775 */
1776 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1777 antenna = sc->bsent & 4 ? 2 : 1;
1778
fa1c114f 1779
8f655dde
NK		 1780 /* FIXME: If we are in g mode and rate is a CCK rate
1781 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1782 * from tx power (value is in dB units already) */
fa1c114f 1783 ds->ds_data = bf->skbaddr;
281c56dd 1784 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1785 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1786 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1787 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1788 1, AR5K_TXKEYIX_INVALID,
400ec45a 1789 antenna, flags, 0, 0);
fa1c114f
JS		 1790 if (ret)
1791 goto err_unmap;
1792
1793 return 0;
1794err_unmap:
aeae4ac9 1795 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1796 return ret;
1797}
1798
8a63facc
BC		 1799/*
1800 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1801 * this is called only once at config_bss time, for AP we do it every
1802 * SWBA interrupt so that the TIM will reflect buffered frames.
1803 *
1804 * Called with the beacon lock.
1805 */
1806static int
1807ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1808{
1809 int ret;
1810 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1811 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1812 struct sk_buff *skb;
1813
1814 if (WARN_ON(!vif)) {
1815 ret = -EINVAL;
1816 goto out;
1817 }
1818
1819 skb = ieee80211_beacon_get(hw, vif);
1820
1821 if (!skb) {
1822 ret = -ENOMEM;
1823 goto out;
1824 }
1825
1826 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1827
b1ae1edf
BG		 1828 ath5k_txbuf_free_skb(sc, avf->bbuf);
1829 avf->bbuf->skb = skb;
1830 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1831 if (ret)
b1ae1edf 1832 avf->bbuf->skb = NULL;
8a63facc
BC		 1833out:
1834 return ret;
1835}
1836
fa1c114f
JS		 1837/*
1838 * Transmit a beacon frame at SWBA. Dynamic updates to the
1839 * frame contents are done as needed and the slot time is
1840 * also adjusted based on current state.
1841 *
5faaff74
BC		 1842 * This is called from software irq context (beacontq tasklets)
1843 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1844 */
1845static void
1846ath5k_beacon_send(struct ath5k_softc *sc)
1847{
fa1c114f 1848 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1849 struct ieee80211_vif *vif;
1850 struct ath5k_vif *avf;
1851 struct ath5k_buf *bf;
cec8db23 1852 struct sk_buff *skb;
fa1c114f 1853
be9b7259 1854 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1855
fa1c114f
JS		 1856 /*
1857 * Check if the previous beacon has gone out. If
a180a130 1858 * not, don't don't try to post another: skip this
fa1c114f
JS		 1859 * period and wait for the next. Missed beacons
1860 * indicate a problem and should not occur. If we
1861 * miss too many consecutive beacons reset the device.
1862 */
1863 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1864 sc->bmisscount++;
be9b7259 1865 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1866 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1867 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1868 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1869 "stuck beacon time (%u missed)\n",
1870 sc->bmisscount);
8d67a031
BR		 1871 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1872 "stuck beacon, resetting\n");
5faaff74 1873 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1874 }
1875 return;
1876 }
1877 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1878 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1879 "resume beacon xmit after %u misses\n",
1880 sc->bmisscount);
1881 sc->bmisscount = 0;
1882 }
1883
b1ae1edf
BG		 1884 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1885 u64 tsf = ath5k_hw_get_tsf64(ah);
1886 u32 tsftu = TSF_TO_TU(tsf);
1887 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1888 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1889 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1890 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1891 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1892 } else /* only one interface */
1893 vif = sc->bslot[0];
1894
1895 if (!vif)
1896 return;
1897
1898 avf = (void *)vif->drv_priv;
1899 bf = avf->bbuf;
1900 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1901 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1902 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1903 return;
1904 }
1905
fa1c114f
JS		 1906 /*
1907 * Stop any current dma and put the new frame on the queue.
1908 * This should never fail since we check above that no frames
1909 * are still pending on the queue.
1910 */
14fae2d4 1911 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1912 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1913 /* NB: hw still stops DMA, so proceed */
1914 }
fa1c114f 1915
1071db86
BC		 1916 /* refresh the beacon for AP mode */
1917 if (sc->opmode == NL80211_IFTYPE_AP)
b1ae1edf 1918 ath5k_beacon_update(sc->hw, vif);
1071db86 1919
c6e387a2
NK		 1920 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1921 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1922 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1923 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1924
b1ae1edf 1925 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1926 while (skb) {
1927 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1928 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1929 }
1930
fa1c114f
JS		 1931 sc->bsent++;
1932}
1933
9804b98d
BR		 1934/**
1935 * ath5k_beacon_update_timers - update beacon timers
1936 *
1937 * @sc: struct ath5k_softc pointer we are operating on
1938 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1939 * beacon timer update based on the current HW TSF.
1940 *
1941 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1942 * of a received beacon or the current local hardware TSF and write it to the
1943 * beacon timer registers.
1944 *
1945 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1946 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1947 * when we otherwise know we have to update the timers, but we keep it in this
1948 * function to have it all together in one place.
1949 */
fa1c114f 1950static void
9804b98d 1951ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1952{
1953 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1954 u32 nexttbtt, intval, hw_tu, bc_tu;
1955 u64 hw_tsf;
fa1c114f
JS		 1956
1957 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1958 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1959 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1960 if (intval < 15)
1961 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1962 intval);
1963 }
fa1c114f
JS		 1964 if (WARN_ON(!intval))
1965 return;
1966
9804b98d
BR		 1967 /* beacon TSF converted to TU */
1968 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1969
9804b98d
BR		 1970 /* current TSF converted to TU */
1971 hw_tsf = ath5k_hw_get_tsf64(ah);
1972 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1973
11f21df3
BR		 1974#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1975 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1976 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1977 * configuration we need to make sure it is bigger than that. */
1978
9804b98d
BR		 1979 if (bc_tsf == -1) {
1980 /*
1981 * no beacons received, called internally.
1982 * just need to refresh timers based on HW TSF.
1983 */
1984 nexttbtt = roundup(hw_tu + FUDGE, intval);
1985 } else if (bc_tsf == 0) {
1986 /*
1987 * no beacon received, probably called by ath5k_reset_tsf().
1988 * reset TSF to start with 0.
1989 */
1990 nexttbtt = intval;
1991 intval |= AR5K_BEACON_RESET_TSF;
1992 } else if (bc_tsf > hw_tsf) {
1993 /*
1994 * beacon received, SW merge happend but HW TSF not yet updated.
1995 * not possible to reconfigure timers yet, but next time we
1996 * receive a beacon with the same BSSID, the hardware will
1997 * automatically update the TSF and then we need to reconfigure
1998 * the timers.
1999 */
2000 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2001 "need to wait for HW TSF sync\n");
2002 return;
2003 } else {
2004 /*
2005 * most important case for beacon synchronization between STA.
2006 *
2007 * beacon received and HW TSF has been already updated by HW.
2008 * update next TBTT based on the TSF of the beacon, but make
2009 * sure it is ahead of our local TSF timer.
2010 */
2011 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2012 }
2013#undef FUDGE
fa1c114f 2014
036cd1ec
BR		 2015 sc->nexttbtt = nexttbtt;
2016
fa1c114f 2017 intval |= AR5K_BEACON_ENA;
fa1c114f 2018 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2019
2020 /*
2021 * debugging output last in order to preserve the time critical aspect
2022 * of this function
2023 */
2024 if (bc_tsf == -1)
2025 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2026 "reconfigured timers based on HW TSF\n");
2027 else if (bc_tsf == 0)
2028 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2029 "reset HW TSF and timers\n");
2030 else
2031 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2032 "updated timers based on beacon TSF\n");
2033
2034 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2035 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2036 (unsigned long long) bc_tsf,
2037 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2038 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2039 intval & AR5K_BEACON_PERIOD,
2040 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2041 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2042}
2043
036cd1ec
BR		 2044/**
2045 * ath5k_beacon_config - Configure the beacon queues and interrupts
2046 *
2047 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2048 *
036cd1ec 2049 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2050 * interrupts to detect TSF updates only.
fa1c114f
JS		 2051 */
2052static void
2053ath5k_beacon_config(struct ath5k_softc *sc)
2054{
2055 struct ath5k_hw *ah = sc->ah;
b5f03956 2056 unsigned long flags;
fa1c114f 2057
21800491 2058 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2059 sc->bmisscount = 0;
dc1968e7 2060 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2061
21800491 2062 if (sc->enable_beacon) {
fa1c114f 2063 /*
036cd1ec
BR		 2064 * In IBSS mode we use a self-linked tx descriptor and let the
2065 * hardware send the beacons automatically. We have to load it
fa1c114f 2066 * only once here.
036cd1ec 2067 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2068 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2069 */
2070 ath5k_beaconq_config(sc);
fa1c114f 2071
036cd1ec
BR		 2072 sc->imask |= AR5K_INT_SWBA;
2073
da966bca 2074 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2075 if (ath5k_hw_hasveol(ah))
da966bca 2076 ath5k_beacon_send(sc);
da966bca
JS		 2077 } else
2078 ath5k_beacon_update_timers(sc, -1);
21800491 2079 } else {
14fae2d4 2080 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2081 }
fa1c114f 2082
c6e387a2 2083 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2084 mmiowb();
2085 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2086}
2087
428cbd4f
NK		 2088static void ath5k_tasklet_beacon(unsigned long data)
2089{
2090 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2091
2092 /*
2093 * Software beacon alert--time to send a beacon.
2094 *
2095 * In IBSS mode we use this interrupt just to
2096 * keep track of the next TBTT (target beacon
2097 * transmission time) in order to detect wether
2098 * automatic TSF updates happened.
2099 */
2100 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2101 /* XXX: only if VEOL suppported */
2102 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2103 sc->nexttbtt += sc->bintval;
2104 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2105 "SWBA nexttbtt: %x hw_tu: %x "
2106 "TSF: %llx\n",
2107 sc->nexttbtt,
2108 TSF_TO_TU(tsf),
2109 (unsigned long long) tsf);
2110 } else {
2111 spin_lock(&sc->block);
2112 ath5k_beacon_send(sc);
2113 spin_unlock(&sc->block);
2114 }
2115}
2116
fa1c114f
JS		 2117
2118/********************\
2119* Interrupt handling *
2120\********************/
2121
6a8a3f6b
BR		 2122static void
2123ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2124{
2111ac0d
BR		 2125 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2126 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2127 /* run ANI only when full calibration is not active */
2128 ah->ah_cal_next_ani = jiffies +
2129 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2130 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2131
2132 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2133 ah->ah_cal_next_full = jiffies +
2134 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2135 tasklet_schedule(&ah->ah_sc->calib);
2136 }
2137 /* we could use SWI to generate enough interrupts to meet our
2138 * calibration interval requirements, if necessary:
2139 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2140}
2141
132b1c3e 2142irqreturn_t
fa1c114f
JS		 2143ath5k_intr(int irq, void *dev_id)
2144{
2145 struct ath5k_softc *sc = dev_id;
2146 struct ath5k_hw *ah = sc->ah;
2147 enum ath5k_int status;
2148 unsigned int counter = 1000;
2149
2150 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2151 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2152 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2153 return IRQ_NONE;
2154
2155 do {
fa1c114f
JS		 2156 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2157 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2158 status, sc->imask);
fa1c114f
JS		 2159 if (unlikely(status & AR5K_INT_FATAL)) {
2160 /*
2161 * Fatal errors are unrecoverable.
2162 * Typically these are caused by DMA errors.
2163 */
8d67a031
BR		 2164 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2165 "fatal int, resetting\n");
5faaff74 2166 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2167 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2168 /*
2169 * Receive buffers are full. Either the bus is busy or
2170 * the CPU is not fast enough to process all received
2171 * frames.
2172 * Older chipsets need a reset to come out of this
2173 * condition, but we treat it as RX for newer chips.
2174 * We don't know exactly which versions need a reset -
2175 * this guess is copied from the HAL.
2176 */
2177 sc->stats.rxorn_intr++;
8d67a031
BR		 2178 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2179 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2180 "rx overrun, resetting\n");
5faaff74 2181 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2182 }
87d77c4e
BR		 2183 else
2184 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2185 } else {
2186 if (status & AR5K_INT_SWBA) {
56d2ac76 2187 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2188 }
2189 if (status & AR5K_INT_RXEOL) {
2190 /*
2191 * NB: the hardware should re-read the link when
2192 * RXE bit is written, but it doesn't work at
2193 * least on older hardware revs.
2194 */
b3f194e5 2195 sc->stats.rxeol_intr++;
fa1c114f
JS		 2196 }
2197 if (status & AR5K_INT_TXURN) {
2198 /* bump tx trigger level */
2199 ath5k_hw_update_tx_triglevel(ah, true);
2200 }
4c674c60 2201 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2202 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2203 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2204 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2205 tasklet_schedule(&sc->txtq);
2206 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2207 /* TODO */
fa1c114f
JS		 2208 }
2209 if (status & AR5K_INT_MIB) {
2111ac0d 2210 sc->stats.mib_intr++;
495391d7 2211 ath5k_hw_update_mib_counters(ah);
2111ac0d 2212 ath5k_ani_mib_intr(ah);
fa1c114f 2213 }
e6a3b616 2214 if (status & AR5K_INT_GPIO)
e6a3b616 2215 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2216
fa1c114f 2217 }
4cebb34c
FF		 2218
2219 if (ath5k_get_bus_type(ah) == ATH_AHB)
2220 break;
2221
2516baa6 2222 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2223
2224 if (unlikely(!counter))
2225 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2226
6a8a3f6b 2227 ath5k_intr_calibration_poll(ah);
6e220662 2228
fa1c114f
JS		 2229 return IRQ_HANDLED;
2230}
2231
fa1c114f
JS		 2232/*
2233 * Periodically recalibrate the PHY to account
2234 * for temperature/environment changes.
2235 */
2236static void
6e220662 2237ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2238{
2239 struct ath5k_softc *sc = (void *)data;
2240 struct ath5k_hw *ah = sc->ah;
2241
6e220662 2242 /* Only full calibration for now */
e65e1d77 2243 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2244
fa1c114f 2245 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2246 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2247 sc->curchan->hw_value);
fa1c114f 2248
6f3b414a 2249 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2250 /*
2251 * Rfgain is out of bounds, reset the chip
2252 * to load new gain values.
2253 */
2254 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2255 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2256 }
2257 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2258 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2259 ieee80211_frequency_to_channel(
2260 sc->curchan->center_freq));
fa1c114f 2261
0e8e02dd 2262 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2263 * doesn't.
2264 * TODO: We should stop TX here, so that it doesn't interfere.
2265 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2266 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2267 ah->ah_cal_next_nf = jiffies +
2268 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2269 ath5k_hw_update_noise_floor(ah);
afe86286 2270 }
6e220662 2271
e65e1d77 2272 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2273}
2274
2275
2111ac0d
BR		 2276static void
2277ath5k_tasklet_ani(unsigned long data)
2278{
2279 struct ath5k_softc *sc = (void *)data;
2280 struct ath5k_hw *ah = sc->ah;
2281
2282 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2283 ath5k_ani_calibration(ah);
2284 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2285}
2286
2287
4edd761f
BR		 2288static void
2289ath5k_tx_complete_poll_work(struct work_struct *work)
2290{
2291 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2292 tx_complete_work.work);
2293 struct ath5k_txq *txq;
2294 int i;
2295 bool needreset = false;
2296
2297 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2298 if (sc->txqs[i].setup) {
2299 txq = &sc->txqs[i];
2300 spin_lock_bh(&txq->lock);
23413296 2301 if (txq->txq_len > 1) {
4edd761f
BR		 2302 if (txq->txq_poll_mark) {
2303 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2304 "TX queue stuck %d\n",
2305 txq->qnum);
2306 needreset = true;
923e5b3d 2307 txq->txq_stuck++;
4edd761f
BR		 2308 spin_unlock_bh(&txq->lock);
2309 break;
2310 } else {
2311 txq->txq_poll_mark = true;
2312 }
2313 }
2314 spin_unlock_bh(&txq->lock);
2315 }
2316 }
2317
2318 if (needreset) {
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2320 "TX queues stuck, resetting\n");
8aec7af9 2321 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2322 }
2323
2324 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2325 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2326}
2327
2328
8a63facc
BC		 2329/*************************\
2330* Initialization routines *
2331\*************************/
fa1c114f 2332
132b1c3e
FF		 2333int
2334ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2335{
2336 struct ieee80211_hw *hw = sc->hw;
2337 struct ath_common *common;
2338 int ret;
2339 int csz;
2340
2341 /* Initialize driver private data */
2342 SET_IEEE80211_DEV(hw, sc->dev);
2343 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2344 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2345 IEEE80211_HW_SIGNAL_DBM;
2346
2347 hw->wiphy->interface_modes =
2348 BIT(NL80211_IFTYPE_AP) |
2349 BIT(NL80211_IFTYPE_STATION) |
2350 BIT(NL80211_IFTYPE_ADHOC) |
2351 BIT(NL80211_IFTYPE_MESH_POINT);
2352
2353 hw->extra_tx_headroom = 2;
2354 hw->channel_change_time = 5000;
2355
2356 /*
2357 * Mark the device as detached to avoid processing
2358 * interrupts until setup is complete.
2359 */
2360 __set_bit(ATH_STAT_INVALID, sc->status);
2361
2362 sc->opmode = NL80211_IFTYPE_STATION;
2363 sc->bintval = 1000;
2364 mutex_init(&sc->lock);
2365 spin_lock_init(&sc->rxbuflock);
2366 spin_lock_init(&sc->txbuflock);
2367 spin_lock_init(&sc->block);
2368
2369
2370 /* Setup interrupt handler */
2371 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2372 if (ret) {
2373 ATH5K_ERR(sc, "request_irq failed\n");
2374 goto err;
2375 }
2376
2377 /* If we passed the test, malloc an ath5k_hw struct */
2378 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2379 if (!sc->ah) {
2380 ret = -ENOMEM;
2381 ATH5K_ERR(sc, "out of memory\n");
2382 goto err_irq;
2383 }
2384
2385 sc->ah->ah_sc = sc;
2386 sc->ah->ah_iobase = sc->iobase;
2387 common = ath5k_hw_common(sc->ah);
2388 common->ops = &ath5k_common_ops;
2389 common->bus_ops = bus_ops;
2390 common->ah = sc->ah;
2391 common->hw = hw;
2392 common->priv = sc;
2393
2394 /*
2395 * Cache line size is used to size and align various
2396 * structures used to communicate with the hardware.
2397 */
2398 ath5k_read_cachesize(common, &csz);
2399 common->cachelsz = csz << 2; /* convert to bytes */
2400
2401 spin_lock_init(&common->cc_lock);
2402
2403 /* Initialize device */
2404 ret = ath5k_hw_init(sc);
2405 if (ret)
2406 goto err_free_ah;
2407
2408 /* set up multi-rate retry capabilities */
2409 if (sc->ah->ah_version == AR5K_AR5212) {
2410 hw->max_rates = 4;
2411 hw->max_rate_tries = 11;
2412 }
2413
2414 hw->vif_data_size = sizeof(struct ath5k_vif);
2415
2416 /* Finish private driver data initialization */
2417 ret = ath5k_init(hw);
2418 if (ret)
2419 goto err_ah;
2420
2421 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2422 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2423 sc->ah->ah_mac_srev,
2424 sc->ah->ah_phy_revision);
2425
2426 if (!sc->ah->ah_single_chip) {
2427 /* Single chip radio (!RF5111) */
2428 if (sc->ah->ah_radio_5ghz_revision &&
2429 !sc->ah->ah_radio_2ghz_revision) {
2430 /* No 5GHz support -> report 2GHz radio */
2431 if (!test_bit(AR5K_MODE_11A,
2432 sc->ah->ah_capabilities.cap_mode)) {
2433 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2434 ath5k_chip_name(AR5K_VERSION_RAD,
2435 sc->ah->ah_radio_5ghz_revision),
2436 sc->ah->ah_radio_5ghz_revision);
2437 /* No 2GHz support (5110 and some
2438 * 5Ghz only cards) -> report 5Ghz radio */
2439 } else if (!test_bit(AR5K_MODE_11B,
2440 sc->ah->ah_capabilities.cap_mode)) {
2441 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2442 ath5k_chip_name(AR5K_VERSION_RAD,
2443 sc->ah->ah_radio_5ghz_revision),
2444 sc->ah->ah_radio_5ghz_revision);
2445 /* Multiband radio */
2446 } else {
2447 ATH5K_INFO(sc, "RF%s multiband radio found"
2448 " (0x%x)\n",
2449 ath5k_chip_name(AR5K_VERSION_RAD,
2450 sc->ah->ah_radio_5ghz_revision),
2451 sc->ah->ah_radio_5ghz_revision);
2452 }
2453 }
2454 /* Multi chip radio (RF5111 - RF2111) ->
2455 * report both 2GHz/5GHz radios */
2456 else if (sc->ah->ah_radio_5ghz_revision &&
2457 sc->ah->ah_radio_2ghz_revision){
2458 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2459 ath5k_chip_name(AR5K_VERSION_RAD,
2460 sc->ah->ah_radio_5ghz_revision),
2461 sc->ah->ah_radio_5ghz_revision);
2462 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2463 ath5k_chip_name(AR5K_VERSION_RAD,
2464 sc->ah->ah_radio_2ghz_revision),
2465 sc->ah->ah_radio_2ghz_revision);
2466 }
2467 }
2468
2469 ath5k_debug_init_device(sc);
2470
2471 /* ready to process interrupts */
2472 __clear_bit(ATH_STAT_INVALID, sc->status);
2473
2474 return 0;
2475err_ah:
2476 ath5k_hw_deinit(sc->ah);
2477err_free_ah:
2478 kfree(sc->ah);
2479err_irq:
2480 free_irq(sc->irq, sc);
2481err:
2482 return ret;
2483}
2484
fa1c114f 2485static int
8a63facc 2486ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2487{
8a63facc 2488 struct ath5k_hw *ah = sc->ah;
cec8db23 2489
8a63facc
BC		 2490 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2491 test_bit(ATH_STAT_INVALID, sc->status));
2492
2493 /*
2494 * Shutdown the hardware and driver:
2495 * stop output from above
2496 * disable interrupts
2497 * turn off timers
2498 * turn off the radio
2499 * clear transmit machinery
2500 * clear receive machinery
2501 * drain and release tx queues
2502 * reclaim beacon resources
2503 * power down hardware
2504 *
2505 * Note that some of this work is not possible if the
2506 * hardware is gone (invalid).
2507 */
2508 ieee80211_stop_queues(sc->hw);
2509
2510 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2511 ath5k_led_off(sc);
2512 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2513 synchronize_irq(sc->irq);
8a63facc 2514 ath5k_rx_stop(sc);
80dac9ee
NK		 2515 ath5k_hw_dma_stop(ah);
2516 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2517 ath5k_hw_phy_disable(ah);
2518 }
2519
2520 return 0;
cec8db23
BC		 2521}
2522
8a63facc 2523static int
132b1c3e 2524ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2525{
8a63facc
BC		 2526 struct ath5k_hw *ah = sc->ah;
2527 struct ath_common *common = ath5k_hw_common(ah);
2528 int ret, i;
fa1c114f 2529
8a63facc
BC		 2530 mutex_lock(&sc->lock);
2531
2532 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2533
fa1c114f 2534 /*
8a63facc
BC		 2535 * Stop anything previously setup. This is safe
2536 * no matter this is the first time through or not.
fa1c114f 2537 */
8a63facc 2538 ath5k_stop_locked(sc);
fa1c114f 2539
8a63facc
BC		 2540 /*
2541 * The basic interface to setting the hardware in a good
2542 * state is ``reset''. On return the hardware is known to
2543 * be powered up and with interrupts disabled. This must
2544 * be followed by initialization of the appropriate bits
2545 * and then setup of the interrupt mask.
2546 */
2547 sc->curchan = sc->hw->conf.channel;
2548 sc->curband = &sc->sbands[sc->curchan->band];
2549 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2550 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2551 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2552
8aec7af9 2553 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2554 if (ret)
2555 goto done;
fa1c114f 2556
8a63facc
BC		 2557 ath5k_rfkill_hw_start(ah);
2558
2559 /*
2560 * Reset the key cache since some parts do not reset the
2561 * contents on initial power up or resume from suspend.
2562 */
2563 for (i = 0; i < common->keymax; i++)
2564 ath_hw_keyreset(common, (u16) i);
2565
61cde037
NK		 2566 /* Use higher rates for acks instead of base
2567 * rate */
2568 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2569
2570 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2571 sc->bslot[i] = NULL;
2572
8a63facc
BC		 2573 ret = 0;
2574done:
2575 mmiowb();
2576 mutex_unlock(&sc->lock);
4edd761f
BR		 2577
2578 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2579 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2580
8a63facc
BC		 2581 return ret;
2582}
2583
2584static void stop_tasklets(struct ath5k_softc *sc)
2585{
2586 tasklet_kill(&sc->rxtq);
2587 tasklet_kill(&sc->txtq);
2588 tasklet_kill(&sc->calib);
2589 tasklet_kill(&sc->beacontq);
2590 tasklet_kill(&sc->ani_tasklet);
2591}
2592
2593/*
2594 * Stop the device, grabbing the top-level lock to protect
2595 * against concurrent entry through ath5k_init (which can happen
2596 * if another thread does a system call and the thread doing the
2597 * stop is preempted).
2598 */
2599static int
2600ath5k_stop_hw(struct ath5k_softc *sc)
2601{
2602 int ret;
2603
2604 mutex_lock(&sc->lock);
2605 ret = ath5k_stop_locked(sc);
2606 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2607 /*
2608 * Don't set the card in full sleep mode!
2609 *
2610 * a) When the device is in this state it must be carefully
2611 * woken up or references to registers in the PCI clock
2612 * domain may freeze the bus (and system). This varies
2613 * by chip and is mostly an issue with newer parts
2614 * (madwifi sources mentioned srev >= 0x78) that go to
2615 * sleep more quickly.
2616 *
2617 * b) On older chips full sleep results a weird behaviour
2618 * during wakeup. I tested various cards with srev < 0x78
2619 * and they don't wake up after module reload, a second
2620 * module reload is needed to bring the card up again.
2621 *
2622 * Until we figure out what's going on don't enable
2623 * full chip reset on any chip (this is what Legacy HAL
2624 * and Sam's HAL do anyway). Instead Perform a full reset
2625 * on the device (same as initial state after attach) and
2626 * leave it idle (keep MAC/BB on warm reset) */
2627 ret = ath5k_hw_on_hold(sc->ah);
2628
2629 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2630 "putting device to sleep\n");
fa1c114f
JS		 2631 }
2632
8a63facc
BC		 2633 mmiowb();
2634 mutex_unlock(&sc->lock);
2635
2636 stop_tasklets(sc);
2637
4edd761f
BR		 2638 cancel_delayed_work_sync(&sc->tx_complete_work);
2639
8a63facc
BC		 2640 ath5k_rfkill_hw_stop(sc->ah);
2641
2642 return ret;
fa1c114f
JS		 2643}
2644
209d889b
BC		 2645/*
2646 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2647 * and change to the given channel.
5faaff74
BC		 2648 *
2649 * This should be called with sc->lock.
209d889b 2650 */
fa1c114f 2651static int
8aec7af9
NK		 2652ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2653 bool skip_pcu)
fa1c114f 2654{
fa1c114f
JS		 2655 struct ath5k_hw *ah = sc->ah;
2656 int ret;
2657
2658 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2659
450464de 2660 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2661 synchronize_irq(sc->irq);
450464de
BC		 2662 stop_tasklets(sc);
2663
19252ecb
NK		 2664 /* We are going to empty hw queues
2665 * so we should also free any remaining
2666 * tx buffers */
2667 ath5k_drain_tx_buffs(sc);
209d889b 2668 if (chan) {
209d889b
BC		 2669 sc->curchan = chan;
2670 sc->curband = &sc->sbands[chan->band];
d7dc1003 2671 }
8aec7af9
NK		 2672 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2673 skip_pcu);
d7dc1003 2674 if (ret) {
fa1c114f
JS		 2675 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2676 goto err;
2677 }
d7dc1003 2678
fa1c114f 2679 ret = ath5k_rx_start(sc);
d7dc1003 2680 if (ret) {
fa1c114f
JS		 2681 ATH5K_ERR(sc, "can't start recv logic\n");
2682 goto err;
2683 }
d7dc1003 2684
2111ac0d
BR		 2685 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2686
ac559526
BR		 2687 ah->ah_cal_next_full = jiffies;
2688 ah->ah_cal_next_ani = jiffies;
afe86286 2689 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2690 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2691
fa1c114f 2692 /*
d7dc1003
JS		 2693 * Change channels and update the h/w rate map if we're switching;
2694 * e.g. 11a to 11b/g.
2695 *
2696 * We may be doing a reset in response to an ioctl that changes the
2697 * channel so update any state that might change as a result.
fa1c114f
JS		 2698 *
2699 * XXX needed?
2700 */
2701/* ath5k_chan_change(sc, c); */
fa1c114f 2702
d7dc1003
JS		 2703 ath5k_beacon_config(sc);
2704 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2705
397f385b
BR		 2706 ieee80211_wake_queues(sc->hw);
2707
fa1c114f
JS		 2708 return 0;
2709err:
2710 return ret;
2711}
2712
5faaff74
BC		 2713static void ath5k_reset_work(struct work_struct *work)
2714{
2715 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2716 reset_work);
2717
2718 mutex_lock(&sc->lock);
8aec7af9 2719 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2720 mutex_unlock(&sc->lock);
2721}
2722
8a63facc 2723static int
132b1c3e 2724ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2725{
132b1c3e 2726
fa1c114f 2727 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2728 struct ath5k_hw *ah = sc->ah;
2729 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2730 struct ath5k_txq *txq;
8a63facc 2731 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2732 int ret;
2733
fa1c114f 2734
8a63facc
BC		 2735 /*
2736 * Check if the MAC has multi-rate retry support.
2737 * We do this by trying to setup a fake extended
2738 * descriptor. MACs that don't have support will
2739 * return false w/o doing anything. MACs that do
2740 * support it will return true w/o doing anything.
2741 */
2742 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2743
8a63facc
BC		 2744 if (ret < 0)
2745 goto err;
2746 if (ret > 0)
2747 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2748
8a63facc
BC		 2749 /*
2750 * Collect the channel list. The 802.11 layer
2751 * is resposible for filtering this list based
2752 * on settings like the phy mode and regulatory
2753 * domain restrictions.
2754 */
2755 ret = ath5k_setup_bands(hw);
2756 if (ret) {
2757 ATH5K_ERR(sc, "can't get channels\n");
2758 goto err;
2759 }
67d2e2df 2760
8a63facc
BC		 2761 /* NB: setup here so ath5k_rate_update is happy */
2762 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2763 ath5k_setcurmode(sc, AR5K_MODE_11A);
2764 else
2765 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2766
8a63facc
BC		 2767 /*
2768 * Allocate tx+rx descriptors and populate the lists.
2769 */
aeae4ac9 2770 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2771 if (ret) {
2772 ATH5K_ERR(sc, "can't allocate descriptors\n");
2773 goto err;
2774 }
fa1c114f 2775
8a63facc
BC		 2776 /*
2777 * Allocate hardware transmit queues: one queue for
2778 * beacon frames and one data queue for each QoS
2779 * priority. Note that hw functions handle resetting
2780 * these queues at the needed time.
2781 */
2782 ret = ath5k_beaconq_setup(ah);
2783 if (ret < 0) {
2784 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2785 goto err_desc;
2786 }
2787 sc->bhalq = ret;
2788 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2789 if (IS_ERR(sc->cabq)) {
2790 ATH5K_ERR(sc, "can't setup cab queue\n");
2791 ret = PTR_ERR(sc->cabq);
2792 goto err_bhal;
2793 }
fa1c114f 2794
925e0b06
BR		 2795 /* This order matches mac80211's queue priority, so we can
2796 * directly use the mac80211 queue number without any mapping */
2797 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2798 if (IS_ERR(txq)) {
2799 ATH5K_ERR(sc, "can't setup xmit queue\n");
2800 ret = PTR_ERR(txq);
2801 goto err_queues;
2802 }
2803 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2804 if (IS_ERR(txq)) {
8a63facc 2805 ATH5K_ERR(sc, "can't setup xmit queue\n");
925e0b06 2806 ret = PTR_ERR(txq);
8a63facc
BC		 2807 goto err_queues;
2808 }
925e0b06
BR		 2809 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2810 if (IS_ERR(txq)) {
2811 ATH5K_ERR(sc, "can't setup xmit queue\n");
2812 ret = PTR_ERR(txq);
2813 goto err_queues;
2814 }
2815 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2816 if (IS_ERR(txq)) {
2817 ATH5K_ERR(sc, "can't setup xmit queue\n");
2818 ret = PTR_ERR(txq);
2819 goto err_queues;
2820 }
2821 hw->queues = 4;
fa1c114f 2822
8a63facc
BC		 2823 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2824 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2825 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2826 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2827 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2828
8a63facc 2829 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2830 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2831
8a63facc
BC		 2832 ret = ath5k_eeprom_read_mac(ah, mac);
2833 if (ret) {
aeae4ac9 2834 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2835 goto err_queues;
e30eb4ab 2836 }
2bed03eb 2837
8a63facc 2838 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2839 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2840 /* All MAC address bits matter for ACKs */
62c58fb4 2841 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2842
2843 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2844 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2845 if (ret) {
2846 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2847 goto err_queues;
2848 }
2849
2850 ret = ieee80211_register_hw(hw);
2851 if (ret) {
2852 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2853 goto err_queues;
2854 }
2855
2856 if (!ath_is_world_regd(regulatory))
2857 regulatory_hint(hw->wiphy, regulatory->alpha2);
2858
2859 ath5k_init_leds(sc);
2860
2861 ath5k_sysfs_register(sc);
2862
2863 return 0;
2864err_queues:
2865 ath5k_txq_release(sc);
2866err_bhal:
2867 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2868err_desc:
aeae4ac9 2869 ath5k_desc_free(sc);
8a63facc
BC		 2870err:
2871 return ret;
2872}
2873
132b1c3e
FF		 2874void
2875ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2876{
132b1c3e 2877 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2878
2879 /*
2880 * NB: the order of these is important:
2881 * o call the 802.11 layer before detaching ath5k_hw to
2882 * ensure callbacks into the driver to delete global
2883 * key cache entries can be handled
2884 * o reclaim the tx queue data structures after calling
2885 * the 802.11 layer as we'll get called back to reclaim
2886 * node state and potentially want to use them
2887 * o to cleanup the tx queues the hal is called, so detach
2888 * it last
2889 * XXX: ??? detach ath5k_hw ???
2890 * Other than that, it's straightforward...
2891 */
132b1c3e 2892 ath5k_debug_finish_device(sc);
8a63facc 2893 ieee80211_unregister_hw(hw);
aeae4ac9 2894 ath5k_desc_free(sc);
8a63facc
BC		 2895 ath5k_txq_release(sc);
2896 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2897 ath5k_unregister_leds(sc);
2898
2899 ath5k_sysfs_unregister(sc);
2900 /*
2901 * NB: can't reclaim these until after ieee80211_ifdetach
2902 * returns because we'll get called back to reclaim node
2903 * state and potentially want to use them.
2904 */
132b1c3e
FF		 2905 ath5k_hw_deinit(sc->ah);
2906 free_irq(sc->irq, sc);
8a63facc
BC		 2907}
2908
2909/********************\
2910* Mac80211 functions *
2911\********************/
2912
2913static int
2914ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2915{
2916 struct ath5k_softc *sc = hw->priv;
925e0b06
BR		 2917 u16 qnum = skb_get_queue_mapping(skb);
2918
2919 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2920 dev_kfree_skb_any(skb);
2921 return 0;
2922 }
8a63facc 2923
925e0b06 2924 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
8a63facc
BC		 2925}
2926
2927static int ath5k_start(struct ieee80211_hw *hw)
2928{
132b1c3e 2929 return ath5k_init_hw(hw->priv);
8a63facc
BC		 2930}
2931
2932static void ath5k_stop(struct ieee80211_hw *hw)
2933{
2934 ath5k_stop_hw(hw->priv);
2935}
2936
2937static int ath5k_add_interface(struct ieee80211_hw *hw,
2938 struct ieee80211_vif *vif)
2939{
2940 struct ath5k_softc *sc = hw->priv;
2941 int ret;
b1ae1edf 2942 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 2943
2944 mutex_lock(&sc->lock);
b1ae1edf
BG		 2945
2946 if ((vif->type == NL80211_IFTYPE_AP ||
2947 vif->type == NL80211_IFTYPE_ADHOC)
2948 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
2949 ret = -ELNRNG;
8a63facc
BC		 2950 goto end;
2951 }
2952
b1ae1edf
BG		 2953 /* Don't allow other interfaces if one ad-hoc is configured.
2954 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2955 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2956 * for the IBSS, but this breaks with additional AP or STA interfaces
2957 * at the moment. */
2958 if (sc->num_adhoc_vifs ||
2959 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
2960 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
2961 ret = -ELNRNG;
2962 goto end;
2963 }
8a63facc
BC		 2964
2965 switch (vif->type) {
2966 case NL80211_IFTYPE_AP:
2967 case NL80211_IFTYPE_STATION:
2968 case NL80211_IFTYPE_ADHOC:
2969 case NL80211_IFTYPE_MESH_POINT:
b1ae1edf 2970 avf->opmode = vif->type;
8a63facc
BC		 2971 break;
2972 default:
2973 ret = -EOPNOTSUPP;
2974 goto end;
2975 }
2976
b1ae1edf
BG		 2977 sc->nvifs++;
2978 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
8a63facc 2979
b1ae1edf
BG		 2980 /* Assign the vap/adhoc to a beacon xmit slot. */
2981 if ((avf->opmode == NL80211_IFTYPE_AP) ||
2982 (avf->opmode == NL80211_IFTYPE_ADHOC)) {
2983 int slot;
2984
2985 WARN_ON(list_empty(&sc->bcbuf));
2986 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
2987 list);
2988 list_del(&avf->bbuf->list);
2989
2990 avf->bslot = 0;
2991 for (slot = 0; slot < ATH_BCBUF; slot++) {
2992 if (!sc->bslot[slot]) {
2993 avf->bslot = slot;
2994 break;
2995 }
2996 }
2997 BUG_ON(sc->bslot[avf->bslot] != NULL);
2998 sc->bslot[avf->bslot] = vif;
2999 if (avf->opmode == NL80211_IFTYPE_AP)
3000 sc->num_ap_vifs++;
3001 else
3002 sc->num_adhoc_vifs++;
3003 }
3004
b1ae1edf
BG		 3005 /* Any MAC address is fine, all others are included through the
3006 * filter.
3007 */
3008 memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
8a63facc 3009 ath5k_hw_set_lladdr(sc->ah, vif->addr);
b1ae1edf
BG		 3010
3011 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
3012
3013 ath5k_mode_setup(sc, vif);
8a63facc
BC		 3014
3015 ret = 0;
3016end:
3017 mutex_unlock(&sc->lock);
3018 return ret;
3019}
3020
3021static void
3022ath5k_remove_interface(struct ieee80211_hw *hw,
3023 struct ieee80211_vif *vif)
3024{
3025 struct ath5k_softc *sc = hw->priv;
b1ae1edf
BG		 3026 struct ath5k_vif *avf = (void *)vif->drv_priv;
3027 unsigned int i;
8a63facc
BC		 3028
3029 mutex_lock(&sc->lock);
b1ae1edf
BG		 3030 sc->nvifs--;
3031
3032 if (avf->bbuf) {
3033 ath5k_txbuf_free_skb(sc, avf->bbuf);
3034 list_add_tail(&avf->bbuf->list, &sc->bcbuf);
3035 for (i = 0; i < ATH_BCBUF; i++) {
3036 if (sc->bslot[i] == vif) {
3037 sc->bslot[i] = NULL;
3038 break;
3039 }
3040 }
3041 avf->bbuf = NULL;
3042 }
3043 if (avf->opmode == NL80211_IFTYPE_AP)
3044 sc->num_ap_vifs--;
3045 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
3046 sc->num_adhoc_vifs--;
8a63facc 3047
62c58fb4 3048 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 3049 mutex_unlock(&sc->lock);
3050}
3051
3052/*
3053 * TODO: Phy disable/diversity etc
3054 */
3055static int
3056ath5k_config(struct ieee80211_hw *hw, u32 changed)
3057{
3058 struct ath5k_softc *sc = hw->priv;
3059 struct ath5k_hw *ah = sc->ah;
3060 struct ieee80211_conf *conf = &hw->conf;
3061 int ret = 0;
3062
3063 mutex_lock(&sc->lock);
3064
3065 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3066 ret = ath5k_chan_set(sc, conf->channel);
3067 if (ret < 0)
3068 goto unlock;
3069 }
3070
3071 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3072 (sc->power_level != conf->power_level)) {
a0823810
NK		 3073 sc->power_level = conf->power_level;
3074
3075 /* Half dB steps */
3076 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3077 }
fa1c114f 3078
2bed03eb
NK		 3079 /* TODO:
3080 * 1) Move this on config_interface and handle each case
3081 * separately eg. when we have only one STA vif, use
3082 * AR5K_ANTMODE_SINGLE_AP
3083 *
3084 * 2) Allow the user to change antenna mode eg. when only
3085 * one antenna is present
3086 *
3087 * 3) Allow the user to set default/tx antenna when possible
3088 *
3089 * 4) Default mode should handle 90% of the cases, together
3090 * with fixed a/b and single AP modes we should be able to
3091 * handle 99%. Sectored modes are extreme cases and i still
3092 * haven't found a usage for them. If we decide to support them,
3093 * then we must allow the user to set how many tx antennas we
3094 * have available
3095 */
caec9112 3096 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 3097
55aa4e0f 3098unlock:
be009370 3099 mutex_unlock(&sc->lock);
55aa4e0f 3100 return ret;
fa1c114f
JS		 3101}
3102
3ac64bee 3103static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 3104 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 3105{
3106 u32 mfilt[2], val;
3ac64bee 3107 u8 pos;
22bedad3 3108 struct netdev_hw_addr *ha;
3ac64bee
JB		 3109
3110 mfilt[0] = 0;
3111 mfilt[1] = 1;
3112
22bedad3 3113 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 3114 /* calculate XOR of eight 6-bit values */
22bedad3 3115 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 3116 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 3117 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 3118 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3119 pos &= 0x3f;
3120 mfilt[pos / 32] |= (1 << (pos % 32));
3121 /* XXX: we might be able to just do this instead,
3122 * but not sure, needs testing, if we do use this we'd
3123 * neet to inform below to not reset the mcast */
3124 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 3125 * ha->addr[5]); */
3ac64bee
JB		 3126 }
3127
3128 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3129}
3130
b1ae1edf
BG		 3131static bool ath_any_vif_assoc(struct ath5k_softc *sc)
3132{
3133 struct ath_vif_iter_data iter_data;
3134 iter_data.hw_macaddr = NULL;
3135 iter_data.any_assoc = false;
3136 iter_data.need_set_hw_addr = false;
3137 iter_data.found_active = true;
3138
3139 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
3140 &iter_data);
3141 return iter_data.any_assoc;
3142}
3143
fa1c114f
JS		 3144#define SUPPORTED_FIF_FLAGS \
3145 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3146 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3147 FIF_BCN_PRBRESP_PROMISC
3148/*
3149 * o always accept unicast, broadcast, and multicast traffic
3150 * o multicast traffic for all BSSIDs will be enabled if mac80211
3151 * says it should be
3152 * o maintain current state of phy ofdm or phy cck error reception.
3153 * If the hardware detects any of these type of errors then
3154 * ath5k_hw_get_rx_filter() will pass to us the respective
3155 * hardware filters to be able to receive these type of frames.
3156 * o probe request frames are accepted only when operating in
3157 * hostap, adhoc, or monitor modes
3158 * o enable promiscuous mode according to the interface state
3159 * o accept beacons:
3160 * - when operating in adhoc mode so the 802.11 layer creates
3161 * node table entries for peers,
3162 * - when operating in station mode for collecting rssi data when
3163 * the station is otherwise quiet, or
3164 * - when scanning
3165 */
3166static void ath5k_configure_filter(struct ieee80211_hw *hw,
3167 unsigned int changed_flags,
3168 unsigned int *new_flags,
3ac64bee 3169 u64 multicast)
fa1c114f
JS		 3170{
3171 struct ath5k_softc *sc = hw->priv;
3172 struct ath5k_hw *ah = sc->ah;
3ac64bee 3173 u32 mfilt[2], rfilt;
fa1c114f 3174
56d1de0a
BC		 3175 mutex_lock(&sc->lock);
3176
3ac64bee
JB		 3177 mfilt[0] = multicast;
3178 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3179
3180 /* Only deal with supported flags */
3181 changed_flags &= SUPPORTED_FIF_FLAGS;
3182 *new_flags &= SUPPORTED_FIF_FLAGS;
3183
3184 /* If HW detects any phy or radar errors, leave those filters on.
3185 * Also, always enable Unicast, Broadcasts and Multicast
3186 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3187 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3188 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3189 AR5K_RX_FILTER_MCAST);
3190
3191 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3192 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 3193 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3194 } else {
fa1c114f 3195 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3196 }
fa1c114f
JS		 3197 }
3198
6b5dcccb
BC		 3199 if (test_bit(ATH_STAT_PROMISC, sc->status))
3200 rfilt |= AR5K_RX_FILTER_PROM;
3201
fa1c114f
JS		 3202 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3203 if (*new_flags & FIF_ALLMULTI) {
3204 mfilt[0] = ~0;
3205 mfilt[1] = ~0;
fa1c114f
JS		 3206 }
3207
3208 /* This is the best we can do */
3209 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3210 rfilt |= AR5K_RX_FILTER_PHYERR;
3211
3212 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
30bf4169 3213 * and probes for any BSSID */
b1ae1edf 3214 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
30bf4169 3215 rfilt |= AR5K_RX_FILTER_BEACON;
fa1c114f
JS		 3216
3217 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3218 * set we should only pass on control frames for this
3219 * station. This needs testing. I believe right now this
3220 * enables *all* control frames, which is OK.. but
3221 * but we should see if we can improve on granularity */
3222 if (*new_flags & FIF_CONTROL)
3223 rfilt |= AR5K_RX_FILTER_CONTROL;
3224
3225 /* Additional settings per mode -- this is per ath5k */
3226
3227 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3228
56d1de0a
BC		 3229 switch (sc->opmode) {
3230 case NL80211_IFTYPE_MESH_POINT:
56d1de0a
BC		 3231 rfilt |= AR5K_RX_FILTER_CONTROL |
3232 AR5K_RX_FILTER_BEACON |
3233 AR5K_RX_FILTER_PROBEREQ |
3234 AR5K_RX_FILTER_PROM;
3235 break;
3236 case NL80211_IFTYPE_AP:
3237 case NL80211_IFTYPE_ADHOC:
3238 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3239 AR5K_RX_FILTER_BEACON;
3240 break;
3241 case NL80211_IFTYPE_STATION:
3242 if (sc->assoc)
3243 rfilt |= AR5K_RX_FILTER_BEACON;
3244 default:
3245 break;
3246 }
fa1c114f
JS		 3247
3248 /* Set filters */
0bbac08f 3249 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3250
3251 /* Set multicast bits */
3252 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
a180a130 3253 /* Set the cached hw filter flags, this will later actually
fa1c114f
JS		 3254 * be set in HW */
3255 sc->filter_flags = rfilt;
56d1de0a
BC		 3256
3257 mutex_unlock(&sc->lock);
fa1c114f
JS		 3258}
3259
3260static int
3261ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3262 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3263 struct ieee80211_key_conf *key)
fa1c114f
JS		 3264{
3265 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3266 struct ath5k_hw *ah = sc->ah;
3267 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3268 int ret = 0;
3269
9ad9a26e
BC		 3270 if (modparam_nohwcrypt)
3271 return -EOPNOTSUPP;
3272
97359d12
JB		 3273 switch (key->cipher) {
3274 case WLAN_CIPHER_SUITE_WEP40:
3275 case WLAN_CIPHER_SUITE_WEP104:
3276 case WLAN_CIPHER_SUITE_TKIP:
3f64b435 3277 break;
97359d12 3278 case WLAN_CIPHER_SUITE_CCMP:
781f3136 3279 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
1c818740 3280 break;
fa1c114f
JS		 3281 return -EOPNOTSUPP;
3282 default:
3283 WARN_ON(1);
3284 return -EINVAL;
3285 }
3286
3287 mutex_lock(&sc->lock);
3288
3289 switch (cmd) {
3290 case SET_KEY:
e0f8c2a9
BR		 3291 ret = ath_key_config(common, vif, sta, key);
3292 if (ret >= 0) {
3293 key->hw_key_idx = ret;
3294 /* push IV and Michael MIC generation to stack */
3295 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3296 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3297 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3298 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3299 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3300 ret = 0;
fa1c114f 3301 }
fa1c114f
JS		 3302 break;
3303 case DISABLE_KEY:
e0f8c2a9 3304 ath_key_delete(common, key);
fa1c114f
JS		 3305 break;
3306 default:
3307 ret = -EINVAL;
fa1c114f
JS		 3308 }
3309
8a63facc
BC		 3310 mmiowb();
3311 mutex_unlock(&sc->lock);
3312 return ret;
3313}
3314
3315static int
3316ath5k_get_stats(struct ieee80211_hw *hw,
3317 struct ieee80211_low_level_stats *stats)
3318{
3319 struct ath5k_softc *sc = hw->priv;
3320
3321 /* Force update */
3322 ath5k_hw_update_mib_counters(sc->ah);
3323
3324 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3325 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3326 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3327 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3328
3329 return 0;
3330}
3331
3332static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3333 struct survey_info *survey)
3334{
3335 struct ath5k_softc *sc = hw->priv;
3336 struct ieee80211_conf *conf = &hw->conf;
edb40a23
BR		 3337 struct ath_common *common = ath5k_hw_common(sc->ah);
3338 struct ath_cycle_counters *cc = &common->cc_survey;
3339 unsigned int div = common->clockrate * 1000;
8a63facc 3340
edb40a23 3341 if (idx != 0)
8a63facc
BC		 3342 return -ENOENT;
3343
3344 survey->channel = conf->channel;
3345 survey->filled = SURVEY_INFO_NOISE_DBM;
3346 survey->noise = sc->ah->ah_noise_floor;
3347
edb40a23
BR		 3348 spin_lock_bh(&common->cc_lock);
3349 ath_hw_cycle_counters_update(common);
3350 if (cc->cycles > 0) {
3351 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
3352 SURVEY_INFO_CHANNEL_TIME_BUSY |
3353 SURVEY_INFO_CHANNEL_TIME_RX |
3354 SURVEY_INFO_CHANNEL_TIME_TX;
3355 survey->channel_time += cc->cycles / div;
3356 survey->channel_time_busy += cc->rx_busy / div;
3357 survey->channel_time_rx += cc->rx_frame / div;
3358 survey->channel_time_tx += cc->tx_frame / div;
3359 }
3360 memset(cc, 0, sizeof(*cc));
3361 spin_unlock_bh(&common->cc_lock);
3362
8a63facc
BC		 3363 return 0;
3364}
3365
3366static u64
3367ath5k_get_tsf(struct ieee80211_hw *hw)
3368{
3369 struct ath5k_softc *sc = hw->priv;
3370
3371 return ath5k_hw_get_tsf64(sc->ah);
3372}
3373
3374static void
3375ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3376{
3377 struct ath5k_softc *sc = hw->priv;
3378
3379 ath5k_hw_set_tsf64(sc->ah, tsf);
3380}
3381
3382static void
3383ath5k_reset_tsf(struct ieee80211_hw *hw)
3384{
3385 struct ath5k_softc *sc = hw->priv;
3386
3387 /*
3388 * in IBSS mode we need to update the beacon timers too.
3389 * this will also reset the TSF if we call it with 0
3390 */
3391 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3392 ath5k_beacon_update_timers(sc, 0);
3393 else
3394 ath5k_hw_reset_tsf(sc->ah);
3395}
3396
3397static void
3398set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3399{
3400 struct ath5k_softc *sc = hw->priv;
3401 struct ath5k_hw *ah = sc->ah;
3402 u32 rfilt;
3403 rfilt = ath5k_hw_get_rx_filter(ah);
3404 if (enable)
3405 rfilt |= AR5K_RX_FILTER_BEACON;
3406 else
3407 rfilt &= ~AR5K_RX_FILTER_BEACON;
3408 ath5k_hw_set_rx_filter(ah, rfilt);
3409 sc->filter_flags = rfilt;
3410}
3411
3412static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3413 struct ieee80211_vif *vif,
3414 struct ieee80211_bss_conf *bss_conf,
3415 u32 changes)
3416{
b1ae1edf 3417 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 3418 struct ath5k_softc *sc = hw->priv;
3419 struct ath5k_hw *ah = sc->ah;
3420 struct ath_common *common = ath5k_hw_common(ah);
3421 unsigned long flags;
3422
3423 mutex_lock(&sc->lock);
8a63facc
BC		 3424
3425 if (changes & BSS_CHANGED_BSSID) {
3426 /* Cache for later use during resets */
3427 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3428 common->curaid = 0;
3429 ath5k_hw_set_bssid(ah);
3430 mmiowb();
3431 }
3432
3433 if (changes & BSS_CHANGED_BEACON_INT)
3434 sc->bintval = bss_conf->beacon_int;
3435
3436 if (changes & BSS_CHANGED_ASSOC) {
b1ae1edf
BG		 3437 avf->assoc = bss_conf->assoc;
3438 if (bss_conf->assoc)
3439 sc->assoc = bss_conf->assoc;
3440 else
3441 sc->assoc = ath_any_vif_assoc(sc);
3442
8a63facc
BC		 3443 if (sc->opmode == NL80211_IFTYPE_STATION)
3444 set_beacon_filter(hw, sc->assoc);
3445 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3446 AR5K_LED_ASSOC : AR5K_LED_INIT);
3447 if (bss_conf->assoc) {
3448 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3449 "Bss Info ASSOC %d, bssid: %pM\n",
3450 bss_conf->aid, common->curbssid);
3451 common->curaid = bss_conf->aid;
3452 ath5k_hw_set_bssid(ah);
3453 /* Once ANI is available you would start it here */
3454 }
3455 }
3456
3457 if (changes & BSS_CHANGED_BEACON) {
3458 spin_lock_irqsave(&sc->block, flags);
3459 ath5k_beacon_update(hw, vif);
3460 spin_unlock_irqrestore(&sc->block, flags);
3461 }
3462
3463 if (changes & BSS_CHANGED_BEACON_ENABLED)
3464 sc->enable_beacon = bss_conf->enable_beacon;
3465
3466 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3467 BSS_CHANGED_BEACON_INT))
3468 ath5k_beacon_config(sc);
3469
8a63facc
BC		 3470 mutex_unlock(&sc->lock);
3471}
3472
3473static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3474{
3475 struct ath5k_softc *sc = hw->priv;
3476 if (!sc->assoc)
3477 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3478}
3479
3480static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3481{
3482 struct ath5k_softc *sc = hw->priv;
3483 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3484 AR5K_LED_ASSOC : AR5K_LED_INIT);
3485}
3486
3487/**
3488 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3489 *
3490 * @hw: struct ieee80211_hw pointer
3491 * @coverage_class: IEEE 802.11 coverage class number
3492 *
3493 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3494 * coverage class. The values are persistent, they are restored after device
3495 * reset.
3496 */
3497static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3498{
3499 struct ath5k_softc *sc = hw->priv;
3500
3501 mutex_lock(&sc->lock);
3502 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3503 mutex_unlock(&sc->lock);
3504}
3505
e0b1cc52
BR		 3506static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3507 const struct ieee80211_tx_queue_params *params)
3508{
3509 struct ath5k_softc *sc = hw->priv;
3510 struct ath5k_hw *ah = sc->ah;
3511 struct ath5k_txq_info qi;
3512 int ret = 0;
3513
3514 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3515 return 0;
3516
3517 mutex_lock(&sc->lock);
3518
3519 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3520
3521 qi.tqi_aifs = params->aifs;
3522 qi.tqi_cw_min = params->cw_min;
3523 qi.tqi_cw_max = params->cw_max;
3524 qi.tqi_burst_time = params->txop;
3525
3526 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3527 "Configure tx [queue %d], "
3528 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3529 queue, params->aifs, params->cw_min,
3530 params->cw_max, params->txop);
3531
3532 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3533 ATH5K_ERR(sc,
3534 "Unable to update hardware queue %u!\n", queue);
3535 ret = -EIO;
3536 } else
3537 ath5k_hw_reset_tx_queue(ah, queue);
3538
3539 mutex_unlock(&sc->lock);
3540
3541 return ret;
3542}
3543
72a80110
BR		 3544static int ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
3545{
3546 struct ath5k_softc *sc = hw->priv;
3547
3548 if (tx_ant == 1 && rx_ant == 1)
3549 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
3550 else if (tx_ant == 2 && rx_ant == 2)
3551 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
3552 else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
3553 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
3554 else
3555 return -EINVAL;
3556 return 0;
3557}
3558
3559static int ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
3560{
3561 struct ath5k_softc *sc = hw->priv;
3562
3563 switch (sc->ah->ah_ant_mode) {
3564 case AR5K_ANTMODE_FIXED_A:
3565 *tx_ant = 1; *rx_ant = 1; break;
3566 case AR5K_ANTMODE_FIXED_B:
3567 *tx_ant = 2; *rx_ant = 2; break;
3568 case AR5K_ANTMODE_DEFAULT:
3569 *tx_ant = 3; *rx_ant = 3; break;
3570 }
3571 return 0;
3572}
3573
132b1c3e 3574const struct ieee80211_ops ath5k_hw_ops = {
8a63facc
BC		 3575 .tx = ath5k_tx,
3576 .start = ath5k_start,
3577 .stop = ath5k_stop,
3578 .add_interface = ath5k_add_interface,
3579 .remove_interface = ath5k_remove_interface,
3580 .config = ath5k_config,
3581 .prepare_multicast = ath5k_prepare_multicast,
3582 .configure_filter = ath5k_configure_filter,
3583 .set_key = ath5k_set_key,
3584 .get_stats = ath5k_get_stats,
3585 .get_survey = ath5k_get_survey,
e0b1cc52 3586 .conf_tx = ath5k_conf_tx,
8a63facc
BC		 3587 .get_tsf = ath5k_get_tsf,
3588 .set_tsf = ath5k_set_tsf,
3589 .reset_tsf = ath5k_reset_tsf,
3590 .bss_info_changed = ath5k_bss_info_changed,
3591 .sw_scan_start = ath5k_sw_scan_start,
3592 .sw_scan_complete = ath5k_sw_scan_complete,
3593 .set_coverage_class = ath5k_set_coverage_class,
72a80110
BR		 3594 .set_antenna = ath5k_set_antenna,
3595 .get_antenna = ath5k_get_antenna,
8a63facc 3596};
Linux kernel - Deliverables
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