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ath5k: fix SWI calibration interrupt storm
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
6e220662 62static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e 63static int modparam_nohwcrypt;
46802a4f 64module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 66
42639fcd 67static int modparam_all_channels;
46802a4f 68module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 69MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
fa1c114f
JS		 71
72/******************\
73* Internal defines *
74\******************/
75
76/* Module info */
77MODULE_AUTHOR("Jiri Slaby");
78MODULE_AUTHOR("Nick Kossifidis");
79MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 82MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 83
84
85/* Known PCI ids */
2c91108c 86static const struct pci_device_id ath5k_pci_id_table[] = {
97a81f5c
PR		 87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 105 { 0 }
106};
107MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109/* Known SREVs */
2c91108c 110static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147};
148
2c91108c 149static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189};
190
fa1c114f
JS		 191/*
192 * Prototypes - PCI stack related functions
193 */
194static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197#ifdef CONFIG_PM
baee1f3c
RW		 198static int ath5k_pci_suspend(struct device *dev);
199static int ath5k_pci_resume(struct device *dev);
200
201SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202#define ATH5K_PM_OPS (&ath5k_pm_ops)
fa1c114f 203#else
baee1f3c 204#define ATH5K_PM_OPS NULL
fa1c114f
JS		 205#endif /* CONFIG_PM */
206
04a9e451 207static struct pci_driver ath5k_pci_driver = {
9764f3f9 208 .name = KBUILD_MODNAME,
fa1c114f
JS		 209 .id_table = ath5k_pci_id_table,
210 .probe = ath5k_pci_probe,
211 .remove = __devexit_p(ath5k_pci_remove),
baee1f3c 212 .driver.pm = ATH5K_PM_OPS,
fa1c114f
JS		 213};
214
215
216
217/*
218 * Prototypes - MAC 802.11 stack related functions
219 */
e039fa4a 220static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 221static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
209d889b 223static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 224static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 225static int ath5k_start(struct ieee80211_hw *hw);
226static void ath5k_stop(struct ieee80211_hw *hw);
227static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
e8975581 231static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee
JB		 232static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
fa1c114f
JS		 234static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
3ac64bee 237 u64 multicast);
fa1c114f
JS		 238static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
dc822b5d 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 241 struct ieee80211_key_conf *key);
242static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
245 struct ieee80211_tx_queue_stats *stats);
246static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 247static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 248static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 249static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
02969b38
MX		 251static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
254 u32 changes);
f0f3d388
BC		 255static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
fa1c114f 257
2c91108c 258static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 259 .tx = ath5k_tx,
260 .start = ath5k_start,
261 .stop = ath5k_stop,
262 .add_interface = ath5k_add_interface,
263 .remove_interface = ath5k_remove_interface,
264 .config = ath5k_config,
3ac64bee 265 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 266 .configure_filter = ath5k_configure_filter,
267 .set_key = ath5k_set_key,
268 .get_stats = ath5k_get_stats,
269 .conf_tx = NULL,
270 .get_tx_stats = ath5k_get_tx_stats,
271 .get_tsf = ath5k_get_tsf,
3b5d665b 272 .set_tsf = ath5k_set_tsf,
fa1c114f 273 .reset_tsf = ath5k_reset_tsf,
02969b38 274 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 275 .sw_scan_start = ath5k_sw_scan_start,
276 .sw_scan_complete = ath5k_sw_scan_complete,
fa1c114f
JS		 277};
278
279/*
280 * Prototypes - Internal functions
281 */
282/* Attach detach */
283static int ath5k_attach(struct pci_dev *pdev,
284 struct ieee80211_hw *hw);
285static void ath5k_detach(struct pci_dev *pdev,
286 struct ieee80211_hw *hw);
287/* Channel/mode setup */
288static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 289static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
290 struct ieee80211_channel *channels,
291 unsigned int mode,
292 unsigned int max);
63266a65 293static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 294static int ath5k_chan_set(struct ath5k_softc *sc,
295 struct ieee80211_channel *chan);
296static void ath5k_setcurmode(struct ath5k_softc *sc,
297 unsigned int mode);
298static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 299
fa1c114f
JS		 300/* Descriptor setup */
301static int ath5k_desc_alloc(struct ath5k_softc *sc,
302 struct pci_dev *pdev);
303static void ath5k_desc_free(struct ath5k_softc *sc,
304 struct pci_dev *pdev);
305/* Buffers setup */
306static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
307 struct ath5k_buf *bf);
308static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23
BC		 309 struct ath5k_buf *bf,
310 struct ath5k_txq *txq);
fa1c114f
JS		 311static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
312 struct ath5k_buf *bf)
313{
314 BUG_ON(!bf);
315 if (!bf->skb)
316 return;
317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
318 PCI_DMA_TODEVICE);
00482973 319 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 320 bf->skb = NULL;
321}
322
a6c8d375
FF		 323static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
324 struct ath5k_buf *bf)
325{
cc861f74
LR		 326 struct ath5k_hw *ah = sc->ah;
327 struct ath_common *common = ath5k_hw_common(ah);
328
a6c8d375
FF		 329 BUG_ON(!bf);
330 if (!bf->skb)
331 return;
cc861f74 332 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 333 PCI_DMA_FROMDEVICE);
334 dev_kfree_skb_any(bf->skb);
335 bf->skb = NULL;
336}
337
338
fa1c114f
JS		 339/* Queues setup */
340static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
341 int qtype, int subtype);
342static int ath5k_beaconq_setup(struct ath5k_hw *ah);
343static int ath5k_beaconq_config(struct ath5k_softc *sc);
344static void ath5k_txq_drainq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346static void ath5k_txq_cleanup(struct ath5k_softc *sc);
347static void ath5k_txq_release(struct ath5k_softc *sc);
348/* Rx handling */
349static int ath5k_rx_start(struct ath5k_softc *sc);
350static void ath5k_rx_stop(struct ath5k_softc *sc);
351static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
352 struct ath5k_desc *ds,
b47f407b
BR		 353 struct sk_buff *skb,
354 struct ath5k_rx_status *rs);
fa1c114f
JS		 355static void ath5k_tasklet_rx(unsigned long data);
356/* Tx handling */
357static void ath5k_tx_processq(struct ath5k_softc *sc,
358 struct ath5k_txq *txq);
359static void ath5k_tasklet_tx(unsigned long data);
360/* Beacon handling */
361static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 362 struct ath5k_buf *bf);
fa1c114f
JS		 363static void ath5k_beacon_send(struct ath5k_softc *sc);
364static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 365static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 366static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 367
368static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
369{
370 u64 tsf = ath5k_hw_get_tsf64(ah);
371
372 if ((tsf & 0x7fff) < rstamp)
373 tsf -= 0x8000;
374
375 return (tsf & ~0x7fff) | rstamp;
376}
377
378/* Interrupt handling */
bb2becac 379static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 380static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 381static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 382static irqreturn_t ath5k_intr(int irq, void *dev_id);
383static void ath5k_tasklet_reset(unsigned long data);
384
6e220662 385static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 386
387/*
388 * Module init/exit functions
389 */
390static int __init
391init_ath5k_pci(void)
392{
393 int ret;
394
395 ath5k_debug_init();
396
04a9e451 397 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 398 if (ret) {
399 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
400 return ret;
401 }
402
403 return 0;
404}
405
406static void __exit
407exit_ath5k_pci(void)
408{
04a9e451 409 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 410
411 ath5k_debug_finish();
412}
413
414module_init(init_ath5k_pci);
415module_exit(exit_ath5k_pci);
416
417
418/********************\
419* PCI Initialization *
420\********************/
421
422static const char *
423ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
424{
425 const char *name = "xxxxx";
426 unsigned int i;
427
428 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
429 if (srev_names[i].sr_type != type)
430 continue;
75d0edb8
NK		 431
432 if ((val & 0xf0) == srev_names[i].sr_val)
433 name = srev_names[i].sr_name;
434
435 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 436 name = srev_names[i].sr_name;
437 break;
438 }
439 }
440
441 return name;
442}
e5aa8474
LR		 443static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
444{
445 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
446 return ath5k_hw_reg_read(ah, reg_offset);
447}
448
449static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
450{
451 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
452 ath5k_hw_reg_write(ah, val, reg_offset);
453}
454
455static const struct ath_ops ath5k_common_ops = {
456 .read = ath5k_ioread32,
457 .write = ath5k_iowrite32,
458};
fa1c114f
JS		 459
460static int __devinit
461ath5k_pci_probe(struct pci_dev *pdev,
462 const struct pci_device_id *id)
463{
464 void __iomem *mem;
465 struct ath5k_softc *sc;
db719718 466 struct ath_common *common;
fa1c114f
JS		 467 struct ieee80211_hw *hw;
468 int ret;
469 u8 csz;
470
471 ret = pci_enable_device(pdev);
472 if (ret) {
473 dev_err(&pdev->dev, "can't enable device\n");
474 goto err;
475 }
476
477 /* XXX 32-bit addressing only */
284901a9 478 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 479 if (ret) {
480 dev_err(&pdev->dev, "32-bit DMA not available\n");
481 goto err_dis;
482 }
483
484 /*
485 * Cache line size is used to size and align various
486 * structures used to communicate with the hardware.
487 */
488 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
489 if (csz == 0) {
490 /*
491 * Linux 2.4.18 (at least) writes the cache line size
492 * register as a 16-bit wide register which is wrong.
493 * We must have this setup properly for rx buffer
494 * DMA to work so force a reasonable value here if it
495 * comes up zero.
496 */
13311b00 497 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 498 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
499 }
500 /*
501 * The default setting of latency timer yields poor results,
502 * set it to the value used by other systems. It may be worth
503 * tweaking this setting more.
504 */
505 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
506
507 /* Enable bus mastering */
508 pci_set_master(pdev);
509
510 /*
511 * Disable the RETRY_TIMEOUT register (0x41) to keep
512 * PCI Tx retries from interfering with C3 CPU state.
513 */
514 pci_write_config_byte(pdev, 0x41, 0);
515
516 ret = pci_request_region(pdev, 0, "ath5k");
517 if (ret) {
518 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
519 goto err_dis;
520 }
521
522 mem = pci_iomap(pdev, 0, 0);
523 if (!mem) {
524 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
525 ret = -EIO;
526 goto err_reg;
527 }
528
529 /*
530 * Allocate hw (mac80211 main struct)
531 * and hw->priv (driver private data)
532 */
533 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
534 if (hw == NULL) {
535 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
536 ret = -ENOMEM;
537 goto err_map;
538 }
539
540 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
541
542 /* Initialize driver private data */
543 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 544 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 545 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 546 IEEE80211_HW_SIGNAL_DBM |
547 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 548
549 hw->wiphy->interface_modes =
6f5f39c9 550 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 551 BIT(NL80211_IFTYPE_STATION) |
552 BIT(NL80211_IFTYPE_ADHOC) |
553 BIT(NL80211_IFTYPE_MESH_POINT);
554
fa1c114f
JS		 555 hw->extra_tx_headroom = 2;
556 hw->channel_change_time = 5000;
fa1c114f
JS		 557 sc = hw->priv;
558 sc->hw = hw;
559 sc->pdev = pdev;
560
561 ath5k_debug_init_device(sc);
562
563 /*
564 * Mark the device as detached to avoid processing
565 * interrupts until setup is complete.
566 */
567 __set_bit(ATH_STAT_INVALID, sc->status);
568
569 sc->iobase = mem; /* So we can unmap it on detach */
05c914fe 570 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 571 sc->bintval = 1000;
fa1c114f
JS		 572 mutex_init(&sc->lock);
573 spin_lock_init(&sc->rxbuflock);
574 spin_lock_init(&sc->txbuflock);
00482973 575 spin_lock_init(&sc->block);
fa1c114f
JS		 576
577 /* Set private data */
578 pci_set_drvdata(pdev, hw);
579
fa1c114f
JS		 580 /* Setup interrupt handler */
581 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
582 if (ret) {
583 ATH5K_ERR(sc, "request_irq failed\n");
584 goto err_free;
585 }
586
9adca126
LR		 587 /*If we passed the test malloc a ath5k_hw struct*/
588 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
589 if (!sc->ah) {
590 ret = -ENOMEM;
591 ATH5K_ERR(sc, "out of memory\n");
fa1c114f
JS		 592 goto err_irq;
593 }
594
9adca126
LR		 595 sc->ah->ah_sc = sc;
596 sc->ah->ah_iobase = sc->iobase;
db719718 597 common = ath5k_hw_common(sc->ah);
e5aa8474 598 common->ops = &ath5k_common_ops;
13b81559 599 common->ah = sc->ah;
b002a4a9 600 common->hw = hw;
db719718
LR		 601 common->cachelsz = csz << 2; /* convert to bytes */
602
9adca126
LR		 603 /* Initialize device */
604 ret = ath5k_hw_attach(sc);
605 if (ret) {
606 goto err_free_ah;
607 }
608
2f7fe870
FF		 609 /* set up multi-rate retry capabilities */
610 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 611 hw->max_rates = 4;
612 hw->max_rate_tries = 11;
2f7fe870
FF		 613 }
614
fa1c114f
JS		 615 /* Finish private driver data initialization */
616 ret = ath5k_attach(pdev, hw);
617 if (ret)
618 goto err_ah;
619
620 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 621 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 622 sc->ah->ah_mac_srev,
623 sc->ah->ah_phy_revision);
624
400ec45a 625 if (!sc->ah->ah_single_chip) {
fa1c114f 626 /* Single chip radio (!RF5111) */
400ec45a
LR		 627 if (sc->ah->ah_radio_5ghz_revision &&
628 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 629 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 630 if (!test_bit(AR5K_MODE_11A,
631 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 632 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 633 ath5k_chip_name(AR5K_VERSION_RAD,
634 sc->ah->ah_radio_5ghz_revision),
635 sc->ah->ah_radio_5ghz_revision);
636 /* No 2GHz support (5110 and some
637 * 5Ghz only cards) -> report 5Ghz radio */
638 } else if (!test_bit(AR5K_MODE_11B,
639 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 640 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 641 ath5k_chip_name(AR5K_VERSION_RAD,
642 sc->ah->ah_radio_5ghz_revision),
643 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 644 /* Multiband radio */
645 } else {
646 ATH5K_INFO(sc, "RF%s multiband radio found"
647 " (0x%x)\n",
400ec45a
LR		 648 ath5k_chip_name(AR5K_VERSION_RAD,
649 sc->ah->ah_radio_5ghz_revision),
650 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 651 }
652 }
400ec45a
LR		 653 /* Multi chip radio (RF5111 - RF2111) ->
654 * report both 2GHz/5GHz radios */
655 else if (sc->ah->ah_radio_5ghz_revision &&
656 sc->ah->ah_radio_2ghz_revision){
fa1c114f 657 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 658 ath5k_chip_name(AR5K_VERSION_RAD,
659 sc->ah->ah_radio_5ghz_revision),
660 sc->ah->ah_radio_5ghz_revision);
fa1c114f 661 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 662 ath5k_chip_name(AR5K_VERSION_RAD,
663 sc->ah->ah_radio_2ghz_revision),
664 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 665 }
666 }
667
668
669 /* ready to process interrupts */
670 __clear_bit(ATH_STAT_INVALID, sc->status);
671
672 return 0;
673err_ah:
674 ath5k_hw_detach(sc->ah);
675err_irq:
676 free_irq(pdev->irq, sc);
9adca126
LR		 677err_free_ah:
678 kfree(sc->ah);
fa1c114f 679err_free:
fa1c114f
JS		 680 ieee80211_free_hw(hw);
681err_map:
682 pci_iounmap(pdev, mem);
683err_reg:
684 pci_release_region(pdev, 0);
685err_dis:
686 pci_disable_device(pdev);
687err:
688 return ret;
689}
690
691static void __devexit
692ath5k_pci_remove(struct pci_dev *pdev)
693{
694 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
695 struct ath5k_softc *sc = hw->priv;
696
697 ath5k_debug_finish_device(sc);
698 ath5k_detach(pdev, hw);
699 ath5k_hw_detach(sc->ah);
9adca126 700 kfree(sc->ah);
fa1c114f 701 free_irq(pdev->irq, sc);
fa1c114f
JS		 702 pci_iounmap(pdev, sc->iobase);
703 pci_release_region(pdev, 0);
704 pci_disable_device(pdev);
705 ieee80211_free_hw(hw);
706}
707
708#ifdef CONFIG_PM
baee1f3c 709static int ath5k_pci_suspend(struct device *dev)
fa1c114f 710{
baee1f3c 711 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
fa1c114f
JS		 712 struct ath5k_softc *sc = hw->priv;
713
3a078876 714 ath5k_led_off(sc);
fa1c114f
JS		 715 return 0;
716}
717
baee1f3c 718static int ath5k_pci_resume(struct device *dev)
fa1c114f 719{
baee1f3c 720 struct pci_dev *pdev = to_pci_dev(dev);
fa1c114f
JS		 721 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
722 struct ath5k_softc *sc = hw->priv;
fa1c114f 723
8451d22d
JM		 724 /*
725 * Suspend/Resume resets the PCI configuration space, so we have to
726 * re-disable the RETRY_TIMEOUT register (0x41) to keep
727 * PCI Tx retries from interfering with C3 CPU state
728 */
729 pci_write_config_byte(pdev, 0x41, 0);
730
3a078876 731 ath5k_led_enable(sc);
fa1c114f
JS		 732 return 0;
733}
734#endif /* CONFIG_PM */
735
736
fa1c114f
JS		 737/***********************\
738* Driver Initialization *
739\***********************/
740
f769c36b
BC		 741static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
742{
743 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
744 struct ath5k_softc *sc = hw->priv;
db719718 745 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
f769c36b 746
608b88cb 747 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 748}
749
fa1c114f
JS		 750static int
751ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
752{
753 struct ath5k_softc *sc = hw->priv;
754 struct ath5k_hw *ah = sc->ah;
db719718 755 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
0e149cf5 756 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 757 int ret;
758
759 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
760
761 /*
762 * Check if the MAC has multi-rate retry support.
763 * We do this by trying to setup a fake extended
764 * descriptor. MAC's that don't have support will
765 * return false w/o doing anything. MAC's that do
766 * support it will return true w/o doing anything.
767 */
c6e387a2 768 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 769 if (ret < 0)
770 goto err;
771 if (ret > 0)
fa1c114f
JS		 772 __set_bit(ATH_STAT_MRRETRY, sc->status);
773
fa1c114f
JS		 774 /*
775 * Collect the channel list. The 802.11 layer
776 * is resposible for filtering this list based
777 * on settings like the phy mode and regulatory
778 * domain restrictions.
779 */
63266a65 780 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 781 if (ret) {
782 ATH5K_ERR(sc, "can't get channels\n");
783 goto err;
784 }
785
786 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 787 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
788 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 789 else
d8ee398d 790 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 791
792 /*
793 * Allocate tx+rx descriptors and populate the lists.
794 */
795 ret = ath5k_desc_alloc(sc, pdev);
796 if (ret) {
797 ATH5K_ERR(sc, "can't allocate descriptors\n");
798 goto err;
799 }
800
801 /*
802 * Allocate hardware transmit queues: one queue for
803 * beacon frames and one data queue for each QoS
804 * priority. Note that hw functions handle reseting
805 * these queues at the needed time.
806 */
807 ret = ath5k_beaconq_setup(ah);
808 if (ret < 0) {
809 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
810 goto err_desc;
811 }
812 sc->bhalq = ret;
cec8db23
BC		 813 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
814 if (IS_ERR(sc->cabq)) {
815 ATH5K_ERR(sc, "can't setup cab queue\n");
816 ret = PTR_ERR(sc->cabq);
817 goto err_bhal;
818 }
fa1c114f
JS		 819
820 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
821 if (IS_ERR(sc->txq)) {
822 ATH5K_ERR(sc, "can't setup xmit queue\n");
823 ret = PTR_ERR(sc->txq);
cec8db23 824 goto err_queues;
fa1c114f
JS		 825 }
826
827 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
828 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
829 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
6e220662 830 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 831 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 832
0e149cf5
BC		 833 ret = ath5k_eeprom_read_mac(ah, mac);
834 if (ret) {
835 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
836 sc->pdev->device);
837 goto err_queues;
838 }
839
fa1c114f
JS		 840 SET_IEEE80211_PERM_ADDR(hw, mac);
841 /* All MAC address bits matter for ACKs */
17753748 842 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 843 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
844
608b88cb
LR		 845 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
846 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 847 if (ret) {
848 ATH5K_ERR(sc, "can't initialize regulatory system\n");
849 goto err_queues;
850 }
851
fa1c114f
JS		 852 ret = ieee80211_register_hw(hw);
853 if (ret) {
854 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
855 goto err_queues;
856 }
857
608b88cb
LR		 858 if (!ath_is_world_regd(regulatory))
859 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 860
3a078876
BC		 861 ath5k_init_leds(sc);
862
fa1c114f
JS		 863 return 0;
864err_queues:
865 ath5k_txq_release(sc);
866err_bhal:
867 ath5k_hw_release_tx_queue(ah, sc->bhalq);
868err_desc:
869 ath5k_desc_free(sc, pdev);
870err:
871 return ret;
872}
873
874static void
875ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
876{
877 struct ath5k_softc *sc = hw->priv;
878
879 /*
880 * NB: the order of these is important:
881 * o call the 802.11 layer before detaching ath5k_hw to
882 * insure callbacks into the driver to delete global
883 * key cache entries can be handled
884 * o reclaim the tx queue data structures after calling
885 * the 802.11 layer as we'll get called back to reclaim
886 * node state and potentially want to use them
887 * o to cleanup the tx queues the hal is called, so detach
888 * it last
889 * XXX: ??? detach ath5k_hw ???
890 * Other than that, it's straightforward...
891 */
892 ieee80211_unregister_hw(hw);
893 ath5k_desc_free(sc, pdev);
894 ath5k_txq_release(sc);
895 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 896 ath5k_unregister_leds(sc);
fa1c114f
JS		 897
898 /*
899 * NB: can't reclaim these until after ieee80211_ifdetach
900 * returns because we'll get called back to reclaim node
901 * state and potentially want to use them.
902 */
903}
904
905
906
907
908/********************\
909* Channel/mode setup *
910\********************/
911
912/*
913 * Convert IEEE channel number to MHz frequency.
914 */
915static inline short
916ath5k_ieee2mhz(short chan)
917{
918 if (chan <= 14 || chan >= 27)
919 return ieee80211chan2mhz(chan);
920 else
921 return 2212 + chan * 20;
922}
923
42639fcd
BC		 924/*
925 * Returns true for the channel numbers used without all_channels modparam.
926 */
927static bool ath5k_is_standard_channel(short chan)
928{
929 return ((chan <= 14) ||
930 /* UNII 1,2 */
931 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
932 /* midband */
933 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
934 /* UNII-3 */
935 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
936}
937
fa1c114f
JS		 938static unsigned int
939ath5k_copy_channels(struct ath5k_hw *ah,
940 struct ieee80211_channel *channels,
941 unsigned int mode,
942 unsigned int max)
943{
d8ee398d 944 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 945
946 if (!test_bit(mode, ah->ah_modes))
947 return 0;
948
fa1c114f 949 switch (mode) {
d8ee398d
LR		 950 case AR5K_MODE_11A:
951 case AR5K_MODE_11A_TURBO:
fa1c114f 952 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 953 size = 220 ;
fa1c114f
JS		 954 chfreq = CHANNEL_5GHZ;
955 break;
d8ee398d
LR		 956 case AR5K_MODE_11B:
957 case AR5K_MODE_11G:
958 case AR5K_MODE_11G_TURBO:
959 size = 26;
fa1c114f
JS		 960 chfreq = CHANNEL_2GHZ;
961 break;
962 default:
963 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
964 return 0;
965 }
966
967 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 968 ch = i + 1 ;
969 freq = ath5k_ieee2mhz(ch);
fa1c114f 970
d8ee398d
LR		 971 /* Check if channel is supported by the chipset */
972 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 973 continue;
974
42639fcd
BC		 975 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
976 continue;
977
d8ee398d
LR		 978 /* Write channel info and increment counter */
979 channels[count].center_freq = freq;
a3f4b914
LR		 980 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
981 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 982 switch (mode) {
983 case AR5K_MODE_11A:
984 case AR5K_MODE_11G:
985 channels[count].hw_value = chfreq | CHANNEL_OFDM;
986 break;
987 case AR5K_MODE_11A_TURBO:
988 case AR5K_MODE_11G_TURBO:
989 channels[count].hw_value = chfreq |
990 CHANNEL_OFDM | CHANNEL_TURBO;
991 break;
992 case AR5K_MODE_11B:
d8ee398d
LR		 993 channels[count].hw_value = CHANNEL_B;
994 }
fa1c114f 995
fa1c114f
JS		 996 count++;
997 max--;
998 }
999
1000 return count;
1001}
1002
63266a65
BR		 1003static void
1004ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1005{
1006 u8 i;
1007
1008 for (i = 0; i < AR5K_MAX_RATES; i++)
1009 sc->rate_idx[b->band][i] = -1;
1010
1011 for (i = 0; i < b->n_bitrates; i++) {
1012 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1013 if (b->bitrates[i].hw_value_short)
1014 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1015 }
1016}
1017
d8ee398d 1018static int
63266a65 1019ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1020{
1021 struct ath5k_softc *sc = hw->priv;
d8ee398d 1022 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1023 struct ieee80211_supported_band *sband;
1024 int max_c, count_c = 0;
1025 int i;
fa1c114f 1026
d8ee398d 1027 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1028 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1029
1030 /* 2GHz band */
63266a65
BR		 1031 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1032 sband->band = IEEE80211_BAND_2GHZ;
1033 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1034
63266a65
BR		 1035 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1036 /* G mode */
1037 memcpy(sband->bitrates, &ath5k_rates[0],
1038 sizeof(struct ieee80211_rate) * 12);
1039 sband->n_bitrates = 12;
fa1c114f 1040
d8ee398d 1041 sband->channels = sc->channels;
d8ee398d 1042 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1043 AR5K_MODE_11G, max_c);
fa1c114f 1044
63266a65 1045 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1046 count_c = sband->n_channels;
63266a65
BR		 1047 max_c -= count_c;
1048 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1049 /* B mode */
1050 memcpy(sband->bitrates, &ath5k_rates[0],
1051 sizeof(struct ieee80211_rate) * 4);
1052 sband->n_bitrates = 4;
1053
1054 /* 5211 only supports B rates and uses 4bit rate codes
1055 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1056 * fix them up here:
1057 */
1058 if (ah->ah_version == AR5K_AR5211) {
1059 for (i = 0; i < 4; i++) {
1060 sband->bitrates[i].hw_value =
1061 sband->bitrates[i].hw_value & 0xF;
1062 sband->bitrates[i].hw_value_short =
1063 sband->bitrates[i].hw_value_short & 0xF;
1064 }
1065 }
fa1c114f 1066
63266a65
BR		 1067 sband->channels = sc->channels;
1068 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1069 AR5K_MODE_11B, max_c);
d8ee398d 1070
63266a65
BR		 1071 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1072 count_c = sband->n_channels;
d8ee398d 1073 max_c -= count_c;
fa1c114f 1074 }
63266a65 1075 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1076
63266a65 1077 /* 5GHz band, A mode */
400ec45a 1078 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1079 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1080 sband->band = IEEE80211_BAND_5GHZ;
1081 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1082
63266a65
BR		 1083 memcpy(sband->bitrates, &ath5k_rates[4],
1084 sizeof(struct ieee80211_rate) * 8);
1085 sband->n_bitrates = 8;
fa1c114f 1086
63266a65 1087 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1088 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1089 AR5K_MODE_11A, max_c);
1090
d8ee398d
LR		 1091 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1092 }
63266a65 1093 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1094
b446197c 1095 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1096
1097 return 0;
fa1c114f
JS		 1098}
1099
1100/*
e30eb4ab
JA		 1101 * Set/change channels. We always reset the chip.
1102 * To accomplish this we must first cleanup any pending DMA,
1103 * then restart stuff after a la ath5k_init.
be009370
BC		 1104 *
1105 * Called with sc->lock.
fa1c114f
JS		 1106 */
1107static int
1108ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1109{
d8ee398d
LR		 1110 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1111 sc->curchan->center_freq, chan->center_freq);
1112
e30eb4ab
JA		 1113 /*
1114 * To switch channels clear any pending DMA operations;
1115 * wait long enough for the RX fifo to drain, reset the
1116 * hardware at the new frequency, and then re-enable
1117 * the relevant bits of the h/w.
1118 */
1119 return ath5k_reset(sc, chan);
fa1c114f
JS		 1120}
1121
1122static void
1123ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1124{
fa1c114f 1125 sc->curmode = mode;
d8ee398d 1126
400ec45a 1127 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1128 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1129 } else {
1130 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1131 }
fa1c114f
JS		 1132}
1133
1134static void
1135ath5k_mode_setup(struct ath5k_softc *sc)
1136{
1137 struct ath5k_hw *ah = sc->ah;
1138 u32 rfilt;
1139
ae6f53f2
BC		 1140 ah->ah_op_mode = sc->opmode;
1141
fa1c114f
JS		 1142 /* configure rx filter */
1143 rfilt = sc->filter_flags;
1144 ath5k_hw_set_rx_filter(ah, rfilt);
1145
1146 if (ath5k_hw_hasbssidmask(ah))
1147 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1148
1149 /* configure operational mode */
1150 ath5k_hw_set_opmode(ah);
1151
fa1c114f
JS		 1152 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1153}
1154
d8ee398d 1155static inline int
63266a65
BR		 1156ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1157{
b7266047
BC		 1158 int rix;
1159
1160 /* return base rate on errors */
1161 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1162 "hw_rix out of bounds: %x\n", hw_rix))
1163 return 0;
1164
1165 rix = sc->rate_idx[sc->curband->band][hw_rix];
1166 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1167 rix = 0;
1168
1169 return rix;
d8ee398d
LR		 1170}
1171
fa1c114f
JS		 1172/***************\
1173* Buffers setup *
1174\***************/
1175
b6ea0356
BC		 1176static
1177struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1178{
db719718 1179 struct ath_common *common = ath5k_hw_common(sc->ah);
b6ea0356 1180 struct sk_buff *skb;
b6ea0356
BC		 1181
1182 /*
1183 * Allocate buffer with headroom_needed space for the
1184 * fake physical layer header at the start.
1185 */
db719718 1186 skb = ath_rxbuf_alloc(common,
dd849782 1187 common->rx_bufsize,
aeb63cfd 1188 GFP_ATOMIC);
b6ea0356
BC		 1189
1190 if (!skb) {
1191 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
dd849782 1192 common->rx_bufsize);
b6ea0356
BC		 1193 return NULL;
1194 }
b6ea0356
BC		 1195
1196 *skb_addr = pci_map_single(sc->pdev,
cc861f74
LR		 1197 skb->data, common->rx_bufsize,
1198 PCI_DMA_FROMDEVICE);
b6ea0356
BC		 1199 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1200 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1201 dev_kfree_skb(skb);
1202 return NULL;
1203 }
1204 return skb;
1205}
1206
fa1c114f
JS		 1207static int
1208ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1209{
1210 struct ath5k_hw *ah = sc->ah;
1211 struct sk_buff *skb = bf->skb;
1212 struct ath5k_desc *ds;
1213
b6ea0356
BC		 1214 if (!skb) {
1215 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1216 if (!skb)
fa1c114f 1217 return -ENOMEM;
fa1c114f 1218 bf->skb = skb;
fa1c114f
JS		 1219 }
1220
1221 /*
1222 * Setup descriptors. For receive we always terminate
1223 * the descriptor list with a self-linked entry so we'll
1224 * not get overrun under high load (as can happen with a
1225 * 5212 when ANI processing enables PHY error frames).
1226 *
1227 * To insure the last descriptor is self-linked we create
1228 * each descriptor as self-linked and add it to the end. As
1229 * each additional descriptor is added the previous self-linked
1230 * entry is ``fixed'' naturally. This should be safe even
1231 * if DMA is happening. When processing RX interrupts we
1232 * never remove/process the last, self-linked, entry on the
1233 * descriptor list. This insures the hardware always has
1234 * someplace to write a new frame.
1235 */
1236 ds = bf->desc;
1237 ds->ds_link = bf->daddr; /* link to self */
1238 ds->ds_data = bf->skbaddr;
c6e387a2 1239 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1240 skb_tailroom(skb), /* buffer size */
1241 0);
1242
1243 if (sc->rxlink != NULL)
1244 *sc->rxlink = bf->daddr;
1245 sc->rxlink = &ds->ds_link;
1246 return 0;
1247}
1248
1249static int
cec8db23
BC		 1250ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1251 struct ath5k_txq *txq)
fa1c114f
JS		 1252{
1253 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1254 struct ath5k_desc *ds = bf->desc;
1255 struct sk_buff *skb = bf->skb;
a888d52d 1256 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1257 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1258 struct ieee80211_rate *rate;
1259 unsigned int mrr_rate[3], mrr_tries[3];
1260 int i, ret;
8902ff4e 1261 u16 hw_rate;
07c1e852
BC		 1262 u16 cts_rate = 0;
1263 u16 duration = 0;
8902ff4e 1264 u8 rc_flags;
fa1c114f
JS		 1265
1266 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1267
fa1c114f
JS		 1268 /* XXX endianness */
1269 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1270 PCI_DMA_TODEVICE);
1271
8902ff4e
BC		 1272 rate = ieee80211_get_tx_rate(sc->hw, info);
1273
e039fa4a 1274 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1275 flags |= AR5K_TXDESC_NOACK;
1276
8902ff4e
BC		 1277 rc_flags = info->control.rates[0].flags;
1278 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1279 rate->hw_value_short : rate->hw_value;
1280
281c56dd 1281 pktlen = skb->len;
fa1c114f 1282
8f655dde
NK		 1283 /* FIXME: If we are in g mode and rate is a CCK rate
1284 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1285 * from tx power (value is in dB units already) */
362695e1
BC		 1286 if (info->control.hw_key) {
1287 keyidx = info->control.hw_key->hw_key_idx;
1288 pktlen += info->control.hw_key->icv_len;
1289 }
07c1e852
BC		 1290 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1291 flags |= AR5K_TXDESC_RTSENA;
1292 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1293 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1294 sc->vif, pktlen, info));
1295 }
1296 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1297 flags |= AR5K_TXDESC_CTSENA;
1298 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1299 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1300 sc->vif, pktlen, info));
1301 }
fa1c114f
JS		 1302 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1303 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1304 (sc->power_level * 2),
8902ff4e 1305 hw_rate,
2bed03eb 1306 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1307 cts_rate, duration);
fa1c114f
JS		 1308 if (ret)
1309 goto err_unmap;
1310
2f7fe870
FF		 1311 memset(mrr_rate, 0, sizeof(mrr_rate));
1312 memset(mrr_tries, 0, sizeof(mrr_tries));
1313 for (i = 0; i < 3; i++) {
1314 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1315 if (!rate)
1316 break;
1317
1318 mrr_rate[i] = rate->hw_value;
e6a9854b 1319 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1320 }
1321
1322 ah->ah_setup_mrr_tx_desc(ah, ds,
1323 mrr_rate[0], mrr_tries[0],
1324 mrr_rate[1], mrr_tries[1],
1325 mrr_rate[2], mrr_tries[2]);
1326
fa1c114f
JS		 1327 ds->ds_link = 0;
1328 ds->ds_data = bf->skbaddr;
1329
1330 spin_lock_bh(&txq->lock);
1331 list_add_tail(&bf->list, &txq->q);
57ffc589 1332 sc->tx_stats[txq->qnum].len++;
fa1c114f 1333 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1334 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1335 else /* no, so only link it */
1336 *txq->link = bf->daddr;
1337
1338 txq->link = &ds->ds_link;
c6e387a2 1339 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1340 mmiowb();
fa1c114f
JS		 1341 spin_unlock_bh(&txq->lock);
1342
1343 return 0;
1344err_unmap:
1345 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1346 return ret;
1347}
1348
1349/*******************\
1350* Descriptors setup *
1351\*******************/
1352
1353static int
1354ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1355{
1356 struct ath5k_desc *ds;
1357 struct ath5k_buf *bf;
1358 dma_addr_t da;
1359 unsigned int i;
1360 int ret;
1361
1362 /* allocate descriptors */
1363 sc->desc_len = sizeof(struct ath5k_desc) *
1364 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1365 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1366 if (sc->desc == NULL) {
1367 ATH5K_ERR(sc, "can't allocate descriptors\n");
1368 ret = -ENOMEM;
1369 goto err;
1370 }
1371 ds = sc->desc;
1372 da = sc->desc_daddr;
1373 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1374 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1375
1376 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1377 sizeof(struct ath5k_buf), GFP_KERNEL);
1378 if (bf == NULL) {
1379 ATH5K_ERR(sc, "can't allocate bufptr\n");
1380 ret = -ENOMEM;
1381 goto err_free;
1382 }
1383 sc->bufptr = bf;
1384
1385 INIT_LIST_HEAD(&sc->rxbuf);
1386 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1387 bf->desc = ds;
1388 bf->daddr = da;
1389 list_add_tail(&bf->list, &sc->rxbuf);
1390 }
1391
1392 INIT_LIST_HEAD(&sc->txbuf);
1393 sc->txbuf_len = ATH_TXBUF;
1394 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1395 da += sizeof(*ds)) {
1396 bf->desc = ds;
1397 bf->daddr = da;
1398 list_add_tail(&bf->list, &sc->txbuf);
1399 }
1400
1401 /* beacon buffer */
1402 bf->desc = ds;
1403 bf->daddr = da;
1404 sc->bbuf = bf;
1405
1406 return 0;
1407err_free:
1408 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1409err:
1410 sc->desc = NULL;
1411 return ret;
1412}
1413
1414static void
1415ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1416{
1417 struct ath5k_buf *bf;
1418
1419 ath5k_txbuf_free(sc, sc->bbuf);
1420 list_for_each_entry(bf, &sc->txbuf, list)
1421 ath5k_txbuf_free(sc, bf);
1422 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1423 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1424
1425 /* Free memory associated with all descriptors */
1426 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1427
1428 kfree(sc->bufptr);
1429 sc->bufptr = NULL;
1430}
1431
1432
1433
1434
1435
1436/**************\
1437* Queues setup *
1438\**************/
1439
1440static struct ath5k_txq *
1441ath5k_txq_setup(struct ath5k_softc *sc,
1442 int qtype, int subtype)
1443{
1444 struct ath5k_hw *ah = sc->ah;
1445 struct ath5k_txq *txq;
1446 struct ath5k_txq_info qi = {
1447 .tqi_subtype = subtype,
1448 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1449 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1450 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1451 };
1452 int qnum;
1453
1454 /*
1455 * Enable interrupts only for EOL and DESC conditions.
1456 * We mark tx descriptors to receive a DESC interrupt
1457 * when a tx queue gets deep; otherwise waiting for the
1458 * EOL to reap descriptors. Note that this is done to
1459 * reduce interrupt load and this only defers reaping
1460 * descriptors, never transmitting frames. Aside from
1461 * reducing interrupts this also permits more concurrency.
1462 * The only potential downside is if the tx queue backs
1463 * up in which case the top half of the kernel may backup
1464 * due to a lack of tx descriptors.
1465 */
1466 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1467 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1468 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1469 if (qnum < 0) {
1470 /*
1471 * NB: don't print a message, this happens
1472 * normally on parts with too few tx queues
1473 */
1474 return ERR_PTR(qnum);
1475 }
1476 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1477 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1478 qnum, ARRAY_SIZE(sc->txqs));
1479 ath5k_hw_release_tx_queue(ah, qnum);
1480 return ERR_PTR(-EINVAL);
1481 }
1482 txq = &sc->txqs[qnum];
1483 if (!txq->setup) {
1484 txq->qnum = qnum;
1485 txq->link = NULL;
1486 INIT_LIST_HEAD(&txq->q);
1487 spin_lock_init(&txq->lock);
1488 txq->setup = true;
1489 }
1490 return &sc->txqs[qnum];
1491}
1492
1493static int
1494ath5k_beaconq_setup(struct ath5k_hw *ah)
1495{
1496 struct ath5k_txq_info qi = {
1497 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1498 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1499 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1500 /* NB: for dynamic turbo, don't enable any other interrupts */
1501 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1502 };
1503
1504 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1505}
1506
1507static int
1508ath5k_beaconq_config(struct ath5k_softc *sc)
1509{
1510 struct ath5k_hw *ah = sc->ah;
1511 struct ath5k_txq_info qi;
1512 int ret;
1513
1514 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1515 if (ret)
1516 return ret;
05c914fe
JB		 1517 if (sc->opmode == NL80211_IFTYPE_AP ||
1518 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1519 /*
1520 * Always burst out beacon and CAB traffic
1521 * (aifs = cwmin = cwmax = 0)
1522 */
1523 qi.tqi_aifs = 0;
1524 qi.tqi_cw_min = 0;
1525 qi.tqi_cw_max = 0;
05c914fe 1526 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1527 /*
1528 * Adhoc mode; backoff between 0 and (2 * cw_min).
1529 */
1530 qi.tqi_aifs = 0;
1531 qi.tqi_cw_min = 0;
1532 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1533 }
1534
6d91e1d8
BR		 1535 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1536 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1537 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1538
c6e387a2 1539 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1540 if (ret) {
1541 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1542 "hardware queue!\n", __func__);
1543 return ret;
1544 }
1545
1546 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1547}
1548
1549static void
1550ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1551{
1552 struct ath5k_buf *bf, *bf0;
1553
1554 /*
1555 * NB: this assumes output has been stopped and
1556 * we do not need to block ath5k_tx_tasklet
1557 */
1558 spin_lock_bh(&txq->lock);
1559 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1560 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1561
1562 ath5k_txbuf_free(sc, bf);
1563
1564 spin_lock_bh(&sc->txbuflock);
57ffc589 1565 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1566 list_move_tail(&bf->list, &sc->txbuf);
1567 sc->txbuf_len++;
1568 spin_unlock_bh(&sc->txbuflock);
1569 }
1570 txq->link = NULL;
1571 spin_unlock_bh(&txq->lock);
1572}
1573
1574/*
1575 * Drain the transmit queues and reclaim resources.
1576 */
1577static void
1578ath5k_txq_cleanup(struct ath5k_softc *sc)
1579{
1580 struct ath5k_hw *ah = sc->ah;
1581 unsigned int i;
1582
1583 /* XXX return value */
1584 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1585 /* don't touch the hardware if marked invalid */
1586 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1587 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1588 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1589 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1590 if (sc->txqs[i].setup) {
1591 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1592 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1593 "link %p\n",
1594 sc->txqs[i].qnum,
c6e387a2 1595 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1596 sc->txqs[i].qnum),
1597 sc->txqs[i].link);
1598 }
1599 }
36d6825b 1600 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1601
1602 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1603 if (sc->txqs[i].setup)
1604 ath5k_txq_drainq(sc, &sc->txqs[i]);
1605}
1606
1607static void
1608ath5k_txq_release(struct ath5k_softc *sc)
1609{
1610 struct ath5k_txq *txq = sc->txqs;
1611 unsigned int i;
1612
1613 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1614 if (txq->setup) {
1615 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1616 txq->setup = false;
1617 }
1618}
1619
1620
1621
1622
1623/*************\
1624* RX Handling *
1625\*************/
1626
1627/*
1628 * Enable the receive h/w following a reset.
1629 */
1630static int
1631ath5k_rx_start(struct ath5k_softc *sc)
1632{
1633 struct ath5k_hw *ah = sc->ah;
db719718 1634 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 1635 struct ath5k_buf *bf;
1636 int ret;
1637
cc861f74 1638 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
fa1c114f 1639
cc861f74
LR		 1640 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1641 common->cachelsz, common->rx_bufsize);
fa1c114f 1642
fa1c114f 1643 spin_lock_bh(&sc->rxbuflock);
26925042 1644 sc->rxlink = NULL;
fa1c114f
JS		 1645 list_for_each_entry(bf, &sc->rxbuf, list) {
1646 ret = ath5k_rxbuf_setup(sc, bf);
1647 if (ret != 0) {
1648 spin_unlock_bh(&sc->rxbuflock);
1649 goto err;
1650 }
1651 }
1652 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1653 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1654 spin_unlock_bh(&sc->rxbuflock);
1655
c6e387a2 1656 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1657 ath5k_mode_setup(sc); /* set filters, etc. */
1658 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1659
1660 return 0;
1661err:
1662 return ret;
1663}
1664
1665/*
1666 * Disable the receive h/w in preparation for a reset.
1667 */
1668static void
1669ath5k_rx_stop(struct ath5k_softc *sc)
1670{
1671 struct ath5k_hw *ah = sc->ah;
1672
c6e387a2 1673 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1674 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1675 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1676
1677 ath5k_debug_printrxbuffs(sc, ah);
1678
1679 sc->rxlink = NULL; /* just in case */
1680}
1681
1682static unsigned int
1683ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1684 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f 1685{
dc1e001b
LR		 1686 struct ath5k_hw *ah = sc->ah;
1687 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1688 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1689 unsigned int keyix, hlen;
fa1c114f 1690
b47f407b
BR		 1691 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1692 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1693 return RX_FLAG_DECRYPTED;
1694
1695 /* Apparently when a default key is used to decrypt the packet
1696 the hw does not set the index used to decrypt. In such cases
1697 get the index from the packet. */
798ee985 1698 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1699 if (ieee80211_has_protected(hdr->frame_control) &&
1700 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1701 skb->len >= hlen + 4) {
fa1c114f
JS		 1702 keyix = skb->data[hlen + 3] >> 6;
1703
dc1e001b 1704 if (test_bit(keyix, common->keymap))
fa1c114f
JS		 1705 return RX_FLAG_DECRYPTED;
1706 }
1707
1708 return 0;
1709}
1710
036cd1ec
BR		 1711
1712static void
6ba81c2c
BR		 1713ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1714 struct ieee80211_rx_status *rxs)
036cd1ec 1715{
954fecea 1716 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1717 u64 tsf, bc_tstamp;
036cd1ec
BR		 1718 u32 hw_tu;
1719 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1720
24b56e70 1721 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1722 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1723 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1724 /*
6ba81c2c
BR		 1725 * Received an IBSS beacon with the same BSSID. Hardware *must*
1726 * have updated the local TSF. We have to work around various
1727 * hardware bugs, though...
036cd1ec 1728 */
6ba81c2c
BR		 1729 tsf = ath5k_hw_get_tsf64(sc->ah);
1730 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1731 hw_tu = TSF_TO_TU(tsf);
1732
1733 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1734 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1735 (unsigned long long)bc_tstamp,
1736 (unsigned long long)rxs->mactime,
1737 (unsigned long long)(rxs->mactime - bc_tstamp),
1738 (unsigned long long)tsf);
6ba81c2c
BR		 1739
1740 /*
1741 * Sometimes the HW will give us a wrong tstamp in the rx
1742 * status, causing the timestamp extension to go wrong.
1743 * (This seems to happen especially with beacon frames bigger
1744 * than 78 byte (incl. FCS))
1745 * But we know that the receive timestamp must be later than the
1746 * timestamp of the beacon since HW must have synced to that.
1747 *
1748 * NOTE: here we assume mactime to be after the frame was
1749 * received, not like mac80211 which defines it at the start.
1750 */
1751 if (bc_tstamp > rxs->mactime) {
036cd1ec 1752 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1753 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1754 (unsigned long long)rxs->mactime,
1755 (unsigned long long)tsf);
6ba81c2c 1756 rxs->mactime = tsf;
036cd1ec 1757 }
6ba81c2c
BR		 1758
1759 /*
1760 * Local TSF might have moved higher than our beacon timers,
1761 * in that case we have to update them to continue sending
1762 * beacons. This also takes care of synchronizing beacon sending
1763 * times with other stations.
1764 */
1765 if (hw_tu >= sc->nexttbtt)
1766 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1767 }
1768}
1769
fa1c114f
JS		 1770static void
1771ath5k_tasklet_rx(unsigned long data)
1772{
1c5256bb 1773 struct ieee80211_rx_status *rxs;
b47f407b 1774 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1775 struct sk_buff *skb, *next_skb;
1776 dma_addr_t next_skb_addr;
fa1c114f 1777 struct ath5k_softc *sc = (void *)data;
cc861f74
LR		 1778 struct ath5k_hw *ah = sc->ah;
1779 struct ath_common *common = ath5k_hw_common(ah);
c57ca815 1780 struct ath5k_buf *bf;
fa1c114f 1781 struct ath5k_desc *ds;
fa1c114f
JS		 1782 int ret;
1783 int hdrlen;
0fe45b1d 1784 int padsize;
1c5256bb 1785 int rx_flag;
fa1c114f
JS		 1786
1787 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1788 if (list_empty(&sc->rxbuf)) {
1789 ATH5K_WARN(sc, "empty rx buf pool\n");
1790 goto unlock;
1791 }
fa1c114f 1792 do {
1c5256bb 1793 rx_flag = 0;
d6894b5b 1794
fa1c114f
JS		 1795 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1796 BUG_ON(bf->skb == NULL);
1797 skb = bf->skb;
1798 ds = bf->desc;
1799
c57ca815
BC		 1800 /* bail if HW is still using self-linked descriptor */
1801 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1802 break;
fa1c114f 1803
b47f407b 1804 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1805 if (unlikely(ret == -EINPROGRESS))
1806 break;
1807 else if (unlikely(ret)) {
1808 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1809 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1810 return;
1811 }
1812
b47f407b 1813 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1814 ATH5K_WARN(sc, "unsupported jumbo\n");
1815 goto next;
1816 }
1817
b47f407b
BR		 1818 if (unlikely(rs.rs_status)) {
1819 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1820 goto next;
b47f407b 1821 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1822 /*
1823 * Decrypt error. If the error occurred
1824 * because there was no hardware key, then
1825 * let the frame through so the upper layers
1826 * can process it. This is necessary for 5210
1827 * parts which have no way to setup a ``clear''
1828 * key cache entry.
1829 *
1830 * XXX do key cache faulting
1831 */
b47f407b
BR		 1832 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1833 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1834 goto accept;
1835 }
b47f407b 1836 if (rs.rs_status & AR5K_RXERR_MIC) {
1c5256bb 1837 rx_flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1838 goto accept;
1839 }
1840
1841 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1842 if ((rs.rs_status &
1843 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1844 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1845 goto next;
1846 }
1847accept:
b6ea0356
BC		 1848 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1849
1850 /*
1851 * If we can't replace bf->skb with a new skb under memory
1852 * pressure, just skip this packet
1853 */
1854 if (!next_skb)
1855 goto next;
1856
cc861f74 1857 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
fa1c114f 1858 PCI_DMA_FROMDEVICE);
b47f407b 1859 skb_put(skb, rs.rs_datalen);
fa1c114f 1860
0fe45b1d
BP		 1861 /* The MAC header is padded to have 32-bit boundary if the
1862 * packet payload is non-zero. The general calculation for
1863 * padsize would take into account odd header lengths:
1864 * padsize = (4 - hdrlen % 4) % 4; However, since only
1865 * even-length headers are used, padding can only be 0 or 2
1866 * bytes and we can optimize this a bit. In addition, we must
1867 * not try to remove padding from short control frames that do
1868 * not have payload. */
fa1c114f 1869 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1870 padsize = ath5k_pad_size(hdrlen);
1871 if (padsize) {
0fe45b1d
BP		 1872 memmove(skb->data + padsize, skb->data, hdrlen);
1873 skb_pull(skb, padsize);
fa1c114f 1874 }
1c5256bb 1875 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 1876
c0e1899b
BR		 1877 /*
1878 * always extend the mac timestamp, since this information is
1879 * also needed for proper IBSS merging.
1880 *
1881 * XXX: it might be too late to do it here, since rs_tstamp is
1882 * 15bit only. that means TSF extension has to be done within
1883 * 32768usec (about 32ms). it might be necessary to move this to
1884 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1885 *
1886 * Unfortunately we don't know when the hardware takes the rx
1887 * timestamp (beginning of phy frame, data frame, end of rx?).
1888 * The only thing we know is that it is hardware specific...
1889 * On AR5213 it seems the rx timestamp is at the end of the
1890 * frame, but i'm not sure.
1891 *
1892 * NOTE: mac80211 defines mactime at the beginning of the first
1893 * data symbol. Since we don't have any time references it's
1894 * impossible to comply to that. This affects IBSS merge only
1895 * right now, so it's not too bad...
c0e1899b 1896 */
1c5256bb
BC		 1897 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1898 rxs->flag = rx_flag | RX_FLAG_TSFT;
c0e1899b 1899
1c5256bb
BC		 1900 rxs->freq = sc->curchan->center_freq;
1901 rxs->band = sc->curband->band;
fa1c114f 1902
1c5256bb
BC		 1903 rxs->noise = sc->ah->ah_noise_floor;
1904 rxs->signal = rxs->noise + rs.rs_rssi;
6e0e0bf8
LR		 1905
1906 /* An rssi of 35 indicates you should be able use
1907 * 54 Mbps reliably. A more elaborate scheme can be used
1908 * here but it requires a map of SNR/throughput for each
1909 * possible mode used */
1c5256bb 1910 rxs->qual = rs.rs_rssi * 100 / 35;
6e0e0bf8
LR		 1911
1912 /* rssi can be more than 35 though, anything above that
1913 * should be considered at 100% */
1c5256bb
BC		 1914 if (rxs->qual > 100)
1915 rxs->qual = 100;
fa1c114f 1916
1c5256bb
BC		 1917 rxs->antenna = rs.rs_antenna;
1918 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1919 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1920
1c5256bb
BC		 1921 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1922 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1923 rxs->flag |= RX_FLAG_SHORTPRE;
06303352 1924
fa1c114f
JS		 1925 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1926
036cd1ec 1927 /* check beacons in IBSS mode */
05c914fe 1928 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1c5256bb 1929 ath5k_check_ibss_tsf(sc, skb, rxs);
036cd1ec 1930
f1d58c25 1931 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 1932
1933 bf->skb = next_skb;
1934 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1935next:
1936 list_move_tail(&bf->list, &sc->rxbuf);
1937 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1938unlock:
fa1c114f
JS		 1939 spin_unlock(&sc->rxbuflock);
1940}
1941
1942
1943
1944
1945/*************\
1946* TX Handling *
1947\*************/
1948
1949static void
1950ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1951{
b47f407b 1952 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1953 struct ath5k_buf *bf, *bf0;
1954 struct ath5k_desc *ds;
1955 struct sk_buff *skb;
e039fa4a 1956 struct ieee80211_tx_info *info;
2f7fe870 1957 int i, ret;
fa1c114f
JS		 1958
1959 spin_lock(&txq->lock);
1960 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1961 ds = bf->desc;
1962
b47f407b 1963 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1964 if (unlikely(ret == -EINPROGRESS))
1965 break;
1966 else if (unlikely(ret)) {
1967 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1968 ret, txq->qnum);
1969 break;
1970 }
1971
1972 skb = bf->skb;
a888d52d 1973 info = IEEE80211_SKB_CB(skb);
fa1c114f 1974 bf->skb = NULL;
e039fa4a 1975
fa1c114f
JS		 1976 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1977 PCI_DMA_TODEVICE);
1978
e6a9854b 1979 ieee80211_tx_info_clear_status(info);
2f7fe870 1980 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1981 struct ieee80211_tx_rate *r =
1982 &info->status.rates[i];
2f7fe870
FF		 1983
1984 if (ts.ts_rate[i]) {
e6a9854b
JB		 1985 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1986 r->count = ts.ts_retry[i];
2f7fe870 1987 } else {
e6a9854b
JB		 1988 r->idx = -1;
1989 r->count = 0;
2f7fe870
FF		 1990 }
1991 }
1992
e6a9854b
JB		 1993 /* count the successful attempt as well */
1994 info->status.rates[ts.ts_final_idx].count++;
1995
b47f407b 1996 if (unlikely(ts.ts_status)) {
fa1c114f 1997 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1998 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1999 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 2000 } else {
e039fa4a
JB		 2001 info->flags |= IEEE80211_TX_STAT_ACK;
2002 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2003 }
2004
e039fa4a 2005 ieee80211_tx_status(sc->hw, skb);
57ffc589 2006 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 2007
2008 spin_lock(&sc->txbuflock);
57ffc589 2009 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 2010 list_move_tail(&bf->list, &sc->txbuf);
2011 sc->txbuf_len++;
2012 spin_unlock(&sc->txbuflock);
2013 }
2014 if (likely(list_empty(&txq->q)))
2015 txq->link = NULL;
2016 spin_unlock(&txq->lock);
2017 if (sc->txbuf_len > ATH_TXBUF / 5)
2018 ieee80211_wake_queues(sc->hw);
2019}
2020
2021static void
2022ath5k_tasklet_tx(unsigned long data)
2023{
8784d2ee 2024 int i;
fa1c114f
JS		 2025 struct ath5k_softc *sc = (void *)data;
2026
8784d2ee
BC		 2027 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2028 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2029 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2030}
2031
2032
fa1c114f
JS		 2033/*****************\
2034* Beacon handling *
2035\*****************/
2036
2037/*
2038 * Setup the beacon frame for transmit.
2039 */
2040static int
e039fa4a 2041ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2042{
2043 struct sk_buff *skb = bf->skb;
a888d52d 2044 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2045 struct ath5k_hw *ah = sc->ah;
2046 struct ath5k_desc *ds;
2bed03eb
NK		 2047 int ret = 0;
2048 u8 antenna;
fa1c114f
JS		 2049 u32 flags;
2050
2051 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2052 PCI_DMA_TODEVICE);
2053 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2054 "skbaddr %llx\n", skb, skb->data, skb->len,
2055 (unsigned long long)bf->skbaddr);
8d8bb39b 2056 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2057 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2058 return -EIO;
2059 }
2060
2061 ds = bf->desc;
2bed03eb 2062 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2063
2064 flags = AR5K_TXDESC_NOACK;
05c914fe 2065 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2066 ds->ds_link = bf->daddr; /* self-linked */
2067 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2068 } else
fa1c114f 2069 ds->ds_link = 0;
2bed03eb
NK		 2070
2071 /*
2072 * If we use multiple antennas on AP and use
2073 * the Sectored AP scenario, switch antenna every
2074 * 4 beacons to make sure everybody hears our AP.
2075 * When a client tries to associate, hw will keep
2076 * track of the tx antenna to be used for this client
2077 * automaticaly, based on ACKed packets.
2078 *
2079 * Note: AP still listens and transmits RTS on the
2080 * default antenna which is supposed to be an omni.
2081 *
2082 * Note2: On sectored scenarios it's possible to have
2083 * multiple antennas (1omni -the default- and 14 sectors)
2084 * so if we choose to actually support this mode we need
2085 * to allow user to set how many antennas we have and tweak
2086 * the code below to send beacons on all of them.
2087 */
2088 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2089 antenna = sc->bsent & 4 ? 2 : 1;
2090
fa1c114f 2091
8f655dde
NK		 2092 /* FIXME: If we are in g mode and rate is a CCK rate
2093 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2094 * from tx power (value is in dB units already) */
fa1c114f 2095 ds->ds_data = bf->skbaddr;
281c56dd 2096 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2097 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2098 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2099 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2100 1, AR5K_TXKEYIX_INVALID,
400ec45a 2101 antenna, flags, 0, 0);
fa1c114f
JS		 2102 if (ret)
2103 goto err_unmap;
2104
2105 return 0;
2106err_unmap:
2107 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2108 return ret;
2109}
2110
2111/*
2112 * Transmit a beacon frame at SWBA. Dynamic updates to the
2113 * frame contents are done as needed and the slot time is
2114 * also adjusted based on current state.
2115 *
acf3c1a5
BC		 2116 * This is called from software irq context (beacontq or restq
2117 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2118 */
2119static void
2120ath5k_beacon_send(struct ath5k_softc *sc)
2121{
2122 struct ath5k_buf *bf = sc->bbuf;
2123 struct ath5k_hw *ah = sc->ah;
cec8db23 2124 struct sk_buff *skb;
fa1c114f 2125
be9b7259 2126 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2127
05c914fe
JB		 2128 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2129 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2130 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2131 return;
2132 }
2133 /*
2134 * Check if the previous beacon has gone out. If
2135 * not don't don't try to post another, skip this
2136 * period and wait for the next. Missed beacons
2137 * indicate a problem and should not occur. If we
2138 * miss too many consecutive beacons reset the device.
2139 */
2140 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2141 sc->bmisscount++;
be9b7259 2142 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2143 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2144 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2145 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2146 "stuck beacon time (%u missed)\n",
2147 sc->bmisscount);
2148 tasklet_schedule(&sc->restq);
2149 }
2150 return;
2151 }
2152 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2153 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2154 "resume beacon xmit after %u misses\n",
2155 sc->bmisscount);
2156 sc->bmisscount = 0;
2157 }
2158
2159 /*
2160 * Stop any current dma and put the new frame on the queue.
2161 * This should never fail since we check above that no frames
2162 * are still pending on the queue.
2163 */
2164 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2165 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2166 /* NB: hw still stops DMA, so proceed */
2167 }
fa1c114f 2168
1071db86
BC		 2169 /* refresh the beacon for AP mode */
2170 if (sc->opmode == NL80211_IFTYPE_AP)
2171 ath5k_beacon_update(sc->hw, sc->vif);
2172
c6e387a2
NK		 2173 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2174 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2175 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2176 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2177
cec8db23
BC		 2178 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2179 while (skb) {
2180 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2181 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2182 }
2183
fa1c114f
JS		 2184 sc->bsent++;
2185}
2186
2187
9804b98d
BR		 2188/**
2189 * ath5k_beacon_update_timers - update beacon timers
2190 *
2191 * @sc: struct ath5k_softc pointer we are operating on
2192 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2193 * beacon timer update based on the current HW TSF.
2194 *
2195 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2196 * of a received beacon or the current local hardware TSF and write it to the
2197 * beacon timer registers.
2198 *
2199 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2200 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2201 * when we otherwise know we have to update the timers, but we keep it in this
2202 * function to have it all together in one place.
2203 */
fa1c114f 2204static void
9804b98d 2205ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2206{
2207 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2208 u32 nexttbtt, intval, hw_tu, bc_tu;
2209 u64 hw_tsf;
fa1c114f
JS		 2210
2211 intval = sc->bintval & AR5K_BEACON_PERIOD;
2212 if (WARN_ON(!intval))
2213 return;
2214
9804b98d
BR		 2215 /* beacon TSF converted to TU */
2216 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2217
9804b98d
BR		 2218 /* current TSF converted to TU */
2219 hw_tsf = ath5k_hw_get_tsf64(ah);
2220 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2221
9804b98d
BR		 2222#define FUDGE 3
2223 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2224 if (bc_tsf == -1) {
2225 /*
2226 * no beacons received, called internally.
2227 * just need to refresh timers based on HW TSF.
2228 */
2229 nexttbtt = roundup(hw_tu + FUDGE, intval);
2230 } else if (bc_tsf == 0) {
2231 /*
2232 * no beacon received, probably called by ath5k_reset_tsf().
2233 * reset TSF to start with 0.
2234 */
2235 nexttbtt = intval;
2236 intval |= AR5K_BEACON_RESET_TSF;
2237 } else if (bc_tsf > hw_tsf) {
2238 /*
2239 * beacon received, SW merge happend but HW TSF not yet updated.
2240 * not possible to reconfigure timers yet, but next time we
2241 * receive a beacon with the same BSSID, the hardware will
2242 * automatically update the TSF and then we need to reconfigure
2243 * the timers.
2244 */
2245 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2246 "need to wait for HW TSF sync\n");
2247 return;
2248 } else {
2249 /*
2250 * most important case for beacon synchronization between STA.
2251 *
2252 * beacon received and HW TSF has been already updated by HW.
2253 * update next TBTT based on the TSF of the beacon, but make
2254 * sure it is ahead of our local TSF timer.
2255 */
2256 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2257 }
2258#undef FUDGE
fa1c114f 2259
036cd1ec
BR		 2260 sc->nexttbtt = nexttbtt;
2261
fa1c114f 2262 intval |= AR5K_BEACON_ENA;
fa1c114f 2263 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2264
2265 /*
2266 * debugging output last in order to preserve the time critical aspect
2267 * of this function
2268 */
2269 if (bc_tsf == -1)
2270 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2271 "reconfigured timers based on HW TSF\n");
2272 else if (bc_tsf == 0)
2273 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2274 "reset HW TSF and timers\n");
2275 else
2276 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2277 "updated timers based on beacon TSF\n");
2278
2279 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2280 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2281 (unsigned long long) bc_tsf,
2282 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2283 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2284 intval & AR5K_BEACON_PERIOD,
2285 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2286 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2287}
2288
2289
036cd1ec
BR		 2290/**
2291 * ath5k_beacon_config - Configure the beacon queues and interrupts
2292 *
2293 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2294 *
036cd1ec 2295 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2296 * interrupts to detect TSF updates only.
fa1c114f
JS		 2297 */
2298static void
2299ath5k_beacon_config(struct ath5k_softc *sc)
2300{
2301 struct ath5k_hw *ah = sc->ah;
b5f03956 2302 unsigned long flags;
fa1c114f 2303
21800491 2304 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2305 sc->bmisscount = 0;
dc1968e7 2306 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2307
21800491 2308 if (sc->enable_beacon) {
fa1c114f 2309 /*
036cd1ec
BR		 2310 * In IBSS mode we use a self-linked tx descriptor and let the
2311 * hardware send the beacons automatically. We have to load it
fa1c114f 2312 * only once here.
036cd1ec 2313 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2314 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2315 */
2316 ath5k_beaconq_config(sc);
fa1c114f 2317
036cd1ec
BR		 2318 sc->imask |= AR5K_INT_SWBA;
2319
da966bca 2320 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2321 if (ath5k_hw_hasveol(ah))
da966bca 2322 ath5k_beacon_send(sc);
da966bca
JS		 2323 } else
2324 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2325 } else {
2326 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2327 }
fa1c114f 2328
c6e387a2 2329 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2330 mmiowb();
2331 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2332}
2333
428cbd4f
NK		 2334static void ath5k_tasklet_beacon(unsigned long data)
2335{
2336 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2337
2338 /*
2339 * Software beacon alert--time to send a beacon.
2340 *
2341 * In IBSS mode we use this interrupt just to
2342 * keep track of the next TBTT (target beacon
2343 * transmission time) in order to detect wether
2344 * automatic TSF updates happened.
2345 */
2346 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2347 /* XXX: only if VEOL suppported */
2348 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2349 sc->nexttbtt += sc->bintval;
2350 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2351 "SWBA nexttbtt: %x hw_tu: %x "
2352 "TSF: %llx\n",
2353 sc->nexttbtt,
2354 TSF_TO_TU(tsf),
2355 (unsigned long long) tsf);
2356 } else {
2357 spin_lock(&sc->block);
2358 ath5k_beacon_send(sc);
2359 spin_unlock(&sc->block);
2360 }
2361}
2362
fa1c114f
JS		 2363
2364/********************\
2365* Interrupt handling *
2366\********************/
2367
2368static int
bb2becac 2369ath5k_init(struct ath5k_softc *sc)
fa1c114f 2370{
bc1b32d6
EO		 2371 struct ath5k_hw *ah = sc->ah;
2372 int ret, i;
fa1c114f
JS		 2373
2374 mutex_lock(&sc->lock);
2375
2376 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2377
2378 /*
2379 * Stop anything previously setup. This is safe
2380 * no matter this is the first time through or not.
2381 */
2382 ath5k_stop_locked(sc);
2383
242ab7ad
BC		 2384 /* Set PHY calibration interval */
2385 ah->ah_cal_intval = ath5k_calinterval;
2386
fa1c114f
JS		 2387 /*
2388 * The basic interface to setting the hardware in a good
2389 * state is ``reset''. On return the hardware is known to
2390 * be powered up and with interrupts disabled. This must
2391 * be followed by initialization of the appropriate bits
2392 * and then setup of the interrupt mask.
2393 */
d8ee398d
LR		 2394 sc->curchan = sc->hw->conf.channel;
2395 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2396 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2397 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
6e220662 2398 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
209d889b 2399 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2400 if (ret)
2401 goto done;
fa1c114f 2402
e6a3b616
TD		 2403 ath5k_rfkill_hw_start(ah);
2404
bc1b32d6
EO		 2405 /*
2406 * Reset the key cache since some parts do not reset the
2407 * contents on initial power up or resume from suspend.
2408 */
2409 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2410 ath5k_hw_reset_key(ah, i);
2411
fa1c114f 2412 /* Set ack to be sent at low bit-rates */
bc1b32d6 2413 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2414 ret = 0;
2415done:
274c7c36 2416 mmiowb();
fa1c114f
JS		 2417 mutex_unlock(&sc->lock);
2418 return ret;
2419}
2420
2421static int
2422ath5k_stop_locked(struct ath5k_softc *sc)
2423{
2424 struct ath5k_hw *ah = sc->ah;
2425
2426 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2427 test_bit(ATH_STAT_INVALID, sc->status));
2428
2429 /*
2430 * Shutdown the hardware and driver:
2431 * stop output from above
2432 * disable interrupts
2433 * turn off timers
2434 * turn off the radio
2435 * clear transmit machinery
2436 * clear receive machinery
2437 * drain and release tx queues
2438 * reclaim beacon resources
2439 * power down hardware
2440 *
2441 * Note that some of this work is not possible if the
2442 * hardware is gone (invalid).
2443 */
2444 ieee80211_stop_queues(sc->hw);
2445
2446 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2447 ath5k_led_off(sc);
c6e387a2 2448 ath5k_hw_set_imr(ah, 0);
274c7c36 2449 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2450 }
2451 ath5k_txq_cleanup(sc);
2452 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2453 ath5k_rx_stop(sc);
2454 ath5k_hw_phy_disable(ah);
2455 } else
2456 sc->rxlink = NULL;
2457
2458 return 0;
2459}
2460
2461/*
2462 * Stop the device, grabbing the top-level lock to protect
2463 * against concurrent entry through ath5k_init (which can happen
2464 * if another thread does a system call and the thread doing the
2465 * stop is preempted).
2466 */
2467static int
bb2becac 2468ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2469{
2470 int ret;
2471
2472 mutex_lock(&sc->lock);
2473 ret = ath5k_stop_locked(sc);
2474 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2475 /*
edd7fc70
NK		 2476 * Don't set the card in full sleep mode!
2477 *
2478 * a) When the device is in this state it must be carefully
2479 * woken up or references to registers in the PCI clock
2480 * domain may freeze the bus (and system). This varies
2481 * by chip and is mostly an issue with newer parts
2482 * (madwifi sources mentioned srev >= 0x78) that go to
2483 * sleep more quickly.
2484 *
2485 * b) On older chips full sleep results a weird behaviour
2486 * during wakeup. I tested various cards with srev < 0x78
2487 * and they don't wake up after module reload, a second
2488 * module reload is needed to bring the card up again.
2489 *
2490 * Until we figure out what's going on don't enable
2491 * full chip reset on any chip (this is what Legacy HAL
2492 * and Sam's HAL do anyway). Instead Perform a full reset
2493 * on the device (same as initial state after attach) and
2494 * leave it idle (keep MAC/BB on warm reset) */
2495 ret = ath5k_hw_on_hold(sc->ah);
2496
2497 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2498 "putting device to sleep\n");
fa1c114f
JS		 2499 }
2500 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2501
274c7c36 2502 mmiowb();
fa1c114f
JS		 2503 mutex_unlock(&sc->lock);
2504
10488f8a
JS		 2505 tasklet_kill(&sc->rxtq);
2506 tasklet_kill(&sc->txtq);
2507 tasklet_kill(&sc->restq);
6e220662 2508 tasklet_kill(&sc->calib);
acf3c1a5 2509 tasklet_kill(&sc->beacontq);
fa1c114f 2510
e6a3b616
TD		 2511 ath5k_rfkill_hw_stop(sc->ah);
2512
fa1c114f
JS		 2513 return ret;
2514}
2515
2516static irqreturn_t
2517ath5k_intr(int irq, void *dev_id)
2518{
2519 struct ath5k_softc *sc = dev_id;
2520 struct ath5k_hw *ah = sc->ah;
2521 enum ath5k_int status;
2522 unsigned int counter = 1000;
2523
2524 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2525 !ath5k_hw_is_intr_pending(ah)))
2526 return IRQ_NONE;
2527
2528 do {
fa1c114f
JS		 2529 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2530 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2531 status, sc->imask);
fa1c114f
JS		 2532 if (unlikely(status & AR5K_INT_FATAL)) {
2533 /*
2534 * Fatal errors are unrecoverable.
2535 * Typically these are caused by DMA errors.
2536 */
2537 tasklet_schedule(&sc->restq);
2538 } else if (unlikely(status & AR5K_INT_RXORN)) {
2539 tasklet_schedule(&sc->restq);
2540 } else {
2541 if (status & AR5K_INT_SWBA) {
56d2ac76 2542 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2543 }
2544 if (status & AR5K_INT_RXEOL) {
2545 /*
2546 * NB: the hardware should re-read the link when
2547 * RXE bit is written, but it doesn't work at
2548 * least on older hardware revs.
2549 */
2550 sc->rxlink = NULL;
2551 }
2552 if (status & AR5K_INT_TXURN) {
2553 /* bump tx trigger level */
2554 ath5k_hw_update_tx_triglevel(ah, true);
2555 }
4c674c60 2556 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2557 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2558 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2559 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2560 tasklet_schedule(&sc->txtq);
2561 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2562 /* TODO */
fa1c114f 2563 }
6e220662
NK		 2564 if (status & AR5K_INT_SWI) {
2565 tasklet_schedule(&sc->calib);
2566 }
fa1c114f 2567 if (status & AR5K_INT_MIB) {
194828a2
NK		 2568 /*
2569 * These stats are also used for ANI i think
2570 * so how about updating them more often ?
2571 */
2572 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f 2573 }
e6a3b616 2574 if (status & AR5K_INT_GPIO)
e6a3b616 2575 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2576
fa1c114f 2577 }
2516baa6 2578 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2579
2580 if (unlikely(!counter))
2581 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2582
6e220662
NK		 2583 ath5k_hw_calibration_poll(ah);
2584
fa1c114f
JS		 2585 return IRQ_HANDLED;
2586}
2587
2588static void
2589ath5k_tasklet_reset(unsigned long data)
2590{
2591 struct ath5k_softc *sc = (void *)data;
2592
d7dc1003 2593 ath5k_reset_wake(sc);
fa1c114f
JS		 2594}
2595
2596/*
2597 * Periodically recalibrate the PHY to account
2598 * for temperature/environment changes.
2599 */
2600static void
6e220662 2601ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2602{
2603 struct ath5k_softc *sc = (void *)data;
2604 struct ath5k_hw *ah = sc->ah;
2605
6e220662
NK		 2606 /* Only full calibration for now */
2607 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2608 return;
2609
2610 /* Stop queues so that calibration
2611 * doesn't interfere with tx */
2612 ieee80211_stop_queues(sc->hw);
2613
fa1c114f 2614 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2615 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2616 sc->curchan->hw_value);
fa1c114f 2617
6f3b414a 2618 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2619 /*
2620 * Rfgain is out of bounds, reset the chip
2621 * to load new gain values.
2622 */
2623 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2624 ath5k_reset_wake(sc);
fa1c114f
JS		 2625 }
2626 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2627 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2628 ieee80211_frequency_to_channel(
2629 sc->curchan->center_freq));
fa1c114f 2630
6e220662
NK		 2631 ah->ah_swi_mask = 0;
2632
2633 /* Wake queues */
2634 ieee80211_wake_queues(sc->hw);
2635
fa1c114f
JS		 2636}
2637
2638
fa1c114f
JS		 2639/********************\
2640* Mac80211 functions *
2641\********************/
2642
2643static int
e039fa4a 2644ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2645{
2646 struct ath5k_softc *sc = hw->priv;
2647
2648 return ath5k_tx_queue(hw, skb, sc->txq);
2649}
2650
2651static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2652 struct ath5k_txq *txq)
fa1c114f
JS		 2653{
2654 struct ath5k_softc *sc = hw->priv;
2655 struct ath5k_buf *bf;
2656 unsigned long flags;
2657 int hdrlen;
0fe45b1d 2658 int padsize;
fa1c114f
JS		 2659
2660 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2661
05c914fe 2662 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2663 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2664
2665 /*
2666 * the hardware expects the header padded to 4 byte boundaries
2667 * if this is not the case we add the padding after the header
2668 */
2669 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2670 padsize = ath5k_pad_size(hdrlen);
2671 if (padsize) {
0fe45b1d
BP		 2672
2673 if (skb_headroom(skb) < padsize) {
fa1c114f 2674 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2675 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2676 goto drop_packet;
fa1c114f 2677 }
0fe45b1d
BP		 2678 skb_push(skb, padsize);
2679 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2680 }
2681
fa1c114f
JS		 2682 spin_lock_irqsave(&sc->txbuflock, flags);
2683 if (list_empty(&sc->txbuf)) {
2684 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2685 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2686 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2687 goto drop_packet;
fa1c114f
JS		 2688 }
2689 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2690 list_del(&bf->list);
2691 sc->txbuf_len--;
2692 if (list_empty(&sc->txbuf))
2693 ieee80211_stop_queues(hw);
2694 spin_unlock_irqrestore(&sc->txbuflock, flags);
2695
2696 bf->skb = skb;
2697
cec8db23 2698 if (ath5k_txbuf_setup(sc, bf, txq)) {
fa1c114f
JS		 2699 bf->skb = NULL;
2700 spin_lock_irqsave(&sc->txbuflock, flags);
2701 list_add_tail(&bf->list, &sc->txbuf);
2702 sc->txbuf_len++;
2703 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2704 goto drop_packet;
fa1c114f 2705 }
5a0fe8ac 2706 return NETDEV_TX_OK;
fa1c114f 2707
5a0fe8ac
BC		 2708drop_packet:
2709 dev_kfree_skb_any(skb);
71ef99c8 2710 return NETDEV_TX_OK;
fa1c114f
JS		 2711}
2712
209d889b
BC		 2713/*
2714 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2715 * and change to the given channel.
2716 */
fa1c114f 2717static int
209d889b 2718ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2719{
fa1c114f
JS		 2720 struct ath5k_hw *ah = sc->ah;
2721 int ret;
2722
2723 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2724
209d889b 2725 if (chan) {
c6e387a2 2726 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2727 ath5k_txq_cleanup(sc);
2728 ath5k_rx_stop(sc);
209d889b
BC		 2729
2730 sc->curchan = chan;
2731 sc->curband = &sc->sbands[chan->band];
d7dc1003 2732 }
3355443a 2733 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2734 if (ret) {
fa1c114f
JS		 2735 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2736 goto err;
2737 }
d7dc1003 2738
fa1c114f 2739 ret = ath5k_rx_start(sc);
d7dc1003 2740 if (ret) {
fa1c114f
JS		 2741 ATH5K_ERR(sc, "can't start recv logic\n");
2742 goto err;
2743 }
d7dc1003 2744
fa1c114f 2745 /*
d7dc1003
JS		 2746 * Change channels and update the h/w rate map if we're switching;
2747 * e.g. 11a to 11b/g.
2748 *
2749 * We may be doing a reset in response to an ioctl that changes the
2750 * channel so update any state that might change as a result.
fa1c114f
JS		 2751 *
2752 * XXX needed?
2753 */
2754/* ath5k_chan_change(sc, c); */
fa1c114f 2755
d7dc1003
JS		 2756 ath5k_beacon_config(sc);
2757 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2758
2759 return 0;
2760err:
2761 return ret;
2762}
2763
d7dc1003
JS		 2764static int
2765ath5k_reset_wake(struct ath5k_softc *sc)
2766{
2767 int ret;
2768
209d889b 2769 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2770 if (!ret)
2771 ieee80211_wake_queues(sc->hw);
2772
2773 return ret;
2774}
2775
fa1c114f
JS		 2776static int ath5k_start(struct ieee80211_hw *hw)
2777{
bb2becac 2778 return ath5k_init(hw->priv);
fa1c114f
JS		 2779}
2780
2781static void ath5k_stop(struct ieee80211_hw *hw)
2782{
bb2becac 2783 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2784}
2785
2786static int ath5k_add_interface(struct ieee80211_hw *hw,
2787 struct ieee80211_if_init_conf *conf)
2788{
2789 struct ath5k_softc *sc = hw->priv;
2790 int ret;
2791
2792 mutex_lock(&sc->lock);
32bfd35d 2793 if (sc->vif) {
fa1c114f
JS		 2794 ret = 0;
2795 goto end;
2796 }
2797
32bfd35d 2798 sc->vif = conf->vif;
fa1c114f
JS		 2799
2800 switch (conf->type) {
da966bca 2801 case NL80211_IFTYPE_AP:
05c914fe
JB		 2802 case NL80211_IFTYPE_STATION:
2803 case NL80211_IFTYPE_ADHOC:
b706e65b 2804 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2805 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2806 sc->opmode = conf->type;
2807 break;
2808 default:
2809 ret = -EOPNOTSUPP;
2810 goto end;
2811 }
67d2e2df 2812
0e149cf5 2813 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
ae6f53f2 2814 ath5k_mode_setup(sc);
67d2e2df 2815
fa1c114f
JS		 2816 ret = 0;
2817end:
2818 mutex_unlock(&sc->lock);
2819 return ret;
2820}
2821
2822static void
2823ath5k_remove_interface(struct ieee80211_hw *hw,
2824 struct ieee80211_if_init_conf *conf)
2825{
2826 struct ath5k_softc *sc = hw->priv;
0e149cf5 2827 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2828
2829 mutex_lock(&sc->lock);
32bfd35d 2830 if (sc->vif != conf->vif)
fa1c114f
JS		 2831 goto end;
2832
0e149cf5 2833 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2834 sc->vif = NULL;
fa1c114f
JS		 2835end:
2836 mutex_unlock(&sc->lock);
2837}
2838
d8ee398d
LR		 2839/*
2840 * TODO: Phy disable/diversity etc
2841 */
fa1c114f 2842static int
e8975581 2843ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2844{
2845 struct ath5k_softc *sc = hw->priv;
a0823810 2846 struct ath5k_hw *ah = sc->ah;
e8975581 2847 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 2848 int ret = 0;
be009370
BC		 2849
2850 mutex_lock(&sc->lock);
fa1c114f 2851
e30eb4ab
JA		 2852 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2853 ret = ath5k_chan_set(sc, conf->channel);
2854 if (ret < 0)
2855 goto unlock;
2856 }
2bed03eb 2857
a0823810
NK		 2858 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2859 (sc->power_level != conf->power_level)) {
2860 sc->power_level = conf->power_level;
2861
2862 /* Half dB steps */
2863 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2864 }
fa1c114f 2865
2bed03eb
NK		 2866 /* TODO:
2867 * 1) Move this on config_interface and handle each case
2868 * separately eg. when we have only one STA vif, use
2869 * AR5K_ANTMODE_SINGLE_AP
2870 *
2871 * 2) Allow the user to change antenna mode eg. when only
2872 * one antenna is present
2873 *
2874 * 3) Allow the user to set default/tx antenna when possible
2875 *
2876 * 4) Default mode should handle 90% of the cases, together
2877 * with fixed a/b and single AP modes we should be able to
2878 * handle 99%. Sectored modes are extreme cases and i still
2879 * haven't found a usage for them. If we decide to support them,
2880 * then we must allow the user to set how many tx antennas we
2881 * have available
2882 */
2883 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
be009370 2884
55aa4e0f 2885unlock:
be009370 2886 mutex_unlock(&sc->lock);
55aa4e0f 2887 return ret;
fa1c114f
JS		 2888}
2889
3ac64bee
JB		 2890static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2891 int mc_count, struct dev_addr_list *mclist)
2892{
2893 u32 mfilt[2], val;
2894 int i;
2895 u8 pos;
2896
2897 mfilt[0] = 0;
2898 mfilt[1] = 1;
2899
2900 for (i = 0; i < mc_count; i++) {
2901 if (!mclist)
2902 break;
2903 /* calculate XOR of eight 6-bit values */
2904 val = get_unaligned_le32(mclist->dmi_addr + 0);
2905 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2906 val = get_unaligned_le32(mclist->dmi_addr + 3);
2907 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2908 pos &= 0x3f;
2909 mfilt[pos / 32] |= (1 << (pos % 32));
2910 /* XXX: we might be able to just do this instead,
2911 * but not sure, needs testing, if we do use this we'd
2912 * neet to inform below to not reset the mcast */
2913 /* ath5k_hw_set_mcast_filterindex(ah,
2914 * mclist->dmi_addr[5]); */
2915 mclist = mclist->next;
2916 }
2917
2918 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2919}
2920
fa1c114f
JS		 2921#define SUPPORTED_FIF_FLAGS \
2922 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2923 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2924 FIF_BCN_PRBRESP_PROMISC
2925/*
2926 * o always accept unicast, broadcast, and multicast traffic
2927 * o multicast traffic for all BSSIDs will be enabled if mac80211
2928 * says it should be
2929 * o maintain current state of phy ofdm or phy cck error reception.
2930 * If the hardware detects any of these type of errors then
2931 * ath5k_hw_get_rx_filter() will pass to us the respective
2932 * hardware filters to be able to receive these type of frames.
2933 * o probe request frames are accepted only when operating in
2934 * hostap, adhoc, or monitor modes
2935 * o enable promiscuous mode according to the interface state
2936 * o accept beacons:
2937 * - when operating in adhoc mode so the 802.11 layer creates
2938 * node table entries for peers,
2939 * - when operating in station mode for collecting rssi data when
2940 * the station is otherwise quiet, or
2941 * - when scanning
2942 */
2943static void ath5k_configure_filter(struct ieee80211_hw *hw,
2944 unsigned int changed_flags,
2945 unsigned int *new_flags,
3ac64bee 2946 u64 multicast)
fa1c114f
JS		 2947{
2948 struct ath5k_softc *sc = hw->priv;
2949 struct ath5k_hw *ah = sc->ah;
3ac64bee 2950 u32 mfilt[2], rfilt;
fa1c114f 2951
56d1de0a
BC		 2952 mutex_lock(&sc->lock);
2953
3ac64bee
JB		 2954 mfilt[0] = multicast;
2955 mfilt[1] = multicast >> 32;
fa1c114f
JS		 2956
2957 /* Only deal with supported flags */
2958 changed_flags &= SUPPORTED_FIF_FLAGS;
2959 *new_flags &= SUPPORTED_FIF_FLAGS;
2960
2961 /* If HW detects any phy or radar errors, leave those filters on.
2962 * Also, always enable Unicast, Broadcasts and Multicast
2963 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2964 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2965 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2966 AR5K_RX_FILTER_MCAST);
2967
2968 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2969 if (*new_flags & FIF_PROMISC_IN_BSS) {
2970 rfilt |= AR5K_RX_FILTER_PROM;
2971 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2972 } else {
fa1c114f 2973 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2974 }
fa1c114f
JS		 2975 }
2976
2977 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2978 if (*new_flags & FIF_ALLMULTI) {
2979 mfilt[0] = ~0;
2980 mfilt[1] = ~0;
fa1c114f
JS		 2981 }
2982
2983 /* This is the best we can do */
2984 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2985 rfilt |= AR5K_RX_FILTER_PHYERR;
2986
2987 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2988 * and probes for any BSSID, this needs testing */
2989 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2990 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2991
2992 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2993 * set we should only pass on control frames for this
2994 * station. This needs testing. I believe right now this
2995 * enables *all* control frames, which is OK.. but
2996 * but we should see if we can improve on granularity */
2997 if (*new_flags & FIF_CONTROL)
2998 rfilt |= AR5K_RX_FILTER_CONTROL;
2999
3000 /* Additional settings per mode -- this is per ath5k */
3001
3002 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3003
56d1de0a
BC		 3004 switch (sc->opmode) {
3005 case NL80211_IFTYPE_MESH_POINT:
3006 case NL80211_IFTYPE_MONITOR:
3007 rfilt |= AR5K_RX_FILTER_CONTROL |
3008 AR5K_RX_FILTER_BEACON |
3009 AR5K_RX_FILTER_PROBEREQ |
3010 AR5K_RX_FILTER_PROM;
3011 break;
3012 case NL80211_IFTYPE_AP:
3013 case NL80211_IFTYPE_ADHOC:
3014 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3015 AR5K_RX_FILTER_BEACON;
3016 break;
3017 case NL80211_IFTYPE_STATION:
3018 if (sc->assoc)
3019 rfilt |= AR5K_RX_FILTER_BEACON;
3020 default:
3021 break;
3022 }
fa1c114f
JS		 3023
3024 /* Set filters */
0bbac08f 3025 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3026
3027 /* Set multicast bits */
3028 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3029 /* Set the cached hw filter flags, this will alter actually
3030 * be set in HW */
3031 sc->filter_flags = rfilt;
56d1de0a
BC		 3032
3033 mutex_unlock(&sc->lock);
fa1c114f
JS		 3034}
3035
3036static int
3037ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3038 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3039 struct ieee80211_key_conf *key)
fa1c114f
JS		 3040{
3041 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3042 struct ath5k_hw *ah = sc->ah;
3043 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3044 int ret = 0;
3045
9ad9a26e
BC		 3046 if (modparam_nohwcrypt)
3047 return -EOPNOTSUPP;
3048
65b5a698
BC		 3049 if (sc->opmode == NL80211_IFTYPE_AP)
3050 return -EOPNOTSUPP;
3051
0bbac08f 3052 switch (key->alg) {
fa1c114f 3053 case ALG_WEP:
fa1c114f 3054 case ALG_TKIP:
3f64b435 3055 break;
fa1c114f 3056 case ALG_CCMP:
1c818740
BC		 3057 if (sc->ah->ah_aes_support)
3058 break;
3059
fa1c114f
JS		 3060 return -EOPNOTSUPP;
3061 default:
3062 WARN_ON(1);
3063 return -EINVAL;
3064 }
3065
3066 mutex_lock(&sc->lock);
3067
3068 switch (cmd) {
3069 case SET_KEY:
dc822b5d
JB		 3070 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3071 sta ? sta->addr : NULL);
fa1c114f
JS		 3072 if (ret) {
3073 ATH5K_ERR(sc, "can't set the key\n");
3074 goto unlock;
3075 }
dc1e001b 3076 __set_bit(key->keyidx, common->keymap);
fa1c114f 3077 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3078 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3079 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3080 break;
3081 case DISABLE_KEY:
3082 ath5k_hw_reset_key(sc->ah, key->keyidx);
dc1e001b 3083 __clear_bit(key->keyidx, common->keymap);
fa1c114f
JS		 3084 break;
3085 default:
3086 ret = -EINVAL;
3087 goto unlock;
3088 }
3089
3090unlock:
274c7c36 3091 mmiowb();
fa1c114f
JS		 3092 mutex_unlock(&sc->lock);
3093 return ret;
3094}
3095
3096static int
3097ath5k_get_stats(struct ieee80211_hw *hw,
3098 struct ieee80211_low_level_stats *stats)
3099{
3100 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3101 struct ath5k_hw *ah = sc->ah;
3102
3103 /* Force update */
3104 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3105
3106 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3107
3108 return 0;
3109}
3110
3111static int
3112ath5k_get_tx_stats(struct ieee80211_hw *hw,
3113 struct ieee80211_tx_queue_stats *stats)
3114{
3115 struct ath5k_softc *sc = hw->priv;
3116
3117 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3118
3119 return 0;
3120}
3121
3122static u64
3123ath5k_get_tsf(struct ieee80211_hw *hw)
3124{
3125 struct ath5k_softc *sc = hw->priv;
3126
3127 return ath5k_hw_get_tsf64(sc->ah);
3128}
3129
3b5d665b
AF		 3130static void
3131ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3132{
3133 struct ath5k_softc *sc = hw->priv;
3134
3135 ath5k_hw_set_tsf64(sc->ah, tsf);
3136}
3137
fa1c114f
JS		 3138static void
3139ath5k_reset_tsf(struct ieee80211_hw *hw)
3140{
3141 struct ath5k_softc *sc = hw->priv;
3142
9804b98d
BR		 3143 /*
3144 * in IBSS mode we need to update the beacon timers too.
3145 * this will also reset the TSF if we call it with 0
3146 */
05c914fe 3147 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3148 ath5k_beacon_update_timers(sc, 0);
3149 else
3150 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3151}
3152
1071db86
BC		 3153/*
3154 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3155 * this is called only once at config_bss time, for AP we do it every
3156 * SWBA interrupt so that the TIM will reflect buffered frames.
3157 *
3158 * Called with the beacon lock.
3159 */
fa1c114f 3160static int
1071db86 3161ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3162{
fa1c114f 3163 int ret;
1071db86 3164 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3165 struct sk_buff *skb;
3166
3167 if (WARN_ON(!vif)) {
3168 ret = -EINVAL;
3169 goto out;
3170 }
3171
3172 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3173
3174 if (!skb) {
3175 ret = -ENOMEM;
3176 goto out;
3177 }
fa1c114f
JS		 3178
3179 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3180
fa1c114f
JS		 3181 ath5k_txbuf_free(sc, sc->bbuf);
3182 sc->bbuf->skb = skb;
e039fa4a 3183 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3184 if (ret)
3185 sc->bbuf->skb = NULL;
1071db86
BC		 3186out:
3187 return ret;
3188}
3189
02969b38
MX		 3190static void
3191set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3192{
3193 struct ath5k_softc *sc = hw->priv;
3194 struct ath5k_hw *ah = sc->ah;
3195 u32 rfilt;
3196 rfilt = ath5k_hw_get_rx_filter(ah);
3197 if (enable)
3198 rfilt |= AR5K_RX_FILTER_BEACON;
3199 else
3200 rfilt &= ~AR5K_RX_FILTER_BEACON;
3201 ath5k_hw_set_rx_filter(ah, rfilt);
3202 sc->filter_flags = rfilt;
3203}
fa1c114f 3204
02969b38
MX		 3205static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3206 struct ieee80211_vif *vif,
3207 struct ieee80211_bss_conf *bss_conf,
3208 u32 changes)
3209{
3210 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3211 struct ath5k_hw *ah = sc->ah;
954fecea 3212 struct ath_common *common = ath5k_hw_common(ah);
21800491 3213 unsigned long flags;
2d0ddec5
JB		 3214
3215 mutex_lock(&sc->lock);
3216 if (WARN_ON(sc->vif != vif))
3217 goto unlock;
3218
3219 if (changes & BSS_CHANGED_BSSID) {
3220 /* Cache for later use during resets */
954fecea 3221 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
8ce54c5a 3222 common->curaid = 0;
be5d6b75 3223 ath5k_hw_set_associd(ah);
2d0ddec5
JB		 3224 mmiowb();
3225 }
57c4d7b4
JB		 3226
3227 if (changes & BSS_CHANGED_BEACON_INT)
3228 sc->bintval = bss_conf->beacon_int;
3229
02969b38 3230 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3231 sc->assoc = bss_conf->assoc;
3232 if (sc->opmode == NL80211_IFTYPE_STATION)
3233 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3234 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3235 AR5K_LED_ASSOC : AR5K_LED_INIT);
8ce54c5a
LR		 3236 if (bss_conf->assoc) {
3237 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3238 "Bss Info ASSOC %d, bssid: %pM\n",
3239 bss_conf->aid, common->curbssid);
3240 common->curaid = bss_conf->aid;
3241 ath5k_hw_set_associd(ah);
3242 /* Once ANI is available you would start it here */
3243 }
02969b38 3244 }
2d0ddec5 3245
21800491
BC		 3246 if (changes & BSS_CHANGED_BEACON) {
3247 spin_lock_irqsave(&sc->block, flags);
3248 ath5k_beacon_update(hw, vif);
3249 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3250 }
3251
21800491
BC		 3252 if (changes & BSS_CHANGED_BEACON_ENABLED)
3253 sc->enable_beacon = bss_conf->enable_beacon;
3254
3255 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3256 BSS_CHANGED_BEACON_INT))
3257 ath5k_beacon_config(sc);
3258
2d0ddec5
JB		 3259 unlock:
3260 mutex_unlock(&sc->lock);
02969b38 3261}
f0f3d388
BC		 3262
3263static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3264{
3265 struct ath5k_softc *sc = hw->priv;
3266 if (!sc->assoc)
3267 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3268}
3269
3270static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3271{
3272 struct ath5k_softc *sc = hw->priv;
3273 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3274 AR5K_LED_ASSOC : AR5K_LED_INIT);
3275}
Linux kernel - Deliverables
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