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ath5k: don't use volatile, it's not needed
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
0e472252
BC		 64#define CREATE_TRACE_POINTS
65#include "trace.h"
66
18cb6e32
JL		 67int ath5k_modparam_nohwcrypt;
68module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 69MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 70
42639fcd 71static int modparam_all_channels;
46802a4f 72module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 73MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
a99168ee
NK		 75static int modparam_fastchanswitch;
76module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
77MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
78
79
fa1c114f
JS		 80/* Module info */
81MODULE_AUTHOR("Jiri Slaby");
82MODULE_AUTHOR("Nick Kossifidis");
83MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
84MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
85MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 86
132b1c3e 87static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 88static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
89 bool skip_pcu);
fa1c114f 90
fa1c114f 91/* Known SREVs */
2c91108c 92static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 93#ifdef CONFIG_ATHEROS_AR231X
94 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
96 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
97 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
99 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
101#else
1bef016a
NK		 102 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
103 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
104 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
105 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
106 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
107 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
108 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
109 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
110 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
111 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
112 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
113 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
114 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
115 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
116 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
117 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
118 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
119 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 120#endif
1bef016a 121 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 124 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 125 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
126 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
127 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 128 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 131 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
132 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
133 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 134 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 135 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 136#ifdef CONFIG_ATHEROS_AR231X
137 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
138 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
139#endif
fa1c114f
JS		 140 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
141};
142
2c91108c 143static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 144 { .bitrate = 10,
145 .hw_value = ATH5K_RATE_CODE_1M, },
146 { .bitrate = 20,
147 .hw_value = ATH5K_RATE_CODE_2M,
148 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
149 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
150 { .bitrate = 55,
151 .hw_value = ATH5K_RATE_CODE_5_5M,
152 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
153 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
154 { .bitrate = 110,
155 .hw_value = ATH5K_RATE_CODE_11M,
156 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 { .bitrate = 60,
159 .hw_value = ATH5K_RATE_CODE_6M,
160 .flags = 0 },
161 { .bitrate = 90,
162 .hw_value = ATH5K_RATE_CODE_9M,
163 .flags = 0 },
164 { .bitrate = 120,
165 .hw_value = ATH5K_RATE_CODE_12M,
166 .flags = 0 },
167 { .bitrate = 180,
168 .hw_value = ATH5K_RATE_CODE_18M,
169 .flags = 0 },
170 { .bitrate = 240,
171 .hw_value = ATH5K_RATE_CODE_24M,
172 .flags = 0 },
173 { .bitrate = 360,
174 .hw_value = ATH5K_RATE_CODE_36M,
175 .flags = 0 },
176 { .bitrate = 480,
177 .hw_value = ATH5K_RATE_CODE_48M,
178 .flags = 0 },
179 { .bitrate = 540,
180 .hw_value = ATH5K_RATE_CODE_54M,
181 .flags = 0 },
182 /* XR missing */
183};
184
fa1c114f
JS		 185static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
186{
187 u64 tsf = ath5k_hw_get_tsf64(ah);
188
189 if ((tsf & 0x7fff) < rstamp)
190 tsf -= 0x8000;
191
192 return (tsf & ~0x7fff) | rstamp;
193}
194
e5b046d8 195const char *
fa1c114f
JS		 196ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
197{
198 const char *name = "xxxxx";
199 unsigned int i;
200
201 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
202 if (srev_names[i].sr_type != type)
203 continue;
75d0edb8
NK		 204
205 if ((val & 0xf0) == srev_names[i].sr_val)
206 name = srev_names[i].sr_name;
207
208 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 209 name = srev_names[i].sr_name;
210 break;
211 }
212 }
213
214 return name;
215}
e5aa8474
LR		 216static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
217{
218 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
219 return ath5k_hw_reg_read(ah, reg_offset);
220}
221
222static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
223{
224 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
225 ath5k_hw_reg_write(ah, val, reg_offset);
226}
227
228static const struct ath_ops ath5k_common_ops = {
229 .read = ath5k_ioread32,
230 .write = ath5k_iowrite32,
231};
fa1c114f 232
8a63facc
BC		 233/***********************\
234* Driver Initialization *
235\***********************/
236
237static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 238{
8a63facc
BC		 239 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
240 struct ath5k_softc *sc = hw->priv;
241 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 242
8a63facc
BC		 243 return ath_reg_notifier_apply(wiphy, request, regulatory);
244}
6ccf15a1 245
8a63facc
BC		 246/********************\
247* Channel/mode setup *
248\********************/
fa1c114f 249
8a63facc
BC		 250/*
251 * Returns true for the channel numbers used without all_channels modparam.
252 */
410e6120 253static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 254{
410e6120
BR		 255 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
256 return true;
257
258 return /* UNII 1,2 */
259 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 260 /* midband */
261 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
262 /* UNII-3 */
410e6120
BR		 263 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
264 /* 802.11j 5.030-5.080 GHz (20MHz) */
265 (chan == 8 || chan == 12 || chan == 16) ||
266 /* 802.11j 4.9GHz (20MHz) */
267 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 268}
fa1c114f 269
8a63facc 270static unsigned int
97d9c3a3
BR		 271ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
272 unsigned int mode, unsigned int max)
8a63facc 273{
2b1351a3 274 unsigned int count, size, chfreq, freq, ch;
90c02d72 275 enum ieee80211_band band;
fa1c114f 276
8a63facc
BC		 277 switch (mode) {
278 case AR5K_MODE_11A:
8a63facc 279 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 280 size = 220;
8a63facc 281 chfreq = CHANNEL_5GHZ;
90c02d72 282 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 283 break;
284 case AR5K_MODE_11B:
285 case AR5K_MODE_11G:
8a63facc
BC		 286 size = 26;
287 chfreq = CHANNEL_2GHZ;
90c02d72 288 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 289 break;
290 default:
291 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
292 return 0;
fa1c114f
JS		 293 }
294
2b1351a3
BR		 295 count = 0;
296 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 297 freq = ieee80211_channel_to_frequency(ch, band);
298
299 if (freq == 0) /* mapping failed - not a standard channel */
300 continue;
fa1c114f 301
8a63facc
BC		 302 /* Check if channel is supported by the chipset */
303 if (!ath5k_channel_ok(ah, freq, chfreq))
304 continue;
f59ac048 305
410e6120
BR		 306 if (!modparam_all_channels &&
307 !ath5k_is_standard_channel(ch, band))
8a63facc 308 continue;
f59ac048 309
8a63facc
BC		 310 /* Write channel info and increment counter */
311 channels[count].center_freq = freq;
90c02d72 312 channels[count].band = band;
8a63facc
BC		 313 switch (mode) {
314 case AR5K_MODE_11A:
315 case AR5K_MODE_11G:
316 channels[count].hw_value = chfreq | CHANNEL_OFDM;
317 break;
8a63facc
BC		 318 case AR5K_MODE_11B:
319 channels[count].hw_value = CHANNEL_B;
320 }
fa1c114f 321
8a63facc 322 count++;
8a63facc 323 }
fa1c114f 324
8a63facc
BC		 325 return count;
326}
fa1c114f 327
8a63facc
BC		 328static void
329ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
330{
331 u8 i;
fa1c114f 332
8a63facc
BC		 333 for (i = 0; i < AR5K_MAX_RATES; i++)
334 sc->rate_idx[b->band][i] = -1;
fa1c114f 335
8a63facc
BC		 336 for (i = 0; i < b->n_bitrates; i++) {
337 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
338 if (b->bitrates[i].hw_value_short)
339 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 340 }
8a63facc 341}
fa1c114f 342
8a63facc
BC		 343static int
344ath5k_setup_bands(struct ieee80211_hw *hw)
345{
346 struct ath5k_softc *sc = hw->priv;
347 struct ath5k_hw *ah = sc->ah;
348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
fa1c114f 351
8a63facc
BC		 352 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(sc->channels);
db719718 354
8a63facc
BC		 355 /* 2GHz band */
356 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
357 sband->band = IEEE80211_BAND_2GHZ;
358 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 359
8a63facc
BC		 360 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
361 /* G mode */
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
2f7fe870 365
8a63facc 366 sband->channels = sc->channels;
08105690 367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 368 AR5K_MODE_11G, max_c);
fa1c114f 369
8a63facc
BC		 370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
372 max_c -= count_c;
373 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
374 /* B mode */
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
fa1c114f 378
8a63facc
BC		 379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
381 * fix them up here:
382 */
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 389 }
390 }
fa1c114f 391
8a63facc 392 sband->channels = sc->channels;
08105690 393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 394 AR5K_MODE_11B, max_c);
fa1c114f 395
8a63facc
BC		 396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
399 }
400 ath5k_setup_rate_idx(sc, sband);
fa1c114f 401
8a63facc
BC		 402 /* 5GHz band, A mode */
403 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
404 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
405 sband->band = IEEE80211_BAND_5GHZ;
406 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 407
8a63facc
BC		 408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
fa1c114f 411
8a63facc 412 sband->channels = &sc->channels[count_c];
08105690 413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 414 AR5K_MODE_11A, max_c);
fa1c114f 415
8a63facc
BC		 416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
418 ath5k_setup_rate_idx(sc, sband);
419
420 ath5k_debug_dump_bands(sc);
fa1c114f 421
fa1c114f
JS		 422 return 0;
423}
424
8a63facc
BC		 425/*
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
429 *
430 * Called with sc->lock.
431 */
cd2c5486 432int
8a63facc
BC		 433ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
434{
435 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
436 "channel set, resetting (%u -> %u MHz)\n",
437 sc->curchan->center_freq, chan->center_freq);
438
8451d22d 439 /*
8a63facc
BC		 440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
8451d22d 444 */
8aec7af9 445 return ath5k_reset(sc, chan, true);
fa1c114f 446}
fa1c114f 447
e4b0b32a 448void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
b1ae1edf 449{
e4b0b32a 450 struct ath5k_vif_iter_data *iter_data = data;
b1ae1edf 451 int i;
62c58fb4 452 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 453
454 if (iter_data->hw_macaddr)
455 for (i = 0; i < ETH_ALEN; i++)
456 iter_data->mask[i] &=
457 ~(iter_data->hw_macaddr[i] ^ mac[i]);
458
459 if (!iter_data->found_active) {
460 iter_data->found_active = true;
461 memcpy(iter_data->active_mac, mac, ETH_ALEN);
462 }
463
464 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
465 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
466 iter_data->need_set_hw_addr = false;
467
468 if (!iter_data->any_assoc) {
b1ae1edf
BG		 469 if (avf->assoc)
470 iter_data->any_assoc = true;
471 }
62c58fb4
BG		 472
473 /* Calculate combined mode - when APs are active, operate in AP mode.
474 * Otherwise use the mode of the new interface. This can currently
475 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 476 * interfaces is allowed.
62c58fb4
BG		 477 */
478 if (avf->opmode == NL80211_IFTYPE_AP)
479 iter_data->opmode = NL80211_IFTYPE_AP;
e4b0b32a
BG		 480 else {
481 if (avf->opmode == NL80211_IFTYPE_STATION)
482 iter_data->n_stas++;
62c58fb4
BG		 483 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
484 iter_data->opmode = avf->opmode;
e4b0b32a 485 }
b1ae1edf
BG		 486}
487
cd2c5486
BR		 488void
489ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
490 struct ieee80211_vif *vif)
b1ae1edf
BG		 491{
492 struct ath_common *common = ath5k_hw_common(sc->ah);
e4b0b32a
BG		 493 struct ath5k_vif_iter_data iter_data;
494 u32 rfilt;
b1ae1edf
BG		 495
496 /*
497 * Use the hardware MAC address as reference, the hardware uses it
498 * together with the BSSID mask when matching addresses.
499 */
500 iter_data.hw_macaddr = common->macaddr;
501 memset(&iter_data.mask, 0xff, ETH_ALEN);
502 iter_data.found_active = false;
503 iter_data.need_set_hw_addr = true;
62c58fb4 504 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
e4b0b32a 505 iter_data.n_stas = 0;
b1ae1edf
BG		 506
507 if (vif)
e4b0b32a 508 ath5k_vif_iter(&iter_data, vif->addr, vif);
b1ae1edf
BG		 509
510 /* Get list of all active MAC addresses */
e4b0b32a 511 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
b1ae1edf
BG		 512 &iter_data);
513 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
514
62c58fb4
BG		 515 sc->opmode = iter_data.opmode;
516 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
517 /* Nothing active, default to station mode */
518 sc->opmode = NL80211_IFTYPE_STATION;
519
7afbb2f0
BG		 520 ath5k_hw_set_opmode(sc->ah, sc->opmode);
521 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
522 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 523
b1ae1edf
BG		 524 if (iter_data.need_set_hw_addr && iter_data.found_active)
525 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
526
62c58fb4
BG		 527 if (ath5k_hw_hasbssidmask(sc->ah))
528 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf 529
e4b0b32a
BG		 530 /* Set up RX Filter */
531 if (iter_data.n_stas > 1) {
532 /* If you have multiple STA interfaces connected to
533 * different APs, ARPs are not received (most of the time?)
534 * Enabling PROMISC appears to fix that probem.
535 */
536 sc->filter_flags |= AR5K_RX_FILTER_PROM;
537 }
fa1c114f 538
8a63facc 539 rfilt = sc->filter_flags;
e4b0b32a 540 ath5k_hw_set_rx_filter(sc->ah, rfilt);
8a63facc
BC		 541 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
542}
fa1c114f 543
8a63facc
BC		 544static inline int
545ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
546{
547 int rix;
fa1c114f 548
8a63facc
BC		 549 /* return base rate on errors */
550 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
551 "hw_rix out of bounds: %x\n", hw_rix))
552 return 0;
553
930a7622 554 rix = sc->rate_idx[sc->curchan->band][hw_rix];
8a63facc
BC		 555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
556 rix = 0;
557
558 return rix;
559}
560
561/***************\
562* Buffers setup *
563\***************/
564
565static
566struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
567{
568 struct ath_common *common = ath5k_hw_common(sc->ah);
569 struct sk_buff *skb;
fa1c114f
JS		 570
571 /*
8a63facc
BC		 572 * Allocate buffer with headroom_needed space for the
573 * fake physical layer header at the start.
fa1c114f 574 */
8a63facc
BC		 575 skb = ath_rxbuf_alloc(common,
576 common->rx_bufsize,
577 GFP_ATOMIC);
fa1c114f 578
8a63facc
BC		 579 if (!skb) {
580 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
581 common->rx_bufsize);
582 return NULL;
fa1c114f
JS		 583 }
584
aeae4ac9 585 *skb_addr = dma_map_single(sc->dev,
8a63facc 586 skb->data, common->rx_bufsize,
aeae4ac9
FF		 587 DMA_FROM_DEVICE);
588
589 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 590 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
591 dev_kfree_skb(skb);
592 return NULL;
0e149cf5 593 }
8a63facc
BC		 594 return skb;
595}
0e149cf5 596
8a63facc
BC		 597static int
598ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
599{
600 struct ath5k_hw *ah = sc->ah;
601 struct sk_buff *skb = bf->skb;
602 struct ath5k_desc *ds;
603 int ret;
fa1c114f 604
8a63facc
BC		 605 if (!skb) {
606 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
607 if (!skb)
608 return -ENOMEM;
609 bf->skb = skb;
f769c36b
BC		 610 }
611
8a63facc
BC		 612 /*
613 * Setup descriptors. For receive we always terminate
614 * the descriptor list with a self-linked entry so we'll
615 * not get overrun under high load (as can happen with a
616 * 5212 when ANI processing enables PHY error frames).
617 *
618 * To ensure the last descriptor is self-linked we create
619 * each descriptor as self-linked and add it to the end. As
620 * each additional descriptor is added the previous self-linked
621 * entry is "fixed" naturally. This should be safe even
622 * if DMA is happening. When processing RX interrupts we
623 * never remove/process the last, self-linked, entry on the
624 * descriptor list. This ensures the hardware always has
625 * someplace to write a new frame.
626 */
627 ds = bf->desc;
628 ds->ds_link = bf->daddr; /* link to self */
629 ds->ds_data = bf->skbaddr;
630 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 631 if (ret) {
8a63facc
BC		 632 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
633 return ret;
fa1c114f
JS		 634 }
635
8a63facc
BC		 636 if (sc->rxlink != NULL)
637 *sc->rxlink = bf->daddr;
638 sc->rxlink = &ds->ds_link;
fa1c114f 639 return 0;
fa1c114f
JS		 640}
641
8a63facc 642static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 643{
8a63facc
BC		 644 struct ieee80211_hdr *hdr;
645 enum ath5k_pkt_type htype;
646 __le16 fc;
fa1c114f 647
8a63facc
BC		 648 hdr = (struct ieee80211_hdr *)skb->data;
649 fc = hdr->frame_control;
fa1c114f 650
8a63facc
BC		 651 if (ieee80211_is_beacon(fc))
652 htype = AR5K_PKT_TYPE_BEACON;
653 else if (ieee80211_is_probe_resp(fc))
654 htype = AR5K_PKT_TYPE_PROBE_RESP;
655 else if (ieee80211_is_atim(fc))
656 htype = AR5K_PKT_TYPE_ATIM;
657 else if (ieee80211_is_pspoll(fc))
658 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 659 else
8a63facc 660 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 661
8a63facc 662 return htype;
42639fcd
BC		 663}
664
8a63facc
BC		 665static int
666ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
667 struct ath5k_txq *txq, int padsize)
fa1c114f 668{
8a63facc
BC		 669 struct ath5k_hw *ah = sc->ah;
670 struct ath5k_desc *ds = bf->desc;
671 struct sk_buff *skb = bf->skb;
672 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
673 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
674 struct ieee80211_rate *rate;
675 unsigned int mrr_rate[3], mrr_tries[3];
676 int i, ret;
677 u16 hw_rate;
678 u16 cts_rate = 0;
679 u16 duration = 0;
680 u8 rc_flags;
fa1c114f 681
8a63facc 682 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 683
8a63facc 684 /* XXX endianness */
aeae4ac9
FF		 685 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
686 DMA_TO_DEVICE);
fa1c114f 687
8a63facc 688 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 689 if (!rate) {
690 ret = -EINVAL;
691 goto err_unmap;
692 }
fa1c114f 693
8a63facc
BC		 694 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
695 flags |= AR5K_TXDESC_NOACK;
fa1c114f 696
8a63facc
BC		 697 rc_flags = info->control.rates[0].flags;
698 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
699 rate->hw_value_short : rate->hw_value;
42639fcd 700
8a63facc
BC		 701 pktlen = skb->len;
702
703 /* FIXME: If we are in g mode and rate is a CCK rate
704 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
705 * from tx power (value is in dB units already) */
706 if (info->control.hw_key) {
707 keyidx = info->control.hw_key->hw_key_idx;
708 pktlen += info->control.hw_key->icv_len;
709 }
710 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
711 flags |= AR5K_TXDESC_RTSENA;
712 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
713 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 714 info->control.vif, pktlen, info));
8a63facc
BC		 715 }
716 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
717 flags |= AR5K_TXDESC_CTSENA;
718 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
719 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 720 info->control.vif, pktlen, info));
8a63facc
BC		 721 }
722 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
723 ieee80211_get_hdrlen_from_skb(skb), padsize,
724 get_hw_packet_type(skb),
725 (sc->power_level * 2),
726 hw_rate,
727 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
728 cts_rate, duration);
729 if (ret)
730 goto err_unmap;
731
732 memset(mrr_rate, 0, sizeof(mrr_rate));
733 memset(mrr_tries, 0, sizeof(mrr_tries));
734 for (i = 0; i < 3; i++) {
735 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
736 if (!rate)
400ec45a 737 break;
fa1c114f 738
8a63facc
BC		 739 mrr_rate[i] = rate->hw_value;
740 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 741 }
742
8a63facc
BC		 743 ath5k_hw_setup_mrr_tx_desc(ah, ds,
744 mrr_rate[0], mrr_tries[0],
745 mrr_rate[1], mrr_tries[1],
746 mrr_rate[2], mrr_tries[2]);
fa1c114f 747
8a63facc
BC		 748 ds->ds_link = 0;
749 ds->ds_data = bf->skbaddr;
63266a65 750
8a63facc
BC		 751 spin_lock_bh(&txq->lock);
752 list_add_tail(&bf->list, &txq->q);
925e0b06 753 txq->txq_len++;
8a63facc
BC		 754 if (txq->link == NULL) /* is this first packet? */
755 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
756 else /* no, so only link it */
757 *txq->link = bf->daddr;
63266a65 758
8a63facc
BC		 759 txq->link = &ds->ds_link;
760 ath5k_hw_start_tx_dma(ah, txq->qnum);
761 mmiowb();
762 spin_unlock_bh(&txq->lock);
763
764 return 0;
765err_unmap:
aeae4ac9 766 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 767 return ret;
63266a65
BR		 768}
769
8a63facc
BC		 770/*******************\
771* Descriptors setup *
772\*******************/
773
d8ee398d 774static int
aeae4ac9 775ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 776{
8a63facc
BC		 777 struct ath5k_desc *ds;
778 struct ath5k_buf *bf;
779 dma_addr_t da;
780 unsigned int i;
781 int ret;
d8ee398d 782
8a63facc
BC		 783 /* allocate descriptors */
784 sc->desc_len = sizeof(struct ath5k_desc) *
785 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 786
787 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
788 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 789 if (sc->desc == NULL) {
790 ATH5K_ERR(sc, "can't allocate descriptors\n");
791 ret = -ENOMEM;
792 goto err;
793 }
794 ds = sc->desc;
795 da = sc->desc_daddr;
796 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
797 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 798
8a63facc
BC		 799 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
800 sizeof(struct ath5k_buf), GFP_KERNEL);
801 if (bf == NULL) {
802 ATH5K_ERR(sc, "can't allocate bufptr\n");
803 ret = -ENOMEM;
804 goto err_free;
805 }
806 sc->bufptr = bf;
fa1c114f 807
8a63facc
BC		 808 INIT_LIST_HEAD(&sc->rxbuf);
809 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
810 bf->desc = ds;
811 bf->daddr = da;
812 list_add_tail(&bf->list, &sc->rxbuf);
813 }
d8ee398d 814
8a63facc
BC		 815 INIT_LIST_HEAD(&sc->txbuf);
816 sc->txbuf_len = ATH_TXBUF;
817 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
818 da += sizeof(*ds)) {
819 bf->desc = ds;
820 bf->daddr = da;
821 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 822 }
823
b1ae1edf
BG		 824 /* beacon buffers */
825 INIT_LIST_HEAD(&sc->bcbuf);
826 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
827 bf->desc = ds;
828 bf->daddr = da;
829 list_add_tail(&bf->list, &sc->bcbuf);
830 }
fa1c114f 831
8a63facc
BC		 832 return 0;
833err_free:
aeae4ac9 834 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 835err:
836 sc->desc = NULL;
837 return ret;
838}
fa1c114f 839
cd2c5486
BR		 840void
841ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
842{
843 BUG_ON(!bf);
844 if (!bf->skb)
845 return;
846 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
847 DMA_TO_DEVICE);
848 dev_kfree_skb_any(bf->skb);
849 bf->skb = NULL;
850 bf->skbaddr = 0;
851 bf->desc->ds_data = 0;
852}
853
854void
855ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
856{
857 struct ath5k_hw *ah = sc->ah;
858 struct ath_common *common = ath5k_hw_common(ah);
859
860 BUG_ON(!bf);
861 if (!bf->skb)
862 return;
863 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
864 DMA_FROM_DEVICE);
865 dev_kfree_skb_any(bf->skb);
866 bf->skb = NULL;
867 bf->skbaddr = 0;
868 bf->desc->ds_data = 0;
869}
870
8a63facc 871static void
aeae4ac9 872ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 873{
874 struct ath5k_buf *bf;
d8ee398d 875
8a63facc
BC		 876 list_for_each_entry(bf, &sc->txbuf, list)
877 ath5k_txbuf_free_skb(sc, bf);
878 list_for_each_entry(bf, &sc->rxbuf, list)
879 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 880 list_for_each_entry(bf, &sc->bcbuf, list)
881 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 882
8a63facc 883 /* Free memory associated with all descriptors */
aeae4ac9 884 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 885 sc->desc = NULL;
886 sc->desc_daddr = 0;
d8ee398d 887
8a63facc
BC		 888 kfree(sc->bufptr);
889 sc->bufptr = NULL;
fa1c114f
JS		 890}
891
8a63facc
BC		 892
893/**************\
894* Queues setup *
895\**************/
896
897static struct ath5k_txq *
898ath5k_txq_setup(struct ath5k_softc *sc,
899 int qtype, int subtype)
fa1c114f 900{
8a63facc
BC		 901 struct ath5k_hw *ah = sc->ah;
902 struct ath5k_txq *txq;
903 struct ath5k_txq_info qi = {
904 .tqi_subtype = subtype,
de8af455
BR		 905 /* XXX: default values not correct for B and XR channels,
906 * but who cares? */
907 .tqi_aifs = AR5K_TUNE_AIFS,
908 .tqi_cw_min = AR5K_TUNE_CWMIN,
909 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 910 };
911 int qnum;
d8ee398d 912
e30eb4ab 913 /*
8a63facc
BC		 914 * Enable interrupts only for EOL and DESC conditions.
915 * We mark tx descriptors to receive a DESC interrupt
916 * when a tx queue gets deep; otherwise we wait for the
917 * EOL to reap descriptors. Note that this is done to
918 * reduce interrupt load and this only defers reaping
919 * descriptors, never transmitting frames. Aside from
920 * reducing interrupts this also permits more concurrency.
921 * The only potential downside is if the tx queue backs
922 * up in which case the top half of the kernel may backup
923 * due to a lack of tx descriptors.
e30eb4ab 924 */
8a63facc
BC		 925 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
926 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
927 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
928 if (qnum < 0) {
929 /*
930 * NB: don't print a message, this happens
931 * normally on parts with too few tx queues
932 */
933 return ERR_PTR(qnum);
934 }
935 if (qnum >= ARRAY_SIZE(sc->txqs)) {
936 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
937 qnum, ARRAY_SIZE(sc->txqs));
938 ath5k_hw_release_tx_queue(ah, qnum);
939 return ERR_PTR(-EINVAL);
940 }
941 txq = &sc->txqs[qnum];
942 if (!txq->setup) {
943 txq->qnum = qnum;
944 txq->link = NULL;
945 INIT_LIST_HEAD(&txq->q);
946 spin_lock_init(&txq->lock);
947 txq->setup = true;
925e0b06 948 txq->txq_len = 0;
81266baf 949 txq->txq_max = ATH5K_TXQ_LEN_MAX;
4edd761f 950 txq->txq_poll_mark = false;
923e5b3d 951 txq->txq_stuck = 0;
8a63facc
BC		 952 }
953 return &sc->txqs[qnum];
fa1c114f
JS		 954}
955
8a63facc
BC		 956static int
957ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 958{
8a63facc 959 struct ath5k_txq_info qi = {
de8af455
BR		 960 /* XXX: default values not correct for B and XR channels,
961 * but who cares? */
962 .tqi_aifs = AR5K_TUNE_AIFS,
963 .tqi_cw_min = AR5K_TUNE_CWMIN,
964 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 965 /* NB: for dynamic turbo, don't enable any other interrupts */
966 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
967 };
d8ee398d 968
8a63facc 969 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 970}
971
8a63facc
BC		 972static int
973ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 974{
975 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 976 struct ath5k_txq_info qi;
977 int ret;
fa1c114f 978
8a63facc
BC		 979 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
980 if (ret)
981 goto err;
fa1c114f 982
8a63facc
BC		 983 if (sc->opmode == NL80211_IFTYPE_AP ||
984 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
985 /*
986 * Always burst out beacon and CAB traffic
987 * (aifs = cwmin = cwmax = 0)
988 */
989 qi.tqi_aifs = 0;
990 qi.tqi_cw_min = 0;
991 qi.tqi_cw_max = 0;
992 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
993 /*
994 * Adhoc mode; backoff between 0 and (2 * cw_min).
995 */
996 qi.tqi_aifs = 0;
997 qi.tqi_cw_min = 0;
de8af455 998 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 999 }
fa1c114f 1000
8a63facc
BC		 1001 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1002 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1003 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1004
8a63facc
BC		 1005 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1006 if (ret) {
1007 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1008 "hardware queue!\n", __func__);
1009 goto err;
1010 }
1011 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1012 if (ret)
1013 goto err;
b7266047 1014
8a63facc
BC		 1015 /* reconfigure cabq with ready time to 80% of beacon_interval */
1016 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1017 if (ret)
1018 goto err;
b7266047 1019
8a63facc
BC		 1020 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1021 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1022 if (ret)
1023 goto err;
b7266047 1024
8a63facc
BC		 1025 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1026err:
1027 return ret;
d8ee398d
LR		 1028}
1029
80dac9ee
NK		 1030/**
1031 * ath5k_drain_tx_buffs - Empty tx buffers
1032 *
1033 * @sc The &struct ath5k_softc
1034 *
1035 * Empty tx buffers from all queues in preparation
1036 * of a reset or during shutdown.
1037 *
1038 * NB: this assumes output has been stopped and
1039 * we do not need to block ath5k_tx_tasklet
1040 */
8a63facc 1041static void
80dac9ee 1042ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1043{
80dac9ee 1044 struct ath5k_txq *txq;
8a63facc 1045 struct ath5k_buf *bf, *bf0;
80dac9ee 1046 int i;
b6ea0356 1047
80dac9ee
NK		 1048 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1049 if (sc->txqs[i].setup) {
1050 txq = &sc->txqs[i];
1051 spin_lock_bh(&txq->lock);
1052 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1053 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1054
80dac9ee 1055 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1056
80dac9ee
NK		 1057 spin_lock_bh(&sc->txbuflock);
1058 list_move_tail(&bf->list, &sc->txbuf);
1059 sc->txbuf_len++;
1060 txq->txq_len--;
1061 spin_unlock_bh(&sc->txbuflock);
8a63facc 1062 }
80dac9ee
NK		 1063 txq->link = NULL;
1064 txq->txq_poll_mark = false;
1065 spin_unlock_bh(&txq->lock);
1066 }
0452d4a5 1067 }
fa1c114f
JS		 1068}
1069
8a63facc
BC		 1070static void
1071ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1072{
8a63facc
BC		 1073 struct ath5k_txq *txq = sc->txqs;
1074 unsigned int i;
2ac2927a 1075
8a63facc
BC		 1076 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1077 if (txq->setup) {
1078 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1079 txq->setup = false;
1080 }
1081}
2ac2927a 1082
2ac2927a 1083
8a63facc
BC		 1084/*************\
1085* RX Handling *
1086\*************/
2ac2927a 1087
8a63facc
BC		 1088/*
1089 * Enable the receive h/w following a reset.
1090 */
fa1c114f 1091static int
8a63facc 1092ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1093{
1094 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1095 struct ath_common *common = ath5k_hw_common(ah);
1096 struct ath5k_buf *bf;
1097 int ret;
fa1c114f 1098
8a63facc 1099 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1100
8a63facc
BC		 1101 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1102 common->cachelsz, common->rx_bufsize);
2f7fe870 1103
8a63facc
BC		 1104 spin_lock_bh(&sc->rxbuflock);
1105 sc->rxlink = NULL;
1106 list_for_each_entry(bf, &sc->rxbuf, list) {
1107 ret = ath5k_rxbuf_setup(sc, bf);
1108 if (ret != 0) {
1109 spin_unlock_bh(&sc->rxbuflock);
1110 goto err;
1111 }
2f7fe870 1112 }
8a63facc
BC		 1113 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1114 ath5k_hw_set_rxdp(ah, bf->daddr);
1115 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1116
8a63facc 1117 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
e4b0b32a 1118 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */
8a63facc 1119 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1120
1121 return 0;
8a63facc 1122err:
fa1c114f
JS		 1123 return ret;
1124}
1125
8a63facc 1126/*
80dac9ee
NK		 1127 * Disable the receive logic on PCU (DRU)
1128 * In preparation for a shutdown.
1129 *
1130 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1131 * does.
8a63facc
BC		 1132 */
1133static void
1134ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1135{
8a63facc 1136 struct ath5k_hw *ah = sc->ah;
fa1c114f 1137
8a63facc 1138 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1139 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1140
8a63facc
BC		 1141 ath5k_debug_printrxbuffs(sc, ah);
1142}
fa1c114f 1143
8a63facc
BC		 1144static unsigned int
1145ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1146 struct ath5k_rx_status *rs)
1147{
1148 struct ath5k_hw *ah = sc->ah;
1149 struct ath_common *common = ath5k_hw_common(ah);
1150 struct ieee80211_hdr *hdr = (void *)skb->data;
1151 unsigned int keyix, hlen;
fa1c114f 1152
8a63facc
BC		 1153 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1154 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1155 return RX_FLAG_DECRYPTED;
fa1c114f 1156
8a63facc
BC		 1157 /* Apparently when a default key is used to decrypt the packet
1158 the hw does not set the index used to decrypt. In such cases
1159 get the index from the packet. */
1160 hlen = ieee80211_hdrlen(hdr->frame_control);
1161 if (ieee80211_has_protected(hdr->frame_control) &&
1162 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1163 skb->len >= hlen + 4) {
1164 keyix = skb->data[hlen + 3] >> 6;
1165
1166 if (test_bit(keyix, common->keymap))
1167 return RX_FLAG_DECRYPTED;
1168 }
fa1c114f
JS		 1169
1170 return 0;
fa1c114f
JS		 1171}
1172
8a63facc 1173
fa1c114f 1174static void
8a63facc
BC		 1175ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1176 struct ieee80211_rx_status *rxs)
fa1c114f 1177{
8a63facc
BC		 1178 struct ath_common *common = ath5k_hw_common(sc->ah);
1179 u64 tsf, bc_tstamp;
1180 u32 hw_tu;
1181 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1182
8a63facc
BC		 1183 if (ieee80211_is_beacon(mgmt->frame_control) &&
1184 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1185 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1186 /*
1187 * Received an IBSS beacon with the same BSSID. Hardware *must*
1188 * have updated the local TSF. We have to work around various
1189 * hardware bugs, though...
1190 */
1191 tsf = ath5k_hw_get_tsf64(sc->ah);
1192 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1193 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1194
8a63facc
BC		 1195 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1196 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1197 (unsigned long long)bc_tstamp,
1198 (unsigned long long)rxs->mactime,
1199 (unsigned long long)(rxs->mactime - bc_tstamp),
1200 (unsigned long long)tsf);
fa1c114f 1201
8a63facc
BC		 1202 /*
1203 * Sometimes the HW will give us a wrong tstamp in the rx
1204 * status, causing the timestamp extension to go wrong.
1205 * (This seems to happen especially with beacon frames bigger
1206 * than 78 byte (incl. FCS))
1207 * But we know that the receive timestamp must be later than the
1208 * timestamp of the beacon since HW must have synced to that.
1209 *
1210 * NOTE: here we assume mactime to be after the frame was
1211 * received, not like mac80211 which defines it at the start.
1212 */
1213 if (bc_tstamp > rxs->mactime) {
1214 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1215 "fixing mactime from %llx to %llx\n",
1216 (unsigned long long)rxs->mactime,
1217 (unsigned long long)tsf);
1218 rxs->mactime = tsf;
1219 }
fa1c114f 1220
8a63facc
BC		 1221 /*
1222 * Local TSF might have moved higher than our beacon timers,
1223 * in that case we have to update them to continue sending
1224 * beacons. This also takes care of synchronizing beacon sending
1225 * times with other stations.
1226 */
1227 if (hw_tu >= sc->nexttbtt)
1228 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1229
1230 /* Check if the beacon timers are still correct, because a TSF
1231 * update might have created a window between them - for a
1232 * longer description see the comment of this function: */
1233 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1234 ath5k_beacon_update_timers(sc, bc_tstamp);
1235 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1236 "fixed beacon timers after beacon receive\n");
1237 }
8a63facc
BC		 1238 }
1239}
fa1c114f 1240
8a63facc
BC		 1241static void
1242ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1243{
1244 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1245 struct ath5k_hw *ah = sc->ah;
1246 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1247
8a63facc
BC		 1248 /* only beacons from our BSSID */
1249 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1250 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1251 return;
fa1c114f 1252
eef39bef 1253 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1254
8a63facc
BC		 1255 /* in IBSS mode we should keep RSSI statistics per neighbour */
1256 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1257}
fa1c114f 1258
8a63facc
BC		 1259/*
1260 * Compute padding position. skb must contain an IEEE 802.11 frame
1261 */
1262static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1263{
8a63facc
BC		 1264 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1265 __le16 frame_control = hdr->frame_control;
1266 int padpos = 24;
fa1c114f 1267
8a63facc
BC		 1268 if (ieee80211_has_a4(frame_control)) {
1269 padpos += ETH_ALEN;
fa1c114f 1270 }
8a63facc
BC		 1271 if (ieee80211_is_data_qos(frame_control)) {
1272 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1273 }
8a63facc
BC		 1274
1275 return padpos;
fa1c114f
JS		 1276}
1277
8a63facc
BC		 1278/*
1279 * This function expects an 802.11 frame and returns the number of
1280 * bytes added, or -1 if we don't have enough header room.
1281 */
1282static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1283{
8a63facc
BC		 1284 int padpos = ath5k_common_padpos(skb);
1285 int padsize = padpos & 3;
fa1c114f 1286
8a63facc 1287 if (padsize && skb->len>padpos) {
fa1c114f 1288
8a63facc
BC		 1289 if (skb_headroom(skb) < padsize)
1290 return -1;
fa1c114f 1291
8a63facc
BC		 1292 skb_push(skb, padsize);
1293 memmove(skb->data, skb->data+padsize, padpos);
1294 return padsize;
1295 }
a951ae21 1296
8a63facc
BC		 1297 return 0;
1298}
fa1c114f 1299
8a63facc
BC		 1300/*
1301 * The MAC header is padded to have 32-bit boundary if the
1302 * packet payload is non-zero. The general calculation for
1303 * padsize would take into account odd header lengths:
1304 * padsize = 4 - (hdrlen & 3); however, since only
1305 * even-length headers are used, padding can only be 0 or 2
1306 * bytes and we can optimize this a bit. We must not try to
1307 * remove padding from short control frames that do not have a
1308 * payload.
1309 *
1310 * This function expects an 802.11 frame and returns the number of
1311 * bytes removed.
1312 */
1313static int ath5k_remove_padding(struct sk_buff *skb)
1314{
1315 int padpos = ath5k_common_padpos(skb);
1316 int padsize = padpos & 3;
6d91e1d8 1317
8a63facc
BC		 1318 if (padsize && skb->len>=padpos+padsize) {
1319 memmove(skb->data + padsize, skb->data, padpos);
1320 skb_pull(skb, padsize);
1321 return padsize;
fa1c114f 1322 }
a951ae21 1323
8a63facc 1324 return 0;
fa1c114f
JS		 1325}
1326
1327static void
8a63facc
BC		 1328ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1329 struct ath5k_rx_status *rs)
fa1c114f 1330{
8a63facc
BC		 1331 struct ieee80211_rx_status *rxs;
1332
1333 ath5k_remove_padding(skb);
1334
1335 rxs = IEEE80211_SKB_RXCB(skb);
1336
1337 rxs->flag = 0;
1338 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1339 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1340
1341 /*
8a63facc
BC		 1342 * always extend the mac timestamp, since this information is
1343 * also needed for proper IBSS merging.
1344 *
1345 * XXX: it might be too late to do it here, since rs_tstamp is
1346 * 15bit only. that means TSF extension has to be done within
1347 * 32768usec (about 32ms). it might be necessary to move this to
1348 * the interrupt handler, like it is done in madwifi.
1349 *
1350 * Unfortunately we don't know when the hardware takes the rx
1351 * timestamp (beginning of phy frame, data frame, end of rx?).
1352 * The only thing we know is that it is hardware specific...
1353 * On AR5213 it seems the rx timestamp is at the end of the
1354 * frame, but i'm not sure.
1355 *
1356 * NOTE: mac80211 defines mactime at the beginning of the first
1357 * data symbol. Since we don't have any time references it's
1358 * impossible to comply to that. This affects IBSS merge only
1359 * right now, so it's not too bad...
fa1c114f 1360 */
8a63facc 1361 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
6ebacbb7 1362 rxs->flag |= RX_FLAG_MACTIME_MPDU;
fa1c114f 1363
8a63facc 1364 rxs->freq = sc->curchan->center_freq;
930a7622 1365 rxs->band = sc->curchan->band;
fa1c114f 1366
8a63facc 1367 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1368
8a63facc 1369 rxs->antenna = rs->rs_antenna;
fa1c114f 1370
8a63facc
BC		 1371 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1372 sc->stats.antenna_rx[rs->rs_antenna]++;
1373 else
1374 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1375
8a63facc
BC		 1376 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1377 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1378
8a63facc 1379 if (rxs->rate_idx >= 0 && rs->rs_rate ==
930a7622 1380 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1381 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1382
0e472252 1383 trace_ath5k_rx(sc, skb);
fa1c114f 1384
8a63facc 1385 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1386
8a63facc
BC		 1387 /* check beacons in IBSS mode */
1388 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1389 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1390
8a63facc
BC		 1391 ieee80211_rx(sc->hw, skb);
1392}
fa1c114f 1393
8a63facc
BC		 1394/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1395 *
1396 * Check if we want to further process this frame or not. Also update
1397 * statistics. Return true if we want this frame, false if not.
fa1c114f 1398 */
8a63facc
BC		 1399static bool
1400ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1401{
8a63facc 1402 sc->stats.rx_all_count++;
b72acddb 1403 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1404
8a63facc
BC		 1405 if (unlikely(rs->rs_status)) {
1406 if (rs->rs_status & AR5K_RXERR_CRC)
1407 sc->stats.rxerr_crc++;
1408 if (rs->rs_status & AR5K_RXERR_FIFO)
1409 sc->stats.rxerr_fifo++;
1410 if (rs->rs_status & AR5K_RXERR_PHY) {
1411 sc->stats.rxerr_phy++;
1412 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1413 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1414 return false;
1415 }
1416 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1417 /*
1418 * Decrypt error. If the error occurred
1419 * because there was no hardware key, then
1420 * let the frame through so the upper layers
1421 * can process it. This is necessary for 5210
1422 * parts which have no way to setup a ``clear''
1423 * key cache entry.
1424 *
1425 * XXX do key cache faulting
1426 */
1427 sc->stats.rxerr_decrypt++;
1428 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1429 !(rs->rs_status & AR5K_RXERR_CRC))
1430 return true;
1431 }
1432 if (rs->rs_status & AR5K_RXERR_MIC) {
1433 sc->stats.rxerr_mic++;
1434 return true;
fa1c114f 1435 }
fa1c114f 1436
8a63facc
BC		 1437 /* reject any frames with non-crypto errors */
1438 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1439 return false;
1440 }
fa1c114f 1441
8a63facc
BC		 1442 if (unlikely(rs->rs_more)) {
1443 sc->stats.rxerr_jumbo++;
1444 return false;
1445 }
1446 return true;
fa1c114f
JS		 1447}
1448
c266c71a
FF		 1449static void
1450ath5k_set_current_imask(struct ath5k_softc *sc)
1451{
1452 enum ath5k_int imask = sc->imask;
1453 unsigned long flags;
1454
1455 spin_lock_irqsave(&sc->irqlock, flags);
1456 if (sc->rx_pending)
1457 imask &= ~AR5K_INT_RX_ALL;
1458 if (sc->tx_pending)
1459 imask &= ~AR5K_INT_TX_ALL;
1460 ath5k_hw_set_imr(sc->ah, imask);
1461 spin_unlock_irqrestore(&sc->irqlock, flags);
1462}
1463
fa1c114f 1464static void
8a63facc 1465ath5k_tasklet_rx(unsigned long data)
fa1c114f 1466{
8a63facc
BC		 1467 struct ath5k_rx_status rs = {};
1468 struct sk_buff *skb, *next_skb;
1469 dma_addr_t next_skb_addr;
1470 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1471 struct ath5k_hw *ah = sc->ah;
1472 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1473 struct ath5k_buf *bf;
1474 struct ath5k_desc *ds;
1475 int ret;
fa1c114f 1476
8a63facc
BC		 1477 spin_lock(&sc->rxbuflock);
1478 if (list_empty(&sc->rxbuf)) {
1479 ATH5K_WARN(sc, "empty rx buf pool\n");
1480 goto unlock;
1481 }
1482 do {
1483 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1484 BUG_ON(bf->skb == NULL);
1485 skb = bf->skb;
1486 ds = bf->desc;
fa1c114f 1487
8a63facc
BC		 1488 /* bail if HW is still using self-linked descriptor */
1489 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1490 break;
fa1c114f 1491
8a63facc
BC		 1492 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1493 if (unlikely(ret == -EINPROGRESS))
1494 break;
1495 else if (unlikely(ret)) {
1496 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1497 sc->stats.rxerr_proc++;
1498 break;
1499 }
fa1c114f 1500
8a63facc
BC		 1501 if (ath5k_receive_frame_ok(sc, &rs)) {
1502 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1503
8a63facc
BC		 1504 /*
1505 * If we can't replace bf->skb with a new skb under
1506 * memory pressure, just skip this packet
1507 */
1508 if (!next_skb)
1509 goto next;
036cd1ec 1510
aeae4ac9 1511 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1512 common->rx_bufsize,
aeae4ac9 1513 DMA_FROM_DEVICE);
036cd1ec 1514
8a63facc 1515 skb_put(skb, rs.rs_datalen);
6ba81c2c 1516
8a63facc 1517 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1518
8a63facc
BC		 1519 bf->skb = next_skb;
1520 bf->skbaddr = next_skb_addr;
036cd1ec 1521 }
8a63facc
BC		 1522next:
1523 list_move_tail(&bf->list, &sc->rxbuf);
1524 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1525unlock:
1526 spin_unlock(&sc->rxbuflock);
c266c71a
FF		 1527 sc->rx_pending = false;
1528 ath5k_set_current_imask(sc);
036cd1ec
BR		 1529}
1530
b4ea449d 1531
8a63facc
BC		 1532/*************\
1533* TX Handling *
1534\*************/
b4ea449d 1535
7bb45683 1536void
cd2c5486
BR		 1537ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1538 struct ath5k_txq *txq)
8a63facc
BC		 1539{
1540 struct ath5k_softc *sc = hw->priv;
1541 struct ath5k_buf *bf;
1542 unsigned long flags;
1543 int padsize;
b4ea449d 1544
0e472252 1545 trace_ath5k_tx(sc, skb, txq);
b4ea449d 1546
8a63facc
BC		 1547 /*
1548 * The hardware expects the header padded to 4 byte boundaries.
1549 * If this is not the case, we add the padding after the header.
1550 */
1551 padsize = ath5k_add_padding(skb);
1552 if (padsize < 0) {
1553 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1554 " headroom to pad");
1555 goto drop_packet;
1556 }
8127fbdc 1557
81266baf 1558 if (txq->txq_len >= txq->txq_max)
925e0b06
BR		 1559 ieee80211_stop_queue(hw, txq->qnum);
1560
8a63facc
BC		 1561 spin_lock_irqsave(&sc->txbuflock, flags);
1562 if (list_empty(&sc->txbuf)) {
1563 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1564 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1565 ieee80211_stop_queues(hw);
8a63facc 1566 goto drop_packet;
8127fbdc 1567 }
8a63facc
BC		 1568 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1569 list_del(&bf->list);
1570 sc->txbuf_len--;
1571 if (list_empty(&sc->txbuf))
1572 ieee80211_stop_queues(hw);
1573 spin_unlock_irqrestore(&sc->txbuflock, flags);
1574
1575 bf->skb = skb;
1576
1577 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1578 bf->skb = NULL;
1579 spin_lock_irqsave(&sc->txbuflock, flags);
1580 list_add_tail(&bf->list, &sc->txbuf);
1581 sc->txbuf_len++;
1582 spin_unlock_irqrestore(&sc->txbuflock, flags);
1583 goto drop_packet;
8127fbdc 1584 }
7bb45683 1585 return;
8127fbdc 1586
8a63facc
BC		 1587drop_packet:
1588 dev_kfree_skb_any(skb);
8127fbdc
BP		 1589}
1590
1440401e
BR		 1591static void
1592ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
0e472252 1593 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1440401e
BR		 1594{
1595 struct ieee80211_tx_info *info;
ed895085 1596 u8 tries[3];
1440401e
BR		 1597 int i;
1598
1599 sc->stats.tx_all_count++;
b72acddb 1600 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1601 info = IEEE80211_SKB_CB(skb);
1602
ed895085
FF		 1603 tries[0] = info->status.rates[0].count;
1604 tries[1] = info->status.rates[1].count;
1605 tries[2] = info->status.rates[2].count;
1606
1440401e 1607 ieee80211_tx_info_clear_status(info);
ed895085
FF		 1608
1609 for (i = 0; i < ts->ts_final_idx; i++) {
1440401e
BR		 1610 struct ieee80211_tx_rate *r =
1611 &info->status.rates[i];
1612
ed895085 1613 r->count = tries[i];
1440401e
BR		 1614 }
1615
ed895085 1616 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
6d7b97b2 1617 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1440401e
BR		 1618
1619 if (unlikely(ts->ts_status)) {
1620 sc->stats.ack_fail++;
1621 if (ts->ts_status & AR5K_TXERR_FILT) {
1622 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1623 sc->stats.txerr_filt++;
1624 }
1625 if (ts->ts_status & AR5K_TXERR_XRETRY)
1626 sc->stats.txerr_retry++;
1627 if (ts->ts_status & AR5K_TXERR_FIFO)
1628 sc->stats.txerr_fifo++;
1629 } else {
1630 info->flags |= IEEE80211_TX_STAT_ACK;
1631 info->status.ack_signal = ts->ts_rssi;
6d7b97b2
FF		 1632
1633 /* count the successful attempt as well */
1634 info->status.rates[ts->ts_final_idx].count++;
1440401e
BR		 1635 }
1636
1637 /*
1638 * Remove MAC header padding before giving the frame
1639 * back to mac80211.
1640 */
1641 ath5k_remove_padding(skb);
1642
1643 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1644 sc->stats.antenna_tx[ts->ts_antenna]++;
1645 else
1646 sc->stats.antenna_tx[0]++; /* invalid */
1647
0e472252 1648 trace_ath5k_tx_complete(sc, skb, txq, ts);
1440401e
BR		 1649 ieee80211_tx_status(sc->hw, skb);
1650}
8a63facc
BC		 1651
1652static void
1653ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1654{
8a63facc
BC		 1655 struct ath5k_tx_status ts = {};
1656 struct ath5k_buf *bf, *bf0;
1657 struct ath5k_desc *ds;
1658 struct sk_buff *skb;
1440401e 1659 int ret;
8127fbdc 1660
8a63facc
BC		 1661 spin_lock(&txq->lock);
1662 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1663
1664 txq->txq_poll_mark = false;
1665
1666 /* skb might already have been processed last time. */
1667 if (bf->skb != NULL) {
1668 ds = bf->desc;
1669
1670 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1671 if (unlikely(ret == -EINPROGRESS))
1672 break;
1673 else if (unlikely(ret)) {
1674 ATH5K_ERR(sc,
1675 "error %d while processing "
1676 "queue %u\n", ret, txq->qnum);
1677 break;
1678 }
1679
1680 skb = bf->skb;
1681 bf->skb = NULL;
aeae4ac9
FF		 1682
1683 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1684 DMA_TO_DEVICE);
0e472252 1685 ath5k_tx_frame_completed(sc, skb, txq, &ts);
23413296 1686 }
8127fbdc 1687
8a63facc
BC		 1688 /*
1689 * It's possible that the hardware can say the buffer is
1690 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1691 * host memory and moved on.
1692 * Always keep the last descriptor to avoid HW races...
8a63facc 1693 */
23413296
BR		 1694 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1695 spin_lock(&sc->txbuflock);
1696 list_move_tail(&bf->list, &sc->txbuf);
1697 sc->txbuf_len++;
1698 txq->txq_len--;
1699 spin_unlock(&sc->txbuflock);
8a63facc 1700 }
fa1c114f 1701 }
fa1c114f 1702 spin_unlock(&txq->lock);
4198a8d0 1703 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1704 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1705}
1706
1707static void
1708ath5k_tasklet_tx(unsigned long data)
1709{
8784d2ee 1710 int i;
fa1c114f
JS		 1711 struct ath5k_softc *sc = (void *)data;
1712
8784d2ee
BC		 1713 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1714 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1715 ath5k_tx_processq(sc, &sc->txqs[i]);
c266c71a
FF		 1716
1717 sc->tx_pending = false;
1718 ath5k_set_current_imask(sc);
fa1c114f
JS		 1719}
1720
1721
fa1c114f
JS		 1722/*****************\
1723* Beacon handling *
1724\*****************/
1725
1726/*
1727 * Setup the beacon frame for transmit.
1728 */
1729static int
e039fa4a 1730ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1731{
1732 struct sk_buff *skb = bf->skb;
a888d52d 1733 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1734 struct ath5k_hw *ah = sc->ah;
1735 struct ath5k_desc *ds;
2bed03eb
NK		 1736 int ret = 0;
1737 u8 antenna;
fa1c114f 1738 u32 flags;
8127fbdc 1739 const int padsize = 0;
fa1c114f 1740
aeae4ac9
FF		 1741 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1742 DMA_TO_DEVICE);
fa1c114f
JS		 1743 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1744 "skbaddr %llx\n", skb, skb->data, skb->len,
1745 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1746
1747 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1748 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1749 return -EIO;
1750 }
1751
1752 ds = bf->desc;
2bed03eb 1753 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1754
1755 flags = AR5K_TXDESC_NOACK;
05c914fe 1756 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1757 ds->ds_link = bf->daddr; /* self-linked */
1758 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1759 } else
fa1c114f 1760 ds->ds_link = 0;
2bed03eb
NK		 1761
1762 /*
1763 * If we use multiple antennas on AP and use
1764 * the Sectored AP scenario, switch antenna every
1765 * 4 beacons to make sure everybody hears our AP.
1766 * When a client tries to associate, hw will keep
1767 * track of the tx antenna to be used for this client
1768 * automaticaly, based on ACKed packets.
1769 *
1770 * Note: AP still listens and transmits RTS on the
1771 * default antenna which is supposed to be an omni.
1772 *
1773 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1774 * multiple antennas (1 omni -- the default -- and 14
1775 * sectors), so if we choose to actually support this
1776 * mode, we need to allow the user to set how many antennas
1777 * we have and tweak the code below to send beacons
1778 * on all of them.
2bed03eb
NK		 1779 */
1780 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1781 antenna = sc->bsent & 4 ? 2 : 1;
1782
fa1c114f 1783
8f655dde
NK		 1784 /* FIXME: If we are in g mode and rate is a CCK rate
1785 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1786 * from tx power (value is in dB units already) */
fa1c114f 1787 ds->ds_data = bf->skbaddr;
281c56dd 1788 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1789 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1790 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1791 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1792 1, AR5K_TXKEYIX_INVALID,
400ec45a 1793 antenna, flags, 0, 0);
fa1c114f
JS		 1794 if (ret)
1795 goto err_unmap;
1796
1797 return 0;
1798err_unmap:
aeae4ac9 1799 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1800 return ret;
1801}
1802
8a63facc
BC		 1803/*
1804 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1805 * this is called only once at config_bss time, for AP we do it every
1806 * SWBA interrupt so that the TIM will reflect buffered frames.
1807 *
1808 * Called with the beacon lock.
1809 */
cd2c5486 1810int
8a63facc
BC		 1811ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1812{
1813 int ret;
1814 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1815 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1816 struct sk_buff *skb;
1817
1818 if (WARN_ON(!vif)) {
1819 ret = -EINVAL;
1820 goto out;
1821 }
1822
1823 skb = ieee80211_beacon_get(hw, vif);
1824
1825 if (!skb) {
1826 ret = -ENOMEM;
1827 goto out;
1828 }
1829
b1ae1edf
BG		 1830 ath5k_txbuf_free_skb(sc, avf->bbuf);
1831 avf->bbuf->skb = skb;
1832 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1833 if (ret)
b1ae1edf 1834 avf->bbuf->skb = NULL;
8a63facc
BC		 1835out:
1836 return ret;
1837}
1838
fa1c114f
JS		 1839/*
1840 * Transmit a beacon frame at SWBA. Dynamic updates to the
1841 * frame contents are done as needed and the slot time is
1842 * also adjusted based on current state.
1843 *
5faaff74
BC		 1844 * This is called from software irq context (beacontq tasklets)
1845 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1846 */
1847static void
1848ath5k_beacon_send(struct ath5k_softc *sc)
1849{
fa1c114f 1850 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1851 struct ieee80211_vif *vif;
1852 struct ath5k_vif *avf;
1853 struct ath5k_buf *bf;
cec8db23 1854 struct sk_buff *skb;
fa1c114f 1855
be9b7259 1856 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1857
fa1c114f
JS		 1858 /*
1859 * Check if the previous beacon has gone out. If
a180a130 1860 * not, don't don't try to post another: skip this
fa1c114f
JS		 1861 * period and wait for the next. Missed beacons
1862 * indicate a problem and should not occur. If we
1863 * miss too many consecutive beacons reset the device.
1864 */
1865 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1866 sc->bmisscount++;
be9b7259 1867 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1868 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1869 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1870 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1871 "stuck beacon time (%u missed)\n",
1872 sc->bmisscount);
8d67a031
BR		 1873 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1874 "stuck beacon, resetting\n");
5faaff74 1875 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1876 }
1877 return;
1878 }
1879 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1880 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1881 "resume beacon xmit after %u misses\n",
1882 sc->bmisscount);
1883 sc->bmisscount = 0;
1884 }
1885
b93996cf
JC		 1886 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1887 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1888 u64 tsf = ath5k_hw_get_tsf64(ah);
1889 u32 tsftu = TSF_TO_TU(tsf);
1890 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1891 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1892 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1893 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1894 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1895 } else /* only one interface */
1896 vif = sc->bslot[0];
1897
1898 if (!vif)
1899 return;
1900
1901 avf = (void *)vif->drv_priv;
1902 bf = avf->bbuf;
1903 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1904 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1905 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1906 return;
1907 }
1908
fa1c114f
JS		 1909 /*
1910 * Stop any current dma and put the new frame on the queue.
1911 * This should never fail since we check above that no frames
1912 * are still pending on the queue.
1913 */
14fae2d4 1914 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1915 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1916 /* NB: hw still stops DMA, so proceed */
1917 }
fa1c114f 1918
d82b577b
JC		 1919 /* refresh the beacon for AP or MESH mode */
1920 if (sc->opmode == NL80211_IFTYPE_AP ||
1921 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1922 ath5k_beacon_update(sc->hw, vif);
1071db86 1923
0e472252
BC		 1924 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
1925
c6e387a2
NK		 1926 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1927 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1928 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1929 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1930
b1ae1edf 1931 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1932 while (skb) {
1933 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1934 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1935 }
1936
fa1c114f
JS		 1937 sc->bsent++;
1938}
1939
9804b98d
BR		 1940/**
1941 * ath5k_beacon_update_timers - update beacon timers
1942 *
1943 * @sc: struct ath5k_softc pointer we are operating on
1944 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1945 * beacon timer update based on the current HW TSF.
1946 *
1947 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1948 * of a received beacon or the current local hardware TSF and write it to the
1949 * beacon timer registers.
1950 *
1951 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1952 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1953 * when we otherwise know we have to update the timers, but we keep it in this
1954 * function to have it all together in one place.
1955 */
cd2c5486 1956void
9804b98d 1957ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1958{
1959 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1960 u32 nexttbtt, intval, hw_tu, bc_tu;
1961 u64 hw_tsf;
fa1c114f
JS		 1962
1963 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1964 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1965 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1966 if (intval < 15)
1967 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1968 intval);
1969 }
fa1c114f
JS		 1970 if (WARN_ON(!intval))
1971 return;
1972
9804b98d
BR		 1973 /* beacon TSF converted to TU */
1974 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1975
9804b98d
BR		 1976 /* current TSF converted to TU */
1977 hw_tsf = ath5k_hw_get_tsf64(ah);
1978 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1979
11f21df3
BR		 1980#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1981 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
25985edc 1982 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
11f21df3
BR		 1983 * configuration we need to make sure it is bigger than that. */
1984
9804b98d
BR		 1985 if (bc_tsf == -1) {
1986 /*
1987 * no beacons received, called internally.
1988 * just need to refresh timers based on HW TSF.
1989 */
1990 nexttbtt = roundup(hw_tu + FUDGE, intval);
1991 } else if (bc_tsf == 0) {
1992 /*
1993 * no beacon received, probably called by ath5k_reset_tsf().
1994 * reset TSF to start with 0.
1995 */
1996 nexttbtt = intval;
1997 intval |= AR5K_BEACON_RESET_TSF;
1998 } else if (bc_tsf > hw_tsf) {
1999 /*
25985edc 2000 * beacon received, SW merge happened but HW TSF not yet updated.
9804b98d
BR		 2001 * not possible to reconfigure timers yet, but next time we
2002 * receive a beacon with the same BSSID, the hardware will
2003 * automatically update the TSF and then we need to reconfigure
2004 * the timers.
2005 */
2006 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2007 "need to wait for HW TSF sync\n");
2008 return;
2009 } else {
2010 /*
2011 * most important case for beacon synchronization between STA.
2012 *
2013 * beacon received and HW TSF has been already updated by HW.
2014 * update next TBTT based on the TSF of the beacon, but make
2015 * sure it is ahead of our local TSF timer.
2016 */
2017 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2018 }
2019#undef FUDGE
fa1c114f 2020
036cd1ec
BR		 2021 sc->nexttbtt = nexttbtt;
2022
fa1c114f 2023 intval |= AR5K_BEACON_ENA;
fa1c114f 2024 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2025
2026 /*
2027 * debugging output last in order to preserve the time critical aspect
2028 * of this function
2029 */
2030 if (bc_tsf == -1)
2031 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2032 "reconfigured timers based on HW TSF\n");
2033 else if (bc_tsf == 0)
2034 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2035 "reset HW TSF and timers\n");
2036 else
2037 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2038 "updated timers based on beacon TSF\n");
2039
2040 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2041 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2042 (unsigned long long) bc_tsf,
2043 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2044 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2045 intval & AR5K_BEACON_PERIOD,
2046 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2047 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2048}
2049
036cd1ec
BR		 2050/**
2051 * ath5k_beacon_config - Configure the beacon queues and interrupts
2052 *
2053 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2054 *
036cd1ec 2055 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2056 * interrupts to detect TSF updates only.
fa1c114f 2057 */
cd2c5486 2058void
fa1c114f
JS		 2059ath5k_beacon_config(struct ath5k_softc *sc)
2060{
2061 struct ath5k_hw *ah = sc->ah;
b5f03956 2062 unsigned long flags;
fa1c114f 2063
21800491 2064 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2065 sc->bmisscount = 0;
dc1968e7 2066 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2067
21800491 2068 if (sc->enable_beacon) {
fa1c114f 2069 /*
036cd1ec
BR		 2070 * In IBSS mode we use a self-linked tx descriptor and let the
2071 * hardware send the beacons automatically. We have to load it
fa1c114f 2072 * only once here.
036cd1ec 2073 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2074 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2075 */
2076 ath5k_beaconq_config(sc);
fa1c114f 2077
036cd1ec
BR		 2078 sc->imask |= AR5K_INT_SWBA;
2079
da966bca 2080 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2081 if (ath5k_hw_hasveol(ah))
da966bca 2082 ath5k_beacon_send(sc);
da966bca
JS		 2083 } else
2084 ath5k_beacon_update_timers(sc, -1);
21800491 2085 } else {
14fae2d4 2086 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2087 }
fa1c114f 2088
c6e387a2 2089 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2090 mmiowb();
2091 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2092}
2093
428cbd4f
NK		 2094static void ath5k_tasklet_beacon(unsigned long data)
2095{
2096 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2097
2098 /*
2099 * Software beacon alert--time to send a beacon.
2100 *
2101 * In IBSS mode we use this interrupt just to
2102 * keep track of the next TBTT (target beacon
2103 * transmission time) in order to detect wether
2104 * automatic TSF updates happened.
2105 */
2106 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2107 /* XXX: only if VEOL suppported */
2108 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2109 sc->nexttbtt += sc->bintval;
2110 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2111 "SWBA nexttbtt: %x hw_tu: %x "
2112 "TSF: %llx\n",
2113 sc->nexttbtt,
2114 TSF_TO_TU(tsf),
2115 (unsigned long long) tsf);
2116 } else {
2117 spin_lock(&sc->block);
2118 ath5k_beacon_send(sc);
2119 spin_unlock(&sc->block);
2120 }
2121}
2122
fa1c114f
JS		 2123
2124/********************\
2125* Interrupt handling *
2126\********************/
2127
6a8a3f6b
BR		 2128static void
2129ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2130{
2111ac0d
BR		 2131 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2132 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2133 /* run ANI only when full calibration is not active */
2134 ah->ah_cal_next_ani = jiffies +
2135 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2136 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2137
2138 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2139 ah->ah_cal_next_full = jiffies +
2140 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2141 tasklet_schedule(&ah->ah_sc->calib);
2142 }
2143 /* we could use SWI to generate enough interrupts to meet our
2144 * calibration interval requirements, if necessary:
2145 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2146}
2147
c266c71a
FF		 2148static void
2149ath5k_schedule_rx(struct ath5k_softc *sc)
2150{
2151 sc->rx_pending = true;
2152 tasklet_schedule(&sc->rxtq);
2153}
2154
2155static void
2156ath5k_schedule_tx(struct ath5k_softc *sc)
2157{
2158 sc->tx_pending = true;
2159 tasklet_schedule(&sc->txtq);
2160}
2161
f5cbc8ba 2162static irqreturn_t
fa1c114f
JS		 2163ath5k_intr(int irq, void *dev_id)
2164{
2165 struct ath5k_softc *sc = dev_id;
2166 struct ath5k_hw *ah = sc->ah;
2167 enum ath5k_int status;
2168 unsigned int counter = 1000;
2169
2170 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2171 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2172 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2173 return IRQ_NONE;
2174
2175 do {
fa1c114f
JS		 2176 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2177 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2178 status, sc->imask);
fa1c114f
JS		 2179 if (unlikely(status & AR5K_INT_FATAL)) {
2180 /*
2181 * Fatal errors are unrecoverable.
2182 * Typically these are caused by DMA errors.
2183 */
8d67a031
BR		 2184 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2185 "fatal int, resetting\n");
5faaff74 2186 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2187 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2188 /*
2189 * Receive buffers are full. Either the bus is busy or
2190 * the CPU is not fast enough to process all received
2191 * frames.
2192 * Older chipsets need a reset to come out of this
2193 * condition, but we treat it as RX for newer chips.
2194 * We don't know exactly which versions need a reset -
2195 * this guess is copied from the HAL.
2196 */
2197 sc->stats.rxorn_intr++;
8d67a031
BR		 2198 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2199 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2200 "rx overrun, resetting\n");
5faaff74 2201 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2202 }
87d77c4e 2203 else
c266c71a 2204 ath5k_schedule_rx(sc);
fa1c114f
JS		 2205 } else {
2206 if (status & AR5K_INT_SWBA) {
56d2ac76 2207 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2208 }
2209 if (status & AR5K_INT_RXEOL) {
2210 /*
2211 * NB: the hardware should re-read the link when
2212 * RXE bit is written, but it doesn't work at
2213 * least on older hardware revs.
2214 */
b3f194e5 2215 sc->stats.rxeol_intr++;
fa1c114f
JS		 2216 }
2217 if (status & AR5K_INT_TXURN) {
2218 /* bump tx trigger level */
2219 ath5k_hw_update_tx_triglevel(ah, true);
2220 }
4c674c60 2221 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
c266c71a 2222 ath5k_schedule_rx(sc);
4c674c60
NK		 2223 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2224 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
c266c71a 2225 ath5k_schedule_tx(sc);
fa1c114f 2226 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2227 /* TODO */
fa1c114f
JS		 2228 }
2229 if (status & AR5K_INT_MIB) {
2111ac0d 2230 sc->stats.mib_intr++;
495391d7 2231 ath5k_hw_update_mib_counters(ah);
2111ac0d 2232 ath5k_ani_mib_intr(ah);
fa1c114f 2233 }
e6a3b616 2234 if (status & AR5K_INT_GPIO)
e6a3b616 2235 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2236
fa1c114f 2237 }
4cebb34c
FF		 2238
2239 if (ath5k_get_bus_type(ah) == ATH_AHB)
2240 break;
2241
2516baa6 2242 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f 2243
c266c71a
FF		 2244 if (sc->rx_pending || sc->tx_pending)
2245 ath5k_set_current_imask(sc);
2246
fa1c114f
JS		 2247 if (unlikely(!counter))
2248 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2249
6a8a3f6b 2250 ath5k_intr_calibration_poll(ah);
6e220662 2251
fa1c114f
JS		 2252 return IRQ_HANDLED;
2253}
2254
fa1c114f
JS		 2255/*
2256 * Periodically recalibrate the PHY to account
2257 * for temperature/environment changes.
2258 */
2259static void
6e220662 2260ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2261{
2262 struct ath5k_softc *sc = (void *)data;
2263 struct ath5k_hw *ah = sc->ah;
2264
6e220662 2265 /* Only full calibration for now */
e65e1d77 2266 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2267
fa1c114f 2268 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2269 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2270 sc->curchan->hw_value);
fa1c114f 2271
6f3b414a 2272 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2273 /*
2274 * Rfgain is out of bounds, reset the chip
2275 * to load new gain values.
2276 */
2277 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2278 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2279 }
2280 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2281 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2282 ieee80211_frequency_to_channel(
2283 sc->curchan->center_freq));
fa1c114f 2284
0e8e02dd 2285 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2286 * doesn't.
2287 * TODO: We should stop TX here, so that it doesn't interfere.
2288 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2289 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2290 ah->ah_cal_next_nf = jiffies +
2291 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2292 ath5k_hw_update_noise_floor(ah);
afe86286 2293 }
6e220662 2294
e65e1d77 2295 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2296}
2297
2298
2111ac0d
BR		 2299static void
2300ath5k_tasklet_ani(unsigned long data)
2301{
2302 struct ath5k_softc *sc = (void *)data;
2303 struct ath5k_hw *ah = sc->ah;
2304
2305 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2306 ath5k_ani_calibration(ah);
2307 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2308}
2309
2310
4edd761f
BR		 2311static void
2312ath5k_tx_complete_poll_work(struct work_struct *work)
2313{
2314 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2315 tx_complete_work.work);
2316 struct ath5k_txq *txq;
2317 int i;
2318 bool needreset = false;
2319
599b13ad
BC		 2320 mutex_lock(&sc->lock);
2321
4edd761f
BR		 2322 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2323 if (sc->txqs[i].setup) {
2324 txq = &sc->txqs[i];
2325 spin_lock_bh(&txq->lock);
23413296 2326 if (txq->txq_len > 1) {
4edd761f
BR		 2327 if (txq->txq_poll_mark) {
2328 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2329 "TX queue stuck %d\n",
2330 txq->qnum);
2331 needreset = true;
923e5b3d 2332 txq->txq_stuck++;
4edd761f
BR		 2333 spin_unlock_bh(&txq->lock);
2334 break;
2335 } else {
2336 txq->txq_poll_mark = true;
2337 }
2338 }
2339 spin_unlock_bh(&txq->lock);
2340 }
2341 }
2342
2343 if (needreset) {
2344 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2345 "TX queues stuck, resetting\n");
8aec7af9 2346 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2347 }
2348
599b13ad
BC		 2349 mutex_unlock(&sc->lock);
2350
4edd761f
BR		 2351 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2352 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2353}
2354
2355
8a63facc
BC		 2356/*************************\
2357* Initialization routines *
2358\*************************/
fa1c114f 2359
25380d80 2360int __devinit
132b1c3e
FF		 2361ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2362{
2363 struct ieee80211_hw *hw = sc->hw;
2364 struct ath_common *common;
2365 int ret;
2366 int csz;
2367
2368 /* Initialize driver private data */
2369 SET_IEEE80211_DEV(hw, sc->dev);
2370 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2371 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2372 IEEE80211_HW_SIGNAL_DBM |
2373 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2374
2375 hw->wiphy->interface_modes =
2376 BIT(NL80211_IFTYPE_AP) |
2377 BIT(NL80211_IFTYPE_STATION) |
2378 BIT(NL80211_IFTYPE_ADHOC) |
2379 BIT(NL80211_IFTYPE_MESH_POINT);
2380
3de135db
BR		 2381 /* both antennas can be configured as RX or TX */
2382 hw->wiphy->available_antennas_tx = 0x3;
2383 hw->wiphy->available_antennas_rx = 0x3;
2384
132b1c3e
FF		 2385 hw->extra_tx_headroom = 2;
2386 hw->channel_change_time = 5000;
2387
2388 /*
2389 * Mark the device as detached to avoid processing
2390 * interrupts until setup is complete.
2391 */
2392 __set_bit(ATH_STAT_INVALID, sc->status);
2393
2394 sc->opmode = NL80211_IFTYPE_STATION;
2395 sc->bintval = 1000;
2396 mutex_init(&sc->lock);
2397 spin_lock_init(&sc->rxbuflock);
2398 spin_lock_init(&sc->txbuflock);
2399 spin_lock_init(&sc->block);
d381f221 2400 spin_lock_init(&sc->irqlock);
132b1c3e
FF		 2401
2402 /* Setup interrupt handler */
2403 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2404 if (ret) {
2405 ATH5K_ERR(sc, "request_irq failed\n");
2406 goto err;
2407 }
2408
2409 /* If we passed the test, malloc an ath5k_hw struct */
2410 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2411 if (!sc->ah) {
2412 ret = -ENOMEM;
2413 ATH5K_ERR(sc, "out of memory\n");
2414 goto err_irq;
2415 }
2416
2417 sc->ah->ah_sc = sc;
2418 sc->ah->ah_iobase = sc->iobase;
2419 common = ath5k_hw_common(sc->ah);
2420 common->ops = &ath5k_common_ops;
2421 common->bus_ops = bus_ops;
2422 common->ah = sc->ah;
2423 common->hw = hw;
2424 common->priv = sc;
2425
2426 /*
2427 * Cache line size is used to size and align various
2428 * structures used to communicate with the hardware.
2429 */
2430 ath5k_read_cachesize(common, &csz);
2431 common->cachelsz = csz << 2; /* convert to bytes */
2432
2433 spin_lock_init(&common->cc_lock);
2434
2435 /* Initialize device */
2436 ret = ath5k_hw_init(sc);
2437 if (ret)
2438 goto err_free_ah;
2439
2440 /* set up multi-rate retry capabilities */
2441 if (sc->ah->ah_version == AR5K_AR5212) {
2442 hw->max_rates = 4;
76a9f6fd
BR		 2443 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2444 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2445 }
2446
2447 hw->vif_data_size = sizeof(struct ath5k_vif);
2448
2449 /* Finish private driver data initialization */
2450 ret = ath5k_init(hw);
2451 if (ret)
2452 goto err_ah;
2453
2454 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2455 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2456 sc->ah->ah_mac_srev,
2457 sc->ah->ah_phy_revision);
2458
2459 if (!sc->ah->ah_single_chip) {
2460 /* Single chip radio (!RF5111) */
2461 if (sc->ah->ah_radio_5ghz_revision &&
2462 !sc->ah->ah_radio_2ghz_revision) {
2463 /* No 5GHz support -> report 2GHz radio */
2464 if (!test_bit(AR5K_MODE_11A,
2465 sc->ah->ah_capabilities.cap_mode)) {
2466 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2467 ath5k_chip_name(AR5K_VERSION_RAD,
2468 sc->ah->ah_radio_5ghz_revision),
2469 sc->ah->ah_radio_5ghz_revision);
2470 /* No 2GHz support (5110 and some
2471 * 5Ghz only cards) -> report 5Ghz radio */
2472 } else if (!test_bit(AR5K_MODE_11B,
2473 sc->ah->ah_capabilities.cap_mode)) {
2474 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2475 ath5k_chip_name(AR5K_VERSION_RAD,
2476 sc->ah->ah_radio_5ghz_revision),
2477 sc->ah->ah_radio_5ghz_revision);
2478 /* Multiband radio */
2479 } else {
2480 ATH5K_INFO(sc, "RF%s multiband radio found"
2481 " (0x%x)\n",
2482 ath5k_chip_name(AR5K_VERSION_RAD,
2483 sc->ah->ah_radio_5ghz_revision),
2484 sc->ah->ah_radio_5ghz_revision);
2485 }
2486 }
2487 /* Multi chip radio (RF5111 - RF2111) ->
2488 * report both 2GHz/5GHz radios */
2489 else if (sc->ah->ah_radio_5ghz_revision &&
2490 sc->ah->ah_radio_2ghz_revision){
2491 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2492 ath5k_chip_name(AR5K_VERSION_RAD,
2493 sc->ah->ah_radio_5ghz_revision),
2494 sc->ah->ah_radio_5ghz_revision);
2495 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2496 ath5k_chip_name(AR5K_VERSION_RAD,
2497 sc->ah->ah_radio_2ghz_revision),
2498 sc->ah->ah_radio_2ghz_revision);
2499 }
2500 }
2501
2502 ath5k_debug_init_device(sc);
2503
2504 /* ready to process interrupts */
2505 __clear_bit(ATH_STAT_INVALID, sc->status);
2506
2507 return 0;
2508err_ah:
2509 ath5k_hw_deinit(sc->ah);
2510err_free_ah:
2511 kfree(sc->ah);
2512err_irq:
2513 free_irq(sc->irq, sc);
2514err:
2515 return ret;
2516}
2517
fa1c114f 2518static int
8a63facc 2519ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2520{
8a63facc 2521 struct ath5k_hw *ah = sc->ah;
cec8db23 2522
8a63facc
BC		 2523 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2524 test_bit(ATH_STAT_INVALID, sc->status));
2525
2526 /*
2527 * Shutdown the hardware and driver:
2528 * stop output from above
2529 * disable interrupts
2530 * turn off timers
2531 * turn off the radio
2532 * clear transmit machinery
2533 * clear receive machinery
2534 * drain and release tx queues
2535 * reclaim beacon resources
2536 * power down hardware
2537 *
2538 * Note that some of this work is not possible if the
2539 * hardware is gone (invalid).
2540 */
2541 ieee80211_stop_queues(sc->hw);
2542
2543 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2544 ath5k_led_off(sc);
2545 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2546 synchronize_irq(sc->irq);
8a63facc 2547 ath5k_rx_stop(sc);
80dac9ee
NK		 2548 ath5k_hw_dma_stop(ah);
2549 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2550 ath5k_hw_phy_disable(ah);
2551 }
2552
2553 return 0;
cec8db23
BC		 2554}
2555
cd2c5486 2556int
132b1c3e 2557ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2558{
8a63facc
BC		 2559 struct ath5k_hw *ah = sc->ah;
2560 struct ath_common *common = ath5k_hw_common(ah);
2561 int ret, i;
fa1c114f 2562
8a63facc
BC		 2563 mutex_lock(&sc->lock);
2564
2565 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2566
fa1c114f 2567 /*
8a63facc
BC		 2568 * Stop anything previously setup. This is safe
2569 * no matter this is the first time through or not.
fa1c114f 2570 */
8a63facc 2571 ath5k_stop_locked(sc);
fa1c114f 2572
8a63facc
BC		 2573 /*
2574 * The basic interface to setting the hardware in a good
2575 * state is ``reset''. On return the hardware is known to
2576 * be powered up and with interrupts disabled. This must
2577 * be followed by initialization of the appropriate bits
2578 * and then setup of the interrupt mask.
2579 */
2580 sc->curchan = sc->hw->conf.channel;
8a63facc
BC		 2581 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2582 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2583 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2584
8aec7af9 2585 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2586 if (ret)
2587 goto done;
fa1c114f 2588
8a63facc
BC		 2589 ath5k_rfkill_hw_start(ah);
2590
2591 /*
2592 * Reset the key cache since some parts do not reset the
2593 * contents on initial power up or resume from suspend.
2594 */
2595 for (i = 0; i < common->keymax; i++)
2596 ath_hw_keyreset(common, (u16) i);
2597
61cde037
NK		 2598 /* Use higher rates for acks instead of base
2599 * rate */
2600 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2601
2602 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2603 sc->bslot[i] = NULL;
2604
8a63facc
BC		 2605 ret = 0;
2606done:
2607 mmiowb();
2608 mutex_unlock(&sc->lock);
4edd761f
BR		 2609
2610 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2611 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2612
8a63facc
BC		 2613 return ret;
2614}
2615
f5cbc8ba 2616static void ath5k_stop_tasklets(struct ath5k_softc *sc)
8a63facc 2617{
c266c71a
FF		 2618 sc->rx_pending = false;
2619 sc->tx_pending = false;
8a63facc
BC		 2620 tasklet_kill(&sc->rxtq);
2621 tasklet_kill(&sc->txtq);
2622 tasklet_kill(&sc->calib);
2623 tasklet_kill(&sc->beacontq);
2624 tasklet_kill(&sc->ani_tasklet);
2625}
2626
2627/*
2628 * Stop the device, grabbing the top-level lock to protect
2629 * against concurrent entry through ath5k_init (which can happen
2630 * if another thread does a system call and the thread doing the
2631 * stop is preempted).
2632 */
cd2c5486 2633int
8a63facc
BC		 2634ath5k_stop_hw(struct ath5k_softc *sc)
2635{
2636 int ret;
2637
2638 mutex_lock(&sc->lock);
2639 ret = ath5k_stop_locked(sc);
2640 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2641 /*
2642 * Don't set the card in full sleep mode!
2643 *
2644 * a) When the device is in this state it must be carefully
2645 * woken up or references to registers in the PCI clock
2646 * domain may freeze the bus (and system). This varies
2647 * by chip and is mostly an issue with newer parts
2648 * (madwifi sources mentioned srev >= 0x78) that go to
2649 * sleep more quickly.
2650 *
2651 * b) On older chips full sleep results a weird behaviour
2652 * during wakeup. I tested various cards with srev < 0x78
2653 * and they don't wake up after module reload, a second
2654 * module reload is needed to bring the card up again.
2655 *
2656 * Until we figure out what's going on don't enable
2657 * full chip reset on any chip (this is what Legacy HAL
2658 * and Sam's HAL do anyway). Instead Perform a full reset
2659 * on the device (same as initial state after attach) and
2660 * leave it idle (keep MAC/BB on warm reset) */
2661 ret = ath5k_hw_on_hold(sc->ah);
2662
2663 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2664 "putting device to sleep\n");
fa1c114f
JS		 2665 }
2666
8a63facc
BC		 2667 mmiowb();
2668 mutex_unlock(&sc->lock);
2669
f5cbc8ba 2670 ath5k_stop_tasklets(sc);
8a63facc 2671
4edd761f
BR		 2672 cancel_delayed_work_sync(&sc->tx_complete_work);
2673
8a63facc
BC		 2674 ath5k_rfkill_hw_stop(sc->ah);
2675
2676 return ret;
fa1c114f
JS		 2677}
2678
209d889b
BC		 2679/*
2680 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2681 * and change to the given channel.
5faaff74
BC		 2682 *
2683 * This should be called with sc->lock.
209d889b 2684 */
fa1c114f 2685static int
8aec7af9
NK		 2686ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2687 bool skip_pcu)
fa1c114f 2688{
fa1c114f 2689 struct ath5k_hw *ah = sc->ah;
f15a4bb2 2690 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2691 int ret, ani_mode;
a99168ee 2692 bool fast;
fa1c114f
JS		 2693
2694 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2695
450464de 2696 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2697 synchronize_irq(sc->irq);
f5cbc8ba 2698 ath5k_stop_tasklets(sc);
450464de 2699
25985edc 2700 /* Save ani mode and disable ANI during
344b54b9
NK		 2701 * reset. If we don't we might get false
2702 * PHY error interrupts. */
2703 ani_mode = ah->ah_sc->ani_state.ani_mode;
2704 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2705
19252ecb
NK		 2706 /* We are going to empty hw queues
2707 * so we should also free any remaining
2708 * tx buffers */
2709 ath5k_drain_tx_buffs(sc);
930a7622 2710 if (chan)
209d889b 2711 sc->curchan = chan;
a99168ee
NK		 2712
2713 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2714
2715 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast,
8aec7af9 2716 skip_pcu);
d7dc1003 2717 if (ret) {
fa1c114f
JS		 2718 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2719 goto err;
2720 }
d7dc1003 2721
fa1c114f 2722 ret = ath5k_rx_start(sc);
d7dc1003 2723 if (ret) {
fa1c114f
JS		 2724 ATH5K_ERR(sc, "can't start recv logic\n");
2725 goto err;
2726 }
d7dc1003 2727
344b54b9 2728 ath5k_ani_init(ah, ani_mode);
2111ac0d 2729
ac559526
BR		 2730 ah->ah_cal_next_full = jiffies;
2731 ah->ah_cal_next_ani = jiffies;
afe86286 2732 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2733 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2734
f15a4bb2
BR		 2735 /* clear survey data and cycle counters */
2736 memset(&sc->survey, 0, sizeof(sc->survey));
bb007554 2737 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2738 ath_hw_cycle_counters_update(common);
2739 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2740 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2741 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2742
fa1c114f 2743 /*
d7dc1003
JS		 2744 * Change channels and update the h/w rate map if we're switching;
2745 * e.g. 11a to 11b/g.
2746 *
2747 * We may be doing a reset in response to an ioctl that changes the
2748 * channel so update any state that might change as a result.
fa1c114f
JS		 2749 *
2750 * XXX needed?
2751 */
2752/* ath5k_chan_change(sc, c); */
fa1c114f 2753
d7dc1003
JS		 2754 ath5k_beacon_config(sc);
2755 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2756
397f385b
BR		 2757 ieee80211_wake_queues(sc->hw);
2758
fa1c114f
JS		 2759 return 0;
2760err:
2761 return ret;
2762}
2763
5faaff74
BC		 2764static void ath5k_reset_work(struct work_struct *work)
2765{
2766 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2767 reset_work);
2768
2769 mutex_lock(&sc->lock);
8aec7af9 2770 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2771 mutex_unlock(&sc->lock);
2772}
2773
25380d80 2774static int __devinit
132b1c3e 2775ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2776{
132b1c3e 2777
fa1c114f 2778 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2779 struct ath5k_hw *ah = sc->ah;
2780 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2781 struct ath5k_txq *txq;
8a63facc 2782 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2783 int ret;
2784
fa1c114f 2785
8a63facc
BC		 2786 /*
2787 * Check if the MAC has multi-rate retry support.
2788 * We do this by trying to setup a fake extended
2789 * descriptor. MACs that don't have support will
2790 * return false w/o doing anything. MACs that do
2791 * support it will return true w/o doing anything.
2792 */
2793 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2794
8a63facc
BC		 2795 if (ret < 0)
2796 goto err;
2797 if (ret > 0)
2798 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2799
8a63facc
BC		 2800 /*
2801 * Collect the channel list. The 802.11 layer
2802 * is resposible for filtering this list based
2803 * on settings like the phy mode and regulatory
2804 * domain restrictions.
2805 */
2806 ret = ath5k_setup_bands(hw);
2807 if (ret) {
2808 ATH5K_ERR(sc, "can't get channels\n");
2809 goto err;
2810 }
67d2e2df 2811
8a63facc
BC		 2812 /*
2813 * Allocate tx+rx descriptors and populate the lists.
2814 */
aeae4ac9 2815 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2816 if (ret) {
2817 ATH5K_ERR(sc, "can't allocate descriptors\n");
2818 goto err;
2819 }
fa1c114f 2820
8a63facc
BC		 2821 /*
2822 * Allocate hardware transmit queues: one queue for
2823 * beacon frames and one data queue for each QoS
2824 * priority. Note that hw functions handle resetting
2825 * these queues at the needed time.
2826 */
2827 ret = ath5k_beaconq_setup(ah);
2828 if (ret < 0) {
2829 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2830 goto err_desc;
2831 }
2832 sc->bhalq = ret;
2833 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2834 if (IS_ERR(sc->cabq)) {
2835 ATH5K_ERR(sc, "can't setup cab queue\n");
2836 ret = PTR_ERR(sc->cabq);
2837 goto err_bhal;
2838 }
fa1c114f 2839
22d8d9f8
BR		 2840 /* 5211 and 5212 usually support 10 queues but we better rely on the
2841 * capability information */
2842 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2843 /* This order matches mac80211's queue priority, so we can
2844 * directly use the mac80211 queue number without any mapping */
2845 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2846 if (IS_ERR(txq)) {
2847 ATH5K_ERR(sc, "can't setup xmit queue\n");
2848 ret = PTR_ERR(txq);
2849 goto err_queues;
2850 }
2851 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2852 if (IS_ERR(txq)) {
2853 ATH5K_ERR(sc, "can't setup xmit queue\n");
2854 ret = PTR_ERR(txq);
2855 goto err_queues;
2856 }
2857 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2858 if (IS_ERR(txq)) {
2859 ATH5K_ERR(sc, "can't setup xmit queue\n");
2860 ret = PTR_ERR(txq);
2861 goto err_queues;
2862 }
2863 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2864 if (IS_ERR(txq)) {
2865 ATH5K_ERR(sc, "can't setup xmit queue\n");
2866 ret = PTR_ERR(txq);
2867 goto err_queues;
2868 }
2869 hw->queues = 4;
2870 } else {
2871 /* older hardware (5210) can only support one data queue */
2872 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2873 if (IS_ERR(txq)) {
2874 ATH5K_ERR(sc, "can't setup xmit queue\n");
2875 ret = PTR_ERR(txq);
2876 goto err_queues;
2877 }
2878 hw->queues = 1;
2879 }
fa1c114f 2880
8a63facc
BC		 2881 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2882 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2883 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2884 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2885 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2886
8a63facc 2887 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2888 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2889
fa9bfd61 2890 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
8a63facc 2891 if (ret) {
aeae4ac9 2892 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2893 goto err_queues;
e30eb4ab 2894 }
2bed03eb 2895
8a63facc 2896 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2897 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2898 /* All MAC address bits matter for ACKs */
62c58fb4 2899 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2900
2901 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2902 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2903 if (ret) {
2904 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2905 goto err_queues;
2906 }
2907
2908 ret = ieee80211_register_hw(hw);
2909 if (ret) {
2910 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2911 goto err_queues;
2912 }
2913
2914 if (!ath_is_world_regd(regulatory))
2915 regulatory_hint(hw->wiphy, regulatory->alpha2);
2916
2917 ath5k_init_leds(sc);
2918
2919 ath5k_sysfs_register(sc);
2920
2921 return 0;
2922err_queues:
2923 ath5k_txq_release(sc);
2924err_bhal:
2925 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2926err_desc:
aeae4ac9 2927 ath5k_desc_free(sc);
8a63facc
BC		 2928err:
2929 return ret;
2930}
2931
132b1c3e
FF		 2932void
2933ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2934{
132b1c3e 2935 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2936
2937 /*
2938 * NB: the order of these is important:
2939 * o call the 802.11 layer before detaching ath5k_hw to
2940 * ensure callbacks into the driver to delete global
2941 * key cache entries can be handled
2942 * o reclaim the tx queue data structures after calling
2943 * the 802.11 layer as we'll get called back to reclaim
2944 * node state and potentially want to use them
2945 * o to cleanup the tx queues the hal is called, so detach
2946 * it last
2947 * XXX: ??? detach ath5k_hw ???
2948 * Other than that, it's straightforward...
2949 */
2950 ieee80211_unregister_hw(hw);
aeae4ac9 2951 ath5k_desc_free(sc);
8a63facc
BC		 2952 ath5k_txq_release(sc);
2953 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2954 ath5k_unregister_leds(sc);
2955
2956 ath5k_sysfs_unregister(sc);
2957 /*
2958 * NB: can't reclaim these until after ieee80211_ifdetach
2959 * returns because we'll get called back to reclaim node
2960 * state and potentially want to use them.
2961 */
132b1c3e 2962 ath5k_hw_deinit(sc->ah);
0e8d1602 2963 kfree(sc->ah);
132b1c3e 2964 free_irq(sc->irq, sc);
8a63facc
BC		 2965}
2966
cd2c5486 2967bool
f5cbc8ba 2968ath5k_any_vif_assoc(struct ath5k_softc *sc)
b1ae1edf 2969{
e4b0b32a 2970 struct ath5k_vif_iter_data iter_data;
b1ae1edf
BG		 2971 iter_data.hw_macaddr = NULL;
2972 iter_data.any_assoc = false;
2973 iter_data.need_set_hw_addr = false;
2974 iter_data.found_active = true;
2975
e4b0b32a 2976 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
b1ae1edf
BG		 2977 &iter_data);
2978 return iter_data.any_assoc;
2979}
2980
cd2c5486 2981void
f5cbc8ba 2982ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
8a63facc
BC		 2983{
2984 struct ath5k_softc *sc = hw->priv;
2985 struct ath5k_hw *ah = sc->ah;
2986 u32 rfilt;
2987 rfilt = ath5k_hw_get_rx_filter(ah);
2988 if (enable)
2989 rfilt |= AR5K_RX_FILTER_BEACON;
2990 else
2991 rfilt &= ~AR5K_RX_FILTER_BEACON;
2992 ath5k_hw_set_rx_filter(ah, rfilt);
2993 sc->filter_flags = rfilt;
2994}
Linux kernel - Deliverables
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