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ath9k: move ath_common to ath_hw
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
6e220662 62static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e 63static int modparam_nohwcrypt;
46802a4f 64module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 66
42639fcd 67static int modparam_all_channels;
46802a4f 68module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 69MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
fa1c114f
JS		 71
72/******************\
73* Internal defines *
74\******************/
75
76/* Module info */
77MODULE_AUTHOR("Jiri Slaby");
78MODULE_AUTHOR("Nick Kossifidis");
79MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 82MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 83
84
85/* Known PCI ids */
2c91108c 86static const struct pci_device_id ath5k_pci_id_table[] = {
97a81f5c
PR		 87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 105 { 0 }
106};
107MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109/* Known SREVs */
2c91108c 110static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147};
148
2c91108c 149static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189};
190
fa1c114f
JS		 191/*
192 * Prototypes - PCI stack related functions
193 */
194static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197#ifdef CONFIG_PM
198static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200static int ath5k_pci_resume(struct pci_dev *pdev);
201#else
202#define ath5k_pci_suspend NULL
203#define ath5k_pci_resume NULL
204#endif /* CONFIG_PM */
205
04a9e451 206static struct pci_driver ath5k_pci_driver = {
9764f3f9 207 .name = KBUILD_MODNAME,
fa1c114f
JS		 208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213};
214
215
216
217/*
218 * Prototypes - MAC 802.11 stack related functions
219 */
e039fa4a 220static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 221static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
209d889b 223static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 224static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 225static int ath5k_start(struct ieee80211_hw *hw);
226static void ath5k_stop(struct ieee80211_hw *hw);
227static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
e8975581 231static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee
JB		 232static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
fa1c114f
JS		 234static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
3ac64bee 237 u64 multicast);
fa1c114f
JS		 238static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
dc822b5d 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 241 struct ieee80211_key_conf *key);
242static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
245 struct ieee80211_tx_queue_stats *stats);
246static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 247static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 248static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 249static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
02969b38
MX		 251static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
254 u32 changes);
f0f3d388
BC		 255static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
fa1c114f 257
2c91108c 258static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 259 .tx = ath5k_tx,
260 .start = ath5k_start,
261 .stop = ath5k_stop,
262 .add_interface = ath5k_add_interface,
263 .remove_interface = ath5k_remove_interface,
264 .config = ath5k_config,
3ac64bee 265 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 266 .configure_filter = ath5k_configure_filter,
267 .set_key = ath5k_set_key,
268 .get_stats = ath5k_get_stats,
269 .conf_tx = NULL,
270 .get_tx_stats = ath5k_get_tx_stats,
271 .get_tsf = ath5k_get_tsf,
3b5d665b 272 .set_tsf = ath5k_set_tsf,
fa1c114f 273 .reset_tsf = ath5k_reset_tsf,
02969b38 274 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 275 .sw_scan_start = ath5k_sw_scan_start,
276 .sw_scan_complete = ath5k_sw_scan_complete,
fa1c114f
JS		 277};
278
279/*
280 * Prototypes - Internal functions
281 */
282/* Attach detach */
283static int ath5k_attach(struct pci_dev *pdev,
284 struct ieee80211_hw *hw);
285static void ath5k_detach(struct pci_dev *pdev,
286 struct ieee80211_hw *hw);
287/* Channel/mode setup */
288static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 289static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
290 struct ieee80211_channel *channels,
291 unsigned int mode,
292 unsigned int max);
63266a65 293static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 294static int ath5k_chan_set(struct ath5k_softc *sc,
295 struct ieee80211_channel *chan);
296static void ath5k_setcurmode(struct ath5k_softc *sc,
297 unsigned int mode);
298static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 299
fa1c114f
JS		 300/* Descriptor setup */
301static int ath5k_desc_alloc(struct ath5k_softc *sc,
302 struct pci_dev *pdev);
303static void ath5k_desc_free(struct ath5k_softc *sc,
304 struct pci_dev *pdev);
305/* Buffers setup */
306static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
307 struct ath5k_buf *bf);
308static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23
BC		 309 struct ath5k_buf *bf,
310 struct ath5k_txq *txq);
fa1c114f
JS		 311static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
312 struct ath5k_buf *bf)
313{
314 BUG_ON(!bf);
315 if (!bf->skb)
316 return;
317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
318 PCI_DMA_TODEVICE);
00482973 319 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 320 bf->skb = NULL;
321}
322
a6c8d375
FF		 323static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
324 struct ath5k_buf *bf)
325{
326 BUG_ON(!bf);
327 if (!bf->skb)
328 return;
329 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
330 PCI_DMA_FROMDEVICE);
331 dev_kfree_skb_any(bf->skb);
332 bf->skb = NULL;
333}
334
335
fa1c114f
JS		 336/* Queues setup */
337static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
338 int qtype, int subtype);
339static int ath5k_beaconq_setup(struct ath5k_hw *ah);
340static int ath5k_beaconq_config(struct ath5k_softc *sc);
341static void ath5k_txq_drainq(struct ath5k_softc *sc,
342 struct ath5k_txq *txq);
343static void ath5k_txq_cleanup(struct ath5k_softc *sc);
344static void ath5k_txq_release(struct ath5k_softc *sc);
345/* Rx handling */
346static int ath5k_rx_start(struct ath5k_softc *sc);
347static void ath5k_rx_stop(struct ath5k_softc *sc);
348static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
349 struct ath5k_desc *ds,
b47f407b
BR		 350 struct sk_buff *skb,
351 struct ath5k_rx_status *rs);
fa1c114f
JS		 352static void ath5k_tasklet_rx(unsigned long data);
353/* Tx handling */
354static void ath5k_tx_processq(struct ath5k_softc *sc,
355 struct ath5k_txq *txq);
356static void ath5k_tasklet_tx(unsigned long data);
357/* Beacon handling */
358static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 359 struct ath5k_buf *bf);
fa1c114f
JS		 360static void ath5k_beacon_send(struct ath5k_softc *sc);
361static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 362static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 363static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 364
365static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
366{
367 u64 tsf = ath5k_hw_get_tsf64(ah);
368
369 if ((tsf & 0x7fff) < rstamp)
370 tsf -= 0x8000;
371
372 return (tsf & ~0x7fff) | rstamp;
373}
374
375/* Interrupt handling */
bb2becac 376static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 377static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 378static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 379static irqreturn_t ath5k_intr(int irq, void *dev_id);
380static void ath5k_tasklet_reset(unsigned long data);
381
6e220662 382static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 383
384/*
385 * Module init/exit functions
386 */
387static int __init
388init_ath5k_pci(void)
389{
390 int ret;
391
392 ath5k_debug_init();
393
04a9e451 394 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 395 if (ret) {
396 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
397 return ret;
398 }
399
400 return 0;
401}
402
403static void __exit
404exit_ath5k_pci(void)
405{
04a9e451 406 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 407
408 ath5k_debug_finish();
409}
410
411module_init(init_ath5k_pci);
412module_exit(exit_ath5k_pci);
413
414
415/********************\
416* PCI Initialization *
417\********************/
418
419static const char *
420ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
421{
422 const char *name = "xxxxx";
423 unsigned int i;
424
425 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
426 if (srev_names[i].sr_type != type)
427 continue;
75d0edb8
NK		 428
429 if ((val & 0xf0) == srev_names[i].sr_val)
430 name = srev_names[i].sr_name;
431
432 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 433 name = srev_names[i].sr_name;
434 break;
435 }
436 }
437
438 return name;
439}
440
441static int __devinit
442ath5k_pci_probe(struct pci_dev *pdev,
443 const struct pci_device_id *id)
444{
445 void __iomem *mem;
446 struct ath5k_softc *sc;
447 struct ieee80211_hw *hw;
448 int ret;
449 u8 csz;
450
451 ret = pci_enable_device(pdev);
452 if (ret) {
453 dev_err(&pdev->dev, "can't enable device\n");
454 goto err;
455 }
456
457 /* XXX 32-bit addressing only */
284901a9 458 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 459 if (ret) {
460 dev_err(&pdev->dev, "32-bit DMA not available\n");
461 goto err_dis;
462 }
463
464 /*
465 * Cache line size is used to size and align various
466 * structures used to communicate with the hardware.
467 */
468 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
469 if (csz == 0) {
470 /*
471 * Linux 2.4.18 (at least) writes the cache line size
472 * register as a 16-bit wide register which is wrong.
473 * We must have this setup properly for rx buffer
474 * DMA to work so force a reasonable value here if it
475 * comes up zero.
476 */
13311b00 477 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 478 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
479 }
480 /*
481 * The default setting of latency timer yields poor results,
482 * set it to the value used by other systems. It may be worth
483 * tweaking this setting more.
484 */
485 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
486
487 /* Enable bus mastering */
488 pci_set_master(pdev);
489
490 /*
491 * Disable the RETRY_TIMEOUT register (0x41) to keep
492 * PCI Tx retries from interfering with C3 CPU state.
493 */
494 pci_write_config_byte(pdev, 0x41, 0);
495
496 ret = pci_request_region(pdev, 0, "ath5k");
497 if (ret) {
498 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
499 goto err_dis;
500 }
501
502 mem = pci_iomap(pdev, 0, 0);
503 if (!mem) {
504 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
505 ret = -EIO;
506 goto err_reg;
507 }
508
509 /*
510 * Allocate hw (mac80211 main struct)
511 * and hw->priv (driver private data)
512 */
513 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
514 if (hw == NULL) {
515 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
516 ret = -ENOMEM;
517 goto err_map;
518 }
519
520 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
521
522 /* Initialize driver private data */
523 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 524 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 525 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 526 IEEE80211_HW_SIGNAL_DBM |
527 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 528
529 hw->wiphy->interface_modes =
6f5f39c9 530 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 531 BIT(NL80211_IFTYPE_STATION) |
532 BIT(NL80211_IFTYPE_ADHOC) |
533 BIT(NL80211_IFTYPE_MESH_POINT);
534
fa1c114f
JS		 535 hw->extra_tx_headroom = 2;
536 hw->channel_change_time = 5000;
fa1c114f
JS		 537 sc = hw->priv;
538 sc->hw = hw;
539 sc->pdev = pdev;
540
541 ath5k_debug_init_device(sc);
542
543 /*
544 * Mark the device as detached to avoid processing
545 * interrupts until setup is complete.
546 */
547 __set_bit(ATH_STAT_INVALID, sc->status);
548
549 sc->iobase = mem; /* So we can unmap it on detach */
13311b00 550 sc->common.cachelsz = csz << 2; /* convert to bytes */
05c914fe 551 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 552 sc->bintval = 1000;
fa1c114f
JS		 553 mutex_init(&sc->lock);
554 spin_lock_init(&sc->rxbuflock);
555 spin_lock_init(&sc->txbuflock);
00482973 556 spin_lock_init(&sc->block);
fa1c114f
JS		 557
558 /* Set private data */
559 pci_set_drvdata(pdev, hw);
560
fa1c114f
JS		 561 /* Setup interrupt handler */
562 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
563 if (ret) {
564 ATH5K_ERR(sc, "request_irq failed\n");
565 goto err_free;
566 }
567
568 /* Initialize device */
97a81f5c 569 sc->ah = ath5k_hw_attach(sc);
fa1c114f
JS		 570 if (IS_ERR(sc->ah)) {
571 ret = PTR_ERR(sc->ah);
572 goto err_irq;
573 }
574
2f7fe870
FF		 575 /* set up multi-rate retry capabilities */
576 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 577 hw->max_rates = 4;
578 hw->max_rate_tries = 11;
2f7fe870
FF		 579 }
580
fa1c114f
JS		 581 /* Finish private driver data initialization */
582 ret = ath5k_attach(pdev, hw);
583 if (ret)
584 goto err_ah;
585
586 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 587 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 588 sc->ah->ah_mac_srev,
589 sc->ah->ah_phy_revision);
590
400ec45a 591 if (!sc->ah->ah_single_chip) {
fa1c114f 592 /* Single chip radio (!RF5111) */
400ec45a
LR		 593 if (sc->ah->ah_radio_5ghz_revision &&
594 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 595 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 596 if (!test_bit(AR5K_MODE_11A,
597 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 598 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 599 ath5k_chip_name(AR5K_VERSION_RAD,
600 sc->ah->ah_radio_5ghz_revision),
601 sc->ah->ah_radio_5ghz_revision);
602 /* No 2GHz support (5110 and some
603 * 5Ghz only cards) -> report 5Ghz radio */
604 } else if (!test_bit(AR5K_MODE_11B,
605 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 606 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 607 ath5k_chip_name(AR5K_VERSION_RAD,
608 sc->ah->ah_radio_5ghz_revision),
609 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 610 /* Multiband radio */
611 } else {
612 ATH5K_INFO(sc, "RF%s multiband radio found"
613 " (0x%x)\n",
400ec45a
LR		 614 ath5k_chip_name(AR5K_VERSION_RAD,
615 sc->ah->ah_radio_5ghz_revision),
616 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 617 }
618 }
400ec45a
LR		 619 /* Multi chip radio (RF5111 - RF2111) ->
620 * report both 2GHz/5GHz radios */
621 else if (sc->ah->ah_radio_5ghz_revision &&
622 sc->ah->ah_radio_2ghz_revision){
fa1c114f 623 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 624 ath5k_chip_name(AR5K_VERSION_RAD,
625 sc->ah->ah_radio_5ghz_revision),
626 sc->ah->ah_radio_5ghz_revision);
fa1c114f 627 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 628 ath5k_chip_name(AR5K_VERSION_RAD,
629 sc->ah->ah_radio_2ghz_revision),
630 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 631 }
632 }
633
634
635 /* ready to process interrupts */
636 __clear_bit(ATH_STAT_INVALID, sc->status);
637
638 return 0;
639err_ah:
640 ath5k_hw_detach(sc->ah);
641err_irq:
642 free_irq(pdev->irq, sc);
643err_free:
fa1c114f
JS		 644 ieee80211_free_hw(hw);
645err_map:
646 pci_iounmap(pdev, mem);
647err_reg:
648 pci_release_region(pdev, 0);
649err_dis:
650 pci_disable_device(pdev);
651err:
652 return ret;
653}
654
655static void __devexit
656ath5k_pci_remove(struct pci_dev *pdev)
657{
658 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
659 struct ath5k_softc *sc = hw->priv;
660
661 ath5k_debug_finish_device(sc);
662 ath5k_detach(pdev, hw);
663 ath5k_hw_detach(sc->ah);
664 free_irq(pdev->irq, sc);
fa1c114f
JS		 665 pci_iounmap(pdev, sc->iobase);
666 pci_release_region(pdev, 0);
667 pci_disable_device(pdev);
668 ieee80211_free_hw(hw);
669}
670
671#ifdef CONFIG_PM
672static int
673ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
674{
675 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
676 struct ath5k_softc *sc = hw->priv;
677
3a078876 678 ath5k_led_off(sc);
fa1c114f 679
fa1c114f
JS		 680 pci_save_state(pdev);
681 pci_disable_device(pdev);
682 pci_set_power_state(pdev, PCI_D3hot);
683
684 return 0;
685}
686
687static int
688ath5k_pci_resume(struct pci_dev *pdev)
689{
690 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
691 struct ath5k_softc *sc = hw->priv;
bc1b32d6 692 int err;
fa1c114f 693
3e4242b9 694 pci_restore_state(pdev);
fa1c114f
JS		 695
696 err = pci_enable_device(pdev);
697 if (err)
698 return err;
699
8451d22d
JM		 700 /*
701 * Suspend/Resume resets the PCI configuration space, so we have to
702 * re-disable the RETRY_TIMEOUT register (0x41) to keep
703 * PCI Tx retries from interfering with C3 CPU state
704 */
705 pci_write_config_byte(pdev, 0x41, 0);
706
3a078876 707 ath5k_led_enable(sc);
fa1c114f
JS		 708 return 0;
709}
710#endif /* CONFIG_PM */
711
712
fa1c114f
JS		 713/***********************\
714* Driver Initialization *
715\***********************/
716
f769c36b
BC		 717static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
718{
719 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
720 struct ath5k_softc *sc = hw->priv;
608b88cb 721 struct ath_regulatory *regulatory = &sc->common.regulatory;
f769c36b 722
608b88cb 723 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 724}
725
fa1c114f
JS		 726static int
727ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
728{
729 struct ath5k_softc *sc = hw->priv;
730 struct ath5k_hw *ah = sc->ah;
608b88cb 731 struct ath_regulatory *regulatory = &sc->common.regulatory;
0e149cf5 732 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 733 int ret;
734
735 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
736
737 /*
738 * Check if the MAC has multi-rate retry support.
739 * We do this by trying to setup a fake extended
740 * descriptor. MAC's that don't have support will
741 * return false w/o doing anything. MAC's that do
742 * support it will return true w/o doing anything.
743 */
c6e387a2 744 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 745 if (ret < 0)
746 goto err;
747 if (ret > 0)
fa1c114f
JS		 748 __set_bit(ATH_STAT_MRRETRY, sc->status);
749
fa1c114f
JS		 750 /*
751 * Collect the channel list. The 802.11 layer
752 * is resposible for filtering this list based
753 * on settings like the phy mode and regulatory
754 * domain restrictions.
755 */
63266a65 756 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 757 if (ret) {
758 ATH5K_ERR(sc, "can't get channels\n");
759 goto err;
760 }
761
762 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 763 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
764 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 765 else
d8ee398d 766 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 767
768 /*
769 * Allocate tx+rx descriptors and populate the lists.
770 */
771 ret = ath5k_desc_alloc(sc, pdev);
772 if (ret) {
773 ATH5K_ERR(sc, "can't allocate descriptors\n");
774 goto err;
775 }
776
777 /*
778 * Allocate hardware transmit queues: one queue for
779 * beacon frames and one data queue for each QoS
780 * priority. Note that hw functions handle reseting
781 * these queues at the needed time.
782 */
783 ret = ath5k_beaconq_setup(ah);
784 if (ret < 0) {
785 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
786 goto err_desc;
787 }
788 sc->bhalq = ret;
cec8db23
BC		 789 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
790 if (IS_ERR(sc->cabq)) {
791 ATH5K_ERR(sc, "can't setup cab queue\n");
792 ret = PTR_ERR(sc->cabq);
793 goto err_bhal;
794 }
fa1c114f
JS		 795
796 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
797 if (IS_ERR(sc->txq)) {
798 ATH5K_ERR(sc, "can't setup xmit queue\n");
799 ret = PTR_ERR(sc->txq);
cec8db23 800 goto err_queues;
fa1c114f
JS		 801 }
802
803 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
804 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
805 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
6e220662 806 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 807 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 808
0e149cf5
BC		 809 ret = ath5k_eeprom_read_mac(ah, mac);
810 if (ret) {
811 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
812 sc->pdev->device);
813 goto err_queues;
814 }
815
fa1c114f
JS		 816 SET_IEEE80211_PERM_ADDR(hw, mac);
817 /* All MAC address bits matter for ACKs */
17753748 818 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 819 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
820
608b88cb
LR		 821 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
822 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 823 if (ret) {
824 ATH5K_ERR(sc, "can't initialize regulatory system\n");
825 goto err_queues;
826 }
827
fa1c114f
JS		 828 ret = ieee80211_register_hw(hw);
829 if (ret) {
830 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
831 goto err_queues;
832 }
833
608b88cb
LR		 834 if (!ath_is_world_regd(regulatory))
835 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 836
3a078876
BC		 837 ath5k_init_leds(sc);
838
fa1c114f
JS		 839 return 0;
840err_queues:
841 ath5k_txq_release(sc);
842err_bhal:
843 ath5k_hw_release_tx_queue(ah, sc->bhalq);
844err_desc:
845 ath5k_desc_free(sc, pdev);
846err:
847 return ret;
848}
849
850static void
851ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
852{
853 struct ath5k_softc *sc = hw->priv;
854
855 /*
856 * NB: the order of these is important:
857 * o call the 802.11 layer before detaching ath5k_hw to
858 * insure callbacks into the driver to delete global
859 * key cache entries can be handled
860 * o reclaim the tx queue data structures after calling
861 * the 802.11 layer as we'll get called back to reclaim
862 * node state and potentially want to use them
863 * o to cleanup the tx queues the hal is called, so detach
864 * it last
865 * XXX: ??? detach ath5k_hw ???
866 * Other than that, it's straightforward...
867 */
868 ieee80211_unregister_hw(hw);
869 ath5k_desc_free(sc, pdev);
870 ath5k_txq_release(sc);
871 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 872 ath5k_unregister_leds(sc);
fa1c114f
JS		 873
874 /*
875 * NB: can't reclaim these until after ieee80211_ifdetach
876 * returns because we'll get called back to reclaim node
877 * state and potentially want to use them.
878 */
879}
880
881
882
883
884/********************\
885* Channel/mode setup *
886\********************/
887
888/*
889 * Convert IEEE channel number to MHz frequency.
890 */
891static inline short
892ath5k_ieee2mhz(short chan)
893{
894 if (chan <= 14 || chan >= 27)
895 return ieee80211chan2mhz(chan);
896 else
897 return 2212 + chan * 20;
898}
899
42639fcd
BC		 900/*
901 * Returns true for the channel numbers used without all_channels modparam.
902 */
903static bool ath5k_is_standard_channel(short chan)
904{
905 return ((chan <= 14) ||
906 /* UNII 1,2 */
907 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
908 /* midband */
909 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
910 /* UNII-3 */
911 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
912}
913
fa1c114f
JS		 914static unsigned int
915ath5k_copy_channels(struct ath5k_hw *ah,
916 struct ieee80211_channel *channels,
917 unsigned int mode,
918 unsigned int max)
919{
d8ee398d 920 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 921
922 if (!test_bit(mode, ah->ah_modes))
923 return 0;
924
fa1c114f 925 switch (mode) {
d8ee398d
LR		 926 case AR5K_MODE_11A:
927 case AR5K_MODE_11A_TURBO:
fa1c114f 928 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 929 size = 220 ;
fa1c114f
JS		 930 chfreq = CHANNEL_5GHZ;
931 break;
d8ee398d
LR		 932 case AR5K_MODE_11B:
933 case AR5K_MODE_11G:
934 case AR5K_MODE_11G_TURBO:
935 size = 26;
fa1c114f
JS		 936 chfreq = CHANNEL_2GHZ;
937 break;
938 default:
939 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
940 return 0;
941 }
942
943 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 944 ch = i + 1 ;
945 freq = ath5k_ieee2mhz(ch);
fa1c114f 946
d8ee398d
LR		 947 /* Check if channel is supported by the chipset */
948 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 949 continue;
950
42639fcd
BC		 951 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
952 continue;
953
d8ee398d
LR		 954 /* Write channel info and increment counter */
955 channels[count].center_freq = freq;
a3f4b914
LR		 956 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
957 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 958 switch (mode) {
959 case AR5K_MODE_11A:
960 case AR5K_MODE_11G:
961 channels[count].hw_value = chfreq | CHANNEL_OFDM;
962 break;
963 case AR5K_MODE_11A_TURBO:
964 case AR5K_MODE_11G_TURBO:
965 channels[count].hw_value = chfreq |
966 CHANNEL_OFDM | CHANNEL_TURBO;
967 break;
968 case AR5K_MODE_11B:
d8ee398d
LR		 969 channels[count].hw_value = CHANNEL_B;
970 }
fa1c114f 971
fa1c114f
JS		 972 count++;
973 max--;
974 }
975
976 return count;
977}
978
63266a65
BR		 979static void
980ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
981{
982 u8 i;
983
984 for (i = 0; i < AR5K_MAX_RATES; i++)
985 sc->rate_idx[b->band][i] = -1;
986
987 for (i = 0; i < b->n_bitrates; i++) {
988 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
989 if (b->bitrates[i].hw_value_short)
990 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
991 }
992}
993
d8ee398d 994static int
63266a65 995ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 996{
997 struct ath5k_softc *sc = hw->priv;
d8ee398d 998 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 999 struct ieee80211_supported_band *sband;
1000 int max_c, count_c = 0;
1001 int i;
fa1c114f 1002
d8ee398d 1003 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1004 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1005
1006 /* 2GHz band */
63266a65
BR		 1007 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1008 sband->band = IEEE80211_BAND_2GHZ;
1009 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1010
63266a65
BR		 1011 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1012 /* G mode */
1013 memcpy(sband->bitrates, &ath5k_rates[0],
1014 sizeof(struct ieee80211_rate) * 12);
1015 sband->n_bitrates = 12;
fa1c114f 1016
d8ee398d 1017 sband->channels = sc->channels;
d8ee398d 1018 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1019 AR5K_MODE_11G, max_c);
fa1c114f 1020
63266a65 1021 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1022 count_c = sband->n_channels;
63266a65
BR		 1023 max_c -= count_c;
1024 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1025 /* B mode */
1026 memcpy(sband->bitrates, &ath5k_rates[0],
1027 sizeof(struct ieee80211_rate) * 4);
1028 sband->n_bitrates = 4;
1029
1030 /* 5211 only supports B rates and uses 4bit rate codes
1031 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1032 * fix them up here:
1033 */
1034 if (ah->ah_version == AR5K_AR5211) {
1035 for (i = 0; i < 4; i++) {
1036 sband->bitrates[i].hw_value =
1037 sband->bitrates[i].hw_value & 0xF;
1038 sband->bitrates[i].hw_value_short =
1039 sband->bitrates[i].hw_value_short & 0xF;
1040 }
1041 }
fa1c114f 1042
63266a65
BR		 1043 sband->channels = sc->channels;
1044 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1045 AR5K_MODE_11B, max_c);
d8ee398d 1046
63266a65
BR		 1047 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1048 count_c = sband->n_channels;
d8ee398d 1049 max_c -= count_c;
fa1c114f 1050 }
63266a65 1051 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1052
63266a65 1053 /* 5GHz band, A mode */
400ec45a 1054 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1055 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1056 sband->band = IEEE80211_BAND_5GHZ;
1057 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1058
63266a65
BR		 1059 memcpy(sband->bitrates, &ath5k_rates[4],
1060 sizeof(struct ieee80211_rate) * 8);
1061 sband->n_bitrates = 8;
fa1c114f 1062
63266a65 1063 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1064 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1065 AR5K_MODE_11A, max_c);
1066
d8ee398d
LR		 1067 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1068 }
63266a65 1069 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1070
b446197c 1071 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1072
1073 return 0;
fa1c114f
JS		 1074}
1075
1076/*
e30eb4ab
JA		 1077 * Set/change channels. We always reset the chip.
1078 * To accomplish this we must first cleanup any pending DMA,
1079 * then restart stuff after a la ath5k_init.
be009370
BC		 1080 *
1081 * Called with sc->lock.
fa1c114f
JS		 1082 */
1083static int
1084ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1085{
d8ee398d
LR		 1086 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1087 sc->curchan->center_freq, chan->center_freq);
1088
e30eb4ab
JA		 1089 /*
1090 * To switch channels clear any pending DMA operations;
1091 * wait long enough for the RX fifo to drain, reset the
1092 * hardware at the new frequency, and then re-enable
1093 * the relevant bits of the h/w.
1094 */
1095 return ath5k_reset(sc, chan);
fa1c114f
JS		 1096}
1097
1098static void
1099ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1100{
fa1c114f 1101 sc->curmode = mode;
d8ee398d 1102
400ec45a 1103 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1104 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1105 } else {
1106 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1107 }
fa1c114f
JS		 1108}
1109
1110static void
1111ath5k_mode_setup(struct ath5k_softc *sc)
1112{
1113 struct ath5k_hw *ah = sc->ah;
1114 u32 rfilt;
1115
ae6f53f2
BC		 1116 ah->ah_op_mode = sc->opmode;
1117
fa1c114f
JS		 1118 /* configure rx filter */
1119 rfilt = sc->filter_flags;
1120 ath5k_hw_set_rx_filter(ah, rfilt);
1121
1122 if (ath5k_hw_hasbssidmask(ah))
1123 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1124
1125 /* configure operational mode */
1126 ath5k_hw_set_opmode(ah);
1127
1128 ath5k_hw_set_mcast_filter(ah, 0, 0);
1129 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1130}
1131
d8ee398d 1132static inline int
63266a65
BR		 1133ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1134{
b7266047
BC		 1135 int rix;
1136
1137 /* return base rate on errors */
1138 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1139 "hw_rix out of bounds: %x\n", hw_rix))
1140 return 0;
1141
1142 rix = sc->rate_idx[sc->curband->band][hw_rix];
1143 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1144 rix = 0;
1145
1146 return rix;
d8ee398d
LR		 1147}
1148
fa1c114f
JS		 1149/***************\
1150* Buffers setup *
1151\***************/
1152
b6ea0356
BC		 1153static
1154struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1155{
1156 struct sk_buff *skb;
b6ea0356
BC		 1157
1158 /*
1159 * Allocate buffer with headroom_needed space for the
1160 * fake physical layer header at the start.
1161 */
aeb63cfd
LR		 1162 skb = ath_rxbuf_alloc(&sc->common,
1163 sc->rxbufsize + sc->common.cachelsz - 1,
1164 GFP_ATOMIC);
b6ea0356
BC		 1165
1166 if (!skb) {
1167 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
aeb63cfd 1168 sc->rxbufsize + sc->common.cachelsz - 1);
b6ea0356
BC		 1169 return NULL;
1170 }
b6ea0356
BC		 1171
1172 *skb_addr = pci_map_single(sc->pdev,
1173 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1174 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1175 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1176 dev_kfree_skb(skb);
1177 return NULL;
1178 }
1179 return skb;
1180}
1181
fa1c114f
JS		 1182static int
1183ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1184{
1185 struct ath5k_hw *ah = sc->ah;
1186 struct sk_buff *skb = bf->skb;
1187 struct ath5k_desc *ds;
1188
b6ea0356
BC		 1189 if (!skb) {
1190 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1191 if (!skb)
fa1c114f 1192 return -ENOMEM;
fa1c114f 1193 bf->skb = skb;
fa1c114f
JS		 1194 }
1195
1196 /*
1197 * Setup descriptors. For receive we always terminate
1198 * the descriptor list with a self-linked entry so we'll
1199 * not get overrun under high load (as can happen with a
1200 * 5212 when ANI processing enables PHY error frames).
1201 *
1202 * To insure the last descriptor is self-linked we create
1203 * each descriptor as self-linked and add it to the end. As
1204 * each additional descriptor is added the previous self-linked
1205 * entry is ``fixed'' naturally. This should be safe even
1206 * if DMA is happening. When processing RX interrupts we
1207 * never remove/process the last, self-linked, entry on the
1208 * descriptor list. This insures the hardware always has
1209 * someplace to write a new frame.
1210 */
1211 ds = bf->desc;
1212 ds->ds_link = bf->daddr; /* link to self */
1213 ds->ds_data = bf->skbaddr;
c6e387a2 1214 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1215 skb_tailroom(skb), /* buffer size */
1216 0);
1217
1218 if (sc->rxlink != NULL)
1219 *sc->rxlink = bf->daddr;
1220 sc->rxlink = &ds->ds_link;
1221 return 0;
1222}
1223
1224static int
cec8db23
BC		 1225ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1226 struct ath5k_txq *txq)
fa1c114f
JS		 1227{
1228 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1229 struct ath5k_desc *ds = bf->desc;
1230 struct sk_buff *skb = bf->skb;
a888d52d 1231 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1232 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1233 struct ieee80211_rate *rate;
1234 unsigned int mrr_rate[3], mrr_tries[3];
1235 int i, ret;
8902ff4e 1236 u16 hw_rate;
07c1e852
BC		 1237 u16 cts_rate = 0;
1238 u16 duration = 0;
8902ff4e 1239 u8 rc_flags;
fa1c114f
JS		 1240
1241 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1242
fa1c114f
JS		 1243 /* XXX endianness */
1244 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1245 PCI_DMA_TODEVICE);
1246
8902ff4e
BC		 1247 rate = ieee80211_get_tx_rate(sc->hw, info);
1248
e039fa4a 1249 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1250 flags |= AR5K_TXDESC_NOACK;
1251
8902ff4e
BC		 1252 rc_flags = info->control.rates[0].flags;
1253 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1254 rate->hw_value_short : rate->hw_value;
1255
281c56dd 1256 pktlen = skb->len;
fa1c114f 1257
8f655dde
NK		 1258 /* FIXME: If we are in g mode and rate is a CCK rate
1259 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1260 * from tx power (value is in dB units already) */
362695e1
BC		 1261 if (info->control.hw_key) {
1262 keyidx = info->control.hw_key->hw_key_idx;
1263 pktlen += info->control.hw_key->icv_len;
1264 }
07c1e852
BC		 1265 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1266 flags |= AR5K_TXDESC_RTSENA;
1267 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1268 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1269 sc->vif, pktlen, info));
1270 }
1271 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1272 flags |= AR5K_TXDESC_CTSENA;
1273 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1274 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1275 sc->vif, pktlen, info));
1276 }
fa1c114f
JS		 1277 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1278 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1279 (sc->power_level * 2),
8902ff4e 1280 hw_rate,
2bed03eb 1281 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1282 cts_rate, duration);
fa1c114f
JS		 1283 if (ret)
1284 goto err_unmap;
1285
2f7fe870
FF		 1286 memset(mrr_rate, 0, sizeof(mrr_rate));
1287 memset(mrr_tries, 0, sizeof(mrr_tries));
1288 for (i = 0; i < 3; i++) {
1289 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1290 if (!rate)
1291 break;
1292
1293 mrr_rate[i] = rate->hw_value;
e6a9854b 1294 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1295 }
1296
1297 ah->ah_setup_mrr_tx_desc(ah, ds,
1298 mrr_rate[0], mrr_tries[0],
1299 mrr_rate[1], mrr_tries[1],
1300 mrr_rate[2], mrr_tries[2]);
1301
fa1c114f
JS		 1302 ds->ds_link = 0;
1303 ds->ds_data = bf->skbaddr;
1304
1305 spin_lock_bh(&txq->lock);
1306 list_add_tail(&bf->list, &txq->q);
57ffc589 1307 sc->tx_stats[txq->qnum].len++;
fa1c114f 1308 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1309 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1310 else /* no, so only link it */
1311 *txq->link = bf->daddr;
1312
1313 txq->link = &ds->ds_link;
c6e387a2 1314 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1315 mmiowb();
fa1c114f
JS		 1316 spin_unlock_bh(&txq->lock);
1317
1318 return 0;
1319err_unmap:
1320 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1321 return ret;
1322}
1323
1324/*******************\
1325* Descriptors setup *
1326\*******************/
1327
1328static int
1329ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1330{
1331 struct ath5k_desc *ds;
1332 struct ath5k_buf *bf;
1333 dma_addr_t da;
1334 unsigned int i;
1335 int ret;
1336
1337 /* allocate descriptors */
1338 sc->desc_len = sizeof(struct ath5k_desc) *
1339 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1340 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1341 if (sc->desc == NULL) {
1342 ATH5K_ERR(sc, "can't allocate descriptors\n");
1343 ret = -ENOMEM;
1344 goto err;
1345 }
1346 ds = sc->desc;
1347 da = sc->desc_daddr;
1348 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1349 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1350
1351 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1352 sizeof(struct ath5k_buf), GFP_KERNEL);
1353 if (bf == NULL) {
1354 ATH5K_ERR(sc, "can't allocate bufptr\n");
1355 ret = -ENOMEM;
1356 goto err_free;
1357 }
1358 sc->bufptr = bf;
1359
1360 INIT_LIST_HEAD(&sc->rxbuf);
1361 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1362 bf->desc = ds;
1363 bf->daddr = da;
1364 list_add_tail(&bf->list, &sc->rxbuf);
1365 }
1366
1367 INIT_LIST_HEAD(&sc->txbuf);
1368 sc->txbuf_len = ATH_TXBUF;
1369 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1370 da += sizeof(*ds)) {
1371 bf->desc = ds;
1372 bf->daddr = da;
1373 list_add_tail(&bf->list, &sc->txbuf);
1374 }
1375
1376 /* beacon buffer */
1377 bf->desc = ds;
1378 bf->daddr = da;
1379 sc->bbuf = bf;
1380
1381 return 0;
1382err_free:
1383 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1384err:
1385 sc->desc = NULL;
1386 return ret;
1387}
1388
1389static void
1390ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1391{
1392 struct ath5k_buf *bf;
1393
1394 ath5k_txbuf_free(sc, sc->bbuf);
1395 list_for_each_entry(bf, &sc->txbuf, list)
1396 ath5k_txbuf_free(sc, bf);
1397 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1398 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1399
1400 /* Free memory associated with all descriptors */
1401 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1402
1403 kfree(sc->bufptr);
1404 sc->bufptr = NULL;
1405}
1406
1407
1408
1409
1410
1411/**************\
1412* Queues setup *
1413\**************/
1414
1415static struct ath5k_txq *
1416ath5k_txq_setup(struct ath5k_softc *sc,
1417 int qtype, int subtype)
1418{
1419 struct ath5k_hw *ah = sc->ah;
1420 struct ath5k_txq *txq;
1421 struct ath5k_txq_info qi = {
1422 .tqi_subtype = subtype,
1423 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1424 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1425 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1426 };
1427 int qnum;
1428
1429 /*
1430 * Enable interrupts only for EOL and DESC conditions.
1431 * We mark tx descriptors to receive a DESC interrupt
1432 * when a tx queue gets deep; otherwise waiting for the
1433 * EOL to reap descriptors. Note that this is done to
1434 * reduce interrupt load and this only defers reaping
1435 * descriptors, never transmitting frames. Aside from
1436 * reducing interrupts this also permits more concurrency.
1437 * The only potential downside is if the tx queue backs
1438 * up in which case the top half of the kernel may backup
1439 * due to a lack of tx descriptors.
1440 */
1441 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1442 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1443 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1444 if (qnum < 0) {
1445 /*
1446 * NB: don't print a message, this happens
1447 * normally on parts with too few tx queues
1448 */
1449 return ERR_PTR(qnum);
1450 }
1451 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1452 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1453 qnum, ARRAY_SIZE(sc->txqs));
1454 ath5k_hw_release_tx_queue(ah, qnum);
1455 return ERR_PTR(-EINVAL);
1456 }
1457 txq = &sc->txqs[qnum];
1458 if (!txq->setup) {
1459 txq->qnum = qnum;
1460 txq->link = NULL;
1461 INIT_LIST_HEAD(&txq->q);
1462 spin_lock_init(&txq->lock);
1463 txq->setup = true;
1464 }
1465 return &sc->txqs[qnum];
1466}
1467
1468static int
1469ath5k_beaconq_setup(struct ath5k_hw *ah)
1470{
1471 struct ath5k_txq_info qi = {
1472 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1473 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1474 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1475 /* NB: for dynamic turbo, don't enable any other interrupts */
1476 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1477 };
1478
1479 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1480}
1481
1482static int
1483ath5k_beaconq_config(struct ath5k_softc *sc)
1484{
1485 struct ath5k_hw *ah = sc->ah;
1486 struct ath5k_txq_info qi;
1487 int ret;
1488
1489 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1490 if (ret)
1491 return ret;
05c914fe
JB		 1492 if (sc->opmode == NL80211_IFTYPE_AP ||
1493 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1494 /*
1495 * Always burst out beacon and CAB traffic
1496 * (aifs = cwmin = cwmax = 0)
1497 */
1498 qi.tqi_aifs = 0;
1499 qi.tqi_cw_min = 0;
1500 qi.tqi_cw_max = 0;
05c914fe 1501 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1502 /*
1503 * Adhoc mode; backoff between 0 and (2 * cw_min).
1504 */
1505 qi.tqi_aifs = 0;
1506 qi.tqi_cw_min = 0;
1507 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1508 }
1509
6d91e1d8
BR		 1510 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1511 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1512 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1513
c6e387a2 1514 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1515 if (ret) {
1516 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1517 "hardware queue!\n", __func__);
1518 return ret;
1519 }
1520
1521 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1522}
1523
1524static void
1525ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1526{
1527 struct ath5k_buf *bf, *bf0;
1528
1529 /*
1530 * NB: this assumes output has been stopped and
1531 * we do not need to block ath5k_tx_tasklet
1532 */
1533 spin_lock_bh(&txq->lock);
1534 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1535 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1536
1537 ath5k_txbuf_free(sc, bf);
1538
1539 spin_lock_bh(&sc->txbuflock);
57ffc589 1540 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1541 list_move_tail(&bf->list, &sc->txbuf);
1542 sc->txbuf_len++;
1543 spin_unlock_bh(&sc->txbuflock);
1544 }
1545 txq->link = NULL;
1546 spin_unlock_bh(&txq->lock);
1547}
1548
1549/*
1550 * Drain the transmit queues and reclaim resources.
1551 */
1552static void
1553ath5k_txq_cleanup(struct ath5k_softc *sc)
1554{
1555 struct ath5k_hw *ah = sc->ah;
1556 unsigned int i;
1557
1558 /* XXX return value */
1559 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1560 /* don't touch the hardware if marked invalid */
1561 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1562 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1563 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1564 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1565 if (sc->txqs[i].setup) {
1566 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1567 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1568 "link %p\n",
1569 sc->txqs[i].qnum,
c6e387a2 1570 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1571 sc->txqs[i].qnum),
1572 sc->txqs[i].link);
1573 }
1574 }
36d6825b 1575 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1576
1577 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1578 if (sc->txqs[i].setup)
1579 ath5k_txq_drainq(sc, &sc->txqs[i]);
1580}
1581
1582static void
1583ath5k_txq_release(struct ath5k_softc *sc)
1584{
1585 struct ath5k_txq *txq = sc->txqs;
1586 unsigned int i;
1587
1588 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1589 if (txq->setup) {
1590 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1591 txq->setup = false;
1592 }
1593}
1594
1595
1596
1597
1598/*************\
1599* RX Handling *
1600\*************/
1601
1602/*
1603 * Enable the receive h/w following a reset.
1604 */
1605static int
1606ath5k_rx_start(struct ath5k_softc *sc)
1607{
1608 struct ath5k_hw *ah = sc->ah;
1609 struct ath5k_buf *bf;
1610 int ret;
1611
aeb63cfd 1612 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->common.cachelsz);
fa1c114f
JS		 1613
1614 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
aeb63cfd 1615 sc->common.cachelsz, sc->rxbufsize);
fa1c114f 1616
fa1c114f 1617 spin_lock_bh(&sc->rxbuflock);
26925042 1618 sc->rxlink = NULL;
fa1c114f
JS		 1619 list_for_each_entry(bf, &sc->rxbuf, list) {
1620 ret = ath5k_rxbuf_setup(sc, bf);
1621 if (ret != 0) {
1622 spin_unlock_bh(&sc->rxbuflock);
1623 goto err;
1624 }
1625 }
1626 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1627 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1628 spin_unlock_bh(&sc->rxbuflock);
1629
c6e387a2 1630 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1631 ath5k_mode_setup(sc); /* set filters, etc. */
1632 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1633
1634 return 0;
1635err:
1636 return ret;
1637}
1638
1639/*
1640 * Disable the receive h/w in preparation for a reset.
1641 */
1642static void
1643ath5k_rx_stop(struct ath5k_softc *sc)
1644{
1645 struct ath5k_hw *ah = sc->ah;
1646
c6e387a2 1647 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1648 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1649 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1650
1651 ath5k_debug_printrxbuffs(sc, ah);
1652
1653 sc->rxlink = NULL; /* just in case */
1654}
1655
1656static unsigned int
1657ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1658 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1659{
1660 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1661 unsigned int keyix, hlen;
fa1c114f 1662
b47f407b
BR		 1663 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1664 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1665 return RX_FLAG_DECRYPTED;
1666
1667 /* Apparently when a default key is used to decrypt the packet
1668 the hw does not set the index used to decrypt. In such cases
1669 get the index from the packet. */
798ee985 1670 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1671 if (ieee80211_has_protected(hdr->frame_control) &&
1672 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1673 skb->len >= hlen + 4) {
fa1c114f
JS		 1674 keyix = skb->data[hlen + 3] >> 6;
1675
1676 if (test_bit(keyix, sc->keymap))
1677 return RX_FLAG_DECRYPTED;
1678 }
1679
1680 return 0;
1681}
1682
036cd1ec
BR		 1683
1684static void
6ba81c2c
BR		 1685ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1686 struct ieee80211_rx_status *rxs)
036cd1ec 1687{
954fecea 1688 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1689 u64 tsf, bc_tstamp;
036cd1ec
BR		 1690 u32 hw_tu;
1691 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1692
24b56e70 1693 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1694 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1695 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1696 /*
6ba81c2c
BR		 1697 * Received an IBSS beacon with the same BSSID. Hardware *must*
1698 * have updated the local TSF. We have to work around various
1699 * hardware bugs, though...
036cd1ec 1700 */
6ba81c2c
BR		 1701 tsf = ath5k_hw_get_tsf64(sc->ah);
1702 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1703 hw_tu = TSF_TO_TU(tsf);
1704
1705 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1706 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1707 (unsigned long long)bc_tstamp,
1708 (unsigned long long)rxs->mactime,
1709 (unsigned long long)(rxs->mactime - bc_tstamp),
1710 (unsigned long long)tsf);
6ba81c2c
BR		 1711
1712 /*
1713 * Sometimes the HW will give us a wrong tstamp in the rx
1714 * status, causing the timestamp extension to go wrong.
1715 * (This seems to happen especially with beacon frames bigger
1716 * than 78 byte (incl. FCS))
1717 * But we know that the receive timestamp must be later than the
1718 * timestamp of the beacon since HW must have synced to that.
1719 *
1720 * NOTE: here we assume mactime to be after the frame was
1721 * received, not like mac80211 which defines it at the start.
1722 */
1723 if (bc_tstamp > rxs->mactime) {
036cd1ec 1724 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1725 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1726 (unsigned long long)rxs->mactime,
1727 (unsigned long long)tsf);
6ba81c2c 1728 rxs->mactime = tsf;
036cd1ec 1729 }
6ba81c2c
BR		 1730
1731 /*
1732 * Local TSF might have moved higher than our beacon timers,
1733 * in that case we have to update them to continue sending
1734 * beacons. This also takes care of synchronizing beacon sending
1735 * times with other stations.
1736 */
1737 if (hw_tu >= sc->nexttbtt)
1738 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1739 }
1740}
1741
fa1c114f
JS		 1742static void
1743ath5k_tasklet_rx(unsigned long data)
1744{
1c5256bb 1745 struct ieee80211_rx_status *rxs;
b47f407b 1746 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1747 struct sk_buff *skb, *next_skb;
1748 dma_addr_t next_skb_addr;
fa1c114f 1749 struct ath5k_softc *sc = (void *)data;
c57ca815 1750 struct ath5k_buf *bf;
fa1c114f 1751 struct ath5k_desc *ds;
fa1c114f
JS		 1752 int ret;
1753 int hdrlen;
0fe45b1d 1754 int padsize;
1c5256bb 1755 int rx_flag;
fa1c114f
JS		 1756
1757 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1758 if (list_empty(&sc->rxbuf)) {
1759 ATH5K_WARN(sc, "empty rx buf pool\n");
1760 goto unlock;
1761 }
fa1c114f 1762 do {
1c5256bb 1763 rx_flag = 0;
d6894b5b 1764
fa1c114f
JS		 1765 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1766 BUG_ON(bf->skb == NULL);
1767 skb = bf->skb;
1768 ds = bf->desc;
1769
c57ca815
BC		 1770 /* bail if HW is still using self-linked descriptor */
1771 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1772 break;
fa1c114f 1773
b47f407b 1774 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1775 if (unlikely(ret == -EINPROGRESS))
1776 break;
1777 else if (unlikely(ret)) {
1778 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1779 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1780 return;
1781 }
1782
b47f407b 1783 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1784 ATH5K_WARN(sc, "unsupported jumbo\n");
1785 goto next;
1786 }
1787
b47f407b
BR		 1788 if (unlikely(rs.rs_status)) {
1789 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1790 goto next;
b47f407b 1791 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1792 /*
1793 * Decrypt error. If the error occurred
1794 * because there was no hardware key, then
1795 * let the frame through so the upper layers
1796 * can process it. This is necessary for 5210
1797 * parts which have no way to setup a ``clear''
1798 * key cache entry.
1799 *
1800 * XXX do key cache faulting
1801 */
b47f407b
BR		 1802 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1803 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1804 goto accept;
1805 }
b47f407b 1806 if (rs.rs_status & AR5K_RXERR_MIC) {
1c5256bb 1807 rx_flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1808 goto accept;
1809 }
1810
1811 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1812 if ((rs.rs_status &
1813 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1814 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1815 goto next;
1816 }
1817accept:
b6ea0356
BC		 1818 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1819
1820 /*
1821 * If we can't replace bf->skb with a new skb under memory
1822 * pressure, just skip this packet
1823 */
1824 if (!next_skb)
1825 goto next;
1826
fa1c114f
JS		 1827 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1828 PCI_DMA_FROMDEVICE);
b47f407b 1829 skb_put(skb, rs.rs_datalen);
fa1c114f 1830
0fe45b1d
BP		 1831 /* The MAC header is padded to have 32-bit boundary if the
1832 * packet payload is non-zero. The general calculation for
1833 * padsize would take into account odd header lengths:
1834 * padsize = (4 - hdrlen % 4) % 4; However, since only
1835 * even-length headers are used, padding can only be 0 or 2
1836 * bytes and we can optimize this a bit. In addition, we must
1837 * not try to remove padding from short control frames that do
1838 * not have payload. */
fa1c114f 1839 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1840 padsize = ath5k_pad_size(hdrlen);
1841 if (padsize) {
0fe45b1d
BP		 1842 memmove(skb->data + padsize, skb->data, hdrlen);
1843 skb_pull(skb, padsize);
fa1c114f 1844 }
1c5256bb 1845 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 1846
c0e1899b
BR		 1847 /*
1848 * always extend the mac timestamp, since this information is
1849 * also needed for proper IBSS merging.
1850 *
1851 * XXX: it might be too late to do it here, since rs_tstamp is
1852 * 15bit only. that means TSF extension has to be done within
1853 * 32768usec (about 32ms). it might be necessary to move this to
1854 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1855 *
1856 * Unfortunately we don't know when the hardware takes the rx
1857 * timestamp (beginning of phy frame, data frame, end of rx?).
1858 * The only thing we know is that it is hardware specific...
1859 * On AR5213 it seems the rx timestamp is at the end of the
1860 * frame, but i'm not sure.
1861 *
1862 * NOTE: mac80211 defines mactime at the beginning of the first
1863 * data symbol. Since we don't have any time references it's
1864 * impossible to comply to that. This affects IBSS merge only
1865 * right now, so it's not too bad...
c0e1899b 1866 */
1c5256bb
BC		 1867 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1868 rxs->flag = rx_flag | RX_FLAG_TSFT;
c0e1899b 1869
1c5256bb
BC		 1870 rxs->freq = sc->curchan->center_freq;
1871 rxs->band = sc->curband->band;
fa1c114f 1872
1c5256bb
BC		 1873 rxs->noise = sc->ah->ah_noise_floor;
1874 rxs->signal = rxs->noise + rs.rs_rssi;
6e0e0bf8
LR		 1875
1876 /* An rssi of 35 indicates you should be able use
1877 * 54 Mbps reliably. A more elaborate scheme can be used
1878 * here but it requires a map of SNR/throughput for each
1879 * possible mode used */
1c5256bb 1880 rxs->qual = rs.rs_rssi * 100 / 35;
6e0e0bf8
LR		 1881
1882 /* rssi can be more than 35 though, anything above that
1883 * should be considered at 100% */
1c5256bb
BC		 1884 if (rxs->qual > 100)
1885 rxs->qual = 100;
fa1c114f 1886
1c5256bb
BC		 1887 rxs->antenna = rs.rs_antenna;
1888 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1889 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1890
1c5256bb
BC		 1891 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1892 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1893 rxs->flag |= RX_FLAG_SHORTPRE;
06303352 1894
fa1c114f
JS		 1895 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1896
036cd1ec 1897 /* check beacons in IBSS mode */
05c914fe 1898 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1c5256bb 1899 ath5k_check_ibss_tsf(sc, skb, rxs);
036cd1ec 1900
f1d58c25 1901 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 1902
1903 bf->skb = next_skb;
1904 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1905next:
1906 list_move_tail(&bf->list, &sc->rxbuf);
1907 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1908unlock:
fa1c114f
JS		 1909 spin_unlock(&sc->rxbuflock);
1910}
1911
1912
1913
1914
1915/*************\
1916* TX Handling *
1917\*************/
1918
1919static void
1920ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1921{
b47f407b 1922 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1923 struct ath5k_buf *bf, *bf0;
1924 struct ath5k_desc *ds;
1925 struct sk_buff *skb;
e039fa4a 1926 struct ieee80211_tx_info *info;
2f7fe870 1927 int i, ret;
fa1c114f
JS		 1928
1929 spin_lock(&txq->lock);
1930 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1931 ds = bf->desc;
1932
b47f407b 1933 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1934 if (unlikely(ret == -EINPROGRESS))
1935 break;
1936 else if (unlikely(ret)) {
1937 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1938 ret, txq->qnum);
1939 break;
1940 }
1941
1942 skb = bf->skb;
a888d52d 1943 info = IEEE80211_SKB_CB(skb);
fa1c114f 1944 bf->skb = NULL;
e039fa4a 1945
fa1c114f
JS		 1946 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1947 PCI_DMA_TODEVICE);
1948
e6a9854b 1949 ieee80211_tx_info_clear_status(info);
2f7fe870 1950 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1951 struct ieee80211_tx_rate *r =
1952 &info->status.rates[i];
2f7fe870
FF		 1953
1954 if (ts.ts_rate[i]) {
e6a9854b
JB		 1955 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1956 r->count = ts.ts_retry[i];
2f7fe870 1957 } else {
e6a9854b
JB		 1958 r->idx = -1;
1959 r->count = 0;
2f7fe870
FF		 1960 }
1961 }
1962
e6a9854b
JB		 1963 /* count the successful attempt as well */
1964 info->status.rates[ts.ts_final_idx].count++;
1965
b47f407b 1966 if (unlikely(ts.ts_status)) {
fa1c114f 1967 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1968 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1969 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1970 } else {
e039fa4a
JB		 1971 info->flags |= IEEE80211_TX_STAT_ACK;
1972 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1973 }
1974
e039fa4a 1975 ieee80211_tx_status(sc->hw, skb);
57ffc589 1976 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1977
1978 spin_lock(&sc->txbuflock);
57ffc589 1979 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1980 list_move_tail(&bf->list, &sc->txbuf);
1981 sc->txbuf_len++;
1982 spin_unlock(&sc->txbuflock);
1983 }
1984 if (likely(list_empty(&txq->q)))
1985 txq->link = NULL;
1986 spin_unlock(&txq->lock);
1987 if (sc->txbuf_len > ATH_TXBUF / 5)
1988 ieee80211_wake_queues(sc->hw);
1989}
1990
1991static void
1992ath5k_tasklet_tx(unsigned long data)
1993{
8784d2ee 1994 int i;
fa1c114f
JS		 1995 struct ath5k_softc *sc = (void *)data;
1996
8784d2ee
BC		 1997 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1998 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1999 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2000}
2001
2002
fa1c114f
JS		 2003/*****************\
2004* Beacon handling *
2005\*****************/
2006
2007/*
2008 * Setup the beacon frame for transmit.
2009 */
2010static int
e039fa4a 2011ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2012{
2013 struct sk_buff *skb = bf->skb;
a888d52d 2014 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2015 struct ath5k_hw *ah = sc->ah;
2016 struct ath5k_desc *ds;
2bed03eb
NK		 2017 int ret = 0;
2018 u8 antenna;
fa1c114f
JS		 2019 u32 flags;
2020
2021 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2022 PCI_DMA_TODEVICE);
2023 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2024 "skbaddr %llx\n", skb, skb->data, skb->len,
2025 (unsigned long long)bf->skbaddr);
8d8bb39b 2026 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2027 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2028 return -EIO;
2029 }
2030
2031 ds = bf->desc;
2bed03eb 2032 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2033
2034 flags = AR5K_TXDESC_NOACK;
05c914fe 2035 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2036 ds->ds_link = bf->daddr; /* self-linked */
2037 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2038 } else
fa1c114f 2039 ds->ds_link = 0;
2bed03eb
NK		 2040
2041 /*
2042 * If we use multiple antennas on AP and use
2043 * the Sectored AP scenario, switch antenna every
2044 * 4 beacons to make sure everybody hears our AP.
2045 * When a client tries to associate, hw will keep
2046 * track of the tx antenna to be used for this client
2047 * automaticaly, based on ACKed packets.
2048 *
2049 * Note: AP still listens and transmits RTS on the
2050 * default antenna which is supposed to be an omni.
2051 *
2052 * Note2: On sectored scenarios it's possible to have
2053 * multiple antennas (1omni -the default- and 14 sectors)
2054 * so if we choose to actually support this mode we need
2055 * to allow user to set how many antennas we have and tweak
2056 * the code below to send beacons on all of them.
2057 */
2058 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2059 antenna = sc->bsent & 4 ? 2 : 1;
2060
fa1c114f 2061
8f655dde
NK		 2062 /* FIXME: If we are in g mode and rate is a CCK rate
2063 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2064 * from tx power (value is in dB units already) */
fa1c114f 2065 ds->ds_data = bf->skbaddr;
281c56dd 2066 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2067 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2068 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2069 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2070 1, AR5K_TXKEYIX_INVALID,
400ec45a 2071 antenna, flags, 0, 0);
fa1c114f
JS		 2072 if (ret)
2073 goto err_unmap;
2074
2075 return 0;
2076err_unmap:
2077 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2078 return ret;
2079}
2080
2081/*
2082 * Transmit a beacon frame at SWBA. Dynamic updates to the
2083 * frame contents are done as needed and the slot time is
2084 * also adjusted based on current state.
2085 *
acf3c1a5
BC		 2086 * This is called from software irq context (beacontq or restq
2087 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2088 */
2089static void
2090ath5k_beacon_send(struct ath5k_softc *sc)
2091{
2092 struct ath5k_buf *bf = sc->bbuf;
2093 struct ath5k_hw *ah = sc->ah;
cec8db23 2094 struct sk_buff *skb;
fa1c114f 2095
be9b7259 2096 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2097
05c914fe
JB		 2098 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2099 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2100 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2101 return;
2102 }
2103 /*
2104 * Check if the previous beacon has gone out. If
2105 * not don't don't try to post another, skip this
2106 * period and wait for the next. Missed beacons
2107 * indicate a problem and should not occur. If we
2108 * miss too many consecutive beacons reset the device.
2109 */
2110 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2111 sc->bmisscount++;
be9b7259 2112 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2113 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2114 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2115 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2116 "stuck beacon time (%u missed)\n",
2117 sc->bmisscount);
2118 tasklet_schedule(&sc->restq);
2119 }
2120 return;
2121 }
2122 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2123 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2124 "resume beacon xmit after %u misses\n",
2125 sc->bmisscount);
2126 sc->bmisscount = 0;
2127 }
2128
2129 /*
2130 * Stop any current dma and put the new frame on the queue.
2131 * This should never fail since we check above that no frames
2132 * are still pending on the queue.
2133 */
2134 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2135 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2136 /* NB: hw still stops DMA, so proceed */
2137 }
fa1c114f 2138
1071db86
BC		 2139 /* refresh the beacon for AP mode */
2140 if (sc->opmode == NL80211_IFTYPE_AP)
2141 ath5k_beacon_update(sc->hw, sc->vif);
2142
c6e387a2
NK		 2143 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2144 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2145 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2146 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2147
cec8db23
BC		 2148 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2149 while (skb) {
2150 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2151 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2152 }
2153
fa1c114f
JS		 2154 sc->bsent++;
2155}
2156
2157
9804b98d
BR		 2158/**
2159 * ath5k_beacon_update_timers - update beacon timers
2160 *
2161 * @sc: struct ath5k_softc pointer we are operating on
2162 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2163 * beacon timer update based on the current HW TSF.
2164 *
2165 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2166 * of a received beacon or the current local hardware TSF and write it to the
2167 * beacon timer registers.
2168 *
2169 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2170 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2171 * when we otherwise know we have to update the timers, but we keep it in this
2172 * function to have it all together in one place.
2173 */
fa1c114f 2174static void
9804b98d 2175ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2176{
2177 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2178 u32 nexttbtt, intval, hw_tu, bc_tu;
2179 u64 hw_tsf;
fa1c114f
JS		 2180
2181 intval = sc->bintval & AR5K_BEACON_PERIOD;
2182 if (WARN_ON(!intval))
2183 return;
2184
9804b98d
BR		 2185 /* beacon TSF converted to TU */
2186 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2187
9804b98d
BR		 2188 /* current TSF converted to TU */
2189 hw_tsf = ath5k_hw_get_tsf64(ah);
2190 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2191
9804b98d
BR		 2192#define FUDGE 3
2193 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2194 if (bc_tsf == -1) {
2195 /*
2196 * no beacons received, called internally.
2197 * just need to refresh timers based on HW TSF.
2198 */
2199 nexttbtt = roundup(hw_tu + FUDGE, intval);
2200 } else if (bc_tsf == 0) {
2201 /*
2202 * no beacon received, probably called by ath5k_reset_tsf().
2203 * reset TSF to start with 0.
2204 */
2205 nexttbtt = intval;
2206 intval |= AR5K_BEACON_RESET_TSF;
2207 } else if (bc_tsf > hw_tsf) {
2208 /*
2209 * beacon received, SW merge happend but HW TSF not yet updated.
2210 * not possible to reconfigure timers yet, but next time we
2211 * receive a beacon with the same BSSID, the hardware will
2212 * automatically update the TSF and then we need to reconfigure
2213 * the timers.
2214 */
2215 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2216 "need to wait for HW TSF sync\n");
2217 return;
2218 } else {
2219 /*
2220 * most important case for beacon synchronization between STA.
2221 *
2222 * beacon received and HW TSF has been already updated by HW.
2223 * update next TBTT based on the TSF of the beacon, but make
2224 * sure it is ahead of our local TSF timer.
2225 */
2226 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2227 }
2228#undef FUDGE
fa1c114f 2229
036cd1ec
BR		 2230 sc->nexttbtt = nexttbtt;
2231
fa1c114f 2232 intval |= AR5K_BEACON_ENA;
fa1c114f 2233 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2234
2235 /*
2236 * debugging output last in order to preserve the time critical aspect
2237 * of this function
2238 */
2239 if (bc_tsf == -1)
2240 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2241 "reconfigured timers based on HW TSF\n");
2242 else if (bc_tsf == 0)
2243 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2244 "reset HW TSF and timers\n");
2245 else
2246 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2247 "updated timers based on beacon TSF\n");
2248
2249 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2250 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2251 (unsigned long long) bc_tsf,
2252 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2253 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2254 intval & AR5K_BEACON_PERIOD,
2255 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2256 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2257}
2258
2259
036cd1ec
BR		 2260/**
2261 * ath5k_beacon_config - Configure the beacon queues and interrupts
2262 *
2263 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2264 *
036cd1ec 2265 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2266 * interrupts to detect TSF updates only.
fa1c114f
JS		 2267 */
2268static void
2269ath5k_beacon_config(struct ath5k_softc *sc)
2270{
2271 struct ath5k_hw *ah = sc->ah;
b5f03956 2272 unsigned long flags;
fa1c114f 2273
21800491 2274 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2275 sc->bmisscount = 0;
dc1968e7 2276 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2277
21800491 2278 if (sc->enable_beacon) {
fa1c114f 2279 /*
036cd1ec
BR		 2280 * In IBSS mode we use a self-linked tx descriptor and let the
2281 * hardware send the beacons automatically. We have to load it
fa1c114f 2282 * only once here.
036cd1ec 2283 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2284 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2285 */
2286 ath5k_beaconq_config(sc);
fa1c114f 2287
036cd1ec
BR		 2288 sc->imask |= AR5K_INT_SWBA;
2289
da966bca 2290 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2291 if (ath5k_hw_hasveol(ah))
da966bca 2292 ath5k_beacon_send(sc);
da966bca
JS		 2293 } else
2294 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2295 } else {
2296 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2297 }
fa1c114f 2298
c6e387a2 2299 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2300 mmiowb();
2301 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2302}
2303
428cbd4f
NK		 2304static void ath5k_tasklet_beacon(unsigned long data)
2305{
2306 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2307
2308 /*
2309 * Software beacon alert--time to send a beacon.
2310 *
2311 * In IBSS mode we use this interrupt just to
2312 * keep track of the next TBTT (target beacon
2313 * transmission time) in order to detect wether
2314 * automatic TSF updates happened.
2315 */
2316 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2317 /* XXX: only if VEOL suppported */
2318 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2319 sc->nexttbtt += sc->bintval;
2320 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2321 "SWBA nexttbtt: %x hw_tu: %x "
2322 "TSF: %llx\n",
2323 sc->nexttbtt,
2324 TSF_TO_TU(tsf),
2325 (unsigned long long) tsf);
2326 } else {
2327 spin_lock(&sc->block);
2328 ath5k_beacon_send(sc);
2329 spin_unlock(&sc->block);
2330 }
2331}
2332
fa1c114f
JS		 2333
2334/********************\
2335* Interrupt handling *
2336\********************/
2337
2338static int
bb2becac 2339ath5k_init(struct ath5k_softc *sc)
fa1c114f 2340{
bc1b32d6
EO		 2341 struct ath5k_hw *ah = sc->ah;
2342 int ret, i;
fa1c114f
JS		 2343
2344 mutex_lock(&sc->lock);
2345
2346 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2347
2348 /*
2349 * Stop anything previously setup. This is safe
2350 * no matter this is the first time through or not.
2351 */
2352 ath5k_stop_locked(sc);
2353
2354 /*
2355 * The basic interface to setting the hardware in a good
2356 * state is ``reset''. On return the hardware is known to
2357 * be powered up and with interrupts disabled. This must
2358 * be followed by initialization of the appropriate bits
2359 * and then setup of the interrupt mask.
2360 */
d8ee398d
LR		 2361 sc->curchan = sc->hw->conf.channel;
2362 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2363 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2364 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
6e220662 2365 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
209d889b 2366 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2367 if (ret)
2368 goto done;
fa1c114f 2369
e6a3b616
TD		 2370 ath5k_rfkill_hw_start(ah);
2371
bc1b32d6
EO		 2372 /*
2373 * Reset the key cache since some parts do not reset the
2374 * contents on initial power up or resume from suspend.
2375 */
2376 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2377 ath5k_hw_reset_key(ah, i);
2378
fa1c114f 2379 /* Set ack to be sent at low bit-rates */
bc1b32d6 2380 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f 2381
6e220662
NK		 2382 /* Set PHY calibration inteval */
2383 ah->ah_cal_intval = ath5k_calinterval;
fa1c114f
JS		 2384
2385 ret = 0;
2386done:
274c7c36 2387 mmiowb();
fa1c114f
JS		 2388 mutex_unlock(&sc->lock);
2389 return ret;
2390}
2391
2392static int
2393ath5k_stop_locked(struct ath5k_softc *sc)
2394{
2395 struct ath5k_hw *ah = sc->ah;
2396
2397 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2398 test_bit(ATH_STAT_INVALID, sc->status));
2399
2400 /*
2401 * Shutdown the hardware and driver:
2402 * stop output from above
2403 * disable interrupts
2404 * turn off timers
2405 * turn off the radio
2406 * clear transmit machinery
2407 * clear receive machinery
2408 * drain and release tx queues
2409 * reclaim beacon resources
2410 * power down hardware
2411 *
2412 * Note that some of this work is not possible if the
2413 * hardware is gone (invalid).
2414 */
2415 ieee80211_stop_queues(sc->hw);
2416
2417 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2418 ath5k_led_off(sc);
c6e387a2 2419 ath5k_hw_set_imr(ah, 0);
274c7c36 2420 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2421 }
2422 ath5k_txq_cleanup(sc);
2423 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2424 ath5k_rx_stop(sc);
2425 ath5k_hw_phy_disable(ah);
2426 } else
2427 sc->rxlink = NULL;
2428
2429 return 0;
2430}
2431
2432/*
2433 * Stop the device, grabbing the top-level lock to protect
2434 * against concurrent entry through ath5k_init (which can happen
2435 * if another thread does a system call and the thread doing the
2436 * stop is preempted).
2437 */
2438static int
bb2becac 2439ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2440{
2441 int ret;
2442
2443 mutex_lock(&sc->lock);
2444 ret = ath5k_stop_locked(sc);
2445 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2446 /*
edd7fc70
NK		 2447 * Don't set the card in full sleep mode!
2448 *
2449 * a) When the device is in this state it must be carefully
2450 * woken up or references to registers in the PCI clock
2451 * domain may freeze the bus (and system). This varies
2452 * by chip and is mostly an issue with newer parts
2453 * (madwifi sources mentioned srev >= 0x78) that go to
2454 * sleep more quickly.
2455 *
2456 * b) On older chips full sleep results a weird behaviour
2457 * during wakeup. I tested various cards with srev < 0x78
2458 * and they don't wake up after module reload, a second
2459 * module reload is needed to bring the card up again.
2460 *
2461 * Until we figure out what's going on don't enable
2462 * full chip reset on any chip (this is what Legacy HAL
2463 * and Sam's HAL do anyway). Instead Perform a full reset
2464 * on the device (same as initial state after attach) and
2465 * leave it idle (keep MAC/BB on warm reset) */
2466 ret = ath5k_hw_on_hold(sc->ah);
2467
2468 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2469 "putting device to sleep\n");
fa1c114f
JS		 2470 }
2471 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2472
274c7c36 2473 mmiowb();
fa1c114f
JS		 2474 mutex_unlock(&sc->lock);
2475
10488f8a
JS		 2476 tasklet_kill(&sc->rxtq);
2477 tasklet_kill(&sc->txtq);
2478 tasklet_kill(&sc->restq);
6e220662 2479 tasklet_kill(&sc->calib);
acf3c1a5 2480 tasklet_kill(&sc->beacontq);
fa1c114f 2481
e6a3b616
TD		 2482 ath5k_rfkill_hw_stop(sc->ah);
2483
fa1c114f
JS		 2484 return ret;
2485}
2486
2487static irqreturn_t
2488ath5k_intr(int irq, void *dev_id)
2489{
2490 struct ath5k_softc *sc = dev_id;
2491 struct ath5k_hw *ah = sc->ah;
2492 enum ath5k_int status;
2493 unsigned int counter = 1000;
2494
2495 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2496 !ath5k_hw_is_intr_pending(ah)))
2497 return IRQ_NONE;
2498
2499 do {
fa1c114f
JS		 2500 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2501 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2502 status, sc->imask);
fa1c114f
JS		 2503 if (unlikely(status & AR5K_INT_FATAL)) {
2504 /*
2505 * Fatal errors are unrecoverable.
2506 * Typically these are caused by DMA errors.
2507 */
2508 tasklet_schedule(&sc->restq);
2509 } else if (unlikely(status & AR5K_INT_RXORN)) {
2510 tasklet_schedule(&sc->restq);
2511 } else {
2512 if (status & AR5K_INT_SWBA) {
56d2ac76 2513 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2514 }
2515 if (status & AR5K_INT_RXEOL) {
2516 /*
2517 * NB: the hardware should re-read the link when
2518 * RXE bit is written, but it doesn't work at
2519 * least on older hardware revs.
2520 */
2521 sc->rxlink = NULL;
2522 }
2523 if (status & AR5K_INT_TXURN) {
2524 /* bump tx trigger level */
2525 ath5k_hw_update_tx_triglevel(ah, true);
2526 }
4c674c60 2527 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2528 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2529 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2530 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2531 tasklet_schedule(&sc->txtq);
2532 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2533 /* TODO */
fa1c114f 2534 }
6e220662
NK		 2535 if (status & AR5K_INT_SWI) {
2536 tasklet_schedule(&sc->calib);
2537 }
fa1c114f 2538 if (status & AR5K_INT_MIB) {
194828a2
NK		 2539 /*
2540 * These stats are also used for ANI i think
2541 * so how about updating them more often ?
2542 */
2543 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f 2544 }
e6a3b616 2545 if (status & AR5K_INT_GPIO)
e6a3b616 2546 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2547
fa1c114f 2548 }
2516baa6 2549 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2550
2551 if (unlikely(!counter))
2552 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2553
6e220662
NK		 2554 ath5k_hw_calibration_poll(ah);
2555
fa1c114f
JS		 2556 return IRQ_HANDLED;
2557}
2558
2559static void
2560ath5k_tasklet_reset(unsigned long data)
2561{
2562 struct ath5k_softc *sc = (void *)data;
2563
d7dc1003 2564 ath5k_reset_wake(sc);
fa1c114f
JS		 2565}
2566
2567/*
2568 * Periodically recalibrate the PHY to account
2569 * for temperature/environment changes.
2570 */
2571static void
6e220662 2572ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2573{
2574 struct ath5k_softc *sc = (void *)data;
2575 struct ath5k_hw *ah = sc->ah;
2576
6e220662
NK		 2577 /* Only full calibration for now */
2578 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2579 return;
2580
2581 /* Stop queues so that calibration
2582 * doesn't interfere with tx */
2583 ieee80211_stop_queues(sc->hw);
2584
fa1c114f 2585 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2586 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2587 sc->curchan->hw_value);
fa1c114f 2588
6f3b414a 2589 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2590 /*
2591 * Rfgain is out of bounds, reset the chip
2592 * to load new gain values.
2593 */
2594 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2595 ath5k_reset_wake(sc);
fa1c114f
JS		 2596 }
2597 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2598 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2599 ieee80211_frequency_to_channel(
2600 sc->curchan->center_freq));
fa1c114f 2601
6e220662
NK		 2602 ah->ah_swi_mask = 0;
2603
2604 /* Wake queues */
2605 ieee80211_wake_queues(sc->hw);
2606
fa1c114f
JS		 2607}
2608
2609
fa1c114f
JS		 2610/********************\
2611* Mac80211 functions *
2612\********************/
2613
2614static int
e039fa4a 2615ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2616{
2617 struct ath5k_softc *sc = hw->priv;
2618
2619 return ath5k_tx_queue(hw, skb, sc->txq);
2620}
2621
2622static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2623 struct ath5k_txq *txq)
fa1c114f
JS		 2624{
2625 struct ath5k_softc *sc = hw->priv;
2626 struct ath5k_buf *bf;
2627 unsigned long flags;
2628 int hdrlen;
0fe45b1d 2629 int padsize;
fa1c114f
JS		 2630
2631 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2632
05c914fe 2633 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2634 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2635
2636 /*
2637 * the hardware expects the header padded to 4 byte boundaries
2638 * if this is not the case we add the padding after the header
2639 */
2640 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2641 padsize = ath5k_pad_size(hdrlen);
2642 if (padsize) {
0fe45b1d
BP		 2643
2644 if (skb_headroom(skb) < padsize) {
fa1c114f 2645 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2646 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2647 goto drop_packet;
fa1c114f 2648 }
0fe45b1d
BP		 2649 skb_push(skb, padsize);
2650 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2651 }
2652
fa1c114f
JS		 2653 spin_lock_irqsave(&sc->txbuflock, flags);
2654 if (list_empty(&sc->txbuf)) {
2655 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2656 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2657 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2658 goto drop_packet;
fa1c114f
JS		 2659 }
2660 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2661 list_del(&bf->list);
2662 sc->txbuf_len--;
2663 if (list_empty(&sc->txbuf))
2664 ieee80211_stop_queues(hw);
2665 spin_unlock_irqrestore(&sc->txbuflock, flags);
2666
2667 bf->skb = skb;
2668
cec8db23 2669 if (ath5k_txbuf_setup(sc, bf, txq)) {
fa1c114f
JS		 2670 bf->skb = NULL;
2671 spin_lock_irqsave(&sc->txbuflock, flags);
2672 list_add_tail(&bf->list, &sc->txbuf);
2673 sc->txbuf_len++;
2674 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2675 goto drop_packet;
fa1c114f 2676 }
5a0fe8ac 2677 return NETDEV_TX_OK;
fa1c114f 2678
5a0fe8ac
BC		 2679drop_packet:
2680 dev_kfree_skb_any(skb);
71ef99c8 2681 return NETDEV_TX_OK;
fa1c114f
JS		 2682}
2683
209d889b
BC		 2684/*
2685 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2686 * and change to the given channel.
2687 */
fa1c114f 2688static int
209d889b 2689ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2690{
fa1c114f
JS		 2691 struct ath5k_hw *ah = sc->ah;
2692 int ret;
2693
2694 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2695
209d889b 2696 if (chan) {
c6e387a2 2697 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2698 ath5k_txq_cleanup(sc);
2699 ath5k_rx_stop(sc);
209d889b
BC		 2700
2701 sc->curchan = chan;
2702 sc->curband = &sc->sbands[chan->band];
d7dc1003 2703 }
3355443a 2704 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2705 if (ret) {
fa1c114f
JS		 2706 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2707 goto err;
2708 }
d7dc1003 2709
fa1c114f 2710 ret = ath5k_rx_start(sc);
d7dc1003 2711 if (ret) {
fa1c114f
JS		 2712 ATH5K_ERR(sc, "can't start recv logic\n");
2713 goto err;
2714 }
d7dc1003 2715
fa1c114f 2716 /*
d7dc1003
JS		 2717 * Change channels and update the h/w rate map if we're switching;
2718 * e.g. 11a to 11b/g.
2719 *
2720 * We may be doing a reset in response to an ioctl that changes the
2721 * channel so update any state that might change as a result.
fa1c114f
JS		 2722 *
2723 * XXX needed?
2724 */
2725/* ath5k_chan_change(sc, c); */
fa1c114f 2726
d7dc1003
JS		 2727 ath5k_beacon_config(sc);
2728 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2729
2730 return 0;
2731err:
2732 return ret;
2733}
2734
d7dc1003
JS		 2735static int
2736ath5k_reset_wake(struct ath5k_softc *sc)
2737{
2738 int ret;
2739
209d889b 2740 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2741 if (!ret)
2742 ieee80211_wake_queues(sc->hw);
2743
2744 return ret;
2745}
2746
fa1c114f
JS		 2747static int ath5k_start(struct ieee80211_hw *hw)
2748{
bb2becac 2749 return ath5k_init(hw->priv);
fa1c114f
JS		 2750}
2751
2752static void ath5k_stop(struct ieee80211_hw *hw)
2753{
bb2becac 2754 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2755}
2756
2757static int ath5k_add_interface(struct ieee80211_hw *hw,
2758 struct ieee80211_if_init_conf *conf)
2759{
2760 struct ath5k_softc *sc = hw->priv;
2761 int ret;
2762
2763 mutex_lock(&sc->lock);
32bfd35d 2764 if (sc->vif) {
fa1c114f
JS		 2765 ret = 0;
2766 goto end;
2767 }
2768
32bfd35d 2769 sc->vif = conf->vif;
fa1c114f
JS		 2770
2771 switch (conf->type) {
da966bca 2772 case NL80211_IFTYPE_AP:
05c914fe
JB		 2773 case NL80211_IFTYPE_STATION:
2774 case NL80211_IFTYPE_ADHOC:
b706e65b 2775 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2776 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2777 sc->opmode = conf->type;
2778 break;
2779 default:
2780 ret = -EOPNOTSUPP;
2781 goto end;
2782 }
67d2e2df 2783
0e149cf5 2784 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
ae6f53f2 2785 ath5k_mode_setup(sc);
67d2e2df 2786
fa1c114f
JS		 2787 ret = 0;
2788end:
2789 mutex_unlock(&sc->lock);
2790 return ret;
2791}
2792
2793static void
2794ath5k_remove_interface(struct ieee80211_hw *hw,
2795 struct ieee80211_if_init_conf *conf)
2796{
2797 struct ath5k_softc *sc = hw->priv;
0e149cf5 2798 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2799
2800 mutex_lock(&sc->lock);
32bfd35d 2801 if (sc->vif != conf->vif)
fa1c114f
JS		 2802 goto end;
2803
0e149cf5 2804 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2805 sc->vif = NULL;
fa1c114f
JS		 2806end:
2807 mutex_unlock(&sc->lock);
2808}
2809
d8ee398d
LR		 2810/*
2811 * TODO: Phy disable/diversity etc
2812 */
fa1c114f 2813static int
e8975581 2814ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2815{
2816 struct ath5k_softc *sc = hw->priv;
a0823810 2817 struct ath5k_hw *ah = sc->ah;
e8975581 2818 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 2819 int ret = 0;
be009370
BC		 2820
2821 mutex_lock(&sc->lock);
fa1c114f 2822
e30eb4ab
JA		 2823 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2824 ret = ath5k_chan_set(sc, conf->channel);
2825 if (ret < 0)
2826 goto unlock;
2827 }
2bed03eb 2828
a0823810
NK		 2829 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2830 (sc->power_level != conf->power_level)) {
2831 sc->power_level = conf->power_level;
2832
2833 /* Half dB steps */
2834 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2835 }
fa1c114f 2836
2bed03eb
NK		 2837 /* TODO:
2838 * 1) Move this on config_interface and handle each case
2839 * separately eg. when we have only one STA vif, use
2840 * AR5K_ANTMODE_SINGLE_AP
2841 *
2842 * 2) Allow the user to change antenna mode eg. when only
2843 * one antenna is present
2844 *
2845 * 3) Allow the user to set default/tx antenna when possible
2846 *
2847 * 4) Default mode should handle 90% of the cases, together
2848 * with fixed a/b and single AP modes we should be able to
2849 * handle 99%. Sectored modes are extreme cases and i still
2850 * haven't found a usage for them. If we decide to support them,
2851 * then we must allow the user to set how many tx antennas we
2852 * have available
2853 */
2854 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
be009370 2855
55aa4e0f 2856unlock:
be009370 2857 mutex_unlock(&sc->lock);
55aa4e0f 2858 return ret;
fa1c114f
JS		 2859}
2860
3ac64bee
JB		 2861static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2862 int mc_count, struct dev_addr_list *mclist)
2863{
2864 u32 mfilt[2], val;
2865 int i;
2866 u8 pos;
2867
2868 mfilt[0] = 0;
2869 mfilt[1] = 1;
2870
2871 for (i = 0; i < mc_count; i++) {
2872 if (!mclist)
2873 break;
2874 /* calculate XOR of eight 6-bit values */
2875 val = get_unaligned_le32(mclist->dmi_addr + 0);
2876 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2877 val = get_unaligned_le32(mclist->dmi_addr + 3);
2878 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2879 pos &= 0x3f;
2880 mfilt[pos / 32] |= (1 << (pos % 32));
2881 /* XXX: we might be able to just do this instead,
2882 * but not sure, needs testing, if we do use this we'd
2883 * neet to inform below to not reset the mcast */
2884 /* ath5k_hw_set_mcast_filterindex(ah,
2885 * mclist->dmi_addr[5]); */
2886 mclist = mclist->next;
2887 }
2888
2889 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2890}
2891
fa1c114f
JS		 2892#define SUPPORTED_FIF_FLAGS \
2893 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2894 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2895 FIF_BCN_PRBRESP_PROMISC
2896/*
2897 * o always accept unicast, broadcast, and multicast traffic
2898 * o multicast traffic for all BSSIDs will be enabled if mac80211
2899 * says it should be
2900 * o maintain current state of phy ofdm or phy cck error reception.
2901 * If the hardware detects any of these type of errors then
2902 * ath5k_hw_get_rx_filter() will pass to us the respective
2903 * hardware filters to be able to receive these type of frames.
2904 * o probe request frames are accepted only when operating in
2905 * hostap, adhoc, or monitor modes
2906 * o enable promiscuous mode according to the interface state
2907 * o accept beacons:
2908 * - when operating in adhoc mode so the 802.11 layer creates
2909 * node table entries for peers,
2910 * - when operating in station mode for collecting rssi data when
2911 * the station is otherwise quiet, or
2912 * - when scanning
2913 */
2914static void ath5k_configure_filter(struct ieee80211_hw *hw,
2915 unsigned int changed_flags,
2916 unsigned int *new_flags,
3ac64bee 2917 u64 multicast)
fa1c114f
JS		 2918{
2919 struct ath5k_softc *sc = hw->priv;
2920 struct ath5k_hw *ah = sc->ah;
3ac64bee 2921 u32 mfilt[2], rfilt;
fa1c114f 2922
56d1de0a
BC		 2923 mutex_lock(&sc->lock);
2924
3ac64bee
JB		 2925 mfilt[0] = multicast;
2926 mfilt[1] = multicast >> 32;
fa1c114f
JS		 2927
2928 /* Only deal with supported flags */
2929 changed_flags &= SUPPORTED_FIF_FLAGS;
2930 *new_flags &= SUPPORTED_FIF_FLAGS;
2931
2932 /* If HW detects any phy or radar errors, leave those filters on.
2933 * Also, always enable Unicast, Broadcasts and Multicast
2934 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2935 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2936 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2937 AR5K_RX_FILTER_MCAST);
2938
2939 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2940 if (*new_flags & FIF_PROMISC_IN_BSS) {
2941 rfilt |= AR5K_RX_FILTER_PROM;
2942 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2943 } else {
fa1c114f 2944 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2945 }
fa1c114f
JS		 2946 }
2947
2948 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2949 if (*new_flags & FIF_ALLMULTI) {
2950 mfilt[0] = ~0;
2951 mfilt[1] = ~0;
fa1c114f
JS		 2952 }
2953
2954 /* This is the best we can do */
2955 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2956 rfilt |= AR5K_RX_FILTER_PHYERR;
2957
2958 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2959 * and probes for any BSSID, this needs testing */
2960 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2961 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2962
2963 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2964 * set we should only pass on control frames for this
2965 * station. This needs testing. I believe right now this
2966 * enables *all* control frames, which is OK.. but
2967 * but we should see if we can improve on granularity */
2968 if (*new_flags & FIF_CONTROL)
2969 rfilt |= AR5K_RX_FILTER_CONTROL;
2970
2971 /* Additional settings per mode -- this is per ath5k */
2972
2973 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2974
56d1de0a
BC		 2975 switch (sc->opmode) {
2976 case NL80211_IFTYPE_MESH_POINT:
2977 case NL80211_IFTYPE_MONITOR:
2978 rfilt |= AR5K_RX_FILTER_CONTROL |
2979 AR5K_RX_FILTER_BEACON |
2980 AR5K_RX_FILTER_PROBEREQ |
2981 AR5K_RX_FILTER_PROM;
2982 break;
2983 case NL80211_IFTYPE_AP:
2984 case NL80211_IFTYPE_ADHOC:
2985 rfilt |= AR5K_RX_FILTER_PROBEREQ |
2986 AR5K_RX_FILTER_BEACON;
2987 break;
2988 case NL80211_IFTYPE_STATION:
2989 if (sc->assoc)
2990 rfilt |= AR5K_RX_FILTER_BEACON;
2991 default:
2992 break;
2993 }
fa1c114f
JS		 2994
2995 /* Set filters */
0bbac08f 2996 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2997
2998 /* Set multicast bits */
2999 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3000 /* Set the cached hw filter flags, this will alter actually
3001 * be set in HW */
3002 sc->filter_flags = rfilt;
56d1de0a
BC		 3003
3004 mutex_unlock(&sc->lock);
fa1c114f
JS		 3005}
3006
3007static int
3008ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3009 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3010 struct ieee80211_key_conf *key)
fa1c114f
JS		 3011{
3012 struct ath5k_softc *sc = hw->priv;
3013 int ret = 0;
3014
9ad9a26e
BC		 3015 if (modparam_nohwcrypt)
3016 return -EOPNOTSUPP;
3017
65b5a698
BC		 3018 if (sc->opmode == NL80211_IFTYPE_AP)
3019 return -EOPNOTSUPP;
3020
0bbac08f 3021 switch (key->alg) {
fa1c114f 3022 case ALG_WEP:
fa1c114f 3023 case ALG_TKIP:
3f64b435 3024 break;
fa1c114f 3025 case ALG_CCMP:
1c818740
BC		 3026 if (sc->ah->ah_aes_support)
3027 break;
3028
fa1c114f
JS		 3029 return -EOPNOTSUPP;
3030 default:
3031 WARN_ON(1);
3032 return -EINVAL;
3033 }
3034
3035 mutex_lock(&sc->lock);
3036
3037 switch (cmd) {
3038 case SET_KEY:
dc822b5d
JB		 3039 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3040 sta ? sta->addr : NULL);
fa1c114f
JS		 3041 if (ret) {
3042 ATH5K_ERR(sc, "can't set the key\n");
3043 goto unlock;
3044 }
3045 __set_bit(key->keyidx, sc->keymap);
3046 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3047 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3048 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3049 break;
3050 case DISABLE_KEY:
3051 ath5k_hw_reset_key(sc->ah, key->keyidx);
3052 __clear_bit(key->keyidx, sc->keymap);
3053 break;
3054 default:
3055 ret = -EINVAL;
3056 goto unlock;
3057 }
3058
3059unlock:
274c7c36 3060 mmiowb();
fa1c114f
JS		 3061 mutex_unlock(&sc->lock);
3062 return ret;
3063}
3064
3065static int
3066ath5k_get_stats(struct ieee80211_hw *hw,
3067 struct ieee80211_low_level_stats *stats)
3068{
3069 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3070 struct ath5k_hw *ah = sc->ah;
3071
3072 /* Force update */
3073 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3074
3075 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3076
3077 return 0;
3078}
3079
3080static int
3081ath5k_get_tx_stats(struct ieee80211_hw *hw,
3082 struct ieee80211_tx_queue_stats *stats)
3083{
3084 struct ath5k_softc *sc = hw->priv;
3085
3086 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3087
3088 return 0;
3089}
3090
3091static u64
3092ath5k_get_tsf(struct ieee80211_hw *hw)
3093{
3094 struct ath5k_softc *sc = hw->priv;
3095
3096 return ath5k_hw_get_tsf64(sc->ah);
3097}
3098
3b5d665b
AF		 3099static void
3100ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3101{
3102 struct ath5k_softc *sc = hw->priv;
3103
3104 ath5k_hw_set_tsf64(sc->ah, tsf);
3105}
3106
fa1c114f
JS		 3107static void
3108ath5k_reset_tsf(struct ieee80211_hw *hw)
3109{
3110 struct ath5k_softc *sc = hw->priv;
3111
9804b98d
BR		 3112 /*
3113 * in IBSS mode we need to update the beacon timers too.
3114 * this will also reset the TSF if we call it with 0
3115 */
05c914fe 3116 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3117 ath5k_beacon_update_timers(sc, 0);
3118 else
3119 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3120}
3121
1071db86
BC		 3122/*
3123 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3124 * this is called only once at config_bss time, for AP we do it every
3125 * SWBA interrupt so that the TIM will reflect buffered frames.
3126 *
3127 * Called with the beacon lock.
3128 */
fa1c114f 3129static int
1071db86 3130ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3131{
fa1c114f 3132 int ret;
1071db86 3133 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3134 struct sk_buff *skb;
3135
3136 if (WARN_ON(!vif)) {
3137 ret = -EINVAL;
3138 goto out;
3139 }
3140
3141 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3142
3143 if (!skb) {
3144 ret = -ENOMEM;
3145 goto out;
3146 }
fa1c114f
JS		 3147
3148 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3149
fa1c114f
JS		 3150 ath5k_txbuf_free(sc, sc->bbuf);
3151 sc->bbuf->skb = skb;
e039fa4a 3152 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3153 if (ret)
3154 sc->bbuf->skb = NULL;
1071db86
BC		 3155out:
3156 return ret;
3157}
3158
02969b38
MX		 3159static void
3160set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3161{
3162 struct ath5k_softc *sc = hw->priv;
3163 struct ath5k_hw *ah = sc->ah;
3164 u32 rfilt;
3165 rfilt = ath5k_hw_get_rx_filter(ah);
3166 if (enable)
3167 rfilt |= AR5K_RX_FILTER_BEACON;
3168 else
3169 rfilt &= ~AR5K_RX_FILTER_BEACON;
3170 ath5k_hw_set_rx_filter(ah, rfilt);
3171 sc->filter_flags = rfilt;
3172}
fa1c114f 3173
02969b38
MX		 3174static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3175 struct ieee80211_vif *vif,
3176 struct ieee80211_bss_conf *bss_conf,
3177 u32 changes)
3178{
3179 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3180 struct ath5k_hw *ah = sc->ah;
954fecea 3181 struct ath_common *common = ath5k_hw_common(ah);
21800491 3182 unsigned long flags;
2d0ddec5
JB		 3183
3184 mutex_lock(&sc->lock);
3185 if (WARN_ON(sc->vif != vif))
3186 goto unlock;
3187
3188 if (changes & BSS_CHANGED_BSSID) {
3189 /* Cache for later use during resets */
954fecea 3190 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2d0ddec5
JB		 3191 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3192 * a clean way of letting us retrieve this yet. */
954fecea 3193 ath5k_hw_set_associd(ah, common->curbssid, 0);
2d0ddec5
JB		 3194 mmiowb();
3195 }
57c4d7b4
JB		 3196
3197 if (changes & BSS_CHANGED_BEACON_INT)
3198 sc->bintval = bss_conf->beacon_int;
3199
02969b38 3200 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3201 sc->assoc = bss_conf->assoc;
3202 if (sc->opmode == NL80211_IFTYPE_STATION)
3203 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3204 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3205 AR5K_LED_ASSOC : AR5K_LED_INIT);
02969b38 3206 }
2d0ddec5 3207
21800491
BC		 3208 if (changes & BSS_CHANGED_BEACON) {
3209 spin_lock_irqsave(&sc->block, flags);
3210 ath5k_beacon_update(hw, vif);
3211 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3212 }
3213
21800491
BC		 3214 if (changes & BSS_CHANGED_BEACON_ENABLED)
3215 sc->enable_beacon = bss_conf->enable_beacon;
3216
3217 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3218 BSS_CHANGED_BEACON_INT))
3219 ath5k_beacon_config(sc);
3220
2d0ddec5
JB		 3221 unlock:
3222 mutex_unlock(&sc->lock);
02969b38 3223}
f0f3d388
BC		 3224
3225static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3226{
3227 struct ath5k_softc *sc = hw->priv;
3228 if (!sc->assoc)
3229 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3230}
3231
3232static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3233{
3234 struct ath5k_softc *sc = hw->priv;
3235 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3236 AR5K_LED_ASSOC : AR5K_LED_INIT);
3237}
Linux kernel - Deliverables
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