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ath5k: fix reference clock frequency for spur mitigation on AR2413
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
0e472252
BC		 64#define CREATE_TRACE_POINTS
65#include "trace.h"
66
18cb6e32
JL		 67int ath5k_modparam_nohwcrypt;
68module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 69MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 70
42639fcd 71static int modparam_all_channels;
46802a4f 72module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 73MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
a99168ee
NK		 75static int modparam_fastchanswitch;
76module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
77MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
78
79
fa1c114f
JS		 80/* Module info */
81MODULE_AUTHOR("Jiri Slaby");
82MODULE_AUTHOR("Nick Kossifidis");
83MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
84MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
85MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 86
132b1c3e 87static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 88static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
89 bool skip_pcu);
fa1c114f 90
fa1c114f 91/* Known SREVs */
2c91108c 92static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 93#ifdef CONFIG_ATHEROS_AR231X
94 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
96 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
97 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
99 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
101#else
1bef016a
NK		 102 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
103 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
104 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
105 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
106 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
107 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
108 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
109 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
110 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
111 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
112 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
113 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
114 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
115 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
116 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
117 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
118 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
119 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 120#endif
1bef016a 121 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 124 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 125 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
126 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
127 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 128 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 131 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
132 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
133 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 134 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 135 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 136#ifdef CONFIG_ATHEROS_AR231X
137 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
138 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
139#endif
fa1c114f
JS		 140 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
141};
142
2c91108c 143static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 144 { .bitrate = 10,
145 .hw_value = ATH5K_RATE_CODE_1M, },
146 { .bitrate = 20,
147 .hw_value = ATH5K_RATE_CODE_2M,
148 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
149 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
150 { .bitrate = 55,
151 .hw_value = ATH5K_RATE_CODE_5_5M,
152 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
153 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
154 { .bitrate = 110,
155 .hw_value = ATH5K_RATE_CODE_11M,
156 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 { .bitrate = 60,
159 .hw_value = ATH5K_RATE_CODE_6M,
160 .flags = 0 },
161 { .bitrate = 90,
162 .hw_value = ATH5K_RATE_CODE_9M,
163 .flags = 0 },
164 { .bitrate = 120,
165 .hw_value = ATH5K_RATE_CODE_12M,
166 .flags = 0 },
167 { .bitrate = 180,
168 .hw_value = ATH5K_RATE_CODE_18M,
169 .flags = 0 },
170 { .bitrate = 240,
171 .hw_value = ATH5K_RATE_CODE_24M,
172 .flags = 0 },
173 { .bitrate = 360,
174 .hw_value = ATH5K_RATE_CODE_36M,
175 .flags = 0 },
176 { .bitrate = 480,
177 .hw_value = ATH5K_RATE_CODE_48M,
178 .flags = 0 },
179 { .bitrate = 540,
180 .hw_value = ATH5K_RATE_CODE_54M,
181 .flags = 0 },
182 /* XR missing */
183};
184
fa1c114f
JS		 185static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
186{
187 u64 tsf = ath5k_hw_get_tsf64(ah);
188
189 if ((tsf & 0x7fff) < rstamp)
190 tsf -= 0x8000;
191
192 return (tsf & ~0x7fff) | rstamp;
193}
194
e5b046d8 195const char *
fa1c114f
JS		 196ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
197{
198 const char *name = "xxxxx";
199 unsigned int i;
200
201 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
202 if (srev_names[i].sr_type != type)
203 continue;
75d0edb8
NK		 204
205 if ((val & 0xf0) == srev_names[i].sr_val)
206 name = srev_names[i].sr_name;
207
208 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 209 name = srev_names[i].sr_name;
210 break;
211 }
212 }
213
214 return name;
215}
e5aa8474
LR		 216static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
217{
218 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
219 return ath5k_hw_reg_read(ah, reg_offset);
220}
221
222static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
223{
224 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
225 ath5k_hw_reg_write(ah, val, reg_offset);
226}
227
228static const struct ath_ops ath5k_common_ops = {
229 .read = ath5k_ioread32,
230 .write = ath5k_iowrite32,
231};
fa1c114f 232
8a63facc
BC		 233/***********************\
234* Driver Initialization *
235\***********************/
236
237static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 238{
8a63facc
BC		 239 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
240 struct ath5k_softc *sc = hw->priv;
241 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 242
8a63facc
BC		 243 return ath_reg_notifier_apply(wiphy, request, regulatory);
244}
6ccf15a1 245
8a63facc
BC		 246/********************\
247* Channel/mode setup *
248\********************/
fa1c114f 249
8a63facc
BC		 250/*
251 * Returns true for the channel numbers used without all_channels modparam.
252 */
410e6120 253static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 254{
410e6120
BR		 255 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
256 return true;
257
258 return /* UNII 1,2 */
259 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 260 /* midband */
261 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
262 /* UNII-3 */
410e6120
BR		 263 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
264 /* 802.11j 5.030-5.080 GHz (20MHz) */
265 (chan == 8 || chan == 12 || chan == 16) ||
266 /* 802.11j 4.9GHz (20MHz) */
267 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 268}
fa1c114f 269
8a63facc 270static unsigned int
97d9c3a3
BR		 271ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
272 unsigned int mode, unsigned int max)
8a63facc 273{
2b1351a3 274 unsigned int count, size, chfreq, freq, ch;
90c02d72 275 enum ieee80211_band band;
fa1c114f 276
8a63facc
BC		 277 switch (mode) {
278 case AR5K_MODE_11A:
8a63facc 279 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 280 size = 220;
8a63facc 281 chfreq = CHANNEL_5GHZ;
90c02d72 282 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 283 break;
284 case AR5K_MODE_11B:
285 case AR5K_MODE_11G:
8a63facc
BC		 286 size = 26;
287 chfreq = CHANNEL_2GHZ;
90c02d72 288 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 289 break;
290 default:
291 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
292 return 0;
fa1c114f
JS		 293 }
294
2b1351a3
BR		 295 count = 0;
296 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 297 freq = ieee80211_channel_to_frequency(ch, band);
298
299 if (freq == 0) /* mapping failed - not a standard channel */
300 continue;
fa1c114f 301
8a63facc
BC		 302 /* Check if channel is supported by the chipset */
303 if (!ath5k_channel_ok(ah, freq, chfreq))
304 continue;
f59ac048 305
410e6120
BR		 306 if (!modparam_all_channels &&
307 !ath5k_is_standard_channel(ch, band))
8a63facc 308 continue;
f59ac048 309
8a63facc
BC		 310 /* Write channel info and increment counter */
311 channels[count].center_freq = freq;
90c02d72 312 channels[count].band = band;
8a63facc
BC		 313 switch (mode) {
314 case AR5K_MODE_11A:
315 case AR5K_MODE_11G:
316 channels[count].hw_value = chfreq | CHANNEL_OFDM;
317 break;
8a63facc
BC		 318 case AR5K_MODE_11B:
319 channels[count].hw_value = CHANNEL_B;
320 }
fa1c114f 321
8a63facc 322 count++;
8a63facc 323 }
fa1c114f 324
8a63facc
BC		 325 return count;
326}
fa1c114f 327
8a63facc
BC		 328static void
329ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
330{
331 u8 i;
fa1c114f 332
8a63facc
BC		 333 for (i = 0; i < AR5K_MAX_RATES; i++)
334 sc->rate_idx[b->band][i] = -1;
fa1c114f 335
8a63facc
BC		 336 for (i = 0; i < b->n_bitrates; i++) {
337 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
338 if (b->bitrates[i].hw_value_short)
339 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 340 }
8a63facc 341}
fa1c114f 342
8a63facc
BC		 343static int
344ath5k_setup_bands(struct ieee80211_hw *hw)
345{
346 struct ath5k_softc *sc = hw->priv;
347 struct ath5k_hw *ah = sc->ah;
348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
fa1c114f 351
8a63facc
BC		 352 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(sc->channels);
db719718 354
8a63facc
BC		 355 /* 2GHz band */
356 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
357 sband->band = IEEE80211_BAND_2GHZ;
358 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 359
8a63facc
BC		 360 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
361 /* G mode */
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
2f7fe870 365
8a63facc 366 sband->channels = sc->channels;
08105690 367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 368 AR5K_MODE_11G, max_c);
fa1c114f 369
8a63facc
BC		 370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
372 max_c -= count_c;
373 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
374 /* B mode */
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
fa1c114f 378
8a63facc
BC		 379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
381 * fix them up here:
382 */
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 389 }
390 }
fa1c114f 391
8a63facc 392 sband->channels = sc->channels;
08105690 393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 394 AR5K_MODE_11B, max_c);
fa1c114f 395
8a63facc
BC		 396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
399 }
400 ath5k_setup_rate_idx(sc, sband);
fa1c114f 401
8a63facc
BC		 402 /* 5GHz band, A mode */
403 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
404 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
405 sband->band = IEEE80211_BAND_5GHZ;
406 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 407
8a63facc
BC		 408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
fa1c114f 411
8a63facc 412 sband->channels = &sc->channels[count_c];
08105690 413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 414 AR5K_MODE_11A, max_c);
fa1c114f 415
8a63facc
BC		 416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
418 ath5k_setup_rate_idx(sc, sband);
419
420 ath5k_debug_dump_bands(sc);
fa1c114f 421
fa1c114f
JS		 422 return 0;
423}
424
8a63facc
BC		 425/*
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
429 *
430 * Called with sc->lock.
431 */
cd2c5486 432int
8a63facc
BC		 433ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
434{
435 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
436 "channel set, resetting (%u -> %u MHz)\n",
437 sc->curchan->center_freq, chan->center_freq);
438
8451d22d 439 /*
8a63facc
BC		 440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
8451d22d 444 */
8aec7af9 445 return ath5k_reset(sc, chan, true);
fa1c114f 446}
fa1c114f 447
e4b0b32a 448void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
b1ae1edf 449{
e4b0b32a 450 struct ath5k_vif_iter_data *iter_data = data;
b1ae1edf 451 int i;
62c58fb4 452 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 453
454 if (iter_data->hw_macaddr)
455 for (i = 0; i < ETH_ALEN; i++)
456 iter_data->mask[i] &=
457 ~(iter_data->hw_macaddr[i] ^ mac[i]);
458
459 if (!iter_data->found_active) {
460 iter_data->found_active = true;
461 memcpy(iter_data->active_mac, mac, ETH_ALEN);
462 }
463
464 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
465 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
466 iter_data->need_set_hw_addr = false;
467
468 if (!iter_data->any_assoc) {
b1ae1edf
BG		 469 if (avf->assoc)
470 iter_data->any_assoc = true;
471 }
62c58fb4
BG		 472
473 /* Calculate combined mode - when APs are active, operate in AP mode.
474 * Otherwise use the mode of the new interface. This can currently
475 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 476 * interfaces is allowed.
62c58fb4
BG		 477 */
478 if (avf->opmode == NL80211_IFTYPE_AP)
479 iter_data->opmode = NL80211_IFTYPE_AP;
e4b0b32a
BG		 480 else {
481 if (avf->opmode == NL80211_IFTYPE_STATION)
482 iter_data->n_stas++;
62c58fb4
BG		 483 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
484 iter_data->opmode = avf->opmode;
e4b0b32a 485 }
b1ae1edf
BG		 486}
487
cd2c5486
BR		 488void
489ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
490 struct ieee80211_vif *vif)
b1ae1edf
BG		 491{
492 struct ath_common *common = ath5k_hw_common(sc->ah);
e4b0b32a
BG		 493 struct ath5k_vif_iter_data iter_data;
494 u32 rfilt;
b1ae1edf
BG		 495
496 /*
497 * Use the hardware MAC address as reference, the hardware uses it
498 * together with the BSSID mask when matching addresses.
499 */
500 iter_data.hw_macaddr = common->macaddr;
501 memset(&iter_data.mask, 0xff, ETH_ALEN);
502 iter_data.found_active = false;
503 iter_data.need_set_hw_addr = true;
62c58fb4 504 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
e4b0b32a 505 iter_data.n_stas = 0;
b1ae1edf
BG		 506
507 if (vif)
e4b0b32a 508 ath5k_vif_iter(&iter_data, vif->addr, vif);
b1ae1edf
BG		 509
510 /* Get list of all active MAC addresses */
e4b0b32a 511 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
b1ae1edf
BG		 512 &iter_data);
513 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
514
62c58fb4
BG		 515 sc->opmode = iter_data.opmode;
516 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
517 /* Nothing active, default to station mode */
518 sc->opmode = NL80211_IFTYPE_STATION;
519
7afbb2f0
BG		 520 ath5k_hw_set_opmode(sc->ah, sc->opmode);
521 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
522 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 523
b1ae1edf
BG		 524 if (iter_data.need_set_hw_addr && iter_data.found_active)
525 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
526
62c58fb4
BG		 527 if (ath5k_hw_hasbssidmask(sc->ah))
528 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf 529
e4b0b32a
BG		 530 /* Set up RX Filter */
531 if (iter_data.n_stas > 1) {
532 /* If you have multiple STA interfaces connected to
533 * different APs, ARPs are not received (most of the time?)
6a2a0e73 534 * Enabling PROMISC appears to fix that problem.
e4b0b32a
BG		 535 */
536 sc->filter_flags |= AR5K_RX_FILTER_PROM;
537 }
fa1c114f 538
8a63facc 539 rfilt = sc->filter_flags;
e4b0b32a 540 ath5k_hw_set_rx_filter(sc->ah, rfilt);
8a63facc
BC		 541 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
542}
fa1c114f 543
8a63facc
BC		 544static inline int
545ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
546{
547 int rix;
fa1c114f 548
8a63facc
BC		 549 /* return base rate on errors */
550 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
551 "hw_rix out of bounds: %x\n", hw_rix))
552 return 0;
553
930a7622 554 rix = sc->rate_idx[sc->curchan->band][hw_rix];
8a63facc
BC		 555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
556 rix = 0;
557
558 return rix;
559}
560
561/***************\
562* Buffers setup *
563\***************/
564
565static
566struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
567{
568 struct ath_common *common = ath5k_hw_common(sc->ah);
569 struct sk_buff *skb;
fa1c114f
JS		 570
571 /*
8a63facc
BC		 572 * Allocate buffer with headroom_needed space for the
573 * fake physical layer header at the start.
fa1c114f 574 */
8a63facc
BC		 575 skb = ath_rxbuf_alloc(common,
576 common->rx_bufsize,
577 GFP_ATOMIC);
fa1c114f 578
8a63facc
BC		 579 if (!skb) {
580 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
581 common->rx_bufsize);
582 return NULL;
fa1c114f
JS		 583 }
584
aeae4ac9 585 *skb_addr = dma_map_single(sc->dev,
8a63facc 586 skb->data, common->rx_bufsize,
aeae4ac9
FF		 587 DMA_FROM_DEVICE);
588
589 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 590 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
591 dev_kfree_skb(skb);
592 return NULL;
0e149cf5 593 }
8a63facc
BC		 594 return skb;
595}
0e149cf5 596
8a63facc
BC		 597static int
598ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
599{
600 struct ath5k_hw *ah = sc->ah;
601 struct sk_buff *skb = bf->skb;
602 struct ath5k_desc *ds;
603 int ret;
fa1c114f 604
8a63facc
BC		 605 if (!skb) {
606 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
607 if (!skb)
608 return -ENOMEM;
609 bf->skb = skb;
f769c36b
BC		 610 }
611
8a63facc
BC		 612 /*
613 * Setup descriptors. For receive we always terminate
614 * the descriptor list with a self-linked entry so we'll
615 * not get overrun under high load (as can happen with a
616 * 5212 when ANI processing enables PHY error frames).
617 *
618 * To ensure the last descriptor is self-linked we create
619 * each descriptor as self-linked and add it to the end. As
620 * each additional descriptor is added the previous self-linked
621 * entry is "fixed" naturally. This should be safe even
622 * if DMA is happening. When processing RX interrupts we
623 * never remove/process the last, self-linked, entry on the
624 * descriptor list. This ensures the hardware always has
625 * someplace to write a new frame.
626 */
627 ds = bf->desc;
628 ds->ds_link = bf->daddr; /* link to self */
629 ds->ds_data = bf->skbaddr;
630 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 631 if (ret) {
8a63facc
BC		 632 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
633 return ret;
fa1c114f
JS		 634 }
635
8a63facc
BC		 636 if (sc->rxlink != NULL)
637 *sc->rxlink = bf->daddr;
638 sc->rxlink = &ds->ds_link;
fa1c114f 639 return 0;
fa1c114f
JS		 640}
641
8a63facc 642static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 643{
8a63facc
BC		 644 struct ieee80211_hdr *hdr;
645 enum ath5k_pkt_type htype;
646 __le16 fc;
fa1c114f 647
8a63facc
BC		 648 hdr = (struct ieee80211_hdr *)skb->data;
649 fc = hdr->frame_control;
fa1c114f 650
8a63facc
BC		 651 if (ieee80211_is_beacon(fc))
652 htype = AR5K_PKT_TYPE_BEACON;
653 else if (ieee80211_is_probe_resp(fc))
654 htype = AR5K_PKT_TYPE_PROBE_RESP;
655 else if (ieee80211_is_atim(fc))
656 htype = AR5K_PKT_TYPE_ATIM;
657 else if (ieee80211_is_pspoll(fc))
658 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 659 else
8a63facc 660 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 661
8a63facc 662 return htype;
42639fcd
BC		 663}
664
8a63facc
BC		 665static int
666ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
667 struct ath5k_txq *txq, int padsize)
fa1c114f 668{
8a63facc
BC		 669 struct ath5k_hw *ah = sc->ah;
670 struct ath5k_desc *ds = bf->desc;
671 struct sk_buff *skb = bf->skb;
672 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
673 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
674 struct ieee80211_rate *rate;
675 unsigned int mrr_rate[3], mrr_tries[3];
676 int i, ret;
677 u16 hw_rate;
678 u16 cts_rate = 0;
679 u16 duration = 0;
680 u8 rc_flags;
fa1c114f 681
8a63facc 682 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 683
8a63facc 684 /* XXX endianness */
aeae4ac9
FF		 685 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
686 DMA_TO_DEVICE);
fa1c114f 687
8a63facc 688 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 689 if (!rate) {
690 ret = -EINVAL;
691 goto err_unmap;
692 }
fa1c114f 693
8a63facc
BC		 694 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
695 flags |= AR5K_TXDESC_NOACK;
fa1c114f 696
8a63facc
BC		 697 rc_flags = info->control.rates[0].flags;
698 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
699 rate->hw_value_short : rate->hw_value;
42639fcd 700
8a63facc
BC		 701 pktlen = skb->len;
702
703 /* FIXME: If we are in g mode and rate is a CCK rate
704 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
705 * from tx power (value is in dB units already) */
706 if (info->control.hw_key) {
707 keyidx = info->control.hw_key->hw_key_idx;
708 pktlen += info->control.hw_key->icv_len;
709 }
710 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
711 flags |= AR5K_TXDESC_RTSENA;
712 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
713 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 714 info->control.vif, pktlen, info));
8a63facc
BC		 715 }
716 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
717 flags |= AR5K_TXDESC_CTSENA;
718 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
719 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 720 info->control.vif, pktlen, info));
8a63facc
BC		 721 }
722 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
723 ieee80211_get_hdrlen_from_skb(skb), padsize,
724 get_hw_packet_type(skb),
725 (sc->power_level * 2),
726 hw_rate,
727 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
728 cts_rate, duration);
729 if (ret)
730 goto err_unmap;
731
732 memset(mrr_rate, 0, sizeof(mrr_rate));
733 memset(mrr_tries, 0, sizeof(mrr_tries));
734 for (i = 0; i < 3; i++) {
735 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
736 if (!rate)
400ec45a 737 break;
fa1c114f 738
8a63facc
BC		 739 mrr_rate[i] = rate->hw_value;
740 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 741 }
742
8a63facc
BC		 743 ath5k_hw_setup_mrr_tx_desc(ah, ds,
744 mrr_rate[0], mrr_tries[0],
745 mrr_rate[1], mrr_tries[1],
746 mrr_rate[2], mrr_tries[2]);
fa1c114f 747
8a63facc
BC		 748 ds->ds_link = 0;
749 ds->ds_data = bf->skbaddr;
63266a65 750
8a63facc
BC		 751 spin_lock_bh(&txq->lock);
752 list_add_tail(&bf->list, &txq->q);
925e0b06 753 txq->txq_len++;
8a63facc
BC		 754 if (txq->link == NULL) /* is this first packet? */
755 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
756 else /* no, so only link it */
757 *txq->link = bf->daddr;
63266a65 758
8a63facc
BC		 759 txq->link = &ds->ds_link;
760 ath5k_hw_start_tx_dma(ah, txq->qnum);
761 mmiowb();
762 spin_unlock_bh(&txq->lock);
763
764 return 0;
765err_unmap:
aeae4ac9 766 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 767 return ret;
63266a65
BR		 768}
769
8a63facc
BC		 770/*******************\
771* Descriptors setup *
772\*******************/
773
d8ee398d 774static int
aeae4ac9 775ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 776{
8a63facc
BC		 777 struct ath5k_desc *ds;
778 struct ath5k_buf *bf;
779 dma_addr_t da;
780 unsigned int i;
781 int ret;
d8ee398d 782
8a63facc
BC		 783 /* allocate descriptors */
784 sc->desc_len = sizeof(struct ath5k_desc) *
785 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 786
787 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
788 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 789 if (sc->desc == NULL) {
790 ATH5K_ERR(sc, "can't allocate descriptors\n");
791 ret = -ENOMEM;
792 goto err;
793 }
794 ds = sc->desc;
795 da = sc->desc_daddr;
796 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
797 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 798
8a63facc
BC		 799 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
800 sizeof(struct ath5k_buf), GFP_KERNEL);
801 if (bf == NULL) {
802 ATH5K_ERR(sc, "can't allocate bufptr\n");
803 ret = -ENOMEM;
804 goto err_free;
805 }
806 sc->bufptr = bf;
fa1c114f 807
8a63facc
BC		 808 INIT_LIST_HEAD(&sc->rxbuf);
809 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
810 bf->desc = ds;
811 bf->daddr = da;
812 list_add_tail(&bf->list, &sc->rxbuf);
813 }
d8ee398d 814
8a63facc
BC		 815 INIT_LIST_HEAD(&sc->txbuf);
816 sc->txbuf_len = ATH_TXBUF;
e4bbf2f5 817 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
8a63facc
BC		 818 bf->desc = ds;
819 bf->daddr = da;
820 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 821 }
822
b1ae1edf
BG		 823 /* beacon buffers */
824 INIT_LIST_HEAD(&sc->bcbuf);
825 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
826 bf->desc = ds;
827 bf->daddr = da;
828 list_add_tail(&bf->list, &sc->bcbuf);
829 }
fa1c114f 830
8a63facc
BC		 831 return 0;
832err_free:
aeae4ac9 833 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 834err:
835 sc->desc = NULL;
836 return ret;
837}
fa1c114f 838
cd2c5486
BR		 839void
840ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
841{
842 BUG_ON(!bf);
843 if (!bf->skb)
844 return;
845 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
846 DMA_TO_DEVICE);
847 dev_kfree_skb_any(bf->skb);
848 bf->skb = NULL;
849 bf->skbaddr = 0;
850 bf->desc->ds_data = 0;
851}
852
853void
854ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
855{
856 struct ath5k_hw *ah = sc->ah;
857 struct ath_common *common = ath5k_hw_common(ah);
858
859 BUG_ON(!bf);
860 if (!bf->skb)
861 return;
862 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
863 DMA_FROM_DEVICE);
864 dev_kfree_skb_any(bf->skb);
865 bf->skb = NULL;
866 bf->skbaddr = 0;
867 bf->desc->ds_data = 0;
868}
869
8a63facc 870static void
aeae4ac9 871ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 872{
873 struct ath5k_buf *bf;
d8ee398d 874
8a63facc
BC		 875 list_for_each_entry(bf, &sc->txbuf, list)
876 ath5k_txbuf_free_skb(sc, bf);
877 list_for_each_entry(bf, &sc->rxbuf, list)
878 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 879 list_for_each_entry(bf, &sc->bcbuf, list)
880 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 881
8a63facc 882 /* Free memory associated with all descriptors */
aeae4ac9 883 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 884 sc->desc = NULL;
885 sc->desc_daddr = 0;
d8ee398d 886
8a63facc
BC		 887 kfree(sc->bufptr);
888 sc->bufptr = NULL;
fa1c114f
JS		 889}
890
8a63facc
BC		 891
892/**************\
893* Queues setup *
894\**************/
895
896static struct ath5k_txq *
897ath5k_txq_setup(struct ath5k_softc *sc,
898 int qtype, int subtype)
fa1c114f 899{
8a63facc
BC		 900 struct ath5k_hw *ah = sc->ah;
901 struct ath5k_txq *txq;
902 struct ath5k_txq_info qi = {
903 .tqi_subtype = subtype,
de8af455
BR		 904 /* XXX: default values not correct for B and XR channels,
905 * but who cares? */
906 .tqi_aifs = AR5K_TUNE_AIFS,
907 .tqi_cw_min = AR5K_TUNE_CWMIN,
908 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 909 };
910 int qnum;
d8ee398d 911
e30eb4ab 912 /*
8a63facc
BC		 913 * Enable interrupts only for EOL and DESC conditions.
914 * We mark tx descriptors to receive a DESC interrupt
915 * when a tx queue gets deep; otherwise we wait for the
916 * EOL to reap descriptors. Note that this is done to
917 * reduce interrupt load and this only defers reaping
918 * descriptors, never transmitting frames. Aside from
919 * reducing interrupts this also permits more concurrency.
920 * The only potential downside is if the tx queue backs
921 * up in which case the top half of the kernel may backup
922 * due to a lack of tx descriptors.
e30eb4ab 923 */
8a63facc
BC		 924 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
925 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
926 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
927 if (qnum < 0) {
928 /*
929 * NB: don't print a message, this happens
930 * normally on parts with too few tx queues
931 */
932 return ERR_PTR(qnum);
933 }
934 if (qnum >= ARRAY_SIZE(sc->txqs)) {
935 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
936 qnum, ARRAY_SIZE(sc->txqs));
937 ath5k_hw_release_tx_queue(ah, qnum);
938 return ERR_PTR(-EINVAL);
939 }
940 txq = &sc->txqs[qnum];
941 if (!txq->setup) {
942 txq->qnum = qnum;
943 txq->link = NULL;
944 INIT_LIST_HEAD(&txq->q);
945 spin_lock_init(&txq->lock);
946 txq->setup = true;
925e0b06 947 txq->txq_len = 0;
81266baf 948 txq->txq_max = ATH5K_TXQ_LEN_MAX;
4edd761f 949 txq->txq_poll_mark = false;
923e5b3d 950 txq->txq_stuck = 0;
8a63facc
BC		 951 }
952 return &sc->txqs[qnum];
fa1c114f
JS		 953}
954
8a63facc
BC		 955static int
956ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 957{
8a63facc 958 struct ath5k_txq_info qi = {
de8af455
BR		 959 /* XXX: default values not correct for B and XR channels,
960 * but who cares? */
961 .tqi_aifs = AR5K_TUNE_AIFS,
962 .tqi_cw_min = AR5K_TUNE_CWMIN,
963 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 964 /* NB: for dynamic turbo, don't enable any other interrupts */
965 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
966 };
d8ee398d 967
8a63facc 968 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 969}
970
8a63facc
BC		 971static int
972ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 973{
974 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 975 struct ath5k_txq_info qi;
976 int ret;
fa1c114f 977
8a63facc
BC		 978 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
979 if (ret)
980 goto err;
fa1c114f 981
8a63facc 982 if (sc->opmode == NL80211_IFTYPE_AP ||
e4bbf2f5 983 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
8a63facc
BC		 984 /*
985 * Always burst out beacon and CAB traffic
986 * (aifs = cwmin = cwmax = 0)
987 */
988 qi.tqi_aifs = 0;
989 qi.tqi_cw_min = 0;
990 qi.tqi_cw_max = 0;
991 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
992 /*
993 * Adhoc mode; backoff between 0 and (2 * cw_min).
994 */
995 qi.tqi_aifs = 0;
996 qi.tqi_cw_min = 0;
de8af455 997 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 998 }
fa1c114f 999
8a63facc
BC		 1000 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1001 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1002 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1003
8a63facc
BC		 1004 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1005 if (ret) {
1006 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1007 "hardware queue!\n", __func__);
1008 goto err;
1009 }
1010 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1011 if (ret)
1012 goto err;
b7266047 1013
8a63facc
BC		 1014 /* reconfigure cabq with ready time to 80% of beacon_interval */
1015 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1016 if (ret)
1017 goto err;
b7266047 1018
8a63facc
BC		 1019 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1020 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1021 if (ret)
1022 goto err;
b7266047 1023
8a63facc
BC		 1024 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1025err:
1026 return ret;
d8ee398d
LR		 1027}
1028
80dac9ee
NK		 1029/**
1030 * ath5k_drain_tx_buffs - Empty tx buffers
1031 *
1032 * @sc The &struct ath5k_softc
1033 *
1034 * Empty tx buffers from all queues in preparation
1035 * of a reset or during shutdown.
1036 *
1037 * NB: this assumes output has been stopped and
1038 * we do not need to block ath5k_tx_tasklet
1039 */
8a63facc 1040static void
80dac9ee 1041ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1042{
80dac9ee 1043 struct ath5k_txq *txq;
8a63facc 1044 struct ath5k_buf *bf, *bf0;
80dac9ee 1045 int i;
b6ea0356 1046
80dac9ee
NK		 1047 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1048 if (sc->txqs[i].setup) {
1049 txq = &sc->txqs[i];
1050 spin_lock_bh(&txq->lock);
1051 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1052 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1053
80dac9ee 1054 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1055
80dac9ee
NK		 1056 spin_lock_bh(&sc->txbuflock);
1057 list_move_tail(&bf->list, &sc->txbuf);
1058 sc->txbuf_len++;
1059 txq->txq_len--;
1060 spin_unlock_bh(&sc->txbuflock);
8a63facc 1061 }
80dac9ee
NK		 1062 txq->link = NULL;
1063 txq->txq_poll_mark = false;
1064 spin_unlock_bh(&txq->lock);
1065 }
0452d4a5 1066 }
fa1c114f
JS		 1067}
1068
8a63facc
BC		 1069static void
1070ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1071{
8a63facc
BC		 1072 struct ath5k_txq *txq = sc->txqs;
1073 unsigned int i;
2ac2927a 1074
8a63facc
BC		 1075 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1076 if (txq->setup) {
1077 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1078 txq->setup = false;
1079 }
1080}
2ac2927a 1081
2ac2927a 1082
8a63facc
BC		 1083/*************\
1084* RX Handling *
1085\*************/
2ac2927a 1086
8a63facc
BC		 1087/*
1088 * Enable the receive h/w following a reset.
1089 */
fa1c114f 1090static int
8a63facc 1091ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1092{
1093 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1094 struct ath_common *common = ath5k_hw_common(ah);
1095 struct ath5k_buf *bf;
1096 int ret;
fa1c114f 1097
8a63facc 1098 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1099
8a63facc
BC		 1100 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1101 common->cachelsz, common->rx_bufsize);
2f7fe870 1102
8a63facc
BC		 1103 spin_lock_bh(&sc->rxbuflock);
1104 sc->rxlink = NULL;
1105 list_for_each_entry(bf, &sc->rxbuf, list) {
1106 ret = ath5k_rxbuf_setup(sc, bf);
1107 if (ret != 0) {
1108 spin_unlock_bh(&sc->rxbuflock);
1109 goto err;
1110 }
2f7fe870 1111 }
8a63facc
BC		 1112 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1113 ath5k_hw_set_rxdp(ah, bf->daddr);
1114 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1115
8a63facc 1116 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
e4b0b32a 1117 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */
8a63facc 1118 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1119
1120 return 0;
8a63facc 1121err:
fa1c114f
JS		 1122 return ret;
1123}
1124
8a63facc 1125/*
80dac9ee
NK		 1126 * Disable the receive logic on PCU (DRU)
1127 * In preparation for a shutdown.
1128 *
1129 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1130 * does.
8a63facc
BC		 1131 */
1132static void
1133ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1134{
8a63facc 1135 struct ath5k_hw *ah = sc->ah;
fa1c114f 1136
8a63facc 1137 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1138 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1139
8a63facc
BC		 1140 ath5k_debug_printrxbuffs(sc, ah);
1141}
fa1c114f 1142
8a63facc
BC		 1143static unsigned int
1144ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1145 struct ath5k_rx_status *rs)
1146{
1147 struct ath5k_hw *ah = sc->ah;
1148 struct ath_common *common = ath5k_hw_common(ah);
1149 struct ieee80211_hdr *hdr = (void *)skb->data;
1150 unsigned int keyix, hlen;
fa1c114f 1151
8a63facc
BC		 1152 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1153 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1154 return RX_FLAG_DECRYPTED;
fa1c114f 1155
8a63facc
BC		 1156 /* Apparently when a default key is used to decrypt the packet
1157 the hw does not set the index used to decrypt. In such cases
1158 get the index from the packet. */
1159 hlen = ieee80211_hdrlen(hdr->frame_control);
1160 if (ieee80211_has_protected(hdr->frame_control) &&
1161 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1162 skb->len >= hlen + 4) {
1163 keyix = skb->data[hlen + 3] >> 6;
1164
1165 if (test_bit(keyix, common->keymap))
1166 return RX_FLAG_DECRYPTED;
1167 }
fa1c114f
JS		 1168
1169 return 0;
fa1c114f
JS		 1170}
1171
8a63facc 1172
fa1c114f 1173static void
8a63facc
BC		 1174ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1175 struct ieee80211_rx_status *rxs)
fa1c114f 1176{
8a63facc
BC		 1177 struct ath_common *common = ath5k_hw_common(sc->ah);
1178 u64 tsf, bc_tstamp;
1179 u32 hw_tu;
1180 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1181
8a63facc
BC		 1182 if (ieee80211_is_beacon(mgmt->frame_control) &&
1183 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1184 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1185 /*
1186 * Received an IBSS beacon with the same BSSID. Hardware *must*
1187 * have updated the local TSF. We have to work around various
1188 * hardware bugs, though...
1189 */
1190 tsf = ath5k_hw_get_tsf64(sc->ah);
1191 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1192 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1193
8a63facc
BC		 1194 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1195 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1196 (unsigned long long)bc_tstamp,
1197 (unsigned long long)rxs->mactime,
1198 (unsigned long long)(rxs->mactime - bc_tstamp),
1199 (unsigned long long)tsf);
fa1c114f 1200
8a63facc
BC		 1201 /*
1202 * Sometimes the HW will give us a wrong tstamp in the rx
1203 * status, causing the timestamp extension to go wrong.
1204 * (This seems to happen especially with beacon frames bigger
1205 * than 78 byte (incl. FCS))
1206 * But we know that the receive timestamp must be later than the
1207 * timestamp of the beacon since HW must have synced to that.
1208 *
1209 * NOTE: here we assume mactime to be after the frame was
1210 * received, not like mac80211 which defines it at the start.
1211 */
1212 if (bc_tstamp > rxs->mactime) {
1213 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1214 "fixing mactime from %llx to %llx\n",
1215 (unsigned long long)rxs->mactime,
1216 (unsigned long long)tsf);
1217 rxs->mactime = tsf;
1218 }
fa1c114f 1219
8a63facc
BC		 1220 /*
1221 * Local TSF might have moved higher than our beacon timers,
1222 * in that case we have to update them to continue sending
1223 * beacons. This also takes care of synchronizing beacon sending
1224 * times with other stations.
1225 */
1226 if (hw_tu >= sc->nexttbtt)
1227 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1228
1229 /* Check if the beacon timers are still correct, because a TSF
1230 * update might have created a window between them - for a
1231 * longer description see the comment of this function: */
1232 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1233 ath5k_beacon_update_timers(sc, bc_tstamp);
1234 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1235 "fixed beacon timers after beacon receive\n");
1236 }
8a63facc
BC		 1237 }
1238}
fa1c114f 1239
8a63facc
BC		 1240static void
1241ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1242{
1243 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1244 struct ath5k_hw *ah = sc->ah;
1245 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1246
8a63facc
BC		 1247 /* only beacons from our BSSID */
1248 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1249 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1250 return;
fa1c114f 1251
eef39bef 1252 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1253
8a63facc
BC		 1254 /* in IBSS mode we should keep RSSI statistics per neighbour */
1255 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1256}
fa1c114f 1257
8a63facc
BC		 1258/*
1259 * Compute padding position. skb must contain an IEEE 802.11 frame
1260 */
1261static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1262{
e4bbf2f5 1263 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8a63facc
BC		 1264 __le16 frame_control = hdr->frame_control;
1265 int padpos = 24;
fa1c114f 1266
d2c7f773 1267 if (ieee80211_has_a4(frame_control))
8a63facc 1268 padpos += ETH_ALEN;
d2c7f773
PR		 1269
1270 if (ieee80211_is_data_qos(frame_control))
8a63facc 1271 padpos += IEEE80211_QOS_CTL_LEN;
8a63facc
BC		 1272
1273 return padpos;
fa1c114f
JS		 1274}
1275
8a63facc
BC		 1276/*
1277 * This function expects an 802.11 frame and returns the number of
1278 * bytes added, or -1 if we don't have enough header room.
1279 */
1280static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1281{
8a63facc
BC		 1282 int padpos = ath5k_common_padpos(skb);
1283 int padsize = padpos & 3;
fa1c114f 1284
e4bbf2f5 1285 if (padsize && skb->len > padpos) {
fa1c114f 1286
8a63facc
BC		 1287 if (skb_headroom(skb) < padsize)
1288 return -1;
fa1c114f 1289
8a63facc 1290 skb_push(skb, padsize);
e4bbf2f5 1291 memmove(skb->data, skb->data + padsize, padpos);
8a63facc
BC		 1292 return padsize;
1293 }
a951ae21 1294
8a63facc
BC		 1295 return 0;
1296}
fa1c114f 1297
8a63facc
BC		 1298/*
1299 * The MAC header is padded to have 32-bit boundary if the
1300 * packet payload is non-zero. The general calculation for
1301 * padsize would take into account odd header lengths:
1302 * padsize = 4 - (hdrlen & 3); however, since only
1303 * even-length headers are used, padding can only be 0 or 2
1304 * bytes and we can optimize this a bit. We must not try to
1305 * remove padding from short control frames that do not have a
1306 * payload.
1307 *
1308 * This function expects an 802.11 frame and returns the number of
1309 * bytes removed.
1310 */
1311static int ath5k_remove_padding(struct sk_buff *skb)
1312{
1313 int padpos = ath5k_common_padpos(skb);
1314 int padsize = padpos & 3;
6d91e1d8 1315
e4bbf2f5 1316 if (padsize && skb->len >= padpos + padsize) {
8a63facc
BC		 1317 memmove(skb->data + padsize, skb->data, padpos);
1318 skb_pull(skb, padsize);
1319 return padsize;
fa1c114f 1320 }
a951ae21 1321
8a63facc 1322 return 0;
fa1c114f
JS		 1323}
1324
1325static void
8a63facc
BC		 1326ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1327 struct ath5k_rx_status *rs)
fa1c114f 1328{
8a63facc
BC		 1329 struct ieee80211_rx_status *rxs;
1330
1331 ath5k_remove_padding(skb);
1332
1333 rxs = IEEE80211_SKB_RXCB(skb);
1334
1335 rxs->flag = 0;
1336 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1337 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1338
1339 /*
8a63facc
BC		 1340 * always extend the mac timestamp, since this information is
1341 * also needed for proper IBSS merging.
1342 *
1343 * XXX: it might be too late to do it here, since rs_tstamp is
1344 * 15bit only. that means TSF extension has to be done within
1345 * 32768usec (about 32ms). it might be necessary to move this to
1346 * the interrupt handler, like it is done in madwifi.
1347 *
1348 * Unfortunately we don't know when the hardware takes the rx
1349 * timestamp (beginning of phy frame, data frame, end of rx?).
1350 * The only thing we know is that it is hardware specific...
1351 * On AR5213 it seems the rx timestamp is at the end of the
6a2a0e73 1352 * frame, but I'm not sure.
8a63facc
BC		 1353 *
1354 * NOTE: mac80211 defines mactime at the beginning of the first
1355 * data symbol. Since we don't have any time references it's
1356 * impossible to comply to that. This affects IBSS merge only
1357 * right now, so it's not too bad...
fa1c114f 1358 */
8a63facc 1359 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
6ebacbb7 1360 rxs->flag |= RX_FLAG_MACTIME_MPDU;
fa1c114f 1361
8a63facc 1362 rxs->freq = sc->curchan->center_freq;
930a7622 1363 rxs->band = sc->curchan->band;
fa1c114f 1364
8a63facc 1365 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1366
8a63facc 1367 rxs->antenna = rs->rs_antenna;
fa1c114f 1368
8a63facc
BC		 1369 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1370 sc->stats.antenna_rx[rs->rs_antenna]++;
1371 else
1372 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1373
8a63facc
BC		 1374 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1375 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1376
8a63facc 1377 if (rxs->rate_idx >= 0 && rs->rs_rate ==
930a7622 1378 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1379 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1380
0e472252 1381 trace_ath5k_rx(sc, skb);
fa1c114f 1382
8a63facc 1383 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1384
8a63facc
BC		 1385 /* check beacons in IBSS mode */
1386 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1387 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1388
8a63facc
BC		 1389 ieee80211_rx(sc->hw, skb);
1390}
fa1c114f 1391
8a63facc
BC		 1392/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1393 *
1394 * Check if we want to further process this frame or not. Also update
1395 * statistics. Return true if we want this frame, false if not.
fa1c114f 1396 */
8a63facc
BC		 1397static bool
1398ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1399{
8a63facc 1400 sc->stats.rx_all_count++;
b72acddb 1401 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1402
8a63facc
BC		 1403 if (unlikely(rs->rs_status)) {
1404 if (rs->rs_status & AR5K_RXERR_CRC)
1405 sc->stats.rxerr_crc++;
1406 if (rs->rs_status & AR5K_RXERR_FIFO)
1407 sc->stats.rxerr_fifo++;
1408 if (rs->rs_status & AR5K_RXERR_PHY) {
1409 sc->stats.rxerr_phy++;
1410 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1411 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1412 return false;
1413 }
1414 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1415 /*
1416 * Decrypt error. If the error occurred
1417 * because there was no hardware key, then
1418 * let the frame through so the upper layers
1419 * can process it. This is necessary for 5210
1420 * parts which have no way to setup a ``clear''
1421 * key cache entry.
1422 *
1423 * XXX do key cache faulting
1424 */
1425 sc->stats.rxerr_decrypt++;
1426 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1427 !(rs->rs_status & AR5K_RXERR_CRC))
1428 return true;
1429 }
1430 if (rs->rs_status & AR5K_RXERR_MIC) {
1431 sc->stats.rxerr_mic++;
1432 return true;
fa1c114f 1433 }
fa1c114f 1434
8a63facc
BC		 1435 /* reject any frames with non-crypto errors */
1436 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1437 return false;
1438 }
fa1c114f 1439
8a63facc
BC		 1440 if (unlikely(rs->rs_more)) {
1441 sc->stats.rxerr_jumbo++;
1442 return false;
1443 }
1444 return true;
fa1c114f
JS		 1445}
1446
c266c71a
FF		 1447static void
1448ath5k_set_current_imask(struct ath5k_softc *sc)
1449{
4fc5401c 1450 enum ath5k_int imask;
c266c71a
FF		 1451 unsigned long flags;
1452
1453 spin_lock_irqsave(&sc->irqlock, flags);
4fc5401c 1454 imask = sc->imask;
c266c71a
FF		 1455 if (sc->rx_pending)
1456 imask &= ~AR5K_INT_RX_ALL;
1457 if (sc->tx_pending)
1458 imask &= ~AR5K_INT_TX_ALL;
1459 ath5k_hw_set_imr(sc->ah, imask);
1460 spin_unlock_irqrestore(&sc->irqlock, flags);
1461}
1462
fa1c114f 1463static void
8a63facc 1464ath5k_tasklet_rx(unsigned long data)
fa1c114f 1465{
8a63facc
BC		 1466 struct ath5k_rx_status rs = {};
1467 struct sk_buff *skb, *next_skb;
1468 dma_addr_t next_skb_addr;
1469 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1470 struct ath5k_hw *ah = sc->ah;
1471 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1472 struct ath5k_buf *bf;
1473 struct ath5k_desc *ds;
1474 int ret;
fa1c114f 1475
8a63facc
BC		 1476 spin_lock(&sc->rxbuflock);
1477 if (list_empty(&sc->rxbuf)) {
1478 ATH5K_WARN(sc, "empty rx buf pool\n");
1479 goto unlock;
1480 }
1481 do {
1482 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1483 BUG_ON(bf->skb == NULL);
1484 skb = bf->skb;
1485 ds = bf->desc;
fa1c114f 1486
8a63facc
BC		 1487 /* bail if HW is still using self-linked descriptor */
1488 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1489 break;
fa1c114f 1490
8a63facc
BC		 1491 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1492 if (unlikely(ret == -EINPROGRESS))
1493 break;
1494 else if (unlikely(ret)) {
1495 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1496 sc->stats.rxerr_proc++;
1497 break;
1498 }
fa1c114f 1499
8a63facc
BC		 1500 if (ath5k_receive_frame_ok(sc, &rs)) {
1501 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1502
8a63facc
BC		 1503 /*
1504 * If we can't replace bf->skb with a new skb under
1505 * memory pressure, just skip this packet
1506 */
1507 if (!next_skb)
1508 goto next;
036cd1ec 1509
aeae4ac9 1510 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1511 common->rx_bufsize,
aeae4ac9 1512 DMA_FROM_DEVICE);
036cd1ec 1513
8a63facc 1514 skb_put(skb, rs.rs_datalen);
6ba81c2c 1515
8a63facc 1516 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1517
8a63facc
BC		 1518 bf->skb = next_skb;
1519 bf->skbaddr = next_skb_addr;
036cd1ec 1520 }
8a63facc
BC		 1521next:
1522 list_move_tail(&bf->list, &sc->rxbuf);
1523 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1524unlock:
1525 spin_unlock(&sc->rxbuflock);
c266c71a
FF		 1526 sc->rx_pending = false;
1527 ath5k_set_current_imask(sc);
036cd1ec
BR		 1528}
1529
b4ea449d 1530
8a63facc
BC		 1531/*************\
1532* TX Handling *
1533\*************/
b4ea449d 1534
7bb45683 1535void
cd2c5486
BR		 1536ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1537 struct ath5k_txq *txq)
8a63facc
BC		 1538{
1539 struct ath5k_softc *sc = hw->priv;
1540 struct ath5k_buf *bf;
1541 unsigned long flags;
1542 int padsize;
b4ea449d 1543
0e472252 1544 trace_ath5k_tx(sc, skb, txq);
b4ea449d 1545
8a63facc
BC		 1546 /*
1547 * The hardware expects the header padded to 4 byte boundaries.
1548 * If this is not the case, we add the padding after the header.
1549 */
1550 padsize = ath5k_add_padding(skb);
1551 if (padsize < 0) {
1552 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1553 " headroom to pad");
1554 goto drop_packet;
1555 }
8127fbdc 1556
81266baf 1557 if (txq->txq_len >= txq->txq_max)
925e0b06
BR		 1558 ieee80211_stop_queue(hw, txq->qnum);
1559
8a63facc
BC		 1560 spin_lock_irqsave(&sc->txbuflock, flags);
1561 if (list_empty(&sc->txbuf)) {
1562 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1563 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1564 ieee80211_stop_queues(hw);
8a63facc 1565 goto drop_packet;
8127fbdc 1566 }
8a63facc
BC		 1567 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1568 list_del(&bf->list);
1569 sc->txbuf_len--;
1570 if (list_empty(&sc->txbuf))
1571 ieee80211_stop_queues(hw);
1572 spin_unlock_irqrestore(&sc->txbuflock, flags);
1573
1574 bf->skb = skb;
1575
1576 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1577 bf->skb = NULL;
1578 spin_lock_irqsave(&sc->txbuflock, flags);
1579 list_add_tail(&bf->list, &sc->txbuf);
1580 sc->txbuf_len++;
1581 spin_unlock_irqrestore(&sc->txbuflock, flags);
1582 goto drop_packet;
8127fbdc 1583 }
7bb45683 1584 return;
8127fbdc 1585
8a63facc
BC		 1586drop_packet:
1587 dev_kfree_skb_any(skb);
8127fbdc
BP		 1588}
1589
1440401e
BR		 1590static void
1591ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
0e472252 1592 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1440401e
BR		 1593{
1594 struct ieee80211_tx_info *info;
ed895085 1595 u8 tries[3];
1440401e
BR		 1596 int i;
1597
1598 sc->stats.tx_all_count++;
b72acddb 1599 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1600 info = IEEE80211_SKB_CB(skb);
1601
ed895085
FF		 1602 tries[0] = info->status.rates[0].count;
1603 tries[1] = info->status.rates[1].count;
1604 tries[2] = info->status.rates[2].count;
1605
1440401e 1606 ieee80211_tx_info_clear_status(info);
ed895085
FF		 1607
1608 for (i = 0; i < ts->ts_final_idx; i++) {
1440401e
BR		 1609 struct ieee80211_tx_rate *r =
1610 &info->status.rates[i];
1611
ed895085 1612 r->count = tries[i];
1440401e
BR		 1613 }
1614
ed895085 1615 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
6d7b97b2 1616 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1440401e
BR		 1617
1618 if (unlikely(ts->ts_status)) {
1619 sc->stats.ack_fail++;
1620 if (ts->ts_status & AR5K_TXERR_FILT) {
1621 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1622 sc->stats.txerr_filt++;
1623 }
1624 if (ts->ts_status & AR5K_TXERR_XRETRY)
1625 sc->stats.txerr_retry++;
1626 if (ts->ts_status & AR5K_TXERR_FIFO)
1627 sc->stats.txerr_fifo++;
1628 } else {
1629 info->flags |= IEEE80211_TX_STAT_ACK;
1630 info->status.ack_signal = ts->ts_rssi;
6d7b97b2
FF		 1631
1632 /* count the successful attempt as well */
1633 info->status.rates[ts->ts_final_idx].count++;
1440401e
BR		 1634 }
1635
1636 /*
1637 * Remove MAC header padding before giving the frame
1638 * back to mac80211.
1639 */
1640 ath5k_remove_padding(skb);
1641
1642 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1643 sc->stats.antenna_tx[ts->ts_antenna]++;
1644 else
1645 sc->stats.antenna_tx[0]++; /* invalid */
1646
0e472252 1647 trace_ath5k_tx_complete(sc, skb, txq, ts);
1440401e
BR		 1648 ieee80211_tx_status(sc->hw, skb);
1649}
8a63facc
BC		 1650
1651static void
1652ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1653{
8a63facc
BC		 1654 struct ath5k_tx_status ts = {};
1655 struct ath5k_buf *bf, *bf0;
1656 struct ath5k_desc *ds;
1657 struct sk_buff *skb;
1440401e 1658 int ret;
8127fbdc 1659
8a63facc
BC		 1660 spin_lock(&txq->lock);
1661 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1662
1663 txq->txq_poll_mark = false;
1664
1665 /* skb might already have been processed last time. */
1666 if (bf->skb != NULL) {
1667 ds = bf->desc;
1668
1669 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1670 if (unlikely(ret == -EINPROGRESS))
1671 break;
1672 else if (unlikely(ret)) {
1673 ATH5K_ERR(sc,
1674 "error %d while processing "
1675 "queue %u\n", ret, txq->qnum);
1676 break;
1677 }
1678
1679 skb = bf->skb;
1680 bf->skb = NULL;
aeae4ac9
FF		 1681
1682 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1683 DMA_TO_DEVICE);
0e472252 1684 ath5k_tx_frame_completed(sc, skb, txq, &ts);
23413296 1685 }
8127fbdc 1686
8a63facc
BC		 1687 /*
1688 * It's possible that the hardware can say the buffer is
1689 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1690 * host memory and moved on.
1691 * Always keep the last descriptor to avoid HW races...
8a63facc 1692 */
23413296
BR		 1693 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1694 spin_lock(&sc->txbuflock);
1695 list_move_tail(&bf->list, &sc->txbuf);
1696 sc->txbuf_len++;
1697 txq->txq_len--;
1698 spin_unlock(&sc->txbuflock);
8a63facc 1699 }
fa1c114f 1700 }
fa1c114f 1701 spin_unlock(&txq->lock);
4198a8d0 1702 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1703 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1704}
1705
1706static void
1707ath5k_tasklet_tx(unsigned long data)
1708{
8784d2ee 1709 int i;
fa1c114f
JS		 1710 struct ath5k_softc *sc = (void *)data;
1711
e4bbf2f5 1712 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
8784d2ee
BC		 1713 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1714 ath5k_tx_processq(sc, &sc->txqs[i]);
c266c71a
FF		 1715
1716 sc->tx_pending = false;
1717 ath5k_set_current_imask(sc);
fa1c114f
JS		 1718}
1719
1720
fa1c114f
JS		 1721/*****************\
1722* Beacon handling *
1723\*****************/
1724
1725/*
1726 * Setup the beacon frame for transmit.
1727 */
1728static int
e039fa4a 1729ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1730{
1731 struct sk_buff *skb = bf->skb;
a888d52d 1732 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1733 struct ath5k_hw *ah = sc->ah;
1734 struct ath5k_desc *ds;
2bed03eb
NK		 1735 int ret = 0;
1736 u8 antenna;
fa1c114f 1737 u32 flags;
8127fbdc 1738 const int padsize = 0;
fa1c114f 1739
aeae4ac9
FF		 1740 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1741 DMA_TO_DEVICE);
fa1c114f
JS		 1742 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1743 "skbaddr %llx\n", skb, skb->data, skb->len,
1744 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1745
1746 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1747 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1748 return -EIO;
1749 }
1750
1751 ds = bf->desc;
2bed03eb 1752 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1753
1754 flags = AR5K_TXDESC_NOACK;
05c914fe 1755 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1756 ds->ds_link = bf->daddr; /* self-linked */
1757 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1758 } else
fa1c114f 1759 ds->ds_link = 0;
2bed03eb
NK		 1760
1761 /*
1762 * If we use multiple antennas on AP and use
1763 * the Sectored AP scenario, switch antenna every
1764 * 4 beacons to make sure everybody hears our AP.
1765 * When a client tries to associate, hw will keep
1766 * track of the tx antenna to be used for this client
6a2a0e73 1767 * automatically, based on ACKed packets.
2bed03eb
NK		 1768 *
1769 * Note: AP still listens and transmits RTS on the
1770 * default antenna which is supposed to be an omni.
1771 *
1772 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1773 * multiple antennas (1 omni -- the default -- and 14
1774 * sectors), so if we choose to actually support this
1775 * mode, we need to allow the user to set how many antennas
1776 * we have and tweak the code below to send beacons
1777 * on all of them.
2bed03eb
NK		 1778 */
1779 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1780 antenna = sc->bsent & 4 ? 2 : 1;
1781
fa1c114f 1782
8f655dde
NK		 1783 /* FIXME: If we are in g mode and rate is a CCK rate
1784 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1785 * from tx power (value is in dB units already) */
fa1c114f 1786 ds->ds_data = bf->skbaddr;
281c56dd 1787 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1788 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1789 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1790 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1791 1, AR5K_TXKEYIX_INVALID,
400ec45a 1792 antenna, flags, 0, 0);
fa1c114f
JS		 1793 if (ret)
1794 goto err_unmap;
1795
1796 return 0;
1797err_unmap:
aeae4ac9 1798 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1799 return ret;
1800}
1801
8a63facc
BC		 1802/*
1803 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1804 * this is called only once at config_bss time, for AP we do it every
1805 * SWBA interrupt so that the TIM will reflect buffered frames.
1806 *
1807 * Called with the beacon lock.
1808 */
cd2c5486 1809int
8a63facc
BC		 1810ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1811{
1812 int ret;
1813 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1814 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1815 struct sk_buff *skb;
1816
1817 if (WARN_ON(!vif)) {
1818 ret = -EINVAL;
1819 goto out;
1820 }
1821
1822 skb = ieee80211_beacon_get(hw, vif);
1823
1824 if (!skb) {
1825 ret = -ENOMEM;
1826 goto out;
1827 }
1828
b1ae1edf
BG		 1829 ath5k_txbuf_free_skb(sc, avf->bbuf);
1830 avf->bbuf->skb = skb;
1831 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1832 if (ret)
b1ae1edf 1833 avf->bbuf->skb = NULL;
8a63facc
BC		 1834out:
1835 return ret;
1836}
1837
fa1c114f
JS		 1838/*
1839 * Transmit a beacon frame at SWBA. Dynamic updates to the
1840 * frame contents are done as needed and the slot time is
1841 * also adjusted based on current state.
1842 *
5faaff74
BC		 1843 * This is called from software irq context (beacontq tasklets)
1844 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1845 */
1846static void
1847ath5k_beacon_send(struct ath5k_softc *sc)
1848{
fa1c114f 1849 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1850 struct ieee80211_vif *vif;
1851 struct ath5k_vif *avf;
1852 struct ath5k_buf *bf;
cec8db23 1853 struct sk_buff *skb;
fa1c114f 1854
be9b7259 1855 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1856
fa1c114f
JS		 1857 /*
1858 * Check if the previous beacon has gone out. If
a180a130 1859 * not, don't don't try to post another: skip this
fa1c114f
JS		 1860 * period and wait for the next. Missed beacons
1861 * indicate a problem and should not occur. If we
1862 * miss too many consecutive beacons reset the device.
1863 */
1864 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1865 sc->bmisscount++;
be9b7259 1866 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1867 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1868 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1869 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1870 "stuck beacon time (%u missed)\n",
1871 sc->bmisscount);
8d67a031
BR		 1872 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1873 "stuck beacon, resetting\n");
5faaff74 1874 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1875 }
1876 return;
1877 }
1878 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1879 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1880 "resume beacon xmit after %u misses\n",
1881 sc->bmisscount);
1882 sc->bmisscount = 0;
1883 }
1884
b93996cf
JC		 1885 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1886 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1887 u64 tsf = ath5k_hw_get_tsf64(ah);
1888 u32 tsftu = TSF_TO_TU(tsf);
1889 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1890 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1891 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1892 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1893 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1894 } else /* only one interface */
1895 vif = sc->bslot[0];
1896
1897 if (!vif)
1898 return;
1899
1900 avf = (void *)vif->drv_priv;
1901 bf = avf->bbuf;
1902 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
e4bbf2f5 1903 sc->opmode == NL80211_IFTYPE_MONITOR)) {
b1ae1edf
BG		 1904 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1905 return;
1906 }
1907
fa1c114f
JS		 1908 /*
1909 * Stop any current dma and put the new frame on the queue.
1910 * This should never fail since we check above that no frames
1911 * are still pending on the queue.
1912 */
14fae2d4 1913 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1914 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1915 /* NB: hw still stops DMA, so proceed */
1916 }
fa1c114f 1917
d82b577b
JC		 1918 /* refresh the beacon for AP or MESH mode */
1919 if (sc->opmode == NL80211_IFTYPE_AP ||
e4bbf2f5 1920 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1921 ath5k_beacon_update(sc->hw, vif);
1071db86 1922
0e472252
BC		 1923 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
1924
c6e387a2
NK		 1925 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1926 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1927 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1928 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1929
b1ae1edf 1930 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1931 while (skb) {
1932 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1933 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1934 }
1935
fa1c114f
JS		 1936 sc->bsent++;
1937}
1938
9804b98d
BR		 1939/**
1940 * ath5k_beacon_update_timers - update beacon timers
1941 *
1942 * @sc: struct ath5k_softc pointer we are operating on
1943 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1944 * beacon timer update based on the current HW TSF.
1945 *
1946 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1947 * of a received beacon or the current local hardware TSF and write it to the
1948 * beacon timer registers.
1949 *
1950 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1951 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1952 * when we otherwise know we have to update the timers, but we keep it in this
1953 * function to have it all together in one place.
1954 */
cd2c5486 1955void
9804b98d 1956ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1957{
1958 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1959 u32 nexttbtt, intval, hw_tu, bc_tu;
1960 u64 hw_tsf;
fa1c114f
JS		 1961
1962 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1963 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1964 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1965 if (intval < 15)
1966 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1967 intval);
1968 }
fa1c114f
JS		 1969 if (WARN_ON(!intval))
1970 return;
1971
9804b98d
BR		 1972 /* beacon TSF converted to TU */
1973 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1974
9804b98d
BR		 1975 /* current TSF converted to TU */
1976 hw_tsf = ath5k_hw_get_tsf64(ah);
1977 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1978
633d006e 1979#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
11f21df3 1980 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
25985edc 1981 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
11f21df3
BR		 1982 * configuration we need to make sure it is bigger than that. */
1983
9804b98d
BR		 1984 if (bc_tsf == -1) {
1985 /*
1986 * no beacons received, called internally.
1987 * just need to refresh timers based on HW TSF.
1988 */
1989 nexttbtt = roundup(hw_tu + FUDGE, intval);
1990 } else if (bc_tsf == 0) {
1991 /*
1992 * no beacon received, probably called by ath5k_reset_tsf().
1993 * reset TSF to start with 0.
1994 */
1995 nexttbtt = intval;
1996 intval |= AR5K_BEACON_RESET_TSF;
1997 } else if (bc_tsf > hw_tsf) {
1998 /*
25985edc 1999 * beacon received, SW merge happened but HW TSF not yet updated.
9804b98d
BR		 2000 * not possible to reconfigure timers yet, but next time we
2001 * receive a beacon with the same BSSID, the hardware will
2002 * automatically update the TSF and then we need to reconfigure
2003 * the timers.
2004 */
2005 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2006 "need to wait for HW TSF sync\n");
2007 return;
2008 } else {
2009 /*
2010 * most important case for beacon synchronization between STA.
2011 *
2012 * beacon received and HW TSF has been already updated by HW.
2013 * update next TBTT based on the TSF of the beacon, but make
2014 * sure it is ahead of our local TSF timer.
2015 */
2016 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2017 }
2018#undef FUDGE
fa1c114f 2019
036cd1ec
BR		 2020 sc->nexttbtt = nexttbtt;
2021
fa1c114f 2022 intval |= AR5K_BEACON_ENA;
fa1c114f 2023 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2024
2025 /*
2026 * debugging output last in order to preserve the time critical aspect
2027 * of this function
2028 */
2029 if (bc_tsf == -1)
2030 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2031 "reconfigured timers based on HW TSF\n");
2032 else if (bc_tsf == 0)
2033 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2034 "reset HW TSF and timers\n");
2035 else
2036 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2037 "updated timers based on beacon TSF\n");
2038
2039 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2040 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2041 (unsigned long long) bc_tsf,
2042 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2043 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2044 intval & AR5K_BEACON_PERIOD,
2045 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2046 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2047}
2048
036cd1ec
BR		 2049/**
2050 * ath5k_beacon_config - Configure the beacon queues and interrupts
2051 *
2052 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2053 *
036cd1ec 2054 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2055 * interrupts to detect TSF updates only.
fa1c114f 2056 */
cd2c5486 2057void
fa1c114f
JS		 2058ath5k_beacon_config(struct ath5k_softc *sc)
2059{
2060 struct ath5k_hw *ah = sc->ah;
b5f03956 2061 unsigned long flags;
fa1c114f 2062
21800491 2063 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2064 sc->bmisscount = 0;
dc1968e7 2065 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2066
21800491 2067 if (sc->enable_beacon) {
fa1c114f 2068 /*
036cd1ec
BR		 2069 * In IBSS mode we use a self-linked tx descriptor and let the
2070 * hardware send the beacons automatically. We have to load it
fa1c114f 2071 * only once here.
036cd1ec 2072 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2073 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2074 */
2075 ath5k_beaconq_config(sc);
fa1c114f 2076
036cd1ec
BR		 2077 sc->imask |= AR5K_INT_SWBA;
2078
da966bca 2079 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2080 if (ath5k_hw_hasveol(ah))
da966bca 2081 ath5k_beacon_send(sc);
da966bca
JS		 2082 } else
2083 ath5k_beacon_update_timers(sc, -1);
21800491 2084 } else {
14fae2d4 2085 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2086 }
fa1c114f 2087
c6e387a2 2088 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2089 mmiowb();
2090 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2091}
2092
428cbd4f
NK		 2093static void ath5k_tasklet_beacon(unsigned long data)
2094{
2095 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2096
2097 /*
2098 * Software beacon alert--time to send a beacon.
2099 *
2100 * In IBSS mode we use this interrupt just to
2101 * keep track of the next TBTT (target beacon
6a2a0e73 2102 * transmission time) in order to detect whether
428cbd4f
NK		 2103 * automatic TSF updates happened.
2104 */
2105 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6a2a0e73 2106 /* XXX: only if VEOL supported */
428cbd4f
NK		 2107 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2108 sc->nexttbtt += sc->bintval;
2109 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2110 "SWBA nexttbtt: %x hw_tu: %x "
2111 "TSF: %llx\n",
2112 sc->nexttbtt,
2113 TSF_TO_TU(tsf),
2114 (unsigned long long) tsf);
2115 } else {
2116 spin_lock(&sc->block);
2117 ath5k_beacon_send(sc);
2118 spin_unlock(&sc->block);
2119 }
2120}
2121
fa1c114f
JS		 2122
2123/********************\
2124* Interrupt handling *
2125\********************/
2126
6a8a3f6b
BR		 2127static void
2128ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2129{
2111ac0d
BR		 2130 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2131 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2132 /* run ANI only when full calibration is not active */
2133 ah->ah_cal_next_ani = jiffies +
2134 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2135 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2136
2137 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2138 ah->ah_cal_next_full = jiffies +
2139 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2140 tasklet_schedule(&ah->ah_sc->calib);
2141 }
2142 /* we could use SWI to generate enough interrupts to meet our
2143 * calibration interval requirements, if necessary:
2144 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2145}
2146
c266c71a
FF		 2147static void
2148ath5k_schedule_rx(struct ath5k_softc *sc)
2149{
2150 sc->rx_pending = true;
2151 tasklet_schedule(&sc->rxtq);
2152}
2153
2154static void
2155ath5k_schedule_tx(struct ath5k_softc *sc)
2156{
2157 sc->tx_pending = true;
2158 tasklet_schedule(&sc->txtq);
2159}
2160
f5cbc8ba 2161static irqreturn_t
fa1c114f
JS		 2162ath5k_intr(int irq, void *dev_id)
2163{
2164 struct ath5k_softc *sc = dev_id;
2165 struct ath5k_hw *ah = sc->ah;
2166 enum ath5k_int status;
2167 unsigned int counter = 1000;
2168
2169 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2170 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2171 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2172 return IRQ_NONE;
2173
2174 do {
fa1c114f
JS		 2175 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2176 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2177 status, sc->imask);
fa1c114f
JS		 2178 if (unlikely(status & AR5K_INT_FATAL)) {
2179 /*
2180 * Fatal errors are unrecoverable.
2181 * Typically these are caused by DMA errors.
2182 */
8d67a031
BR		 2183 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2184 "fatal int, resetting\n");
5faaff74 2185 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2186 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2187 /*
2188 * Receive buffers are full. Either the bus is busy or
2189 * the CPU is not fast enough to process all received
2190 * frames.
2191 * Older chipsets need a reset to come out of this
2192 * condition, but we treat it as RX for newer chips.
2193 * We don't know exactly which versions need a reset -
2194 * this guess is copied from the HAL.
2195 */
2196 sc->stats.rxorn_intr++;
8d67a031
BR		 2197 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2198 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2199 "rx overrun, resetting\n");
5faaff74 2200 ieee80211_queue_work(sc->hw, &sc->reset_work);
d2c7f773 2201 } else
c266c71a 2202 ath5k_schedule_rx(sc);
fa1c114f 2203 } else {
d2c7f773 2204 if (status & AR5K_INT_SWBA)
56d2ac76 2205 tasklet_hi_schedule(&sc->beacontq);
d2c7f773 2206
fa1c114f
JS		 2207 if (status & AR5K_INT_RXEOL) {
2208 /*
2209 * NB: the hardware should re-read the link when
2210 * RXE bit is written, but it doesn't work at
2211 * least on older hardware revs.
2212 */
b3f194e5 2213 sc->stats.rxeol_intr++;
fa1c114f
JS		 2214 }
2215 if (status & AR5K_INT_TXURN) {
2216 /* bump tx trigger level */
2217 ath5k_hw_update_tx_triglevel(ah, true);
2218 }
4c674c60 2219 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
c266c71a 2220 ath5k_schedule_rx(sc);
4c674c60
NK		 2221 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2222 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
c266c71a 2223 ath5k_schedule_tx(sc);
fa1c114f 2224 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2225 /* TODO */
fa1c114f
JS		 2226 }
2227 if (status & AR5K_INT_MIB) {
2111ac0d 2228 sc->stats.mib_intr++;
495391d7 2229 ath5k_hw_update_mib_counters(ah);
2111ac0d 2230 ath5k_ani_mib_intr(ah);
fa1c114f 2231 }
e6a3b616 2232 if (status & AR5K_INT_GPIO)
e6a3b616 2233 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2234
fa1c114f 2235 }
4cebb34c
FF		 2236
2237 if (ath5k_get_bus_type(ah) == ATH_AHB)
2238 break;
2239
2516baa6 2240 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f 2241
c266c71a
FF		 2242 if (sc->rx_pending || sc->tx_pending)
2243 ath5k_set_current_imask(sc);
2244
fa1c114f
JS		 2245 if (unlikely(!counter))
2246 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2247
6a8a3f6b 2248 ath5k_intr_calibration_poll(ah);
6e220662 2249
fa1c114f
JS		 2250 return IRQ_HANDLED;
2251}
2252
fa1c114f
JS		 2253/*
2254 * Periodically recalibrate the PHY to account
2255 * for temperature/environment changes.
2256 */
2257static void
6e220662 2258ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2259{
2260 struct ath5k_softc *sc = (void *)data;
2261 struct ath5k_hw *ah = sc->ah;
2262
6e220662 2263 /* Only full calibration for now */
e65e1d77 2264 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2265
fa1c114f 2266 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2267 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2268 sc->curchan->hw_value);
fa1c114f 2269
6f3b414a 2270 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2271 /*
2272 * Rfgain is out of bounds, reset the chip
2273 * to load new gain values.
2274 */
2275 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2276 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2277 }
2278 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2279 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2280 ieee80211_frequency_to_channel(
2281 sc->curchan->center_freq));
fa1c114f 2282
0e8e02dd 2283 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2284 * doesn't.
2285 * TODO: We should stop TX here, so that it doesn't interfere.
2286 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2287 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2288 ah->ah_cal_next_nf = jiffies +
2289 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2290 ath5k_hw_update_noise_floor(ah);
afe86286 2291 }
6e220662 2292
e65e1d77 2293 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2294}
2295
2296
2111ac0d
BR		 2297static void
2298ath5k_tasklet_ani(unsigned long data)
2299{
2300 struct ath5k_softc *sc = (void *)data;
2301 struct ath5k_hw *ah = sc->ah;
2302
2303 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2304 ath5k_ani_calibration(ah);
2305 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2306}
2307
2308
4edd761f
BR		 2309static void
2310ath5k_tx_complete_poll_work(struct work_struct *work)
2311{
2312 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2313 tx_complete_work.work);
2314 struct ath5k_txq *txq;
2315 int i;
2316 bool needreset = false;
2317
599b13ad
BC		 2318 mutex_lock(&sc->lock);
2319
4edd761f
BR		 2320 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2321 if (sc->txqs[i].setup) {
2322 txq = &sc->txqs[i];
2323 spin_lock_bh(&txq->lock);
23413296 2324 if (txq->txq_len > 1) {
4edd761f
BR		 2325 if (txq->txq_poll_mark) {
2326 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2327 "TX queue stuck %d\n",
2328 txq->qnum);
2329 needreset = true;
923e5b3d 2330 txq->txq_stuck++;
4edd761f
BR		 2331 spin_unlock_bh(&txq->lock);
2332 break;
2333 } else {
2334 txq->txq_poll_mark = true;
2335 }
2336 }
2337 spin_unlock_bh(&txq->lock);
2338 }
2339 }
2340
2341 if (needreset) {
2342 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2343 "TX queues stuck, resetting\n");
8aec7af9 2344 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2345 }
2346
599b13ad
BC		 2347 mutex_unlock(&sc->lock);
2348
4edd761f
BR		 2349 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2350 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2351}
2352
2353
8a63facc
BC		 2354/*************************\
2355* Initialization routines *
2356\*************************/
fa1c114f 2357
25380d80 2358int __devinit
132b1c3e
FF		 2359ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2360{
2361 struct ieee80211_hw *hw = sc->hw;
2362 struct ath_common *common;
2363 int ret;
2364 int csz;
2365
2366 /* Initialize driver private data */
2367 SET_IEEE80211_DEV(hw, sc->dev);
2368 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2369 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2370 IEEE80211_HW_SIGNAL_DBM |
2371 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2372
2373 hw->wiphy->interface_modes =
2374 BIT(NL80211_IFTYPE_AP) |
2375 BIT(NL80211_IFTYPE_STATION) |
2376 BIT(NL80211_IFTYPE_ADHOC) |
2377 BIT(NL80211_IFTYPE_MESH_POINT);
2378
3de135db
BR		 2379 /* both antennas can be configured as RX or TX */
2380 hw->wiphy->available_antennas_tx = 0x3;
2381 hw->wiphy->available_antennas_rx = 0x3;
2382
132b1c3e
FF		 2383 hw->extra_tx_headroom = 2;
2384 hw->channel_change_time = 5000;
2385
2386 /*
2387 * Mark the device as detached to avoid processing
2388 * interrupts until setup is complete.
2389 */
2390 __set_bit(ATH_STAT_INVALID, sc->status);
2391
2392 sc->opmode = NL80211_IFTYPE_STATION;
2393 sc->bintval = 1000;
2394 mutex_init(&sc->lock);
2395 spin_lock_init(&sc->rxbuflock);
2396 spin_lock_init(&sc->txbuflock);
2397 spin_lock_init(&sc->block);
d381f221 2398 spin_lock_init(&sc->irqlock);
132b1c3e
FF		 2399
2400 /* Setup interrupt handler */
2401 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2402 if (ret) {
2403 ATH5K_ERR(sc, "request_irq failed\n");
2404 goto err;
2405 }
2406
2407 /* If we passed the test, malloc an ath5k_hw struct */
2408 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2409 if (!sc->ah) {
2410 ret = -ENOMEM;
2411 ATH5K_ERR(sc, "out of memory\n");
2412 goto err_irq;
2413 }
2414
2415 sc->ah->ah_sc = sc;
2416 sc->ah->ah_iobase = sc->iobase;
2417 common = ath5k_hw_common(sc->ah);
2418 common->ops = &ath5k_common_ops;
2419 common->bus_ops = bus_ops;
2420 common->ah = sc->ah;
2421 common->hw = hw;
2422 common->priv = sc;
2423
2424 /*
2425 * Cache line size is used to size and align various
2426 * structures used to communicate with the hardware.
2427 */
2428 ath5k_read_cachesize(common, &csz);
2429 common->cachelsz = csz << 2; /* convert to bytes */
2430
2431 spin_lock_init(&common->cc_lock);
2432
2433 /* Initialize device */
2434 ret = ath5k_hw_init(sc);
2435 if (ret)
2436 goto err_free_ah;
2437
2438 /* set up multi-rate retry capabilities */
2439 if (sc->ah->ah_version == AR5K_AR5212) {
2440 hw->max_rates = 4;
76a9f6fd
BR		 2441 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2442 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2443 }
2444
2445 hw->vif_data_size = sizeof(struct ath5k_vif);
2446
2447 /* Finish private driver data initialization */
2448 ret = ath5k_init(hw);
2449 if (ret)
2450 goto err_ah;
2451
2452 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2453 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2454 sc->ah->ah_mac_srev,
2455 sc->ah->ah_phy_revision);
2456
2457 if (!sc->ah->ah_single_chip) {
2458 /* Single chip radio (!RF5111) */
2459 if (sc->ah->ah_radio_5ghz_revision &&
2460 !sc->ah->ah_radio_2ghz_revision) {
2461 /* No 5GHz support -> report 2GHz radio */
2462 if (!test_bit(AR5K_MODE_11A,
2463 sc->ah->ah_capabilities.cap_mode)) {
2464 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2465 ath5k_chip_name(AR5K_VERSION_RAD,
2466 sc->ah->ah_radio_5ghz_revision),
2467 sc->ah->ah_radio_5ghz_revision);
2468 /* No 2GHz support (5110 and some
6a2a0e73 2469 * 5GHz only cards) -> report 5GHz radio */
132b1c3e
FF		 2470 } else if (!test_bit(AR5K_MODE_11B,
2471 sc->ah->ah_capabilities.cap_mode)) {
2472 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2473 ath5k_chip_name(AR5K_VERSION_RAD,
2474 sc->ah->ah_radio_5ghz_revision),
2475 sc->ah->ah_radio_5ghz_revision);
2476 /* Multiband radio */
2477 } else {
2478 ATH5K_INFO(sc, "RF%s multiband radio found"
2479 " (0x%x)\n",
2480 ath5k_chip_name(AR5K_VERSION_RAD,
2481 sc->ah->ah_radio_5ghz_revision),
2482 sc->ah->ah_radio_5ghz_revision);
2483 }
2484 }
2485 /* Multi chip radio (RF5111 - RF2111) ->
2486 * report both 2GHz/5GHz radios */
2487 else if (sc->ah->ah_radio_5ghz_revision &&
e4bbf2f5 2488 sc->ah->ah_radio_2ghz_revision) {
132b1c3e
FF		 2489 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2490 ath5k_chip_name(AR5K_VERSION_RAD,
2491 sc->ah->ah_radio_5ghz_revision),
2492 sc->ah->ah_radio_5ghz_revision);
2493 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2494 ath5k_chip_name(AR5K_VERSION_RAD,
2495 sc->ah->ah_radio_2ghz_revision),
2496 sc->ah->ah_radio_2ghz_revision);
2497 }
2498 }
2499
2500 ath5k_debug_init_device(sc);
2501
2502 /* ready to process interrupts */
2503 __clear_bit(ATH_STAT_INVALID, sc->status);
2504
2505 return 0;
2506err_ah:
2507 ath5k_hw_deinit(sc->ah);
2508err_free_ah:
2509 kfree(sc->ah);
2510err_irq:
2511 free_irq(sc->irq, sc);
2512err:
2513 return ret;
2514}
2515
fa1c114f 2516static int
8a63facc 2517ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2518{
8a63facc 2519 struct ath5k_hw *ah = sc->ah;
cec8db23 2520
8a63facc
BC		 2521 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2522 test_bit(ATH_STAT_INVALID, sc->status));
2523
2524 /*
2525 * Shutdown the hardware and driver:
2526 * stop output from above
2527 * disable interrupts
2528 * turn off timers
2529 * turn off the radio
2530 * clear transmit machinery
2531 * clear receive machinery
2532 * drain and release tx queues
2533 * reclaim beacon resources
2534 * power down hardware
2535 *
2536 * Note that some of this work is not possible if the
2537 * hardware is gone (invalid).
2538 */
2539 ieee80211_stop_queues(sc->hw);
2540
2541 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2542 ath5k_led_off(sc);
2543 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2544 synchronize_irq(sc->irq);
8a63facc 2545 ath5k_rx_stop(sc);
80dac9ee
NK		 2546 ath5k_hw_dma_stop(ah);
2547 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2548 ath5k_hw_phy_disable(ah);
2549 }
2550
2551 return 0;
cec8db23
BC		 2552}
2553
cd2c5486 2554int
132b1c3e 2555ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2556{
8a63facc
BC		 2557 struct ath5k_hw *ah = sc->ah;
2558 struct ath_common *common = ath5k_hw_common(ah);
2559 int ret, i;
fa1c114f 2560
8a63facc
BC		 2561 mutex_lock(&sc->lock);
2562
2563 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2564
fa1c114f 2565 /*
8a63facc
BC		 2566 * Stop anything previously setup. This is safe
2567 * no matter this is the first time through or not.
fa1c114f 2568 */
8a63facc 2569 ath5k_stop_locked(sc);
fa1c114f 2570
8a63facc
BC		 2571 /*
2572 * The basic interface to setting the hardware in a good
2573 * state is ``reset''. On return the hardware is known to
2574 * be powered up and with interrupts disabled. This must
2575 * be followed by initialization of the appropriate bits
2576 * and then setup of the interrupt mask.
2577 */
2578 sc->curchan = sc->hw->conf.channel;
8a63facc
BC		 2579 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2580 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2581 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2582
8aec7af9 2583 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2584 if (ret)
2585 goto done;
fa1c114f 2586
8a63facc
BC		 2587 ath5k_rfkill_hw_start(ah);
2588
2589 /*
2590 * Reset the key cache since some parts do not reset the
2591 * contents on initial power up or resume from suspend.
2592 */
2593 for (i = 0; i < common->keymax; i++)
2594 ath_hw_keyreset(common, (u16) i);
2595
61cde037
NK		 2596 /* Use higher rates for acks instead of base
2597 * rate */
2598 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2599
2600 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2601 sc->bslot[i] = NULL;
2602
8a63facc
BC		 2603 ret = 0;
2604done:
2605 mmiowb();
2606 mutex_unlock(&sc->lock);
4edd761f
BR		 2607
2608 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2609 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2610
8a63facc
BC		 2611 return ret;
2612}
2613
f5cbc8ba 2614static void ath5k_stop_tasklets(struct ath5k_softc *sc)
8a63facc 2615{
c266c71a
FF		 2616 sc->rx_pending = false;
2617 sc->tx_pending = false;
8a63facc
BC		 2618 tasklet_kill(&sc->rxtq);
2619 tasklet_kill(&sc->txtq);
2620 tasklet_kill(&sc->calib);
2621 tasklet_kill(&sc->beacontq);
2622 tasklet_kill(&sc->ani_tasklet);
2623}
2624
2625/*
2626 * Stop the device, grabbing the top-level lock to protect
2627 * against concurrent entry through ath5k_init (which can happen
2628 * if another thread does a system call and the thread doing the
2629 * stop is preempted).
2630 */
cd2c5486 2631int
8a63facc
BC		 2632ath5k_stop_hw(struct ath5k_softc *sc)
2633{
2634 int ret;
2635
2636 mutex_lock(&sc->lock);
2637 ret = ath5k_stop_locked(sc);
2638 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2639 /*
2640 * Don't set the card in full sleep mode!
2641 *
2642 * a) When the device is in this state it must be carefully
2643 * woken up or references to registers in the PCI clock
2644 * domain may freeze the bus (and system). This varies
2645 * by chip and is mostly an issue with newer parts
2646 * (madwifi sources mentioned srev >= 0x78) that go to
2647 * sleep more quickly.
2648 *
2649 * b) On older chips full sleep results a weird behaviour
2650 * during wakeup. I tested various cards with srev < 0x78
2651 * and they don't wake up after module reload, a second
2652 * module reload is needed to bring the card up again.
2653 *
2654 * Until we figure out what's going on don't enable
2655 * full chip reset on any chip (this is what Legacy HAL
2656 * and Sam's HAL do anyway). Instead Perform a full reset
2657 * on the device (same as initial state after attach) and
2658 * leave it idle (keep MAC/BB on warm reset) */
2659 ret = ath5k_hw_on_hold(sc->ah);
2660
2661 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2662 "putting device to sleep\n");
fa1c114f
JS		 2663 }
2664
8a63facc
BC		 2665 mmiowb();
2666 mutex_unlock(&sc->lock);
2667
f5cbc8ba 2668 ath5k_stop_tasklets(sc);
8a63facc 2669
4edd761f
BR		 2670 cancel_delayed_work_sync(&sc->tx_complete_work);
2671
8a63facc
BC		 2672 ath5k_rfkill_hw_stop(sc->ah);
2673
2674 return ret;
fa1c114f
JS		 2675}
2676
209d889b
BC		 2677/*
2678 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2679 * and change to the given channel.
5faaff74
BC		 2680 *
2681 * This should be called with sc->lock.
209d889b 2682 */
fa1c114f 2683static int
8aec7af9
NK		 2684ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2685 bool skip_pcu)
fa1c114f 2686{
fa1c114f 2687 struct ath5k_hw *ah = sc->ah;
f15a4bb2 2688 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2689 int ret, ani_mode;
a99168ee 2690 bool fast;
fa1c114f
JS		 2691
2692 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2693
450464de 2694 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2695 synchronize_irq(sc->irq);
f5cbc8ba 2696 ath5k_stop_tasklets(sc);
450464de 2697
25985edc 2698 /* Save ani mode and disable ANI during
344b54b9
NK		 2699 * reset. If we don't we might get false
2700 * PHY error interrupts. */
2701 ani_mode = ah->ah_sc->ani_state.ani_mode;
2702 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2703
19252ecb
NK		 2704 /* We are going to empty hw queues
2705 * so we should also free any remaining
2706 * tx buffers */
2707 ath5k_drain_tx_buffs(sc);
930a7622 2708 if (chan)
209d889b 2709 sc->curchan = chan;
a99168ee
NK		 2710
2711 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2712
e4bbf2f5 2713 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast, skip_pcu);
d7dc1003 2714 if (ret) {
fa1c114f
JS		 2715 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2716 goto err;
2717 }
d7dc1003 2718
fa1c114f 2719 ret = ath5k_rx_start(sc);
d7dc1003 2720 if (ret) {
fa1c114f
JS		 2721 ATH5K_ERR(sc, "can't start recv logic\n");
2722 goto err;
2723 }
d7dc1003 2724
344b54b9 2725 ath5k_ani_init(ah, ani_mode);
2111ac0d 2726
ac559526
BR		 2727 ah->ah_cal_next_full = jiffies;
2728 ah->ah_cal_next_ani = jiffies;
afe86286 2729 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2730 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2731
f15a4bb2
BR		 2732 /* clear survey data and cycle counters */
2733 memset(&sc->survey, 0, sizeof(sc->survey));
bb007554 2734 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2735 ath_hw_cycle_counters_update(common);
2736 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2737 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2738 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2739
fa1c114f 2740 /*
d7dc1003
JS		 2741 * Change channels and update the h/w rate map if we're switching;
2742 * e.g. 11a to 11b/g.
2743 *
2744 * We may be doing a reset in response to an ioctl that changes the
2745 * channel so update any state that might change as a result.
fa1c114f
JS		 2746 *
2747 * XXX needed?
2748 */
2749/* ath5k_chan_change(sc, c); */
fa1c114f 2750
d7dc1003
JS		 2751 ath5k_beacon_config(sc);
2752 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2753
397f385b
BR		 2754 ieee80211_wake_queues(sc->hw);
2755
fa1c114f
JS		 2756 return 0;
2757err:
2758 return ret;
2759}
2760
5faaff74
BC		 2761static void ath5k_reset_work(struct work_struct *work)
2762{
2763 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2764 reset_work);
2765
2766 mutex_lock(&sc->lock);
8aec7af9 2767 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2768 mutex_unlock(&sc->lock);
2769}
2770
25380d80 2771static int __devinit
132b1c3e 2772ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2773{
132b1c3e 2774
fa1c114f 2775 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2776 struct ath5k_hw *ah = sc->ah;
2777 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2778 struct ath5k_txq *txq;
8a63facc 2779 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2780 int ret;
2781
fa1c114f 2782
8a63facc
BC		 2783 /*
2784 * Check if the MAC has multi-rate retry support.
2785 * We do this by trying to setup a fake extended
2786 * descriptor. MACs that don't have support will
2787 * return false w/o doing anything. MACs that do
2788 * support it will return true w/o doing anything.
2789 */
2790 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2791
8a63facc
BC		 2792 if (ret < 0)
2793 goto err;
2794 if (ret > 0)
2795 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2796
8a63facc
BC		 2797 /*
2798 * Collect the channel list. The 802.11 layer
6a2a0e73 2799 * is responsible for filtering this list based
8a63facc
BC		 2800 * on settings like the phy mode and regulatory
2801 * domain restrictions.
2802 */
2803 ret = ath5k_setup_bands(hw);
2804 if (ret) {
2805 ATH5K_ERR(sc, "can't get channels\n");
2806 goto err;
2807 }
67d2e2df 2808
8a63facc
BC		 2809 /*
2810 * Allocate tx+rx descriptors and populate the lists.
2811 */
aeae4ac9 2812 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2813 if (ret) {
2814 ATH5K_ERR(sc, "can't allocate descriptors\n");
2815 goto err;
2816 }
fa1c114f 2817
8a63facc
BC		 2818 /*
2819 * Allocate hardware transmit queues: one queue for
2820 * beacon frames and one data queue for each QoS
2821 * priority. Note that hw functions handle resetting
2822 * these queues at the needed time.
2823 */
2824 ret = ath5k_beaconq_setup(ah);
2825 if (ret < 0) {
2826 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2827 goto err_desc;
2828 }
2829 sc->bhalq = ret;
2830 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2831 if (IS_ERR(sc->cabq)) {
2832 ATH5K_ERR(sc, "can't setup cab queue\n");
2833 ret = PTR_ERR(sc->cabq);
2834 goto err_bhal;
2835 }
fa1c114f 2836
22d8d9f8
BR		 2837 /* 5211 and 5212 usually support 10 queues but we better rely on the
2838 * capability information */
2839 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2840 /* This order matches mac80211's queue priority, so we can
2841 * directly use the mac80211 queue number without any mapping */
2842 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2843 if (IS_ERR(txq)) {
2844 ATH5K_ERR(sc, "can't setup xmit queue\n");
2845 ret = PTR_ERR(txq);
2846 goto err_queues;
2847 }
2848 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2849 if (IS_ERR(txq)) {
2850 ATH5K_ERR(sc, "can't setup xmit queue\n");
2851 ret = PTR_ERR(txq);
2852 goto err_queues;
2853 }
2854 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2855 if (IS_ERR(txq)) {
2856 ATH5K_ERR(sc, "can't setup xmit queue\n");
2857 ret = PTR_ERR(txq);
2858 goto err_queues;
2859 }
2860 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2861 if (IS_ERR(txq)) {
2862 ATH5K_ERR(sc, "can't setup xmit queue\n");
2863 ret = PTR_ERR(txq);
2864 goto err_queues;
2865 }
2866 hw->queues = 4;
2867 } else {
2868 /* older hardware (5210) can only support one data queue */
2869 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2870 if (IS_ERR(txq)) {
2871 ATH5K_ERR(sc, "can't setup xmit queue\n");
2872 ret = PTR_ERR(txq);
2873 goto err_queues;
2874 }
2875 hw->queues = 1;
2876 }
fa1c114f 2877
8a63facc
BC		 2878 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2879 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2880 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2881 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2882 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2883
8a63facc 2884 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2885 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2886
fa9bfd61 2887 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
8a63facc 2888 if (ret) {
aeae4ac9 2889 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2890 goto err_queues;
e30eb4ab 2891 }
2bed03eb 2892
8a63facc 2893 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2894 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2895 /* All MAC address bits matter for ACKs */
62c58fb4 2896 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2897
2898 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2899 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2900 if (ret) {
2901 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2902 goto err_queues;
2903 }
2904
2905 ret = ieee80211_register_hw(hw);
2906 if (ret) {
2907 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2908 goto err_queues;
2909 }
2910
2911 if (!ath_is_world_regd(regulatory))
2912 regulatory_hint(hw->wiphy, regulatory->alpha2);
2913
2914 ath5k_init_leds(sc);
2915
2916 ath5k_sysfs_register(sc);
2917
2918 return 0;
2919err_queues:
2920 ath5k_txq_release(sc);
2921err_bhal:
2922 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2923err_desc:
aeae4ac9 2924 ath5k_desc_free(sc);
8a63facc
BC		 2925err:
2926 return ret;
2927}
2928
132b1c3e
FF		 2929void
2930ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2931{
132b1c3e 2932 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2933
2934 /*
2935 * NB: the order of these is important:
2936 * o call the 802.11 layer before detaching ath5k_hw to
2937 * ensure callbacks into the driver to delete global
2938 * key cache entries can be handled
2939 * o reclaim the tx queue data structures after calling
2940 * the 802.11 layer as we'll get called back to reclaim
2941 * node state and potentially want to use them
2942 * o to cleanup the tx queues the hal is called, so detach
2943 * it last
2944 * XXX: ??? detach ath5k_hw ???
2945 * Other than that, it's straightforward...
2946 */
2947 ieee80211_unregister_hw(hw);
aeae4ac9 2948 ath5k_desc_free(sc);
8a63facc
BC		 2949 ath5k_txq_release(sc);
2950 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2951 ath5k_unregister_leds(sc);
2952
2953 ath5k_sysfs_unregister(sc);
2954 /*
2955 * NB: can't reclaim these until after ieee80211_ifdetach
2956 * returns because we'll get called back to reclaim node
2957 * state and potentially want to use them.
2958 */
132b1c3e 2959 ath5k_hw_deinit(sc->ah);
0e8d1602 2960 kfree(sc->ah);
132b1c3e 2961 free_irq(sc->irq, sc);
8a63facc
BC		 2962}
2963
cd2c5486 2964bool
f5cbc8ba 2965ath5k_any_vif_assoc(struct ath5k_softc *sc)
b1ae1edf 2966{
e4b0b32a 2967 struct ath5k_vif_iter_data iter_data;
b1ae1edf
BG		 2968 iter_data.hw_macaddr = NULL;
2969 iter_data.any_assoc = false;
2970 iter_data.need_set_hw_addr = false;
2971 iter_data.found_active = true;
2972
e4b0b32a 2973 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
b1ae1edf
BG		 2974 &iter_data);
2975 return iter_data.any_assoc;
2976}
2977
cd2c5486 2978void
f5cbc8ba 2979ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
8a63facc
BC		 2980{
2981 struct ath5k_softc *sc = hw->priv;
2982 struct ath5k_hw *ah = sc->ah;
2983 u32 rfilt;
2984 rfilt = ath5k_hw_get_rx_filter(ah);
2985 if (enable)
2986 rfilt |= AR5K_RX_FILTER_BEACON;
2987 else
2988 rfilt &= ~AR5K_RX_FILTER_BEACON;
2989 ath5k_hw_set_rx_filter(ah, rfilt);
2990 sc->filter_flags = rfilt;
2991}
Linux kernel - Deliverables
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