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ath9k: fix spur mitigation no-spur case for AR9002
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
cd2c5486 64int modparam_nohwcrypt;
46802a4f 65module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 66MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 67
42639fcd 68static int modparam_all_channels;
46802a4f 69module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 70MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
fa1c114f
JS		 72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 78
132b1c3e 79static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 80static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
81 bool skip_pcu);
cd2c5486
BR		 82int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
83void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f 84
fa1c114f 85/* Known SREVs */
2c91108c 86static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 87#ifdef CONFIG_ATHEROS_AR231X
88 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
89 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
90 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
91 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
92 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
93 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
94 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
95#else
1bef016a
NK		 96 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
97 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
98 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
99 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
100 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
101 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
102 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
103 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
104 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
105 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
106 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
107 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
108 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
109 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
110 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
111 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
112 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
113 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 114#endif
1bef016a 115 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 116 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
117 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 118 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 119 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
120 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
121 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 122 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 123 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
124 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 125 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
126 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
127 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 128 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 129 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 130#ifdef CONFIG_ATHEROS_AR231X
131 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
132 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
133#endif
fa1c114f
JS		 134 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
135};
136
2c91108c 137static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 138 { .bitrate = 10,
139 .hw_value = ATH5K_RATE_CODE_1M, },
140 { .bitrate = 20,
141 .hw_value = ATH5K_RATE_CODE_2M,
142 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
143 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
144 { .bitrate = 55,
145 .hw_value = ATH5K_RATE_CODE_5_5M,
146 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
147 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
148 { .bitrate = 110,
149 .hw_value = ATH5K_RATE_CODE_11M,
150 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 60,
153 .hw_value = ATH5K_RATE_CODE_6M,
154 .flags = 0 },
155 { .bitrate = 90,
156 .hw_value = ATH5K_RATE_CODE_9M,
157 .flags = 0 },
158 { .bitrate = 120,
159 .hw_value = ATH5K_RATE_CODE_12M,
160 .flags = 0 },
161 { .bitrate = 180,
162 .hw_value = ATH5K_RATE_CODE_18M,
163 .flags = 0 },
164 { .bitrate = 240,
165 .hw_value = ATH5K_RATE_CODE_24M,
166 .flags = 0 },
167 { .bitrate = 360,
168 .hw_value = ATH5K_RATE_CODE_36M,
169 .flags = 0 },
170 { .bitrate = 480,
171 .hw_value = ATH5K_RATE_CODE_48M,
172 .flags = 0 },
173 { .bitrate = 540,
174 .hw_value = ATH5K_RATE_CODE_54M,
175 .flags = 0 },
176 /* XR missing */
177};
178
fa1c114f
JS		 179static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
180{
181 u64 tsf = ath5k_hw_get_tsf64(ah);
182
183 if ((tsf & 0x7fff) < rstamp)
184 tsf -= 0x8000;
185
186 return (tsf & ~0x7fff) | rstamp;
187}
188
e5b046d8 189const char *
fa1c114f
JS		 190ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
191{
192 const char *name = "xxxxx";
193 unsigned int i;
194
195 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
196 if (srev_names[i].sr_type != type)
197 continue;
75d0edb8
NK		 198
199 if ((val & 0xf0) == srev_names[i].sr_val)
200 name = srev_names[i].sr_name;
201
202 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 203 name = srev_names[i].sr_name;
204 break;
205 }
206 }
207
208 return name;
209}
e5aa8474
LR		 210static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
211{
212 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
213 return ath5k_hw_reg_read(ah, reg_offset);
214}
215
216static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
217{
218 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
219 ath5k_hw_reg_write(ah, val, reg_offset);
220}
221
222static const struct ath_ops ath5k_common_ops = {
223 .read = ath5k_ioread32,
224 .write = ath5k_iowrite32,
225};
fa1c114f 226
8a63facc
BC		 227/***********************\
228* Driver Initialization *
229\***********************/
230
231static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 232{
8a63facc
BC		 233 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
234 struct ath5k_softc *sc = hw->priv;
235 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 236
8a63facc
BC		 237 return ath_reg_notifier_apply(wiphy, request, regulatory);
238}
6ccf15a1 239
8a63facc
BC		 240/********************\
241* Channel/mode setup *
242\********************/
fa1c114f 243
8a63facc
BC		 244/*
245 * Convert IEEE channel number to MHz frequency.
246 */
247static inline short
248ath5k_ieee2mhz(short chan)
249{
250 if (chan <= 14 || chan >= 27)
251 return ieee80211chan2mhz(chan);
252 else
253 return 2212 + chan * 20;
254}
fa1c114f 255
8a63facc
BC		 256/*
257 * Returns true for the channel numbers used without all_channels modparam.
258 */
259static bool ath5k_is_standard_channel(short chan)
260{
261 return ((chan <= 14) ||
262 /* UNII 1,2 */
263 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
264 /* midband */
265 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
266 /* UNII-3 */
267 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
268}
fa1c114f 269
8a63facc
BC		 270static unsigned int
271ath5k_copy_channels(struct ath5k_hw *ah,
272 struct ieee80211_channel *channels,
273 unsigned int mode,
274 unsigned int max)
275{
276 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f 277
8a63facc
BC		 278 if (!test_bit(mode, ah->ah_modes))
279 return 0;
fa1c114f 280
8a63facc
BC		 281 switch (mode) {
282 case AR5K_MODE_11A:
8a63facc
BC		 283 /* 1..220, but 2GHz frequencies are filtered by check_channel */
284 size = 220 ;
285 chfreq = CHANNEL_5GHZ;
286 break;
287 case AR5K_MODE_11B:
288 case AR5K_MODE_11G:
8a63facc
BC		 289 size = 26;
290 chfreq = CHANNEL_2GHZ;
291 break;
292 default:
293 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
294 return 0;
fa1c114f
JS		 295 }
296
8a63facc
BC		 297 for (i = 0, count = 0; i < size && max > 0; i++) {
298 ch = i + 1 ;
299 freq = ath5k_ieee2mhz(ch);
fa1c114f 300
8a63facc
BC		 301 /* Check if channel is supported by the chipset */
302 if (!ath5k_channel_ok(ah, freq, chfreq))
303 continue;
f59ac048 304
8a63facc
BC		 305 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
306 continue;
f59ac048 307
8a63facc
BC		 308 /* Write channel info and increment counter */
309 channels[count].center_freq = freq;
310 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
311 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
312 switch (mode) {
313 case AR5K_MODE_11A:
314 case AR5K_MODE_11G:
315 channels[count].hw_value = chfreq | CHANNEL_OFDM;
316 break;
8a63facc
BC		 317 case AR5K_MODE_11B:
318 channels[count].hw_value = CHANNEL_B;
319 }
fa1c114f 320
8a63facc
BC		 321 count++;
322 max--;
323 }
fa1c114f 324
8a63facc
BC		 325 return count;
326}
fa1c114f 327
8a63facc
BC		 328static void
329ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
330{
331 u8 i;
fa1c114f 332
8a63facc
BC		 333 for (i = 0; i < AR5K_MAX_RATES; i++)
334 sc->rate_idx[b->band][i] = -1;
fa1c114f 335
8a63facc
BC		 336 for (i = 0; i < b->n_bitrates; i++) {
337 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
338 if (b->bitrates[i].hw_value_short)
339 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 340 }
8a63facc 341}
fa1c114f 342
8a63facc
BC		 343static int
344ath5k_setup_bands(struct ieee80211_hw *hw)
345{
346 struct ath5k_softc *sc = hw->priv;
347 struct ath5k_hw *ah = sc->ah;
348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
fa1c114f 351
8a63facc
BC		 352 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(sc->channels);
db719718 354
8a63facc
BC		 355 /* 2GHz band */
356 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
357 sband->band = IEEE80211_BAND_2GHZ;
358 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 359
8a63facc
BC		 360 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
361 /* G mode */
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
2f7fe870 365
8a63facc
BC		 366 sband->channels = sc->channels;
367 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
368 AR5K_MODE_11G, max_c);
fa1c114f 369
8a63facc
BC		 370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
372 max_c -= count_c;
373 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
374 /* B mode */
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
fa1c114f 378
8a63facc
BC		 379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
381 * fix them up here:
382 */
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 389 }
390 }
fa1c114f 391
8a63facc
BC		 392 sband->channels = sc->channels;
393 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
394 AR5K_MODE_11B, max_c);
fa1c114f 395
8a63facc
BC		 396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
399 }
400 ath5k_setup_rate_idx(sc, sband);
fa1c114f 401
8a63facc
BC		 402 /* 5GHz band, A mode */
403 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
404 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
405 sband->band = IEEE80211_BAND_5GHZ;
406 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 407
8a63facc
BC		 408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
fa1c114f 411
8a63facc
BC		 412 sband->channels = &sc->channels[count_c];
413 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
414 AR5K_MODE_11A, max_c);
fa1c114f 415
8a63facc
BC		 416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
418 ath5k_setup_rate_idx(sc, sband);
419
420 ath5k_debug_dump_bands(sc);
fa1c114f 421
fa1c114f
JS		 422 return 0;
423}
424
8a63facc
BC		 425/*
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
429 *
430 * Called with sc->lock.
431 */
cd2c5486 432int
8a63facc
BC		 433ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
434{
435 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
436 "channel set, resetting (%u -> %u MHz)\n",
437 sc->curchan->center_freq, chan->center_freq);
438
8451d22d 439 /*
8a63facc
BC		 440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
8451d22d 444 */
8aec7af9 445 return ath5k_reset(sc, chan, true);
fa1c114f 446}
fa1c114f 447
8a63facc
BC		 448static void
449ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 450{
8a63facc 451 sc->curmode = mode;
f769c36b 452
8a63facc
BC		 453 if (mode == AR5K_MODE_11A) {
454 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
455 } else {
456 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
457 }
f769c36b
BC		 458}
459
b1ae1edf
BG		 460struct ath_vif_iter_data {
461 const u8 *hw_macaddr;
462 u8 mask[ETH_ALEN];
463 u8 active_mac[ETH_ALEN]; /* first active MAC */
464 bool need_set_hw_addr;
465 bool found_active;
466 bool any_assoc;
62c58fb4 467 enum nl80211_iftype opmode;
b1ae1edf
BG		 468};
469
470static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
471{
472 struct ath_vif_iter_data *iter_data = data;
473 int i;
62c58fb4 474 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 475
476 if (iter_data->hw_macaddr)
477 for (i = 0; i < ETH_ALEN; i++)
478 iter_data->mask[i] &=
479 ~(iter_data->hw_macaddr[i] ^ mac[i]);
480
481 if (!iter_data->found_active) {
482 iter_data->found_active = true;
483 memcpy(iter_data->active_mac, mac, ETH_ALEN);
484 }
485
486 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
487 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
488 iter_data->need_set_hw_addr = false;
489
490 if (!iter_data->any_assoc) {
b1ae1edf
BG		 491 if (avf->assoc)
492 iter_data->any_assoc = true;
493 }
62c58fb4
BG		 494
495 /* Calculate combined mode - when APs are active, operate in AP mode.
496 * Otherwise use the mode of the new interface. This can currently
497 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 498 * interfaces is allowed.
62c58fb4
BG		 499 */
500 if (avf->opmode == NL80211_IFTYPE_AP)
501 iter_data->opmode = NL80211_IFTYPE_AP;
502 else
503 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
504 iter_data->opmode = avf->opmode;
b1ae1edf
BG		 505}
506
cd2c5486
BR		 507void
508ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
509 struct ieee80211_vif *vif)
b1ae1edf
BG		 510{
511 struct ath_common *common = ath5k_hw_common(sc->ah);
512 struct ath_vif_iter_data iter_data;
513
514 /*
515 * Use the hardware MAC address as reference, the hardware uses it
516 * together with the BSSID mask when matching addresses.
517 */
518 iter_data.hw_macaddr = common->macaddr;
519 memset(&iter_data.mask, 0xff, ETH_ALEN);
520 iter_data.found_active = false;
521 iter_data.need_set_hw_addr = true;
62c58fb4 522 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
b1ae1edf
BG		 523
524 if (vif)
525 ath_vif_iter(&iter_data, vif->addr, vif);
526
527 /* Get list of all active MAC addresses */
528 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
529 &iter_data);
530 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
531
62c58fb4
BG		 532 sc->opmode = iter_data.opmode;
533 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
534 /* Nothing active, default to station mode */
535 sc->opmode = NL80211_IFTYPE_STATION;
536
7afbb2f0
BG		 537 ath5k_hw_set_opmode(sc->ah, sc->opmode);
538 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
539 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 540
b1ae1edf
BG		 541 if (iter_data.need_set_hw_addr && iter_data.found_active)
542 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
543
62c58fb4
BG		 544 if (ath5k_hw_hasbssidmask(sc->ah))
545 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf
BG		 546}
547
cd2c5486 548void
b1ae1edf 549ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
fa1c114f 550{
fa1c114f 551 struct ath5k_hw *ah = sc->ah;
8a63facc 552 u32 rfilt;
fa1c114f 553
8a63facc
BC		 554 /* configure rx filter */
555 rfilt = sc->filter_flags;
556 ath5k_hw_set_rx_filter(ah, rfilt);
8a63facc 557 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
62c58fb4
BG		 558
559 ath5k_update_bssid_mask_and_opmode(sc, vif);
8a63facc 560}
fa1c114f 561
8a63facc
BC		 562static inline int
563ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
564{
565 int rix;
fa1c114f 566
8a63facc
BC		 567 /* return base rate on errors */
568 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
569 "hw_rix out of bounds: %x\n", hw_rix))
570 return 0;
571
572 rix = sc->rate_idx[sc->curband->band][hw_rix];
573 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
574 rix = 0;
575
576 return rix;
577}
578
579/***************\
580* Buffers setup *
581\***************/
582
583static
584struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
585{
586 struct ath_common *common = ath5k_hw_common(sc->ah);
587 struct sk_buff *skb;
fa1c114f
JS		 588
589 /*
8a63facc
BC		 590 * Allocate buffer with headroom_needed space for the
591 * fake physical layer header at the start.
fa1c114f 592 */
8a63facc
BC		 593 skb = ath_rxbuf_alloc(common,
594 common->rx_bufsize,
595 GFP_ATOMIC);
fa1c114f 596
8a63facc
BC		 597 if (!skb) {
598 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
599 common->rx_bufsize);
600 return NULL;
fa1c114f
JS		 601 }
602
aeae4ac9 603 *skb_addr = dma_map_single(sc->dev,
8a63facc 604 skb->data, common->rx_bufsize,
aeae4ac9
FF		 605 DMA_FROM_DEVICE);
606
607 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 608 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
609 dev_kfree_skb(skb);
610 return NULL;
0e149cf5 611 }
8a63facc
BC		 612 return skb;
613}
0e149cf5 614
8a63facc
BC		 615static int
616ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
617{
618 struct ath5k_hw *ah = sc->ah;
619 struct sk_buff *skb = bf->skb;
620 struct ath5k_desc *ds;
621 int ret;
fa1c114f 622
8a63facc
BC		 623 if (!skb) {
624 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
625 if (!skb)
626 return -ENOMEM;
627 bf->skb = skb;
f769c36b
BC		 628 }
629
8a63facc
BC		 630 /*
631 * Setup descriptors. For receive we always terminate
632 * the descriptor list with a self-linked entry so we'll
633 * not get overrun under high load (as can happen with a
634 * 5212 when ANI processing enables PHY error frames).
635 *
636 * To ensure the last descriptor is self-linked we create
637 * each descriptor as self-linked and add it to the end. As
638 * each additional descriptor is added the previous self-linked
639 * entry is "fixed" naturally. This should be safe even
640 * if DMA is happening. When processing RX interrupts we
641 * never remove/process the last, self-linked, entry on the
642 * descriptor list. This ensures the hardware always has
643 * someplace to write a new frame.
644 */
645 ds = bf->desc;
646 ds->ds_link = bf->daddr; /* link to self */
647 ds->ds_data = bf->skbaddr;
648 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 649 if (ret) {
8a63facc
BC		 650 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
651 return ret;
fa1c114f
JS		 652 }
653
8a63facc
BC		 654 if (sc->rxlink != NULL)
655 *sc->rxlink = bf->daddr;
656 sc->rxlink = &ds->ds_link;
fa1c114f 657 return 0;
fa1c114f
JS		 658}
659
8a63facc 660static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 661{
8a63facc
BC		 662 struct ieee80211_hdr *hdr;
663 enum ath5k_pkt_type htype;
664 __le16 fc;
fa1c114f 665
8a63facc
BC		 666 hdr = (struct ieee80211_hdr *)skb->data;
667 fc = hdr->frame_control;
fa1c114f 668
8a63facc
BC		 669 if (ieee80211_is_beacon(fc))
670 htype = AR5K_PKT_TYPE_BEACON;
671 else if (ieee80211_is_probe_resp(fc))
672 htype = AR5K_PKT_TYPE_PROBE_RESP;
673 else if (ieee80211_is_atim(fc))
674 htype = AR5K_PKT_TYPE_ATIM;
675 else if (ieee80211_is_pspoll(fc))
676 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 677 else
8a63facc 678 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 679
8a63facc 680 return htype;
42639fcd
BC		 681}
682
8a63facc
BC		 683static int
684ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
685 struct ath5k_txq *txq, int padsize)
fa1c114f 686{
8a63facc
BC		 687 struct ath5k_hw *ah = sc->ah;
688 struct ath5k_desc *ds = bf->desc;
689 struct sk_buff *skb = bf->skb;
690 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
691 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
692 struct ieee80211_rate *rate;
693 unsigned int mrr_rate[3], mrr_tries[3];
694 int i, ret;
695 u16 hw_rate;
696 u16 cts_rate = 0;
697 u16 duration = 0;
698 u8 rc_flags;
fa1c114f 699
8a63facc 700 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 701
8a63facc 702 /* XXX endianness */
aeae4ac9
FF		 703 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
704 DMA_TO_DEVICE);
fa1c114f 705
8a63facc 706 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 707 if (!rate) {
708 ret = -EINVAL;
709 goto err_unmap;
710 }
fa1c114f 711
8a63facc
BC		 712 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
713 flags |= AR5K_TXDESC_NOACK;
fa1c114f 714
8a63facc
BC		 715 rc_flags = info->control.rates[0].flags;
716 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
717 rate->hw_value_short : rate->hw_value;
42639fcd 718
8a63facc
BC		 719 pktlen = skb->len;
720
721 /* FIXME: If we are in g mode and rate is a CCK rate
722 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
723 * from tx power (value is in dB units already) */
724 if (info->control.hw_key) {
725 keyidx = info->control.hw_key->hw_key_idx;
726 pktlen += info->control.hw_key->icv_len;
727 }
728 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
729 flags |= AR5K_TXDESC_RTSENA;
730 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
731 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 732 info->control.vif, pktlen, info));
8a63facc
BC		 733 }
734 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
735 flags |= AR5K_TXDESC_CTSENA;
736 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
737 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 738 info->control.vif, pktlen, info));
8a63facc
BC		 739 }
740 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
741 ieee80211_get_hdrlen_from_skb(skb), padsize,
742 get_hw_packet_type(skb),
743 (sc->power_level * 2),
744 hw_rate,
745 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
746 cts_rate, duration);
747 if (ret)
748 goto err_unmap;
749
750 memset(mrr_rate, 0, sizeof(mrr_rate));
751 memset(mrr_tries, 0, sizeof(mrr_tries));
752 for (i = 0; i < 3; i++) {
753 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
754 if (!rate)
400ec45a 755 break;
fa1c114f 756
8a63facc
BC		 757 mrr_rate[i] = rate->hw_value;
758 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 759 }
760
8a63facc
BC		 761 ath5k_hw_setup_mrr_tx_desc(ah, ds,
762 mrr_rate[0], mrr_tries[0],
763 mrr_rate[1], mrr_tries[1],
764 mrr_rate[2], mrr_tries[2]);
fa1c114f 765
8a63facc
BC		 766 ds->ds_link = 0;
767 ds->ds_data = bf->skbaddr;
63266a65 768
8a63facc
BC		 769 spin_lock_bh(&txq->lock);
770 list_add_tail(&bf->list, &txq->q);
925e0b06 771 txq->txq_len++;
8a63facc
BC		 772 if (txq->link == NULL) /* is this first packet? */
773 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
774 else /* no, so only link it */
775 *txq->link = bf->daddr;
63266a65 776
8a63facc
BC		 777 txq->link = &ds->ds_link;
778 ath5k_hw_start_tx_dma(ah, txq->qnum);
779 mmiowb();
780 spin_unlock_bh(&txq->lock);
781
782 return 0;
783err_unmap:
aeae4ac9 784 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 785 return ret;
63266a65
BR		 786}
787
8a63facc
BC		 788/*******************\
789* Descriptors setup *
790\*******************/
791
d8ee398d 792static int
aeae4ac9 793ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 794{
8a63facc
BC		 795 struct ath5k_desc *ds;
796 struct ath5k_buf *bf;
797 dma_addr_t da;
798 unsigned int i;
799 int ret;
d8ee398d 800
8a63facc
BC		 801 /* allocate descriptors */
802 sc->desc_len = sizeof(struct ath5k_desc) *
803 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 804
805 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
806 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 807 if (sc->desc == NULL) {
808 ATH5K_ERR(sc, "can't allocate descriptors\n");
809 ret = -ENOMEM;
810 goto err;
811 }
812 ds = sc->desc;
813 da = sc->desc_daddr;
814 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
815 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 816
8a63facc
BC		 817 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
818 sizeof(struct ath5k_buf), GFP_KERNEL);
819 if (bf == NULL) {
820 ATH5K_ERR(sc, "can't allocate bufptr\n");
821 ret = -ENOMEM;
822 goto err_free;
823 }
824 sc->bufptr = bf;
fa1c114f 825
8a63facc
BC		 826 INIT_LIST_HEAD(&sc->rxbuf);
827 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
828 bf->desc = ds;
829 bf->daddr = da;
830 list_add_tail(&bf->list, &sc->rxbuf);
831 }
d8ee398d 832
8a63facc
BC		 833 INIT_LIST_HEAD(&sc->txbuf);
834 sc->txbuf_len = ATH_TXBUF;
835 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
836 da += sizeof(*ds)) {
837 bf->desc = ds;
838 bf->daddr = da;
839 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 840 }
841
b1ae1edf
BG		 842 /* beacon buffers */
843 INIT_LIST_HEAD(&sc->bcbuf);
844 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
845 bf->desc = ds;
846 bf->daddr = da;
847 list_add_tail(&bf->list, &sc->bcbuf);
848 }
fa1c114f 849
8a63facc
BC		 850 return 0;
851err_free:
aeae4ac9 852 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 853err:
854 sc->desc = NULL;
855 return ret;
856}
fa1c114f 857
cd2c5486
BR		 858void
859ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
860{
861 BUG_ON(!bf);
862 if (!bf->skb)
863 return;
864 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
865 DMA_TO_DEVICE);
866 dev_kfree_skb_any(bf->skb);
867 bf->skb = NULL;
868 bf->skbaddr = 0;
869 bf->desc->ds_data = 0;
870}
871
872void
873ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
874{
875 struct ath5k_hw *ah = sc->ah;
876 struct ath_common *common = ath5k_hw_common(ah);
877
878 BUG_ON(!bf);
879 if (!bf->skb)
880 return;
881 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
882 DMA_FROM_DEVICE);
883 dev_kfree_skb_any(bf->skb);
884 bf->skb = NULL;
885 bf->skbaddr = 0;
886 bf->desc->ds_data = 0;
887}
888
8a63facc 889static void
aeae4ac9 890ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 891{
892 struct ath5k_buf *bf;
d8ee398d 893
8a63facc
BC		 894 list_for_each_entry(bf, &sc->txbuf, list)
895 ath5k_txbuf_free_skb(sc, bf);
896 list_for_each_entry(bf, &sc->rxbuf, list)
897 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 898 list_for_each_entry(bf, &sc->bcbuf, list)
899 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 900
8a63facc 901 /* Free memory associated with all descriptors */
aeae4ac9 902 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 903 sc->desc = NULL;
904 sc->desc_daddr = 0;
d8ee398d 905
8a63facc
BC		 906 kfree(sc->bufptr);
907 sc->bufptr = NULL;
fa1c114f
JS		 908}
909
8a63facc
BC		 910
911/**************\
912* Queues setup *
913\**************/
914
915static struct ath5k_txq *
916ath5k_txq_setup(struct ath5k_softc *sc,
917 int qtype, int subtype)
fa1c114f 918{
8a63facc
BC		 919 struct ath5k_hw *ah = sc->ah;
920 struct ath5k_txq *txq;
921 struct ath5k_txq_info qi = {
922 .tqi_subtype = subtype,
de8af455
BR		 923 /* XXX: default values not correct for B and XR channels,
924 * but who cares? */
925 .tqi_aifs = AR5K_TUNE_AIFS,
926 .tqi_cw_min = AR5K_TUNE_CWMIN,
927 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 928 };
929 int qnum;
d8ee398d 930
e30eb4ab 931 /*
8a63facc
BC		 932 * Enable interrupts only for EOL and DESC conditions.
933 * We mark tx descriptors to receive a DESC interrupt
934 * when a tx queue gets deep; otherwise we wait for the
935 * EOL to reap descriptors. Note that this is done to
936 * reduce interrupt load and this only defers reaping
937 * descriptors, never transmitting frames. Aside from
938 * reducing interrupts this also permits more concurrency.
939 * The only potential downside is if the tx queue backs
940 * up in which case the top half of the kernel may backup
941 * due to a lack of tx descriptors.
e30eb4ab 942 */
8a63facc
BC		 943 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
944 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
945 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
946 if (qnum < 0) {
947 /*
948 * NB: don't print a message, this happens
949 * normally on parts with too few tx queues
950 */
951 return ERR_PTR(qnum);
952 }
953 if (qnum >= ARRAY_SIZE(sc->txqs)) {
954 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
955 qnum, ARRAY_SIZE(sc->txqs));
956 ath5k_hw_release_tx_queue(ah, qnum);
957 return ERR_PTR(-EINVAL);
958 }
959 txq = &sc->txqs[qnum];
960 if (!txq->setup) {
961 txq->qnum = qnum;
962 txq->link = NULL;
963 INIT_LIST_HEAD(&txq->q);
964 spin_lock_init(&txq->lock);
965 txq->setup = true;
925e0b06 966 txq->txq_len = 0;
4edd761f 967 txq->txq_poll_mark = false;
923e5b3d 968 txq->txq_stuck = 0;
8a63facc
BC		 969 }
970 return &sc->txqs[qnum];
fa1c114f
JS		 971}
972
8a63facc
BC		 973static int
974ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 975{
8a63facc 976 struct ath5k_txq_info qi = {
de8af455
BR		 977 /* XXX: default values not correct for B and XR channels,
978 * but who cares? */
979 .tqi_aifs = AR5K_TUNE_AIFS,
980 .tqi_cw_min = AR5K_TUNE_CWMIN,
981 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 982 /* NB: for dynamic turbo, don't enable any other interrupts */
983 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
984 };
d8ee398d 985
8a63facc 986 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 987}
988
8a63facc
BC		 989static int
990ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 991{
992 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 993 struct ath5k_txq_info qi;
994 int ret;
fa1c114f 995
8a63facc
BC		 996 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
997 if (ret)
998 goto err;
fa1c114f 999
8a63facc
BC		 1000 if (sc->opmode == NL80211_IFTYPE_AP ||
1001 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1002 /*
1003 * Always burst out beacon and CAB traffic
1004 * (aifs = cwmin = cwmax = 0)
1005 */
1006 qi.tqi_aifs = 0;
1007 qi.tqi_cw_min = 0;
1008 qi.tqi_cw_max = 0;
1009 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1010 /*
1011 * Adhoc mode; backoff between 0 and (2 * cw_min).
1012 */
1013 qi.tqi_aifs = 0;
1014 qi.tqi_cw_min = 0;
de8af455 1015 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 1016 }
fa1c114f 1017
8a63facc
BC		 1018 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1019 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1020 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1021
8a63facc
BC		 1022 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1023 if (ret) {
1024 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1025 "hardware queue!\n", __func__);
1026 goto err;
1027 }
1028 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1029 if (ret)
1030 goto err;
b7266047 1031
8a63facc
BC		 1032 /* reconfigure cabq with ready time to 80% of beacon_interval */
1033 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1034 if (ret)
1035 goto err;
b7266047 1036
8a63facc
BC		 1037 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1038 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1039 if (ret)
1040 goto err;
b7266047 1041
8a63facc
BC		 1042 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1043err:
1044 return ret;
d8ee398d
LR		 1045}
1046
80dac9ee
NK		 1047/**
1048 * ath5k_drain_tx_buffs - Empty tx buffers
1049 *
1050 * @sc The &struct ath5k_softc
1051 *
1052 * Empty tx buffers from all queues in preparation
1053 * of a reset or during shutdown.
1054 *
1055 * NB: this assumes output has been stopped and
1056 * we do not need to block ath5k_tx_tasklet
1057 */
8a63facc 1058static void
80dac9ee 1059ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1060{
80dac9ee 1061 struct ath5k_txq *txq;
8a63facc 1062 struct ath5k_buf *bf, *bf0;
80dac9ee 1063 int i;
b6ea0356 1064
80dac9ee
NK		 1065 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1066 if (sc->txqs[i].setup) {
1067 txq = &sc->txqs[i];
1068 spin_lock_bh(&txq->lock);
1069 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1070 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1071
80dac9ee 1072 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1073
80dac9ee
NK		 1074 spin_lock_bh(&sc->txbuflock);
1075 list_move_tail(&bf->list, &sc->txbuf);
1076 sc->txbuf_len++;
1077 txq->txq_len--;
1078 spin_unlock_bh(&sc->txbuflock);
8a63facc 1079 }
80dac9ee
NK		 1080 txq->link = NULL;
1081 txq->txq_poll_mark = false;
1082 spin_unlock_bh(&txq->lock);
1083 }
0452d4a5 1084 }
fa1c114f
JS		 1085}
1086
8a63facc
BC		 1087static void
1088ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1089{
8a63facc
BC		 1090 struct ath5k_txq *txq = sc->txqs;
1091 unsigned int i;
2ac2927a 1092
8a63facc
BC		 1093 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1094 if (txq->setup) {
1095 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1096 txq->setup = false;
1097 }
1098}
2ac2927a 1099
2ac2927a 1100
8a63facc
BC		 1101/*************\
1102* RX Handling *
1103\*************/
2ac2927a 1104
8a63facc
BC		 1105/*
1106 * Enable the receive h/w following a reset.
1107 */
fa1c114f 1108static int
8a63facc 1109ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1110{
1111 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1112 struct ath_common *common = ath5k_hw_common(ah);
1113 struct ath5k_buf *bf;
1114 int ret;
fa1c114f 1115
8a63facc 1116 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1117
8a63facc
BC		 1118 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1119 common->cachelsz, common->rx_bufsize);
2f7fe870 1120
8a63facc
BC		 1121 spin_lock_bh(&sc->rxbuflock);
1122 sc->rxlink = NULL;
1123 list_for_each_entry(bf, &sc->rxbuf, list) {
1124 ret = ath5k_rxbuf_setup(sc, bf);
1125 if (ret != 0) {
1126 spin_unlock_bh(&sc->rxbuflock);
1127 goto err;
1128 }
2f7fe870 1129 }
8a63facc
BC		 1130 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1131 ath5k_hw_set_rxdp(ah, bf->daddr);
1132 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1133
8a63facc 1134 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
b1ae1edf 1135 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
8a63facc 1136 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1137
1138 return 0;
8a63facc 1139err:
fa1c114f
JS		 1140 return ret;
1141}
1142
8a63facc 1143/*
80dac9ee
NK		 1144 * Disable the receive logic on PCU (DRU)
1145 * In preparation for a shutdown.
1146 *
1147 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1148 * does.
8a63facc
BC		 1149 */
1150static void
1151ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1152{
8a63facc 1153 struct ath5k_hw *ah = sc->ah;
fa1c114f 1154
8a63facc 1155 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1156 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1157
8a63facc
BC		 1158 ath5k_debug_printrxbuffs(sc, ah);
1159}
fa1c114f 1160
8a63facc
BC		 1161static unsigned int
1162ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1163 struct ath5k_rx_status *rs)
1164{
1165 struct ath5k_hw *ah = sc->ah;
1166 struct ath_common *common = ath5k_hw_common(ah);
1167 struct ieee80211_hdr *hdr = (void *)skb->data;
1168 unsigned int keyix, hlen;
fa1c114f 1169
8a63facc
BC		 1170 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1171 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1172 return RX_FLAG_DECRYPTED;
fa1c114f 1173
8a63facc
BC		 1174 /* Apparently when a default key is used to decrypt the packet
1175 the hw does not set the index used to decrypt. In such cases
1176 get the index from the packet. */
1177 hlen = ieee80211_hdrlen(hdr->frame_control);
1178 if (ieee80211_has_protected(hdr->frame_control) &&
1179 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1180 skb->len >= hlen + 4) {
1181 keyix = skb->data[hlen + 3] >> 6;
1182
1183 if (test_bit(keyix, common->keymap))
1184 return RX_FLAG_DECRYPTED;
1185 }
fa1c114f
JS		 1186
1187 return 0;
fa1c114f
JS		 1188}
1189
8a63facc 1190
fa1c114f 1191static void
8a63facc
BC		 1192ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1193 struct ieee80211_rx_status *rxs)
fa1c114f 1194{
8a63facc
BC		 1195 struct ath_common *common = ath5k_hw_common(sc->ah);
1196 u64 tsf, bc_tstamp;
1197 u32 hw_tu;
1198 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1199
8a63facc
BC		 1200 if (ieee80211_is_beacon(mgmt->frame_control) &&
1201 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1202 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1203 /*
1204 * Received an IBSS beacon with the same BSSID. Hardware *must*
1205 * have updated the local TSF. We have to work around various
1206 * hardware bugs, though...
1207 */
1208 tsf = ath5k_hw_get_tsf64(sc->ah);
1209 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1210 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1211
8a63facc
BC		 1212 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1213 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1214 (unsigned long long)bc_tstamp,
1215 (unsigned long long)rxs->mactime,
1216 (unsigned long long)(rxs->mactime - bc_tstamp),
1217 (unsigned long long)tsf);
fa1c114f 1218
8a63facc
BC		 1219 /*
1220 * Sometimes the HW will give us a wrong tstamp in the rx
1221 * status, causing the timestamp extension to go wrong.
1222 * (This seems to happen especially with beacon frames bigger
1223 * than 78 byte (incl. FCS))
1224 * But we know that the receive timestamp must be later than the
1225 * timestamp of the beacon since HW must have synced to that.
1226 *
1227 * NOTE: here we assume mactime to be after the frame was
1228 * received, not like mac80211 which defines it at the start.
1229 */
1230 if (bc_tstamp > rxs->mactime) {
1231 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1232 "fixing mactime from %llx to %llx\n",
1233 (unsigned long long)rxs->mactime,
1234 (unsigned long long)tsf);
1235 rxs->mactime = tsf;
1236 }
fa1c114f 1237
8a63facc
BC		 1238 /*
1239 * Local TSF might have moved higher than our beacon timers,
1240 * in that case we have to update them to continue sending
1241 * beacons. This also takes care of synchronizing beacon sending
1242 * times with other stations.
1243 */
1244 if (hw_tu >= sc->nexttbtt)
1245 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1246
1247 /* Check if the beacon timers are still correct, because a TSF
1248 * update might have created a window between them - for a
1249 * longer description see the comment of this function: */
1250 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1251 ath5k_beacon_update_timers(sc, bc_tstamp);
1252 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1253 "fixed beacon timers after beacon receive\n");
1254 }
8a63facc
BC		 1255 }
1256}
fa1c114f 1257
8a63facc
BC		 1258static void
1259ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1260{
1261 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1262 struct ath5k_hw *ah = sc->ah;
1263 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1264
8a63facc
BC		 1265 /* only beacons from our BSSID */
1266 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1267 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1268 return;
fa1c114f 1269
eef39bef 1270 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1271
8a63facc
BC		 1272 /* in IBSS mode we should keep RSSI statistics per neighbour */
1273 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1274}
fa1c114f 1275
8a63facc
BC		 1276/*
1277 * Compute padding position. skb must contain an IEEE 802.11 frame
1278 */
1279static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1280{
8a63facc
BC		 1281 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1282 __le16 frame_control = hdr->frame_control;
1283 int padpos = 24;
fa1c114f 1284
8a63facc
BC		 1285 if (ieee80211_has_a4(frame_control)) {
1286 padpos += ETH_ALEN;
fa1c114f 1287 }
8a63facc
BC		 1288 if (ieee80211_is_data_qos(frame_control)) {
1289 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1290 }
8a63facc
BC		 1291
1292 return padpos;
fa1c114f
JS		 1293}
1294
8a63facc
BC		 1295/*
1296 * This function expects an 802.11 frame and returns the number of
1297 * bytes added, or -1 if we don't have enough header room.
1298 */
1299static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1300{
8a63facc
BC		 1301 int padpos = ath5k_common_padpos(skb);
1302 int padsize = padpos & 3;
fa1c114f 1303
8a63facc 1304 if (padsize && skb->len>padpos) {
fa1c114f 1305
8a63facc
BC		 1306 if (skb_headroom(skb) < padsize)
1307 return -1;
fa1c114f 1308
8a63facc
BC		 1309 skb_push(skb, padsize);
1310 memmove(skb->data, skb->data+padsize, padpos);
1311 return padsize;
1312 }
a951ae21 1313
8a63facc
BC		 1314 return 0;
1315}
fa1c114f 1316
8a63facc
BC		 1317/*
1318 * The MAC header is padded to have 32-bit boundary if the
1319 * packet payload is non-zero. The general calculation for
1320 * padsize would take into account odd header lengths:
1321 * padsize = 4 - (hdrlen & 3); however, since only
1322 * even-length headers are used, padding can only be 0 or 2
1323 * bytes and we can optimize this a bit. We must not try to
1324 * remove padding from short control frames that do not have a
1325 * payload.
1326 *
1327 * This function expects an 802.11 frame and returns the number of
1328 * bytes removed.
1329 */
1330static int ath5k_remove_padding(struct sk_buff *skb)
1331{
1332 int padpos = ath5k_common_padpos(skb);
1333 int padsize = padpos & 3;
6d91e1d8 1334
8a63facc
BC		 1335 if (padsize && skb->len>=padpos+padsize) {
1336 memmove(skb->data + padsize, skb->data, padpos);
1337 skb_pull(skb, padsize);
1338 return padsize;
fa1c114f 1339 }
a951ae21 1340
8a63facc 1341 return 0;
fa1c114f
JS		 1342}
1343
1344static void
8a63facc
BC		 1345ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1346 struct ath5k_rx_status *rs)
fa1c114f 1347{
8a63facc
BC		 1348 struct ieee80211_rx_status *rxs;
1349
1350 ath5k_remove_padding(skb);
1351
1352 rxs = IEEE80211_SKB_RXCB(skb);
1353
1354 rxs->flag = 0;
1355 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1356 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1357
1358 /*
8a63facc
BC		 1359 * always extend the mac timestamp, since this information is
1360 * also needed for proper IBSS merging.
1361 *
1362 * XXX: it might be too late to do it here, since rs_tstamp is
1363 * 15bit only. that means TSF extension has to be done within
1364 * 32768usec (about 32ms). it might be necessary to move this to
1365 * the interrupt handler, like it is done in madwifi.
1366 *
1367 * Unfortunately we don't know when the hardware takes the rx
1368 * timestamp (beginning of phy frame, data frame, end of rx?).
1369 * The only thing we know is that it is hardware specific...
1370 * On AR5213 it seems the rx timestamp is at the end of the
1371 * frame, but i'm not sure.
1372 *
1373 * NOTE: mac80211 defines mactime at the beginning of the first
1374 * data symbol. Since we don't have any time references it's
1375 * impossible to comply to that. This affects IBSS merge only
1376 * right now, so it's not too bad...
fa1c114f 1377 */
8a63facc
BC		 1378 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1379 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1380
8a63facc
BC		 1381 rxs->freq = sc->curchan->center_freq;
1382 rxs->band = sc->curband->band;
fa1c114f 1383
8a63facc 1384 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1385
8a63facc 1386 rxs->antenna = rs->rs_antenna;
fa1c114f 1387
8a63facc
BC		 1388 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1389 sc->stats.antenna_rx[rs->rs_antenna]++;
1390 else
1391 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1392
8a63facc
BC		 1393 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1394 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1395
8a63facc
BC		 1396 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1397 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1398 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1399
8a63facc 1400 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1401
8a63facc 1402 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1403
8a63facc
BC		 1404 /* check beacons in IBSS mode */
1405 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1406 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1407
8a63facc
BC		 1408 ieee80211_rx(sc->hw, skb);
1409}
fa1c114f 1410
8a63facc
BC		 1411/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1412 *
1413 * Check if we want to further process this frame or not. Also update
1414 * statistics. Return true if we want this frame, false if not.
fa1c114f 1415 */
8a63facc
BC		 1416static bool
1417ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1418{
8a63facc 1419 sc->stats.rx_all_count++;
b72acddb 1420 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1421
8a63facc
BC		 1422 if (unlikely(rs->rs_status)) {
1423 if (rs->rs_status & AR5K_RXERR_CRC)
1424 sc->stats.rxerr_crc++;
1425 if (rs->rs_status & AR5K_RXERR_FIFO)
1426 sc->stats.rxerr_fifo++;
1427 if (rs->rs_status & AR5K_RXERR_PHY) {
1428 sc->stats.rxerr_phy++;
1429 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1430 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1431 return false;
1432 }
1433 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1434 /*
1435 * Decrypt error. If the error occurred
1436 * because there was no hardware key, then
1437 * let the frame through so the upper layers
1438 * can process it. This is necessary for 5210
1439 * parts which have no way to setup a ``clear''
1440 * key cache entry.
1441 *
1442 * XXX do key cache faulting
1443 */
1444 sc->stats.rxerr_decrypt++;
1445 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1446 !(rs->rs_status & AR5K_RXERR_CRC))
1447 return true;
1448 }
1449 if (rs->rs_status & AR5K_RXERR_MIC) {
1450 sc->stats.rxerr_mic++;
1451 return true;
fa1c114f 1452 }
fa1c114f 1453
8a63facc
BC		 1454 /* reject any frames with non-crypto errors */
1455 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1456 return false;
1457 }
fa1c114f 1458
8a63facc
BC		 1459 if (unlikely(rs->rs_more)) {
1460 sc->stats.rxerr_jumbo++;
1461 return false;
1462 }
1463 return true;
fa1c114f
JS		 1464}
1465
fa1c114f 1466static void
8a63facc 1467ath5k_tasklet_rx(unsigned long data)
fa1c114f 1468{
8a63facc
BC		 1469 struct ath5k_rx_status rs = {};
1470 struct sk_buff *skb, *next_skb;
1471 dma_addr_t next_skb_addr;
1472 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1473 struct ath5k_hw *ah = sc->ah;
1474 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1475 struct ath5k_buf *bf;
1476 struct ath5k_desc *ds;
1477 int ret;
fa1c114f 1478
8a63facc
BC		 1479 spin_lock(&sc->rxbuflock);
1480 if (list_empty(&sc->rxbuf)) {
1481 ATH5K_WARN(sc, "empty rx buf pool\n");
1482 goto unlock;
1483 }
1484 do {
1485 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1486 BUG_ON(bf->skb == NULL);
1487 skb = bf->skb;
1488 ds = bf->desc;
fa1c114f 1489
8a63facc
BC		 1490 /* bail if HW is still using self-linked descriptor */
1491 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1492 break;
fa1c114f 1493
8a63facc
BC		 1494 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1495 if (unlikely(ret == -EINPROGRESS))
1496 break;
1497 else if (unlikely(ret)) {
1498 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1499 sc->stats.rxerr_proc++;
1500 break;
1501 }
fa1c114f 1502
8a63facc
BC		 1503 if (ath5k_receive_frame_ok(sc, &rs)) {
1504 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1505
8a63facc
BC		 1506 /*
1507 * If we can't replace bf->skb with a new skb under
1508 * memory pressure, just skip this packet
1509 */
1510 if (!next_skb)
1511 goto next;
036cd1ec 1512
aeae4ac9 1513 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1514 common->rx_bufsize,
aeae4ac9 1515 DMA_FROM_DEVICE);
036cd1ec 1516
8a63facc 1517 skb_put(skb, rs.rs_datalen);
6ba81c2c 1518
8a63facc 1519 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1520
8a63facc
BC		 1521 bf->skb = next_skb;
1522 bf->skbaddr = next_skb_addr;
036cd1ec 1523 }
8a63facc
BC		 1524next:
1525 list_move_tail(&bf->list, &sc->rxbuf);
1526 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1527unlock:
1528 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1529}
1530
b4ea449d 1531
8a63facc
BC		 1532/*************\
1533* TX Handling *
1534\*************/
b4ea449d 1535
cd2c5486
BR		 1536int
1537ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1538 struct ath5k_txq *txq)
8a63facc
BC		 1539{
1540 struct ath5k_softc *sc = hw->priv;
1541 struct ath5k_buf *bf;
1542 unsigned long flags;
1543 int padsize;
b4ea449d 1544
8a63facc 1545 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
b4ea449d 1546
8a63facc
BC		 1547 /*
1548 * The hardware expects the header padded to 4 byte boundaries.
1549 * If this is not the case, we add the padding after the header.
1550 */
1551 padsize = ath5k_add_padding(skb);
1552 if (padsize < 0) {
1553 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1554 " headroom to pad");
1555 goto drop_packet;
1556 }
8127fbdc 1557
925e0b06
BR		 1558 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1559 ieee80211_stop_queue(hw, txq->qnum);
1560
8a63facc
BC		 1561 spin_lock_irqsave(&sc->txbuflock, flags);
1562 if (list_empty(&sc->txbuf)) {
1563 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1564 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1565 ieee80211_stop_queues(hw);
8a63facc 1566 goto drop_packet;
8127fbdc 1567 }
8a63facc
BC		 1568 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1569 list_del(&bf->list);
1570 sc->txbuf_len--;
1571 if (list_empty(&sc->txbuf))
1572 ieee80211_stop_queues(hw);
1573 spin_unlock_irqrestore(&sc->txbuflock, flags);
1574
1575 bf->skb = skb;
1576
1577 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1578 bf->skb = NULL;
1579 spin_lock_irqsave(&sc->txbuflock, flags);
1580 list_add_tail(&bf->list, &sc->txbuf);
1581 sc->txbuf_len++;
1582 spin_unlock_irqrestore(&sc->txbuflock, flags);
1583 goto drop_packet;
8127fbdc 1584 }
8a63facc 1585 return NETDEV_TX_OK;
8127fbdc 1586
8a63facc
BC		 1587drop_packet:
1588 dev_kfree_skb_any(skb);
1589 return NETDEV_TX_OK;
8127fbdc
BP		 1590}
1591
1440401e
BR		 1592static void
1593ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1594 struct ath5k_tx_status *ts)
1595{
1596 struct ieee80211_tx_info *info;
1597 int i;
1598
1599 sc->stats.tx_all_count++;
b72acddb 1600 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1601 info = IEEE80211_SKB_CB(skb);
1602
1603 ieee80211_tx_info_clear_status(info);
1604 for (i = 0; i < 4; i++) {
1605 struct ieee80211_tx_rate *r =
1606 &info->status.rates[i];
1607
1608 if (ts->ts_rate[i]) {
1609 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1610 r->count = ts->ts_retry[i];
1611 } else {
1612 r->idx = -1;
1613 r->count = 0;
1614 }
1615 }
1616
1617 /* count the successful attempt as well */
1618 info->status.rates[ts->ts_final_idx].count++;
1619
1620 if (unlikely(ts->ts_status)) {
1621 sc->stats.ack_fail++;
1622 if (ts->ts_status & AR5K_TXERR_FILT) {
1623 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1624 sc->stats.txerr_filt++;
1625 }
1626 if (ts->ts_status & AR5K_TXERR_XRETRY)
1627 sc->stats.txerr_retry++;
1628 if (ts->ts_status & AR5K_TXERR_FIFO)
1629 sc->stats.txerr_fifo++;
1630 } else {
1631 info->flags |= IEEE80211_TX_STAT_ACK;
1632 info->status.ack_signal = ts->ts_rssi;
1633 }
1634
1635 /*
1636 * Remove MAC header padding before giving the frame
1637 * back to mac80211.
1638 */
1639 ath5k_remove_padding(skb);
1640
1641 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1642 sc->stats.antenna_tx[ts->ts_antenna]++;
1643 else
1644 sc->stats.antenna_tx[0]++; /* invalid */
1645
1646 ieee80211_tx_status(sc->hw, skb);
1647}
8a63facc
BC		 1648
1649static void
1650ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1651{
8a63facc
BC		 1652 struct ath5k_tx_status ts = {};
1653 struct ath5k_buf *bf, *bf0;
1654 struct ath5k_desc *ds;
1655 struct sk_buff *skb;
1440401e 1656 int ret;
8127fbdc 1657
8a63facc
BC		 1658 spin_lock(&txq->lock);
1659 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1660
1661 txq->txq_poll_mark = false;
1662
1663 /* skb might already have been processed last time. */
1664 if (bf->skb != NULL) {
1665 ds = bf->desc;
1666
1667 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1668 if (unlikely(ret == -EINPROGRESS))
1669 break;
1670 else if (unlikely(ret)) {
1671 ATH5K_ERR(sc,
1672 "error %d while processing "
1673 "queue %u\n", ret, txq->qnum);
1674 break;
1675 }
1676
1677 skb = bf->skb;
1678 bf->skb = NULL;
aeae4ac9
FF		 1679
1680 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1681 DMA_TO_DEVICE);
23413296
BR		 1682 ath5k_tx_frame_completed(sc, skb, &ts);
1683 }
8127fbdc 1684
8a63facc
BC		 1685 /*
1686 * It's possible that the hardware can say the buffer is
1687 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1688 * host memory and moved on.
1689 * Always keep the last descriptor to avoid HW races...
8a63facc 1690 */
23413296
BR		 1691 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1692 spin_lock(&sc->txbuflock);
1693 list_move_tail(&bf->list, &sc->txbuf);
1694 sc->txbuf_len++;
1695 txq->txq_len--;
1696 spin_unlock(&sc->txbuflock);
8a63facc 1697 }
fa1c114f 1698 }
fa1c114f 1699 spin_unlock(&txq->lock);
4198a8d0 1700 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1701 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1702}
1703
1704static void
1705ath5k_tasklet_tx(unsigned long data)
1706{
8784d2ee 1707 int i;
fa1c114f
JS		 1708 struct ath5k_softc *sc = (void *)data;
1709
8784d2ee
BC		 1710 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1711 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1712 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1713}
1714
1715
fa1c114f
JS		 1716/*****************\
1717* Beacon handling *
1718\*****************/
1719
1720/*
1721 * Setup the beacon frame for transmit.
1722 */
1723static int
e039fa4a 1724ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1725{
1726 struct sk_buff *skb = bf->skb;
a888d52d 1727 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1728 struct ath5k_hw *ah = sc->ah;
1729 struct ath5k_desc *ds;
2bed03eb
NK		 1730 int ret = 0;
1731 u8 antenna;
fa1c114f 1732 u32 flags;
8127fbdc 1733 const int padsize = 0;
fa1c114f 1734
aeae4ac9
FF		 1735 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1736 DMA_TO_DEVICE);
fa1c114f
JS		 1737 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1738 "skbaddr %llx\n", skb, skb->data, skb->len,
1739 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1740
1741 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1742 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1743 return -EIO;
1744 }
1745
1746 ds = bf->desc;
2bed03eb 1747 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1748
1749 flags = AR5K_TXDESC_NOACK;
05c914fe 1750 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1751 ds->ds_link = bf->daddr; /* self-linked */
1752 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1753 } else
fa1c114f 1754 ds->ds_link = 0;
2bed03eb
NK		 1755
1756 /*
1757 * If we use multiple antennas on AP and use
1758 * the Sectored AP scenario, switch antenna every
1759 * 4 beacons to make sure everybody hears our AP.
1760 * When a client tries to associate, hw will keep
1761 * track of the tx antenna to be used for this client
1762 * automaticaly, based on ACKed packets.
1763 *
1764 * Note: AP still listens and transmits RTS on the
1765 * default antenna which is supposed to be an omni.
1766 *
1767 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1768 * multiple antennas (1 omni -- the default -- and 14
1769 * sectors), so if we choose to actually support this
1770 * mode, we need to allow the user to set how many antennas
1771 * we have and tweak the code below to send beacons
1772 * on all of them.
2bed03eb
NK		 1773 */
1774 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1775 antenna = sc->bsent & 4 ? 2 : 1;
1776
fa1c114f 1777
8f655dde
NK		 1778 /* FIXME: If we are in g mode and rate is a CCK rate
1779 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1780 * from tx power (value is in dB units already) */
fa1c114f 1781 ds->ds_data = bf->skbaddr;
281c56dd 1782 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1783 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1784 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1785 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1786 1, AR5K_TXKEYIX_INVALID,
400ec45a 1787 antenna, flags, 0, 0);
fa1c114f
JS		 1788 if (ret)
1789 goto err_unmap;
1790
1791 return 0;
1792err_unmap:
aeae4ac9 1793 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1794 return ret;
1795}
1796
8a63facc
BC		 1797/*
1798 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1799 * this is called only once at config_bss time, for AP we do it every
1800 * SWBA interrupt so that the TIM will reflect buffered frames.
1801 *
1802 * Called with the beacon lock.
1803 */
cd2c5486 1804int
8a63facc
BC		 1805ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1806{
1807 int ret;
1808 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1809 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1810 struct sk_buff *skb;
1811
1812 if (WARN_ON(!vif)) {
1813 ret = -EINVAL;
1814 goto out;
1815 }
1816
1817 skb = ieee80211_beacon_get(hw, vif);
1818
1819 if (!skb) {
1820 ret = -ENOMEM;
1821 goto out;
1822 }
1823
1824 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1825
b1ae1edf
BG		 1826 ath5k_txbuf_free_skb(sc, avf->bbuf);
1827 avf->bbuf->skb = skb;
1828 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1829 if (ret)
b1ae1edf 1830 avf->bbuf->skb = NULL;
8a63facc
BC		 1831out:
1832 return ret;
1833}
1834
fa1c114f
JS		 1835/*
1836 * Transmit a beacon frame at SWBA. Dynamic updates to the
1837 * frame contents are done as needed and the slot time is
1838 * also adjusted based on current state.
1839 *
5faaff74
BC		 1840 * This is called from software irq context (beacontq tasklets)
1841 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1842 */
1843static void
1844ath5k_beacon_send(struct ath5k_softc *sc)
1845{
fa1c114f 1846 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1847 struct ieee80211_vif *vif;
1848 struct ath5k_vif *avf;
1849 struct ath5k_buf *bf;
cec8db23 1850 struct sk_buff *skb;
fa1c114f 1851
be9b7259 1852 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1853
fa1c114f
JS		 1854 /*
1855 * Check if the previous beacon has gone out. If
a180a130 1856 * not, don't don't try to post another: skip this
fa1c114f
JS		 1857 * period and wait for the next. Missed beacons
1858 * indicate a problem and should not occur. If we
1859 * miss too many consecutive beacons reset the device.
1860 */
1861 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1862 sc->bmisscount++;
be9b7259 1863 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1864 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1865 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1866 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1867 "stuck beacon time (%u missed)\n",
1868 sc->bmisscount);
8d67a031
BR		 1869 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1870 "stuck beacon, resetting\n");
5faaff74 1871 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1872 }
1873 return;
1874 }
1875 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1876 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1877 "resume beacon xmit after %u misses\n",
1878 sc->bmisscount);
1879 sc->bmisscount = 0;
1880 }
1881
b93996cf
JC		 1882 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1883 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1884 u64 tsf = ath5k_hw_get_tsf64(ah);
1885 u32 tsftu = TSF_TO_TU(tsf);
1886 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1887 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1888 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1889 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1890 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1891 } else /* only one interface */
1892 vif = sc->bslot[0];
1893
1894 if (!vif)
1895 return;
1896
1897 avf = (void *)vif->drv_priv;
1898 bf = avf->bbuf;
1899 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1900 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1901 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1902 return;
1903 }
1904
fa1c114f
JS		 1905 /*
1906 * Stop any current dma and put the new frame on the queue.
1907 * This should never fail since we check above that no frames
1908 * are still pending on the queue.
1909 */
14fae2d4 1910 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1911 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1912 /* NB: hw still stops DMA, so proceed */
1913 }
fa1c114f 1914
d82b577b
JC		 1915 /* refresh the beacon for AP or MESH mode */
1916 if (sc->opmode == NL80211_IFTYPE_AP ||
1917 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1918 ath5k_beacon_update(sc->hw, vif);
1071db86 1919
c6e387a2
NK		 1920 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1921 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1922 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1923 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1924
b1ae1edf 1925 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1926 while (skb) {
1927 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1928 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1929 }
1930
fa1c114f
JS		 1931 sc->bsent++;
1932}
1933
9804b98d
BR		 1934/**
1935 * ath5k_beacon_update_timers - update beacon timers
1936 *
1937 * @sc: struct ath5k_softc pointer we are operating on
1938 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1939 * beacon timer update based on the current HW TSF.
1940 *
1941 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1942 * of a received beacon or the current local hardware TSF and write it to the
1943 * beacon timer registers.
1944 *
1945 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1946 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1947 * when we otherwise know we have to update the timers, but we keep it in this
1948 * function to have it all together in one place.
1949 */
cd2c5486 1950void
9804b98d 1951ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1952{
1953 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1954 u32 nexttbtt, intval, hw_tu, bc_tu;
1955 u64 hw_tsf;
fa1c114f
JS		 1956
1957 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1958 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1959 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1960 if (intval < 15)
1961 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1962 intval);
1963 }
fa1c114f
JS		 1964 if (WARN_ON(!intval))
1965 return;
1966
9804b98d
BR		 1967 /* beacon TSF converted to TU */
1968 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1969
9804b98d
BR		 1970 /* current TSF converted to TU */
1971 hw_tsf = ath5k_hw_get_tsf64(ah);
1972 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1973
11f21df3
BR		 1974#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1975 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1976 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1977 * configuration we need to make sure it is bigger than that. */
1978
9804b98d
BR		 1979 if (bc_tsf == -1) {
1980 /*
1981 * no beacons received, called internally.
1982 * just need to refresh timers based on HW TSF.
1983 */
1984 nexttbtt = roundup(hw_tu + FUDGE, intval);
1985 } else if (bc_tsf == 0) {
1986 /*
1987 * no beacon received, probably called by ath5k_reset_tsf().
1988 * reset TSF to start with 0.
1989 */
1990 nexttbtt = intval;
1991 intval |= AR5K_BEACON_RESET_TSF;
1992 } else if (bc_tsf > hw_tsf) {
1993 /*
1994 * beacon received, SW merge happend but HW TSF not yet updated.
1995 * not possible to reconfigure timers yet, but next time we
1996 * receive a beacon with the same BSSID, the hardware will
1997 * automatically update the TSF and then we need to reconfigure
1998 * the timers.
1999 */
2000 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2001 "need to wait for HW TSF sync\n");
2002 return;
2003 } else {
2004 /*
2005 * most important case for beacon synchronization between STA.
2006 *
2007 * beacon received and HW TSF has been already updated by HW.
2008 * update next TBTT based on the TSF of the beacon, but make
2009 * sure it is ahead of our local TSF timer.
2010 */
2011 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2012 }
2013#undef FUDGE
fa1c114f 2014
036cd1ec
BR		 2015 sc->nexttbtt = nexttbtt;
2016
fa1c114f 2017 intval |= AR5K_BEACON_ENA;
fa1c114f 2018 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2019
2020 /*
2021 * debugging output last in order to preserve the time critical aspect
2022 * of this function
2023 */
2024 if (bc_tsf == -1)
2025 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2026 "reconfigured timers based on HW TSF\n");
2027 else if (bc_tsf == 0)
2028 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2029 "reset HW TSF and timers\n");
2030 else
2031 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2032 "updated timers based on beacon TSF\n");
2033
2034 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2035 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2036 (unsigned long long) bc_tsf,
2037 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2038 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2039 intval & AR5K_BEACON_PERIOD,
2040 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2041 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2042}
2043
036cd1ec
BR		 2044/**
2045 * ath5k_beacon_config - Configure the beacon queues and interrupts
2046 *
2047 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2048 *
036cd1ec 2049 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2050 * interrupts to detect TSF updates only.
fa1c114f 2051 */
cd2c5486 2052void
fa1c114f
JS		 2053ath5k_beacon_config(struct ath5k_softc *sc)
2054{
2055 struct ath5k_hw *ah = sc->ah;
b5f03956 2056 unsigned long flags;
fa1c114f 2057
21800491 2058 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2059 sc->bmisscount = 0;
dc1968e7 2060 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2061
21800491 2062 if (sc->enable_beacon) {
fa1c114f 2063 /*
036cd1ec
BR		 2064 * In IBSS mode we use a self-linked tx descriptor and let the
2065 * hardware send the beacons automatically. We have to load it
fa1c114f 2066 * only once here.
036cd1ec 2067 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2068 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2069 */
2070 ath5k_beaconq_config(sc);
fa1c114f 2071
036cd1ec
BR		 2072 sc->imask |= AR5K_INT_SWBA;
2073
da966bca 2074 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2075 if (ath5k_hw_hasveol(ah))
da966bca 2076 ath5k_beacon_send(sc);
da966bca
JS		 2077 } else
2078 ath5k_beacon_update_timers(sc, -1);
21800491 2079 } else {
14fae2d4 2080 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2081 }
fa1c114f 2082
c6e387a2 2083 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2084 mmiowb();
2085 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2086}
2087
428cbd4f
NK		 2088static void ath5k_tasklet_beacon(unsigned long data)
2089{
2090 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2091
2092 /*
2093 * Software beacon alert--time to send a beacon.
2094 *
2095 * In IBSS mode we use this interrupt just to
2096 * keep track of the next TBTT (target beacon
2097 * transmission time) in order to detect wether
2098 * automatic TSF updates happened.
2099 */
2100 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2101 /* XXX: only if VEOL suppported */
2102 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2103 sc->nexttbtt += sc->bintval;
2104 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2105 "SWBA nexttbtt: %x hw_tu: %x "
2106 "TSF: %llx\n",
2107 sc->nexttbtt,
2108 TSF_TO_TU(tsf),
2109 (unsigned long long) tsf);
2110 } else {
2111 spin_lock(&sc->block);
2112 ath5k_beacon_send(sc);
2113 spin_unlock(&sc->block);
2114 }
2115}
2116
fa1c114f
JS		 2117
2118/********************\
2119* Interrupt handling *
2120\********************/
2121
6a8a3f6b
BR		 2122static void
2123ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2124{
2111ac0d
BR		 2125 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2126 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2127 /* run ANI only when full calibration is not active */
2128 ah->ah_cal_next_ani = jiffies +
2129 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2130 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2131
2132 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2133 ah->ah_cal_next_full = jiffies +
2134 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2135 tasklet_schedule(&ah->ah_sc->calib);
2136 }
2137 /* we could use SWI to generate enough interrupts to meet our
2138 * calibration interval requirements, if necessary:
2139 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2140}
2141
132b1c3e 2142irqreturn_t
fa1c114f
JS		 2143ath5k_intr(int irq, void *dev_id)
2144{
2145 struct ath5k_softc *sc = dev_id;
2146 struct ath5k_hw *ah = sc->ah;
2147 enum ath5k_int status;
2148 unsigned int counter = 1000;
2149
2150 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2151 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2152 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2153 return IRQ_NONE;
2154
2155 do {
fa1c114f
JS		 2156 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2157 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2158 status, sc->imask);
fa1c114f
JS		 2159 if (unlikely(status & AR5K_INT_FATAL)) {
2160 /*
2161 * Fatal errors are unrecoverable.
2162 * Typically these are caused by DMA errors.
2163 */
8d67a031
BR		 2164 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2165 "fatal int, resetting\n");
5faaff74 2166 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2167 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2168 /*
2169 * Receive buffers are full. Either the bus is busy or
2170 * the CPU is not fast enough to process all received
2171 * frames.
2172 * Older chipsets need a reset to come out of this
2173 * condition, but we treat it as RX for newer chips.
2174 * We don't know exactly which versions need a reset -
2175 * this guess is copied from the HAL.
2176 */
2177 sc->stats.rxorn_intr++;
8d67a031
BR		 2178 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2179 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2180 "rx overrun, resetting\n");
5faaff74 2181 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2182 }
87d77c4e
BR		 2183 else
2184 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2185 } else {
2186 if (status & AR5K_INT_SWBA) {
56d2ac76 2187 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2188 }
2189 if (status & AR5K_INT_RXEOL) {
2190 /*
2191 * NB: the hardware should re-read the link when
2192 * RXE bit is written, but it doesn't work at
2193 * least on older hardware revs.
2194 */
b3f194e5 2195 sc->stats.rxeol_intr++;
fa1c114f
JS		 2196 }
2197 if (status & AR5K_INT_TXURN) {
2198 /* bump tx trigger level */
2199 ath5k_hw_update_tx_triglevel(ah, true);
2200 }
4c674c60 2201 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2202 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2203 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2204 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2205 tasklet_schedule(&sc->txtq);
2206 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2207 /* TODO */
fa1c114f
JS		 2208 }
2209 if (status & AR5K_INT_MIB) {
2111ac0d 2210 sc->stats.mib_intr++;
495391d7 2211 ath5k_hw_update_mib_counters(ah);
2111ac0d 2212 ath5k_ani_mib_intr(ah);
fa1c114f 2213 }
e6a3b616 2214 if (status & AR5K_INT_GPIO)
e6a3b616 2215 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2216
fa1c114f 2217 }
4cebb34c
FF		 2218
2219 if (ath5k_get_bus_type(ah) == ATH_AHB)
2220 break;
2221
2516baa6 2222 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2223
2224 if (unlikely(!counter))
2225 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2226
6a8a3f6b 2227 ath5k_intr_calibration_poll(ah);
6e220662 2228
fa1c114f
JS		 2229 return IRQ_HANDLED;
2230}
2231
fa1c114f
JS		 2232/*
2233 * Periodically recalibrate the PHY to account
2234 * for temperature/environment changes.
2235 */
2236static void
6e220662 2237ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2238{
2239 struct ath5k_softc *sc = (void *)data;
2240 struct ath5k_hw *ah = sc->ah;
2241
6e220662 2242 /* Only full calibration for now */
e65e1d77 2243 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2244
fa1c114f 2245 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2246 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2247 sc->curchan->hw_value);
fa1c114f 2248
6f3b414a 2249 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2250 /*
2251 * Rfgain is out of bounds, reset the chip
2252 * to load new gain values.
2253 */
2254 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2255 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2256 }
2257 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2258 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2259 ieee80211_frequency_to_channel(
2260 sc->curchan->center_freq));
fa1c114f 2261
0e8e02dd 2262 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2263 * doesn't.
2264 * TODO: We should stop TX here, so that it doesn't interfere.
2265 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2266 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2267 ah->ah_cal_next_nf = jiffies +
2268 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2269 ath5k_hw_update_noise_floor(ah);
afe86286 2270 }
6e220662 2271
e65e1d77 2272 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2273}
2274
2275
2111ac0d
BR		 2276static void
2277ath5k_tasklet_ani(unsigned long data)
2278{
2279 struct ath5k_softc *sc = (void *)data;
2280 struct ath5k_hw *ah = sc->ah;
2281
2282 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2283 ath5k_ani_calibration(ah);
2284 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2285}
2286
2287
4edd761f
BR		 2288static void
2289ath5k_tx_complete_poll_work(struct work_struct *work)
2290{
2291 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2292 tx_complete_work.work);
2293 struct ath5k_txq *txq;
2294 int i;
2295 bool needreset = false;
2296
2297 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2298 if (sc->txqs[i].setup) {
2299 txq = &sc->txqs[i];
2300 spin_lock_bh(&txq->lock);
23413296 2301 if (txq->txq_len > 1) {
4edd761f
BR		 2302 if (txq->txq_poll_mark) {
2303 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2304 "TX queue stuck %d\n",
2305 txq->qnum);
2306 needreset = true;
923e5b3d 2307 txq->txq_stuck++;
4edd761f
BR		 2308 spin_unlock_bh(&txq->lock);
2309 break;
2310 } else {
2311 txq->txq_poll_mark = true;
2312 }
2313 }
2314 spin_unlock_bh(&txq->lock);
2315 }
2316 }
2317
2318 if (needreset) {
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2320 "TX queues stuck, resetting\n");
8aec7af9 2321 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2322 }
2323
2324 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2325 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2326}
2327
2328
8a63facc
BC		 2329/*************************\
2330* Initialization routines *
2331\*************************/
fa1c114f 2332
132b1c3e
FF		 2333int
2334ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2335{
2336 struct ieee80211_hw *hw = sc->hw;
2337 struct ath_common *common;
2338 int ret;
2339 int csz;
2340
2341 /* Initialize driver private data */
2342 SET_IEEE80211_DEV(hw, sc->dev);
2343 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2344 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2345 IEEE80211_HW_SIGNAL_DBM |
2346 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2347
2348 hw->wiphy->interface_modes =
2349 BIT(NL80211_IFTYPE_AP) |
2350 BIT(NL80211_IFTYPE_STATION) |
2351 BIT(NL80211_IFTYPE_ADHOC) |
2352 BIT(NL80211_IFTYPE_MESH_POINT);
2353
3de135db
BR		 2354 /* both antennas can be configured as RX or TX */
2355 hw->wiphy->available_antennas_tx = 0x3;
2356 hw->wiphy->available_antennas_rx = 0x3;
2357
132b1c3e
FF		 2358 hw->extra_tx_headroom = 2;
2359 hw->channel_change_time = 5000;
2360
2361 /*
2362 * Mark the device as detached to avoid processing
2363 * interrupts until setup is complete.
2364 */
2365 __set_bit(ATH_STAT_INVALID, sc->status);
2366
2367 sc->opmode = NL80211_IFTYPE_STATION;
2368 sc->bintval = 1000;
2369 mutex_init(&sc->lock);
2370 spin_lock_init(&sc->rxbuflock);
2371 spin_lock_init(&sc->txbuflock);
2372 spin_lock_init(&sc->block);
2373
2374
2375 /* Setup interrupt handler */
2376 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2377 if (ret) {
2378 ATH5K_ERR(sc, "request_irq failed\n");
2379 goto err;
2380 }
2381
2382 /* If we passed the test, malloc an ath5k_hw struct */
2383 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2384 if (!sc->ah) {
2385 ret = -ENOMEM;
2386 ATH5K_ERR(sc, "out of memory\n");
2387 goto err_irq;
2388 }
2389
2390 sc->ah->ah_sc = sc;
2391 sc->ah->ah_iobase = sc->iobase;
2392 common = ath5k_hw_common(sc->ah);
2393 common->ops = &ath5k_common_ops;
2394 common->bus_ops = bus_ops;
2395 common->ah = sc->ah;
2396 common->hw = hw;
2397 common->priv = sc;
2398
2399 /*
2400 * Cache line size is used to size and align various
2401 * structures used to communicate with the hardware.
2402 */
2403 ath5k_read_cachesize(common, &csz);
2404 common->cachelsz = csz << 2; /* convert to bytes */
2405
2406 spin_lock_init(&common->cc_lock);
2407
2408 /* Initialize device */
2409 ret = ath5k_hw_init(sc);
2410 if (ret)
2411 goto err_free_ah;
2412
2413 /* set up multi-rate retry capabilities */
2414 if (sc->ah->ah_version == AR5K_AR5212) {
2415 hw->max_rates = 4;
2416 hw->max_rate_tries = 11;
2417 }
2418
2419 hw->vif_data_size = sizeof(struct ath5k_vif);
2420
2421 /* Finish private driver data initialization */
2422 ret = ath5k_init(hw);
2423 if (ret)
2424 goto err_ah;
2425
2426 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2427 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2428 sc->ah->ah_mac_srev,
2429 sc->ah->ah_phy_revision);
2430
2431 if (!sc->ah->ah_single_chip) {
2432 /* Single chip radio (!RF5111) */
2433 if (sc->ah->ah_radio_5ghz_revision &&
2434 !sc->ah->ah_radio_2ghz_revision) {
2435 /* No 5GHz support -> report 2GHz radio */
2436 if (!test_bit(AR5K_MODE_11A,
2437 sc->ah->ah_capabilities.cap_mode)) {
2438 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2439 ath5k_chip_name(AR5K_VERSION_RAD,
2440 sc->ah->ah_radio_5ghz_revision),
2441 sc->ah->ah_radio_5ghz_revision);
2442 /* No 2GHz support (5110 and some
2443 * 5Ghz only cards) -> report 5Ghz radio */
2444 } else if (!test_bit(AR5K_MODE_11B,
2445 sc->ah->ah_capabilities.cap_mode)) {
2446 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2447 ath5k_chip_name(AR5K_VERSION_RAD,
2448 sc->ah->ah_radio_5ghz_revision),
2449 sc->ah->ah_radio_5ghz_revision);
2450 /* Multiband radio */
2451 } else {
2452 ATH5K_INFO(sc, "RF%s multiband radio found"
2453 " (0x%x)\n",
2454 ath5k_chip_name(AR5K_VERSION_RAD,
2455 sc->ah->ah_radio_5ghz_revision),
2456 sc->ah->ah_radio_5ghz_revision);
2457 }
2458 }
2459 /* Multi chip radio (RF5111 - RF2111) ->
2460 * report both 2GHz/5GHz radios */
2461 else if (sc->ah->ah_radio_5ghz_revision &&
2462 sc->ah->ah_radio_2ghz_revision){
2463 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2464 ath5k_chip_name(AR5K_VERSION_RAD,
2465 sc->ah->ah_radio_5ghz_revision),
2466 sc->ah->ah_radio_5ghz_revision);
2467 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2468 ath5k_chip_name(AR5K_VERSION_RAD,
2469 sc->ah->ah_radio_2ghz_revision),
2470 sc->ah->ah_radio_2ghz_revision);
2471 }
2472 }
2473
2474 ath5k_debug_init_device(sc);
2475
2476 /* ready to process interrupts */
2477 __clear_bit(ATH_STAT_INVALID, sc->status);
2478
2479 return 0;
2480err_ah:
2481 ath5k_hw_deinit(sc->ah);
2482err_free_ah:
2483 kfree(sc->ah);
2484err_irq:
2485 free_irq(sc->irq, sc);
2486err:
2487 return ret;
2488}
2489
fa1c114f 2490static int
8a63facc 2491ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2492{
8a63facc 2493 struct ath5k_hw *ah = sc->ah;
cec8db23 2494
8a63facc
BC		 2495 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2496 test_bit(ATH_STAT_INVALID, sc->status));
2497
2498 /*
2499 * Shutdown the hardware and driver:
2500 * stop output from above
2501 * disable interrupts
2502 * turn off timers
2503 * turn off the radio
2504 * clear transmit machinery
2505 * clear receive machinery
2506 * drain and release tx queues
2507 * reclaim beacon resources
2508 * power down hardware
2509 *
2510 * Note that some of this work is not possible if the
2511 * hardware is gone (invalid).
2512 */
2513 ieee80211_stop_queues(sc->hw);
2514
2515 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2516 ath5k_led_off(sc);
2517 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2518 synchronize_irq(sc->irq);
8a63facc 2519 ath5k_rx_stop(sc);
80dac9ee
NK		 2520 ath5k_hw_dma_stop(ah);
2521 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2522 ath5k_hw_phy_disable(ah);
2523 }
2524
2525 return 0;
cec8db23
BC		 2526}
2527
cd2c5486 2528int
132b1c3e 2529ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2530{
8a63facc
BC		 2531 struct ath5k_hw *ah = sc->ah;
2532 struct ath_common *common = ath5k_hw_common(ah);
2533 int ret, i;
fa1c114f 2534
8a63facc
BC		 2535 mutex_lock(&sc->lock);
2536
2537 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2538
fa1c114f 2539 /*
8a63facc
BC		 2540 * Stop anything previously setup. This is safe
2541 * no matter this is the first time through or not.
fa1c114f 2542 */
8a63facc 2543 ath5k_stop_locked(sc);
fa1c114f 2544
8a63facc
BC		 2545 /*
2546 * The basic interface to setting the hardware in a good
2547 * state is ``reset''. On return the hardware is known to
2548 * be powered up and with interrupts disabled. This must
2549 * be followed by initialization of the appropriate bits
2550 * and then setup of the interrupt mask.
2551 */
2552 sc->curchan = sc->hw->conf.channel;
2553 sc->curband = &sc->sbands[sc->curchan->band];
2554 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2555 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2556 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2557
8aec7af9 2558 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2559 if (ret)
2560 goto done;
fa1c114f 2561
8a63facc
BC		 2562 ath5k_rfkill_hw_start(ah);
2563
2564 /*
2565 * Reset the key cache since some parts do not reset the
2566 * contents on initial power up or resume from suspend.
2567 */
2568 for (i = 0; i < common->keymax; i++)
2569 ath_hw_keyreset(common, (u16) i);
2570
61cde037
NK		 2571 /* Use higher rates for acks instead of base
2572 * rate */
2573 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2574
2575 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2576 sc->bslot[i] = NULL;
2577
8a63facc
BC		 2578 ret = 0;
2579done:
2580 mmiowb();
2581 mutex_unlock(&sc->lock);
4edd761f
BR		 2582
2583 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2584 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2585
8a63facc
BC		 2586 return ret;
2587}
2588
2589static void stop_tasklets(struct ath5k_softc *sc)
2590{
2591 tasklet_kill(&sc->rxtq);
2592 tasklet_kill(&sc->txtq);
2593 tasklet_kill(&sc->calib);
2594 tasklet_kill(&sc->beacontq);
2595 tasklet_kill(&sc->ani_tasklet);
2596}
2597
2598/*
2599 * Stop the device, grabbing the top-level lock to protect
2600 * against concurrent entry through ath5k_init (which can happen
2601 * if another thread does a system call and the thread doing the
2602 * stop is preempted).
2603 */
cd2c5486 2604int
8a63facc
BC		 2605ath5k_stop_hw(struct ath5k_softc *sc)
2606{
2607 int ret;
2608
2609 mutex_lock(&sc->lock);
2610 ret = ath5k_stop_locked(sc);
2611 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2612 /*
2613 * Don't set the card in full sleep mode!
2614 *
2615 * a) When the device is in this state it must be carefully
2616 * woken up or references to registers in the PCI clock
2617 * domain may freeze the bus (and system). This varies
2618 * by chip and is mostly an issue with newer parts
2619 * (madwifi sources mentioned srev >= 0x78) that go to
2620 * sleep more quickly.
2621 *
2622 * b) On older chips full sleep results a weird behaviour
2623 * during wakeup. I tested various cards with srev < 0x78
2624 * and they don't wake up after module reload, a second
2625 * module reload is needed to bring the card up again.
2626 *
2627 * Until we figure out what's going on don't enable
2628 * full chip reset on any chip (this is what Legacy HAL
2629 * and Sam's HAL do anyway). Instead Perform a full reset
2630 * on the device (same as initial state after attach) and
2631 * leave it idle (keep MAC/BB on warm reset) */
2632 ret = ath5k_hw_on_hold(sc->ah);
2633
2634 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2635 "putting device to sleep\n");
fa1c114f
JS		 2636 }
2637
8a63facc
BC		 2638 mmiowb();
2639 mutex_unlock(&sc->lock);
2640
2641 stop_tasklets(sc);
2642
4edd761f
BR		 2643 cancel_delayed_work_sync(&sc->tx_complete_work);
2644
8a63facc
BC		 2645 ath5k_rfkill_hw_stop(sc->ah);
2646
2647 return ret;
fa1c114f
JS		 2648}
2649
209d889b
BC		 2650/*
2651 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2652 * and change to the given channel.
5faaff74
BC		 2653 *
2654 * This should be called with sc->lock.
209d889b 2655 */
fa1c114f 2656static int
8aec7af9
NK		 2657ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2658 bool skip_pcu)
fa1c114f 2659{
fa1c114f 2660 struct ath5k_hw *ah = sc->ah;
f15a4bb2 2661 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2662 int ret, ani_mode;
fa1c114f
JS		 2663
2664 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2665
450464de 2666 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2667 synchronize_irq(sc->irq);
450464de
BC		 2668 stop_tasklets(sc);
2669
344b54b9
NK		 2670 /* Save ani mode and disable ANI durring
2671 * reset. If we don't we might get false
2672 * PHY error interrupts. */
2673 ani_mode = ah->ah_sc->ani_state.ani_mode;
2674 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2675
19252ecb
NK		 2676 /* We are going to empty hw queues
2677 * so we should also free any remaining
2678 * tx buffers */
2679 ath5k_drain_tx_buffs(sc);
209d889b 2680 if (chan) {
209d889b
BC		 2681 sc->curchan = chan;
2682 sc->curband = &sc->sbands[chan->band];
d7dc1003 2683 }
8aec7af9
NK		 2684 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2685 skip_pcu);
d7dc1003 2686 if (ret) {
fa1c114f
JS		 2687 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2688 goto err;
2689 }
d7dc1003 2690
fa1c114f 2691 ret = ath5k_rx_start(sc);
d7dc1003 2692 if (ret) {
fa1c114f
JS		 2693 ATH5K_ERR(sc, "can't start recv logic\n");
2694 goto err;
2695 }
d7dc1003 2696
344b54b9 2697 ath5k_ani_init(ah, ani_mode);
2111ac0d 2698
ac559526
BR		 2699 ah->ah_cal_next_full = jiffies;
2700 ah->ah_cal_next_ani = jiffies;
afe86286 2701 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2702 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2703
f15a4bb2
BR		 2704 /* clear survey data and cycle counters */
2705 memset(&sc->survey, 0, sizeof(sc->survey));
2706 spin_lock(&common->cc_lock);
2707 ath_hw_cycle_counters_update(common);
2708 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2709 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2710 spin_unlock(&common->cc_lock);
2711
fa1c114f 2712 /*
d7dc1003
JS		 2713 * Change channels and update the h/w rate map if we're switching;
2714 * e.g. 11a to 11b/g.
2715 *
2716 * We may be doing a reset in response to an ioctl that changes the
2717 * channel so update any state that might change as a result.
fa1c114f
JS		 2718 *
2719 * XXX needed?
2720 */
2721/* ath5k_chan_change(sc, c); */
fa1c114f 2722
d7dc1003
JS		 2723 ath5k_beacon_config(sc);
2724 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2725
397f385b
BR		 2726 ieee80211_wake_queues(sc->hw);
2727
fa1c114f
JS		 2728 return 0;
2729err:
2730 return ret;
2731}
2732
5faaff74
BC		 2733static void ath5k_reset_work(struct work_struct *work)
2734{
2735 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2736 reset_work);
2737
2738 mutex_lock(&sc->lock);
8aec7af9 2739 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2740 mutex_unlock(&sc->lock);
2741}
2742
8a63facc 2743static int
132b1c3e 2744ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2745{
132b1c3e 2746
fa1c114f 2747 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2748 struct ath5k_hw *ah = sc->ah;
2749 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2750 struct ath5k_txq *txq;
8a63facc 2751 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2752 int ret;
2753
fa1c114f 2754
8a63facc
BC		 2755 /*
2756 * Check if the MAC has multi-rate retry support.
2757 * We do this by trying to setup a fake extended
2758 * descriptor. MACs that don't have support will
2759 * return false w/o doing anything. MACs that do
2760 * support it will return true w/o doing anything.
2761 */
2762 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2763
8a63facc
BC		 2764 if (ret < 0)
2765 goto err;
2766 if (ret > 0)
2767 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2768
8a63facc
BC		 2769 /*
2770 * Collect the channel list. The 802.11 layer
2771 * is resposible for filtering this list based
2772 * on settings like the phy mode and regulatory
2773 * domain restrictions.
2774 */
2775 ret = ath5k_setup_bands(hw);
2776 if (ret) {
2777 ATH5K_ERR(sc, "can't get channels\n");
2778 goto err;
2779 }
67d2e2df 2780
8a63facc
BC		 2781 /* NB: setup here so ath5k_rate_update is happy */
2782 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2783 ath5k_setcurmode(sc, AR5K_MODE_11A);
2784 else
2785 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2786
8a63facc
BC		 2787 /*
2788 * Allocate tx+rx descriptors and populate the lists.
2789 */
aeae4ac9 2790 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2791 if (ret) {
2792 ATH5K_ERR(sc, "can't allocate descriptors\n");
2793 goto err;
2794 }
fa1c114f 2795
8a63facc
BC		 2796 /*
2797 * Allocate hardware transmit queues: one queue for
2798 * beacon frames and one data queue for each QoS
2799 * priority. Note that hw functions handle resetting
2800 * these queues at the needed time.
2801 */
2802 ret = ath5k_beaconq_setup(ah);
2803 if (ret < 0) {
2804 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2805 goto err_desc;
2806 }
2807 sc->bhalq = ret;
2808 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2809 if (IS_ERR(sc->cabq)) {
2810 ATH5K_ERR(sc, "can't setup cab queue\n");
2811 ret = PTR_ERR(sc->cabq);
2812 goto err_bhal;
2813 }
fa1c114f 2814
22d8d9f8
BR		 2815 /* 5211 and 5212 usually support 10 queues but we better rely on the
2816 * capability information */
2817 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2818 /* This order matches mac80211's queue priority, so we can
2819 * directly use the mac80211 queue number without any mapping */
2820 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2821 if (IS_ERR(txq)) {
2822 ATH5K_ERR(sc, "can't setup xmit queue\n");
2823 ret = PTR_ERR(txq);
2824 goto err_queues;
2825 }
2826 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2827 if (IS_ERR(txq)) {
2828 ATH5K_ERR(sc, "can't setup xmit queue\n");
2829 ret = PTR_ERR(txq);
2830 goto err_queues;
2831 }
2832 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2833 if (IS_ERR(txq)) {
2834 ATH5K_ERR(sc, "can't setup xmit queue\n");
2835 ret = PTR_ERR(txq);
2836 goto err_queues;
2837 }
2838 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2839 if (IS_ERR(txq)) {
2840 ATH5K_ERR(sc, "can't setup xmit queue\n");
2841 ret = PTR_ERR(txq);
2842 goto err_queues;
2843 }
2844 hw->queues = 4;
2845 } else {
2846 /* older hardware (5210) can only support one data queue */
2847 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2848 if (IS_ERR(txq)) {
2849 ATH5K_ERR(sc, "can't setup xmit queue\n");
2850 ret = PTR_ERR(txq);
2851 goto err_queues;
2852 }
2853 hw->queues = 1;
2854 }
fa1c114f 2855
8a63facc
BC		 2856 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2857 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2858 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2859 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2860 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2861
8a63facc 2862 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2863 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2864
8a63facc
BC		 2865 ret = ath5k_eeprom_read_mac(ah, mac);
2866 if (ret) {
aeae4ac9 2867 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2868 goto err_queues;
e30eb4ab 2869 }
2bed03eb 2870
8a63facc 2871 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2872 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2873 /* All MAC address bits matter for ACKs */
62c58fb4 2874 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2875
2876 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2877 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2878 if (ret) {
2879 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2880 goto err_queues;
2881 }
2882
2883 ret = ieee80211_register_hw(hw);
2884 if (ret) {
2885 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2886 goto err_queues;
2887 }
2888
2889 if (!ath_is_world_regd(regulatory))
2890 regulatory_hint(hw->wiphy, regulatory->alpha2);
2891
2892 ath5k_init_leds(sc);
2893
2894 ath5k_sysfs_register(sc);
2895
2896 return 0;
2897err_queues:
2898 ath5k_txq_release(sc);
2899err_bhal:
2900 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2901err_desc:
aeae4ac9 2902 ath5k_desc_free(sc);
8a63facc
BC		 2903err:
2904 return ret;
2905}
2906
132b1c3e
FF		 2907void
2908ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2909{
132b1c3e 2910 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2911
2912 /*
2913 * NB: the order of these is important:
2914 * o call the 802.11 layer before detaching ath5k_hw to
2915 * ensure callbacks into the driver to delete global
2916 * key cache entries can be handled
2917 * o reclaim the tx queue data structures after calling
2918 * the 802.11 layer as we'll get called back to reclaim
2919 * node state and potentially want to use them
2920 * o to cleanup the tx queues the hal is called, so detach
2921 * it last
2922 * XXX: ??? detach ath5k_hw ???
2923 * Other than that, it's straightforward...
2924 */
132b1c3e 2925 ath5k_debug_finish_device(sc);
8a63facc 2926 ieee80211_unregister_hw(hw);
aeae4ac9 2927 ath5k_desc_free(sc);
8a63facc
BC		 2928 ath5k_txq_release(sc);
2929 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2930 ath5k_unregister_leds(sc);
2931
2932 ath5k_sysfs_unregister(sc);
2933 /*
2934 * NB: can't reclaim these until after ieee80211_ifdetach
2935 * returns because we'll get called back to reclaim node
2936 * state and potentially want to use them.
2937 */
132b1c3e
FF		 2938 ath5k_hw_deinit(sc->ah);
2939 free_irq(sc->irq, sc);
8a63facc
BC		 2940}
2941
cd2c5486
BR		 2942bool
2943ath_any_vif_assoc(struct ath5k_softc *sc)
b1ae1edf
BG		 2944{
2945 struct ath_vif_iter_data iter_data;
2946 iter_data.hw_macaddr = NULL;
2947 iter_data.any_assoc = false;
2948 iter_data.need_set_hw_addr = false;
2949 iter_data.found_active = true;
2950
2951 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
2952 &iter_data);
2953 return iter_data.any_assoc;
2954}
2955
cd2c5486 2956void
8a63facc
BC		 2957set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2958{
2959 struct ath5k_softc *sc = hw->priv;
2960 struct ath5k_hw *ah = sc->ah;
2961 u32 rfilt;
2962 rfilt = ath5k_hw_get_rx_filter(ah);
2963 if (enable)
2964 rfilt |= AR5K_RX_FILTER_BEACON;
2965 else
2966 rfilt &= ~AR5K_RX_FILTER_BEACON;
2967 ath5k_hw_set_rx_filter(ah, rfilt);
2968 sc->filter_flags = rfilt;
2969}
Linux kernel - Deliverables
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