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rtl8192ce: Fix build on powerpc
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
9ad9a26e 64static int modparam_nohwcrypt;
46802a4f 65module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 66MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 67
42639fcd 68static int modparam_all_channels;
46802a4f 69module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 70MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
fa1c114f
JS		 72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 78
132b1c3e 79static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 80static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
81 bool skip_pcu);
8a63facc
BC		 82static int ath5k_beacon_update(struct ieee80211_hw *hw,
83 struct ieee80211_vif *vif);
84static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f 85
fa1c114f 86/* Known SREVs */
2c91108c 87static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 88#ifdef CONFIG_ATHEROS_AR231X
89 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
90 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
91 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
92 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
93 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
94 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
95 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
96#else
1bef016a
NK		 97 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
98 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
99 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
100 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
101 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
102 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
103 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
104 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
105 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
106 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
107 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
108 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
109 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
110 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
111 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
112 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
113 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
114 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 115#endif
1bef016a 116 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 117 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
118 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 119 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 120 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
121 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
122 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 123 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 124 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
125 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 126 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
127 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
128 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 129 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 130 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 131#ifdef CONFIG_ATHEROS_AR231X
132 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
133 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
134#endif
fa1c114f
JS		 135 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
136};
137
2c91108c 138static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 139 { .bitrate = 10,
140 .hw_value = ATH5K_RATE_CODE_1M, },
141 { .bitrate = 20,
142 .hw_value = ATH5K_RATE_CODE_2M,
143 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
144 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
145 { .bitrate = 55,
146 .hw_value = ATH5K_RATE_CODE_5_5M,
147 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
148 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
149 { .bitrate = 110,
150 .hw_value = ATH5K_RATE_CODE_11M,
151 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
152 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 { .bitrate = 60,
154 .hw_value = ATH5K_RATE_CODE_6M,
155 .flags = 0 },
156 { .bitrate = 90,
157 .hw_value = ATH5K_RATE_CODE_9M,
158 .flags = 0 },
159 { .bitrate = 120,
160 .hw_value = ATH5K_RATE_CODE_12M,
161 .flags = 0 },
162 { .bitrate = 180,
163 .hw_value = ATH5K_RATE_CODE_18M,
164 .flags = 0 },
165 { .bitrate = 240,
166 .hw_value = ATH5K_RATE_CODE_24M,
167 .flags = 0 },
168 { .bitrate = 360,
169 .hw_value = ATH5K_RATE_CODE_36M,
170 .flags = 0 },
171 { .bitrate = 480,
172 .hw_value = ATH5K_RATE_CODE_48M,
173 .flags = 0 },
174 { .bitrate = 540,
175 .hw_value = ATH5K_RATE_CODE_54M,
176 .flags = 0 },
177 /* XR missing */
178};
179
9e4e43f2 180static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 181 struct ath5k_buf *bf)
182{
183 BUG_ON(!bf);
184 if (!bf->skb)
185 return;
aeae4ac9
FF		 186 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
187 DMA_TO_DEVICE);
00482973 188 dev_kfree_skb_any(bf->skb);
fa1c114f 189 bf->skb = NULL;
39d63f2a
BR		 190 bf->skbaddr = 0;
191 bf->desc->ds_data = 0;
fa1c114f
JS		 192}
193
9e4e43f2 194static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 195 struct ath5k_buf *bf)
196{
cc861f74
LR		 197 struct ath5k_hw *ah = sc->ah;
198 struct ath_common *common = ath5k_hw_common(ah);
199
a6c8d375
FF		 200 BUG_ON(!bf);
201 if (!bf->skb)
202 return;
aeae4ac9
FF		 203 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
204 DMA_FROM_DEVICE);
a6c8d375
FF		 205 dev_kfree_skb_any(bf->skb);
206 bf->skb = NULL;
39d63f2a
BR		 207 bf->skbaddr = 0;
208 bf->desc->ds_data = 0;
a6c8d375
FF		 209}
210
211
fa1c114f
JS		 212static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
213{
214 u64 tsf = ath5k_hw_get_tsf64(ah);
215
216 if ((tsf & 0x7fff) < rstamp)
217 tsf -= 0x8000;
218
219 return (tsf & ~0x7fff) | rstamp;
220}
221
e5b046d8 222const char *
fa1c114f
JS		 223ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
224{
225 const char *name = "xxxxx";
226 unsigned int i;
227
228 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
229 if (srev_names[i].sr_type != type)
230 continue;
75d0edb8
NK		 231
232 if ((val & 0xf0) == srev_names[i].sr_val)
233 name = srev_names[i].sr_name;
234
235 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 236 name = srev_names[i].sr_name;
237 break;
238 }
239 }
240
241 return name;
242}
e5aa8474
LR		 243static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
244{
245 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
246 return ath5k_hw_reg_read(ah, reg_offset);
247}
248
249static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
250{
251 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
252 ath5k_hw_reg_write(ah, val, reg_offset);
253}
254
255static const struct ath_ops ath5k_common_ops = {
256 .read = ath5k_ioread32,
257 .write = ath5k_iowrite32,
258};
fa1c114f 259
8a63facc
BC		 260/***********************\
261* Driver Initialization *
262\***********************/
263
264static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 265{
8a63facc
BC		 266 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
267 struct ath5k_softc *sc = hw->priv;
268 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 269
8a63facc
BC		 270 return ath_reg_notifier_apply(wiphy, request, regulatory);
271}
6ccf15a1 272
8a63facc
BC		 273/********************\
274* Channel/mode setup *
275\********************/
fa1c114f 276
8a63facc
BC		 277/*
278 * Convert IEEE channel number to MHz frequency.
279 */
280static inline short
281ath5k_ieee2mhz(short chan)
282{
283 if (chan <= 14 || chan >= 27)
284 return ieee80211chan2mhz(chan);
285 else
286 return 2212 + chan * 20;
287}
fa1c114f 288
8a63facc
BC		 289/*
290 * Returns true for the channel numbers used without all_channels modparam.
291 */
292static bool ath5k_is_standard_channel(short chan)
293{
294 return ((chan <= 14) ||
295 /* UNII 1,2 */
296 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
297 /* midband */
298 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
299 /* UNII-3 */
300 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
301}
fa1c114f 302
8a63facc
BC		 303static unsigned int
304ath5k_copy_channels(struct ath5k_hw *ah,
305 struct ieee80211_channel *channels,
306 unsigned int mode,
307 unsigned int max)
308{
309 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f 310
8a63facc
BC		 311 if (!test_bit(mode, ah->ah_modes))
312 return 0;
fa1c114f 313
8a63facc
BC		 314 switch (mode) {
315 case AR5K_MODE_11A:
8a63facc
BC		 316 /* 1..220, but 2GHz frequencies are filtered by check_channel */
317 size = 220 ;
318 chfreq = CHANNEL_5GHZ;
319 break;
320 case AR5K_MODE_11B:
321 case AR5K_MODE_11G:
8a63facc
BC		 322 size = 26;
323 chfreq = CHANNEL_2GHZ;
324 break;
325 default:
326 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
327 return 0;
fa1c114f
JS		 328 }
329
8a63facc
BC		 330 for (i = 0, count = 0; i < size && max > 0; i++) {
331 ch = i + 1 ;
332 freq = ath5k_ieee2mhz(ch);
fa1c114f 333
8a63facc
BC		 334 /* Check if channel is supported by the chipset */
335 if (!ath5k_channel_ok(ah, freq, chfreq))
336 continue;
f59ac048 337
8a63facc
BC		 338 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
339 continue;
f59ac048 340
8a63facc
BC		 341 /* Write channel info and increment counter */
342 channels[count].center_freq = freq;
343 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
344 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
345 switch (mode) {
346 case AR5K_MODE_11A:
347 case AR5K_MODE_11G:
348 channels[count].hw_value = chfreq | CHANNEL_OFDM;
349 break;
8a63facc
BC		 350 case AR5K_MODE_11B:
351 channels[count].hw_value = CHANNEL_B;
352 }
fa1c114f 353
8a63facc
BC		 354 count++;
355 max--;
356 }
fa1c114f 357
8a63facc
BC		 358 return count;
359}
fa1c114f 360
8a63facc
BC		 361static void
362ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
363{
364 u8 i;
fa1c114f 365
8a63facc
BC		 366 for (i = 0; i < AR5K_MAX_RATES; i++)
367 sc->rate_idx[b->band][i] = -1;
fa1c114f 368
8a63facc
BC		 369 for (i = 0; i < b->n_bitrates; i++) {
370 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
371 if (b->bitrates[i].hw_value_short)
372 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 373 }
8a63facc 374}
fa1c114f 375
8a63facc
BC		 376static int
377ath5k_setup_bands(struct ieee80211_hw *hw)
378{
379 struct ath5k_softc *sc = hw->priv;
380 struct ath5k_hw *ah = sc->ah;
381 struct ieee80211_supported_band *sband;
382 int max_c, count_c = 0;
383 int i;
fa1c114f 384
8a63facc
BC		 385 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
386 max_c = ARRAY_SIZE(sc->channels);
db719718 387
8a63facc
BC		 388 /* 2GHz band */
389 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
390 sband->band = IEEE80211_BAND_2GHZ;
391 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 392
8a63facc
BC		 393 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
394 /* G mode */
395 memcpy(sband->bitrates, &ath5k_rates[0],
396 sizeof(struct ieee80211_rate) * 12);
397 sband->n_bitrates = 12;
2f7fe870 398
8a63facc
BC		 399 sband->channels = sc->channels;
400 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
401 AR5K_MODE_11G, max_c);
fa1c114f 402
8a63facc
BC		 403 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
404 count_c = sband->n_channels;
405 max_c -= count_c;
406 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
407 /* B mode */
408 memcpy(sband->bitrates, &ath5k_rates[0],
409 sizeof(struct ieee80211_rate) * 4);
410 sband->n_bitrates = 4;
fa1c114f 411
8a63facc
BC		 412 /* 5211 only supports B rates and uses 4bit rate codes
413 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
414 * fix them up here:
415 */
416 if (ah->ah_version == AR5K_AR5211) {
417 for (i = 0; i < 4; i++) {
418 sband->bitrates[i].hw_value =
419 sband->bitrates[i].hw_value & 0xF;
420 sband->bitrates[i].hw_value_short =
421 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 422 }
423 }
fa1c114f 424
8a63facc
BC		 425 sband->channels = sc->channels;
426 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
427 AR5K_MODE_11B, max_c);
fa1c114f 428
8a63facc
BC		 429 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
430 count_c = sband->n_channels;
431 max_c -= count_c;
432 }
433 ath5k_setup_rate_idx(sc, sband);
fa1c114f 434
8a63facc
BC		 435 /* 5GHz band, A mode */
436 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
437 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
438 sband->band = IEEE80211_BAND_5GHZ;
439 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 440
8a63facc
BC		 441 memcpy(sband->bitrates, &ath5k_rates[4],
442 sizeof(struct ieee80211_rate) * 8);
443 sband->n_bitrates = 8;
fa1c114f 444
8a63facc
BC		 445 sband->channels = &sc->channels[count_c];
446 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
447 AR5K_MODE_11A, max_c);
fa1c114f 448
8a63facc
BC		 449 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
450 }
451 ath5k_setup_rate_idx(sc, sband);
452
453 ath5k_debug_dump_bands(sc);
fa1c114f 454
fa1c114f
JS		 455 return 0;
456}
457
8a63facc
BC		 458/*
459 * Set/change channels. We always reset the chip.
460 * To accomplish this we must first cleanup any pending DMA,
461 * then restart stuff after a la ath5k_init.
462 *
463 * Called with sc->lock.
464 */
465static int
466ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
467{
468 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
469 "channel set, resetting (%u -> %u MHz)\n",
470 sc->curchan->center_freq, chan->center_freq);
471
8451d22d 472 /*
8a63facc
BC		 473 * To switch channels clear any pending DMA operations;
474 * wait long enough for the RX fifo to drain, reset the
475 * hardware at the new frequency, and then re-enable
476 * the relevant bits of the h/w.
8451d22d 477 */
8aec7af9 478 return ath5k_reset(sc, chan, true);
fa1c114f 479}
fa1c114f 480
8a63facc
BC		 481static void
482ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 483{
8a63facc 484 sc->curmode = mode;
f769c36b 485
8a63facc
BC		 486 if (mode == AR5K_MODE_11A) {
487 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
488 } else {
489 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
490 }
f769c36b
BC		 491}
492
b1ae1edf
BG		 493struct ath_vif_iter_data {
494 const u8 *hw_macaddr;
495 u8 mask[ETH_ALEN];
496 u8 active_mac[ETH_ALEN]; /* first active MAC */
497 bool need_set_hw_addr;
498 bool found_active;
499 bool any_assoc;
62c58fb4 500 enum nl80211_iftype opmode;
b1ae1edf
BG		 501};
502
503static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
504{
505 struct ath_vif_iter_data *iter_data = data;
506 int i;
62c58fb4 507 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 508
509 if (iter_data->hw_macaddr)
510 for (i = 0; i < ETH_ALEN; i++)
511 iter_data->mask[i] &=
512 ~(iter_data->hw_macaddr[i] ^ mac[i]);
513
514 if (!iter_data->found_active) {
515 iter_data->found_active = true;
516 memcpy(iter_data->active_mac, mac, ETH_ALEN);
517 }
518
519 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
520 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
521 iter_data->need_set_hw_addr = false;
522
523 if (!iter_data->any_assoc) {
b1ae1edf
BG		 524 if (avf->assoc)
525 iter_data->any_assoc = true;
526 }
62c58fb4
BG		 527
528 /* Calculate combined mode - when APs are active, operate in AP mode.
529 * Otherwise use the mode of the new interface. This can currently
530 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 531 * interfaces is allowed.
62c58fb4
BG		 532 */
533 if (avf->opmode == NL80211_IFTYPE_AP)
534 iter_data->opmode = NL80211_IFTYPE_AP;
535 else
536 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
537 iter_data->opmode = avf->opmode;
b1ae1edf
BG		 538}
539
14fb7c17
LR		 540static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
541 struct ieee80211_vif *vif)
b1ae1edf
BG		 542{
543 struct ath_common *common = ath5k_hw_common(sc->ah);
544 struct ath_vif_iter_data iter_data;
545
546 /*
547 * Use the hardware MAC address as reference, the hardware uses it
548 * together with the BSSID mask when matching addresses.
549 */
550 iter_data.hw_macaddr = common->macaddr;
551 memset(&iter_data.mask, 0xff, ETH_ALEN);
552 iter_data.found_active = false;
553 iter_data.need_set_hw_addr = true;
62c58fb4 554 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
b1ae1edf
BG		 555
556 if (vif)
557 ath_vif_iter(&iter_data, vif->addr, vif);
558
559 /* Get list of all active MAC addresses */
560 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
561 &iter_data);
562 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
563
62c58fb4
BG		 564 sc->opmode = iter_data.opmode;
565 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
566 /* Nothing active, default to station mode */
567 sc->opmode = NL80211_IFTYPE_STATION;
568
7afbb2f0
BG		 569 ath5k_hw_set_opmode(sc->ah, sc->opmode);
570 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
571 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 572
b1ae1edf
BG		 573 if (iter_data.need_set_hw_addr && iter_data.found_active)
574 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
575
62c58fb4
BG		 576 if (ath5k_hw_hasbssidmask(sc->ah))
577 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf
BG		 578}
579
8a63facc 580static void
b1ae1edf 581ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
fa1c114f 582{
fa1c114f 583 struct ath5k_hw *ah = sc->ah;
8a63facc 584 u32 rfilt;
fa1c114f 585
8a63facc
BC		 586 /* configure rx filter */
587 rfilt = sc->filter_flags;
588 ath5k_hw_set_rx_filter(ah, rfilt);
8a63facc 589 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
62c58fb4
BG		 590
591 ath5k_update_bssid_mask_and_opmode(sc, vif);
8a63facc 592}
fa1c114f 593
8a63facc
BC		 594static inline int
595ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
596{
597 int rix;
fa1c114f 598
8a63facc
BC		 599 /* return base rate on errors */
600 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
601 "hw_rix out of bounds: %x\n", hw_rix))
602 return 0;
603
604 rix = sc->rate_idx[sc->curband->band][hw_rix];
605 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
606 rix = 0;
607
608 return rix;
609}
610
611/***************\
612* Buffers setup *
613\***************/
614
615static
616struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
617{
618 struct ath_common *common = ath5k_hw_common(sc->ah);
619 struct sk_buff *skb;
fa1c114f
JS		 620
621 /*
8a63facc
BC		 622 * Allocate buffer with headroom_needed space for the
623 * fake physical layer header at the start.
fa1c114f 624 */
8a63facc
BC		 625 skb = ath_rxbuf_alloc(common,
626 common->rx_bufsize,
627 GFP_ATOMIC);
fa1c114f 628
8a63facc
BC		 629 if (!skb) {
630 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
631 common->rx_bufsize);
632 return NULL;
fa1c114f
JS		 633 }
634
aeae4ac9 635 *skb_addr = dma_map_single(sc->dev,
8a63facc 636 skb->data, common->rx_bufsize,
aeae4ac9
FF		 637 DMA_FROM_DEVICE);
638
639 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 640 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
641 dev_kfree_skb(skb);
642 return NULL;
0e149cf5 643 }
8a63facc
BC		 644 return skb;
645}
0e149cf5 646
8a63facc
BC		 647static int
648ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
649{
650 struct ath5k_hw *ah = sc->ah;
651 struct sk_buff *skb = bf->skb;
652 struct ath5k_desc *ds;
653 int ret;
fa1c114f 654
8a63facc
BC		 655 if (!skb) {
656 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
657 if (!skb)
658 return -ENOMEM;
659 bf->skb = skb;
f769c36b
BC		 660 }
661
8a63facc
BC		 662 /*
663 * Setup descriptors. For receive we always terminate
664 * the descriptor list with a self-linked entry so we'll
665 * not get overrun under high load (as can happen with a
666 * 5212 when ANI processing enables PHY error frames).
667 *
668 * To ensure the last descriptor is self-linked we create
669 * each descriptor as self-linked and add it to the end. As
670 * each additional descriptor is added the previous self-linked
671 * entry is "fixed" naturally. This should be safe even
672 * if DMA is happening. When processing RX interrupts we
673 * never remove/process the last, self-linked, entry on the
674 * descriptor list. This ensures the hardware always has
675 * someplace to write a new frame.
676 */
677 ds = bf->desc;
678 ds->ds_link = bf->daddr; /* link to self */
679 ds->ds_data = bf->skbaddr;
680 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 681 if (ret) {
8a63facc
BC		 682 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
683 return ret;
fa1c114f
JS		 684 }
685
8a63facc
BC		 686 if (sc->rxlink != NULL)
687 *sc->rxlink = bf->daddr;
688 sc->rxlink = &ds->ds_link;
fa1c114f 689 return 0;
fa1c114f
JS		 690}
691
8a63facc 692static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 693{
8a63facc
BC		 694 struct ieee80211_hdr *hdr;
695 enum ath5k_pkt_type htype;
696 __le16 fc;
fa1c114f 697
8a63facc
BC		 698 hdr = (struct ieee80211_hdr *)skb->data;
699 fc = hdr->frame_control;
fa1c114f 700
8a63facc
BC		 701 if (ieee80211_is_beacon(fc))
702 htype = AR5K_PKT_TYPE_BEACON;
703 else if (ieee80211_is_probe_resp(fc))
704 htype = AR5K_PKT_TYPE_PROBE_RESP;
705 else if (ieee80211_is_atim(fc))
706 htype = AR5K_PKT_TYPE_ATIM;
707 else if (ieee80211_is_pspoll(fc))
708 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 709 else
8a63facc 710 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 711
8a63facc 712 return htype;
42639fcd
BC		 713}
714
8a63facc
BC		 715static int
716ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
717 struct ath5k_txq *txq, int padsize)
fa1c114f 718{
8a63facc
BC		 719 struct ath5k_hw *ah = sc->ah;
720 struct ath5k_desc *ds = bf->desc;
721 struct sk_buff *skb = bf->skb;
722 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
723 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
724 struct ieee80211_rate *rate;
725 unsigned int mrr_rate[3], mrr_tries[3];
726 int i, ret;
727 u16 hw_rate;
728 u16 cts_rate = 0;
729 u16 duration = 0;
730 u8 rc_flags;
fa1c114f 731
8a63facc 732 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 733
8a63facc 734 /* XXX endianness */
aeae4ac9
FF		 735 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
736 DMA_TO_DEVICE);
fa1c114f 737
8a63facc 738 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 739 if (!rate) {
740 ret = -EINVAL;
741 goto err_unmap;
742 }
fa1c114f 743
8a63facc
BC		 744 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
745 flags |= AR5K_TXDESC_NOACK;
fa1c114f 746
8a63facc
BC		 747 rc_flags = info->control.rates[0].flags;
748 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
749 rate->hw_value_short : rate->hw_value;
42639fcd 750
8a63facc
BC		 751 pktlen = skb->len;
752
753 /* FIXME: If we are in g mode and rate is a CCK rate
754 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
755 * from tx power (value is in dB units already) */
756 if (info->control.hw_key) {
757 keyidx = info->control.hw_key->hw_key_idx;
758 pktlen += info->control.hw_key->icv_len;
759 }
760 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
761 flags |= AR5K_TXDESC_RTSENA;
762 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
763 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 764 info->control.vif, pktlen, info));
8a63facc
BC		 765 }
766 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
767 flags |= AR5K_TXDESC_CTSENA;
768 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
769 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 770 info->control.vif, pktlen, info));
8a63facc
BC		 771 }
772 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
773 ieee80211_get_hdrlen_from_skb(skb), padsize,
774 get_hw_packet_type(skb),
775 (sc->power_level * 2),
776 hw_rate,
777 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
778 cts_rate, duration);
779 if (ret)
780 goto err_unmap;
781
782 memset(mrr_rate, 0, sizeof(mrr_rate));
783 memset(mrr_tries, 0, sizeof(mrr_tries));
784 for (i = 0; i < 3; i++) {
785 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
786 if (!rate)
400ec45a 787 break;
fa1c114f 788
8a63facc
BC		 789 mrr_rate[i] = rate->hw_value;
790 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 791 }
792
8a63facc
BC		 793 ath5k_hw_setup_mrr_tx_desc(ah, ds,
794 mrr_rate[0], mrr_tries[0],
795 mrr_rate[1], mrr_tries[1],
796 mrr_rate[2], mrr_tries[2]);
fa1c114f 797
8a63facc
BC		 798 ds->ds_link = 0;
799 ds->ds_data = bf->skbaddr;
63266a65 800
8a63facc
BC		 801 spin_lock_bh(&txq->lock);
802 list_add_tail(&bf->list, &txq->q);
925e0b06 803 txq->txq_len++;
8a63facc
BC		 804 if (txq->link == NULL) /* is this first packet? */
805 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
806 else /* no, so only link it */
807 *txq->link = bf->daddr;
63266a65 808
8a63facc
BC		 809 txq->link = &ds->ds_link;
810 ath5k_hw_start_tx_dma(ah, txq->qnum);
811 mmiowb();
812 spin_unlock_bh(&txq->lock);
813
814 return 0;
815err_unmap:
aeae4ac9 816 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 817 return ret;
63266a65
BR		 818}
819
8a63facc
BC		 820/*******************\
821* Descriptors setup *
822\*******************/
823
d8ee398d 824static int
aeae4ac9 825ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 826{
8a63facc
BC		 827 struct ath5k_desc *ds;
828 struct ath5k_buf *bf;
829 dma_addr_t da;
830 unsigned int i;
831 int ret;
d8ee398d 832
8a63facc
BC		 833 /* allocate descriptors */
834 sc->desc_len = sizeof(struct ath5k_desc) *
835 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 836
837 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
838 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 839 if (sc->desc == NULL) {
840 ATH5K_ERR(sc, "can't allocate descriptors\n");
841 ret = -ENOMEM;
842 goto err;
843 }
844 ds = sc->desc;
845 da = sc->desc_daddr;
846 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
847 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 848
8a63facc
BC		 849 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
850 sizeof(struct ath5k_buf), GFP_KERNEL);
851 if (bf == NULL) {
852 ATH5K_ERR(sc, "can't allocate bufptr\n");
853 ret = -ENOMEM;
854 goto err_free;
855 }
856 sc->bufptr = bf;
fa1c114f 857
8a63facc
BC		 858 INIT_LIST_HEAD(&sc->rxbuf);
859 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
860 bf->desc = ds;
861 bf->daddr = da;
862 list_add_tail(&bf->list, &sc->rxbuf);
863 }
d8ee398d 864
8a63facc
BC		 865 INIT_LIST_HEAD(&sc->txbuf);
866 sc->txbuf_len = ATH_TXBUF;
867 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
868 da += sizeof(*ds)) {
869 bf->desc = ds;
870 bf->daddr = da;
871 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 872 }
873
b1ae1edf
BG		 874 /* beacon buffers */
875 INIT_LIST_HEAD(&sc->bcbuf);
876 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
877 bf->desc = ds;
878 bf->daddr = da;
879 list_add_tail(&bf->list, &sc->bcbuf);
880 }
fa1c114f 881
8a63facc
BC		 882 return 0;
883err_free:
aeae4ac9 884 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 885err:
886 sc->desc = NULL;
887 return ret;
888}
fa1c114f 889
8a63facc 890static void
aeae4ac9 891ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 892{
893 struct ath5k_buf *bf;
d8ee398d 894
8a63facc
BC		 895 list_for_each_entry(bf, &sc->txbuf, list)
896 ath5k_txbuf_free_skb(sc, bf);
897 list_for_each_entry(bf, &sc->rxbuf, list)
898 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 899 list_for_each_entry(bf, &sc->bcbuf, list)
900 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 901
8a63facc 902 /* Free memory associated with all descriptors */
aeae4ac9 903 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 904 sc->desc = NULL;
905 sc->desc_daddr = 0;
d8ee398d 906
8a63facc
BC		 907 kfree(sc->bufptr);
908 sc->bufptr = NULL;
fa1c114f
JS		 909}
910
8a63facc
BC		 911
912/**************\
913* Queues setup *
914\**************/
915
916static struct ath5k_txq *
917ath5k_txq_setup(struct ath5k_softc *sc,
918 int qtype, int subtype)
fa1c114f 919{
8a63facc
BC		 920 struct ath5k_hw *ah = sc->ah;
921 struct ath5k_txq *txq;
922 struct ath5k_txq_info qi = {
923 .tqi_subtype = subtype,
de8af455
BR		 924 /* XXX: default values not correct for B and XR channels,
925 * but who cares? */
926 .tqi_aifs = AR5K_TUNE_AIFS,
927 .tqi_cw_min = AR5K_TUNE_CWMIN,
928 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 929 };
930 int qnum;
d8ee398d 931
e30eb4ab 932 /*
8a63facc
BC		 933 * Enable interrupts only for EOL and DESC conditions.
934 * We mark tx descriptors to receive a DESC interrupt
935 * when a tx queue gets deep; otherwise we wait for the
936 * EOL to reap descriptors. Note that this is done to
937 * reduce interrupt load and this only defers reaping
938 * descriptors, never transmitting frames. Aside from
939 * reducing interrupts this also permits more concurrency.
940 * The only potential downside is if the tx queue backs
941 * up in which case the top half of the kernel may backup
942 * due to a lack of tx descriptors.
e30eb4ab 943 */
8a63facc
BC		 944 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
945 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
946 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
947 if (qnum < 0) {
948 /*
949 * NB: don't print a message, this happens
950 * normally on parts with too few tx queues
951 */
952 return ERR_PTR(qnum);
953 }
954 if (qnum >= ARRAY_SIZE(sc->txqs)) {
955 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
956 qnum, ARRAY_SIZE(sc->txqs));
957 ath5k_hw_release_tx_queue(ah, qnum);
958 return ERR_PTR(-EINVAL);
959 }
960 txq = &sc->txqs[qnum];
961 if (!txq->setup) {
962 txq->qnum = qnum;
963 txq->link = NULL;
964 INIT_LIST_HEAD(&txq->q);
965 spin_lock_init(&txq->lock);
966 txq->setup = true;
925e0b06 967 txq->txq_len = 0;
4edd761f 968 txq->txq_poll_mark = false;
923e5b3d 969 txq->txq_stuck = 0;
8a63facc
BC		 970 }
971 return &sc->txqs[qnum];
fa1c114f
JS		 972}
973
8a63facc
BC		 974static int
975ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 976{
8a63facc 977 struct ath5k_txq_info qi = {
de8af455
BR		 978 /* XXX: default values not correct for B and XR channels,
979 * but who cares? */
980 .tqi_aifs = AR5K_TUNE_AIFS,
981 .tqi_cw_min = AR5K_TUNE_CWMIN,
982 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 983 /* NB: for dynamic turbo, don't enable any other interrupts */
984 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
985 };
d8ee398d 986
8a63facc 987 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 988}
989
8a63facc
BC		 990static int
991ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 992{
993 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 994 struct ath5k_txq_info qi;
995 int ret;
fa1c114f 996
8a63facc
BC		 997 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
998 if (ret)
999 goto err;
fa1c114f 1000
8a63facc
BC		 1001 if (sc->opmode == NL80211_IFTYPE_AP ||
1002 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1003 /*
1004 * Always burst out beacon and CAB traffic
1005 * (aifs = cwmin = cwmax = 0)
1006 */
1007 qi.tqi_aifs = 0;
1008 qi.tqi_cw_min = 0;
1009 qi.tqi_cw_max = 0;
1010 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1011 /*
1012 * Adhoc mode; backoff between 0 and (2 * cw_min).
1013 */
1014 qi.tqi_aifs = 0;
1015 qi.tqi_cw_min = 0;
de8af455 1016 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 1017 }
fa1c114f 1018
8a63facc
BC		 1019 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1020 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1021 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1022
8a63facc
BC		 1023 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1024 if (ret) {
1025 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1026 "hardware queue!\n", __func__);
1027 goto err;
1028 }
1029 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1030 if (ret)
1031 goto err;
b7266047 1032
8a63facc
BC		 1033 /* reconfigure cabq with ready time to 80% of beacon_interval */
1034 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1035 if (ret)
1036 goto err;
b7266047 1037
8a63facc
BC		 1038 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1039 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1040 if (ret)
1041 goto err;
b7266047 1042
8a63facc
BC		 1043 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1044err:
1045 return ret;
d8ee398d
LR		 1046}
1047
80dac9ee
NK		 1048/**
1049 * ath5k_drain_tx_buffs - Empty tx buffers
1050 *
1051 * @sc The &struct ath5k_softc
1052 *
1053 * Empty tx buffers from all queues in preparation
1054 * of a reset or during shutdown.
1055 *
1056 * NB: this assumes output has been stopped and
1057 * we do not need to block ath5k_tx_tasklet
1058 */
8a63facc 1059static void
80dac9ee 1060ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1061{
80dac9ee 1062 struct ath5k_txq *txq;
8a63facc 1063 struct ath5k_buf *bf, *bf0;
80dac9ee 1064 int i;
b6ea0356 1065
80dac9ee
NK		 1066 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1067 if (sc->txqs[i].setup) {
1068 txq = &sc->txqs[i];
1069 spin_lock_bh(&txq->lock);
1070 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1071 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1072
80dac9ee 1073 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1074
80dac9ee
NK		 1075 spin_lock_bh(&sc->txbuflock);
1076 list_move_tail(&bf->list, &sc->txbuf);
1077 sc->txbuf_len++;
1078 txq->txq_len--;
1079 spin_unlock_bh(&sc->txbuflock);
8a63facc 1080 }
80dac9ee
NK		 1081 txq->link = NULL;
1082 txq->txq_poll_mark = false;
1083 spin_unlock_bh(&txq->lock);
1084 }
0452d4a5 1085 }
fa1c114f
JS		 1086}
1087
8a63facc
BC		 1088static void
1089ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1090{
8a63facc
BC		 1091 struct ath5k_txq *txq = sc->txqs;
1092 unsigned int i;
2ac2927a 1093
8a63facc
BC		 1094 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1095 if (txq->setup) {
1096 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1097 txq->setup = false;
1098 }
1099}
2ac2927a 1100
2ac2927a 1101
8a63facc
BC		 1102/*************\
1103* RX Handling *
1104\*************/
2ac2927a 1105
8a63facc
BC		 1106/*
1107 * Enable the receive h/w following a reset.
1108 */
fa1c114f 1109static int
8a63facc 1110ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1111{
1112 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1113 struct ath_common *common = ath5k_hw_common(ah);
1114 struct ath5k_buf *bf;
1115 int ret;
fa1c114f 1116
8a63facc 1117 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1118
8a63facc
BC		 1119 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1120 common->cachelsz, common->rx_bufsize);
2f7fe870 1121
8a63facc
BC		 1122 spin_lock_bh(&sc->rxbuflock);
1123 sc->rxlink = NULL;
1124 list_for_each_entry(bf, &sc->rxbuf, list) {
1125 ret = ath5k_rxbuf_setup(sc, bf);
1126 if (ret != 0) {
1127 spin_unlock_bh(&sc->rxbuflock);
1128 goto err;
1129 }
2f7fe870 1130 }
8a63facc
BC		 1131 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1132 ath5k_hw_set_rxdp(ah, bf->daddr);
1133 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1134
8a63facc 1135 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
b1ae1edf 1136 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
8a63facc 1137 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1138
1139 return 0;
8a63facc 1140err:
fa1c114f
JS		 1141 return ret;
1142}
1143
8a63facc 1144/*
80dac9ee
NK		 1145 * Disable the receive logic on PCU (DRU)
1146 * In preparation for a shutdown.
1147 *
1148 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1149 * does.
8a63facc
BC		 1150 */
1151static void
1152ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1153{
8a63facc 1154 struct ath5k_hw *ah = sc->ah;
fa1c114f 1155
8a63facc 1156 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1157 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1158
8a63facc
BC		 1159 ath5k_debug_printrxbuffs(sc, ah);
1160}
fa1c114f 1161
8a63facc
BC		 1162static unsigned int
1163ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1164 struct ath5k_rx_status *rs)
1165{
1166 struct ath5k_hw *ah = sc->ah;
1167 struct ath_common *common = ath5k_hw_common(ah);
1168 struct ieee80211_hdr *hdr = (void *)skb->data;
1169 unsigned int keyix, hlen;
fa1c114f 1170
8a63facc
BC		 1171 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1172 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1173 return RX_FLAG_DECRYPTED;
fa1c114f 1174
8a63facc
BC		 1175 /* Apparently when a default key is used to decrypt the packet
1176 the hw does not set the index used to decrypt. In such cases
1177 get the index from the packet. */
1178 hlen = ieee80211_hdrlen(hdr->frame_control);
1179 if (ieee80211_has_protected(hdr->frame_control) &&
1180 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1181 skb->len >= hlen + 4) {
1182 keyix = skb->data[hlen + 3] >> 6;
1183
1184 if (test_bit(keyix, common->keymap))
1185 return RX_FLAG_DECRYPTED;
1186 }
fa1c114f
JS		 1187
1188 return 0;
fa1c114f
JS		 1189}
1190
8a63facc 1191
fa1c114f 1192static void
8a63facc
BC		 1193ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1194 struct ieee80211_rx_status *rxs)
fa1c114f 1195{
8a63facc
BC		 1196 struct ath_common *common = ath5k_hw_common(sc->ah);
1197 u64 tsf, bc_tstamp;
1198 u32 hw_tu;
1199 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1200
8a63facc
BC		 1201 if (ieee80211_is_beacon(mgmt->frame_control) &&
1202 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1203 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1204 /*
1205 * Received an IBSS beacon with the same BSSID. Hardware *must*
1206 * have updated the local TSF. We have to work around various
1207 * hardware bugs, though...
1208 */
1209 tsf = ath5k_hw_get_tsf64(sc->ah);
1210 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1211 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1212
8a63facc
BC		 1213 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1214 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1215 (unsigned long long)bc_tstamp,
1216 (unsigned long long)rxs->mactime,
1217 (unsigned long long)(rxs->mactime - bc_tstamp),
1218 (unsigned long long)tsf);
fa1c114f 1219
8a63facc
BC		 1220 /*
1221 * Sometimes the HW will give us a wrong tstamp in the rx
1222 * status, causing the timestamp extension to go wrong.
1223 * (This seems to happen especially with beacon frames bigger
1224 * than 78 byte (incl. FCS))
1225 * But we know that the receive timestamp must be later than the
1226 * timestamp of the beacon since HW must have synced to that.
1227 *
1228 * NOTE: here we assume mactime to be after the frame was
1229 * received, not like mac80211 which defines it at the start.
1230 */
1231 if (bc_tstamp > rxs->mactime) {
1232 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1233 "fixing mactime from %llx to %llx\n",
1234 (unsigned long long)rxs->mactime,
1235 (unsigned long long)tsf);
1236 rxs->mactime = tsf;
1237 }
fa1c114f 1238
8a63facc
BC		 1239 /*
1240 * Local TSF might have moved higher than our beacon timers,
1241 * in that case we have to update them to continue sending
1242 * beacons. This also takes care of synchronizing beacon sending
1243 * times with other stations.
1244 */
1245 if (hw_tu >= sc->nexttbtt)
1246 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1247
1248 /* Check if the beacon timers are still correct, because a TSF
1249 * update might have created a window between them - for a
1250 * longer description see the comment of this function: */
1251 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1252 ath5k_beacon_update_timers(sc, bc_tstamp);
1253 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1254 "fixed beacon timers after beacon receive\n");
1255 }
8a63facc
BC		 1256 }
1257}
fa1c114f 1258
8a63facc
BC		 1259static void
1260ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1261{
1262 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1263 struct ath5k_hw *ah = sc->ah;
1264 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1265
8a63facc
BC		 1266 /* only beacons from our BSSID */
1267 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1268 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1269 return;
fa1c114f 1270
eef39bef 1271 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1272
8a63facc
BC		 1273 /* in IBSS mode we should keep RSSI statistics per neighbour */
1274 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1275}
fa1c114f 1276
8a63facc
BC		 1277/*
1278 * Compute padding position. skb must contain an IEEE 802.11 frame
1279 */
1280static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1281{
8a63facc
BC		 1282 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1283 __le16 frame_control = hdr->frame_control;
1284 int padpos = 24;
fa1c114f 1285
8a63facc
BC		 1286 if (ieee80211_has_a4(frame_control)) {
1287 padpos += ETH_ALEN;
fa1c114f 1288 }
8a63facc
BC		 1289 if (ieee80211_is_data_qos(frame_control)) {
1290 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1291 }
8a63facc
BC		 1292
1293 return padpos;
fa1c114f
JS		 1294}
1295
8a63facc
BC		 1296/*
1297 * This function expects an 802.11 frame and returns the number of
1298 * bytes added, or -1 if we don't have enough header room.
1299 */
1300static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1301{
8a63facc
BC		 1302 int padpos = ath5k_common_padpos(skb);
1303 int padsize = padpos & 3;
fa1c114f 1304
8a63facc 1305 if (padsize && skb->len>padpos) {
fa1c114f 1306
8a63facc
BC		 1307 if (skb_headroom(skb) < padsize)
1308 return -1;
fa1c114f 1309
8a63facc
BC		 1310 skb_push(skb, padsize);
1311 memmove(skb->data, skb->data+padsize, padpos);
1312 return padsize;
1313 }
a951ae21 1314
8a63facc
BC		 1315 return 0;
1316}
fa1c114f 1317
8a63facc
BC		 1318/*
1319 * The MAC header is padded to have 32-bit boundary if the
1320 * packet payload is non-zero. The general calculation for
1321 * padsize would take into account odd header lengths:
1322 * padsize = 4 - (hdrlen & 3); however, since only
1323 * even-length headers are used, padding can only be 0 or 2
1324 * bytes and we can optimize this a bit. We must not try to
1325 * remove padding from short control frames that do not have a
1326 * payload.
1327 *
1328 * This function expects an 802.11 frame and returns the number of
1329 * bytes removed.
1330 */
1331static int ath5k_remove_padding(struct sk_buff *skb)
1332{
1333 int padpos = ath5k_common_padpos(skb);
1334 int padsize = padpos & 3;
6d91e1d8 1335
8a63facc
BC		 1336 if (padsize && skb->len>=padpos+padsize) {
1337 memmove(skb->data + padsize, skb->data, padpos);
1338 skb_pull(skb, padsize);
1339 return padsize;
fa1c114f 1340 }
a951ae21 1341
8a63facc 1342 return 0;
fa1c114f
JS		 1343}
1344
1345static void
8a63facc
BC		 1346ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1347 struct ath5k_rx_status *rs)
fa1c114f 1348{
8a63facc
BC		 1349 struct ieee80211_rx_status *rxs;
1350
1351 ath5k_remove_padding(skb);
1352
1353 rxs = IEEE80211_SKB_RXCB(skb);
1354
1355 rxs->flag = 0;
1356 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1357 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1358
1359 /*
8a63facc
BC		 1360 * always extend the mac timestamp, since this information is
1361 * also needed for proper IBSS merging.
1362 *
1363 * XXX: it might be too late to do it here, since rs_tstamp is
1364 * 15bit only. that means TSF extension has to be done within
1365 * 32768usec (about 32ms). it might be necessary to move this to
1366 * the interrupt handler, like it is done in madwifi.
1367 *
1368 * Unfortunately we don't know when the hardware takes the rx
1369 * timestamp (beginning of phy frame, data frame, end of rx?).
1370 * The only thing we know is that it is hardware specific...
1371 * On AR5213 it seems the rx timestamp is at the end of the
1372 * frame, but i'm not sure.
1373 *
1374 * NOTE: mac80211 defines mactime at the beginning of the first
1375 * data symbol. Since we don't have any time references it's
1376 * impossible to comply to that. This affects IBSS merge only
1377 * right now, so it's not too bad...
fa1c114f 1378 */
8a63facc
BC		 1379 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1380 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1381
8a63facc
BC		 1382 rxs->freq = sc->curchan->center_freq;
1383 rxs->band = sc->curband->band;
fa1c114f 1384
8a63facc 1385 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1386
8a63facc 1387 rxs->antenna = rs->rs_antenna;
fa1c114f 1388
8a63facc
BC		 1389 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1390 sc->stats.antenna_rx[rs->rs_antenna]++;
1391 else
1392 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1393
8a63facc
BC		 1394 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1395 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1396
8a63facc
BC		 1397 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1398 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1399 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1400
8a63facc 1401 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1402
8a63facc 1403 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1404
8a63facc
BC		 1405 /* check beacons in IBSS mode */
1406 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1407 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1408
8a63facc
BC		 1409 ieee80211_rx(sc->hw, skb);
1410}
fa1c114f 1411
8a63facc
BC		 1412/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1413 *
1414 * Check if we want to further process this frame or not. Also update
1415 * statistics. Return true if we want this frame, false if not.
fa1c114f 1416 */
8a63facc
BC		 1417static bool
1418ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1419{
8a63facc 1420 sc->stats.rx_all_count++;
b72acddb 1421 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1422
8a63facc
BC		 1423 if (unlikely(rs->rs_status)) {
1424 if (rs->rs_status & AR5K_RXERR_CRC)
1425 sc->stats.rxerr_crc++;
1426 if (rs->rs_status & AR5K_RXERR_FIFO)
1427 sc->stats.rxerr_fifo++;
1428 if (rs->rs_status & AR5K_RXERR_PHY) {
1429 sc->stats.rxerr_phy++;
1430 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1431 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1432 return false;
1433 }
1434 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1435 /*
1436 * Decrypt error. If the error occurred
1437 * because there was no hardware key, then
1438 * let the frame through so the upper layers
1439 * can process it. This is necessary for 5210
1440 * parts which have no way to setup a ``clear''
1441 * key cache entry.
1442 *
1443 * XXX do key cache faulting
1444 */
1445 sc->stats.rxerr_decrypt++;
1446 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1447 !(rs->rs_status & AR5K_RXERR_CRC))
1448 return true;
1449 }
1450 if (rs->rs_status & AR5K_RXERR_MIC) {
1451 sc->stats.rxerr_mic++;
1452 return true;
fa1c114f 1453 }
fa1c114f 1454
8a63facc
BC		 1455 /* reject any frames with non-crypto errors */
1456 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1457 return false;
1458 }
fa1c114f 1459
8a63facc
BC		 1460 if (unlikely(rs->rs_more)) {
1461 sc->stats.rxerr_jumbo++;
1462 return false;
1463 }
1464 return true;
fa1c114f
JS		 1465}
1466
fa1c114f 1467static void
8a63facc 1468ath5k_tasklet_rx(unsigned long data)
fa1c114f 1469{
8a63facc
BC		 1470 struct ath5k_rx_status rs = {};
1471 struct sk_buff *skb, *next_skb;
1472 dma_addr_t next_skb_addr;
1473 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1474 struct ath5k_hw *ah = sc->ah;
1475 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1476 struct ath5k_buf *bf;
1477 struct ath5k_desc *ds;
1478 int ret;
fa1c114f 1479
8a63facc
BC		 1480 spin_lock(&sc->rxbuflock);
1481 if (list_empty(&sc->rxbuf)) {
1482 ATH5K_WARN(sc, "empty rx buf pool\n");
1483 goto unlock;
1484 }
1485 do {
1486 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1487 BUG_ON(bf->skb == NULL);
1488 skb = bf->skb;
1489 ds = bf->desc;
fa1c114f 1490
8a63facc
BC		 1491 /* bail if HW is still using self-linked descriptor */
1492 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1493 break;
fa1c114f 1494
8a63facc
BC		 1495 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1496 if (unlikely(ret == -EINPROGRESS))
1497 break;
1498 else if (unlikely(ret)) {
1499 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1500 sc->stats.rxerr_proc++;
1501 break;
1502 }
fa1c114f 1503
8a63facc
BC		 1504 if (ath5k_receive_frame_ok(sc, &rs)) {
1505 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1506
8a63facc
BC		 1507 /*
1508 * If we can't replace bf->skb with a new skb under
1509 * memory pressure, just skip this packet
1510 */
1511 if (!next_skb)
1512 goto next;
036cd1ec 1513
aeae4ac9 1514 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1515 common->rx_bufsize,
aeae4ac9 1516 DMA_FROM_DEVICE);
036cd1ec 1517
8a63facc 1518 skb_put(skb, rs.rs_datalen);
6ba81c2c 1519
8a63facc 1520 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1521
8a63facc
BC		 1522 bf->skb = next_skb;
1523 bf->skbaddr = next_skb_addr;
036cd1ec 1524 }
8a63facc
BC		 1525next:
1526 list_move_tail(&bf->list, &sc->rxbuf);
1527 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1528unlock:
1529 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1530}
1531
b4ea449d 1532
8a63facc
BC		 1533/*************\
1534* TX Handling *
1535\*************/
b4ea449d 1536
8a63facc
BC		 1537static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1538 struct ath5k_txq *txq)
1539{
1540 struct ath5k_softc *sc = hw->priv;
1541 struct ath5k_buf *bf;
1542 unsigned long flags;
1543 int padsize;
b4ea449d 1544
8a63facc 1545 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
b4ea449d 1546
8a63facc
BC		 1547 /*
1548 * The hardware expects the header padded to 4 byte boundaries.
1549 * If this is not the case, we add the padding after the header.
1550 */
1551 padsize = ath5k_add_padding(skb);
1552 if (padsize < 0) {
1553 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1554 " headroom to pad");
1555 goto drop_packet;
1556 }
8127fbdc 1557
925e0b06
BR		 1558 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1559 ieee80211_stop_queue(hw, txq->qnum);
1560
8a63facc
BC		 1561 spin_lock_irqsave(&sc->txbuflock, flags);
1562 if (list_empty(&sc->txbuf)) {
1563 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1564 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1565 ieee80211_stop_queues(hw);
8a63facc 1566 goto drop_packet;
8127fbdc 1567 }
8a63facc
BC		 1568 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1569 list_del(&bf->list);
1570 sc->txbuf_len--;
1571 if (list_empty(&sc->txbuf))
1572 ieee80211_stop_queues(hw);
1573 spin_unlock_irqrestore(&sc->txbuflock, flags);
1574
1575 bf->skb = skb;
1576
1577 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1578 bf->skb = NULL;
1579 spin_lock_irqsave(&sc->txbuflock, flags);
1580 list_add_tail(&bf->list, &sc->txbuf);
1581 sc->txbuf_len++;
1582 spin_unlock_irqrestore(&sc->txbuflock, flags);
1583 goto drop_packet;
8127fbdc 1584 }
8a63facc 1585 return NETDEV_TX_OK;
8127fbdc 1586
8a63facc
BC		 1587drop_packet:
1588 dev_kfree_skb_any(skb);
1589 return NETDEV_TX_OK;
8127fbdc
BP		 1590}
1591
1440401e
BR		 1592static void
1593ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1594 struct ath5k_tx_status *ts)
1595{
1596 struct ieee80211_tx_info *info;
1597 int i;
1598
1599 sc->stats.tx_all_count++;
b72acddb 1600 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1601 info = IEEE80211_SKB_CB(skb);
1602
1603 ieee80211_tx_info_clear_status(info);
1604 for (i = 0; i < 4; i++) {
1605 struct ieee80211_tx_rate *r =
1606 &info->status.rates[i];
1607
1608 if (ts->ts_rate[i]) {
1609 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1610 r->count = ts->ts_retry[i];
1611 } else {
1612 r->idx = -1;
1613 r->count = 0;
1614 }
1615 }
1616
1617 /* count the successful attempt as well */
1618 info->status.rates[ts->ts_final_idx].count++;
1619
1620 if (unlikely(ts->ts_status)) {
1621 sc->stats.ack_fail++;
1622 if (ts->ts_status & AR5K_TXERR_FILT) {
1623 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1624 sc->stats.txerr_filt++;
1625 }
1626 if (ts->ts_status & AR5K_TXERR_XRETRY)
1627 sc->stats.txerr_retry++;
1628 if (ts->ts_status & AR5K_TXERR_FIFO)
1629 sc->stats.txerr_fifo++;
1630 } else {
1631 info->flags |= IEEE80211_TX_STAT_ACK;
1632 info->status.ack_signal = ts->ts_rssi;
1633 }
1634
1635 /*
1636 * Remove MAC header padding before giving the frame
1637 * back to mac80211.
1638 */
1639 ath5k_remove_padding(skb);
1640
1641 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1642 sc->stats.antenna_tx[ts->ts_antenna]++;
1643 else
1644 sc->stats.antenna_tx[0]++; /* invalid */
1645
1646 ieee80211_tx_status(sc->hw, skb);
1647}
8a63facc
BC		 1648
1649static void
1650ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1651{
8a63facc
BC		 1652 struct ath5k_tx_status ts = {};
1653 struct ath5k_buf *bf, *bf0;
1654 struct ath5k_desc *ds;
1655 struct sk_buff *skb;
1440401e 1656 int ret;
8127fbdc 1657
8a63facc
BC		 1658 spin_lock(&txq->lock);
1659 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1660
1661 txq->txq_poll_mark = false;
1662
1663 /* skb might already have been processed last time. */
1664 if (bf->skb != NULL) {
1665 ds = bf->desc;
1666
1667 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1668 if (unlikely(ret == -EINPROGRESS))
1669 break;
1670 else if (unlikely(ret)) {
1671 ATH5K_ERR(sc,
1672 "error %d while processing "
1673 "queue %u\n", ret, txq->qnum);
1674 break;
1675 }
1676
1677 skb = bf->skb;
1678 bf->skb = NULL;
aeae4ac9
FF		 1679
1680 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1681 DMA_TO_DEVICE);
23413296
BR		 1682 ath5k_tx_frame_completed(sc, skb, &ts);
1683 }
8127fbdc 1684
8a63facc
BC		 1685 /*
1686 * It's possible that the hardware can say the buffer is
1687 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1688 * host memory and moved on.
1689 * Always keep the last descriptor to avoid HW races...
8a63facc 1690 */
23413296
BR		 1691 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1692 spin_lock(&sc->txbuflock);
1693 list_move_tail(&bf->list, &sc->txbuf);
1694 sc->txbuf_len++;
1695 txq->txq_len--;
1696 spin_unlock(&sc->txbuflock);
8a63facc 1697 }
fa1c114f 1698 }
fa1c114f 1699 spin_unlock(&txq->lock);
4198a8d0 1700 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1701 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1702}
1703
1704static void
1705ath5k_tasklet_tx(unsigned long data)
1706{
8784d2ee 1707 int i;
fa1c114f
JS		 1708 struct ath5k_softc *sc = (void *)data;
1709
8784d2ee
BC		 1710 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1711 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1712 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1713}
1714
1715
fa1c114f
JS		 1716/*****************\
1717* Beacon handling *
1718\*****************/
1719
1720/*
1721 * Setup the beacon frame for transmit.
1722 */
1723static int
e039fa4a 1724ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1725{
1726 struct sk_buff *skb = bf->skb;
a888d52d 1727 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1728 struct ath5k_hw *ah = sc->ah;
1729 struct ath5k_desc *ds;
2bed03eb
NK		 1730 int ret = 0;
1731 u8 antenna;
fa1c114f 1732 u32 flags;
8127fbdc 1733 const int padsize = 0;
fa1c114f 1734
aeae4ac9
FF		 1735 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1736 DMA_TO_DEVICE);
fa1c114f
JS		 1737 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1738 "skbaddr %llx\n", skb, skb->data, skb->len,
1739 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1740
1741 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1742 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1743 return -EIO;
1744 }
1745
1746 ds = bf->desc;
2bed03eb 1747 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1748
1749 flags = AR5K_TXDESC_NOACK;
05c914fe 1750 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1751 ds->ds_link = bf->daddr; /* self-linked */
1752 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1753 } else
fa1c114f 1754 ds->ds_link = 0;
2bed03eb
NK		 1755
1756 /*
1757 * If we use multiple antennas on AP and use
1758 * the Sectored AP scenario, switch antenna every
1759 * 4 beacons to make sure everybody hears our AP.
1760 * When a client tries to associate, hw will keep
1761 * track of the tx antenna to be used for this client
1762 * automaticaly, based on ACKed packets.
1763 *
1764 * Note: AP still listens and transmits RTS on the
1765 * default antenna which is supposed to be an omni.
1766 *
1767 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1768 * multiple antennas (1 omni -- the default -- and 14
1769 * sectors), so if we choose to actually support this
1770 * mode, we need to allow the user to set how many antennas
1771 * we have and tweak the code below to send beacons
1772 * on all of them.
2bed03eb
NK		 1773 */
1774 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1775 antenna = sc->bsent & 4 ? 2 : 1;
1776
fa1c114f 1777
8f655dde
NK		 1778 /* FIXME: If we are in g mode and rate is a CCK rate
1779 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1780 * from tx power (value is in dB units already) */
fa1c114f 1781 ds->ds_data = bf->skbaddr;
281c56dd 1782 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1783 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1784 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1785 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1786 1, AR5K_TXKEYIX_INVALID,
400ec45a 1787 antenna, flags, 0, 0);
fa1c114f
JS		 1788 if (ret)
1789 goto err_unmap;
1790
1791 return 0;
1792err_unmap:
aeae4ac9 1793 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1794 return ret;
1795}
1796
8a63facc
BC		 1797/*
1798 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1799 * this is called only once at config_bss time, for AP we do it every
1800 * SWBA interrupt so that the TIM will reflect buffered frames.
1801 *
1802 * Called with the beacon lock.
1803 */
1804static int
1805ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1806{
1807 int ret;
1808 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1809 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1810 struct sk_buff *skb;
1811
1812 if (WARN_ON(!vif)) {
1813 ret = -EINVAL;
1814 goto out;
1815 }
1816
1817 skb = ieee80211_beacon_get(hw, vif);
1818
1819 if (!skb) {
1820 ret = -ENOMEM;
1821 goto out;
1822 }
1823
1824 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1825
b1ae1edf
BG		 1826 ath5k_txbuf_free_skb(sc, avf->bbuf);
1827 avf->bbuf->skb = skb;
1828 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1829 if (ret)
b1ae1edf 1830 avf->bbuf->skb = NULL;
8a63facc
BC		 1831out:
1832 return ret;
1833}
1834
fa1c114f
JS		 1835/*
1836 * Transmit a beacon frame at SWBA. Dynamic updates to the
1837 * frame contents are done as needed and the slot time is
1838 * also adjusted based on current state.
1839 *
5faaff74
BC		 1840 * This is called from software irq context (beacontq tasklets)
1841 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1842 */
1843static void
1844ath5k_beacon_send(struct ath5k_softc *sc)
1845{
fa1c114f 1846 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1847 struct ieee80211_vif *vif;
1848 struct ath5k_vif *avf;
1849 struct ath5k_buf *bf;
cec8db23 1850 struct sk_buff *skb;
fa1c114f 1851
be9b7259 1852 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1853
fa1c114f
JS		 1854 /*
1855 * Check if the previous beacon has gone out. If
a180a130 1856 * not, don't don't try to post another: skip this
fa1c114f
JS		 1857 * period and wait for the next. Missed beacons
1858 * indicate a problem and should not occur. If we
1859 * miss too many consecutive beacons reset the device.
1860 */
1861 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1862 sc->bmisscount++;
be9b7259 1863 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1864 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1865 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1866 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1867 "stuck beacon time (%u missed)\n",
1868 sc->bmisscount);
8d67a031
BR		 1869 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1870 "stuck beacon, resetting\n");
5faaff74 1871 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1872 }
1873 return;
1874 }
1875 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1876 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1877 "resume beacon xmit after %u misses\n",
1878 sc->bmisscount);
1879 sc->bmisscount = 0;
1880 }
1881
b93996cf
JC		 1882 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1883 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1884 u64 tsf = ath5k_hw_get_tsf64(ah);
1885 u32 tsftu = TSF_TO_TU(tsf);
1886 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1887 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1888 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1889 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1890 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1891 } else /* only one interface */
1892 vif = sc->bslot[0];
1893
1894 if (!vif)
1895 return;
1896
1897 avf = (void *)vif->drv_priv;
1898 bf = avf->bbuf;
1899 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1900 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1901 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1902 return;
1903 }
1904
fa1c114f
JS		 1905 /*
1906 * Stop any current dma and put the new frame on the queue.
1907 * This should never fail since we check above that no frames
1908 * are still pending on the queue.
1909 */
14fae2d4 1910 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1911 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1912 /* NB: hw still stops DMA, so proceed */
1913 }
fa1c114f 1914
d82b577b
JC		 1915 /* refresh the beacon for AP or MESH mode */
1916 if (sc->opmode == NL80211_IFTYPE_AP ||
1917 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1918 ath5k_beacon_update(sc->hw, vif);
1071db86 1919
c6e387a2
NK		 1920 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1921 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1922 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1923 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1924
b1ae1edf 1925 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1926 while (skb) {
1927 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1928 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1929 }
1930
fa1c114f
JS		 1931 sc->bsent++;
1932}
1933
9804b98d
BR		 1934/**
1935 * ath5k_beacon_update_timers - update beacon timers
1936 *
1937 * @sc: struct ath5k_softc pointer we are operating on
1938 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1939 * beacon timer update based on the current HW TSF.
1940 *
1941 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1942 * of a received beacon or the current local hardware TSF and write it to the
1943 * beacon timer registers.
1944 *
1945 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1946 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1947 * when we otherwise know we have to update the timers, but we keep it in this
1948 * function to have it all together in one place.
1949 */
fa1c114f 1950static void
9804b98d 1951ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1952{
1953 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1954 u32 nexttbtt, intval, hw_tu, bc_tu;
1955 u64 hw_tsf;
fa1c114f
JS		 1956
1957 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1958 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1959 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1960 if (intval < 15)
1961 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1962 intval);
1963 }
fa1c114f
JS		 1964 if (WARN_ON(!intval))
1965 return;
1966
9804b98d
BR		 1967 /* beacon TSF converted to TU */
1968 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1969
9804b98d
BR		 1970 /* current TSF converted to TU */
1971 hw_tsf = ath5k_hw_get_tsf64(ah);
1972 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1973
11f21df3
BR		 1974#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1975 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1976 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1977 * configuration we need to make sure it is bigger than that. */
1978
9804b98d
BR		 1979 if (bc_tsf == -1) {
1980 /*
1981 * no beacons received, called internally.
1982 * just need to refresh timers based on HW TSF.
1983 */
1984 nexttbtt = roundup(hw_tu + FUDGE, intval);
1985 } else if (bc_tsf == 0) {
1986 /*
1987 * no beacon received, probably called by ath5k_reset_tsf().
1988 * reset TSF to start with 0.
1989 */
1990 nexttbtt = intval;
1991 intval |= AR5K_BEACON_RESET_TSF;
1992 } else if (bc_tsf > hw_tsf) {
1993 /*
1994 * beacon received, SW merge happend but HW TSF not yet updated.
1995 * not possible to reconfigure timers yet, but next time we
1996 * receive a beacon with the same BSSID, the hardware will
1997 * automatically update the TSF and then we need to reconfigure
1998 * the timers.
1999 */
2000 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2001 "need to wait for HW TSF sync\n");
2002 return;
2003 } else {
2004 /*
2005 * most important case for beacon synchronization between STA.
2006 *
2007 * beacon received and HW TSF has been already updated by HW.
2008 * update next TBTT based on the TSF of the beacon, but make
2009 * sure it is ahead of our local TSF timer.
2010 */
2011 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2012 }
2013#undef FUDGE
fa1c114f 2014
036cd1ec
BR		 2015 sc->nexttbtt = nexttbtt;
2016
fa1c114f 2017 intval |= AR5K_BEACON_ENA;
fa1c114f 2018 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2019
2020 /*
2021 * debugging output last in order to preserve the time critical aspect
2022 * of this function
2023 */
2024 if (bc_tsf == -1)
2025 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2026 "reconfigured timers based on HW TSF\n");
2027 else if (bc_tsf == 0)
2028 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2029 "reset HW TSF and timers\n");
2030 else
2031 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2032 "updated timers based on beacon TSF\n");
2033
2034 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2035 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2036 (unsigned long long) bc_tsf,
2037 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2038 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2039 intval & AR5K_BEACON_PERIOD,
2040 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2041 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2042}
2043
036cd1ec
BR		 2044/**
2045 * ath5k_beacon_config - Configure the beacon queues and interrupts
2046 *
2047 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2048 *
036cd1ec 2049 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2050 * interrupts to detect TSF updates only.
fa1c114f
JS		 2051 */
2052static void
2053ath5k_beacon_config(struct ath5k_softc *sc)
2054{
2055 struct ath5k_hw *ah = sc->ah;
b5f03956 2056 unsigned long flags;
fa1c114f 2057
21800491 2058 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2059 sc->bmisscount = 0;
dc1968e7 2060 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2061
21800491 2062 if (sc->enable_beacon) {
fa1c114f 2063 /*
036cd1ec
BR		 2064 * In IBSS mode we use a self-linked tx descriptor and let the
2065 * hardware send the beacons automatically. We have to load it
fa1c114f 2066 * only once here.
036cd1ec 2067 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2068 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2069 */
2070 ath5k_beaconq_config(sc);
fa1c114f 2071
036cd1ec
BR		 2072 sc->imask |= AR5K_INT_SWBA;
2073
da966bca 2074 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2075 if (ath5k_hw_hasveol(ah))
da966bca 2076 ath5k_beacon_send(sc);
da966bca
JS		 2077 } else
2078 ath5k_beacon_update_timers(sc, -1);
21800491 2079 } else {
14fae2d4 2080 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2081 }
fa1c114f 2082
c6e387a2 2083 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2084 mmiowb();
2085 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2086}
2087
428cbd4f
NK		 2088static void ath5k_tasklet_beacon(unsigned long data)
2089{
2090 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2091
2092 /*
2093 * Software beacon alert--time to send a beacon.
2094 *
2095 * In IBSS mode we use this interrupt just to
2096 * keep track of the next TBTT (target beacon
2097 * transmission time) in order to detect wether
2098 * automatic TSF updates happened.
2099 */
2100 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2101 /* XXX: only if VEOL suppported */
2102 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2103 sc->nexttbtt += sc->bintval;
2104 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2105 "SWBA nexttbtt: %x hw_tu: %x "
2106 "TSF: %llx\n",
2107 sc->nexttbtt,
2108 TSF_TO_TU(tsf),
2109 (unsigned long long) tsf);
2110 } else {
2111 spin_lock(&sc->block);
2112 ath5k_beacon_send(sc);
2113 spin_unlock(&sc->block);
2114 }
2115}
2116
fa1c114f
JS		 2117
2118/********************\
2119* Interrupt handling *
2120\********************/
2121
6a8a3f6b
BR		 2122static void
2123ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2124{
2111ac0d
BR		 2125 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2126 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2127 /* run ANI only when full calibration is not active */
2128 ah->ah_cal_next_ani = jiffies +
2129 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2130 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2131
2132 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2133 ah->ah_cal_next_full = jiffies +
2134 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2135 tasklet_schedule(&ah->ah_sc->calib);
2136 }
2137 /* we could use SWI to generate enough interrupts to meet our
2138 * calibration interval requirements, if necessary:
2139 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2140}
2141
132b1c3e 2142irqreturn_t
fa1c114f
JS		 2143ath5k_intr(int irq, void *dev_id)
2144{
2145 struct ath5k_softc *sc = dev_id;
2146 struct ath5k_hw *ah = sc->ah;
2147 enum ath5k_int status;
2148 unsigned int counter = 1000;
2149
2150 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2151 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2152 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2153 return IRQ_NONE;
2154
2155 do {
fa1c114f
JS		 2156 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2157 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2158 status, sc->imask);
fa1c114f
JS		 2159 if (unlikely(status & AR5K_INT_FATAL)) {
2160 /*
2161 * Fatal errors are unrecoverable.
2162 * Typically these are caused by DMA errors.
2163 */
8d67a031
BR		 2164 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2165 "fatal int, resetting\n");
5faaff74 2166 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2167 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2168 /*
2169 * Receive buffers are full. Either the bus is busy or
2170 * the CPU is not fast enough to process all received
2171 * frames.
2172 * Older chipsets need a reset to come out of this
2173 * condition, but we treat it as RX for newer chips.
2174 * We don't know exactly which versions need a reset -
2175 * this guess is copied from the HAL.
2176 */
2177 sc->stats.rxorn_intr++;
8d67a031
BR		 2178 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2179 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2180 "rx overrun, resetting\n");
5faaff74 2181 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2182 }
87d77c4e
BR		 2183 else
2184 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2185 } else {
2186 if (status & AR5K_INT_SWBA) {
56d2ac76 2187 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2188 }
2189 if (status & AR5K_INT_RXEOL) {
2190 /*
2191 * NB: the hardware should re-read the link when
2192 * RXE bit is written, but it doesn't work at
2193 * least on older hardware revs.
2194 */
b3f194e5 2195 sc->stats.rxeol_intr++;
fa1c114f
JS		 2196 }
2197 if (status & AR5K_INT_TXURN) {
2198 /* bump tx trigger level */
2199 ath5k_hw_update_tx_triglevel(ah, true);
2200 }
4c674c60 2201 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2202 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2203 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2204 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2205 tasklet_schedule(&sc->txtq);
2206 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2207 /* TODO */
fa1c114f
JS		 2208 }
2209 if (status & AR5K_INT_MIB) {
2111ac0d 2210 sc->stats.mib_intr++;
495391d7 2211 ath5k_hw_update_mib_counters(ah);
2111ac0d 2212 ath5k_ani_mib_intr(ah);
fa1c114f 2213 }
e6a3b616 2214 if (status & AR5K_INT_GPIO)
e6a3b616 2215 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2216
fa1c114f 2217 }
4cebb34c
FF		 2218
2219 if (ath5k_get_bus_type(ah) == ATH_AHB)
2220 break;
2221
2516baa6 2222 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2223
2224 if (unlikely(!counter))
2225 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2226
6a8a3f6b 2227 ath5k_intr_calibration_poll(ah);
6e220662 2228
fa1c114f
JS		 2229 return IRQ_HANDLED;
2230}
2231
fa1c114f
JS		 2232/*
2233 * Periodically recalibrate the PHY to account
2234 * for temperature/environment changes.
2235 */
2236static void
6e220662 2237ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2238{
2239 struct ath5k_softc *sc = (void *)data;
2240 struct ath5k_hw *ah = sc->ah;
2241
6e220662 2242 /* Only full calibration for now */
e65e1d77 2243 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2244
fa1c114f 2245 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2246 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2247 sc->curchan->hw_value);
fa1c114f 2248
6f3b414a 2249 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2250 /*
2251 * Rfgain is out of bounds, reset the chip
2252 * to load new gain values.
2253 */
2254 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2255 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2256 }
2257 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2258 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2259 ieee80211_frequency_to_channel(
2260 sc->curchan->center_freq));
fa1c114f 2261
0e8e02dd 2262 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2263 * doesn't.
2264 * TODO: We should stop TX here, so that it doesn't interfere.
2265 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2266 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2267 ah->ah_cal_next_nf = jiffies +
2268 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2269 ath5k_hw_update_noise_floor(ah);
afe86286 2270 }
6e220662 2271
e65e1d77 2272 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2273}
2274
2275
2111ac0d
BR		 2276static void
2277ath5k_tasklet_ani(unsigned long data)
2278{
2279 struct ath5k_softc *sc = (void *)data;
2280 struct ath5k_hw *ah = sc->ah;
2281
2282 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2283 ath5k_ani_calibration(ah);
2284 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2285}
2286
2287
4edd761f
BR		 2288static void
2289ath5k_tx_complete_poll_work(struct work_struct *work)
2290{
2291 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2292 tx_complete_work.work);
2293 struct ath5k_txq *txq;
2294 int i;
2295 bool needreset = false;
2296
2297 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2298 if (sc->txqs[i].setup) {
2299 txq = &sc->txqs[i];
2300 spin_lock_bh(&txq->lock);
23413296 2301 if (txq->txq_len > 1) {
4edd761f
BR		 2302 if (txq->txq_poll_mark) {
2303 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2304 "TX queue stuck %d\n",
2305 txq->qnum);
2306 needreset = true;
923e5b3d 2307 txq->txq_stuck++;
4edd761f
BR		 2308 spin_unlock_bh(&txq->lock);
2309 break;
2310 } else {
2311 txq->txq_poll_mark = true;
2312 }
2313 }
2314 spin_unlock_bh(&txq->lock);
2315 }
2316 }
2317
2318 if (needreset) {
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2320 "TX queues stuck, resetting\n");
8aec7af9 2321 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2322 }
2323
2324 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2325 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2326}
2327
2328
8a63facc
BC		 2329/*************************\
2330* Initialization routines *
2331\*************************/
fa1c114f 2332
132b1c3e
FF		 2333int
2334ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2335{
2336 struct ieee80211_hw *hw = sc->hw;
2337 struct ath_common *common;
2338 int ret;
2339 int csz;
2340
2341 /* Initialize driver private data */
2342 SET_IEEE80211_DEV(hw, sc->dev);
2343 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2344 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2345 IEEE80211_HW_SIGNAL_DBM |
2346 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2347
2348 hw->wiphy->interface_modes =
2349 BIT(NL80211_IFTYPE_AP) |
2350 BIT(NL80211_IFTYPE_STATION) |
2351 BIT(NL80211_IFTYPE_ADHOC) |
2352 BIT(NL80211_IFTYPE_MESH_POINT);
2353
2354 hw->extra_tx_headroom = 2;
2355 hw->channel_change_time = 5000;
2356
2357 /*
2358 * Mark the device as detached to avoid processing
2359 * interrupts until setup is complete.
2360 */
2361 __set_bit(ATH_STAT_INVALID, sc->status);
2362
2363 sc->opmode = NL80211_IFTYPE_STATION;
2364 sc->bintval = 1000;
2365 mutex_init(&sc->lock);
2366 spin_lock_init(&sc->rxbuflock);
2367 spin_lock_init(&sc->txbuflock);
2368 spin_lock_init(&sc->block);
2369
2370
2371 /* Setup interrupt handler */
2372 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2373 if (ret) {
2374 ATH5K_ERR(sc, "request_irq failed\n");
2375 goto err;
2376 }
2377
2378 /* If we passed the test, malloc an ath5k_hw struct */
2379 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2380 if (!sc->ah) {
2381 ret = -ENOMEM;
2382 ATH5K_ERR(sc, "out of memory\n");
2383 goto err_irq;
2384 }
2385
2386 sc->ah->ah_sc = sc;
2387 sc->ah->ah_iobase = sc->iobase;
2388 common = ath5k_hw_common(sc->ah);
2389 common->ops = &ath5k_common_ops;
2390 common->bus_ops = bus_ops;
2391 common->ah = sc->ah;
2392 common->hw = hw;
2393 common->priv = sc;
2394
2395 /*
2396 * Cache line size is used to size and align various
2397 * structures used to communicate with the hardware.
2398 */
2399 ath5k_read_cachesize(common, &csz);
2400 common->cachelsz = csz << 2; /* convert to bytes */
2401
2402 spin_lock_init(&common->cc_lock);
2403
2404 /* Initialize device */
2405 ret = ath5k_hw_init(sc);
2406 if (ret)
2407 goto err_free_ah;
2408
2409 /* set up multi-rate retry capabilities */
2410 if (sc->ah->ah_version == AR5K_AR5212) {
2411 hw->max_rates = 4;
2412 hw->max_rate_tries = 11;
2413 }
2414
2415 hw->vif_data_size = sizeof(struct ath5k_vif);
2416
2417 /* Finish private driver data initialization */
2418 ret = ath5k_init(hw);
2419 if (ret)
2420 goto err_ah;
2421
2422 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2423 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2424 sc->ah->ah_mac_srev,
2425 sc->ah->ah_phy_revision);
2426
2427 if (!sc->ah->ah_single_chip) {
2428 /* Single chip radio (!RF5111) */
2429 if (sc->ah->ah_radio_5ghz_revision &&
2430 !sc->ah->ah_radio_2ghz_revision) {
2431 /* No 5GHz support -> report 2GHz radio */
2432 if (!test_bit(AR5K_MODE_11A,
2433 sc->ah->ah_capabilities.cap_mode)) {
2434 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2435 ath5k_chip_name(AR5K_VERSION_RAD,
2436 sc->ah->ah_radio_5ghz_revision),
2437 sc->ah->ah_radio_5ghz_revision);
2438 /* No 2GHz support (5110 and some
2439 * 5Ghz only cards) -> report 5Ghz radio */
2440 } else if (!test_bit(AR5K_MODE_11B,
2441 sc->ah->ah_capabilities.cap_mode)) {
2442 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2443 ath5k_chip_name(AR5K_VERSION_RAD,
2444 sc->ah->ah_radio_5ghz_revision),
2445 sc->ah->ah_radio_5ghz_revision);
2446 /* Multiband radio */
2447 } else {
2448 ATH5K_INFO(sc, "RF%s multiband radio found"
2449 " (0x%x)\n",
2450 ath5k_chip_name(AR5K_VERSION_RAD,
2451 sc->ah->ah_radio_5ghz_revision),
2452 sc->ah->ah_radio_5ghz_revision);
2453 }
2454 }
2455 /* Multi chip radio (RF5111 - RF2111) ->
2456 * report both 2GHz/5GHz radios */
2457 else if (sc->ah->ah_radio_5ghz_revision &&
2458 sc->ah->ah_radio_2ghz_revision){
2459 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2460 ath5k_chip_name(AR5K_VERSION_RAD,
2461 sc->ah->ah_radio_5ghz_revision),
2462 sc->ah->ah_radio_5ghz_revision);
2463 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2464 ath5k_chip_name(AR5K_VERSION_RAD,
2465 sc->ah->ah_radio_2ghz_revision),
2466 sc->ah->ah_radio_2ghz_revision);
2467 }
2468 }
2469
2470 ath5k_debug_init_device(sc);
2471
2472 /* ready to process interrupts */
2473 __clear_bit(ATH_STAT_INVALID, sc->status);
2474
2475 return 0;
2476err_ah:
2477 ath5k_hw_deinit(sc->ah);
2478err_free_ah:
2479 kfree(sc->ah);
2480err_irq:
2481 free_irq(sc->irq, sc);
2482err:
2483 return ret;
2484}
2485
fa1c114f 2486static int
8a63facc 2487ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2488{
8a63facc 2489 struct ath5k_hw *ah = sc->ah;
cec8db23 2490
8a63facc
BC		 2491 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2492 test_bit(ATH_STAT_INVALID, sc->status));
2493
2494 /*
2495 * Shutdown the hardware and driver:
2496 * stop output from above
2497 * disable interrupts
2498 * turn off timers
2499 * turn off the radio
2500 * clear transmit machinery
2501 * clear receive machinery
2502 * drain and release tx queues
2503 * reclaim beacon resources
2504 * power down hardware
2505 *
2506 * Note that some of this work is not possible if the
2507 * hardware is gone (invalid).
2508 */
2509 ieee80211_stop_queues(sc->hw);
2510
2511 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2512 ath5k_led_off(sc);
2513 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2514 synchronize_irq(sc->irq);
8a63facc 2515 ath5k_rx_stop(sc);
80dac9ee
NK		 2516 ath5k_hw_dma_stop(ah);
2517 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2518 ath5k_hw_phy_disable(ah);
2519 }
2520
2521 return 0;
cec8db23
BC		 2522}
2523
8a63facc 2524static int
132b1c3e 2525ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2526{
8a63facc
BC		 2527 struct ath5k_hw *ah = sc->ah;
2528 struct ath_common *common = ath5k_hw_common(ah);
2529 int ret, i;
fa1c114f 2530
8a63facc
BC		 2531 mutex_lock(&sc->lock);
2532
2533 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2534
fa1c114f 2535 /*
8a63facc
BC		 2536 * Stop anything previously setup. This is safe
2537 * no matter this is the first time through or not.
fa1c114f 2538 */
8a63facc 2539 ath5k_stop_locked(sc);
fa1c114f 2540
8a63facc
BC		 2541 /*
2542 * The basic interface to setting the hardware in a good
2543 * state is ``reset''. On return the hardware is known to
2544 * be powered up and with interrupts disabled. This must
2545 * be followed by initialization of the appropriate bits
2546 * and then setup of the interrupt mask.
2547 */
2548 sc->curchan = sc->hw->conf.channel;
2549 sc->curband = &sc->sbands[sc->curchan->band];
2550 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2551 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2552 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2553
8aec7af9 2554 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2555 if (ret)
2556 goto done;
fa1c114f 2557
8a63facc
BC		 2558 ath5k_rfkill_hw_start(ah);
2559
2560 /*
2561 * Reset the key cache since some parts do not reset the
2562 * contents on initial power up or resume from suspend.
2563 */
2564 for (i = 0; i < common->keymax; i++)
2565 ath_hw_keyreset(common, (u16) i);
2566
61cde037
NK		 2567 /* Use higher rates for acks instead of base
2568 * rate */
2569 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2570
2571 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2572 sc->bslot[i] = NULL;
2573
8a63facc
BC		 2574 ret = 0;
2575done:
2576 mmiowb();
2577 mutex_unlock(&sc->lock);
4edd761f
BR		 2578
2579 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2580 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2581
8a63facc
BC		 2582 return ret;
2583}
2584
2585static void stop_tasklets(struct ath5k_softc *sc)
2586{
2587 tasklet_kill(&sc->rxtq);
2588 tasklet_kill(&sc->txtq);
2589 tasklet_kill(&sc->calib);
2590 tasklet_kill(&sc->beacontq);
2591 tasklet_kill(&sc->ani_tasklet);
2592}
2593
2594/*
2595 * Stop the device, grabbing the top-level lock to protect
2596 * against concurrent entry through ath5k_init (which can happen
2597 * if another thread does a system call and the thread doing the
2598 * stop is preempted).
2599 */
2600static int
2601ath5k_stop_hw(struct ath5k_softc *sc)
2602{
2603 int ret;
2604
2605 mutex_lock(&sc->lock);
2606 ret = ath5k_stop_locked(sc);
2607 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2608 /*
2609 * Don't set the card in full sleep mode!
2610 *
2611 * a) When the device is in this state it must be carefully
2612 * woken up or references to registers in the PCI clock
2613 * domain may freeze the bus (and system). This varies
2614 * by chip and is mostly an issue with newer parts
2615 * (madwifi sources mentioned srev >= 0x78) that go to
2616 * sleep more quickly.
2617 *
2618 * b) On older chips full sleep results a weird behaviour
2619 * during wakeup. I tested various cards with srev < 0x78
2620 * and they don't wake up after module reload, a second
2621 * module reload is needed to bring the card up again.
2622 *
2623 * Until we figure out what's going on don't enable
2624 * full chip reset on any chip (this is what Legacy HAL
2625 * and Sam's HAL do anyway). Instead Perform a full reset
2626 * on the device (same as initial state after attach) and
2627 * leave it idle (keep MAC/BB on warm reset) */
2628 ret = ath5k_hw_on_hold(sc->ah);
2629
2630 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2631 "putting device to sleep\n");
fa1c114f
JS		 2632 }
2633
8a63facc
BC		 2634 mmiowb();
2635 mutex_unlock(&sc->lock);
2636
2637 stop_tasklets(sc);
2638
4edd761f
BR		 2639 cancel_delayed_work_sync(&sc->tx_complete_work);
2640
8a63facc
BC		 2641 ath5k_rfkill_hw_stop(sc->ah);
2642
2643 return ret;
fa1c114f
JS		 2644}
2645
209d889b
BC		 2646/*
2647 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2648 * and change to the given channel.
5faaff74
BC		 2649 *
2650 * This should be called with sc->lock.
209d889b 2651 */
fa1c114f 2652static int
8aec7af9
NK		 2653ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2654 bool skip_pcu)
fa1c114f 2655{
fa1c114f 2656 struct ath5k_hw *ah = sc->ah;
344b54b9 2657 int ret, ani_mode;
fa1c114f
JS		 2658
2659 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2660
450464de 2661 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2662 synchronize_irq(sc->irq);
450464de
BC		 2663 stop_tasklets(sc);
2664
344b54b9
NK		 2665 /* Save ani mode and disable ANI durring
2666 * reset. If we don't we might get false
2667 * PHY error interrupts. */
2668 ani_mode = ah->ah_sc->ani_state.ani_mode;
2669 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2670
19252ecb
NK		 2671 /* We are going to empty hw queues
2672 * so we should also free any remaining
2673 * tx buffers */
2674 ath5k_drain_tx_buffs(sc);
209d889b 2675 if (chan) {
209d889b
BC		 2676 sc->curchan = chan;
2677 sc->curband = &sc->sbands[chan->band];
d7dc1003 2678 }
8aec7af9
NK		 2679 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2680 skip_pcu);
d7dc1003 2681 if (ret) {
fa1c114f
JS		 2682 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2683 goto err;
2684 }
d7dc1003 2685
fa1c114f 2686 ret = ath5k_rx_start(sc);
d7dc1003 2687 if (ret) {
fa1c114f
JS		 2688 ATH5K_ERR(sc, "can't start recv logic\n");
2689 goto err;
2690 }
d7dc1003 2691
344b54b9 2692 ath5k_ani_init(ah, ani_mode);
2111ac0d 2693
ac559526
BR		 2694 ah->ah_cal_next_full = jiffies;
2695 ah->ah_cal_next_ani = jiffies;
afe86286 2696 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2697 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2698
fa1c114f 2699 /*
d7dc1003
JS		 2700 * Change channels and update the h/w rate map if we're switching;
2701 * e.g. 11a to 11b/g.
2702 *
2703 * We may be doing a reset in response to an ioctl that changes the
2704 * channel so update any state that might change as a result.
fa1c114f
JS		 2705 *
2706 * XXX needed?
2707 */
2708/* ath5k_chan_change(sc, c); */
fa1c114f 2709
d7dc1003
JS		 2710 ath5k_beacon_config(sc);
2711 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2712
397f385b
BR		 2713 ieee80211_wake_queues(sc->hw);
2714
fa1c114f
JS		 2715 return 0;
2716err:
2717 return ret;
2718}
2719
5faaff74
BC		 2720static void ath5k_reset_work(struct work_struct *work)
2721{
2722 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2723 reset_work);
2724
2725 mutex_lock(&sc->lock);
8aec7af9 2726 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2727 mutex_unlock(&sc->lock);
2728}
2729
8a63facc 2730static int
132b1c3e 2731ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2732{
132b1c3e 2733
fa1c114f 2734 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2735 struct ath5k_hw *ah = sc->ah;
2736 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2737 struct ath5k_txq *txq;
8a63facc 2738 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2739 int ret;
2740
fa1c114f 2741
8a63facc
BC		 2742 /*
2743 * Check if the MAC has multi-rate retry support.
2744 * We do this by trying to setup a fake extended
2745 * descriptor. MACs that don't have support will
2746 * return false w/o doing anything. MACs that do
2747 * support it will return true w/o doing anything.
2748 */
2749 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2750
8a63facc
BC		 2751 if (ret < 0)
2752 goto err;
2753 if (ret > 0)
2754 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2755
8a63facc
BC		 2756 /*
2757 * Collect the channel list. The 802.11 layer
2758 * is resposible for filtering this list based
2759 * on settings like the phy mode and regulatory
2760 * domain restrictions.
2761 */
2762 ret = ath5k_setup_bands(hw);
2763 if (ret) {
2764 ATH5K_ERR(sc, "can't get channels\n");
2765 goto err;
2766 }
67d2e2df 2767
8a63facc
BC		 2768 /* NB: setup here so ath5k_rate_update is happy */
2769 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2770 ath5k_setcurmode(sc, AR5K_MODE_11A);
2771 else
2772 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2773
8a63facc
BC		 2774 /*
2775 * Allocate tx+rx descriptors and populate the lists.
2776 */
aeae4ac9 2777 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2778 if (ret) {
2779 ATH5K_ERR(sc, "can't allocate descriptors\n");
2780 goto err;
2781 }
fa1c114f 2782
8a63facc
BC		 2783 /*
2784 * Allocate hardware transmit queues: one queue for
2785 * beacon frames and one data queue for each QoS
2786 * priority. Note that hw functions handle resetting
2787 * these queues at the needed time.
2788 */
2789 ret = ath5k_beaconq_setup(ah);
2790 if (ret < 0) {
2791 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2792 goto err_desc;
2793 }
2794 sc->bhalq = ret;
2795 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2796 if (IS_ERR(sc->cabq)) {
2797 ATH5K_ERR(sc, "can't setup cab queue\n");
2798 ret = PTR_ERR(sc->cabq);
2799 goto err_bhal;
2800 }
fa1c114f 2801
22d8d9f8
BR		 2802 /* 5211 and 5212 usually support 10 queues but we better rely on the
2803 * capability information */
2804 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2805 /* This order matches mac80211's queue priority, so we can
2806 * directly use the mac80211 queue number without any mapping */
2807 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2808 if (IS_ERR(txq)) {
2809 ATH5K_ERR(sc, "can't setup xmit queue\n");
2810 ret = PTR_ERR(txq);
2811 goto err_queues;
2812 }
2813 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2814 if (IS_ERR(txq)) {
2815 ATH5K_ERR(sc, "can't setup xmit queue\n");
2816 ret = PTR_ERR(txq);
2817 goto err_queues;
2818 }
2819 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2820 if (IS_ERR(txq)) {
2821 ATH5K_ERR(sc, "can't setup xmit queue\n");
2822 ret = PTR_ERR(txq);
2823 goto err_queues;
2824 }
2825 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2826 if (IS_ERR(txq)) {
2827 ATH5K_ERR(sc, "can't setup xmit queue\n");
2828 ret = PTR_ERR(txq);
2829 goto err_queues;
2830 }
2831 hw->queues = 4;
2832 } else {
2833 /* older hardware (5210) can only support one data queue */
2834 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2835 if (IS_ERR(txq)) {
2836 ATH5K_ERR(sc, "can't setup xmit queue\n");
2837 ret = PTR_ERR(txq);
2838 goto err_queues;
2839 }
2840 hw->queues = 1;
2841 }
fa1c114f 2842
8a63facc
BC		 2843 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2844 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2845 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2846 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2847 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2848
8a63facc 2849 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2850 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2851
8a63facc
BC		 2852 ret = ath5k_eeprom_read_mac(ah, mac);
2853 if (ret) {
aeae4ac9 2854 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2855 goto err_queues;
e30eb4ab 2856 }
2bed03eb 2857
8a63facc 2858 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2859 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2860 /* All MAC address bits matter for ACKs */
62c58fb4 2861 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2862
2863 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2864 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2865 if (ret) {
2866 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2867 goto err_queues;
2868 }
2869
2870 ret = ieee80211_register_hw(hw);
2871 if (ret) {
2872 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2873 goto err_queues;
2874 }
2875
2876 if (!ath_is_world_regd(regulatory))
2877 regulatory_hint(hw->wiphy, regulatory->alpha2);
2878
2879 ath5k_init_leds(sc);
2880
2881 ath5k_sysfs_register(sc);
2882
2883 return 0;
2884err_queues:
2885 ath5k_txq_release(sc);
2886err_bhal:
2887 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2888err_desc:
aeae4ac9 2889 ath5k_desc_free(sc);
8a63facc
BC		 2890err:
2891 return ret;
2892}
2893
132b1c3e
FF		 2894void
2895ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2896{
132b1c3e 2897 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2898
2899 /*
2900 * NB: the order of these is important:
2901 * o call the 802.11 layer before detaching ath5k_hw to
2902 * ensure callbacks into the driver to delete global
2903 * key cache entries can be handled
2904 * o reclaim the tx queue data structures after calling
2905 * the 802.11 layer as we'll get called back to reclaim
2906 * node state and potentially want to use them
2907 * o to cleanup the tx queues the hal is called, so detach
2908 * it last
2909 * XXX: ??? detach ath5k_hw ???
2910 * Other than that, it's straightforward...
2911 */
132b1c3e 2912 ath5k_debug_finish_device(sc);
8a63facc 2913 ieee80211_unregister_hw(hw);
aeae4ac9 2914 ath5k_desc_free(sc);
8a63facc
BC		 2915 ath5k_txq_release(sc);
2916 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2917 ath5k_unregister_leds(sc);
2918
2919 ath5k_sysfs_unregister(sc);
2920 /*
2921 * NB: can't reclaim these until after ieee80211_ifdetach
2922 * returns because we'll get called back to reclaim node
2923 * state and potentially want to use them.
2924 */
132b1c3e
FF		 2925 ath5k_hw_deinit(sc->ah);
2926 free_irq(sc->irq, sc);
8a63facc
BC		 2927}
2928
2929/********************\
2930* Mac80211 functions *
2931\********************/
2932
2933static int
2934ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2935{
2936 struct ath5k_softc *sc = hw->priv;
925e0b06
BR		 2937 u16 qnum = skb_get_queue_mapping(skb);
2938
2939 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2940 dev_kfree_skb_any(skb);
2941 return 0;
2942 }
8a63facc 2943
925e0b06 2944 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
8a63facc
BC		 2945}
2946
2947static int ath5k_start(struct ieee80211_hw *hw)
2948{
132b1c3e 2949 return ath5k_init_hw(hw->priv);
8a63facc
BC		 2950}
2951
2952static void ath5k_stop(struct ieee80211_hw *hw)
2953{
2954 ath5k_stop_hw(hw->priv);
2955}
2956
2957static int ath5k_add_interface(struct ieee80211_hw *hw,
2958 struct ieee80211_vif *vif)
2959{
2960 struct ath5k_softc *sc = hw->priv;
2961 int ret;
b1ae1edf 2962 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 2963
2964 mutex_lock(&sc->lock);
b1ae1edf
BG		 2965
2966 if ((vif->type == NL80211_IFTYPE_AP ||
2967 vif->type == NL80211_IFTYPE_ADHOC)
2968 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
2969 ret = -ELNRNG;
8a63facc
BC		 2970 goto end;
2971 }
2972
b1ae1edf
BG		 2973 /* Don't allow other interfaces if one ad-hoc is configured.
2974 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2975 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2976 * for the IBSS, but this breaks with additional AP or STA interfaces
2977 * at the moment. */
2978 if (sc->num_adhoc_vifs ||
2979 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
2980 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
2981 ret = -ELNRNG;
2982 goto end;
2983 }
8a63facc
BC		 2984
2985 switch (vif->type) {
2986 case NL80211_IFTYPE_AP:
2987 case NL80211_IFTYPE_STATION:
2988 case NL80211_IFTYPE_ADHOC:
2989 case NL80211_IFTYPE_MESH_POINT:
b1ae1edf 2990 avf->opmode = vif->type;
8a63facc
BC		 2991 break;
2992 default:
2993 ret = -EOPNOTSUPP;
2994 goto end;
2995 }
2996
b1ae1edf
BG		 2997 sc->nvifs++;
2998 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
8a63facc 2999
b1ae1edf
BG		 3000 /* Assign the vap/adhoc to a beacon xmit slot. */
3001 if ((avf->opmode == NL80211_IFTYPE_AP) ||
d82b577b
JC		 3002 (avf->opmode == NL80211_IFTYPE_ADHOC) ||
3003 (avf->opmode == NL80211_IFTYPE_MESH_POINT)) {
b1ae1edf
BG		 3004 int slot;
3005
3006 WARN_ON(list_empty(&sc->bcbuf));
3007 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
3008 list);
3009 list_del(&avf->bbuf->list);
3010
3011 avf->bslot = 0;
3012 for (slot = 0; slot < ATH_BCBUF; slot++) {
3013 if (!sc->bslot[slot]) {
3014 avf->bslot = slot;
3015 break;
3016 }
3017 }
3018 BUG_ON(sc->bslot[avf->bslot] != NULL);
3019 sc->bslot[avf->bslot] = vif;
3020 if (avf->opmode == NL80211_IFTYPE_AP)
3021 sc->num_ap_vifs++;
c26d5339 3022 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
b1ae1edf
BG		 3023 sc->num_adhoc_vifs++;
3024 }
3025
b1ae1edf
BG		 3026 /* Any MAC address is fine, all others are included through the
3027 * filter.
3028 */
3029 memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
8a63facc 3030 ath5k_hw_set_lladdr(sc->ah, vif->addr);
b1ae1edf
BG		 3031
3032 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
3033
3034 ath5k_mode_setup(sc, vif);
8a63facc
BC		 3035
3036 ret = 0;
3037end:
3038 mutex_unlock(&sc->lock);
3039 return ret;
3040}
3041
3042static void
3043ath5k_remove_interface(struct ieee80211_hw *hw,
3044 struct ieee80211_vif *vif)
3045{
3046 struct ath5k_softc *sc = hw->priv;
b1ae1edf
BG		 3047 struct ath5k_vif *avf = (void *)vif->drv_priv;
3048 unsigned int i;
8a63facc
BC		 3049
3050 mutex_lock(&sc->lock);
b1ae1edf
BG		 3051 sc->nvifs--;
3052
3053 if (avf->bbuf) {
3054 ath5k_txbuf_free_skb(sc, avf->bbuf);
3055 list_add_tail(&avf->bbuf->list, &sc->bcbuf);
3056 for (i = 0; i < ATH_BCBUF; i++) {
3057 if (sc->bslot[i] == vif) {
3058 sc->bslot[i] = NULL;
3059 break;
3060 }
3061 }
3062 avf->bbuf = NULL;
3063 }
3064 if (avf->opmode == NL80211_IFTYPE_AP)
3065 sc->num_ap_vifs--;
3066 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
3067 sc->num_adhoc_vifs--;
8a63facc 3068
62c58fb4 3069 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 3070 mutex_unlock(&sc->lock);
3071}
3072
3073/*
3074 * TODO: Phy disable/diversity etc
3075 */
3076static int
3077ath5k_config(struct ieee80211_hw *hw, u32 changed)
3078{
3079 struct ath5k_softc *sc = hw->priv;
3080 struct ath5k_hw *ah = sc->ah;
3081 struct ieee80211_conf *conf = &hw->conf;
3082 int ret = 0;
3083
3084 mutex_lock(&sc->lock);
3085
3086 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3087 ret = ath5k_chan_set(sc, conf->channel);
3088 if (ret < 0)
3089 goto unlock;
3090 }
3091
3092 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3093 (sc->power_level != conf->power_level)) {
a0823810
NK		 3094 sc->power_level = conf->power_level;
3095
3096 /* Half dB steps */
3097 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3098 }
fa1c114f 3099
2bed03eb
NK		 3100 /* TODO:
3101 * 1) Move this on config_interface and handle each case
3102 * separately eg. when we have only one STA vif, use
3103 * AR5K_ANTMODE_SINGLE_AP
3104 *
3105 * 2) Allow the user to change antenna mode eg. when only
3106 * one antenna is present
3107 *
3108 * 3) Allow the user to set default/tx antenna when possible
3109 *
3110 * 4) Default mode should handle 90% of the cases, together
3111 * with fixed a/b and single AP modes we should be able to
3112 * handle 99%. Sectored modes are extreme cases and i still
3113 * haven't found a usage for them. If we decide to support them,
3114 * then we must allow the user to set how many tx antennas we
3115 * have available
3116 */
caec9112 3117 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 3118
55aa4e0f 3119unlock:
be009370 3120 mutex_unlock(&sc->lock);
55aa4e0f 3121 return ret;
fa1c114f
JS		 3122}
3123
3ac64bee 3124static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 3125 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 3126{
3127 u32 mfilt[2], val;
3ac64bee 3128 u8 pos;
22bedad3 3129 struct netdev_hw_addr *ha;
3ac64bee
JB		 3130
3131 mfilt[0] = 0;
3132 mfilt[1] = 1;
3133
22bedad3 3134 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 3135 /* calculate XOR of eight 6-bit values */
22bedad3 3136 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 3137 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 3138 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 3139 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3140 pos &= 0x3f;
3141 mfilt[pos / 32] |= (1 << (pos % 32));
3142 /* XXX: we might be able to just do this instead,
3143 * but not sure, needs testing, if we do use this we'd
3144 * neet to inform below to not reset the mcast */
3145 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 3146 * ha->addr[5]); */
3ac64bee
JB		 3147 }
3148
3149 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3150}
3151
b1ae1edf
BG		 3152static bool ath_any_vif_assoc(struct ath5k_softc *sc)
3153{
3154 struct ath_vif_iter_data iter_data;
3155 iter_data.hw_macaddr = NULL;
3156 iter_data.any_assoc = false;
3157 iter_data.need_set_hw_addr = false;
3158 iter_data.found_active = true;
3159
3160 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
3161 &iter_data);
3162 return iter_data.any_assoc;
3163}
3164
fa1c114f
JS		 3165#define SUPPORTED_FIF_FLAGS \
3166 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3167 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3168 FIF_BCN_PRBRESP_PROMISC
3169/*
3170 * o always accept unicast, broadcast, and multicast traffic
3171 * o multicast traffic for all BSSIDs will be enabled if mac80211
3172 * says it should be
3173 * o maintain current state of phy ofdm or phy cck error reception.
3174 * If the hardware detects any of these type of errors then
3175 * ath5k_hw_get_rx_filter() will pass to us the respective
3176 * hardware filters to be able to receive these type of frames.
3177 * o probe request frames are accepted only when operating in
3178 * hostap, adhoc, or monitor modes
3179 * o enable promiscuous mode according to the interface state
3180 * o accept beacons:
3181 * - when operating in adhoc mode so the 802.11 layer creates
3182 * node table entries for peers,
3183 * - when operating in station mode for collecting rssi data when
3184 * the station is otherwise quiet, or
3185 * - when scanning
3186 */
3187static void ath5k_configure_filter(struct ieee80211_hw *hw,
3188 unsigned int changed_flags,
3189 unsigned int *new_flags,
3ac64bee 3190 u64 multicast)
fa1c114f
JS		 3191{
3192 struct ath5k_softc *sc = hw->priv;
3193 struct ath5k_hw *ah = sc->ah;
3ac64bee 3194 u32 mfilt[2], rfilt;
fa1c114f 3195
56d1de0a
BC		 3196 mutex_lock(&sc->lock);
3197
3ac64bee
JB		 3198 mfilt[0] = multicast;
3199 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3200
3201 /* Only deal with supported flags */
3202 changed_flags &= SUPPORTED_FIF_FLAGS;
3203 *new_flags &= SUPPORTED_FIF_FLAGS;
3204
3205 /* If HW detects any phy or radar errors, leave those filters on.
3206 * Also, always enable Unicast, Broadcasts and Multicast
3207 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3208 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3209 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3210 AR5K_RX_FILTER_MCAST);
3211
3212 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3213 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 3214 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3215 } else {
fa1c114f 3216 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3217 }
fa1c114f
JS		 3218 }
3219
6b5dcccb
BC		 3220 if (test_bit(ATH_STAT_PROMISC, sc->status))
3221 rfilt |= AR5K_RX_FILTER_PROM;
3222
fa1c114f
JS		 3223 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3224 if (*new_flags & FIF_ALLMULTI) {
3225 mfilt[0] = ~0;
3226 mfilt[1] = ~0;
fa1c114f
JS		 3227 }
3228
3229 /* This is the best we can do */
3230 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3231 rfilt |= AR5K_RX_FILTER_PHYERR;
3232
3233 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
30bf4169 3234 * and probes for any BSSID */
b1ae1edf 3235 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
30bf4169 3236 rfilt |= AR5K_RX_FILTER_BEACON;
fa1c114f
JS		 3237
3238 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3239 * set we should only pass on control frames for this
3240 * station. This needs testing. I believe right now this
3241 * enables *all* control frames, which is OK.. but
3242 * but we should see if we can improve on granularity */
3243 if (*new_flags & FIF_CONTROL)
3244 rfilt |= AR5K_RX_FILTER_CONTROL;
3245
3246 /* Additional settings per mode -- this is per ath5k */
3247
3248 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3249
56d1de0a
BC		 3250 switch (sc->opmode) {
3251 case NL80211_IFTYPE_MESH_POINT:
56d1de0a
BC		 3252 rfilt |= AR5K_RX_FILTER_CONTROL |
3253 AR5K_RX_FILTER_BEACON |
3254 AR5K_RX_FILTER_PROBEREQ |
3255 AR5K_RX_FILTER_PROM;
3256 break;
3257 case NL80211_IFTYPE_AP:
3258 case NL80211_IFTYPE_ADHOC:
3259 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3260 AR5K_RX_FILTER_BEACON;
3261 break;
3262 case NL80211_IFTYPE_STATION:
3263 if (sc->assoc)
3264 rfilt |= AR5K_RX_FILTER_BEACON;
3265 default:
3266 break;
3267 }
fa1c114f
JS		 3268
3269 /* Set filters */
0bbac08f 3270 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3271
3272 /* Set multicast bits */
3273 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
a180a130 3274 /* Set the cached hw filter flags, this will later actually
fa1c114f
JS		 3275 * be set in HW */
3276 sc->filter_flags = rfilt;
56d1de0a
BC		 3277
3278 mutex_unlock(&sc->lock);
fa1c114f
JS		 3279}
3280
3281static int
3282ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3283 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3284 struct ieee80211_key_conf *key)
fa1c114f
JS		 3285{
3286 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3287 struct ath5k_hw *ah = sc->ah;
3288 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3289 int ret = 0;
3290
9ad9a26e
BC		 3291 if (modparam_nohwcrypt)
3292 return -EOPNOTSUPP;
3293
97359d12
JB		 3294 switch (key->cipher) {
3295 case WLAN_CIPHER_SUITE_WEP40:
3296 case WLAN_CIPHER_SUITE_WEP104:
3297 case WLAN_CIPHER_SUITE_TKIP:
3f64b435 3298 break;
97359d12 3299 case WLAN_CIPHER_SUITE_CCMP:
781f3136 3300 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
1c818740 3301 break;
fa1c114f
JS		 3302 return -EOPNOTSUPP;
3303 default:
3304 WARN_ON(1);
3305 return -EINVAL;
3306 }
3307
3308 mutex_lock(&sc->lock);
3309
3310 switch (cmd) {
3311 case SET_KEY:
e0f8c2a9
BR		 3312 ret = ath_key_config(common, vif, sta, key);
3313 if (ret >= 0) {
3314 key->hw_key_idx = ret;
3315 /* push IV and Michael MIC generation to stack */
3316 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3317 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3318 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3319 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3320 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3321 ret = 0;
fa1c114f 3322 }
fa1c114f
JS		 3323 break;
3324 case DISABLE_KEY:
e0f8c2a9 3325 ath_key_delete(common, key);
fa1c114f
JS		 3326 break;
3327 default:
3328 ret = -EINVAL;
fa1c114f
JS		 3329 }
3330
8a63facc
BC		 3331 mmiowb();
3332 mutex_unlock(&sc->lock);
3333 return ret;
3334}
3335
3336static int
3337ath5k_get_stats(struct ieee80211_hw *hw,
3338 struct ieee80211_low_level_stats *stats)
3339{
3340 struct ath5k_softc *sc = hw->priv;
3341
3342 /* Force update */
3343 ath5k_hw_update_mib_counters(sc->ah);
3344
3345 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3346 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3347 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3348 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3349
3350 return 0;
3351}
3352
3353static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3354 struct survey_info *survey)
3355{
3356 struct ath5k_softc *sc = hw->priv;
3357 struct ieee80211_conf *conf = &hw->conf;
edb40a23
BR		 3358 struct ath_common *common = ath5k_hw_common(sc->ah);
3359 struct ath_cycle_counters *cc = &common->cc_survey;
3360 unsigned int div = common->clockrate * 1000;
8a63facc 3361
edb40a23 3362 if (idx != 0)
8a63facc
BC		 3363 return -ENOENT;
3364
3365 survey->channel = conf->channel;
3366 survey->filled = SURVEY_INFO_NOISE_DBM;
3367 survey->noise = sc->ah->ah_noise_floor;
3368
edb40a23
BR		 3369 spin_lock_bh(&common->cc_lock);
3370 ath_hw_cycle_counters_update(common);
3371 if (cc->cycles > 0) {
3372 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
3373 SURVEY_INFO_CHANNEL_TIME_BUSY |
3374 SURVEY_INFO_CHANNEL_TIME_RX |
3375 SURVEY_INFO_CHANNEL_TIME_TX;
3376 survey->channel_time += cc->cycles / div;
3377 survey->channel_time_busy += cc->rx_busy / div;
3378 survey->channel_time_rx += cc->rx_frame / div;
3379 survey->channel_time_tx += cc->tx_frame / div;
3380 }
3381 memset(cc, 0, sizeof(*cc));
3382 spin_unlock_bh(&common->cc_lock);
3383
8a63facc
BC		 3384 return 0;
3385}
3386
3387static u64
3388ath5k_get_tsf(struct ieee80211_hw *hw)
3389{
3390 struct ath5k_softc *sc = hw->priv;
3391
3392 return ath5k_hw_get_tsf64(sc->ah);
3393}
3394
3395static void
3396ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3397{
3398 struct ath5k_softc *sc = hw->priv;
3399
3400 ath5k_hw_set_tsf64(sc->ah, tsf);
3401}
3402
3403static void
3404ath5k_reset_tsf(struct ieee80211_hw *hw)
3405{
3406 struct ath5k_softc *sc = hw->priv;
3407
3408 /*
3409 * in IBSS mode we need to update the beacon timers too.
3410 * this will also reset the TSF if we call it with 0
3411 */
3412 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3413 ath5k_beacon_update_timers(sc, 0);
3414 else
3415 ath5k_hw_reset_tsf(sc->ah);
3416}
3417
3418static void
3419set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3420{
3421 struct ath5k_softc *sc = hw->priv;
3422 struct ath5k_hw *ah = sc->ah;
3423 u32 rfilt;
3424 rfilt = ath5k_hw_get_rx_filter(ah);
3425 if (enable)
3426 rfilt |= AR5K_RX_FILTER_BEACON;
3427 else
3428 rfilt &= ~AR5K_RX_FILTER_BEACON;
3429 ath5k_hw_set_rx_filter(ah, rfilt);
3430 sc->filter_flags = rfilt;
3431}
3432
3433static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3434 struct ieee80211_vif *vif,
3435 struct ieee80211_bss_conf *bss_conf,
3436 u32 changes)
3437{
b1ae1edf 3438 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 3439 struct ath5k_softc *sc = hw->priv;
3440 struct ath5k_hw *ah = sc->ah;
3441 struct ath_common *common = ath5k_hw_common(ah);
3442 unsigned long flags;
3443
3444 mutex_lock(&sc->lock);
8a63facc
BC		 3445
3446 if (changes & BSS_CHANGED_BSSID) {
3447 /* Cache for later use during resets */
3448 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3449 common->curaid = 0;
3450 ath5k_hw_set_bssid(ah);
3451 mmiowb();
3452 }
3453
3454 if (changes & BSS_CHANGED_BEACON_INT)
3455 sc->bintval = bss_conf->beacon_int;
3456
3457 if (changes & BSS_CHANGED_ASSOC) {
b1ae1edf
BG		 3458 avf->assoc = bss_conf->assoc;
3459 if (bss_conf->assoc)
3460 sc->assoc = bss_conf->assoc;
3461 else
3462 sc->assoc = ath_any_vif_assoc(sc);
3463
8a63facc
BC		 3464 if (sc->opmode == NL80211_IFTYPE_STATION)
3465 set_beacon_filter(hw, sc->assoc);
3466 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3467 AR5K_LED_ASSOC : AR5K_LED_INIT);
3468 if (bss_conf->assoc) {
3469 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3470 "Bss Info ASSOC %d, bssid: %pM\n",
3471 bss_conf->aid, common->curbssid);
3472 common->curaid = bss_conf->aid;
3473 ath5k_hw_set_bssid(ah);
3474 /* Once ANI is available you would start it here */
3475 }
3476 }
3477
3478 if (changes & BSS_CHANGED_BEACON) {
3479 spin_lock_irqsave(&sc->block, flags);
3480 ath5k_beacon_update(hw, vif);
3481 spin_unlock_irqrestore(&sc->block, flags);
3482 }
3483
3484 if (changes & BSS_CHANGED_BEACON_ENABLED)
3485 sc->enable_beacon = bss_conf->enable_beacon;
3486
3487 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3488 BSS_CHANGED_BEACON_INT))
3489 ath5k_beacon_config(sc);
3490
8a63facc
BC		 3491 mutex_unlock(&sc->lock);
3492}
3493
3494static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3495{
3496 struct ath5k_softc *sc = hw->priv;
3497 if (!sc->assoc)
3498 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3499}
3500
3501static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3502{
3503 struct ath5k_softc *sc = hw->priv;
3504 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3505 AR5K_LED_ASSOC : AR5K_LED_INIT);
3506}
3507
3508/**
3509 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3510 *
3511 * @hw: struct ieee80211_hw pointer
3512 * @coverage_class: IEEE 802.11 coverage class number
3513 *
3514 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3515 * coverage class. The values are persistent, they are restored after device
3516 * reset.
3517 */
3518static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3519{
3520 struct ath5k_softc *sc = hw->priv;
3521
3522 mutex_lock(&sc->lock);
3523 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3524 mutex_unlock(&sc->lock);
3525}
3526
e0b1cc52
BR		 3527static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3528 const struct ieee80211_tx_queue_params *params)
3529{
3530 struct ath5k_softc *sc = hw->priv;
3531 struct ath5k_hw *ah = sc->ah;
3532 struct ath5k_txq_info qi;
3533 int ret = 0;
3534
3535 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3536 return 0;
3537
3538 mutex_lock(&sc->lock);
3539
3540 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3541
3542 qi.tqi_aifs = params->aifs;
3543 qi.tqi_cw_min = params->cw_min;
3544 qi.tqi_cw_max = params->cw_max;
3545 qi.tqi_burst_time = params->txop;
3546
3547 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3548 "Configure tx [queue %d], "
3549 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3550 queue, params->aifs, params->cw_min,
3551 params->cw_max, params->txop);
3552
3553 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3554 ATH5K_ERR(sc,
3555 "Unable to update hardware queue %u!\n", queue);
3556 ret = -EIO;
3557 } else
3558 ath5k_hw_reset_tx_queue(ah, queue);
3559
3560 mutex_unlock(&sc->lock);
3561
3562 return ret;
3563}
3564
72a80110
BR		 3565static int ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
3566{
3567 struct ath5k_softc *sc = hw->priv;
3568
3569 if (tx_ant == 1 && rx_ant == 1)
3570 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
3571 else if (tx_ant == 2 && rx_ant == 2)
3572 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
3573 else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
3574 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
3575 else
3576 return -EINVAL;
3577 return 0;
3578}
3579
3580static int ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
3581{
3582 struct ath5k_softc *sc = hw->priv;
3583
3584 switch (sc->ah->ah_ant_mode) {
3585 case AR5K_ANTMODE_FIXED_A:
3586 *tx_ant = 1; *rx_ant = 1; break;
3587 case AR5K_ANTMODE_FIXED_B:
3588 *tx_ant = 2; *rx_ant = 2; break;
3589 case AR5K_ANTMODE_DEFAULT:
3590 *tx_ant = 3; *rx_ant = 3; break;
3591 }
3592 return 0;
3593}
3594
132b1c3e 3595const struct ieee80211_ops ath5k_hw_ops = {
8a63facc
BC		 3596 .tx = ath5k_tx,
3597 .start = ath5k_start,
3598 .stop = ath5k_stop,
3599 .add_interface = ath5k_add_interface,
3600 .remove_interface = ath5k_remove_interface,
3601 .config = ath5k_config,
3602 .prepare_multicast = ath5k_prepare_multicast,
3603 .configure_filter = ath5k_configure_filter,
3604 .set_key = ath5k_set_key,
3605 .get_stats = ath5k_get_stats,
3606 .get_survey = ath5k_get_survey,
e0b1cc52 3607 .conf_tx = ath5k_conf_tx,
8a63facc
BC		 3608 .get_tsf = ath5k_get_tsf,
3609 .set_tsf = ath5k_set_tsf,
3610 .reset_tsf = ath5k_reset_tsf,
3611 .bss_info_changed = ath5k_bss_info_changed,
3612 .sw_scan_start = ath5k_sw_scan_start,
3613 .sw_scan_complete = ath5k_sw_scan_complete,
3614 .set_coverage_class = ath5k_set_coverage_class,
72a80110
BR		 3615 .set_antenna = ath5k_set_antenna,
3616 .get_antenna = ath5k_get_antenna,
8a63facc 3617};
Linux kernel - Deliverables
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