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cfg80211/mac80211: report signal strength for mgmt frames
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
b7f080cf 45#include <linux/dma-mapping.h>
274c7c36 46#include <linux/hardirq.h>
fa1c114f 47#include <linux/if.h>
274c7c36 48#include <linux/io.h>
fa1c114f
JS		 49#include <linux/netdevice.h>
50#include <linux/cache.h>
fa1c114f
JS		 51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
5a0e3ad6 53#include <linux/slab.h>
b1ae1edf 54#include <linux/etherdevice.h>
931be260 55#include <linux/nl80211.h>
fa1c114f
JS		 56
57#include <net/ieee80211_radiotap.h>
58
59#include <asm/unaligned.h>
60
61#include "base.h"
62#include "reg.h"
63#include "debug.h"
2111ac0d 64#include "ani.h"
931be260
PR		 65#include "ath5k.h"
66#include "../regd.h"
fa1c114f 67
0e472252
BC		 68#define CREATE_TRACE_POINTS
69#include "trace.h"
70
eb939922 71bool ath5k_modparam_nohwcrypt;
18cb6e32 72module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 73MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 74
eb939922 75static bool modparam_all_channels;
46802a4f 76module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 77MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
78
eb939922 79static bool modparam_fastchanswitch;
a99168ee
NK		 80module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
81MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
82
11deb533 83static bool ath5k_modparam_no_hw_rfkill_switch;
84e1e737
NK		 84module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
85 bool, S_IRUGO);
86MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
87
a99168ee 88
fa1c114f
JS		 89/* Module info */
90MODULE_AUTHOR("Jiri Slaby");
91MODULE_AUTHOR("Nick Kossifidis");
92MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
93MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
94MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 95
132b1c3e 96static int ath5k_init(struct ieee80211_hw *hw);
e0d687bd 97static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
8aec7af9 98 bool skip_pcu);
fa1c114f 99
fa1c114f 100/* Known SREVs */
2c91108c 101static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 102#ifdef CONFIG_ATHEROS_AR231X
103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
104 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
105 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
107 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
109 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
110#else
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 129#endif
1bef016a 130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 143 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 144 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 145#ifdef CONFIG_ATHEROS_AR231X
146 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
147 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
148#endif
fa1c114f
JS		 149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150};
151
2c91108c 152static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 153 { .bitrate = 10,
154 .hw_value = ATH5K_RATE_CODE_1M, },
155 { .bitrate = 20,
156 .hw_value = ATH5K_RATE_CODE_2M,
157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 { .bitrate = 55,
160 .hw_value = ATH5K_RATE_CODE_5_5M,
161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
162 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
163 { .bitrate = 110,
164 .hw_value = ATH5K_RATE_CODE_11M,
165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
166 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
167 { .bitrate = 60,
168 .hw_value = ATH5K_RATE_CODE_6M,
169 .flags = 0 },
170 { .bitrate = 90,
171 .hw_value = ATH5K_RATE_CODE_9M,
172 .flags = 0 },
173 { .bitrate = 120,
174 .hw_value = ATH5K_RATE_CODE_12M,
175 .flags = 0 },
176 { .bitrate = 180,
177 .hw_value = ATH5K_RATE_CODE_18M,
178 .flags = 0 },
179 { .bitrate = 240,
180 .hw_value = ATH5K_RATE_CODE_24M,
181 .flags = 0 },
182 { .bitrate = 360,
183 .hw_value = ATH5K_RATE_CODE_36M,
184 .flags = 0 },
185 { .bitrate = 480,
186 .hw_value = ATH5K_RATE_CODE_48M,
187 .flags = 0 },
188 { .bitrate = 540,
189 .hw_value = ATH5K_RATE_CODE_54M,
190 .flags = 0 },
63266a65
BR		 191};
192
fa1c114f
JS		 193static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
194{
195 u64 tsf = ath5k_hw_get_tsf64(ah);
196
197 if ((tsf & 0x7fff) < rstamp)
198 tsf -= 0x8000;
199
200 return (tsf & ~0x7fff) | rstamp;
201}
202
e5b046d8 203const char *
fa1c114f
JS		 204ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
205{
206 const char *name = "xxxxx";
207 unsigned int i;
208
209 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
210 if (srev_names[i].sr_type != type)
211 continue;
75d0edb8
NK		 212
213 if ((val & 0xf0) == srev_names[i].sr_val)
214 name = srev_names[i].sr_name;
215
216 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 217 name = srev_names[i].sr_name;
218 break;
219 }
220 }
221
222 return name;
223}
e5aa8474
LR		 224static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
225{
226 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
227 return ath5k_hw_reg_read(ah, reg_offset);
228}
229
230static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
231{
232 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
233 ath5k_hw_reg_write(ah, val, reg_offset);
234}
235
236static const struct ath_ops ath5k_common_ops = {
237 .read = ath5k_ioread32,
238 .write = ath5k_iowrite32,
239};
fa1c114f 240
8a63facc
BC		 241/***********************\
242* Driver Initialization *
243\***********************/
244
245static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 246{
8a63facc 247 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
e0d687bd
PR		 248 struct ath5k_hw *ah = hw->priv;
249 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
fa1c114f 250
8a63facc
BC		 251 return ath_reg_notifier_apply(wiphy, request, regulatory);
252}
6ccf15a1 253
8a63facc
BC		 254/********************\
255* Channel/mode setup *
256\********************/
fa1c114f 257
8a63facc
BC		 258/*
259 * Returns true for the channel numbers used without all_channels modparam.
260 */
410e6120 261static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 262{
410e6120
BR		 263 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
264 return true;
265
266 return /* UNII 1,2 */
267 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 268 /* midband */
269 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
270 /* UNII-3 */
410e6120
BR		 271 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
272 /* 802.11j 5.030-5.080 GHz (20MHz) */
273 (chan == 8 || chan == 12 || chan == 16) ||
274 /* 802.11j 4.9GHz (20MHz) */
275 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 276}
fa1c114f 277
8a63facc 278static unsigned int
97d9c3a3
BR		 279ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
280 unsigned int mode, unsigned int max)
8a63facc 281{
32c25464 282 unsigned int count, size, freq, ch;
90c02d72 283 enum ieee80211_band band;
fa1c114f 284
8a63facc
BC		 285 switch (mode) {
286 case AR5K_MODE_11A:
8a63facc 287 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 288 size = 220;
90c02d72 289 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 290 break;
291 case AR5K_MODE_11B:
292 case AR5K_MODE_11G:
8a63facc 293 size = 26;
90c02d72 294 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 295 break;
296 default:
e0d687bd 297 ATH5K_WARN(ah, "bad mode, not copying channels\n");
8a63facc 298 return 0;
fa1c114f
JS		 299 }
300
2b1351a3
BR		 301 count = 0;
302 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 303 freq = ieee80211_channel_to_frequency(ch, band);
304
305 if (freq == 0) /* mapping failed - not a standard channel */
306 continue;
fa1c114f 307
32c25464
PR		 308 /* Write channel info, needed for ath5k_channel_ok() */
309 channels[count].center_freq = freq;
310 channels[count].band = band;
311 channels[count].hw_value = mode;
312
8a63facc 313 /* Check if channel is supported by the chipset */
32c25464 314 if (!ath5k_channel_ok(ah, &channels[count]))
8a63facc 315 continue;
f59ac048 316
410e6120
BR		 317 if (!modparam_all_channels &&
318 !ath5k_is_standard_channel(ch, band))
8a63facc 319 continue;
f59ac048 320
8a63facc 321 count++;
8a63facc 322 }
fa1c114f 323
8a63facc
BC		 324 return count;
325}
fa1c114f 326
8a63facc 327static void
e0d687bd 328ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
8a63facc
BC		 329{
330 u8 i;
fa1c114f 331
8a63facc 332 for (i = 0; i < AR5K_MAX_RATES; i++)
e0d687bd 333 ah->rate_idx[b->band][i] = -1;
fa1c114f 334
8a63facc 335 for (i = 0; i < b->n_bitrates; i++) {
e0d687bd 336 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
8a63facc 337 if (b->bitrates[i].hw_value_short)
e0d687bd 338 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 339 }
8a63facc 340}
fa1c114f 341
8a63facc
BC		 342static int
343ath5k_setup_bands(struct ieee80211_hw *hw)
344{
e0d687bd 345 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 346 struct ieee80211_supported_band *sband;
347 int max_c, count_c = 0;
348 int i;
fa1c114f 349
e0d687bd
PR		 350 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
351 max_c = ARRAY_SIZE(ah->channels);
db719718 352
8a63facc 353 /* 2GHz band */
e0d687bd 354 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
8a63facc 355 sband->band = IEEE80211_BAND_2GHZ;
e0d687bd 356 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
9adca126 357
e0d687bd 358 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
8a63facc
BC		 359 /* G mode */
360 memcpy(sband->bitrates, &ath5k_rates[0],
361 sizeof(struct ieee80211_rate) * 12);
362 sband->n_bitrates = 12;
2f7fe870 363
e0d687bd 364 sband->channels = ah->channels;
08105690 365 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 366 AR5K_MODE_11G, max_c);
fa1c114f 367
8a63facc
BC		 368 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
369 count_c = sband->n_channels;
370 max_c -= count_c;
e0d687bd 371 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
8a63facc
BC		 372 /* B mode */
373 memcpy(sband->bitrates, &ath5k_rates[0],
374 sizeof(struct ieee80211_rate) * 4);
375 sband->n_bitrates = 4;
fa1c114f 376
8a63facc
BC		 377 /* 5211 only supports B rates and uses 4bit rate codes
378 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
379 * fix them up here:
380 */
381 if (ah->ah_version == AR5K_AR5211) {
382 for (i = 0; i < 4; i++) {
383 sband->bitrates[i].hw_value =
384 sband->bitrates[i].hw_value & 0xF;
385 sband->bitrates[i].hw_value_short =
386 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 387 }
388 }
fa1c114f 389
e0d687bd 390 sband->channels = ah->channels;
08105690 391 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 392 AR5K_MODE_11B, max_c);
fa1c114f 393
8a63facc
BC		 394 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
395 count_c = sband->n_channels;
396 max_c -= count_c;
397 }
e0d687bd 398 ath5k_setup_rate_idx(ah, sband);
fa1c114f 399
8a63facc 400 /* 5GHz band, A mode */
e0d687bd
PR		 401 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
402 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
8a63facc 403 sband->band = IEEE80211_BAND_5GHZ;
e0d687bd 404 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 405
8a63facc
BC		 406 memcpy(sband->bitrates, &ath5k_rates[4],
407 sizeof(struct ieee80211_rate) * 8);
408 sband->n_bitrates = 8;
fa1c114f 409
e0d687bd 410 sband->channels = &ah->channels[count_c];
08105690 411 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 412 AR5K_MODE_11A, max_c);
fa1c114f 413
8a63facc
BC		 414 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
415 }
e0d687bd 416 ath5k_setup_rate_idx(ah, sband);
8a63facc 417
e0d687bd 418 ath5k_debug_dump_bands(ah);
fa1c114f 419
fa1c114f
JS		 420 return 0;
421}
422
8a63facc
BC		 423/*
424 * Set/change channels. We always reset the chip.
425 * To accomplish this we must first cleanup any pending DMA,
426 * then restart stuff after a la ath5k_init.
427 *
e0d687bd 428 * Called with ah->lock.
8a63facc 429 */
cd2c5486 430int
e0d687bd 431ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
8a63facc 432{
e0d687bd 433 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8a63facc 434 "channel set, resetting (%u -> %u MHz)\n",
e0d687bd 435 ah->curchan->center_freq, chan->center_freq);
8a63facc 436
8451d22d 437 /*
8a63facc
BC		 438 * To switch channels clear any pending DMA operations;
439 * wait long enough for the RX fifo to drain, reset the
440 * hardware at the new frequency, and then re-enable
441 * the relevant bits of the h/w.
8451d22d 442 */
e0d687bd 443 return ath5k_reset(ah, chan, true);
fa1c114f 444}
fa1c114f 445
e4b0b32a 446void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
b1ae1edf 447{
e4b0b32a 448 struct ath5k_vif_iter_data *iter_data = data;
b1ae1edf 449 int i;
62c58fb4 450 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 451
452 if (iter_data->hw_macaddr)
453 for (i = 0; i < ETH_ALEN; i++)
454 iter_data->mask[i] &=
455 ~(iter_data->hw_macaddr[i] ^ mac[i]);
456
457 if (!iter_data->found_active) {
458 iter_data->found_active = true;
459 memcpy(iter_data->active_mac, mac, ETH_ALEN);
460 }
461
462 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
463 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
464 iter_data->need_set_hw_addr = false;
465
466 if (!iter_data->any_assoc) {
b1ae1edf
BG		 467 if (avf->assoc)
468 iter_data->any_assoc = true;
469 }
62c58fb4
BG		 470
471 /* Calculate combined mode - when APs are active, operate in AP mode.
472 * Otherwise use the mode of the new interface. This can currently
473 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 474 * interfaces is allowed.
62c58fb4
BG		 475 */
476 if (avf->opmode == NL80211_IFTYPE_AP)
477 iter_data->opmode = NL80211_IFTYPE_AP;
e4b0b32a
BG		 478 else {
479 if (avf->opmode == NL80211_IFTYPE_STATION)
480 iter_data->n_stas++;
62c58fb4
BG		 481 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
482 iter_data->opmode = avf->opmode;
e4b0b32a 483 }
b1ae1edf
BG		 484}
485
cd2c5486 486void
e0d687bd 487ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
cd2c5486 488 struct ieee80211_vif *vif)
b1ae1edf 489{
e0d687bd 490 struct ath_common *common = ath5k_hw_common(ah);
e4b0b32a
BG		 491 struct ath5k_vif_iter_data iter_data;
492 u32 rfilt;
b1ae1edf
BG		 493
494 /*
495 * Use the hardware MAC address as reference, the hardware uses it
496 * together with the BSSID mask when matching addresses.
497 */
498 iter_data.hw_macaddr = common->macaddr;
499 memset(&iter_data.mask, 0xff, ETH_ALEN);
500 iter_data.found_active = false;
501 iter_data.need_set_hw_addr = true;
62c58fb4 502 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
e4b0b32a 503 iter_data.n_stas = 0;
b1ae1edf
BG		 504
505 if (vif)
e4b0b32a 506 ath5k_vif_iter(&iter_data, vif->addr, vif);
b1ae1edf
BG		 507
508 /* Get list of all active MAC addresses */
e0d687bd 509 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
b1ae1edf 510 &iter_data);
e0d687bd 511 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
b1ae1edf 512
e0d687bd
PR		 513 ah->opmode = iter_data.opmode;
514 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
62c58fb4 515 /* Nothing active, default to station mode */
e0d687bd 516 ah->opmode = NL80211_IFTYPE_STATION;
62c58fb4 517
e0d687bd
PR		 518 ath5k_hw_set_opmode(ah, ah->opmode);
519 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
520 ah->opmode, ath_opmode_to_string(ah->opmode));
62c58fb4 521
b1ae1edf 522 if (iter_data.need_set_hw_addr && iter_data.found_active)
e0d687bd 523 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
b1ae1edf 524
e0d687bd
PR		 525 if (ath5k_hw_hasbssidmask(ah))
526 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
b1ae1edf 527
e4b0b32a
BG		 528 /* Set up RX Filter */
529 if (iter_data.n_stas > 1) {
530 /* If you have multiple STA interfaces connected to
531 * different APs, ARPs are not received (most of the time?)
6a2a0e73 532 * Enabling PROMISC appears to fix that problem.
e4b0b32a 533 */
e0d687bd 534 ah->filter_flags |= AR5K_RX_FILTER_PROM;
e4b0b32a 535 }
fa1c114f 536
e0d687bd
PR		 537 rfilt = ah->filter_flags;
538 ath5k_hw_set_rx_filter(ah, rfilt);
539 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
8a63facc 540}
fa1c114f 541
8a63facc 542static inline int
e0d687bd 543ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
8a63facc
BC		 544{
545 int rix;
fa1c114f 546
8a63facc
BC		 547 /* return base rate on errors */
548 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
549 "hw_rix out of bounds: %x\n", hw_rix))
550 return 0;
551
e0d687bd 552 rix = ah->rate_idx[ah->curchan->band][hw_rix];
8a63facc
BC		 553 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
554 rix = 0;
555
556 return rix;
557}
558
559/***************\
560* Buffers setup *
561\***************/
562
563static
e0d687bd 564struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
8a63facc 565{
e0d687bd 566 struct ath_common *common = ath5k_hw_common(ah);
8a63facc 567 struct sk_buff *skb;
fa1c114f
JS		 568
569 /*
8a63facc
BC		 570 * Allocate buffer with headroom_needed space for the
571 * fake physical layer header at the start.
fa1c114f 572 */
8a63facc
BC		 573 skb = ath_rxbuf_alloc(common,
574 common->rx_bufsize,
575 GFP_ATOMIC);
fa1c114f 576
8a63facc 577 if (!skb) {
e0d687bd 578 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
8a63facc
BC		 579 common->rx_bufsize);
580 return NULL;
fa1c114f
JS		 581 }
582
e0d687bd 583 *skb_addr = dma_map_single(ah->dev,
8a63facc 584 skb->data, common->rx_bufsize,
aeae4ac9
FF		 585 DMA_FROM_DEVICE);
586
e0d687bd
PR		 587 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
588 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
8a63facc
BC		 589 dev_kfree_skb(skb);
590 return NULL;
0e149cf5 591 }
8a63facc
BC		 592 return skb;
593}
0e149cf5 594
8a63facc 595static int
e0d687bd 596ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
8a63facc 597{
8a63facc
BC		 598 struct sk_buff *skb = bf->skb;
599 struct ath5k_desc *ds;
600 int ret;
fa1c114f 601
8a63facc 602 if (!skb) {
e0d687bd 603 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
8a63facc
BC		 604 if (!skb)
605 return -ENOMEM;
606 bf->skb = skb;
f769c36b
BC		 607 }
608
8a63facc
BC		 609 /*
610 * Setup descriptors. For receive we always terminate
611 * the descriptor list with a self-linked entry so we'll
612 * not get overrun under high load (as can happen with a
613 * 5212 when ANI processing enables PHY error frames).
614 *
615 * To ensure the last descriptor is self-linked we create
616 * each descriptor as self-linked and add it to the end. As
617 * each additional descriptor is added the previous self-linked
618 * entry is "fixed" naturally. This should be safe even
619 * if DMA is happening. When processing RX interrupts we
620 * never remove/process the last, self-linked, entry on the
621 * descriptor list. This ensures the hardware always has
622 * someplace to write a new frame.
623 */
624 ds = bf->desc;
625 ds->ds_link = bf->daddr; /* link to self */
626 ds->ds_data = bf->skbaddr;
627 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 628 if (ret) {
e0d687bd 629 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
8a63facc 630 return ret;
fa1c114f
JS		 631 }
632
e0d687bd
PR		 633 if (ah->rxlink != NULL)
634 *ah->rxlink = bf->daddr;
635 ah->rxlink = &ds->ds_link;
fa1c114f 636 return 0;
fa1c114f
JS		 637}
638
8a63facc 639static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 640{
8a63facc
BC		 641 struct ieee80211_hdr *hdr;
642 enum ath5k_pkt_type htype;
643 __le16 fc;
fa1c114f 644
8a63facc
BC		 645 hdr = (struct ieee80211_hdr *)skb->data;
646 fc = hdr->frame_control;
fa1c114f 647
8a63facc
BC		 648 if (ieee80211_is_beacon(fc))
649 htype = AR5K_PKT_TYPE_BEACON;
650 else if (ieee80211_is_probe_resp(fc))
651 htype = AR5K_PKT_TYPE_PROBE_RESP;
652 else if (ieee80211_is_atim(fc))
653 htype = AR5K_PKT_TYPE_ATIM;
654 else if (ieee80211_is_pspoll(fc))
655 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 656 else
8a63facc 657 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 658
8a63facc 659 return htype;
42639fcd
BC		 660}
661
8a63facc 662static int
e0d687bd 663ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
8a63facc 664 struct ath5k_txq *txq, int padsize)
fa1c114f 665{
8a63facc
BC		 666 struct ath5k_desc *ds = bf->desc;
667 struct sk_buff *skb = bf->skb;
668 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
669 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
670 struct ieee80211_rate *rate;
671 unsigned int mrr_rate[3], mrr_tries[3];
672 int i, ret;
673 u16 hw_rate;
674 u16 cts_rate = 0;
675 u16 duration = 0;
676 u8 rc_flags;
fa1c114f 677
8a63facc 678 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 679
8a63facc 680 /* XXX endianness */
e0d687bd 681 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
aeae4ac9 682 DMA_TO_DEVICE);
fa1c114f 683
e0d687bd 684 rate = ieee80211_get_tx_rate(ah->hw, info);
29ad2fac
JL		 685 if (!rate) {
686 ret = -EINVAL;
687 goto err_unmap;
688 }
fa1c114f 689
8a63facc
BC		 690 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
691 flags |= AR5K_TXDESC_NOACK;
fa1c114f 692
8a63facc
BC		 693 rc_flags = info->control.rates[0].flags;
694 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
695 rate->hw_value_short : rate->hw_value;
42639fcd 696
8a63facc
BC		 697 pktlen = skb->len;
698
699 /* FIXME: If we are in g mode and rate is a CCK rate
700 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
701 * from tx power (value is in dB units already) */
702 if (info->control.hw_key) {
703 keyidx = info->control.hw_key->hw_key_idx;
704 pktlen += info->control.hw_key->icv_len;
705 }
706 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
707 flags |= AR5K_TXDESC_RTSENA;
e0d687bd
PR		 708 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
709 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
b1ae1edf 710 info->control.vif, pktlen, info));
8a63facc
BC		 711 }
712 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
713 flags |= AR5K_TXDESC_CTSENA;
e0d687bd
PR		 714 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
715 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
b1ae1edf 716 info->control.vif, pktlen, info));
8a63facc
BC		 717 }
718 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
719 ieee80211_get_hdrlen_from_skb(skb), padsize,
720 get_hw_packet_type(skb),
e0d687bd 721 (ah->power_level * 2),
8a63facc
BC		 722 hw_rate,
723 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
724 cts_rate, duration);
725 if (ret)
726 goto err_unmap;
727
86f62d9b
NK		 728 /* Set up MRR descriptor */
729 if (ah->ah_capabilities.cap_has_mrr_support) {
730 memset(mrr_rate, 0, sizeof(mrr_rate));
731 memset(mrr_tries, 0, sizeof(mrr_tries));
732 for (i = 0; i < 3; i++) {
733 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
734 if (!rate)
735 break;
fa1c114f 736
86f62d9b
NK		 737 mrr_rate[i] = rate->hw_value;
738 mrr_tries[i] = info->control.rates[i + 1].count;
739 }
fa1c114f 740
86f62d9b
NK		 741 ath5k_hw_setup_mrr_tx_desc(ah, ds,
742 mrr_rate[0], mrr_tries[0],
743 mrr_rate[1], mrr_tries[1],
744 mrr_rate[2], mrr_tries[2]);
745 }
fa1c114f 746
8a63facc
BC		 747 ds->ds_link = 0;
748 ds->ds_data = bf->skbaddr;
63266a65 749
8a63facc
BC		 750 spin_lock_bh(&txq->lock);
751 list_add_tail(&bf->list, &txq->q);
925e0b06 752 txq->txq_len++;
8a63facc
BC		 753 if (txq->link == NULL) /* is this first packet? */
754 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
755 else /* no, so only link it */
756 *txq->link = bf->daddr;
63266a65 757
8a63facc
BC		 758 txq->link = &ds->ds_link;
759 ath5k_hw_start_tx_dma(ah, txq->qnum);
760 mmiowb();
761 spin_unlock_bh(&txq->lock);
762
763 return 0;
764err_unmap:
e0d687bd 765 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 766 return ret;
63266a65
BR		 767}
768
8a63facc
BC		 769/*******************\
770* Descriptors setup *
771\*******************/
772
d8ee398d 773static int
e0d687bd 774ath5k_desc_alloc(struct ath5k_hw *ah)
fa1c114f 775{
8a63facc
BC		 776 struct ath5k_desc *ds;
777 struct ath5k_buf *bf;
778 dma_addr_t da;
779 unsigned int i;
780 int ret;
d8ee398d 781
8a63facc 782 /* allocate descriptors */
e0d687bd 783 ah->desc_len = sizeof(struct ath5k_desc) *
8a63facc 784 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9 785
e0d687bd
PR		 786 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
787 &ah->desc_daddr, GFP_KERNEL);
788 if (ah->desc == NULL) {
789 ATH5K_ERR(ah, "can't allocate descriptors\n");
8a63facc
BC		 790 ret = -ENOMEM;
791 goto err;
792 }
e0d687bd
PR		 793 ds = ah->desc;
794 da = ah->desc_daddr;
795 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
796 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
fa1c114f 797
8a63facc
BC		 798 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
799 sizeof(struct ath5k_buf), GFP_KERNEL);
800 if (bf == NULL) {
e0d687bd 801 ATH5K_ERR(ah, "can't allocate bufptr\n");
8a63facc
BC		 802 ret = -ENOMEM;
803 goto err_free;
804 }
e0d687bd 805 ah->bufptr = bf;
fa1c114f 806
e0d687bd 807 INIT_LIST_HEAD(&ah->rxbuf);
8a63facc
BC		 808 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
809 bf->desc = ds;
810 bf->daddr = da;
e0d687bd 811 list_add_tail(&bf->list, &ah->rxbuf);
8a63facc 812 }
d8ee398d 813
e0d687bd
PR		 814 INIT_LIST_HEAD(&ah->txbuf);
815 ah->txbuf_len = ATH_TXBUF;
e4bbf2f5 816 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
8a63facc
BC		 817 bf->desc = ds;
818 bf->daddr = da;
e0d687bd 819 list_add_tail(&bf->list, &ah->txbuf);
fa1c114f
JS		 820 }
821
b1ae1edf 822 /* beacon buffers */
e0d687bd 823 INIT_LIST_HEAD(&ah->bcbuf);
b1ae1edf
BG		 824 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
825 bf->desc = ds;
826 bf->daddr = da;
e0d687bd 827 list_add_tail(&bf->list, &ah->bcbuf);
b1ae1edf 828 }
fa1c114f 829
8a63facc
BC		 830 return 0;
831err_free:
e0d687bd 832 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
8a63facc 833err:
e0d687bd 834 ah->desc = NULL;
8a63facc
BC		 835 return ret;
836}
fa1c114f 837
cd2c5486 838void
e0d687bd 839ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
cd2c5486
BR		 840{
841 BUG_ON(!bf);
842 if (!bf->skb)
843 return;
e0d687bd 844 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
cd2c5486
BR		 845 DMA_TO_DEVICE);
846 dev_kfree_skb_any(bf->skb);
847 bf->skb = NULL;
848 bf->skbaddr = 0;
849 bf->desc->ds_data = 0;
850}
851
852void
e0d687bd 853ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
cd2c5486 854{
cd2c5486
BR		 855 struct ath_common *common = ath5k_hw_common(ah);
856
857 BUG_ON(!bf);
858 if (!bf->skb)
859 return;
e0d687bd 860 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
cd2c5486
BR		 861 DMA_FROM_DEVICE);
862 dev_kfree_skb_any(bf->skb);
863 bf->skb = NULL;
864 bf->skbaddr = 0;
865 bf->desc->ds_data = 0;
866}
867
8a63facc 868static void
e0d687bd 869ath5k_desc_free(struct ath5k_hw *ah)
8a63facc
BC		 870{
871 struct ath5k_buf *bf;
d8ee398d 872
e0d687bd
PR		 873 list_for_each_entry(bf, &ah->txbuf, list)
874 ath5k_txbuf_free_skb(ah, bf);
875 list_for_each_entry(bf, &ah->rxbuf, list)
876 ath5k_rxbuf_free_skb(ah, bf);
877 list_for_each_entry(bf, &ah->bcbuf, list)
878 ath5k_txbuf_free_skb(ah, bf);
d8ee398d 879
8a63facc 880 /* Free memory associated with all descriptors */
e0d687bd
PR		 881 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
882 ah->desc = NULL;
883 ah->desc_daddr = 0;
d8ee398d 884
e0d687bd
PR		 885 kfree(ah->bufptr);
886 ah->bufptr = NULL;
fa1c114f
JS		 887}
888
8a63facc
BC		 889
890/**************\
891* Queues setup *
892\**************/
893
894static struct ath5k_txq *
e0d687bd 895ath5k_txq_setup(struct ath5k_hw *ah,
8a63facc 896 int qtype, int subtype)
fa1c114f 897{
8a63facc
BC		 898 struct ath5k_txq *txq;
899 struct ath5k_txq_info qi = {
900 .tqi_subtype = subtype,
de8af455
BR		 901 /* XXX: default values not correct for B and XR channels,
902 * but who cares? */
903 .tqi_aifs = AR5K_TUNE_AIFS,
904 .tqi_cw_min = AR5K_TUNE_CWMIN,
905 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 906 };
907 int qnum;
d8ee398d 908
e30eb4ab 909 /*
8a63facc
BC		 910 * Enable interrupts only for EOL and DESC conditions.
911 * We mark tx descriptors to receive a DESC interrupt
912 * when a tx queue gets deep; otherwise we wait for the
913 * EOL to reap descriptors. Note that this is done to
914 * reduce interrupt load and this only defers reaping
915 * descriptors, never transmitting frames. Aside from
916 * reducing interrupts this also permits more concurrency.
917 * The only potential downside is if the tx queue backs
918 * up in which case the top half of the kernel may backup
919 * due to a lack of tx descriptors.
e30eb4ab 920 */
8a63facc
BC		 921 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
922 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
923 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
924 if (qnum < 0) {
925 /*
926 * NB: don't print a message, this happens
927 * normally on parts with too few tx queues
928 */
929 return ERR_PTR(qnum);
930 }
e0d687bd 931 txq = &ah->txqs[qnum];
8a63facc
BC		 932 if (!txq->setup) {
933 txq->qnum = qnum;
934 txq->link = NULL;
935 INIT_LIST_HEAD(&txq->q);
936 spin_lock_init(&txq->lock);
937 txq->setup = true;
925e0b06 938 txq->txq_len = 0;
81266baf 939 txq->txq_max = ATH5K_TXQ_LEN_MAX;
4edd761f 940 txq->txq_poll_mark = false;
923e5b3d 941 txq->txq_stuck = 0;
8a63facc 942 }
e0d687bd 943 return &ah->txqs[qnum];
fa1c114f
JS		 944}
945
8a63facc
BC		 946static int
947ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 948{
8a63facc 949 struct ath5k_txq_info qi = {
de8af455
BR		 950 /* XXX: default values not correct for B and XR channels,
951 * but who cares? */
952 .tqi_aifs = AR5K_TUNE_AIFS,
953 .tqi_cw_min = AR5K_TUNE_CWMIN,
954 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 955 /* NB: for dynamic turbo, don't enable any other interrupts */
956 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
957 };
d8ee398d 958
8a63facc 959 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 960}
961
8a63facc 962static int
e0d687bd 963ath5k_beaconq_config(struct ath5k_hw *ah)
fa1c114f 964{
8a63facc
BC		 965 struct ath5k_txq_info qi;
966 int ret;
fa1c114f 967
e0d687bd 968 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
8a63facc
BC		 969 if (ret)
970 goto err;
fa1c114f 971
e0d687bd
PR		 972 if (ah->opmode == NL80211_IFTYPE_AP ||
973 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
8a63facc
BC		 974 /*
975 * Always burst out beacon and CAB traffic
976 * (aifs = cwmin = cwmax = 0)
977 */
978 qi.tqi_aifs = 0;
979 qi.tqi_cw_min = 0;
980 qi.tqi_cw_max = 0;
e0d687bd 981 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
8a63facc
BC		 982 /*
983 * Adhoc mode; backoff between 0 and (2 * cw_min).
984 */
985 qi.tqi_aifs = 0;
986 qi.tqi_cw_min = 0;
de8af455 987 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 988 }
fa1c114f 989
e0d687bd 990 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 991 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
992 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 993
e0d687bd 994 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
8a63facc 995 if (ret) {
e0d687bd 996 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
8a63facc
BC		 997 "hardware queue!\n", __func__);
998 goto err;
999 }
e0d687bd 1000 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
8a63facc
BC		 1001 if (ret)
1002 goto err;
b7266047 1003
8a63facc
BC		 1004 /* reconfigure cabq with ready time to 80% of beacon_interval */
1005 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1006 if (ret)
1007 goto err;
b7266047 1008
e0d687bd 1009 qi.tqi_ready_time = (ah->bintval * 80) / 100;
8a63facc
BC		 1010 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1011 if (ret)
1012 goto err;
b7266047 1013
8a63facc
BC		 1014 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1015err:
1016 return ret;
d8ee398d
LR		 1017}
1018
80dac9ee
NK		 1019/**
1020 * ath5k_drain_tx_buffs - Empty tx buffers
1021 *
e0d687bd 1022 * @ah The &struct ath5k_hw
80dac9ee
NK		 1023 *
1024 * Empty tx buffers from all queues in preparation
1025 * of a reset or during shutdown.
1026 *
1027 * NB: this assumes output has been stopped and
1028 * we do not need to block ath5k_tx_tasklet
1029 */
8a63facc 1030static void
e0d687bd 1031ath5k_drain_tx_buffs(struct ath5k_hw *ah)
8a63facc 1032{
80dac9ee 1033 struct ath5k_txq *txq;
8a63facc 1034 struct ath5k_buf *bf, *bf0;
80dac9ee 1035 int i;
b6ea0356 1036
e0d687bd
PR		 1037 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1038 if (ah->txqs[i].setup) {
1039 txq = &ah->txqs[i];
80dac9ee
NK		 1040 spin_lock_bh(&txq->lock);
1041 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
e0d687bd 1042 ath5k_debug_printtxbuf(ah, bf);
b6ea0356 1043
e0d687bd 1044 ath5k_txbuf_free_skb(ah, bf);
fa1c114f 1045
e0d687bd
PR		 1046 spin_lock_bh(&ah->txbuflock);
1047 list_move_tail(&bf->list, &ah->txbuf);
1048 ah->txbuf_len++;
80dac9ee 1049 txq->txq_len--;
e0d687bd 1050 spin_unlock_bh(&ah->txbuflock);
8a63facc 1051 }
80dac9ee
NK		 1052 txq->link = NULL;
1053 txq->txq_poll_mark = false;
1054 spin_unlock_bh(&txq->lock);
1055 }
0452d4a5 1056 }
fa1c114f
JS		 1057}
1058
8a63facc 1059static void
e0d687bd 1060ath5k_txq_release(struct ath5k_hw *ah)
2ac2927a 1061{
e0d687bd 1062 struct ath5k_txq *txq = ah->txqs;
8a63facc 1063 unsigned int i;
2ac2927a 1064
e0d687bd 1065 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
8a63facc 1066 if (txq->setup) {
e0d687bd 1067 ath5k_hw_release_tx_queue(ah, txq->qnum);
8a63facc
BC		 1068 txq->setup = false;
1069 }
1070}
2ac2927a 1071
2ac2927a 1072
8a63facc
BC		 1073/*************\
1074* RX Handling *
1075\*************/
2ac2927a 1076
8a63facc
BC		 1077/*
1078 * Enable the receive h/w following a reset.
1079 */
fa1c114f 1080static int
e0d687bd 1081ath5k_rx_start(struct ath5k_hw *ah)
fa1c114f 1082{
8a63facc
BC		 1083 struct ath_common *common = ath5k_hw_common(ah);
1084 struct ath5k_buf *bf;
1085 int ret;
fa1c114f 1086
8a63facc 1087 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1088
e0d687bd 1089 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
8a63facc 1090 common->cachelsz, common->rx_bufsize);
2f7fe870 1091
e0d687bd
PR		 1092 spin_lock_bh(&ah->rxbuflock);
1093 ah->rxlink = NULL;
1094 list_for_each_entry(bf, &ah->rxbuf, list) {
1095 ret = ath5k_rxbuf_setup(ah, bf);
8a63facc 1096 if (ret != 0) {
e0d687bd 1097 spin_unlock_bh(&ah->rxbuflock);
8a63facc
BC		 1098 goto err;
1099 }
2f7fe870 1100 }
e0d687bd 1101 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
8a63facc 1102 ath5k_hw_set_rxdp(ah, bf->daddr);
e0d687bd 1103 spin_unlock_bh(&ah->rxbuflock);
2f7fe870 1104
8a63facc 1105 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
e0d687bd 1106 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
8a63facc 1107 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1108
1109 return 0;
8a63facc 1110err:
fa1c114f
JS		 1111 return ret;
1112}
1113
8a63facc 1114/*
80dac9ee
NK		 1115 * Disable the receive logic on PCU (DRU)
1116 * In preparation for a shutdown.
1117 *
1118 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1119 * does.
8a63facc
BC		 1120 */
1121static void
e0d687bd 1122ath5k_rx_stop(struct ath5k_hw *ah)
fa1c114f 1123{
fa1c114f 1124
8a63facc 1125 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1126 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1127
e0d687bd 1128 ath5k_debug_printrxbuffs(ah);
8a63facc 1129}
fa1c114f 1130
8a63facc 1131static unsigned int
e0d687bd 1132ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc
BC		 1133 struct ath5k_rx_status *rs)
1134{
8a63facc
BC		 1135 struct ath_common *common = ath5k_hw_common(ah);
1136 struct ieee80211_hdr *hdr = (void *)skb->data;
1137 unsigned int keyix, hlen;
fa1c114f 1138
8a63facc
BC		 1139 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1140 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1141 return RX_FLAG_DECRYPTED;
fa1c114f 1142
8a63facc
BC		 1143 /* Apparently when a default key is used to decrypt the packet
1144 the hw does not set the index used to decrypt. In such cases
1145 get the index from the packet. */
1146 hlen = ieee80211_hdrlen(hdr->frame_control);
1147 if (ieee80211_has_protected(hdr->frame_control) &&
1148 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1149 skb->len >= hlen + 4) {
1150 keyix = skb->data[hlen + 3] >> 6;
1151
1152 if (test_bit(keyix, common->keymap))
1153 return RX_FLAG_DECRYPTED;
1154 }
fa1c114f
JS		 1155
1156 return 0;
fa1c114f
JS		 1157}
1158
8a63facc 1159
fa1c114f 1160static void
e0d687bd 1161ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc 1162 struct ieee80211_rx_status *rxs)
fa1c114f 1163{
e0d687bd 1164 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1165 u64 tsf, bc_tstamp;
1166 u32 hw_tu;
1167 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1168
8a63facc
BC		 1169 if (ieee80211_is_beacon(mgmt->frame_control) &&
1170 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1171 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1172 /*
1173 * Received an IBSS beacon with the same BSSID. Hardware *must*
1174 * have updated the local TSF. We have to work around various
1175 * hardware bugs, though...
1176 */
e0d687bd 1177 tsf = ath5k_hw_get_tsf64(ah);
8a63facc
BC		 1178 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1179 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1180
e0d687bd 1181 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1182 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1183 (unsigned long long)bc_tstamp,
1184 (unsigned long long)rxs->mactime,
1185 (unsigned long long)(rxs->mactime - bc_tstamp),
1186 (unsigned long long)tsf);
fa1c114f 1187
8a63facc
BC		 1188 /*
1189 * Sometimes the HW will give us a wrong tstamp in the rx
1190 * status, causing the timestamp extension to go wrong.
1191 * (This seems to happen especially with beacon frames bigger
1192 * than 78 byte (incl. FCS))
1193 * But we know that the receive timestamp must be later than the
1194 * timestamp of the beacon since HW must have synced to that.
1195 *
1196 * NOTE: here we assume mactime to be after the frame was
1197 * received, not like mac80211 which defines it at the start.
1198 */
1199 if (bc_tstamp > rxs->mactime) {
e0d687bd 1200 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1201 "fixing mactime from %llx to %llx\n",
1202 (unsigned long long)rxs->mactime,
1203 (unsigned long long)tsf);
1204 rxs->mactime = tsf;
1205 }
fa1c114f 1206
8a63facc
BC		 1207 /*
1208 * Local TSF might have moved higher than our beacon timers,
1209 * in that case we have to update them to continue sending
1210 * beacons. This also takes care of synchronizing beacon sending
1211 * times with other stations.
1212 */
e0d687bd
PR		 1213 if (hw_tu >= ah->nexttbtt)
1214 ath5k_beacon_update_timers(ah, bc_tstamp);
7f896126
BR		 1215
1216 /* Check if the beacon timers are still correct, because a TSF
1217 * update might have created a window between them - for a
1218 * longer description see the comment of this function: */
e0d687bd
PR		 1219 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1220 ath5k_beacon_update_timers(ah, bc_tstamp);
1221 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
7f896126
BR		 1222 "fixed beacon timers after beacon receive\n");
1223 }
8a63facc
BC		 1224 }
1225}
fa1c114f 1226
8a63facc 1227static void
e0d687bd 1228ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
8a63facc
BC		 1229{
1230 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
8a63facc 1231 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1232
8a63facc
BC		 1233 /* only beacons from our BSSID */
1234 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1235 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1236 return;
fa1c114f 1237
eef39bef 1238 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1239
8a63facc
BC		 1240 /* in IBSS mode we should keep RSSI statistics per neighbour */
1241 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1242}
fa1c114f 1243
8a63facc
BC		 1244/*
1245 * Compute padding position. skb must contain an IEEE 802.11 frame
1246 */
1247static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1248{
e4bbf2f5 1249 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8a63facc
BC		 1250 __le16 frame_control = hdr->frame_control;
1251 int padpos = 24;
fa1c114f 1252
d2c7f773 1253 if (ieee80211_has_a4(frame_control))
8a63facc 1254 padpos += ETH_ALEN;
d2c7f773
PR		 1255
1256 if (ieee80211_is_data_qos(frame_control))
8a63facc 1257 padpos += IEEE80211_QOS_CTL_LEN;
8a63facc
BC		 1258
1259 return padpos;
fa1c114f
JS		 1260}
1261
8a63facc
BC		 1262/*
1263 * This function expects an 802.11 frame and returns the number of
1264 * bytes added, or -1 if we don't have enough header room.
1265 */
1266static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1267{
8a63facc
BC		 1268 int padpos = ath5k_common_padpos(skb);
1269 int padsize = padpos & 3;
fa1c114f 1270
e4bbf2f5 1271 if (padsize && skb->len > padpos) {
fa1c114f 1272
8a63facc
BC		 1273 if (skb_headroom(skb) < padsize)
1274 return -1;
fa1c114f 1275
8a63facc 1276 skb_push(skb, padsize);
e4bbf2f5 1277 memmove(skb->data, skb->data + padsize, padpos);
8a63facc
BC		 1278 return padsize;
1279 }
a951ae21 1280
8a63facc
BC		 1281 return 0;
1282}
fa1c114f 1283
8a63facc
BC		 1284/*
1285 * The MAC header is padded to have 32-bit boundary if the
1286 * packet payload is non-zero. The general calculation for
1287 * padsize would take into account odd header lengths:
1288 * padsize = 4 - (hdrlen & 3); however, since only
1289 * even-length headers are used, padding can only be 0 or 2
1290 * bytes and we can optimize this a bit. We must not try to
1291 * remove padding from short control frames that do not have a
1292 * payload.
1293 *
1294 * This function expects an 802.11 frame and returns the number of
1295 * bytes removed.
1296 */
1297static int ath5k_remove_padding(struct sk_buff *skb)
1298{
1299 int padpos = ath5k_common_padpos(skb);
1300 int padsize = padpos & 3;
6d91e1d8 1301
e4bbf2f5 1302 if (padsize && skb->len >= padpos + padsize) {
8a63facc
BC		 1303 memmove(skb->data + padsize, skb->data, padpos);
1304 skb_pull(skb, padsize);
1305 return padsize;
fa1c114f 1306 }
a951ae21 1307
8a63facc 1308 return 0;
fa1c114f
JS		 1309}
1310
1311static void
e0d687bd 1312ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc 1313 struct ath5k_rx_status *rs)
fa1c114f 1314{
8a63facc
BC		 1315 struct ieee80211_rx_status *rxs;
1316
1317 ath5k_remove_padding(skb);
1318
1319 rxs = IEEE80211_SKB_RXCB(skb);
1320
1321 rxs->flag = 0;
1322 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1323 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1324
1325 /*
8a63facc
BC		 1326 * always extend the mac timestamp, since this information is
1327 * also needed for proper IBSS merging.
1328 *
1329 * XXX: it might be too late to do it here, since rs_tstamp is
1330 * 15bit only. that means TSF extension has to be done within
1331 * 32768usec (about 32ms). it might be necessary to move this to
1332 * the interrupt handler, like it is done in madwifi.
1333 *
1334 * Unfortunately we don't know when the hardware takes the rx
1335 * timestamp (beginning of phy frame, data frame, end of rx?).
1336 * The only thing we know is that it is hardware specific...
1337 * On AR5213 it seems the rx timestamp is at the end of the
6a2a0e73 1338 * frame, but I'm not sure.
8a63facc
BC		 1339 *
1340 * NOTE: mac80211 defines mactime at the beginning of the first
1341 * data symbol. Since we don't have any time references it's
1342 * impossible to comply to that. This affects IBSS merge only
1343 * right now, so it's not too bad...
fa1c114f 1344 */
e0d687bd 1345 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
6ebacbb7 1346 rxs->flag |= RX_FLAG_MACTIME_MPDU;
fa1c114f 1347
e0d687bd
PR		 1348 rxs->freq = ah->curchan->center_freq;
1349 rxs->band = ah->curchan->band;
fa1c114f 1350
e0d687bd 1351 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1352
8a63facc 1353 rxs->antenna = rs->rs_antenna;
fa1c114f 1354
8a63facc 1355 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
e0d687bd 1356 ah->stats.antenna_rx[rs->rs_antenna]++;
8a63facc 1357 else
e0d687bd 1358 ah->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1359
e0d687bd
PR		 1360 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1361 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
fa1c114f 1362
8a63facc 1363 if (rxs->rate_idx >= 0 && rs->rs_rate ==
e0d687bd 1364 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1365 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1366
e0d687bd 1367 trace_ath5k_rx(ah, skb);
fa1c114f 1368
e0d687bd 1369 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
fa1c114f 1370
8a63facc 1371 /* check beacons in IBSS mode */
e0d687bd
PR		 1372 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1373 ath5k_check_ibss_tsf(ah, skb, rxs);
fa1c114f 1374
e0d687bd 1375 ieee80211_rx(ah->hw, skb);
8a63facc 1376}
fa1c114f 1377
8a63facc
BC		 1378/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1379 *
1380 * Check if we want to further process this frame or not. Also update
1381 * statistics. Return true if we want this frame, false if not.
fa1c114f 1382 */
8a63facc 1383static bool
e0d687bd 1384ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
fa1c114f 1385{
e0d687bd
PR		 1386 ah->stats.rx_all_count++;
1387 ah->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1388
8a63facc
BC		 1389 if (unlikely(rs->rs_status)) {
1390 if (rs->rs_status & AR5K_RXERR_CRC)
e0d687bd 1391 ah->stats.rxerr_crc++;
8a63facc 1392 if (rs->rs_status & AR5K_RXERR_FIFO)
e0d687bd 1393 ah->stats.rxerr_fifo++;
8a63facc 1394 if (rs->rs_status & AR5K_RXERR_PHY) {
e0d687bd 1395 ah->stats.rxerr_phy++;
8a63facc 1396 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
e0d687bd 1397 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
8a63facc
BC		 1398 return false;
1399 }
1400 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1401 /*
1402 * Decrypt error. If the error occurred
1403 * because there was no hardware key, then
1404 * let the frame through so the upper layers
1405 * can process it. This is necessary for 5210
1406 * parts which have no way to setup a ``clear''
1407 * key cache entry.
1408 *
1409 * XXX do key cache faulting
1410 */
e0d687bd 1411 ah->stats.rxerr_decrypt++;
8a63facc
BC		 1412 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1413 !(rs->rs_status & AR5K_RXERR_CRC))
1414 return true;
1415 }
1416 if (rs->rs_status & AR5K_RXERR_MIC) {
e0d687bd 1417 ah->stats.rxerr_mic++;
8a63facc 1418 return true;
fa1c114f 1419 }
fa1c114f 1420
8a63facc
BC		 1421 /* reject any frames with non-crypto errors */
1422 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1423 return false;
1424 }
fa1c114f 1425
8a63facc 1426 if (unlikely(rs->rs_more)) {
e0d687bd 1427 ah->stats.rxerr_jumbo++;
8a63facc
BC		 1428 return false;
1429 }
1430 return true;
fa1c114f
JS		 1431}
1432
c266c71a 1433static void
e0d687bd 1434ath5k_set_current_imask(struct ath5k_hw *ah)
c266c71a 1435{
4fc5401c 1436 enum ath5k_int imask;
c266c71a
FF		 1437 unsigned long flags;
1438
e0d687bd
PR		 1439 spin_lock_irqsave(&ah->irqlock, flags);
1440 imask = ah->imask;
1441 if (ah->rx_pending)
c266c71a 1442 imask &= ~AR5K_INT_RX_ALL;
e0d687bd 1443 if (ah->tx_pending)
c266c71a 1444 imask &= ~AR5K_INT_TX_ALL;
e0d687bd
PR		 1445 ath5k_hw_set_imr(ah, imask);
1446 spin_unlock_irqrestore(&ah->irqlock, flags);
c266c71a
FF		 1447}
1448
fa1c114f 1449static void
8a63facc 1450ath5k_tasklet_rx(unsigned long data)
fa1c114f 1451{
8a63facc
BC		 1452 struct ath5k_rx_status rs = {};
1453 struct sk_buff *skb, *next_skb;
1454 dma_addr_t next_skb_addr;
e0d687bd 1455 struct ath5k_hw *ah = (void *)data;
dc1e001b 1456 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1457 struct ath5k_buf *bf;
1458 struct ath5k_desc *ds;
1459 int ret;
fa1c114f 1460
e0d687bd
PR		 1461 spin_lock(&ah->rxbuflock);
1462 if (list_empty(&ah->rxbuf)) {
1463 ATH5K_WARN(ah, "empty rx buf pool\n");
8a63facc
BC		 1464 goto unlock;
1465 }
1466 do {
e0d687bd 1467 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
8a63facc
BC		 1468 BUG_ON(bf->skb == NULL);
1469 skb = bf->skb;
1470 ds = bf->desc;
fa1c114f 1471
8a63facc 1472 /* bail if HW is still using self-linked descriptor */
e0d687bd 1473 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
8a63facc 1474 break;
fa1c114f 1475
e0d687bd 1476 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
8a63facc
BC		 1477 if (unlikely(ret == -EINPROGRESS))
1478 break;
1479 else if (unlikely(ret)) {
e0d687bd
PR		 1480 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1481 ah->stats.rxerr_proc++;
8a63facc
BC		 1482 break;
1483 }
fa1c114f 1484
e0d687bd
PR		 1485 if (ath5k_receive_frame_ok(ah, &rs)) {
1486 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
fa1c114f 1487
8a63facc
BC		 1488 /*
1489 * If we can't replace bf->skb with a new skb under
1490 * memory pressure, just skip this packet
1491 */
1492 if (!next_skb)
1493 goto next;
036cd1ec 1494
e0d687bd 1495 dma_unmap_single(ah->dev, bf->skbaddr,
8a63facc 1496 common->rx_bufsize,
aeae4ac9 1497 DMA_FROM_DEVICE);
036cd1ec 1498
8a63facc 1499 skb_put(skb, rs.rs_datalen);
6ba81c2c 1500
e0d687bd 1501 ath5k_receive_frame(ah, skb, &rs);
6ba81c2c 1502
8a63facc
BC		 1503 bf->skb = next_skb;
1504 bf->skbaddr = next_skb_addr;
036cd1ec 1505 }
8a63facc 1506next:
e0d687bd
PR		 1507 list_move_tail(&bf->list, &ah->rxbuf);
1508 } while (ath5k_rxbuf_setup(ah, bf) == 0);
8a63facc 1509unlock:
e0d687bd
PR		 1510 spin_unlock(&ah->rxbuflock);
1511 ah->rx_pending = false;
1512 ath5k_set_current_imask(ah);
036cd1ec
BR		 1513}
1514
b4ea449d 1515
8a63facc
BC		 1516/*************\
1517* TX Handling *
1518\*************/
b4ea449d 1519
7bb45683 1520void
cd2c5486
BR		 1521ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1522 struct ath5k_txq *txq)
8a63facc 1523{
e0d687bd 1524 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 1525 struct ath5k_buf *bf;
1526 unsigned long flags;
1527 int padsize;
b4ea449d 1528
e0d687bd 1529 trace_ath5k_tx(ah, skb, txq);
b4ea449d 1530
8a63facc
BC		 1531 /*
1532 * The hardware expects the header padded to 4 byte boundaries.
1533 * If this is not the case, we add the padding after the header.
1534 */
1535 padsize = ath5k_add_padding(skb);
1536 if (padsize < 0) {
e0d687bd 1537 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
8a63facc
BC		 1538 " headroom to pad");
1539 goto drop_packet;
1540 }
8127fbdc 1541
4e868796
FF		 1542 if (txq->txq_len >= txq->txq_max &&
1543 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
925e0b06
BR		 1544 ieee80211_stop_queue(hw, txq->qnum);
1545
e0d687bd
PR		 1546 spin_lock_irqsave(&ah->txbuflock, flags);
1547 if (list_empty(&ah->txbuf)) {
1548 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1549 spin_unlock_irqrestore(&ah->txbuflock, flags);
651d9375 1550 ieee80211_stop_queues(hw);
8a63facc 1551 goto drop_packet;
8127fbdc 1552 }
e0d687bd 1553 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
8a63facc 1554 list_del(&bf->list);
e0d687bd
PR		 1555 ah->txbuf_len--;
1556 if (list_empty(&ah->txbuf))
8a63facc 1557 ieee80211_stop_queues(hw);
e0d687bd 1558 spin_unlock_irqrestore(&ah->txbuflock, flags);
8a63facc
BC		 1559
1560 bf->skb = skb;
1561
e0d687bd 1562 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
8a63facc 1563 bf->skb = NULL;
e0d687bd
PR		 1564 spin_lock_irqsave(&ah->txbuflock, flags);
1565 list_add_tail(&bf->list, &ah->txbuf);
1566 ah->txbuf_len++;
1567 spin_unlock_irqrestore(&ah->txbuflock, flags);
8a63facc 1568 goto drop_packet;
8127fbdc 1569 }
7bb45683 1570 return;
8127fbdc 1571
8a63facc
BC		 1572drop_packet:
1573 dev_kfree_skb_any(skb);
8127fbdc
BP		 1574}
1575
1440401e 1576static void
e0d687bd 1577ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
0e472252 1578 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1440401e
BR		 1579{
1580 struct ieee80211_tx_info *info;
ed895085 1581 u8 tries[3];
1440401e
BR		 1582 int i;
1583
e0d687bd
PR		 1584 ah->stats.tx_all_count++;
1585 ah->stats.tx_bytes_count += skb->len;
1440401e
BR		 1586 info = IEEE80211_SKB_CB(skb);
1587
ed895085
FF		 1588 tries[0] = info->status.rates[0].count;
1589 tries[1] = info->status.rates[1].count;
1590 tries[2] = info->status.rates[2].count;
1591
1440401e 1592 ieee80211_tx_info_clear_status(info);
ed895085
FF		 1593
1594 for (i = 0; i < ts->ts_final_idx; i++) {
1440401e
BR		 1595 struct ieee80211_tx_rate *r =
1596 &info->status.rates[i];
1597
ed895085 1598 r->count = tries[i];
1440401e
BR		 1599 }
1600
ed895085 1601 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
6d7b97b2 1602 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1440401e
BR		 1603
1604 if (unlikely(ts->ts_status)) {
e0d687bd 1605 ah->stats.ack_fail++;
1440401e
BR		 1606 if (ts->ts_status & AR5K_TXERR_FILT) {
1607 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
e0d687bd 1608 ah->stats.txerr_filt++;
1440401e
BR		 1609 }
1610 if (ts->ts_status & AR5K_TXERR_XRETRY)
e0d687bd 1611 ah->stats.txerr_retry++;
1440401e 1612 if (ts->ts_status & AR5K_TXERR_FIFO)
e0d687bd 1613 ah->stats.txerr_fifo++;
1440401e
BR		 1614 } else {
1615 info->flags |= IEEE80211_TX_STAT_ACK;
1616 info->status.ack_signal = ts->ts_rssi;
6d7b97b2
FF		 1617
1618 /* count the successful attempt as well */
1619 info->status.rates[ts->ts_final_idx].count++;
1440401e
BR		 1620 }
1621
1622 /*
1623 * Remove MAC header padding before giving the frame
1624 * back to mac80211.
1625 */
1626 ath5k_remove_padding(skb);
1627
1628 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
e0d687bd 1629 ah->stats.antenna_tx[ts->ts_antenna]++;
1440401e 1630 else
e0d687bd 1631 ah->stats.antenna_tx[0]++; /* invalid */
1440401e 1632
e0d687bd
PR		 1633 trace_ath5k_tx_complete(ah, skb, txq, ts);
1634 ieee80211_tx_status(ah->hw, skb);
1440401e 1635}
8a63facc
BC		 1636
1637static void
e0d687bd 1638ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
8127fbdc 1639{
8a63facc
BC		 1640 struct ath5k_tx_status ts = {};
1641 struct ath5k_buf *bf, *bf0;
1642 struct ath5k_desc *ds;
1643 struct sk_buff *skb;
1440401e 1644 int ret;
8127fbdc 1645
8a63facc
BC		 1646 spin_lock(&txq->lock);
1647 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1648
1649 txq->txq_poll_mark = false;
1650
1651 /* skb might already have been processed last time. */
1652 if (bf->skb != NULL) {
1653 ds = bf->desc;
1654
e0d687bd 1655 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
23413296
BR		 1656 if (unlikely(ret == -EINPROGRESS))
1657 break;
1658 else if (unlikely(ret)) {
e0d687bd 1659 ATH5K_ERR(ah,
23413296
BR		 1660 "error %d while processing "
1661 "queue %u\n", ret, txq->qnum);
1662 break;
1663 }
1664
1665 skb = bf->skb;
1666 bf->skb = NULL;
aeae4ac9 1667
e0d687bd 1668 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
aeae4ac9 1669 DMA_TO_DEVICE);
e0d687bd 1670 ath5k_tx_frame_completed(ah, skb, txq, &ts);
23413296 1671 }
8127fbdc 1672
8a63facc
BC		 1673 /*
1674 * It's possible that the hardware can say the buffer is
1675 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1676 * host memory and moved on.
1677 * Always keep the last descriptor to avoid HW races...
8a63facc 1678 */
e0d687bd
PR		 1679 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1680 spin_lock(&ah->txbuflock);
1681 list_move_tail(&bf->list, &ah->txbuf);
1682 ah->txbuf_len++;
23413296 1683 txq->txq_len--;
e0d687bd 1684 spin_unlock(&ah->txbuflock);
8a63facc 1685 }
fa1c114f 1686 }
fa1c114f 1687 spin_unlock(&txq->lock);
4198a8d0 1688 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
e0d687bd 1689 ieee80211_wake_queue(ah->hw, txq->qnum);
fa1c114f
JS		 1690}
1691
1692static void
1693ath5k_tasklet_tx(unsigned long data)
1694{
8784d2ee 1695 int i;
e0d687bd 1696 struct ath5k_hw *ah = (void *)data;
fa1c114f 1697
e4bbf2f5 1698 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
7ff7c82e 1699 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
e0d687bd 1700 ath5k_tx_processq(ah, &ah->txqs[i]);
c266c71a 1701
e0d687bd
PR		 1702 ah->tx_pending = false;
1703 ath5k_set_current_imask(ah);
fa1c114f
JS		 1704}
1705
1706
fa1c114f
JS		 1707/*****************\
1708* Beacon handling *
1709\*****************/
1710
1711/*
1712 * Setup the beacon frame for transmit.
1713 */
1714static int
e0d687bd 1715ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
fa1c114f
JS		 1716{
1717 struct sk_buff *skb = bf->skb;
a888d52d 1718 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1719 struct ath5k_desc *ds;
2bed03eb
NK		 1720 int ret = 0;
1721 u8 antenna;
fa1c114f 1722 u32 flags;
8127fbdc 1723 const int padsize = 0;
fa1c114f 1724
e0d687bd 1725 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
aeae4ac9 1726 DMA_TO_DEVICE);
e0d687bd 1727 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
fa1c114f
JS		 1728 "skbaddr %llx\n", skb, skb->data, skb->len,
1729 (unsigned long long)bf->skbaddr);
aeae4ac9 1730
e0d687bd
PR		 1731 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1732 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
bdc71bc5
BC		 1733 dev_kfree_skb_any(skb);
1734 bf->skb = NULL;
fa1c114f
JS		 1735 return -EIO;
1736 }
1737
1738 ds = bf->desc;
2bed03eb 1739 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1740
1741 flags = AR5K_TXDESC_NOACK;
e0d687bd 1742 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1743 ds->ds_link = bf->daddr; /* self-linked */
1744 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1745 } else
fa1c114f 1746 ds->ds_link = 0;
2bed03eb
NK		 1747
1748 /*
1749 * If we use multiple antennas on AP and use
1750 * the Sectored AP scenario, switch antenna every
1751 * 4 beacons to make sure everybody hears our AP.
1752 * When a client tries to associate, hw will keep
1753 * track of the tx antenna to be used for this client
6a2a0e73 1754 * automatically, based on ACKed packets.
2bed03eb
NK		 1755 *
1756 * Note: AP still listens and transmits RTS on the
1757 * default antenna which is supposed to be an omni.
1758 *
1759 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1760 * multiple antennas (1 omni -- the default -- and 14
1761 * sectors), so if we choose to actually support this
1762 * mode, we need to allow the user to set how many antennas
1763 * we have and tweak the code below to send beacons
1764 * on all of them.
2bed03eb
NK		 1765 */
1766 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
e0d687bd 1767 antenna = ah->bsent & 4 ? 2 : 1;
2bed03eb 1768
fa1c114f 1769
8f655dde
NK		 1770 /* FIXME: If we are in g mode and rate is a CCK rate
1771 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1772 * from tx power (value is in dB units already) */
fa1c114f 1773 ds->ds_data = bf->skbaddr;
281c56dd 1774 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1775 ieee80211_get_hdrlen_from_skb(skb), padsize,
e0d687bd
PR		 1776 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
1777 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
2e92e6f2 1778 1, AR5K_TXKEYIX_INVALID,
400ec45a 1779 antenna, flags, 0, 0);
fa1c114f
JS		 1780 if (ret)
1781 goto err_unmap;
1782
1783 return 0;
1784err_unmap:
e0d687bd 1785 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1786 return ret;
1787}
1788
8a63facc
BC		 1789/*
1790 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1791 * this is called only once at config_bss time, for AP we do it every
1792 * SWBA interrupt so that the TIM will reflect buffered frames.
1793 *
1794 * Called with the beacon lock.
1795 */
cd2c5486 1796int
8a63facc
BC		 1797ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1798{
1799 int ret;
e0d687bd 1800 struct ath5k_hw *ah = hw->priv;
b1ae1edf 1801 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1802 struct sk_buff *skb;
1803
1804 if (WARN_ON(!vif)) {
1805 ret = -EINVAL;
1806 goto out;
1807 }
1808
1809 skb = ieee80211_beacon_get(hw, vif);
1810
1811 if (!skb) {
1812 ret = -ENOMEM;
1813 goto out;
1814 }
1815
e0d687bd 1816 ath5k_txbuf_free_skb(ah, avf->bbuf);
b1ae1edf 1817 avf->bbuf->skb = skb;
e0d687bd 1818 ret = ath5k_beacon_setup(ah, avf->bbuf);
8a63facc
BC		 1819out:
1820 return ret;
1821}
1822
fa1c114f
JS		 1823/*
1824 * Transmit a beacon frame at SWBA. Dynamic updates to the
1825 * frame contents are done as needed and the slot time is
1826 * also adjusted based on current state.
1827 *
5faaff74
BC		 1828 * This is called from software irq context (beacontq tasklets)
1829 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1830 */
1831static void
e0d687bd 1832ath5k_beacon_send(struct ath5k_hw *ah)
fa1c114f 1833{
b1ae1edf
BG		 1834 struct ieee80211_vif *vif;
1835 struct ath5k_vif *avf;
1836 struct ath5k_buf *bf;
cec8db23 1837 struct sk_buff *skb;
bdc71bc5 1838 int err;
fa1c114f 1839
e0d687bd 1840 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1841
fa1c114f
JS		 1842 /*
1843 * Check if the previous beacon has gone out. If
a180a130 1844 * not, don't don't try to post another: skip this
fa1c114f
JS		 1845 * period and wait for the next. Missed beacons
1846 * indicate a problem and should not occur. If we
1847 * miss too many consecutive beacons reset the device.
1848 */
e0d687bd
PR		 1849 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1850 ah->bmisscount++;
1851 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1852 "missed %u consecutive beacons\n", ah->bmisscount);
1853 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1854 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
fa1c114f 1855 "stuck beacon time (%u missed)\n",
e0d687bd
PR		 1856 ah->bmisscount);
1857 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 1858 "stuck beacon, resetting\n");
e0d687bd 1859 ieee80211_queue_work(ah->hw, &ah->reset_work);
fa1c114f
JS		 1860 }
1861 return;
1862 }
e0d687bd
PR		 1863 if (unlikely(ah->bmisscount != 0)) {
1864 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
fa1c114f 1865 "resume beacon xmit after %u misses\n",
e0d687bd
PR		 1866 ah->bmisscount);
1867 ah->bmisscount = 0;
fa1c114f
JS		 1868 }
1869
e0d687bd
PR		 1870 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
1871 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1872 u64 tsf = ath5k_hw_get_tsf64(ah);
1873 u32 tsftu = TSF_TO_TU(tsf);
e0d687bd
PR		 1874 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1875 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1876 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
b1ae1edf 1877 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
e0d687bd 1878 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
b1ae1edf 1879 } else /* only one interface */
e0d687bd 1880 vif = ah->bslot[0];
b1ae1edf
BG		 1881
1882 if (!vif)
1883 return;
1884
1885 avf = (void *)vif->drv_priv;
1886 bf = avf->bbuf;
b1ae1edf 1887
fa1c114f
JS		 1888 /*
1889 * Stop any current dma and put the new frame on the queue.
1890 * This should never fail since we check above that no frames
1891 * are still pending on the queue.
1892 */
e0d687bd
PR		 1893 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1894 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
fa1c114f
JS		 1895 /* NB: hw still stops DMA, so proceed */
1896 }
fa1c114f 1897
d82b577b 1898 /* refresh the beacon for AP or MESH mode */
e0d687bd 1899 if (ah->opmode == NL80211_IFTYPE_AP ||
bdc71bc5
BC		 1900 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1901 err = ath5k_beacon_update(ah->hw, vif);
1902 if (err)
1903 return;
1904 }
1905
1906 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1907 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1908 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
1909 return;
1910 }
1071db86 1911
e0d687bd 1912 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
0e472252 1913
e0d687bd
PR		 1914 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1915 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1916 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1917 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
fa1c114f 1918
e0d687bd 1919 skb = ieee80211_get_buffered_bc(ah->hw, vif);
cec8db23 1920 while (skb) {
e0d687bd 1921 ath5k_tx_queue(ah->hw, skb, ah->cabq);
4e868796 1922
e0d687bd 1923 if (ah->cabq->txq_len >= ah->cabq->txq_max)
4e868796
FF		 1924 break;
1925
e0d687bd 1926 skb = ieee80211_get_buffered_bc(ah->hw, vif);
cec8db23
BC		 1927 }
1928
e0d687bd 1929 ah->bsent++;
fa1c114f
JS		 1930}
1931
9804b98d
BR		 1932/**
1933 * ath5k_beacon_update_timers - update beacon timers
1934 *
e0d687bd 1935 * @ah: struct ath5k_hw pointer we are operating on
9804b98d
BR		 1936 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1937 * beacon timer update based on the current HW TSF.
1938 *
1939 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1940 * of a received beacon or the current local hardware TSF and write it to the
1941 * beacon timer registers.
1942 *
1943 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1944 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1945 * when we otherwise know we have to update the timers, but we keep it in this
1946 * function to have it all together in one place.
1947 */
cd2c5486 1948void
e0d687bd 1949ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
fa1c114f 1950{
9804b98d
BR		 1951 u32 nexttbtt, intval, hw_tu, bc_tu;
1952 u64 hw_tsf;
fa1c114f 1953
e0d687bd
PR		 1954 intval = ah->bintval & AR5K_BEACON_PERIOD;
1955 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
b1ae1edf
BG		 1956 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1957 if (intval < 15)
e0d687bd 1958 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
b1ae1edf
BG		 1959 intval);
1960 }
fa1c114f
JS		 1961 if (WARN_ON(!intval))
1962 return;
1963
9804b98d
BR		 1964 /* beacon TSF converted to TU */
1965 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1966
9804b98d
BR		 1967 /* current TSF converted to TU */
1968 hw_tsf = ath5k_hw_get_tsf64(ah);
1969 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1970
633d006e 1971#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
11f21df3 1972 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
25985edc 1973 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
11f21df3
BR		 1974 * configuration we need to make sure it is bigger than that. */
1975
9804b98d
BR		 1976 if (bc_tsf == -1) {
1977 /*
1978 * no beacons received, called internally.
1979 * just need to refresh timers based on HW TSF.
1980 */
1981 nexttbtt = roundup(hw_tu + FUDGE, intval);
1982 } else if (bc_tsf == 0) {
1983 /*
1984 * no beacon received, probably called by ath5k_reset_tsf().
1985 * reset TSF to start with 0.
1986 */
1987 nexttbtt = intval;
1988 intval |= AR5K_BEACON_RESET_TSF;
1989 } else if (bc_tsf > hw_tsf) {
1990 /*
25985edc 1991 * beacon received, SW merge happened but HW TSF not yet updated.
9804b98d
BR		 1992 * not possible to reconfigure timers yet, but next time we
1993 * receive a beacon with the same BSSID, the hardware will
1994 * automatically update the TSF and then we need to reconfigure
1995 * the timers.
1996 */
e0d687bd 1997 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 1998 "need to wait for HW TSF sync\n");
1999 return;
2000 } else {
2001 /*
2002 * most important case for beacon synchronization between STA.
2003 *
2004 * beacon received and HW TSF has been already updated by HW.
2005 * update next TBTT based on the TSF of the beacon, but make
2006 * sure it is ahead of our local TSF timer.
2007 */
2008 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2009 }
2010#undef FUDGE
fa1c114f 2011
e0d687bd 2012 ah->nexttbtt = nexttbtt;
036cd1ec 2013
fa1c114f 2014 intval |= AR5K_BEACON_ENA;
c47faa36 2015 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
9804b98d
BR		 2016
2017 /*
2018 * debugging output last in order to preserve the time critical aspect
2019 * of this function
2020 */
2021 if (bc_tsf == -1)
e0d687bd 2022 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2023 "reconfigured timers based on HW TSF\n");
2024 else if (bc_tsf == 0)
e0d687bd 2025 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2026 "reset HW TSF and timers\n");
2027 else
e0d687bd 2028 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2029 "updated timers based on beacon TSF\n");
2030
e0d687bd 2031 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2032 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2033 (unsigned long long) bc_tsf,
2034 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
e0d687bd 2035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
9804b98d
BR		 2036 intval & AR5K_BEACON_PERIOD,
2037 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2038 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2039}
2040
036cd1ec
BR		 2041/**
2042 * ath5k_beacon_config - Configure the beacon queues and interrupts
2043 *
e0d687bd 2044 * @ah: struct ath5k_hw pointer we are operating on
fa1c114f 2045 *
036cd1ec 2046 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2047 * interrupts to detect TSF updates only.
fa1c114f 2048 */
cd2c5486 2049void
e0d687bd 2050ath5k_beacon_config(struct ath5k_hw *ah)
fa1c114f 2051{
b5f03956 2052 unsigned long flags;
fa1c114f 2053
e0d687bd
PR		 2054 spin_lock_irqsave(&ah->block, flags);
2055 ah->bmisscount = 0;
2056 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2057
e0d687bd 2058 if (ah->enable_beacon) {
fa1c114f 2059 /*
036cd1ec
BR		 2060 * In IBSS mode we use a self-linked tx descriptor and let the
2061 * hardware send the beacons automatically. We have to load it
fa1c114f 2062 * only once here.
036cd1ec 2063 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2064 * timers in order to detect automatic TSF updates.
fa1c114f 2065 */
e0d687bd 2066 ath5k_beaconq_config(ah);
fa1c114f 2067
e0d687bd 2068 ah->imask |= AR5K_INT_SWBA;
036cd1ec 2069
e0d687bd 2070 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2071 if (ath5k_hw_hasveol(ah))
e0d687bd 2072 ath5k_beacon_send(ah);
da966bca 2073 } else
e0d687bd 2074 ath5k_beacon_update_timers(ah, -1);
21800491 2075 } else {
e0d687bd 2076 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
fa1c114f 2077 }
fa1c114f 2078
e0d687bd 2079 ath5k_hw_set_imr(ah, ah->imask);
21800491 2080 mmiowb();
e0d687bd 2081 spin_unlock_irqrestore(&ah->block, flags);
fa1c114f
JS		 2082}
2083
428cbd4f
NK		 2084static void ath5k_tasklet_beacon(unsigned long data)
2085{
e0d687bd 2086 struct ath5k_hw *ah = (struct ath5k_hw *) data;
428cbd4f
NK		 2087
2088 /*
2089 * Software beacon alert--time to send a beacon.
2090 *
2091 * In IBSS mode we use this interrupt just to
2092 * keep track of the next TBTT (target beacon
6a2a0e73 2093 * transmission time) in order to detect whether
428cbd4f
NK		 2094 * automatic TSF updates happened.
2095 */
e0d687bd 2096 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
6a2a0e73 2097 /* XXX: only if VEOL supported */
e0d687bd
PR		 2098 u64 tsf = ath5k_hw_get_tsf64(ah);
2099 ah->nexttbtt += ah->bintval;
2100 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
428cbd4f
NK		 2101 "SWBA nexttbtt: %x hw_tu: %x "
2102 "TSF: %llx\n",
e0d687bd 2103 ah->nexttbtt,
428cbd4f
NK		 2104 TSF_TO_TU(tsf),
2105 (unsigned long long) tsf);
2106 } else {
e0d687bd
PR		 2107 spin_lock(&ah->block);
2108 ath5k_beacon_send(ah);
2109 spin_unlock(&ah->block);
428cbd4f
NK		 2110 }
2111}
2112
fa1c114f
JS		 2113
2114/********************\
2115* Interrupt handling *
2116\********************/
2117
6a8a3f6b
BR		 2118static void
2119ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2120{
2111ac0d 2121 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
ce169aca
NK		 2122 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2123 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2124
2125 /* Run ANI only when calibration is not active */
2126
2111ac0d
BR		 2127 ah->ah_cal_next_ani = jiffies +
2128 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
e0d687bd 2129 tasklet_schedule(&ah->ani_tasklet);
2111ac0d 2130
ce169aca
NK		 2131 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2132 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2133 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2134
2135 /* Run calibration only when another calibration
2136 * is not running.
2137 *
2138 * Note: This is for both full/short calibration,
2139 * if it's time for a full one, ath5k_calibrate_work will deal
2140 * with it. */
2141
2142 ah->ah_cal_next_short = jiffies +
2143 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2144 ieee80211_queue_work(ah->hw, &ah->calib_work);
6a8a3f6b
BR		 2145 }
2146 /* we could use SWI to generate enough interrupts to meet our
2147 * calibration interval requirements, if necessary:
2148 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2149}
2150
c266c71a 2151static void
e0d687bd 2152ath5k_schedule_rx(struct ath5k_hw *ah)
c266c71a 2153{
e0d687bd
PR		 2154 ah->rx_pending = true;
2155 tasklet_schedule(&ah->rxtq);
c266c71a
FF		 2156}
2157
2158static void
e0d687bd 2159ath5k_schedule_tx(struct ath5k_hw *ah)
c266c71a 2160{
e0d687bd
PR		 2161 ah->tx_pending = true;
2162 tasklet_schedule(&ah->txtq);
c266c71a
FF		 2163}
2164
f5cbc8ba 2165static irqreturn_t
fa1c114f
JS		 2166ath5k_intr(int irq, void *dev_id)
2167{
e0d687bd 2168 struct ath5k_hw *ah = dev_id;
fa1c114f
JS		 2169 enum ath5k_int status;
2170 unsigned int counter = 1000;
2171
34ce644a
NK		 2172
2173 /*
2174 * If hw is not ready (or detached) and we get an
2175 * interrupt, or if we have no interrupts pending
2176 * (that means it's not for us) skip it.
2177 *
2178 * NOTE: Group 0/1 PCI interface registers are not
2179 * supported on WiSOCs, so we can't check for pending
2180 * interrupts (ISR belongs to another register group
2181 * so we are ok).
2182 */
e0d687bd 2183 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
34ce644a
NK		 2184 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2185 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2186 return IRQ_NONE;
2187
34ce644a 2188 /** Main loop **/
fa1c114f 2189 do {
34ce644a
NK		 2190 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2191
e0d687bd
PR		 2192 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2193 status, ah->imask);
34ce644a
NK		 2194
2195 /*
2196 * Fatal hw error -> Log and reset
2197 *
2198 * Fatal errors are unrecoverable so we have to
2199 * reset the card. These errors include bus and
2200 * dma errors.
2201 */
fa1c114f 2202 if (unlikely(status & AR5K_INT_FATAL)) {
34ce644a 2203
e0d687bd 2204 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 2205 "fatal int, resetting\n");
e0d687bd 2206 ieee80211_queue_work(ah->hw, &ah->reset_work);
34ce644a
NK		 2207
2208 /*
2209 * RX Overrun -> Count and reset if needed
2210 *
2211 * Receive buffers are full. Either the bus is busy or
2212 * the CPU is not fast enough to process all received
2213 * frames.
2214 */
fa1c114f 2215 } else if (unlikely(status & AR5K_INT_RXORN)) {
34ce644a 2216
87d77c4e 2217 /*
87d77c4e
BR		 2218 * Older chipsets need a reset to come out of this
2219 * condition, but we treat it as RX for newer chips.
34ce644a 2220 * We don't know exactly which versions need a reset
87d77c4e
BR		 2221 * this guess is copied from the HAL.
2222 */
e0d687bd 2223 ah->stats.rxorn_intr++;
34ce644a 2224
8d67a031 2225 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
e0d687bd 2226 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 2227 "rx overrun, resetting\n");
e0d687bd 2228 ieee80211_queue_work(ah->hw, &ah->reset_work);
d2c7f773 2229 } else
e0d687bd 2230 ath5k_schedule_rx(ah);
34ce644a 2231
fa1c114f 2232 } else {
34ce644a
NK		 2233
2234 /* Software Beacon Alert -> Schedule beacon tasklet */
d2c7f773 2235 if (status & AR5K_INT_SWBA)
e0d687bd 2236 tasklet_hi_schedule(&ah->beacontq);
d2c7f773 2237
34ce644a
NK		 2238 /*
2239 * No more RX descriptors -> Just count
2240 *
2241 * NB: the hardware should re-read the link when
2242 * RXE bit is written, but it doesn't work at
2243 * least on older hardware revs.
2244 */
2245 if (status & AR5K_INT_RXEOL)
e0d687bd 2246 ah->stats.rxeol_intr++;
34ce644a
NK		 2247
2248
2249 /* TX Underrun -> Bump tx trigger level */
2250 if (status & AR5K_INT_TXURN)
fa1c114f 2251 ath5k_hw_update_tx_triglevel(ah, true);
34ce644a
NK		 2252
2253 /* RX -> Schedule rx tasklet */
4c674c60 2254 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
e0d687bd 2255 ath5k_schedule_rx(ah);
34ce644a
NK		 2256
2257 /* TX -> Schedule tx tasklet */
2258 if (status & (AR5K_INT_TXOK
2259 | AR5K_INT_TXDESC
2260 | AR5K_INT_TXERR
2261 | AR5K_INT_TXEOL))
e0d687bd 2262 ath5k_schedule_tx(ah);
34ce644a
NK		 2263
2264 /* Missed beacon -> TODO
2265 if (status & AR5K_INT_BMISS)
2266 */
2267
2268 /* MIB event -> Update counters and notify ANI */
fa1c114f 2269 if (status & AR5K_INT_MIB) {
e0d687bd 2270 ah->stats.mib_intr++;
495391d7 2271 ath5k_hw_update_mib_counters(ah);
2111ac0d 2272 ath5k_ani_mib_intr(ah);
fa1c114f 2273 }
34ce644a
NK		 2274
2275 /* GPIO -> Notify RFKill layer */
e6a3b616 2276 if (status & AR5K_INT_GPIO)
e0d687bd 2277 tasklet_schedule(&ah->rf_kill.toggleq);
a6ae0716 2278
fa1c114f 2279 }
4cebb34c
FF		 2280
2281 if (ath5k_get_bus_type(ah) == ATH_AHB)
2282 break;
2283
2516baa6 2284 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f 2285
34ce644a
NK		 2286 /*
2287 * Until we handle rx/tx interrupts mask them on IMR
2288 *
2289 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2290 * and unset after we 've handled the interrupts.
2291 */
e0d687bd
PR		 2292 if (ah->rx_pending || ah->tx_pending)
2293 ath5k_set_current_imask(ah);
c266c71a 2294
fa1c114f 2295 if (unlikely(!counter))
e0d687bd 2296 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
fa1c114f 2297
34ce644a 2298 /* Fire up calibration poll */
6a8a3f6b 2299 ath5k_intr_calibration_poll(ah);
6e220662 2300
fa1c114f
JS		 2301 return IRQ_HANDLED;
2302}
2303
fa1c114f
JS		 2304/*
2305 * Periodically recalibrate the PHY to account
2306 * for temperature/environment changes.
2307 */
2308static void
ce169aca 2309ath5k_calibrate_work(struct work_struct *work)
fa1c114f 2310{
ce169aca
NK		 2311 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2312 calib_work);
2313
2314 /* Should we run a full calibration ? */
2315 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2316
2317 ah->ah_cal_next_full = jiffies +
2318 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2319 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2320
2321 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2322 "running full calibration\n");
2323
2324 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2325 /*
2326 * Rfgain is out of bounds, reset the chip
2327 * to load new gain values.
2328 */
2329 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2330 "got new rfgain, resetting\n");
2331 ieee80211_queue_work(ah->hw, &ah->reset_work);
2332 }
2333
2334 /* TODO: On full calibration we should stop TX here,
2335 * so that it doesn't interfere (mostly due to gain_f
2336 * calibration that messes with tx packets -see phy.c).
2337 *
2338 * NOTE: Stopping the queues from above is not enough
2339 * to stop TX but saves us from disconecting (at least
2340 * we don't lose packets). */
2341 ieee80211_stop_queues(ah->hw);
2342 } else
2343 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
fa1c114f 2344
6e220662 2345
e0d687bd
PR		 2346 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2347 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2348 ah->curchan->hw_value);
fa1c114f 2349
e0d687bd
PR		 2350 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2351 ATH5K_ERR(ah, "calibration of channel %u failed\n",
400ec45a 2352 ieee80211_frequency_to_channel(
e0d687bd 2353 ah->curchan->center_freq));
fa1c114f 2354
ce169aca
NK		 2355 /* Clear calibration flags */
2356 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) {
2357 ieee80211_wake_queues(ah->hw);
2358 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2359 } else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2360 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
fa1c114f
JS		 2361}
2362
2363
2111ac0d
BR		 2364static void
2365ath5k_tasklet_ani(unsigned long data)
2366{
e0d687bd 2367 struct ath5k_hw *ah = (void *)data;
2111ac0d
BR		 2368
2369 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2370 ath5k_ani_calibration(ah);
2371 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2372}
2373
2374
4edd761f
BR		 2375static void
2376ath5k_tx_complete_poll_work(struct work_struct *work)
2377{
e0d687bd 2378 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
4edd761f
BR		 2379 tx_complete_work.work);
2380 struct ath5k_txq *txq;
2381 int i;
2382 bool needreset = false;
2383
e0d687bd 2384 mutex_lock(&ah->lock);
599b13ad 2385
e0d687bd
PR		 2386 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2387 if (ah->txqs[i].setup) {
2388 txq = &ah->txqs[i];
4edd761f 2389 spin_lock_bh(&txq->lock);
23413296 2390 if (txq->txq_len > 1) {
4edd761f 2391 if (txq->txq_poll_mark) {
e0d687bd 2392 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
4edd761f
BR		 2393 "TX queue stuck %d\n",
2394 txq->qnum);
2395 needreset = true;
923e5b3d 2396 txq->txq_stuck++;
4edd761f
BR		 2397 spin_unlock_bh(&txq->lock);
2398 break;
2399 } else {
2400 txq->txq_poll_mark = true;
2401 }
2402 }
2403 spin_unlock_bh(&txq->lock);
2404 }
2405 }
2406
2407 if (needreset) {
e0d687bd 2408 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
4edd761f 2409 "TX queues stuck, resetting\n");
e0d687bd 2410 ath5k_reset(ah, NULL, true);
4edd761f
BR		 2411 }
2412
e0d687bd 2413 mutex_unlock(&ah->lock);
599b13ad 2414
e0d687bd 2415 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
4edd761f
BR		 2416 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2417}
2418
2419
8a63facc
BC		 2420/*************************\
2421* Initialization routines *
2422\*************************/
fa1c114f 2423
25380d80 2424int __devinit
bb1f3ad9 2425ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
132b1c3e 2426{
e0d687bd 2427 struct ieee80211_hw *hw = ah->hw;
132b1c3e
FF		 2428 struct ath_common *common;
2429 int ret;
2430 int csz;
2431
2432 /* Initialize driver private data */
e0d687bd 2433 SET_IEEE80211_DEV(hw, ah->dev);
132b1c3e 2434 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2435 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2436 IEEE80211_HW_SIGNAL_DBM |
2437 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2438
2439 hw->wiphy->interface_modes =
2440 BIT(NL80211_IFTYPE_AP) |
2441 BIT(NL80211_IFTYPE_STATION) |
2442 BIT(NL80211_IFTYPE_ADHOC) |
2443 BIT(NL80211_IFTYPE_MESH_POINT);
2444
f9972577
AQ		 2445 /* SW support for IBSS_RSN is provided by mac80211 */
2446 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2447
3de135db
BR		 2448 /* both antennas can be configured as RX or TX */
2449 hw->wiphy->available_antennas_tx = 0x3;
2450 hw->wiphy->available_antennas_rx = 0x3;
2451
132b1c3e
FF		 2452 hw->extra_tx_headroom = 2;
2453 hw->channel_change_time = 5000;
2454
2455 /*
2456 * Mark the device as detached to avoid processing
2457 * interrupts until setup is complete.
2458 */
e0d687bd 2459 __set_bit(ATH_STAT_INVALID, ah->status);
132b1c3e 2460
e0d687bd
PR		 2461 ah->opmode = NL80211_IFTYPE_STATION;
2462 ah->bintval = 1000;
2463 mutex_init(&ah->lock);
2464 spin_lock_init(&ah->rxbuflock);
2465 spin_lock_init(&ah->txbuflock);
2466 spin_lock_init(&ah->block);
2467 spin_lock_init(&ah->irqlock);
132b1c3e
FF		 2468
2469 /* Setup interrupt handler */
e0d687bd 2470 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
132b1c3e 2471 if (ret) {
e0d687bd 2472 ATH5K_ERR(ah, "request_irq failed\n");
132b1c3e
FF		 2473 goto err;
2474 }
2475
e0d687bd 2476 common = ath5k_hw_common(ah);
132b1c3e
FF		 2477 common->ops = &ath5k_common_ops;
2478 common->bus_ops = bus_ops;
e0d687bd 2479 common->ah = ah;
132b1c3e 2480 common->hw = hw;
e0d687bd 2481 common->priv = ah;
26d16d23 2482 common->clockrate = 40;
132b1c3e
FF		 2483
2484 /*
2485 * Cache line size is used to size and align various
2486 * structures used to communicate with the hardware.
2487 */
2488 ath5k_read_cachesize(common, &csz);
2489 common->cachelsz = csz << 2; /* convert to bytes */
2490
2491 spin_lock_init(&common->cc_lock);
2492
2493 /* Initialize device */
e0d687bd 2494 ret = ath5k_hw_init(ah);
132b1c3e 2495 if (ret)
e0d687bd 2496 goto err_irq;
132b1c3e 2497
86f62d9b
NK		 2498 /* Set up multi-rate retry capabilities */
2499 if (ah->ah_capabilities.cap_has_mrr_support) {
132b1c3e 2500 hw->max_rates = 4;
76a9f6fd
BR		 2501 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2502 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2503 }
2504
2505 hw->vif_data_size = sizeof(struct ath5k_vif);
2506
2507 /* Finish private driver data initialization */
2508 ret = ath5k_init(hw);
2509 if (ret)
2510 goto err_ah;
2511
e0d687bd
PR		 2512 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2513 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2514 ah->ah_mac_srev,
2515 ah->ah_phy_revision);
132b1c3e 2516
e0d687bd 2517 if (!ah->ah_single_chip) {
132b1c3e 2518 /* Single chip radio (!RF5111) */
e0d687bd
PR		 2519 if (ah->ah_radio_5ghz_revision &&
2520 !ah->ah_radio_2ghz_revision) {
132b1c3e
FF		 2521 /* No 5GHz support -> report 2GHz radio */
2522 if (!test_bit(AR5K_MODE_11A,
e0d687bd
PR		 2523 ah->ah_capabilities.cap_mode)) {
2524 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
132b1c3e 2525 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2526 ah->ah_radio_5ghz_revision),
2527 ah->ah_radio_5ghz_revision);
132b1c3e 2528 /* No 2GHz support (5110 and some
6a2a0e73 2529 * 5GHz only cards) -> report 5GHz radio */
132b1c3e 2530 } else if (!test_bit(AR5K_MODE_11B,
e0d687bd
PR		 2531 ah->ah_capabilities.cap_mode)) {
2532 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
132b1c3e 2533 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2534 ah->ah_radio_5ghz_revision),
2535 ah->ah_radio_5ghz_revision);
132b1c3e
FF		 2536 /* Multiband radio */
2537 } else {
e0d687bd 2538 ATH5K_INFO(ah, "RF%s multiband radio found"
132b1c3e
FF		 2539 " (0x%x)\n",
2540 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2541 ah->ah_radio_5ghz_revision),
2542 ah->ah_radio_5ghz_revision);
132b1c3e
FF		 2543 }
2544 }
2545 /* Multi chip radio (RF5111 - RF2111) ->
2546 * report both 2GHz/5GHz radios */
e0d687bd
PR		 2547 else if (ah->ah_radio_5ghz_revision &&
2548 ah->ah_radio_2ghz_revision) {
2549 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
132b1c3e 2550 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2551 ah->ah_radio_5ghz_revision),
2552 ah->ah_radio_5ghz_revision);
2553 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
132b1c3e 2554 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2555 ah->ah_radio_2ghz_revision),
2556 ah->ah_radio_2ghz_revision);
132b1c3e
FF		 2557 }
2558 }
2559
e0d687bd 2560 ath5k_debug_init_device(ah);
132b1c3e
FF		 2561
2562 /* ready to process interrupts */
e0d687bd 2563 __clear_bit(ATH_STAT_INVALID, ah->status);
132b1c3e
FF		 2564
2565 return 0;
2566err_ah:
e0d687bd 2567 ath5k_hw_deinit(ah);
132b1c3e 2568err_irq:
e0d687bd 2569 free_irq(ah->irq, ah);
132b1c3e
FF		 2570err:
2571 return ret;
2572}
2573
fa1c114f 2574static int
e0d687bd 2575ath5k_stop_locked(struct ath5k_hw *ah)
cec8db23 2576{
cec8db23 2577
e0d687bd
PR		 2578 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2579 test_bit(ATH_STAT_INVALID, ah->status));
8a63facc
BC		 2580
2581 /*
2582 * Shutdown the hardware and driver:
2583 * stop output from above
2584 * disable interrupts
2585 * turn off timers
2586 * turn off the radio
2587 * clear transmit machinery
2588 * clear receive machinery
2589 * drain and release tx queues
2590 * reclaim beacon resources
2591 * power down hardware
2592 *
2593 * Note that some of this work is not possible if the
2594 * hardware is gone (invalid).
2595 */
e0d687bd 2596 ieee80211_stop_queues(ah->hw);
8a63facc 2597
e0d687bd
PR		 2598 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2599 ath5k_led_off(ah);
8a63facc 2600 ath5k_hw_set_imr(ah, 0);
e0d687bd
PR		 2601 synchronize_irq(ah->irq);
2602 ath5k_rx_stop(ah);
80dac9ee 2603 ath5k_hw_dma_stop(ah);
e0d687bd 2604 ath5k_drain_tx_buffs(ah);
8a63facc
BC		 2605 ath5k_hw_phy_disable(ah);
2606 }
2607
2608 return 0;
cec8db23
BC		 2609}
2610
fabba048 2611int ath5k_start(struct ieee80211_hw *hw)
fa1c114f 2612{
fabba048 2613 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2614 struct ath_common *common = ath5k_hw_common(ah);
2615 int ret, i;
fa1c114f 2616
e0d687bd 2617 mutex_lock(&ah->lock);
8a63facc 2618
e0d687bd 2619 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
fa1c114f 2620
fa1c114f 2621 /*
8a63facc
BC		 2622 * Stop anything previously setup. This is safe
2623 * no matter this is the first time through or not.
fa1c114f 2624 */
e0d687bd 2625 ath5k_stop_locked(ah);
fa1c114f 2626
8a63facc
BC		 2627 /*
2628 * The basic interface to setting the hardware in a good
2629 * state is ``reset''. On return the hardware is known to
2630 * be powered up and with interrupts disabled. This must
2631 * be followed by initialization of the appropriate bits
2632 * and then setup of the interrupt mask.
2633 */
e0d687bd 2634 ah->curchan = ah->hw->conf.channel;
34ce644a
NK		 2635 ah->imask = AR5K_INT_RXOK
2636 | AR5K_INT_RXERR
2637 | AR5K_INT_RXEOL
2638 | AR5K_INT_RXORN
2639 | AR5K_INT_TXDESC
2640 | AR5K_INT_TXEOL
2641 | AR5K_INT_FATAL
2642 | AR5K_INT_GLOBAL
2643 | AR5K_INT_MIB;
fa1c114f 2644
e0d687bd 2645 ret = ath5k_reset(ah, NULL, false);
8a63facc
BC		 2646 if (ret)
2647 goto done;
fa1c114f 2648
84e1e737
NK		 2649 if (!ath5k_modparam_no_hw_rfkill_switch)
2650 ath5k_rfkill_hw_start(ah);
8a63facc
BC		 2651
2652 /*
2653 * Reset the key cache since some parts do not reset the
2654 * contents on initial power up or resume from suspend.
2655 */
2656 for (i = 0; i < common->keymax; i++)
2657 ath_hw_keyreset(common, (u16) i);
2658
61cde037
NK		 2659 /* Use higher rates for acks instead of base
2660 * rate */
2661 ah->ah_ack_bitrate_high = true;
b1ae1edf 2662
e0d687bd
PR		 2663 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2664 ah->bslot[i] = NULL;
b1ae1edf 2665
8a63facc
BC		 2666 ret = 0;
2667done:
2668 mmiowb();
e0d687bd 2669 mutex_unlock(&ah->lock);
4edd761f 2670
e0d687bd 2671 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
4edd761f
BR		 2672 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2673
8a63facc
BC		 2674 return ret;
2675}
2676
e0d687bd 2677static void ath5k_stop_tasklets(struct ath5k_hw *ah)
8a63facc 2678{
e0d687bd
PR		 2679 ah->rx_pending = false;
2680 ah->tx_pending = false;
2681 tasklet_kill(&ah->rxtq);
2682 tasklet_kill(&ah->txtq);
e0d687bd
PR		 2683 tasklet_kill(&ah->beacontq);
2684 tasklet_kill(&ah->ani_tasklet);
8a63facc
BC		 2685}
2686
2687/*
2688 * Stop the device, grabbing the top-level lock to protect
2689 * against concurrent entry through ath5k_init (which can happen
2690 * if another thread does a system call and the thread doing the
2691 * stop is preempted).
2692 */
fabba048 2693void ath5k_stop(struct ieee80211_hw *hw)
8a63facc 2694{
fabba048 2695 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2696 int ret;
2697
e0d687bd
PR		 2698 mutex_lock(&ah->lock);
2699 ret = ath5k_stop_locked(ah);
2700 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
8a63facc
BC		 2701 /*
2702 * Don't set the card in full sleep mode!
2703 *
2704 * a) When the device is in this state it must be carefully
2705 * woken up or references to registers in the PCI clock
2706 * domain may freeze the bus (and system). This varies
2707 * by chip and is mostly an issue with newer parts
2708 * (madwifi sources mentioned srev >= 0x78) that go to
2709 * sleep more quickly.
2710 *
2711 * b) On older chips full sleep results a weird behaviour
2712 * during wakeup. I tested various cards with srev < 0x78
2713 * and they don't wake up after module reload, a second
2714 * module reload is needed to bring the card up again.
2715 *
2716 * Until we figure out what's going on don't enable
2717 * full chip reset on any chip (this is what Legacy HAL
2718 * and Sam's HAL do anyway). Instead Perform a full reset
2719 * on the device (same as initial state after attach) and
2720 * leave it idle (keep MAC/BB on warm reset) */
e0d687bd 2721 ret = ath5k_hw_on_hold(ah);
8a63facc 2722
e0d687bd 2723 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8a63facc 2724 "putting device to sleep\n");
fa1c114f
JS		 2725 }
2726
8a63facc 2727 mmiowb();
e0d687bd 2728 mutex_unlock(&ah->lock);
8a63facc 2729
e0d687bd 2730 ath5k_stop_tasklets(ah);
4edd761f 2731
e0d687bd 2732 cancel_delayed_work_sync(&ah->tx_complete_work);
8a63facc 2733
84e1e737
NK		 2734 if (!ath5k_modparam_no_hw_rfkill_switch)
2735 ath5k_rfkill_hw_stop(ah);
fa1c114f
JS		 2736}
2737
209d889b
BC		 2738/*
2739 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2740 * and change to the given channel.
5faaff74 2741 *
e0d687bd 2742 * This should be called with ah->lock.
209d889b 2743 */
fa1c114f 2744static int
e0d687bd 2745ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
8aec7af9 2746 bool skip_pcu)
fa1c114f 2747{
f15a4bb2 2748 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2749 int ret, ani_mode;
a99168ee 2750 bool fast;
fa1c114f 2751
e0d687bd 2752 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2753
450464de 2754 ath5k_hw_set_imr(ah, 0);
e0d687bd
PR		 2755 synchronize_irq(ah->irq);
2756 ath5k_stop_tasklets(ah);
450464de 2757
25985edc 2758 /* Save ani mode and disable ANI during
344b54b9
NK		 2759 * reset. If we don't we might get false
2760 * PHY error interrupts. */
e0d687bd 2761 ani_mode = ah->ani_state.ani_mode;
344b54b9
NK		 2762 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2763
19252ecb
NK		 2764 /* We are going to empty hw queues
2765 * so we should also free any remaining
2766 * tx buffers */
e0d687bd 2767 ath5k_drain_tx_buffs(ah);
930a7622 2768 if (chan)
e0d687bd 2769 ah->curchan = chan;
a99168ee
NK		 2770
2771 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2772
e0d687bd 2773 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
d7dc1003 2774 if (ret) {
e0d687bd 2775 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
fa1c114f
JS		 2776 goto err;
2777 }
d7dc1003 2778
e0d687bd 2779 ret = ath5k_rx_start(ah);
d7dc1003 2780 if (ret) {
e0d687bd 2781 ATH5K_ERR(ah, "can't start recv logic\n");
fa1c114f
JS		 2782 goto err;
2783 }
d7dc1003 2784
344b54b9 2785 ath5k_ani_init(ah, ani_mode);
2111ac0d 2786
ce169aca
NK		 2787 /*
2788 * Set calibration intervals
2789 *
2790 * Note: We don't need to run calibration imediately
2791 * since some initial calibration is done on reset
2792 * even for fast channel switching. Also on scanning
2793 * this will get set again and again and it won't get
2794 * executed unless we connect somewhere and spend some
2795 * time on the channel (that's what calibration needs
2796 * anyway to be accurate).
2797 */
2798 ah->ah_cal_next_full = jiffies +
2799 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2800 ah->ah_cal_next_ani = jiffies +
2801 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2802 ah->ah_cal_next_short = jiffies +
2803 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2804
5dcc03fe 2805 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2806
f15a4bb2 2807 /* clear survey data and cycle counters */
e0d687bd 2808 memset(&ah->survey, 0, sizeof(ah->survey));
bb007554 2809 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2810 ath_hw_cycle_counters_update(common);
2811 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2812 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2813 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2814
fa1c114f 2815 /*
d7dc1003
JS		 2816 * Change channels and update the h/w rate map if we're switching;
2817 * e.g. 11a to 11b/g.
2818 *
2819 * We may be doing a reset in response to an ioctl that changes the
2820 * channel so update any state that might change as a result.
fa1c114f
JS		 2821 *
2822 * XXX needed?
2823 */
e0d687bd 2824/* ath5k_chan_change(ah, c); */
fa1c114f 2825
e0d687bd 2826 ath5k_beacon_config(ah);
d7dc1003 2827 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2828
e0d687bd 2829 ieee80211_wake_queues(ah->hw);
397f385b 2830
fa1c114f
JS		 2831 return 0;
2832err:
2833 return ret;
2834}
2835
5faaff74
BC		 2836static void ath5k_reset_work(struct work_struct *work)
2837{
e0d687bd 2838 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
5faaff74
BC		 2839 reset_work);
2840
e0d687bd
PR		 2841 mutex_lock(&ah->lock);
2842 ath5k_reset(ah, NULL, true);
2843 mutex_unlock(&ah->lock);
5faaff74
BC		 2844}
2845
25380d80 2846static int __devinit
132b1c3e 2847ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2848{
132b1c3e 2849
e0d687bd 2850 struct ath5k_hw *ah = hw->priv;
8a63facc 2851 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2852 struct ath5k_txq *txq;
8a63facc 2853 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2854 int ret;
2855
fa1c114f 2856
8a63facc
BC		 2857 /*
2858 * Collect the channel list. The 802.11 layer
6a2a0e73 2859 * is responsible for filtering this list based
8a63facc
BC		 2860 * on settings like the phy mode and regulatory
2861 * domain restrictions.
2862 */
2863 ret = ath5k_setup_bands(hw);
2864 if (ret) {
e0d687bd 2865 ATH5K_ERR(ah, "can't get channels\n");
8a63facc
BC		 2866 goto err;
2867 }
67d2e2df 2868
8a63facc
BC		 2869 /*
2870 * Allocate tx+rx descriptors and populate the lists.
2871 */
e0d687bd 2872 ret = ath5k_desc_alloc(ah);
8a63facc 2873 if (ret) {
e0d687bd 2874 ATH5K_ERR(ah, "can't allocate descriptors\n");
8a63facc
BC		 2875 goto err;
2876 }
fa1c114f 2877
8a63facc
BC		 2878 /*
2879 * Allocate hardware transmit queues: one queue for
2880 * beacon frames and one data queue for each QoS
2881 * priority. Note that hw functions handle resetting
2882 * these queues at the needed time.
2883 */
2884 ret = ath5k_beaconq_setup(ah);
2885 if (ret < 0) {
e0d687bd 2886 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
8a63facc
BC		 2887 goto err_desc;
2888 }
e0d687bd
PR		 2889 ah->bhalq = ret;
2890 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2891 if (IS_ERR(ah->cabq)) {
2892 ATH5K_ERR(ah, "can't setup cab queue\n");
2893 ret = PTR_ERR(ah->cabq);
8a63facc
BC		 2894 goto err_bhal;
2895 }
fa1c114f 2896
22d8d9f8
BR		 2897 /* 5211 and 5212 usually support 10 queues but we better rely on the
2898 * capability information */
2899 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2900 /* This order matches mac80211's queue priority, so we can
2901 * directly use the mac80211 queue number without any mapping */
e0d687bd 2902 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
22d8d9f8 2903 if (IS_ERR(txq)) {
e0d687bd 2904 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2905 ret = PTR_ERR(txq);
2906 goto err_queues;
2907 }
e0d687bd 2908 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
22d8d9f8 2909 if (IS_ERR(txq)) {
e0d687bd 2910 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2911 ret = PTR_ERR(txq);
2912 goto err_queues;
2913 }
e0d687bd 2914 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
22d8d9f8 2915 if (IS_ERR(txq)) {
e0d687bd 2916 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2917 ret = PTR_ERR(txq);
2918 goto err_queues;
2919 }
e0d687bd 2920 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
22d8d9f8 2921 if (IS_ERR(txq)) {
e0d687bd 2922 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2923 ret = PTR_ERR(txq);
2924 goto err_queues;
2925 }
2926 hw->queues = 4;
2927 } else {
2928 /* older hardware (5210) can only support one data queue */
e0d687bd 2929 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
22d8d9f8 2930 if (IS_ERR(txq)) {
e0d687bd 2931 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2932 ret = PTR_ERR(txq);
2933 goto err_queues;
2934 }
2935 hw->queues = 1;
2936 }
fa1c114f 2937
e0d687bd
PR		 2938 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2939 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
e0d687bd
PR		 2940 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2941 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
be009370 2942
e0d687bd 2943 INIT_WORK(&ah->reset_work, ath5k_reset_work);
ce169aca 2944 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
e0d687bd 2945 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2946
fa9bfd61 2947 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
8a63facc 2948 if (ret) {
e0d687bd 2949 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
8a63facc 2950 goto err_queues;
e30eb4ab 2951 }
2bed03eb 2952
8a63facc
BC		 2953 SET_IEEE80211_PERM_ADDR(hw, mac);
2954 /* All MAC address bits matter for ACKs */
e0d687bd 2955 ath5k_update_bssid_mask_and_opmode(ah, NULL);
8a63facc
BC		 2956
2957 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2958 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2959 if (ret) {
e0d687bd 2960 ATH5K_ERR(ah, "can't initialize regulatory system\n");
8a63facc
BC		 2961 goto err_queues;
2962 }
2963
2964 ret = ieee80211_register_hw(hw);
2965 if (ret) {
e0d687bd 2966 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
8a63facc
BC		 2967 goto err_queues;
2968 }
2969
2970 if (!ath_is_world_regd(regulatory))
2971 regulatory_hint(hw->wiphy, regulatory->alpha2);
2972
e0d687bd 2973 ath5k_init_leds(ah);
8a63facc 2974
e0d687bd 2975 ath5k_sysfs_register(ah);
8a63facc
BC		 2976
2977 return 0;
2978err_queues:
e0d687bd 2979 ath5k_txq_release(ah);
8a63facc 2980err_bhal:
e0d687bd 2981 ath5k_hw_release_tx_queue(ah, ah->bhalq);
8a63facc 2982err_desc:
e0d687bd 2983 ath5k_desc_free(ah);
8a63facc
BC		 2984err:
2985 return ret;
2986}
2987
132b1c3e 2988void
bb1f3ad9 2989ath5k_deinit_ah(struct ath5k_hw *ah)
8a63facc 2990{
e0d687bd 2991 struct ieee80211_hw *hw = ah->hw;
8a63facc
BC		 2992
2993 /*
2994 * NB: the order of these is important:
2995 * o call the 802.11 layer before detaching ath5k_hw to
2996 * ensure callbacks into the driver to delete global
2997 * key cache entries can be handled
2998 * o reclaim the tx queue data structures after calling
2999 * the 802.11 layer as we'll get called back to reclaim
3000 * node state and potentially want to use them
3001 * o to cleanup the tx queues the hal is called, so detach
3002 * it last
3003 * XXX: ??? detach ath5k_hw ???
3004 * Other than that, it's straightforward...
3005 */
3006 ieee80211_unregister_hw(hw);
e0d687bd
PR		 3007 ath5k_desc_free(ah);
3008 ath5k_txq_release(ah);
3009 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3010 ath5k_unregister_leds(ah);
8a63facc 3011
e0d687bd 3012 ath5k_sysfs_unregister(ah);
8a63facc
BC		 3013 /*
3014 * NB: can't reclaim these until after ieee80211_ifdetach
3015 * returns because we'll get called back to reclaim node
3016 * state and potentially want to use them.
3017 */
e0d687bd
PR		 3018 ath5k_hw_deinit(ah);
3019 free_irq(ah->irq, ah);
8a63facc
BC		 3020}
3021
cd2c5486 3022bool
e0d687bd 3023ath5k_any_vif_assoc(struct ath5k_hw *ah)
b1ae1edf 3024{
e4b0b32a 3025 struct ath5k_vif_iter_data iter_data;
b1ae1edf
BG		 3026 iter_data.hw_macaddr = NULL;
3027 iter_data.any_assoc = false;
3028 iter_data.need_set_hw_addr = false;
3029 iter_data.found_active = true;
3030
e0d687bd 3031 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
b1ae1edf
BG		 3032 &iter_data);
3033 return iter_data.any_assoc;
3034}
3035
cd2c5486 3036void
f5cbc8ba 3037ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
8a63facc 3038{
e0d687bd 3039 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 3040 u32 rfilt;
3041 rfilt = ath5k_hw_get_rx_filter(ah);
3042 if (enable)
3043 rfilt |= AR5K_RX_FILTER_BEACON;
3044 else
3045 rfilt &= ~AR5K_RX_FILTER_BEACON;
3046 ath5k_hw_set_rx_filter(ah, rfilt);
e0d687bd 3047 ah->filter_flags = rfilt;
8a63facc 3048}
Linux kernel - Deliverables
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