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ath5k: remove most references to XR
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
b7f080cf 45#include <linux/dma-mapping.h>
274c7c36 46#include <linux/hardirq.h>
fa1c114f 47#include <linux/if.h>
274c7c36 48#include <linux/io.h>
fa1c114f
JS		 49#include <linux/netdevice.h>
50#include <linux/cache.h>
fa1c114f
JS		 51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
5a0e3ad6 53#include <linux/slab.h>
b1ae1edf 54#include <linux/etherdevice.h>
fa1c114f
JS		 55
56#include <net/ieee80211_radiotap.h>
57
58#include <asm/unaligned.h>
59
60#include "base.h"
61#include "reg.h"
62#include "debug.h"
2111ac0d 63#include "ani.h"
fa1c114f 64
0e472252
BC		 65#define CREATE_TRACE_POINTS
66#include "trace.h"
67
18cb6e32
JL		 68int ath5k_modparam_nohwcrypt;
69module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 70MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 71
42639fcd 72static int modparam_all_channels;
46802a4f 73module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 74MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
75
a99168ee
NK		 76static int modparam_fastchanswitch;
77module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
78MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
79
80
fa1c114f
JS		 81/* Module info */
82MODULE_AUTHOR("Jiri Slaby");
83MODULE_AUTHOR("Nick Kossifidis");
84MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
85MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
86MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 87
132b1c3e 88static int ath5k_init(struct ieee80211_hw *hw);
e0d687bd 89static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
8aec7af9 90 bool skip_pcu);
fa1c114f 91
fa1c114f 92/* Known SREVs */
2c91108c 93static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 94#ifdef CONFIG_ATHEROS_AR231X
95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
96 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
97 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
99 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
101 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
102#else
1bef016a
NK		 103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 121#endif
1bef016a 122 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 123 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
124 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 125 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 129 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 130 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
131 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 132 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
133 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
134 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 135 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 136 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 137#ifdef CONFIG_ATHEROS_AR231X
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140#endif
fa1c114f
JS		 141 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
142};
143
2c91108c 144static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 145 { .bitrate = 10,
146 .hw_value = ATH5K_RATE_CODE_1M, },
147 { .bitrate = 20,
148 .hw_value = ATH5K_RATE_CODE_2M,
149 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
150 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
151 { .bitrate = 55,
152 .hw_value = ATH5K_RATE_CODE_5_5M,
153 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
155 { .bitrate = 110,
156 .hw_value = ATH5K_RATE_CODE_11M,
157 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 { .bitrate = 60,
160 .hw_value = ATH5K_RATE_CODE_6M,
161 .flags = 0 },
162 { .bitrate = 90,
163 .hw_value = ATH5K_RATE_CODE_9M,
164 .flags = 0 },
165 { .bitrate = 120,
166 .hw_value = ATH5K_RATE_CODE_12M,
167 .flags = 0 },
168 { .bitrate = 180,
169 .hw_value = ATH5K_RATE_CODE_18M,
170 .flags = 0 },
171 { .bitrate = 240,
172 .hw_value = ATH5K_RATE_CODE_24M,
173 .flags = 0 },
174 { .bitrate = 360,
175 .hw_value = ATH5K_RATE_CODE_36M,
176 .flags = 0 },
177 { .bitrate = 480,
178 .hw_value = ATH5K_RATE_CODE_48M,
179 .flags = 0 },
180 { .bitrate = 540,
181 .hw_value = ATH5K_RATE_CODE_54M,
182 .flags = 0 },
183 /* XR missing */
184};
185
fa1c114f
JS		 186static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
187{
188 u64 tsf = ath5k_hw_get_tsf64(ah);
189
190 if ((tsf & 0x7fff) < rstamp)
191 tsf -= 0x8000;
192
193 return (tsf & ~0x7fff) | rstamp;
194}
195
e5b046d8 196const char *
fa1c114f
JS		 197ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
198{
199 const char *name = "xxxxx";
200 unsigned int i;
201
202 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
203 if (srev_names[i].sr_type != type)
204 continue;
75d0edb8
NK		 205
206 if ((val & 0xf0) == srev_names[i].sr_val)
207 name = srev_names[i].sr_name;
208
209 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 210 name = srev_names[i].sr_name;
211 break;
212 }
213 }
214
215 return name;
216}
e5aa8474
LR		 217static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
218{
219 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
220 return ath5k_hw_reg_read(ah, reg_offset);
221}
222
223static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
224{
225 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
226 ath5k_hw_reg_write(ah, val, reg_offset);
227}
228
229static const struct ath_ops ath5k_common_ops = {
230 .read = ath5k_ioread32,
231 .write = ath5k_iowrite32,
232};
fa1c114f 233
8a63facc
BC		 234/***********************\
235* Driver Initialization *
236\***********************/
237
238static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 239{
8a63facc 240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
e0d687bd
PR		 241 struct ath5k_hw *ah = hw->priv;
242 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
fa1c114f 243
8a63facc
BC		 244 return ath_reg_notifier_apply(wiphy, request, regulatory);
245}
6ccf15a1 246
8a63facc
BC		 247/********************\
248* Channel/mode setup *
249\********************/
fa1c114f 250
8a63facc
BC		 251/*
252 * Returns true for the channel numbers used without all_channels modparam.
253 */
410e6120 254static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 255{
410e6120
BR		 256 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
257 return true;
258
259 return /* UNII 1,2 */
260 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 261 /* midband */
262 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
263 /* UNII-3 */
410e6120
BR		 264 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
265 /* 802.11j 5.030-5.080 GHz (20MHz) */
266 (chan == 8 || chan == 12 || chan == 16) ||
267 /* 802.11j 4.9GHz (20MHz) */
268 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 269}
fa1c114f 270
8a63facc 271static unsigned int
97d9c3a3
BR		 272ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
273 unsigned int mode, unsigned int max)
8a63facc 274{
2b1351a3 275 unsigned int count, size, chfreq, freq, ch;
90c02d72 276 enum ieee80211_band band;
fa1c114f 277
8a63facc
BC		 278 switch (mode) {
279 case AR5K_MODE_11A:
8a63facc 280 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 281 size = 220;
8a63facc 282 chfreq = CHANNEL_5GHZ;
90c02d72 283 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 284 break;
285 case AR5K_MODE_11B:
286 case AR5K_MODE_11G:
8a63facc
BC		 287 size = 26;
288 chfreq = CHANNEL_2GHZ;
90c02d72 289 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 290 break;
291 default:
e0d687bd 292 ATH5K_WARN(ah, "bad mode, not copying channels\n");
8a63facc 293 return 0;
fa1c114f
JS		 294 }
295
2b1351a3
BR		 296 count = 0;
297 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 298 freq = ieee80211_channel_to_frequency(ch, band);
299
300 if (freq == 0) /* mapping failed - not a standard channel */
301 continue;
fa1c114f 302
8a63facc
BC		 303 /* Check if channel is supported by the chipset */
304 if (!ath5k_channel_ok(ah, freq, chfreq))
305 continue;
f59ac048 306
410e6120
BR		 307 if (!modparam_all_channels &&
308 !ath5k_is_standard_channel(ch, band))
8a63facc 309 continue;
f59ac048 310
8a63facc
BC		 311 /* Write channel info and increment counter */
312 channels[count].center_freq = freq;
90c02d72 313 channels[count].band = band;
8a63facc
BC		 314 switch (mode) {
315 case AR5K_MODE_11A:
316 case AR5K_MODE_11G:
317 channels[count].hw_value = chfreq | CHANNEL_OFDM;
318 break;
8a63facc
BC		 319 case AR5K_MODE_11B:
320 channels[count].hw_value = CHANNEL_B;
321 }
fa1c114f 322
8a63facc 323 count++;
8a63facc 324 }
fa1c114f 325
8a63facc
BC		 326 return count;
327}
fa1c114f 328
8a63facc 329static void
e0d687bd 330ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
8a63facc
BC		 331{
332 u8 i;
fa1c114f 333
8a63facc 334 for (i = 0; i < AR5K_MAX_RATES; i++)
e0d687bd 335 ah->rate_idx[b->band][i] = -1;
fa1c114f 336
8a63facc 337 for (i = 0; i < b->n_bitrates; i++) {
e0d687bd 338 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
8a63facc 339 if (b->bitrates[i].hw_value_short)
e0d687bd 340 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 341 }
8a63facc 342}
fa1c114f 343
8a63facc
BC		 344static int
345ath5k_setup_bands(struct ieee80211_hw *hw)
346{
e0d687bd 347 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
fa1c114f 351
e0d687bd
PR		 352 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(ah->channels);
db719718 354
8a63facc 355 /* 2GHz band */
e0d687bd 356 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
8a63facc 357 sband->band = IEEE80211_BAND_2GHZ;
e0d687bd 358 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
9adca126 359
e0d687bd 360 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
8a63facc
BC		 361 /* G mode */
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
2f7fe870 365
e0d687bd 366 sband->channels = ah->channels;
08105690 367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 368 AR5K_MODE_11G, max_c);
fa1c114f 369
8a63facc
BC		 370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
372 max_c -= count_c;
e0d687bd 373 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
8a63facc
BC		 374 /* B mode */
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
fa1c114f 378
8a63facc
BC		 379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
381 * fix them up here:
382 */
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 389 }
390 }
fa1c114f 391
e0d687bd 392 sband->channels = ah->channels;
08105690 393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 394 AR5K_MODE_11B, max_c);
fa1c114f 395
8a63facc
BC		 396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
399 }
e0d687bd 400 ath5k_setup_rate_idx(ah, sband);
fa1c114f 401
8a63facc 402 /* 5GHz band, A mode */
e0d687bd
PR		 403 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
404 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
8a63facc 405 sband->band = IEEE80211_BAND_5GHZ;
e0d687bd 406 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 407
8a63facc
BC		 408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
fa1c114f 411
e0d687bd 412 sband->channels = &ah->channels[count_c];
08105690 413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 414 AR5K_MODE_11A, max_c);
fa1c114f 415
8a63facc
BC		 416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
e0d687bd 418 ath5k_setup_rate_idx(ah, sband);
8a63facc 419
e0d687bd 420 ath5k_debug_dump_bands(ah);
fa1c114f 421
fa1c114f
JS		 422 return 0;
423}
424
8a63facc
BC		 425/*
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
429 *
e0d687bd 430 * Called with ah->lock.
8a63facc 431 */
cd2c5486 432int
e0d687bd 433ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
8a63facc 434{
e0d687bd 435 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8a63facc 436 "channel set, resetting (%u -> %u MHz)\n",
e0d687bd 437 ah->curchan->center_freq, chan->center_freq);
8a63facc 438
8451d22d 439 /*
8a63facc
BC		 440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
8451d22d 444 */
e0d687bd 445 return ath5k_reset(ah, chan, true);
fa1c114f 446}
fa1c114f 447
e4b0b32a 448void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
b1ae1edf 449{
e4b0b32a 450 struct ath5k_vif_iter_data *iter_data = data;
b1ae1edf 451 int i;
62c58fb4 452 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 453
454 if (iter_data->hw_macaddr)
455 for (i = 0; i < ETH_ALEN; i++)
456 iter_data->mask[i] &=
457 ~(iter_data->hw_macaddr[i] ^ mac[i]);
458
459 if (!iter_data->found_active) {
460 iter_data->found_active = true;
461 memcpy(iter_data->active_mac, mac, ETH_ALEN);
462 }
463
464 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
465 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
466 iter_data->need_set_hw_addr = false;
467
468 if (!iter_data->any_assoc) {
b1ae1edf
BG		 469 if (avf->assoc)
470 iter_data->any_assoc = true;
471 }
62c58fb4
BG		 472
473 /* Calculate combined mode - when APs are active, operate in AP mode.
474 * Otherwise use the mode of the new interface. This can currently
475 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 476 * interfaces is allowed.
62c58fb4
BG		 477 */
478 if (avf->opmode == NL80211_IFTYPE_AP)
479 iter_data->opmode = NL80211_IFTYPE_AP;
e4b0b32a
BG		 480 else {
481 if (avf->opmode == NL80211_IFTYPE_STATION)
482 iter_data->n_stas++;
62c58fb4
BG		 483 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
484 iter_data->opmode = avf->opmode;
e4b0b32a 485 }
b1ae1edf
BG		 486}
487
cd2c5486 488void
e0d687bd 489ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
cd2c5486 490 struct ieee80211_vif *vif)
b1ae1edf 491{
e0d687bd 492 struct ath_common *common = ath5k_hw_common(ah);
e4b0b32a
BG		 493 struct ath5k_vif_iter_data iter_data;
494 u32 rfilt;
b1ae1edf
BG		 495
496 /*
497 * Use the hardware MAC address as reference, the hardware uses it
498 * together with the BSSID mask when matching addresses.
499 */
500 iter_data.hw_macaddr = common->macaddr;
501 memset(&iter_data.mask, 0xff, ETH_ALEN);
502 iter_data.found_active = false;
503 iter_data.need_set_hw_addr = true;
62c58fb4 504 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
e4b0b32a 505 iter_data.n_stas = 0;
b1ae1edf
BG		 506
507 if (vif)
e4b0b32a 508 ath5k_vif_iter(&iter_data, vif->addr, vif);
b1ae1edf
BG		 509
510 /* Get list of all active MAC addresses */
e0d687bd 511 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
b1ae1edf 512 &iter_data);
e0d687bd 513 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
b1ae1edf 514
e0d687bd
PR		 515 ah->opmode = iter_data.opmode;
516 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
62c58fb4 517 /* Nothing active, default to station mode */
e0d687bd 518 ah->opmode = NL80211_IFTYPE_STATION;
62c58fb4 519
e0d687bd
PR		 520 ath5k_hw_set_opmode(ah, ah->opmode);
521 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
522 ah->opmode, ath_opmode_to_string(ah->opmode));
62c58fb4 523
b1ae1edf 524 if (iter_data.need_set_hw_addr && iter_data.found_active)
e0d687bd 525 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
b1ae1edf 526
e0d687bd
PR		 527 if (ath5k_hw_hasbssidmask(ah))
528 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
b1ae1edf 529
e4b0b32a
BG		 530 /* Set up RX Filter */
531 if (iter_data.n_stas > 1) {
532 /* If you have multiple STA interfaces connected to
533 * different APs, ARPs are not received (most of the time?)
6a2a0e73 534 * Enabling PROMISC appears to fix that problem.
e4b0b32a 535 */
e0d687bd 536 ah->filter_flags |= AR5K_RX_FILTER_PROM;
e4b0b32a 537 }
fa1c114f 538
e0d687bd
PR		 539 rfilt = ah->filter_flags;
540 ath5k_hw_set_rx_filter(ah, rfilt);
541 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
8a63facc 542}
fa1c114f 543
8a63facc 544static inline int
e0d687bd 545ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
8a63facc
BC		 546{
547 int rix;
fa1c114f 548
8a63facc
BC		 549 /* return base rate on errors */
550 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
551 "hw_rix out of bounds: %x\n", hw_rix))
552 return 0;
553
e0d687bd 554 rix = ah->rate_idx[ah->curchan->band][hw_rix];
8a63facc
BC		 555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
556 rix = 0;
557
558 return rix;
559}
560
561/***************\
562* Buffers setup *
563\***************/
564
565static
e0d687bd 566struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
8a63facc 567{
e0d687bd 568 struct ath_common *common = ath5k_hw_common(ah);
8a63facc 569 struct sk_buff *skb;
fa1c114f
JS		 570
571 /*
8a63facc
BC		 572 * Allocate buffer with headroom_needed space for the
573 * fake physical layer header at the start.
fa1c114f 574 */
8a63facc
BC		 575 skb = ath_rxbuf_alloc(common,
576 common->rx_bufsize,
577 GFP_ATOMIC);
fa1c114f 578
8a63facc 579 if (!skb) {
e0d687bd 580 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
8a63facc
BC		 581 common->rx_bufsize);
582 return NULL;
fa1c114f
JS		 583 }
584
e0d687bd 585 *skb_addr = dma_map_single(ah->dev,
8a63facc 586 skb->data, common->rx_bufsize,
aeae4ac9
FF		 587 DMA_FROM_DEVICE);
588
e0d687bd
PR		 589 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
590 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
8a63facc
BC		 591 dev_kfree_skb(skb);
592 return NULL;
0e149cf5 593 }
8a63facc
BC		 594 return skb;
595}
0e149cf5 596
8a63facc 597static int
e0d687bd 598ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
8a63facc 599{
8a63facc
BC		 600 struct sk_buff *skb = bf->skb;
601 struct ath5k_desc *ds;
602 int ret;
fa1c114f 603
8a63facc 604 if (!skb) {
e0d687bd 605 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
8a63facc
BC		 606 if (!skb)
607 return -ENOMEM;
608 bf->skb = skb;
f769c36b
BC		 609 }
610
8a63facc
BC		 611 /*
612 * Setup descriptors. For receive we always terminate
613 * the descriptor list with a self-linked entry so we'll
614 * not get overrun under high load (as can happen with a
615 * 5212 when ANI processing enables PHY error frames).
616 *
617 * To ensure the last descriptor is self-linked we create
618 * each descriptor as self-linked and add it to the end. As
619 * each additional descriptor is added the previous self-linked
620 * entry is "fixed" naturally. This should be safe even
621 * if DMA is happening. When processing RX interrupts we
622 * never remove/process the last, self-linked, entry on the
623 * descriptor list. This ensures the hardware always has
624 * someplace to write a new frame.
625 */
626 ds = bf->desc;
627 ds->ds_link = bf->daddr; /* link to self */
628 ds->ds_data = bf->skbaddr;
629 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 630 if (ret) {
e0d687bd 631 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
8a63facc 632 return ret;
fa1c114f
JS		 633 }
634
e0d687bd
PR		 635 if (ah->rxlink != NULL)
636 *ah->rxlink = bf->daddr;
637 ah->rxlink = &ds->ds_link;
fa1c114f 638 return 0;
fa1c114f
JS		 639}
640
8a63facc 641static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 642{
8a63facc
BC		 643 struct ieee80211_hdr *hdr;
644 enum ath5k_pkt_type htype;
645 __le16 fc;
fa1c114f 646
8a63facc
BC		 647 hdr = (struct ieee80211_hdr *)skb->data;
648 fc = hdr->frame_control;
fa1c114f 649
8a63facc
BC		 650 if (ieee80211_is_beacon(fc))
651 htype = AR5K_PKT_TYPE_BEACON;
652 else if (ieee80211_is_probe_resp(fc))
653 htype = AR5K_PKT_TYPE_PROBE_RESP;
654 else if (ieee80211_is_atim(fc))
655 htype = AR5K_PKT_TYPE_ATIM;
656 else if (ieee80211_is_pspoll(fc))
657 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 658 else
8a63facc 659 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 660
8a63facc 661 return htype;
42639fcd
BC		 662}
663
8a63facc 664static int
e0d687bd 665ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
8a63facc 666 struct ath5k_txq *txq, int padsize)
fa1c114f 667{
8a63facc
BC		 668 struct ath5k_desc *ds = bf->desc;
669 struct sk_buff *skb = bf->skb;
670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
671 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
672 struct ieee80211_rate *rate;
673 unsigned int mrr_rate[3], mrr_tries[3];
674 int i, ret;
675 u16 hw_rate;
676 u16 cts_rate = 0;
677 u16 duration = 0;
678 u8 rc_flags;
fa1c114f 679
8a63facc 680 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 681
8a63facc 682 /* XXX endianness */
e0d687bd 683 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
aeae4ac9 684 DMA_TO_DEVICE);
fa1c114f 685
e0d687bd 686 rate = ieee80211_get_tx_rate(ah->hw, info);
29ad2fac
JL		 687 if (!rate) {
688 ret = -EINVAL;
689 goto err_unmap;
690 }
fa1c114f 691
8a63facc
BC		 692 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
693 flags |= AR5K_TXDESC_NOACK;
fa1c114f 694
8a63facc
BC		 695 rc_flags = info->control.rates[0].flags;
696 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
697 rate->hw_value_short : rate->hw_value;
42639fcd 698
8a63facc
BC		 699 pktlen = skb->len;
700
701 /* FIXME: If we are in g mode and rate is a CCK rate
702 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
703 * from tx power (value is in dB units already) */
704 if (info->control.hw_key) {
705 keyidx = info->control.hw_key->hw_key_idx;
706 pktlen += info->control.hw_key->icv_len;
707 }
708 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
709 flags |= AR5K_TXDESC_RTSENA;
e0d687bd
PR		 710 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
711 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
b1ae1edf 712 info->control.vif, pktlen, info));
8a63facc
BC		 713 }
714 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
715 flags |= AR5K_TXDESC_CTSENA;
e0d687bd
PR		 716 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
717 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
b1ae1edf 718 info->control.vif, pktlen, info));
8a63facc
BC		 719 }
720 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
721 ieee80211_get_hdrlen_from_skb(skb), padsize,
722 get_hw_packet_type(skb),
e0d687bd 723 (ah->power_level * 2),
8a63facc
BC		 724 hw_rate,
725 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
726 cts_rate, duration);
727 if (ret)
728 goto err_unmap;
729
730 memset(mrr_rate, 0, sizeof(mrr_rate));
731 memset(mrr_tries, 0, sizeof(mrr_tries));
732 for (i = 0; i < 3; i++) {
e0d687bd 733 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
8a63facc 734 if (!rate)
400ec45a 735 break;
fa1c114f 736
8a63facc
BC		 737 mrr_rate[i] = rate->hw_value;
738 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 739 }
740
8a63facc
BC		 741 ath5k_hw_setup_mrr_tx_desc(ah, ds,
742 mrr_rate[0], mrr_tries[0],
743 mrr_rate[1], mrr_tries[1],
744 mrr_rate[2], mrr_tries[2]);
fa1c114f 745
8a63facc
BC		 746 ds->ds_link = 0;
747 ds->ds_data = bf->skbaddr;
63266a65 748
8a63facc
BC		 749 spin_lock_bh(&txq->lock);
750 list_add_tail(&bf->list, &txq->q);
925e0b06 751 txq->txq_len++;
8a63facc
BC		 752 if (txq->link == NULL) /* is this first packet? */
753 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
754 else /* no, so only link it */
755 *txq->link = bf->daddr;
63266a65 756
8a63facc
BC		 757 txq->link = &ds->ds_link;
758 ath5k_hw_start_tx_dma(ah, txq->qnum);
759 mmiowb();
760 spin_unlock_bh(&txq->lock);
761
762 return 0;
763err_unmap:
e0d687bd 764 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 765 return ret;
63266a65
BR		 766}
767
8a63facc
BC		 768/*******************\
769* Descriptors setup *
770\*******************/
771
d8ee398d 772static int
e0d687bd 773ath5k_desc_alloc(struct ath5k_hw *ah)
fa1c114f 774{
8a63facc
BC		 775 struct ath5k_desc *ds;
776 struct ath5k_buf *bf;
777 dma_addr_t da;
778 unsigned int i;
779 int ret;
d8ee398d 780
8a63facc 781 /* allocate descriptors */
e0d687bd 782 ah->desc_len = sizeof(struct ath5k_desc) *
8a63facc 783 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9 784
e0d687bd
PR		 785 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
786 &ah->desc_daddr, GFP_KERNEL);
787 if (ah->desc == NULL) {
788 ATH5K_ERR(ah, "can't allocate descriptors\n");
8a63facc
BC		 789 ret = -ENOMEM;
790 goto err;
791 }
e0d687bd
PR		 792 ds = ah->desc;
793 da = ah->desc_daddr;
794 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
795 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
fa1c114f 796
8a63facc
BC		 797 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
798 sizeof(struct ath5k_buf), GFP_KERNEL);
799 if (bf == NULL) {
e0d687bd 800 ATH5K_ERR(ah, "can't allocate bufptr\n");
8a63facc
BC		 801 ret = -ENOMEM;
802 goto err_free;
803 }
e0d687bd 804 ah->bufptr = bf;
fa1c114f 805
e0d687bd 806 INIT_LIST_HEAD(&ah->rxbuf);
8a63facc
BC		 807 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
808 bf->desc = ds;
809 bf->daddr = da;
e0d687bd 810 list_add_tail(&bf->list, &ah->rxbuf);
8a63facc 811 }
d8ee398d 812
e0d687bd
PR		 813 INIT_LIST_HEAD(&ah->txbuf);
814 ah->txbuf_len = ATH_TXBUF;
e4bbf2f5 815 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
8a63facc
BC		 816 bf->desc = ds;
817 bf->daddr = da;
e0d687bd 818 list_add_tail(&bf->list, &ah->txbuf);
fa1c114f
JS		 819 }
820
b1ae1edf 821 /* beacon buffers */
e0d687bd 822 INIT_LIST_HEAD(&ah->bcbuf);
b1ae1edf
BG		 823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
824 bf->desc = ds;
825 bf->daddr = da;
e0d687bd 826 list_add_tail(&bf->list, &ah->bcbuf);
b1ae1edf 827 }
fa1c114f 828
8a63facc
BC		 829 return 0;
830err_free:
e0d687bd 831 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
8a63facc 832err:
e0d687bd 833 ah->desc = NULL;
8a63facc
BC		 834 return ret;
835}
fa1c114f 836
cd2c5486 837void
e0d687bd 838ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
cd2c5486
BR		 839{
840 BUG_ON(!bf);
841 if (!bf->skb)
842 return;
e0d687bd 843 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
cd2c5486
BR		 844 DMA_TO_DEVICE);
845 dev_kfree_skb_any(bf->skb);
846 bf->skb = NULL;
847 bf->skbaddr = 0;
848 bf->desc->ds_data = 0;
849}
850
851void
e0d687bd 852ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
cd2c5486 853{
cd2c5486
BR		 854 struct ath_common *common = ath5k_hw_common(ah);
855
856 BUG_ON(!bf);
857 if (!bf->skb)
858 return;
e0d687bd 859 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
cd2c5486
BR		 860 DMA_FROM_DEVICE);
861 dev_kfree_skb_any(bf->skb);
862 bf->skb = NULL;
863 bf->skbaddr = 0;
864 bf->desc->ds_data = 0;
865}
866
8a63facc 867static void
e0d687bd 868ath5k_desc_free(struct ath5k_hw *ah)
8a63facc
BC		 869{
870 struct ath5k_buf *bf;
d8ee398d 871
e0d687bd
PR		 872 list_for_each_entry(bf, &ah->txbuf, list)
873 ath5k_txbuf_free_skb(ah, bf);
874 list_for_each_entry(bf, &ah->rxbuf, list)
875 ath5k_rxbuf_free_skb(ah, bf);
876 list_for_each_entry(bf, &ah->bcbuf, list)
877 ath5k_txbuf_free_skb(ah, bf);
d8ee398d 878
8a63facc 879 /* Free memory associated with all descriptors */
e0d687bd
PR		 880 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
881 ah->desc = NULL;
882 ah->desc_daddr = 0;
d8ee398d 883
e0d687bd
PR		 884 kfree(ah->bufptr);
885 ah->bufptr = NULL;
fa1c114f
JS		 886}
887
8a63facc
BC		 888
889/**************\
890* Queues setup *
891\**************/
892
893static struct ath5k_txq *
e0d687bd 894ath5k_txq_setup(struct ath5k_hw *ah,
8a63facc 895 int qtype, int subtype)
fa1c114f 896{
8a63facc
BC		 897 struct ath5k_txq *txq;
898 struct ath5k_txq_info qi = {
899 .tqi_subtype = subtype,
de8af455
BR		 900 /* XXX: default values not correct for B and XR channels,
901 * but who cares? */
902 .tqi_aifs = AR5K_TUNE_AIFS,
903 .tqi_cw_min = AR5K_TUNE_CWMIN,
904 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 905 };
906 int qnum;
d8ee398d 907
e30eb4ab 908 /*
8a63facc
BC		 909 * Enable interrupts only for EOL and DESC conditions.
910 * We mark tx descriptors to receive a DESC interrupt
911 * when a tx queue gets deep; otherwise we wait for the
912 * EOL to reap descriptors. Note that this is done to
913 * reduce interrupt load and this only defers reaping
914 * descriptors, never transmitting frames. Aside from
915 * reducing interrupts this also permits more concurrency.
916 * The only potential downside is if the tx queue backs
917 * up in which case the top half of the kernel may backup
918 * due to a lack of tx descriptors.
e30eb4ab 919 */
8a63facc
BC		 920 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
921 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
922 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
923 if (qnum < 0) {
924 /*
925 * NB: don't print a message, this happens
926 * normally on parts with too few tx queues
927 */
928 return ERR_PTR(qnum);
929 }
e0d687bd
PR		 930 if (qnum >= ARRAY_SIZE(ah->txqs)) {
931 ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
932 qnum, ARRAY_SIZE(ah->txqs));
8a63facc
BC		 933 ath5k_hw_release_tx_queue(ah, qnum);
934 return ERR_PTR(-EINVAL);
935 }
e0d687bd 936 txq = &ah->txqs[qnum];
8a63facc
BC		 937 if (!txq->setup) {
938 txq->qnum = qnum;
939 txq->link = NULL;
940 INIT_LIST_HEAD(&txq->q);
941 spin_lock_init(&txq->lock);
942 txq->setup = true;
925e0b06 943 txq->txq_len = 0;
81266baf 944 txq->txq_max = ATH5K_TXQ_LEN_MAX;
4edd761f 945 txq->txq_poll_mark = false;
923e5b3d 946 txq->txq_stuck = 0;
8a63facc 947 }
e0d687bd 948 return &ah->txqs[qnum];
fa1c114f
JS		 949}
950
8a63facc
BC		 951static int
952ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 953{
8a63facc 954 struct ath5k_txq_info qi = {
de8af455
BR		 955 /* XXX: default values not correct for B and XR channels,
956 * but who cares? */
957 .tqi_aifs = AR5K_TUNE_AIFS,
958 .tqi_cw_min = AR5K_TUNE_CWMIN,
959 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 960 /* NB: for dynamic turbo, don't enable any other interrupts */
961 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
962 };
d8ee398d 963
8a63facc 964 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 965}
966
8a63facc 967static int
e0d687bd 968ath5k_beaconq_config(struct ath5k_hw *ah)
fa1c114f 969{
8a63facc
BC		 970 struct ath5k_txq_info qi;
971 int ret;
fa1c114f 972
e0d687bd 973 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
8a63facc
BC		 974 if (ret)
975 goto err;
fa1c114f 976
e0d687bd
PR		 977 if (ah->opmode == NL80211_IFTYPE_AP ||
978 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
8a63facc
BC		 979 /*
980 * Always burst out beacon and CAB traffic
981 * (aifs = cwmin = cwmax = 0)
982 */
983 qi.tqi_aifs = 0;
984 qi.tqi_cw_min = 0;
985 qi.tqi_cw_max = 0;
e0d687bd 986 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
8a63facc
BC		 987 /*
988 * Adhoc mode; backoff between 0 and (2 * cw_min).
989 */
990 qi.tqi_aifs = 0;
991 qi.tqi_cw_min = 0;
de8af455 992 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 993 }
fa1c114f 994
e0d687bd 995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 996 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
997 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 998
e0d687bd 999 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
8a63facc 1000 if (ret) {
e0d687bd 1001 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
8a63facc
BC		 1002 "hardware queue!\n", __func__);
1003 goto err;
1004 }
e0d687bd 1005 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
8a63facc
BC		 1006 if (ret)
1007 goto err;
b7266047 1008
8a63facc
BC		 1009 /* reconfigure cabq with ready time to 80% of beacon_interval */
1010 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1011 if (ret)
1012 goto err;
b7266047 1013
e0d687bd 1014 qi.tqi_ready_time = (ah->bintval * 80) / 100;
8a63facc
BC		 1015 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1016 if (ret)
1017 goto err;
b7266047 1018
8a63facc
BC		 1019 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1020err:
1021 return ret;
d8ee398d
LR		 1022}
1023
80dac9ee
NK		 1024/**
1025 * ath5k_drain_tx_buffs - Empty tx buffers
1026 *
e0d687bd 1027 * @ah The &struct ath5k_hw
80dac9ee
NK		 1028 *
1029 * Empty tx buffers from all queues in preparation
1030 * of a reset or during shutdown.
1031 *
1032 * NB: this assumes output has been stopped and
1033 * we do not need to block ath5k_tx_tasklet
1034 */
8a63facc 1035static void
e0d687bd 1036ath5k_drain_tx_buffs(struct ath5k_hw *ah)
8a63facc 1037{
80dac9ee 1038 struct ath5k_txq *txq;
8a63facc 1039 struct ath5k_buf *bf, *bf0;
80dac9ee 1040 int i;
b6ea0356 1041
e0d687bd
PR		 1042 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1043 if (ah->txqs[i].setup) {
1044 txq = &ah->txqs[i];
80dac9ee
NK		 1045 spin_lock_bh(&txq->lock);
1046 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
e0d687bd 1047 ath5k_debug_printtxbuf(ah, bf);
b6ea0356 1048
e0d687bd 1049 ath5k_txbuf_free_skb(ah, bf);
fa1c114f 1050
e0d687bd
PR		 1051 spin_lock_bh(&ah->txbuflock);
1052 list_move_tail(&bf->list, &ah->txbuf);
1053 ah->txbuf_len++;
80dac9ee 1054 txq->txq_len--;
e0d687bd 1055 spin_unlock_bh(&ah->txbuflock);
8a63facc 1056 }
80dac9ee
NK		 1057 txq->link = NULL;
1058 txq->txq_poll_mark = false;
1059 spin_unlock_bh(&txq->lock);
1060 }
0452d4a5 1061 }
fa1c114f
JS		 1062}
1063
8a63facc 1064static void
e0d687bd 1065ath5k_txq_release(struct ath5k_hw *ah)
2ac2927a 1066{
e0d687bd 1067 struct ath5k_txq *txq = ah->txqs;
8a63facc 1068 unsigned int i;
2ac2927a 1069
e0d687bd 1070 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
8a63facc 1071 if (txq->setup) {
e0d687bd 1072 ath5k_hw_release_tx_queue(ah, txq->qnum);
8a63facc
BC		 1073 txq->setup = false;
1074 }
1075}
2ac2927a 1076
2ac2927a 1077
8a63facc
BC		 1078/*************\
1079* RX Handling *
1080\*************/
2ac2927a 1081
8a63facc
BC		 1082/*
1083 * Enable the receive h/w following a reset.
1084 */
fa1c114f 1085static int
e0d687bd 1086ath5k_rx_start(struct ath5k_hw *ah)
fa1c114f 1087{
8a63facc
BC		 1088 struct ath_common *common = ath5k_hw_common(ah);
1089 struct ath5k_buf *bf;
1090 int ret;
fa1c114f 1091
8a63facc 1092 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1093
e0d687bd 1094 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
8a63facc 1095 common->cachelsz, common->rx_bufsize);
2f7fe870 1096
e0d687bd
PR		 1097 spin_lock_bh(&ah->rxbuflock);
1098 ah->rxlink = NULL;
1099 list_for_each_entry(bf, &ah->rxbuf, list) {
1100 ret = ath5k_rxbuf_setup(ah, bf);
8a63facc 1101 if (ret != 0) {
e0d687bd 1102 spin_unlock_bh(&ah->rxbuflock);
8a63facc
BC		 1103 goto err;
1104 }
2f7fe870 1105 }
e0d687bd 1106 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
8a63facc 1107 ath5k_hw_set_rxdp(ah, bf->daddr);
e0d687bd 1108 spin_unlock_bh(&ah->rxbuflock);
2f7fe870 1109
8a63facc 1110 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
e0d687bd 1111 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
8a63facc 1112 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1113
1114 return 0;
8a63facc 1115err:
fa1c114f
JS		 1116 return ret;
1117}
1118
8a63facc 1119/*
80dac9ee
NK		 1120 * Disable the receive logic on PCU (DRU)
1121 * In preparation for a shutdown.
1122 *
1123 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1124 * does.
8a63facc
BC		 1125 */
1126static void
e0d687bd 1127ath5k_rx_stop(struct ath5k_hw *ah)
fa1c114f 1128{
fa1c114f 1129
8a63facc 1130 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1131 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1132
e0d687bd 1133 ath5k_debug_printrxbuffs(ah);
8a63facc 1134}
fa1c114f 1135
8a63facc 1136static unsigned int
e0d687bd 1137ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc
BC		 1138 struct ath5k_rx_status *rs)
1139{
8a63facc
BC		 1140 struct ath_common *common = ath5k_hw_common(ah);
1141 struct ieee80211_hdr *hdr = (void *)skb->data;
1142 unsigned int keyix, hlen;
fa1c114f 1143
8a63facc
BC		 1144 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1145 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1146 return RX_FLAG_DECRYPTED;
fa1c114f 1147
8a63facc
BC		 1148 /* Apparently when a default key is used to decrypt the packet
1149 the hw does not set the index used to decrypt. In such cases
1150 get the index from the packet. */
1151 hlen = ieee80211_hdrlen(hdr->frame_control);
1152 if (ieee80211_has_protected(hdr->frame_control) &&
1153 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1154 skb->len >= hlen + 4) {
1155 keyix = skb->data[hlen + 3] >> 6;
1156
1157 if (test_bit(keyix, common->keymap))
1158 return RX_FLAG_DECRYPTED;
1159 }
fa1c114f
JS		 1160
1161 return 0;
fa1c114f
JS		 1162}
1163
8a63facc 1164
fa1c114f 1165static void
e0d687bd 1166ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc 1167 struct ieee80211_rx_status *rxs)
fa1c114f 1168{
e0d687bd 1169 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1170 u64 tsf, bc_tstamp;
1171 u32 hw_tu;
1172 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1173
8a63facc
BC		 1174 if (ieee80211_is_beacon(mgmt->frame_control) &&
1175 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1176 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1177 /*
1178 * Received an IBSS beacon with the same BSSID. Hardware *must*
1179 * have updated the local TSF. We have to work around various
1180 * hardware bugs, though...
1181 */
e0d687bd 1182 tsf = ath5k_hw_get_tsf64(ah);
8a63facc
BC		 1183 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1184 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1185
e0d687bd 1186 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1187 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1188 (unsigned long long)bc_tstamp,
1189 (unsigned long long)rxs->mactime,
1190 (unsigned long long)(rxs->mactime - bc_tstamp),
1191 (unsigned long long)tsf);
fa1c114f 1192
8a63facc
BC		 1193 /*
1194 * Sometimes the HW will give us a wrong tstamp in the rx
1195 * status, causing the timestamp extension to go wrong.
1196 * (This seems to happen especially with beacon frames bigger
1197 * than 78 byte (incl. FCS))
1198 * But we know that the receive timestamp must be later than the
1199 * timestamp of the beacon since HW must have synced to that.
1200 *
1201 * NOTE: here we assume mactime to be after the frame was
1202 * received, not like mac80211 which defines it at the start.
1203 */
1204 if (bc_tstamp > rxs->mactime) {
e0d687bd 1205 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1206 "fixing mactime from %llx to %llx\n",
1207 (unsigned long long)rxs->mactime,
1208 (unsigned long long)tsf);
1209 rxs->mactime = tsf;
1210 }
fa1c114f 1211
8a63facc
BC		 1212 /*
1213 * Local TSF might have moved higher than our beacon timers,
1214 * in that case we have to update them to continue sending
1215 * beacons. This also takes care of synchronizing beacon sending
1216 * times with other stations.
1217 */
e0d687bd
PR		 1218 if (hw_tu >= ah->nexttbtt)
1219 ath5k_beacon_update_timers(ah, bc_tstamp);
7f896126
BR		 1220
1221 /* Check if the beacon timers are still correct, because a TSF
1222 * update might have created a window between them - for a
1223 * longer description see the comment of this function: */
e0d687bd
PR		 1224 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1225 ath5k_beacon_update_timers(ah, bc_tstamp);
1226 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
7f896126
BR		 1227 "fixed beacon timers after beacon receive\n");
1228 }
8a63facc
BC		 1229 }
1230}
fa1c114f 1231
8a63facc 1232static void
e0d687bd 1233ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
8a63facc
BC		 1234{
1235 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
8a63facc 1236 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1237
8a63facc
BC		 1238 /* only beacons from our BSSID */
1239 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1240 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1241 return;
fa1c114f 1242
eef39bef 1243 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1244
8a63facc
BC		 1245 /* in IBSS mode we should keep RSSI statistics per neighbour */
1246 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1247}
fa1c114f 1248
8a63facc
BC		 1249/*
1250 * Compute padding position. skb must contain an IEEE 802.11 frame
1251 */
1252static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1253{
e4bbf2f5 1254 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8a63facc
BC		 1255 __le16 frame_control = hdr->frame_control;
1256 int padpos = 24;
fa1c114f 1257
d2c7f773 1258 if (ieee80211_has_a4(frame_control))
8a63facc 1259 padpos += ETH_ALEN;
d2c7f773
PR		 1260
1261 if (ieee80211_is_data_qos(frame_control))
8a63facc 1262 padpos += IEEE80211_QOS_CTL_LEN;
8a63facc
BC		 1263
1264 return padpos;
fa1c114f
JS		 1265}
1266
8a63facc
BC		 1267/*
1268 * This function expects an 802.11 frame and returns the number of
1269 * bytes added, or -1 if we don't have enough header room.
1270 */
1271static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1272{
8a63facc
BC		 1273 int padpos = ath5k_common_padpos(skb);
1274 int padsize = padpos & 3;
fa1c114f 1275
e4bbf2f5 1276 if (padsize && skb->len > padpos) {
fa1c114f 1277
8a63facc
BC		 1278 if (skb_headroom(skb) < padsize)
1279 return -1;
fa1c114f 1280
8a63facc 1281 skb_push(skb, padsize);
e4bbf2f5 1282 memmove(skb->data, skb->data + padsize, padpos);
8a63facc
BC		 1283 return padsize;
1284 }
a951ae21 1285
8a63facc
BC		 1286 return 0;
1287}
fa1c114f 1288
8a63facc
BC		 1289/*
1290 * The MAC header is padded to have 32-bit boundary if the
1291 * packet payload is non-zero. The general calculation for
1292 * padsize would take into account odd header lengths:
1293 * padsize = 4 - (hdrlen & 3); however, since only
1294 * even-length headers are used, padding can only be 0 or 2
1295 * bytes and we can optimize this a bit. We must not try to
1296 * remove padding from short control frames that do not have a
1297 * payload.
1298 *
1299 * This function expects an 802.11 frame and returns the number of
1300 * bytes removed.
1301 */
1302static int ath5k_remove_padding(struct sk_buff *skb)
1303{
1304 int padpos = ath5k_common_padpos(skb);
1305 int padsize = padpos & 3;
6d91e1d8 1306
e4bbf2f5 1307 if (padsize && skb->len >= padpos + padsize) {
8a63facc
BC		 1308 memmove(skb->data + padsize, skb->data, padpos);
1309 skb_pull(skb, padsize);
1310 return padsize;
fa1c114f 1311 }
a951ae21 1312
8a63facc 1313 return 0;
fa1c114f
JS		 1314}
1315
1316static void
e0d687bd 1317ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc 1318 struct ath5k_rx_status *rs)
fa1c114f 1319{
8a63facc
BC		 1320 struct ieee80211_rx_status *rxs;
1321
1322 ath5k_remove_padding(skb);
1323
1324 rxs = IEEE80211_SKB_RXCB(skb);
1325
1326 rxs->flag = 0;
1327 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1328 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1329
1330 /*
8a63facc
BC		 1331 * always extend the mac timestamp, since this information is
1332 * also needed for proper IBSS merging.
1333 *
1334 * XXX: it might be too late to do it here, since rs_tstamp is
1335 * 15bit only. that means TSF extension has to be done within
1336 * 32768usec (about 32ms). it might be necessary to move this to
1337 * the interrupt handler, like it is done in madwifi.
1338 *
1339 * Unfortunately we don't know when the hardware takes the rx
1340 * timestamp (beginning of phy frame, data frame, end of rx?).
1341 * The only thing we know is that it is hardware specific...
1342 * On AR5213 it seems the rx timestamp is at the end of the
6a2a0e73 1343 * frame, but I'm not sure.
8a63facc
BC		 1344 *
1345 * NOTE: mac80211 defines mactime at the beginning of the first
1346 * data symbol. Since we don't have any time references it's
1347 * impossible to comply to that. This affects IBSS merge only
1348 * right now, so it's not too bad...
fa1c114f 1349 */
e0d687bd 1350 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
6ebacbb7 1351 rxs->flag |= RX_FLAG_MACTIME_MPDU;
fa1c114f 1352
e0d687bd
PR		 1353 rxs->freq = ah->curchan->center_freq;
1354 rxs->band = ah->curchan->band;
fa1c114f 1355
e0d687bd 1356 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1357
8a63facc 1358 rxs->antenna = rs->rs_antenna;
fa1c114f 1359
8a63facc 1360 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
e0d687bd 1361 ah->stats.antenna_rx[rs->rs_antenna]++;
8a63facc 1362 else
e0d687bd 1363 ah->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1364
e0d687bd
PR		 1365 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1366 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
fa1c114f 1367
8a63facc 1368 if (rxs->rate_idx >= 0 && rs->rs_rate ==
e0d687bd 1369 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1370 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1371
e0d687bd 1372 trace_ath5k_rx(ah, skb);
fa1c114f 1373
e0d687bd 1374 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
fa1c114f 1375
8a63facc 1376 /* check beacons in IBSS mode */
e0d687bd
PR		 1377 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1378 ath5k_check_ibss_tsf(ah, skb, rxs);
fa1c114f 1379
e0d687bd 1380 ieee80211_rx(ah->hw, skb);
8a63facc 1381}
fa1c114f 1382
8a63facc
BC		 1383/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1384 *
1385 * Check if we want to further process this frame or not. Also update
1386 * statistics. Return true if we want this frame, false if not.
fa1c114f 1387 */
8a63facc 1388static bool
e0d687bd 1389ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
fa1c114f 1390{
e0d687bd
PR		 1391 ah->stats.rx_all_count++;
1392 ah->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1393
8a63facc
BC		 1394 if (unlikely(rs->rs_status)) {
1395 if (rs->rs_status & AR5K_RXERR_CRC)
e0d687bd 1396 ah->stats.rxerr_crc++;
8a63facc 1397 if (rs->rs_status & AR5K_RXERR_FIFO)
e0d687bd 1398 ah->stats.rxerr_fifo++;
8a63facc 1399 if (rs->rs_status & AR5K_RXERR_PHY) {
e0d687bd 1400 ah->stats.rxerr_phy++;
8a63facc 1401 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
e0d687bd 1402 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
8a63facc
BC		 1403 return false;
1404 }
1405 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1406 /*
1407 * Decrypt error. If the error occurred
1408 * because there was no hardware key, then
1409 * let the frame through so the upper layers
1410 * can process it. This is necessary for 5210
1411 * parts which have no way to setup a ``clear''
1412 * key cache entry.
1413 *
1414 * XXX do key cache faulting
1415 */
e0d687bd 1416 ah->stats.rxerr_decrypt++;
8a63facc
BC		 1417 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1418 !(rs->rs_status & AR5K_RXERR_CRC))
1419 return true;
1420 }
1421 if (rs->rs_status & AR5K_RXERR_MIC) {
e0d687bd 1422 ah->stats.rxerr_mic++;
8a63facc 1423 return true;
fa1c114f 1424 }
fa1c114f 1425
8a63facc
BC		 1426 /* reject any frames with non-crypto errors */
1427 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1428 return false;
1429 }
fa1c114f 1430
8a63facc 1431 if (unlikely(rs->rs_more)) {
e0d687bd 1432 ah->stats.rxerr_jumbo++;
8a63facc
BC		 1433 return false;
1434 }
1435 return true;
fa1c114f
JS		 1436}
1437
c266c71a 1438static void
e0d687bd 1439ath5k_set_current_imask(struct ath5k_hw *ah)
c266c71a 1440{
4fc5401c 1441 enum ath5k_int imask;
c266c71a
FF		 1442 unsigned long flags;
1443
e0d687bd
PR		 1444 spin_lock_irqsave(&ah->irqlock, flags);
1445 imask = ah->imask;
1446 if (ah->rx_pending)
c266c71a 1447 imask &= ~AR5K_INT_RX_ALL;
e0d687bd 1448 if (ah->tx_pending)
c266c71a 1449 imask &= ~AR5K_INT_TX_ALL;
e0d687bd
PR		 1450 ath5k_hw_set_imr(ah, imask);
1451 spin_unlock_irqrestore(&ah->irqlock, flags);
c266c71a
FF		 1452}
1453
fa1c114f 1454static void
8a63facc 1455ath5k_tasklet_rx(unsigned long data)
fa1c114f 1456{
8a63facc
BC		 1457 struct ath5k_rx_status rs = {};
1458 struct sk_buff *skb, *next_skb;
1459 dma_addr_t next_skb_addr;
e0d687bd 1460 struct ath5k_hw *ah = (void *)data;
dc1e001b 1461 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1462 struct ath5k_buf *bf;
1463 struct ath5k_desc *ds;
1464 int ret;
fa1c114f 1465
e0d687bd
PR		 1466 spin_lock(&ah->rxbuflock);
1467 if (list_empty(&ah->rxbuf)) {
1468 ATH5K_WARN(ah, "empty rx buf pool\n");
8a63facc
BC		 1469 goto unlock;
1470 }
1471 do {
e0d687bd 1472 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
8a63facc
BC		 1473 BUG_ON(bf->skb == NULL);
1474 skb = bf->skb;
1475 ds = bf->desc;
fa1c114f 1476
8a63facc 1477 /* bail if HW is still using self-linked descriptor */
e0d687bd 1478 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
8a63facc 1479 break;
fa1c114f 1480
e0d687bd 1481 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
8a63facc
BC		 1482 if (unlikely(ret == -EINPROGRESS))
1483 break;
1484 else if (unlikely(ret)) {
e0d687bd
PR		 1485 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1486 ah->stats.rxerr_proc++;
8a63facc
BC		 1487 break;
1488 }
fa1c114f 1489
e0d687bd
PR		 1490 if (ath5k_receive_frame_ok(ah, &rs)) {
1491 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
fa1c114f 1492
8a63facc
BC		 1493 /*
1494 * If we can't replace bf->skb with a new skb under
1495 * memory pressure, just skip this packet
1496 */
1497 if (!next_skb)
1498 goto next;
036cd1ec 1499
e0d687bd 1500 dma_unmap_single(ah->dev, bf->skbaddr,
8a63facc 1501 common->rx_bufsize,
aeae4ac9 1502 DMA_FROM_DEVICE);
036cd1ec 1503
8a63facc 1504 skb_put(skb, rs.rs_datalen);
6ba81c2c 1505
e0d687bd 1506 ath5k_receive_frame(ah, skb, &rs);
6ba81c2c 1507
8a63facc
BC		 1508 bf->skb = next_skb;
1509 bf->skbaddr = next_skb_addr;
036cd1ec 1510 }
8a63facc 1511next:
e0d687bd
PR		 1512 list_move_tail(&bf->list, &ah->rxbuf);
1513 } while (ath5k_rxbuf_setup(ah, bf) == 0);
8a63facc 1514unlock:
e0d687bd
PR		 1515 spin_unlock(&ah->rxbuflock);
1516 ah->rx_pending = false;
1517 ath5k_set_current_imask(ah);
036cd1ec
BR		 1518}
1519
b4ea449d 1520
8a63facc
BC		 1521/*************\
1522* TX Handling *
1523\*************/
b4ea449d 1524
7bb45683 1525void
cd2c5486
BR		 1526ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1527 struct ath5k_txq *txq)
8a63facc 1528{
e0d687bd 1529 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 1530 struct ath5k_buf *bf;
1531 unsigned long flags;
1532 int padsize;
b4ea449d 1533
e0d687bd 1534 trace_ath5k_tx(ah, skb, txq);
b4ea449d 1535
8a63facc
BC		 1536 /*
1537 * The hardware expects the header padded to 4 byte boundaries.
1538 * If this is not the case, we add the padding after the header.
1539 */
1540 padsize = ath5k_add_padding(skb);
1541 if (padsize < 0) {
e0d687bd 1542 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
8a63facc
BC		 1543 " headroom to pad");
1544 goto drop_packet;
1545 }
8127fbdc 1546
4e868796
FF		 1547 if (txq->txq_len >= txq->txq_max &&
1548 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
925e0b06
BR		 1549 ieee80211_stop_queue(hw, txq->qnum);
1550
e0d687bd
PR		 1551 spin_lock_irqsave(&ah->txbuflock, flags);
1552 if (list_empty(&ah->txbuf)) {
1553 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1554 spin_unlock_irqrestore(&ah->txbuflock, flags);
651d9375 1555 ieee80211_stop_queues(hw);
8a63facc 1556 goto drop_packet;
8127fbdc 1557 }
e0d687bd 1558 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
8a63facc 1559 list_del(&bf->list);
e0d687bd
PR		 1560 ah->txbuf_len--;
1561 if (list_empty(&ah->txbuf))
8a63facc 1562 ieee80211_stop_queues(hw);
e0d687bd 1563 spin_unlock_irqrestore(&ah->txbuflock, flags);
8a63facc
BC		 1564
1565 bf->skb = skb;
1566
e0d687bd 1567 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
8a63facc 1568 bf->skb = NULL;
e0d687bd
PR		 1569 spin_lock_irqsave(&ah->txbuflock, flags);
1570 list_add_tail(&bf->list, &ah->txbuf);
1571 ah->txbuf_len++;
1572 spin_unlock_irqrestore(&ah->txbuflock, flags);
8a63facc 1573 goto drop_packet;
8127fbdc 1574 }
7bb45683 1575 return;
8127fbdc 1576
8a63facc
BC		 1577drop_packet:
1578 dev_kfree_skb_any(skb);
8127fbdc
BP		 1579}
1580
1440401e 1581static void
e0d687bd 1582ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
0e472252 1583 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1440401e
BR		 1584{
1585 struct ieee80211_tx_info *info;
ed895085 1586 u8 tries[3];
1440401e
BR		 1587 int i;
1588
e0d687bd
PR		 1589 ah->stats.tx_all_count++;
1590 ah->stats.tx_bytes_count += skb->len;
1440401e
BR		 1591 info = IEEE80211_SKB_CB(skb);
1592
ed895085
FF		 1593 tries[0] = info->status.rates[0].count;
1594 tries[1] = info->status.rates[1].count;
1595 tries[2] = info->status.rates[2].count;
1596
1440401e 1597 ieee80211_tx_info_clear_status(info);
ed895085
FF		 1598
1599 for (i = 0; i < ts->ts_final_idx; i++) {
1440401e
BR		 1600 struct ieee80211_tx_rate *r =
1601 &info->status.rates[i];
1602
ed895085 1603 r->count = tries[i];
1440401e
BR		 1604 }
1605
ed895085 1606 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
6d7b97b2 1607 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1440401e
BR		 1608
1609 if (unlikely(ts->ts_status)) {
e0d687bd 1610 ah->stats.ack_fail++;
1440401e
BR		 1611 if (ts->ts_status & AR5K_TXERR_FILT) {
1612 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
e0d687bd 1613 ah->stats.txerr_filt++;
1440401e
BR		 1614 }
1615 if (ts->ts_status & AR5K_TXERR_XRETRY)
e0d687bd 1616 ah->stats.txerr_retry++;
1440401e 1617 if (ts->ts_status & AR5K_TXERR_FIFO)
e0d687bd 1618 ah->stats.txerr_fifo++;
1440401e
BR		 1619 } else {
1620 info->flags |= IEEE80211_TX_STAT_ACK;
1621 info->status.ack_signal = ts->ts_rssi;
6d7b97b2
FF		 1622
1623 /* count the successful attempt as well */
1624 info->status.rates[ts->ts_final_idx].count++;
1440401e
BR		 1625 }
1626
1627 /*
1628 * Remove MAC header padding before giving the frame
1629 * back to mac80211.
1630 */
1631 ath5k_remove_padding(skb);
1632
1633 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
e0d687bd 1634 ah->stats.antenna_tx[ts->ts_antenna]++;
1440401e 1635 else
e0d687bd 1636 ah->stats.antenna_tx[0]++; /* invalid */
1440401e 1637
e0d687bd
PR		 1638 trace_ath5k_tx_complete(ah, skb, txq, ts);
1639 ieee80211_tx_status(ah->hw, skb);
1440401e 1640}
8a63facc
BC		 1641
1642static void
e0d687bd 1643ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
8127fbdc 1644{
8a63facc
BC		 1645 struct ath5k_tx_status ts = {};
1646 struct ath5k_buf *bf, *bf0;
1647 struct ath5k_desc *ds;
1648 struct sk_buff *skb;
1440401e 1649 int ret;
8127fbdc 1650
8a63facc
BC		 1651 spin_lock(&txq->lock);
1652 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1653
1654 txq->txq_poll_mark = false;
1655
1656 /* skb might already have been processed last time. */
1657 if (bf->skb != NULL) {
1658 ds = bf->desc;
1659
e0d687bd 1660 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
23413296
BR		 1661 if (unlikely(ret == -EINPROGRESS))
1662 break;
1663 else if (unlikely(ret)) {
e0d687bd 1664 ATH5K_ERR(ah,
23413296
BR		 1665 "error %d while processing "
1666 "queue %u\n", ret, txq->qnum);
1667 break;
1668 }
1669
1670 skb = bf->skb;
1671 bf->skb = NULL;
aeae4ac9 1672
e0d687bd 1673 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
aeae4ac9 1674 DMA_TO_DEVICE);
e0d687bd 1675 ath5k_tx_frame_completed(ah, skb, txq, &ts);
23413296 1676 }
8127fbdc 1677
8a63facc
BC		 1678 /*
1679 * It's possible that the hardware can say the buffer is
1680 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1681 * host memory and moved on.
1682 * Always keep the last descriptor to avoid HW races...
8a63facc 1683 */
e0d687bd
PR		 1684 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1685 spin_lock(&ah->txbuflock);
1686 list_move_tail(&bf->list, &ah->txbuf);
1687 ah->txbuf_len++;
23413296 1688 txq->txq_len--;
e0d687bd 1689 spin_unlock(&ah->txbuflock);
8a63facc 1690 }
fa1c114f 1691 }
fa1c114f 1692 spin_unlock(&txq->lock);
4198a8d0 1693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
e0d687bd 1694 ieee80211_wake_queue(ah->hw, txq->qnum);
fa1c114f
JS		 1695}
1696
1697static void
1698ath5k_tasklet_tx(unsigned long data)
1699{
8784d2ee 1700 int i;
e0d687bd 1701 struct ath5k_hw *ah = (void *)data;
fa1c114f 1702
e4bbf2f5 1703 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
e0d687bd
PR		 1704 if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
1705 ath5k_tx_processq(ah, &ah->txqs[i]);
c266c71a 1706
e0d687bd
PR		 1707 ah->tx_pending = false;
1708 ath5k_set_current_imask(ah);
fa1c114f
JS		 1709}
1710
1711
fa1c114f
JS		 1712/*****************\
1713* Beacon handling *
1714\*****************/
1715
1716/*
1717 * Setup the beacon frame for transmit.
1718 */
1719static int
e0d687bd 1720ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
fa1c114f
JS		 1721{
1722 struct sk_buff *skb = bf->skb;
a888d52d 1723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1724 struct ath5k_desc *ds;
2bed03eb
NK		 1725 int ret = 0;
1726 u8 antenna;
fa1c114f 1727 u32 flags;
8127fbdc 1728 const int padsize = 0;
fa1c114f 1729
e0d687bd 1730 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
aeae4ac9 1731 DMA_TO_DEVICE);
e0d687bd 1732 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
fa1c114f
JS		 1733 "skbaddr %llx\n", skb, skb->data, skb->len,
1734 (unsigned long long)bf->skbaddr);
aeae4ac9 1735
e0d687bd
PR		 1736 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1737 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
fa1c114f
JS		 1738 return -EIO;
1739 }
1740
1741 ds = bf->desc;
2bed03eb 1742 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1743
1744 flags = AR5K_TXDESC_NOACK;
e0d687bd 1745 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1746 ds->ds_link = bf->daddr; /* self-linked */
1747 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1748 } else
fa1c114f 1749 ds->ds_link = 0;
2bed03eb
NK		 1750
1751 /*
1752 * If we use multiple antennas on AP and use
1753 * the Sectored AP scenario, switch antenna every
1754 * 4 beacons to make sure everybody hears our AP.
1755 * When a client tries to associate, hw will keep
1756 * track of the tx antenna to be used for this client
6a2a0e73 1757 * automatically, based on ACKed packets.
2bed03eb
NK		 1758 *
1759 * Note: AP still listens and transmits RTS on the
1760 * default antenna which is supposed to be an omni.
1761 *
1762 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1763 * multiple antennas (1 omni -- the default -- and 14
1764 * sectors), so if we choose to actually support this
1765 * mode, we need to allow the user to set how many antennas
1766 * we have and tweak the code below to send beacons
1767 * on all of them.
2bed03eb
NK		 1768 */
1769 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
e0d687bd 1770 antenna = ah->bsent & 4 ? 2 : 1;
2bed03eb 1771
fa1c114f 1772
8f655dde
NK		 1773 /* FIXME: If we are in g mode and rate is a CCK rate
1774 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1775 * from tx power (value is in dB units already) */
fa1c114f 1776 ds->ds_data = bf->skbaddr;
281c56dd 1777 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1778 ieee80211_get_hdrlen_from_skb(skb), padsize,
e0d687bd
PR		 1779 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
1780 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
2e92e6f2 1781 1, AR5K_TXKEYIX_INVALID,
400ec45a 1782 antenna, flags, 0, 0);
fa1c114f
JS		 1783 if (ret)
1784 goto err_unmap;
1785
1786 return 0;
1787err_unmap:
e0d687bd 1788 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1789 return ret;
1790}
1791
8a63facc
BC		 1792/*
1793 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1794 * this is called only once at config_bss time, for AP we do it every
1795 * SWBA interrupt so that the TIM will reflect buffered frames.
1796 *
1797 * Called with the beacon lock.
1798 */
cd2c5486 1799int
8a63facc
BC		 1800ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1801{
1802 int ret;
e0d687bd 1803 struct ath5k_hw *ah = hw->priv;
b1ae1edf 1804 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1805 struct sk_buff *skb;
1806
1807 if (WARN_ON(!vif)) {
1808 ret = -EINVAL;
1809 goto out;
1810 }
1811
1812 skb = ieee80211_beacon_get(hw, vif);
1813
1814 if (!skb) {
1815 ret = -ENOMEM;
1816 goto out;
1817 }
1818
e0d687bd 1819 ath5k_txbuf_free_skb(ah, avf->bbuf);
b1ae1edf 1820 avf->bbuf->skb = skb;
e0d687bd 1821 ret = ath5k_beacon_setup(ah, avf->bbuf);
8a63facc 1822 if (ret)
b1ae1edf 1823 avf->bbuf->skb = NULL;
8a63facc
BC		 1824out:
1825 return ret;
1826}
1827
fa1c114f
JS		 1828/*
1829 * Transmit a beacon frame at SWBA. Dynamic updates to the
1830 * frame contents are done as needed and the slot time is
1831 * also adjusted based on current state.
1832 *
5faaff74
BC		 1833 * This is called from software irq context (beacontq tasklets)
1834 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1835 */
1836static void
e0d687bd 1837ath5k_beacon_send(struct ath5k_hw *ah)
fa1c114f 1838{
b1ae1edf
BG		 1839 struct ieee80211_vif *vif;
1840 struct ath5k_vif *avf;
1841 struct ath5k_buf *bf;
cec8db23 1842 struct sk_buff *skb;
fa1c114f 1843
e0d687bd 1844 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1845
fa1c114f
JS		 1846 /*
1847 * Check if the previous beacon has gone out. If
a180a130 1848 * not, don't don't try to post another: skip this
fa1c114f
JS		 1849 * period and wait for the next. Missed beacons
1850 * indicate a problem and should not occur. If we
1851 * miss too many consecutive beacons reset the device.
1852 */
e0d687bd
PR		 1853 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1854 ah->bmisscount++;
1855 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1856 "missed %u consecutive beacons\n", ah->bmisscount);
1857 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1858 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
fa1c114f 1859 "stuck beacon time (%u missed)\n",
e0d687bd
PR		 1860 ah->bmisscount);
1861 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 1862 "stuck beacon, resetting\n");
e0d687bd 1863 ieee80211_queue_work(ah->hw, &ah->reset_work);
fa1c114f
JS		 1864 }
1865 return;
1866 }
e0d687bd
PR		 1867 if (unlikely(ah->bmisscount != 0)) {
1868 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
fa1c114f 1869 "resume beacon xmit after %u misses\n",
e0d687bd
PR		 1870 ah->bmisscount);
1871 ah->bmisscount = 0;
fa1c114f
JS		 1872 }
1873
e0d687bd
PR		 1874 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
1875 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1876 u64 tsf = ath5k_hw_get_tsf64(ah);
1877 u32 tsftu = TSF_TO_TU(tsf);
e0d687bd
PR		 1878 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1879 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1880 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
b1ae1edf 1881 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
e0d687bd 1882 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
b1ae1edf 1883 } else /* only one interface */
e0d687bd 1884 vif = ah->bslot[0];
b1ae1edf
BG		 1885
1886 if (!vif)
1887 return;
1888
1889 avf = (void *)vif->drv_priv;
1890 bf = avf->bbuf;
e0d687bd
PR		 1891 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1892 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1893 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
b1ae1edf
BG		 1894 return;
1895 }
1896
fa1c114f
JS		 1897 /*
1898 * Stop any current dma and put the new frame on the queue.
1899 * This should never fail since we check above that no frames
1900 * are still pending on the queue.
1901 */
e0d687bd
PR		 1902 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1903 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
fa1c114f
JS		 1904 /* NB: hw still stops DMA, so proceed */
1905 }
fa1c114f 1906
d82b577b 1907 /* refresh the beacon for AP or MESH mode */
e0d687bd
PR		 1908 if (ah->opmode == NL80211_IFTYPE_AP ||
1909 ah->opmode == NL80211_IFTYPE_MESH_POINT)
1910 ath5k_beacon_update(ah->hw, vif);
1071db86 1911
e0d687bd 1912 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
0e472252 1913
e0d687bd
PR		 1914 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1915 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1916 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1917 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
fa1c114f 1918
e0d687bd 1919 skb = ieee80211_get_buffered_bc(ah->hw, vif);
cec8db23 1920 while (skb) {
e0d687bd 1921 ath5k_tx_queue(ah->hw, skb, ah->cabq);
4e868796 1922
e0d687bd 1923 if (ah->cabq->txq_len >= ah->cabq->txq_max)
4e868796
FF		 1924 break;
1925
e0d687bd 1926 skb = ieee80211_get_buffered_bc(ah->hw, vif);
cec8db23
BC		 1927 }
1928
e0d687bd 1929 ah->bsent++;
fa1c114f
JS		 1930}
1931
9804b98d
BR		 1932/**
1933 * ath5k_beacon_update_timers - update beacon timers
1934 *
e0d687bd 1935 * @ah: struct ath5k_hw pointer we are operating on
9804b98d
BR		 1936 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1937 * beacon timer update based on the current HW TSF.
1938 *
1939 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1940 * of a received beacon or the current local hardware TSF and write it to the
1941 * beacon timer registers.
1942 *
1943 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1944 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1945 * when we otherwise know we have to update the timers, but we keep it in this
1946 * function to have it all together in one place.
1947 */
cd2c5486 1948void
e0d687bd 1949ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
fa1c114f 1950{
9804b98d
BR		 1951 u32 nexttbtt, intval, hw_tu, bc_tu;
1952 u64 hw_tsf;
fa1c114f 1953
e0d687bd
PR		 1954 intval = ah->bintval & AR5K_BEACON_PERIOD;
1955 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
b1ae1edf
BG		 1956 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1957 if (intval < 15)
e0d687bd 1958 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
b1ae1edf
BG		 1959 intval);
1960 }
fa1c114f
JS		 1961 if (WARN_ON(!intval))
1962 return;
1963
9804b98d
BR		 1964 /* beacon TSF converted to TU */
1965 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1966
9804b98d
BR		 1967 /* current TSF converted to TU */
1968 hw_tsf = ath5k_hw_get_tsf64(ah);
1969 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1970
633d006e 1971#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
11f21df3 1972 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
25985edc 1973 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
11f21df3
BR		 1974 * configuration we need to make sure it is bigger than that. */
1975
9804b98d
BR		 1976 if (bc_tsf == -1) {
1977 /*
1978 * no beacons received, called internally.
1979 * just need to refresh timers based on HW TSF.
1980 */
1981 nexttbtt = roundup(hw_tu + FUDGE, intval);
1982 } else if (bc_tsf == 0) {
1983 /*
1984 * no beacon received, probably called by ath5k_reset_tsf().
1985 * reset TSF to start with 0.
1986 */
1987 nexttbtt = intval;
1988 intval |= AR5K_BEACON_RESET_TSF;
1989 } else if (bc_tsf > hw_tsf) {
1990 /*
25985edc 1991 * beacon received, SW merge happened but HW TSF not yet updated.
9804b98d
BR		 1992 * not possible to reconfigure timers yet, but next time we
1993 * receive a beacon with the same BSSID, the hardware will
1994 * automatically update the TSF and then we need to reconfigure
1995 * the timers.
1996 */
e0d687bd 1997 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 1998 "need to wait for HW TSF sync\n");
1999 return;
2000 } else {
2001 /*
2002 * most important case for beacon synchronization between STA.
2003 *
2004 * beacon received and HW TSF has been already updated by HW.
2005 * update next TBTT based on the TSF of the beacon, but make
2006 * sure it is ahead of our local TSF timer.
2007 */
2008 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2009 }
2010#undef FUDGE
fa1c114f 2011
e0d687bd 2012 ah->nexttbtt = nexttbtt;
036cd1ec 2013
fa1c114f 2014 intval |= AR5K_BEACON_ENA;
fa1c114f 2015 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2016
2017 /*
2018 * debugging output last in order to preserve the time critical aspect
2019 * of this function
2020 */
2021 if (bc_tsf == -1)
e0d687bd 2022 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2023 "reconfigured timers based on HW TSF\n");
2024 else if (bc_tsf == 0)
e0d687bd 2025 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2026 "reset HW TSF and timers\n");
2027 else
e0d687bd 2028 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2029 "updated timers based on beacon TSF\n");
2030
e0d687bd 2031 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2032 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2033 (unsigned long long) bc_tsf,
2034 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
e0d687bd 2035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
9804b98d
BR		 2036 intval & AR5K_BEACON_PERIOD,
2037 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2038 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2039}
2040
036cd1ec
BR		 2041/**
2042 * ath5k_beacon_config - Configure the beacon queues and interrupts
2043 *
e0d687bd 2044 * @ah: struct ath5k_hw pointer we are operating on
fa1c114f 2045 *
036cd1ec 2046 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2047 * interrupts to detect TSF updates only.
fa1c114f 2048 */
cd2c5486 2049void
e0d687bd 2050ath5k_beacon_config(struct ath5k_hw *ah)
fa1c114f 2051{
b5f03956 2052 unsigned long flags;
fa1c114f 2053
e0d687bd
PR		 2054 spin_lock_irqsave(&ah->block, flags);
2055 ah->bmisscount = 0;
2056 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2057
e0d687bd 2058 if (ah->enable_beacon) {
fa1c114f 2059 /*
036cd1ec
BR		 2060 * In IBSS mode we use a self-linked tx descriptor and let the
2061 * hardware send the beacons automatically. We have to load it
fa1c114f 2062 * only once here.
036cd1ec 2063 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2064 * timers in order to detect automatic TSF updates.
fa1c114f 2065 */
e0d687bd 2066 ath5k_beaconq_config(ah);
fa1c114f 2067
e0d687bd 2068 ah->imask |= AR5K_INT_SWBA;
036cd1ec 2069
e0d687bd 2070 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2071 if (ath5k_hw_hasveol(ah))
e0d687bd 2072 ath5k_beacon_send(ah);
da966bca 2073 } else
e0d687bd 2074 ath5k_beacon_update_timers(ah, -1);
21800491 2075 } else {
e0d687bd 2076 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
fa1c114f 2077 }
fa1c114f 2078
e0d687bd 2079 ath5k_hw_set_imr(ah, ah->imask);
21800491 2080 mmiowb();
e0d687bd 2081 spin_unlock_irqrestore(&ah->block, flags);
fa1c114f
JS		 2082}
2083
428cbd4f
NK		 2084static void ath5k_tasklet_beacon(unsigned long data)
2085{
e0d687bd 2086 struct ath5k_hw *ah = (struct ath5k_hw *) data;
428cbd4f
NK		 2087
2088 /*
2089 * Software beacon alert--time to send a beacon.
2090 *
2091 * In IBSS mode we use this interrupt just to
2092 * keep track of the next TBTT (target beacon
6a2a0e73 2093 * transmission time) in order to detect whether
428cbd4f
NK		 2094 * automatic TSF updates happened.
2095 */
e0d687bd 2096 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
6a2a0e73 2097 /* XXX: only if VEOL supported */
e0d687bd
PR		 2098 u64 tsf = ath5k_hw_get_tsf64(ah);
2099 ah->nexttbtt += ah->bintval;
2100 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
428cbd4f
NK		 2101 "SWBA nexttbtt: %x hw_tu: %x "
2102 "TSF: %llx\n",
e0d687bd 2103 ah->nexttbtt,
428cbd4f
NK		 2104 TSF_TO_TU(tsf),
2105 (unsigned long long) tsf);
2106 } else {
e0d687bd
PR		 2107 spin_lock(&ah->block);
2108 ath5k_beacon_send(ah);
2109 spin_unlock(&ah->block);
428cbd4f
NK		 2110 }
2111}
2112
fa1c114f
JS		 2113
2114/********************\
2115* Interrupt handling *
2116\********************/
2117
6a8a3f6b
BR		 2118static void
2119ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2120{
2111ac0d
BR		 2121 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2122 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2123 /* run ANI only when full calibration is not active */
2124 ah->ah_cal_next_ani = jiffies +
2125 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
e0d687bd 2126 tasklet_schedule(&ah->ani_tasklet);
2111ac0d
BR		 2127
2128 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2129 ah->ah_cal_next_full = jiffies +
2130 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
e0d687bd 2131 tasklet_schedule(&ah->calib);
6a8a3f6b
BR		 2132 }
2133 /* we could use SWI to generate enough interrupts to meet our
2134 * calibration interval requirements, if necessary:
2135 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2136}
2137
c266c71a 2138static void
e0d687bd 2139ath5k_schedule_rx(struct ath5k_hw *ah)
c266c71a 2140{
e0d687bd
PR		 2141 ah->rx_pending = true;
2142 tasklet_schedule(&ah->rxtq);
c266c71a
FF		 2143}
2144
2145static void
e0d687bd 2146ath5k_schedule_tx(struct ath5k_hw *ah)
c266c71a 2147{
e0d687bd
PR		 2148 ah->tx_pending = true;
2149 tasklet_schedule(&ah->txtq);
c266c71a
FF		 2150}
2151
f5cbc8ba 2152static irqreturn_t
fa1c114f
JS		 2153ath5k_intr(int irq, void *dev_id)
2154{
e0d687bd 2155 struct ath5k_hw *ah = dev_id;
fa1c114f
JS		 2156 enum ath5k_int status;
2157 unsigned int counter = 1000;
2158
e0d687bd 2159 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
4cebb34c
FF		 2160 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2161 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2162 return IRQ_NONE;
2163
2164 do {
fa1c114f 2165 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
e0d687bd
PR		 2166 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2167 status, ah->imask);
fa1c114f
JS		 2168 if (unlikely(status & AR5K_INT_FATAL)) {
2169 /*
2170 * Fatal errors are unrecoverable.
2171 * Typically these are caused by DMA errors.
2172 */
e0d687bd 2173 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 2174 "fatal int, resetting\n");
e0d687bd 2175 ieee80211_queue_work(ah->hw, &ah->reset_work);
fa1c114f 2176 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2177 /*
2178 * Receive buffers are full. Either the bus is busy or
2179 * the CPU is not fast enough to process all received
2180 * frames.
2181 * Older chipsets need a reset to come out of this
2182 * condition, but we treat it as RX for newer chips.
2183 * We don't know exactly which versions need a reset -
2184 * this guess is copied from the HAL.
2185 */
e0d687bd 2186 ah->stats.rxorn_intr++;
8d67a031 2187 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
e0d687bd 2188 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 2189 "rx overrun, resetting\n");
e0d687bd 2190 ieee80211_queue_work(ah->hw, &ah->reset_work);
d2c7f773 2191 } else
e0d687bd 2192 ath5k_schedule_rx(ah);
fa1c114f 2193 } else {
d2c7f773 2194 if (status & AR5K_INT_SWBA)
e0d687bd 2195 tasklet_hi_schedule(&ah->beacontq);
d2c7f773 2196
fa1c114f
JS		 2197 if (status & AR5K_INT_RXEOL) {
2198 /*
2199 * NB: the hardware should re-read the link when
2200 * RXE bit is written, but it doesn't work at
2201 * least on older hardware revs.
2202 */
e0d687bd 2203 ah->stats.rxeol_intr++;
fa1c114f
JS		 2204 }
2205 if (status & AR5K_INT_TXURN) {
2206 /* bump tx trigger level */
2207 ath5k_hw_update_tx_triglevel(ah, true);
2208 }
4c674c60 2209 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
e0d687bd 2210 ath5k_schedule_rx(ah);
4c674c60
NK		 2211 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2212 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
e0d687bd 2213 ath5k_schedule_tx(ah);
fa1c114f 2214 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2215 /* TODO */
fa1c114f
JS		 2216 }
2217 if (status & AR5K_INT_MIB) {
e0d687bd 2218 ah->stats.mib_intr++;
495391d7 2219 ath5k_hw_update_mib_counters(ah);
2111ac0d 2220 ath5k_ani_mib_intr(ah);
fa1c114f 2221 }
e6a3b616 2222 if (status & AR5K_INT_GPIO)
e0d687bd 2223 tasklet_schedule(&ah->rf_kill.toggleq);
a6ae0716 2224
fa1c114f 2225 }
4cebb34c
FF		 2226
2227 if (ath5k_get_bus_type(ah) == ATH_AHB)
2228 break;
2229
2516baa6 2230 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f 2231
e0d687bd
PR		 2232 if (ah->rx_pending || ah->tx_pending)
2233 ath5k_set_current_imask(ah);
c266c71a 2234
fa1c114f 2235 if (unlikely(!counter))
e0d687bd 2236 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
fa1c114f 2237
6a8a3f6b 2238 ath5k_intr_calibration_poll(ah);
6e220662 2239
fa1c114f
JS		 2240 return IRQ_HANDLED;
2241}
2242
fa1c114f
JS		 2243/*
2244 * Periodically recalibrate the PHY to account
2245 * for temperature/environment changes.
2246 */
2247static void
6e220662 2248ath5k_tasklet_calibrate(unsigned long data)
fa1c114f 2249{
e0d687bd 2250 struct ath5k_hw *ah = (void *)data;
fa1c114f 2251
6e220662 2252 /* Only full calibration for now */
e65e1d77 2253 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2254
e0d687bd
PR		 2255 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2256 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2257 ah->curchan->hw_value);
fa1c114f 2258
6f3b414a 2259 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2260 /*
2261 * Rfgain is out of bounds, reset the chip
2262 * to load new gain values.
2263 */
e0d687bd
PR		 2264 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2265 ieee80211_queue_work(ah->hw, &ah->reset_work);
fa1c114f 2266 }
e0d687bd
PR		 2267 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2268 ATH5K_ERR(ah, "calibration of channel %u failed\n",
400ec45a 2269 ieee80211_frequency_to_channel(
e0d687bd 2270 ah->curchan->center_freq));
fa1c114f 2271
0e8e02dd 2272 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2273 * doesn't.
2274 * TODO: We should stop TX here, so that it doesn't interfere.
2275 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2276 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2277 ah->ah_cal_next_nf = jiffies +
2278 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2279 ath5k_hw_update_noise_floor(ah);
afe86286 2280 }
6e220662 2281
e65e1d77 2282 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2283}
2284
2285
2111ac0d
BR		 2286static void
2287ath5k_tasklet_ani(unsigned long data)
2288{
e0d687bd 2289 struct ath5k_hw *ah = (void *)data;
2111ac0d
BR		 2290
2291 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2292 ath5k_ani_calibration(ah);
2293 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2294}
2295
2296
4edd761f
BR		 2297static void
2298ath5k_tx_complete_poll_work(struct work_struct *work)
2299{
e0d687bd 2300 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
4edd761f
BR		 2301 tx_complete_work.work);
2302 struct ath5k_txq *txq;
2303 int i;
2304 bool needreset = false;
2305
e0d687bd 2306 mutex_lock(&ah->lock);
599b13ad 2307
e0d687bd
PR		 2308 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2309 if (ah->txqs[i].setup) {
2310 txq = &ah->txqs[i];
4edd761f 2311 spin_lock_bh(&txq->lock);
23413296 2312 if (txq->txq_len > 1) {
4edd761f 2313 if (txq->txq_poll_mark) {
e0d687bd 2314 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
4edd761f
BR		 2315 "TX queue stuck %d\n",
2316 txq->qnum);
2317 needreset = true;
923e5b3d 2318 txq->txq_stuck++;
4edd761f
BR		 2319 spin_unlock_bh(&txq->lock);
2320 break;
2321 } else {
2322 txq->txq_poll_mark = true;
2323 }
2324 }
2325 spin_unlock_bh(&txq->lock);
2326 }
2327 }
2328
2329 if (needreset) {
e0d687bd 2330 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
4edd761f 2331 "TX queues stuck, resetting\n");
e0d687bd 2332 ath5k_reset(ah, NULL, true);
4edd761f
BR		 2333 }
2334
e0d687bd 2335 mutex_unlock(&ah->lock);
599b13ad 2336
e0d687bd 2337 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
4edd761f
BR		 2338 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2339}
2340
2341
8a63facc
BC		 2342/*************************\
2343* Initialization routines *
2344\*************************/
fa1c114f 2345
25380d80 2346int __devinit
e0d687bd 2347ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
132b1c3e 2348{
e0d687bd 2349 struct ieee80211_hw *hw = ah->hw;
132b1c3e
FF		 2350 struct ath_common *common;
2351 int ret;
2352 int csz;
2353
2354 /* Initialize driver private data */
e0d687bd 2355 SET_IEEE80211_DEV(hw, ah->dev);
132b1c3e 2356 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2357 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2358 IEEE80211_HW_SIGNAL_DBM |
2359 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2360
2361 hw->wiphy->interface_modes =
2362 BIT(NL80211_IFTYPE_AP) |
2363 BIT(NL80211_IFTYPE_STATION) |
2364 BIT(NL80211_IFTYPE_ADHOC) |
2365 BIT(NL80211_IFTYPE_MESH_POINT);
2366
3de135db
BR		 2367 /* both antennas can be configured as RX or TX */
2368 hw->wiphy->available_antennas_tx = 0x3;
2369 hw->wiphy->available_antennas_rx = 0x3;
2370
132b1c3e
FF		 2371 hw->extra_tx_headroom = 2;
2372 hw->channel_change_time = 5000;
2373
2374 /*
2375 * Mark the device as detached to avoid processing
2376 * interrupts until setup is complete.
2377 */
e0d687bd 2378 __set_bit(ATH_STAT_INVALID, ah->status);
132b1c3e 2379
e0d687bd
PR		 2380 ah->opmode = NL80211_IFTYPE_STATION;
2381 ah->bintval = 1000;
2382 mutex_init(&ah->lock);
2383 spin_lock_init(&ah->rxbuflock);
2384 spin_lock_init(&ah->txbuflock);
2385 spin_lock_init(&ah->block);
2386 spin_lock_init(&ah->irqlock);
132b1c3e
FF		 2387
2388 /* Setup interrupt handler */
e0d687bd 2389 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
132b1c3e 2390 if (ret) {
e0d687bd 2391 ATH5K_ERR(ah, "request_irq failed\n");
132b1c3e
FF		 2392 goto err;
2393 }
2394
e0d687bd 2395 common = ath5k_hw_common(ah);
132b1c3e
FF		 2396 common->ops = &ath5k_common_ops;
2397 common->bus_ops = bus_ops;
e0d687bd 2398 common->ah = ah;
132b1c3e 2399 common->hw = hw;
e0d687bd 2400 common->priv = ah;
26d16d23 2401 common->clockrate = 40;
132b1c3e
FF		 2402
2403 /*
2404 * Cache line size is used to size and align various
2405 * structures used to communicate with the hardware.
2406 */
2407 ath5k_read_cachesize(common, &csz);
2408 common->cachelsz = csz << 2; /* convert to bytes */
2409
2410 spin_lock_init(&common->cc_lock);
2411
2412 /* Initialize device */
e0d687bd 2413 ret = ath5k_hw_init(ah);
132b1c3e 2414 if (ret)
e0d687bd 2415 goto err_irq;
132b1c3e
FF		 2416
2417 /* set up multi-rate retry capabilities */
e0d687bd 2418 if (ah->ah_version == AR5K_AR5212) {
132b1c3e 2419 hw->max_rates = 4;
76a9f6fd
BR		 2420 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2421 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2422 }
2423
2424 hw->vif_data_size = sizeof(struct ath5k_vif);
2425
2426 /* Finish private driver data initialization */
2427 ret = ath5k_init(hw);
2428 if (ret)
2429 goto err_ah;
2430
e0d687bd
PR		 2431 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2432 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2433 ah->ah_mac_srev,
2434 ah->ah_phy_revision);
132b1c3e 2435
e0d687bd 2436 if (!ah->ah_single_chip) {
132b1c3e 2437 /* Single chip radio (!RF5111) */
e0d687bd
PR		 2438 if (ah->ah_radio_5ghz_revision &&
2439 !ah->ah_radio_2ghz_revision) {
132b1c3e
FF		 2440 /* No 5GHz support -> report 2GHz radio */
2441 if (!test_bit(AR5K_MODE_11A,
e0d687bd
PR		 2442 ah->ah_capabilities.cap_mode)) {
2443 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
132b1c3e 2444 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2445 ah->ah_radio_5ghz_revision),
2446 ah->ah_radio_5ghz_revision);
132b1c3e 2447 /* No 2GHz support (5110 and some
6a2a0e73 2448 * 5GHz only cards) -> report 5GHz radio */
132b1c3e 2449 } else if (!test_bit(AR5K_MODE_11B,
e0d687bd
PR		 2450 ah->ah_capabilities.cap_mode)) {
2451 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
132b1c3e 2452 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2453 ah->ah_radio_5ghz_revision),
2454 ah->ah_radio_5ghz_revision);
132b1c3e
FF		 2455 /* Multiband radio */
2456 } else {
e0d687bd 2457 ATH5K_INFO(ah, "RF%s multiband radio found"
132b1c3e
FF		 2458 " (0x%x)\n",
2459 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2460 ah->ah_radio_5ghz_revision),
2461 ah->ah_radio_5ghz_revision);
132b1c3e
FF		 2462 }
2463 }
2464 /* Multi chip radio (RF5111 - RF2111) ->
2465 * report both 2GHz/5GHz radios */
e0d687bd
PR		 2466 else if (ah->ah_radio_5ghz_revision &&
2467 ah->ah_radio_2ghz_revision) {
2468 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
132b1c3e 2469 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2470 ah->ah_radio_5ghz_revision),
2471 ah->ah_radio_5ghz_revision);
2472 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
132b1c3e 2473 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2474 ah->ah_radio_2ghz_revision),
2475 ah->ah_radio_2ghz_revision);
132b1c3e
FF		 2476 }
2477 }
2478
e0d687bd 2479 ath5k_debug_init_device(ah);
132b1c3e
FF		 2480
2481 /* ready to process interrupts */
e0d687bd 2482 __clear_bit(ATH_STAT_INVALID, ah->status);
132b1c3e
FF		 2483
2484 return 0;
2485err_ah:
e0d687bd 2486 ath5k_hw_deinit(ah);
132b1c3e 2487err_irq:
e0d687bd 2488 free_irq(ah->irq, ah);
132b1c3e
FF		 2489err:
2490 return ret;
2491}
2492
fa1c114f 2493static int
e0d687bd 2494ath5k_stop_locked(struct ath5k_hw *ah)
cec8db23 2495{
cec8db23 2496
e0d687bd
PR		 2497 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2498 test_bit(ATH_STAT_INVALID, ah->status));
8a63facc
BC		 2499
2500 /*
2501 * Shutdown the hardware and driver:
2502 * stop output from above
2503 * disable interrupts
2504 * turn off timers
2505 * turn off the radio
2506 * clear transmit machinery
2507 * clear receive machinery
2508 * drain and release tx queues
2509 * reclaim beacon resources
2510 * power down hardware
2511 *
2512 * Note that some of this work is not possible if the
2513 * hardware is gone (invalid).
2514 */
e0d687bd 2515 ieee80211_stop_queues(ah->hw);
8a63facc 2516
e0d687bd
PR		 2517 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2518 ath5k_led_off(ah);
8a63facc 2519 ath5k_hw_set_imr(ah, 0);
e0d687bd
PR		 2520 synchronize_irq(ah->irq);
2521 ath5k_rx_stop(ah);
80dac9ee 2522 ath5k_hw_dma_stop(ah);
e0d687bd 2523 ath5k_drain_tx_buffs(ah);
8a63facc
BC		 2524 ath5k_hw_phy_disable(ah);
2525 }
2526
2527 return 0;
cec8db23
BC		 2528}
2529
fabba048 2530int ath5k_start(struct ieee80211_hw *hw)
fa1c114f 2531{
fabba048 2532 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2533 struct ath_common *common = ath5k_hw_common(ah);
2534 int ret, i;
fa1c114f 2535
e0d687bd 2536 mutex_lock(&ah->lock);
8a63facc 2537
e0d687bd 2538 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
fa1c114f 2539
fa1c114f 2540 /*
8a63facc
BC		 2541 * Stop anything previously setup. This is safe
2542 * no matter this is the first time through or not.
fa1c114f 2543 */
e0d687bd 2544 ath5k_stop_locked(ah);
fa1c114f 2545
8a63facc
BC		 2546 /*
2547 * The basic interface to setting the hardware in a good
2548 * state is ``reset''. On return the hardware is known to
2549 * be powered up and with interrupts disabled. This must
2550 * be followed by initialization of the appropriate bits
2551 * and then setup of the interrupt mask.
2552 */
e0d687bd
PR		 2553 ah->curchan = ah->hw->conf.channel;
2554 ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
8a63facc
BC		 2555 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2556 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2557
e0d687bd 2558 ret = ath5k_reset(ah, NULL, false);
8a63facc
BC		 2559 if (ret)
2560 goto done;
fa1c114f 2561
8a63facc
BC		 2562 ath5k_rfkill_hw_start(ah);
2563
2564 /*
2565 * Reset the key cache since some parts do not reset the
2566 * contents on initial power up or resume from suspend.
2567 */
2568 for (i = 0; i < common->keymax; i++)
2569 ath_hw_keyreset(common, (u16) i);
2570
61cde037
NK		 2571 /* Use higher rates for acks instead of base
2572 * rate */
2573 ah->ah_ack_bitrate_high = true;
b1ae1edf 2574
e0d687bd
PR		 2575 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2576 ah->bslot[i] = NULL;
b1ae1edf 2577
8a63facc
BC		 2578 ret = 0;
2579done:
2580 mmiowb();
e0d687bd 2581 mutex_unlock(&ah->lock);
4edd761f 2582
e0d687bd 2583 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
4edd761f
BR		 2584 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2585
8a63facc
BC		 2586 return ret;
2587}
2588
e0d687bd 2589static void ath5k_stop_tasklets(struct ath5k_hw *ah)
8a63facc 2590{
e0d687bd
PR		 2591 ah->rx_pending = false;
2592 ah->tx_pending = false;
2593 tasklet_kill(&ah->rxtq);
2594 tasklet_kill(&ah->txtq);
2595 tasklet_kill(&ah->calib);
2596 tasklet_kill(&ah->beacontq);
2597 tasklet_kill(&ah->ani_tasklet);
8a63facc
BC		 2598}
2599
2600/*
2601 * Stop the device, grabbing the top-level lock to protect
2602 * against concurrent entry through ath5k_init (which can happen
2603 * if another thread does a system call and the thread doing the
2604 * stop is preempted).
2605 */
fabba048 2606void ath5k_stop(struct ieee80211_hw *hw)
8a63facc 2607{
fabba048 2608 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2609 int ret;
2610
e0d687bd
PR		 2611 mutex_lock(&ah->lock);
2612 ret = ath5k_stop_locked(ah);
2613 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
8a63facc
BC		 2614 /*
2615 * Don't set the card in full sleep mode!
2616 *
2617 * a) When the device is in this state it must be carefully
2618 * woken up or references to registers in the PCI clock
2619 * domain may freeze the bus (and system). This varies
2620 * by chip and is mostly an issue with newer parts
2621 * (madwifi sources mentioned srev >= 0x78) that go to
2622 * sleep more quickly.
2623 *
2624 * b) On older chips full sleep results a weird behaviour
2625 * during wakeup. I tested various cards with srev < 0x78
2626 * and they don't wake up after module reload, a second
2627 * module reload is needed to bring the card up again.
2628 *
2629 * Until we figure out what's going on don't enable
2630 * full chip reset on any chip (this is what Legacy HAL
2631 * and Sam's HAL do anyway). Instead Perform a full reset
2632 * on the device (same as initial state after attach) and
2633 * leave it idle (keep MAC/BB on warm reset) */
e0d687bd 2634 ret = ath5k_hw_on_hold(ah);
8a63facc 2635
e0d687bd 2636 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8a63facc 2637 "putting device to sleep\n");
fa1c114f
JS		 2638 }
2639
8a63facc 2640 mmiowb();
e0d687bd 2641 mutex_unlock(&ah->lock);
8a63facc 2642
e0d687bd 2643 ath5k_stop_tasklets(ah);
4edd761f 2644
e0d687bd 2645 cancel_delayed_work_sync(&ah->tx_complete_work);
8a63facc 2646
e0d687bd 2647 ath5k_rfkill_hw_stop(ah);
fa1c114f
JS		 2648}
2649
209d889b
BC		 2650/*
2651 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2652 * and change to the given channel.
5faaff74 2653 *
e0d687bd 2654 * This should be called with ah->lock.
209d889b 2655 */
fa1c114f 2656static int
e0d687bd 2657ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
8aec7af9 2658 bool skip_pcu)
fa1c114f 2659{
f15a4bb2 2660 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2661 int ret, ani_mode;
a99168ee 2662 bool fast;
fa1c114f 2663
e0d687bd 2664 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2665
450464de 2666 ath5k_hw_set_imr(ah, 0);
e0d687bd
PR		 2667 synchronize_irq(ah->irq);
2668 ath5k_stop_tasklets(ah);
450464de 2669
25985edc 2670 /* Save ani mode and disable ANI during
344b54b9
NK		 2671 * reset. If we don't we might get false
2672 * PHY error interrupts. */
e0d687bd 2673 ani_mode = ah->ani_state.ani_mode;
344b54b9
NK		 2674 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2675
19252ecb
NK		 2676 /* We are going to empty hw queues
2677 * so we should also free any remaining
2678 * tx buffers */
e0d687bd 2679 ath5k_drain_tx_buffs(ah);
930a7622 2680 if (chan)
e0d687bd 2681 ah->curchan = chan;
a99168ee
NK		 2682
2683 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2684
e0d687bd 2685 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
d7dc1003 2686 if (ret) {
e0d687bd 2687 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
fa1c114f
JS		 2688 goto err;
2689 }
d7dc1003 2690
e0d687bd 2691 ret = ath5k_rx_start(ah);
d7dc1003 2692 if (ret) {
e0d687bd 2693 ATH5K_ERR(ah, "can't start recv logic\n");
fa1c114f
JS		 2694 goto err;
2695 }
d7dc1003 2696
344b54b9 2697 ath5k_ani_init(ah, ani_mode);
2111ac0d 2698
fe00deb3 2699 ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100);
ac559526 2700 ah->ah_cal_next_ani = jiffies;
afe86286 2701 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2702 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2703
f15a4bb2 2704 /* clear survey data and cycle counters */
e0d687bd 2705 memset(&ah->survey, 0, sizeof(ah->survey));
bb007554 2706 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2707 ath_hw_cycle_counters_update(common);
2708 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2709 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2710 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2711
fa1c114f 2712 /*
d7dc1003
JS		 2713 * Change channels and update the h/w rate map if we're switching;
2714 * e.g. 11a to 11b/g.
2715 *
2716 * We may be doing a reset in response to an ioctl that changes the
2717 * channel so update any state that might change as a result.
fa1c114f
JS		 2718 *
2719 * XXX needed?
2720 */
e0d687bd 2721/* ath5k_chan_change(ah, c); */
fa1c114f 2722
e0d687bd 2723 ath5k_beacon_config(ah);
d7dc1003 2724 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2725
e0d687bd 2726 ieee80211_wake_queues(ah->hw);
397f385b 2727
fa1c114f
JS		 2728 return 0;
2729err:
2730 return ret;
2731}
2732
5faaff74
BC		 2733static void ath5k_reset_work(struct work_struct *work)
2734{
e0d687bd 2735 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
5faaff74
BC		 2736 reset_work);
2737
e0d687bd
PR		 2738 mutex_lock(&ah->lock);
2739 ath5k_reset(ah, NULL, true);
2740 mutex_unlock(&ah->lock);
5faaff74
BC		 2741}
2742
25380d80 2743static int __devinit
132b1c3e 2744ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2745{
132b1c3e 2746
e0d687bd 2747 struct ath5k_hw *ah = hw->priv;
8a63facc 2748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2749 struct ath5k_txq *txq;
8a63facc 2750 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2751 int ret;
2752
fa1c114f 2753
8a63facc
BC		 2754 /*
2755 * Check if the MAC has multi-rate retry support.
2756 * We do this by trying to setup a fake extended
2757 * descriptor. MACs that don't have support will
2758 * return false w/o doing anything. MACs that do
2759 * support it will return true w/o doing anything.
2760 */
2761 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2762
8a63facc
BC		 2763 if (ret < 0)
2764 goto err;
2765 if (ret > 0)
e0d687bd 2766 __set_bit(ATH_STAT_MRRETRY, ah->status);
ccfe5552 2767
8a63facc
BC		 2768 /*
2769 * Collect the channel list. The 802.11 layer
6a2a0e73 2770 * is responsible for filtering this list based
8a63facc
BC		 2771 * on settings like the phy mode and regulatory
2772 * domain restrictions.
2773 */
2774 ret = ath5k_setup_bands(hw);
2775 if (ret) {
e0d687bd 2776 ATH5K_ERR(ah, "can't get channels\n");
8a63facc
BC		 2777 goto err;
2778 }
67d2e2df 2779
8a63facc
BC		 2780 /*
2781 * Allocate tx+rx descriptors and populate the lists.
2782 */
e0d687bd 2783 ret = ath5k_desc_alloc(ah);
8a63facc 2784 if (ret) {
e0d687bd 2785 ATH5K_ERR(ah, "can't allocate descriptors\n");
8a63facc
BC		 2786 goto err;
2787 }
fa1c114f 2788
8a63facc
BC		 2789 /*
2790 * Allocate hardware transmit queues: one queue for
2791 * beacon frames and one data queue for each QoS
2792 * priority. Note that hw functions handle resetting
2793 * these queues at the needed time.
2794 */
2795 ret = ath5k_beaconq_setup(ah);
2796 if (ret < 0) {
e0d687bd 2797 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
8a63facc
BC		 2798 goto err_desc;
2799 }
e0d687bd
PR		 2800 ah->bhalq = ret;
2801 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2802 if (IS_ERR(ah->cabq)) {
2803 ATH5K_ERR(ah, "can't setup cab queue\n");
2804 ret = PTR_ERR(ah->cabq);
8a63facc
BC		 2805 goto err_bhal;
2806 }
fa1c114f 2807
22d8d9f8
BR		 2808 /* 5211 and 5212 usually support 10 queues but we better rely on the
2809 * capability information */
2810 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2811 /* This order matches mac80211's queue priority, so we can
2812 * directly use the mac80211 queue number without any mapping */
e0d687bd 2813 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
22d8d9f8 2814 if (IS_ERR(txq)) {
e0d687bd 2815 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2816 ret = PTR_ERR(txq);
2817 goto err_queues;
2818 }
e0d687bd 2819 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
22d8d9f8 2820 if (IS_ERR(txq)) {
e0d687bd 2821 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2822 ret = PTR_ERR(txq);
2823 goto err_queues;
2824 }
e0d687bd 2825 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
22d8d9f8 2826 if (IS_ERR(txq)) {
e0d687bd 2827 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2828 ret = PTR_ERR(txq);
2829 goto err_queues;
2830 }
e0d687bd 2831 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
22d8d9f8 2832 if (IS_ERR(txq)) {
e0d687bd 2833 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2834 ret = PTR_ERR(txq);
2835 goto err_queues;
2836 }
2837 hw->queues = 4;
2838 } else {
2839 /* older hardware (5210) can only support one data queue */
e0d687bd 2840 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
22d8d9f8 2841 if (IS_ERR(txq)) {
e0d687bd 2842 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2843 ret = PTR_ERR(txq);
2844 goto err_queues;
2845 }
2846 hw->queues = 1;
2847 }
fa1c114f 2848
e0d687bd
PR		 2849 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2850 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2851 tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
2852 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2853 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
be009370 2854
e0d687bd
PR		 2855 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2856 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2857
fa9bfd61 2858 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
8a63facc 2859 if (ret) {
e0d687bd 2860 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
8a63facc 2861 goto err_queues;
e30eb4ab 2862 }
2bed03eb 2863
8a63facc
BC		 2864 SET_IEEE80211_PERM_ADDR(hw, mac);
2865 /* All MAC address bits matter for ACKs */
e0d687bd 2866 ath5k_update_bssid_mask_and_opmode(ah, NULL);
8a63facc
BC		 2867
2868 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2869 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2870 if (ret) {
e0d687bd 2871 ATH5K_ERR(ah, "can't initialize regulatory system\n");
8a63facc
BC		 2872 goto err_queues;
2873 }
2874
2875 ret = ieee80211_register_hw(hw);
2876 if (ret) {
e0d687bd 2877 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
8a63facc
BC		 2878 goto err_queues;
2879 }
2880
2881 if (!ath_is_world_regd(regulatory))
2882 regulatory_hint(hw->wiphy, regulatory->alpha2);
2883
e0d687bd 2884 ath5k_init_leds(ah);
8a63facc 2885
e0d687bd 2886 ath5k_sysfs_register(ah);
8a63facc
BC		 2887
2888 return 0;
2889err_queues:
e0d687bd 2890 ath5k_txq_release(ah);
8a63facc 2891err_bhal:
e0d687bd 2892 ath5k_hw_release_tx_queue(ah, ah->bhalq);
8a63facc 2893err_desc:
e0d687bd 2894 ath5k_desc_free(ah);
8a63facc
BC		 2895err:
2896 return ret;
2897}
2898
132b1c3e 2899void
e0d687bd 2900ath5k_deinit_softc(struct ath5k_hw *ah)
8a63facc 2901{
e0d687bd 2902 struct ieee80211_hw *hw = ah->hw;
8a63facc
BC		 2903
2904 /*
2905 * NB: the order of these is important:
2906 * o call the 802.11 layer before detaching ath5k_hw to
2907 * ensure callbacks into the driver to delete global
2908 * key cache entries can be handled
2909 * o reclaim the tx queue data structures after calling
2910 * the 802.11 layer as we'll get called back to reclaim
2911 * node state and potentially want to use them
2912 * o to cleanup the tx queues the hal is called, so detach
2913 * it last
2914 * XXX: ??? detach ath5k_hw ???
2915 * Other than that, it's straightforward...
2916 */
2917 ieee80211_unregister_hw(hw);
e0d687bd
PR		 2918 ath5k_desc_free(ah);
2919 ath5k_txq_release(ah);
2920 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2921 ath5k_unregister_leds(ah);
8a63facc 2922
e0d687bd 2923 ath5k_sysfs_unregister(ah);
8a63facc
BC		 2924 /*
2925 * NB: can't reclaim these until after ieee80211_ifdetach
2926 * returns because we'll get called back to reclaim node
2927 * state and potentially want to use them.
2928 */
e0d687bd
PR		 2929 ath5k_hw_deinit(ah);
2930 free_irq(ah->irq, ah);
8a63facc
BC		 2931}
2932
cd2c5486 2933bool
e0d687bd 2934ath5k_any_vif_assoc(struct ath5k_hw *ah)
b1ae1edf 2935{
e4b0b32a 2936 struct ath5k_vif_iter_data iter_data;
b1ae1edf
BG		 2937 iter_data.hw_macaddr = NULL;
2938 iter_data.any_assoc = false;
2939 iter_data.need_set_hw_addr = false;
2940 iter_data.found_active = true;
2941
e0d687bd 2942 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
b1ae1edf
BG		 2943 &iter_data);
2944 return iter_data.any_assoc;
2945}
2946
cd2c5486 2947void
f5cbc8ba 2948ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
8a63facc 2949{
e0d687bd 2950 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2951 u32 rfilt;
2952 rfilt = ath5k_hw_get_rx_filter(ah);
2953 if (enable)
2954 rfilt |= AR5K_RX_FILTER_BEACON;
2955 else
2956 rfilt &= ~AR5K_RX_FILTER_BEACON;
2957 ath5k_hw_set_rx_filter(ah, rfilt);
e0d687bd 2958 ah->filter_flags = rfilt;
8a63facc 2959}
Linux kernel - Deliverables
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