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ath5k: Use Generic DMA for later support of AHB bus.
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
6ccf15a1 51#include <linux/pci-aspm.h>
fa1c114f
JS		 52#include <linux/ethtool.h>
53#include <linux/uaccess.h>
5a0e3ad6 54#include <linux/slab.h>
b1ae1edf 55#include <linux/etherdevice.h>
fa1c114f
JS		 56
57#include <net/ieee80211_radiotap.h>
58
59#include <asm/unaligned.h>
60
61#include "base.h"
62#include "reg.h"
63#include "debug.h"
2111ac0d 64#include "ani.h"
62c58fb4 65#include "../debug.h"
fa1c114f 66
9ad9a26e 67static int modparam_nohwcrypt;
46802a4f 68module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 69MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 70
42639fcd 71static int modparam_all_channels;
46802a4f 72module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 73MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
fa1c114f
JS		 75/* Module info */
76MODULE_AUTHOR("Jiri Slaby");
77MODULE_AUTHOR("Nick Kossifidis");
78MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 81MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f 82
8aec7af9
NK		 83static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
84 bool skip_pcu);
8a63facc
BC		 85static int ath5k_beacon_update(struct ieee80211_hw *hw,
86 struct ieee80211_vif *vif);
87static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 88
89/* Known PCI ids */
a3aa1884 90static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 91 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
92 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
93 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
94 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
95 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
96 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
97 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
98 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
99 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
104 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
105 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
106 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
107 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
108 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 109 { 0 }
110};
111MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
112
113/* Known SREVs */
2c91108c 114static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 115 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
116 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
117 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
118 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
119 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
120 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
121 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
122 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
123 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
124 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
125 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
126 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
127 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
128 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
129 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
130 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
131 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
132 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
133 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 134 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
135 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 136 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 137 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
138 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
139 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 140 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 141 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
142 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 143 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
144 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
145 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
146 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
147 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
148 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 149 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
150 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
151};
152
2c91108c 153static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 154 { .bitrate = 10,
155 .hw_value = ATH5K_RATE_CODE_1M, },
156 { .bitrate = 20,
157 .hw_value = ATH5K_RATE_CODE_2M,
158 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 55,
161 .hw_value = ATH5K_RATE_CODE_5_5M,
162 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 110,
165 .hw_value = ATH5K_RATE_CODE_11M,
166 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
167 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
168 { .bitrate = 60,
169 .hw_value = ATH5K_RATE_CODE_6M,
170 .flags = 0 },
171 { .bitrate = 90,
172 .hw_value = ATH5K_RATE_CODE_9M,
173 .flags = 0 },
174 { .bitrate = 120,
175 .hw_value = ATH5K_RATE_CODE_12M,
176 .flags = 0 },
177 { .bitrate = 180,
178 .hw_value = ATH5K_RATE_CODE_18M,
179 .flags = 0 },
180 { .bitrate = 240,
181 .hw_value = ATH5K_RATE_CODE_24M,
182 .flags = 0 },
183 { .bitrate = 360,
184 .hw_value = ATH5K_RATE_CODE_36M,
185 .flags = 0 },
186 { .bitrate = 480,
187 .hw_value = ATH5K_RATE_CODE_48M,
188 .flags = 0 },
189 { .bitrate = 540,
190 .hw_value = ATH5K_RATE_CODE_54M,
191 .flags = 0 },
192 /* XR missing */
193};
194
9e4e43f2 195static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 196 struct ath5k_buf *bf)
197{
198 BUG_ON(!bf);
199 if (!bf->skb)
200 return;
aeae4ac9
FF		 201 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
202 DMA_TO_DEVICE);
00482973 203 dev_kfree_skb_any(bf->skb);
fa1c114f 204 bf->skb = NULL;
39d63f2a
BR		 205 bf->skbaddr = 0;
206 bf->desc->ds_data = 0;
fa1c114f
JS		 207}
208
9e4e43f2 209static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 210 struct ath5k_buf *bf)
211{
cc861f74
LR		 212 struct ath5k_hw *ah = sc->ah;
213 struct ath_common *common = ath5k_hw_common(ah);
214
a6c8d375
FF		 215 BUG_ON(!bf);
216 if (!bf->skb)
217 return;
aeae4ac9
FF		 218 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
219 DMA_FROM_DEVICE);
a6c8d375
FF		 220 dev_kfree_skb_any(bf->skb);
221 bf->skb = NULL;
39d63f2a
BR		 222 bf->skbaddr = 0;
223 bf->desc->ds_data = 0;
a6c8d375
FF		 224}
225
226
fa1c114f
JS		 227static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
228{
229 u64 tsf = ath5k_hw_get_tsf64(ah);
230
231 if ((tsf & 0x7fff) < rstamp)
232 tsf -= 0x8000;
233
234 return (tsf & ~0x7fff) | rstamp;
235}
236
fa1c114f
JS		 237static const char *
238ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
239{
240 const char *name = "xxxxx";
241 unsigned int i;
242
243 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
244 if (srev_names[i].sr_type != type)
245 continue;
75d0edb8
NK		 246
247 if ((val & 0xf0) == srev_names[i].sr_val)
248 name = srev_names[i].sr_name;
249
250 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 251 name = srev_names[i].sr_name;
252 break;
253 }
254 }
255
256 return name;
257}
e5aa8474
LR		 258static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
259{
260 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
261 return ath5k_hw_reg_read(ah, reg_offset);
262}
263
264static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
265{
266 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
267 ath5k_hw_reg_write(ah, val, reg_offset);
268}
269
270static const struct ath_ops ath5k_common_ops = {
271 .read = ath5k_ioread32,
272 .write = ath5k_iowrite32,
273};
fa1c114f 274
8a63facc
BC		 275/***********************\
276* Driver Initialization *
277\***********************/
278
279static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 280{
8a63facc
BC		 281 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
282 struct ath5k_softc *sc = hw->priv;
283 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 284
8a63facc
BC		 285 return ath_reg_notifier_apply(wiphy, request, regulatory);
286}
6ccf15a1 287
8a63facc
BC		 288/********************\
289* Channel/mode setup *
290\********************/
fa1c114f 291
8a63facc
BC		 292/*
293 * Convert IEEE channel number to MHz frequency.
294 */
295static inline short
296ath5k_ieee2mhz(short chan)
297{
298 if (chan <= 14 || chan >= 27)
299 return ieee80211chan2mhz(chan);
300 else
301 return 2212 + chan * 20;
302}
fa1c114f 303
8a63facc
BC		 304/*
305 * Returns true for the channel numbers used without all_channels modparam.
306 */
307static bool ath5k_is_standard_channel(short chan)
308{
309 return ((chan <= 14) ||
310 /* UNII 1,2 */
311 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
312 /* midband */
313 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
314 /* UNII-3 */
315 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
316}
fa1c114f 317
8a63facc
BC		 318static unsigned int
319ath5k_copy_channels(struct ath5k_hw *ah,
320 struct ieee80211_channel *channels,
321 unsigned int mode,
322 unsigned int max)
323{
324 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f 325
8a63facc
BC		 326 if (!test_bit(mode, ah->ah_modes))
327 return 0;
fa1c114f 328
8a63facc
BC		 329 switch (mode) {
330 case AR5K_MODE_11A:
8a63facc
BC		 331 /* 1..220, but 2GHz frequencies are filtered by check_channel */
332 size = 220 ;
333 chfreq = CHANNEL_5GHZ;
334 break;
335 case AR5K_MODE_11B:
336 case AR5K_MODE_11G:
8a63facc
BC		 337 size = 26;
338 chfreq = CHANNEL_2GHZ;
339 break;
340 default:
341 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
342 return 0;
fa1c114f
JS		 343 }
344
8a63facc
BC		 345 for (i = 0, count = 0; i < size && max > 0; i++) {
346 ch = i + 1 ;
347 freq = ath5k_ieee2mhz(ch);
fa1c114f 348
8a63facc
BC		 349 /* Check if channel is supported by the chipset */
350 if (!ath5k_channel_ok(ah, freq, chfreq))
351 continue;
f59ac048 352
8a63facc
BC		 353 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
354 continue;
f59ac048 355
8a63facc
BC		 356 /* Write channel info and increment counter */
357 channels[count].center_freq = freq;
358 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
359 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
360 switch (mode) {
361 case AR5K_MODE_11A:
362 case AR5K_MODE_11G:
363 channels[count].hw_value = chfreq | CHANNEL_OFDM;
364 break;
8a63facc
BC		 365 case AR5K_MODE_11B:
366 channels[count].hw_value = CHANNEL_B;
367 }
fa1c114f 368
8a63facc
BC		 369 count++;
370 max--;
371 }
fa1c114f 372
8a63facc
BC		 373 return count;
374}
fa1c114f 375
8a63facc
BC		 376static void
377ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
378{
379 u8 i;
fa1c114f 380
8a63facc
BC		 381 for (i = 0; i < AR5K_MAX_RATES; i++)
382 sc->rate_idx[b->band][i] = -1;
fa1c114f 383
8a63facc
BC		 384 for (i = 0; i < b->n_bitrates; i++) {
385 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
386 if (b->bitrates[i].hw_value_short)
387 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 388 }
8a63facc 389}
fa1c114f 390
8a63facc
BC		 391static int
392ath5k_setup_bands(struct ieee80211_hw *hw)
393{
394 struct ath5k_softc *sc = hw->priv;
395 struct ath5k_hw *ah = sc->ah;
396 struct ieee80211_supported_band *sband;
397 int max_c, count_c = 0;
398 int i;
fa1c114f 399
8a63facc
BC		 400 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
401 max_c = ARRAY_SIZE(sc->channels);
db719718 402
8a63facc
BC		 403 /* 2GHz band */
404 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
405 sband->band = IEEE80211_BAND_2GHZ;
406 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 407
8a63facc
BC		 408 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
409 /* G mode */
410 memcpy(sband->bitrates, &ath5k_rates[0],
411 sizeof(struct ieee80211_rate) * 12);
412 sband->n_bitrates = 12;
2f7fe870 413
8a63facc
BC		 414 sband->channels = sc->channels;
415 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
416 AR5K_MODE_11G, max_c);
fa1c114f 417
8a63facc
BC		 418 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
419 count_c = sband->n_channels;
420 max_c -= count_c;
421 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
422 /* B mode */
423 memcpy(sband->bitrates, &ath5k_rates[0],
424 sizeof(struct ieee80211_rate) * 4);
425 sband->n_bitrates = 4;
fa1c114f 426
8a63facc
BC		 427 /* 5211 only supports B rates and uses 4bit rate codes
428 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
429 * fix them up here:
430 */
431 if (ah->ah_version == AR5K_AR5211) {
432 for (i = 0; i < 4; i++) {
433 sband->bitrates[i].hw_value =
434 sband->bitrates[i].hw_value & 0xF;
435 sband->bitrates[i].hw_value_short =
436 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 437 }
438 }
fa1c114f 439
8a63facc
BC		 440 sband->channels = sc->channels;
441 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
442 AR5K_MODE_11B, max_c);
fa1c114f 443
8a63facc
BC		 444 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
445 count_c = sband->n_channels;
446 max_c -= count_c;
447 }
448 ath5k_setup_rate_idx(sc, sband);
fa1c114f 449
8a63facc
BC		 450 /* 5GHz band, A mode */
451 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
452 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
453 sband->band = IEEE80211_BAND_5GHZ;
454 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 455
8a63facc
BC		 456 memcpy(sband->bitrates, &ath5k_rates[4],
457 sizeof(struct ieee80211_rate) * 8);
458 sband->n_bitrates = 8;
fa1c114f 459
8a63facc
BC		 460 sband->channels = &sc->channels[count_c];
461 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
462 AR5K_MODE_11A, max_c);
fa1c114f 463
8a63facc
BC		 464 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
465 }
466 ath5k_setup_rate_idx(sc, sband);
467
468 ath5k_debug_dump_bands(sc);
fa1c114f 469
fa1c114f
JS		 470 return 0;
471}
472
8a63facc
BC		 473/*
474 * Set/change channels. We always reset the chip.
475 * To accomplish this we must first cleanup any pending DMA,
476 * then restart stuff after a la ath5k_init.
477 *
478 * Called with sc->lock.
479 */
480static int
481ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
482{
483 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
484 "channel set, resetting (%u -> %u MHz)\n",
485 sc->curchan->center_freq, chan->center_freq);
486
8451d22d 487 /*
8a63facc
BC		 488 * To switch channels clear any pending DMA operations;
489 * wait long enough for the RX fifo to drain, reset the
490 * hardware at the new frequency, and then re-enable
491 * the relevant bits of the h/w.
8451d22d 492 */
8aec7af9 493 return ath5k_reset(sc, chan, true);
fa1c114f 494}
fa1c114f 495
8a63facc
BC		 496static void
497ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 498{
8a63facc 499 sc->curmode = mode;
f769c36b 500
8a63facc
BC		 501 if (mode == AR5K_MODE_11A) {
502 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
503 } else {
504 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
505 }
f769c36b
BC		 506}
507
b1ae1edf
BG		 508struct ath_vif_iter_data {
509 const u8 *hw_macaddr;
510 u8 mask[ETH_ALEN];
511 u8 active_mac[ETH_ALEN]; /* first active MAC */
512 bool need_set_hw_addr;
513 bool found_active;
514 bool any_assoc;
62c58fb4 515 enum nl80211_iftype opmode;
b1ae1edf
BG		 516};
517
518static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
519{
520 struct ath_vif_iter_data *iter_data = data;
521 int i;
62c58fb4 522 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 523
524 if (iter_data->hw_macaddr)
525 for (i = 0; i < ETH_ALEN; i++)
526 iter_data->mask[i] &=
527 ~(iter_data->hw_macaddr[i] ^ mac[i]);
528
529 if (!iter_data->found_active) {
530 iter_data->found_active = true;
531 memcpy(iter_data->active_mac, mac, ETH_ALEN);
532 }
533
534 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
535 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
536 iter_data->need_set_hw_addr = false;
537
538 if (!iter_data->any_assoc) {
b1ae1edf
BG		 539 if (avf->assoc)
540 iter_data->any_assoc = true;
541 }
62c58fb4
BG		 542
543 /* Calculate combined mode - when APs are active, operate in AP mode.
544 * Otherwise use the mode of the new interface. This can currently
545 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 546 * interfaces is allowed.
62c58fb4
BG		 547 */
548 if (avf->opmode == NL80211_IFTYPE_AP)
549 iter_data->opmode = NL80211_IFTYPE_AP;
550 else
551 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
552 iter_data->opmode = avf->opmode;
b1ae1edf
BG		 553}
554
14fb7c17
LR		 555static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
556 struct ieee80211_vif *vif)
b1ae1edf
BG		 557{
558 struct ath_common *common = ath5k_hw_common(sc->ah);
559 struct ath_vif_iter_data iter_data;
560
561 /*
562 * Use the hardware MAC address as reference, the hardware uses it
563 * together with the BSSID mask when matching addresses.
564 */
565 iter_data.hw_macaddr = common->macaddr;
566 memset(&iter_data.mask, 0xff, ETH_ALEN);
567 iter_data.found_active = false;
568 iter_data.need_set_hw_addr = true;
62c58fb4 569 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
b1ae1edf
BG		 570
571 if (vif)
572 ath_vif_iter(&iter_data, vif->addr, vif);
573
574 /* Get list of all active MAC addresses */
575 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
576 &iter_data);
577 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
578
62c58fb4
BG		 579 sc->opmode = iter_data.opmode;
580 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
581 /* Nothing active, default to station mode */
582 sc->opmode = NL80211_IFTYPE_STATION;
583
7afbb2f0
BG		 584 ath5k_hw_set_opmode(sc->ah, sc->opmode);
585 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
586 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 587
b1ae1edf
BG		 588 if (iter_data.need_set_hw_addr && iter_data.found_active)
589 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
590
62c58fb4
BG		 591 if (ath5k_hw_hasbssidmask(sc->ah))
592 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf
BG		 593}
594
8a63facc 595static void
b1ae1edf 596ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
fa1c114f 597{
fa1c114f 598 struct ath5k_hw *ah = sc->ah;
8a63facc 599 u32 rfilt;
fa1c114f 600
8a63facc
BC		 601 /* configure rx filter */
602 rfilt = sc->filter_flags;
603 ath5k_hw_set_rx_filter(ah, rfilt);
8a63facc 604 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
62c58fb4
BG		 605
606 ath5k_update_bssid_mask_and_opmode(sc, vif);
8a63facc 607}
fa1c114f 608
8a63facc
BC		 609static inline int
610ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
611{
612 int rix;
fa1c114f 613
8a63facc
BC		 614 /* return base rate on errors */
615 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
616 "hw_rix out of bounds: %x\n", hw_rix))
617 return 0;
618
619 rix = sc->rate_idx[sc->curband->band][hw_rix];
620 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
621 rix = 0;
622
623 return rix;
624}
625
626/***************\
627* Buffers setup *
628\***************/
629
630static
631struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
632{
633 struct ath_common *common = ath5k_hw_common(sc->ah);
634 struct sk_buff *skb;
fa1c114f
JS		 635
636 /*
8a63facc
BC		 637 * Allocate buffer with headroom_needed space for the
638 * fake physical layer header at the start.
fa1c114f 639 */
8a63facc
BC		 640 skb = ath_rxbuf_alloc(common,
641 common->rx_bufsize,
642 GFP_ATOMIC);
fa1c114f 643
8a63facc
BC		 644 if (!skb) {
645 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
646 common->rx_bufsize);
647 return NULL;
fa1c114f
JS		 648 }
649
aeae4ac9 650 *skb_addr = dma_map_single(sc->dev,
8a63facc 651 skb->data, common->rx_bufsize,
aeae4ac9
FF		 652 DMA_FROM_DEVICE);
653
654 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 655 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
656 dev_kfree_skb(skb);
657 return NULL;
0e149cf5 658 }
8a63facc
BC		 659 return skb;
660}
0e149cf5 661
8a63facc
BC		 662static int
663ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
664{
665 struct ath5k_hw *ah = sc->ah;
666 struct sk_buff *skb = bf->skb;
667 struct ath5k_desc *ds;
668 int ret;
fa1c114f 669
8a63facc
BC		 670 if (!skb) {
671 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
672 if (!skb)
673 return -ENOMEM;
674 bf->skb = skb;
f769c36b
BC		 675 }
676
8a63facc
BC		 677 /*
678 * Setup descriptors. For receive we always terminate
679 * the descriptor list with a self-linked entry so we'll
680 * not get overrun under high load (as can happen with a
681 * 5212 when ANI processing enables PHY error frames).
682 *
683 * To ensure the last descriptor is self-linked we create
684 * each descriptor as self-linked and add it to the end. As
685 * each additional descriptor is added the previous self-linked
686 * entry is "fixed" naturally. This should be safe even
687 * if DMA is happening. When processing RX interrupts we
688 * never remove/process the last, self-linked, entry on the
689 * descriptor list. This ensures the hardware always has
690 * someplace to write a new frame.
691 */
692 ds = bf->desc;
693 ds->ds_link = bf->daddr; /* link to self */
694 ds->ds_data = bf->skbaddr;
695 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 696 if (ret) {
8a63facc
BC		 697 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
698 return ret;
fa1c114f
JS		 699 }
700
8a63facc
BC		 701 if (sc->rxlink != NULL)
702 *sc->rxlink = bf->daddr;
703 sc->rxlink = &ds->ds_link;
fa1c114f 704 return 0;
fa1c114f
JS		 705}
706
8a63facc 707static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 708{
8a63facc
BC		 709 struct ieee80211_hdr *hdr;
710 enum ath5k_pkt_type htype;
711 __le16 fc;
fa1c114f 712
8a63facc
BC		 713 hdr = (struct ieee80211_hdr *)skb->data;
714 fc = hdr->frame_control;
fa1c114f 715
8a63facc
BC		 716 if (ieee80211_is_beacon(fc))
717 htype = AR5K_PKT_TYPE_BEACON;
718 else if (ieee80211_is_probe_resp(fc))
719 htype = AR5K_PKT_TYPE_PROBE_RESP;
720 else if (ieee80211_is_atim(fc))
721 htype = AR5K_PKT_TYPE_ATIM;
722 else if (ieee80211_is_pspoll(fc))
723 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 724 else
8a63facc 725 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 726
8a63facc 727 return htype;
42639fcd
BC		 728}
729
8a63facc
BC		 730static int
731ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
732 struct ath5k_txq *txq, int padsize)
fa1c114f 733{
8a63facc
BC		 734 struct ath5k_hw *ah = sc->ah;
735 struct ath5k_desc *ds = bf->desc;
736 struct sk_buff *skb = bf->skb;
737 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
738 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
739 struct ieee80211_rate *rate;
740 unsigned int mrr_rate[3], mrr_tries[3];
741 int i, ret;
742 u16 hw_rate;
743 u16 cts_rate = 0;
744 u16 duration = 0;
745 u8 rc_flags;
fa1c114f 746
8a63facc 747 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 748
8a63facc 749 /* XXX endianness */
aeae4ac9
FF		 750 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
751 DMA_TO_DEVICE);
fa1c114f 752
8a63facc 753 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 754 if (!rate) {
755 ret = -EINVAL;
756 goto err_unmap;
757 }
fa1c114f 758
8a63facc
BC		 759 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
760 flags |= AR5K_TXDESC_NOACK;
fa1c114f 761
8a63facc
BC		 762 rc_flags = info->control.rates[0].flags;
763 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
764 rate->hw_value_short : rate->hw_value;
42639fcd 765
8a63facc
BC		 766 pktlen = skb->len;
767
768 /* FIXME: If we are in g mode and rate is a CCK rate
769 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
770 * from tx power (value is in dB units already) */
771 if (info->control.hw_key) {
772 keyidx = info->control.hw_key->hw_key_idx;
773 pktlen += info->control.hw_key->icv_len;
774 }
775 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
776 flags |= AR5K_TXDESC_RTSENA;
777 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
778 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 779 info->control.vif, pktlen, info));
8a63facc
BC		 780 }
781 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
782 flags |= AR5K_TXDESC_CTSENA;
783 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
784 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 785 info->control.vif, pktlen, info));
8a63facc
BC		 786 }
787 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
788 ieee80211_get_hdrlen_from_skb(skb), padsize,
789 get_hw_packet_type(skb),
790 (sc->power_level * 2),
791 hw_rate,
792 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
793 cts_rate, duration);
794 if (ret)
795 goto err_unmap;
796
797 memset(mrr_rate, 0, sizeof(mrr_rate));
798 memset(mrr_tries, 0, sizeof(mrr_tries));
799 for (i = 0; i < 3; i++) {
800 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
801 if (!rate)
400ec45a 802 break;
fa1c114f 803
8a63facc
BC		 804 mrr_rate[i] = rate->hw_value;
805 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 806 }
807
8a63facc
BC		 808 ath5k_hw_setup_mrr_tx_desc(ah, ds,
809 mrr_rate[0], mrr_tries[0],
810 mrr_rate[1], mrr_tries[1],
811 mrr_rate[2], mrr_tries[2]);
fa1c114f 812
8a63facc
BC		 813 ds->ds_link = 0;
814 ds->ds_data = bf->skbaddr;
63266a65 815
8a63facc
BC		 816 spin_lock_bh(&txq->lock);
817 list_add_tail(&bf->list, &txq->q);
925e0b06 818 txq->txq_len++;
8a63facc
BC		 819 if (txq->link == NULL) /* is this first packet? */
820 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
821 else /* no, so only link it */
822 *txq->link = bf->daddr;
63266a65 823
8a63facc
BC		 824 txq->link = &ds->ds_link;
825 ath5k_hw_start_tx_dma(ah, txq->qnum);
826 mmiowb();
827 spin_unlock_bh(&txq->lock);
828
829 return 0;
830err_unmap:
aeae4ac9 831 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 832 return ret;
63266a65
BR		 833}
834
8a63facc
BC		 835/*******************\
836* Descriptors setup *
837\*******************/
838
d8ee398d 839static int
aeae4ac9 840ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 841{
8a63facc
BC		 842 struct ath5k_desc *ds;
843 struct ath5k_buf *bf;
844 dma_addr_t da;
845 unsigned int i;
846 int ret;
d8ee398d 847
8a63facc
BC		 848 /* allocate descriptors */
849 sc->desc_len = sizeof(struct ath5k_desc) *
850 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 851
852 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
853 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 854 if (sc->desc == NULL) {
855 ATH5K_ERR(sc, "can't allocate descriptors\n");
856 ret = -ENOMEM;
857 goto err;
858 }
859 ds = sc->desc;
860 da = sc->desc_daddr;
861 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
862 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 863
8a63facc
BC		 864 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
865 sizeof(struct ath5k_buf), GFP_KERNEL);
866 if (bf == NULL) {
867 ATH5K_ERR(sc, "can't allocate bufptr\n");
868 ret = -ENOMEM;
869 goto err_free;
870 }
871 sc->bufptr = bf;
fa1c114f 872
8a63facc
BC		 873 INIT_LIST_HEAD(&sc->rxbuf);
874 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
875 bf->desc = ds;
876 bf->daddr = da;
877 list_add_tail(&bf->list, &sc->rxbuf);
878 }
d8ee398d 879
8a63facc
BC		 880 INIT_LIST_HEAD(&sc->txbuf);
881 sc->txbuf_len = ATH_TXBUF;
882 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
883 da += sizeof(*ds)) {
884 bf->desc = ds;
885 bf->daddr = da;
886 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 887 }
888
b1ae1edf
BG		 889 /* beacon buffers */
890 INIT_LIST_HEAD(&sc->bcbuf);
891 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
892 bf->desc = ds;
893 bf->daddr = da;
894 list_add_tail(&bf->list, &sc->bcbuf);
895 }
fa1c114f 896
8a63facc
BC		 897 return 0;
898err_free:
aeae4ac9 899 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 900err:
901 sc->desc = NULL;
902 return ret;
903}
fa1c114f 904
8a63facc 905static void
aeae4ac9 906ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 907{
908 struct ath5k_buf *bf;
d8ee398d 909
8a63facc
BC		 910 list_for_each_entry(bf, &sc->txbuf, list)
911 ath5k_txbuf_free_skb(sc, bf);
912 list_for_each_entry(bf, &sc->rxbuf, list)
913 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 914 list_for_each_entry(bf, &sc->bcbuf, list)
915 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 916
8a63facc 917 /* Free memory associated with all descriptors */
aeae4ac9 918 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 919 sc->desc = NULL;
920 sc->desc_daddr = 0;
d8ee398d 921
8a63facc
BC		 922 kfree(sc->bufptr);
923 sc->bufptr = NULL;
fa1c114f
JS		 924}
925
8a63facc
BC		 926
927/**************\
928* Queues setup *
929\**************/
930
931static struct ath5k_txq *
932ath5k_txq_setup(struct ath5k_softc *sc,
933 int qtype, int subtype)
fa1c114f 934{
8a63facc
BC		 935 struct ath5k_hw *ah = sc->ah;
936 struct ath5k_txq *txq;
937 struct ath5k_txq_info qi = {
938 .tqi_subtype = subtype,
de8af455
BR		 939 /* XXX: default values not correct for B and XR channels,
940 * but who cares? */
941 .tqi_aifs = AR5K_TUNE_AIFS,
942 .tqi_cw_min = AR5K_TUNE_CWMIN,
943 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 944 };
945 int qnum;
d8ee398d 946
e30eb4ab 947 /*
8a63facc
BC		 948 * Enable interrupts only for EOL and DESC conditions.
949 * We mark tx descriptors to receive a DESC interrupt
950 * when a tx queue gets deep; otherwise we wait for the
951 * EOL to reap descriptors. Note that this is done to
952 * reduce interrupt load and this only defers reaping
953 * descriptors, never transmitting frames. Aside from
954 * reducing interrupts this also permits more concurrency.
955 * The only potential downside is if the tx queue backs
956 * up in which case the top half of the kernel may backup
957 * due to a lack of tx descriptors.
e30eb4ab 958 */
8a63facc
BC		 959 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
960 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
961 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
962 if (qnum < 0) {
963 /*
964 * NB: don't print a message, this happens
965 * normally on parts with too few tx queues
966 */
967 return ERR_PTR(qnum);
968 }
969 if (qnum >= ARRAY_SIZE(sc->txqs)) {
970 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
971 qnum, ARRAY_SIZE(sc->txqs));
972 ath5k_hw_release_tx_queue(ah, qnum);
973 return ERR_PTR(-EINVAL);
974 }
975 txq = &sc->txqs[qnum];
976 if (!txq->setup) {
977 txq->qnum = qnum;
978 txq->link = NULL;
979 INIT_LIST_HEAD(&txq->q);
980 spin_lock_init(&txq->lock);
981 txq->setup = true;
925e0b06 982 txq->txq_len = 0;
4edd761f 983 txq->txq_poll_mark = false;
923e5b3d 984 txq->txq_stuck = 0;
8a63facc
BC		 985 }
986 return &sc->txqs[qnum];
fa1c114f
JS		 987}
988
8a63facc
BC		 989static int
990ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 991{
8a63facc 992 struct ath5k_txq_info qi = {
de8af455
BR		 993 /* XXX: default values not correct for B and XR channels,
994 * but who cares? */
995 .tqi_aifs = AR5K_TUNE_AIFS,
996 .tqi_cw_min = AR5K_TUNE_CWMIN,
997 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 998 /* NB: for dynamic turbo, don't enable any other interrupts */
999 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1000 };
d8ee398d 1001
8a63facc 1002 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 1003}
1004
8a63facc
BC		 1005static int
1006ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 1007{
1008 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1009 struct ath5k_txq_info qi;
1010 int ret;
fa1c114f 1011
8a63facc
BC		 1012 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1013 if (ret)
1014 goto err;
fa1c114f 1015
8a63facc
BC		 1016 if (sc->opmode == NL80211_IFTYPE_AP ||
1017 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1018 /*
1019 * Always burst out beacon and CAB traffic
1020 * (aifs = cwmin = cwmax = 0)
1021 */
1022 qi.tqi_aifs = 0;
1023 qi.tqi_cw_min = 0;
1024 qi.tqi_cw_max = 0;
1025 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1026 /*
1027 * Adhoc mode; backoff between 0 and (2 * cw_min).
1028 */
1029 qi.tqi_aifs = 0;
1030 qi.tqi_cw_min = 0;
de8af455 1031 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 1032 }
fa1c114f 1033
8a63facc
BC		 1034 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1035 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1036 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1037
8a63facc
BC		 1038 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1039 if (ret) {
1040 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1041 "hardware queue!\n", __func__);
1042 goto err;
1043 }
1044 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1045 if (ret)
1046 goto err;
b7266047 1047
8a63facc
BC		 1048 /* reconfigure cabq with ready time to 80% of beacon_interval */
1049 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1050 if (ret)
1051 goto err;
b7266047 1052
8a63facc
BC		 1053 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1054 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1055 if (ret)
1056 goto err;
b7266047 1057
8a63facc
BC		 1058 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1059err:
1060 return ret;
d8ee398d
LR		 1061}
1062
80dac9ee
NK		 1063/**
1064 * ath5k_drain_tx_buffs - Empty tx buffers
1065 *
1066 * @sc The &struct ath5k_softc
1067 *
1068 * Empty tx buffers from all queues in preparation
1069 * of a reset or during shutdown.
1070 *
1071 * NB: this assumes output has been stopped and
1072 * we do not need to block ath5k_tx_tasklet
1073 */
8a63facc 1074static void
80dac9ee 1075ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1076{
80dac9ee 1077 struct ath5k_txq *txq;
8a63facc 1078 struct ath5k_buf *bf, *bf0;
80dac9ee 1079 int i;
b6ea0356 1080
80dac9ee
NK		 1081 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1082 if (sc->txqs[i].setup) {
1083 txq = &sc->txqs[i];
1084 spin_lock_bh(&txq->lock);
1085 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1086 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1087
80dac9ee 1088 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1089
80dac9ee
NK		 1090 spin_lock_bh(&sc->txbuflock);
1091 list_move_tail(&bf->list, &sc->txbuf);
1092 sc->txbuf_len++;
1093 txq->txq_len--;
1094 spin_unlock_bh(&sc->txbuflock);
8a63facc 1095 }
80dac9ee
NK		 1096 txq->link = NULL;
1097 txq->txq_poll_mark = false;
1098 spin_unlock_bh(&txq->lock);
1099 }
0452d4a5 1100 }
fa1c114f
JS		 1101}
1102
8a63facc
BC		 1103static void
1104ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1105{
8a63facc
BC		 1106 struct ath5k_txq *txq = sc->txqs;
1107 unsigned int i;
2ac2927a 1108
8a63facc
BC		 1109 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1110 if (txq->setup) {
1111 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1112 txq->setup = false;
1113 }
1114}
2ac2927a 1115
2ac2927a 1116
8a63facc
BC		 1117/*************\
1118* RX Handling *
1119\*************/
2ac2927a 1120
8a63facc
BC		 1121/*
1122 * Enable the receive h/w following a reset.
1123 */
fa1c114f 1124static int
8a63facc 1125ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1126{
1127 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1128 struct ath_common *common = ath5k_hw_common(ah);
1129 struct ath5k_buf *bf;
1130 int ret;
fa1c114f 1131
8a63facc 1132 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1133
8a63facc
BC		 1134 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1135 common->cachelsz, common->rx_bufsize);
2f7fe870 1136
8a63facc
BC		 1137 spin_lock_bh(&sc->rxbuflock);
1138 sc->rxlink = NULL;
1139 list_for_each_entry(bf, &sc->rxbuf, list) {
1140 ret = ath5k_rxbuf_setup(sc, bf);
1141 if (ret != 0) {
1142 spin_unlock_bh(&sc->rxbuflock);
1143 goto err;
1144 }
2f7fe870 1145 }
8a63facc
BC		 1146 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1147 ath5k_hw_set_rxdp(ah, bf->daddr);
1148 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1149
8a63facc 1150 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
b1ae1edf 1151 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
8a63facc 1152 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1153
1154 return 0;
8a63facc 1155err:
fa1c114f
JS		 1156 return ret;
1157}
1158
8a63facc 1159/*
80dac9ee
NK		 1160 * Disable the receive logic on PCU (DRU)
1161 * In preparation for a shutdown.
1162 *
1163 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1164 * does.
8a63facc
BC		 1165 */
1166static void
1167ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1168{
8a63facc 1169 struct ath5k_hw *ah = sc->ah;
fa1c114f 1170
8a63facc 1171 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1172 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1173
8a63facc
BC		 1174 ath5k_debug_printrxbuffs(sc, ah);
1175}
fa1c114f 1176
8a63facc
BC		 1177static unsigned int
1178ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1179 struct ath5k_rx_status *rs)
1180{
1181 struct ath5k_hw *ah = sc->ah;
1182 struct ath_common *common = ath5k_hw_common(ah);
1183 struct ieee80211_hdr *hdr = (void *)skb->data;
1184 unsigned int keyix, hlen;
fa1c114f 1185
8a63facc
BC		 1186 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1187 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1188 return RX_FLAG_DECRYPTED;
fa1c114f 1189
8a63facc
BC		 1190 /* Apparently when a default key is used to decrypt the packet
1191 the hw does not set the index used to decrypt. In such cases
1192 get the index from the packet. */
1193 hlen = ieee80211_hdrlen(hdr->frame_control);
1194 if (ieee80211_has_protected(hdr->frame_control) &&
1195 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1196 skb->len >= hlen + 4) {
1197 keyix = skb->data[hlen + 3] >> 6;
1198
1199 if (test_bit(keyix, common->keymap))
1200 return RX_FLAG_DECRYPTED;
1201 }
fa1c114f
JS		 1202
1203 return 0;
fa1c114f
JS		 1204}
1205
8a63facc 1206
fa1c114f 1207static void
8a63facc
BC		 1208ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1209 struct ieee80211_rx_status *rxs)
fa1c114f 1210{
8a63facc
BC		 1211 struct ath_common *common = ath5k_hw_common(sc->ah);
1212 u64 tsf, bc_tstamp;
1213 u32 hw_tu;
1214 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1215
8a63facc
BC		 1216 if (ieee80211_is_beacon(mgmt->frame_control) &&
1217 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1218 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1219 /*
1220 * Received an IBSS beacon with the same BSSID. Hardware *must*
1221 * have updated the local TSF. We have to work around various
1222 * hardware bugs, though...
1223 */
1224 tsf = ath5k_hw_get_tsf64(sc->ah);
1225 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1226 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1227
8a63facc
BC		 1228 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1229 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1230 (unsigned long long)bc_tstamp,
1231 (unsigned long long)rxs->mactime,
1232 (unsigned long long)(rxs->mactime - bc_tstamp),
1233 (unsigned long long)tsf);
fa1c114f 1234
8a63facc
BC		 1235 /*
1236 * Sometimes the HW will give us a wrong tstamp in the rx
1237 * status, causing the timestamp extension to go wrong.
1238 * (This seems to happen especially with beacon frames bigger
1239 * than 78 byte (incl. FCS))
1240 * But we know that the receive timestamp must be later than the
1241 * timestamp of the beacon since HW must have synced to that.
1242 *
1243 * NOTE: here we assume mactime to be after the frame was
1244 * received, not like mac80211 which defines it at the start.
1245 */
1246 if (bc_tstamp > rxs->mactime) {
1247 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1248 "fixing mactime from %llx to %llx\n",
1249 (unsigned long long)rxs->mactime,
1250 (unsigned long long)tsf);
1251 rxs->mactime = tsf;
1252 }
fa1c114f 1253
8a63facc
BC		 1254 /*
1255 * Local TSF might have moved higher than our beacon timers,
1256 * in that case we have to update them to continue sending
1257 * beacons. This also takes care of synchronizing beacon sending
1258 * times with other stations.
1259 */
1260 if (hw_tu >= sc->nexttbtt)
1261 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1262
1263 /* Check if the beacon timers are still correct, because a TSF
1264 * update might have created a window between them - for a
1265 * longer description see the comment of this function: */
1266 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1267 ath5k_beacon_update_timers(sc, bc_tstamp);
1268 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1269 "fixed beacon timers after beacon receive\n");
1270 }
8a63facc
BC		 1271 }
1272}
fa1c114f 1273
8a63facc
BC		 1274static void
1275ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1276{
1277 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1278 struct ath5k_hw *ah = sc->ah;
1279 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1280
8a63facc
BC		 1281 /* only beacons from our BSSID */
1282 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1283 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1284 return;
fa1c114f 1285
eef39bef 1286 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1287
8a63facc
BC		 1288 /* in IBSS mode we should keep RSSI statistics per neighbour */
1289 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1290}
fa1c114f 1291
8a63facc
BC		 1292/*
1293 * Compute padding position. skb must contain an IEEE 802.11 frame
1294 */
1295static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1296{
8a63facc
BC		 1297 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1298 __le16 frame_control = hdr->frame_control;
1299 int padpos = 24;
fa1c114f 1300
8a63facc
BC		 1301 if (ieee80211_has_a4(frame_control)) {
1302 padpos += ETH_ALEN;
fa1c114f 1303 }
8a63facc
BC		 1304 if (ieee80211_is_data_qos(frame_control)) {
1305 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1306 }
8a63facc
BC		 1307
1308 return padpos;
fa1c114f
JS		 1309}
1310
8a63facc
BC		 1311/*
1312 * This function expects an 802.11 frame and returns the number of
1313 * bytes added, or -1 if we don't have enough header room.
1314 */
1315static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1316{
8a63facc
BC		 1317 int padpos = ath5k_common_padpos(skb);
1318 int padsize = padpos & 3;
fa1c114f 1319
8a63facc 1320 if (padsize && skb->len>padpos) {
fa1c114f 1321
8a63facc
BC		 1322 if (skb_headroom(skb) < padsize)
1323 return -1;
fa1c114f 1324
8a63facc
BC		 1325 skb_push(skb, padsize);
1326 memmove(skb->data, skb->data+padsize, padpos);
1327 return padsize;
1328 }
a951ae21 1329
8a63facc
BC		 1330 return 0;
1331}
fa1c114f 1332
8a63facc
BC		 1333/*
1334 * The MAC header is padded to have 32-bit boundary if the
1335 * packet payload is non-zero. The general calculation for
1336 * padsize would take into account odd header lengths:
1337 * padsize = 4 - (hdrlen & 3); however, since only
1338 * even-length headers are used, padding can only be 0 or 2
1339 * bytes and we can optimize this a bit. We must not try to
1340 * remove padding from short control frames that do not have a
1341 * payload.
1342 *
1343 * This function expects an 802.11 frame and returns the number of
1344 * bytes removed.
1345 */
1346static int ath5k_remove_padding(struct sk_buff *skb)
1347{
1348 int padpos = ath5k_common_padpos(skb);
1349 int padsize = padpos & 3;
6d91e1d8 1350
8a63facc
BC		 1351 if (padsize && skb->len>=padpos+padsize) {
1352 memmove(skb->data + padsize, skb->data, padpos);
1353 skb_pull(skb, padsize);
1354 return padsize;
fa1c114f 1355 }
a951ae21 1356
8a63facc 1357 return 0;
fa1c114f
JS		 1358}
1359
1360static void
8a63facc
BC		 1361ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1362 struct ath5k_rx_status *rs)
fa1c114f 1363{
8a63facc
BC		 1364 struct ieee80211_rx_status *rxs;
1365
1366 ath5k_remove_padding(skb);
1367
1368 rxs = IEEE80211_SKB_RXCB(skb);
1369
1370 rxs->flag = 0;
1371 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1372 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1373
1374 /*
8a63facc
BC		 1375 * always extend the mac timestamp, since this information is
1376 * also needed for proper IBSS merging.
1377 *
1378 * XXX: it might be too late to do it here, since rs_tstamp is
1379 * 15bit only. that means TSF extension has to be done within
1380 * 32768usec (about 32ms). it might be necessary to move this to
1381 * the interrupt handler, like it is done in madwifi.
1382 *
1383 * Unfortunately we don't know when the hardware takes the rx
1384 * timestamp (beginning of phy frame, data frame, end of rx?).
1385 * The only thing we know is that it is hardware specific...
1386 * On AR5213 it seems the rx timestamp is at the end of the
1387 * frame, but i'm not sure.
1388 *
1389 * NOTE: mac80211 defines mactime at the beginning of the first
1390 * data symbol. Since we don't have any time references it's
1391 * impossible to comply to that. This affects IBSS merge only
1392 * right now, so it's not too bad...
fa1c114f 1393 */
8a63facc
BC		 1394 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1395 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1396
8a63facc
BC		 1397 rxs->freq = sc->curchan->center_freq;
1398 rxs->band = sc->curband->band;
fa1c114f 1399
8a63facc 1400 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1401
8a63facc 1402 rxs->antenna = rs->rs_antenna;
fa1c114f 1403
8a63facc
BC		 1404 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1405 sc->stats.antenna_rx[rs->rs_antenna]++;
1406 else
1407 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1408
8a63facc
BC		 1409 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1410 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1411
8a63facc
BC		 1412 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1413 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1414 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1415
8a63facc 1416 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1417
8a63facc 1418 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1419
8a63facc
BC		 1420 /* check beacons in IBSS mode */
1421 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1422 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1423
8a63facc
BC		 1424 ieee80211_rx(sc->hw, skb);
1425}
fa1c114f 1426
8a63facc
BC		 1427/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1428 *
1429 * Check if we want to further process this frame or not. Also update
1430 * statistics. Return true if we want this frame, false if not.
fa1c114f 1431 */
8a63facc
BC		 1432static bool
1433ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1434{
8a63facc 1435 sc->stats.rx_all_count++;
b72acddb 1436 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1437
8a63facc
BC		 1438 if (unlikely(rs->rs_status)) {
1439 if (rs->rs_status & AR5K_RXERR_CRC)
1440 sc->stats.rxerr_crc++;
1441 if (rs->rs_status & AR5K_RXERR_FIFO)
1442 sc->stats.rxerr_fifo++;
1443 if (rs->rs_status & AR5K_RXERR_PHY) {
1444 sc->stats.rxerr_phy++;
1445 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1446 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1447 return false;
1448 }
1449 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1450 /*
1451 * Decrypt error. If the error occurred
1452 * because there was no hardware key, then
1453 * let the frame through so the upper layers
1454 * can process it. This is necessary for 5210
1455 * parts which have no way to setup a ``clear''
1456 * key cache entry.
1457 *
1458 * XXX do key cache faulting
1459 */
1460 sc->stats.rxerr_decrypt++;
1461 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1462 !(rs->rs_status & AR5K_RXERR_CRC))
1463 return true;
1464 }
1465 if (rs->rs_status & AR5K_RXERR_MIC) {
1466 sc->stats.rxerr_mic++;
1467 return true;
fa1c114f 1468 }
fa1c114f 1469
8a63facc
BC		 1470 /* reject any frames with non-crypto errors */
1471 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1472 return false;
1473 }
fa1c114f 1474
8a63facc
BC		 1475 if (unlikely(rs->rs_more)) {
1476 sc->stats.rxerr_jumbo++;
1477 return false;
1478 }
1479 return true;
fa1c114f
JS		 1480}
1481
fa1c114f 1482static void
8a63facc 1483ath5k_tasklet_rx(unsigned long data)
fa1c114f 1484{
8a63facc
BC		 1485 struct ath5k_rx_status rs = {};
1486 struct sk_buff *skb, *next_skb;
1487 dma_addr_t next_skb_addr;
1488 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1489 struct ath5k_hw *ah = sc->ah;
1490 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1491 struct ath5k_buf *bf;
1492 struct ath5k_desc *ds;
1493 int ret;
fa1c114f 1494
8a63facc
BC		 1495 spin_lock(&sc->rxbuflock);
1496 if (list_empty(&sc->rxbuf)) {
1497 ATH5K_WARN(sc, "empty rx buf pool\n");
1498 goto unlock;
1499 }
1500 do {
1501 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1502 BUG_ON(bf->skb == NULL);
1503 skb = bf->skb;
1504 ds = bf->desc;
fa1c114f 1505
8a63facc
BC		 1506 /* bail if HW is still using self-linked descriptor */
1507 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1508 break;
fa1c114f 1509
8a63facc
BC		 1510 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1511 if (unlikely(ret == -EINPROGRESS))
1512 break;
1513 else if (unlikely(ret)) {
1514 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1515 sc->stats.rxerr_proc++;
1516 break;
1517 }
fa1c114f 1518
8a63facc
BC		 1519 if (ath5k_receive_frame_ok(sc, &rs)) {
1520 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1521
8a63facc
BC		 1522 /*
1523 * If we can't replace bf->skb with a new skb under
1524 * memory pressure, just skip this packet
1525 */
1526 if (!next_skb)
1527 goto next;
036cd1ec 1528
aeae4ac9 1529 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1530 common->rx_bufsize,
aeae4ac9 1531 DMA_FROM_DEVICE);
036cd1ec 1532
8a63facc 1533 skb_put(skb, rs.rs_datalen);
6ba81c2c 1534
8a63facc 1535 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1536
8a63facc
BC		 1537 bf->skb = next_skb;
1538 bf->skbaddr = next_skb_addr;
036cd1ec 1539 }
8a63facc
BC		 1540next:
1541 list_move_tail(&bf->list, &sc->rxbuf);
1542 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1543unlock:
1544 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1545}
1546
b4ea449d 1547
8a63facc
BC		 1548/*************\
1549* TX Handling *
1550\*************/
b4ea449d 1551
8a63facc
BC		 1552static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1553 struct ath5k_txq *txq)
1554{
1555 struct ath5k_softc *sc = hw->priv;
1556 struct ath5k_buf *bf;
1557 unsigned long flags;
1558 int padsize;
b4ea449d 1559
8a63facc 1560 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
b4ea449d 1561
8a63facc
BC		 1562 /*
1563 * The hardware expects the header padded to 4 byte boundaries.
1564 * If this is not the case, we add the padding after the header.
1565 */
1566 padsize = ath5k_add_padding(skb);
1567 if (padsize < 0) {
1568 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1569 " headroom to pad");
1570 goto drop_packet;
1571 }
8127fbdc 1572
925e0b06
BR		 1573 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1574 ieee80211_stop_queue(hw, txq->qnum);
1575
8a63facc
BC		 1576 spin_lock_irqsave(&sc->txbuflock, flags);
1577 if (list_empty(&sc->txbuf)) {
1578 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1579 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1580 ieee80211_stop_queues(hw);
8a63facc 1581 goto drop_packet;
8127fbdc 1582 }
8a63facc
BC		 1583 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1584 list_del(&bf->list);
1585 sc->txbuf_len--;
1586 if (list_empty(&sc->txbuf))
1587 ieee80211_stop_queues(hw);
1588 spin_unlock_irqrestore(&sc->txbuflock, flags);
1589
1590 bf->skb = skb;
1591
1592 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1593 bf->skb = NULL;
1594 spin_lock_irqsave(&sc->txbuflock, flags);
1595 list_add_tail(&bf->list, &sc->txbuf);
1596 sc->txbuf_len++;
1597 spin_unlock_irqrestore(&sc->txbuflock, flags);
1598 goto drop_packet;
8127fbdc 1599 }
8a63facc 1600 return NETDEV_TX_OK;
8127fbdc 1601
8a63facc
BC		 1602drop_packet:
1603 dev_kfree_skb_any(skb);
1604 return NETDEV_TX_OK;
8127fbdc
BP		 1605}
1606
1440401e
BR		 1607static void
1608ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1609 struct ath5k_tx_status *ts)
1610{
1611 struct ieee80211_tx_info *info;
1612 int i;
1613
1614 sc->stats.tx_all_count++;
b72acddb 1615 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1616 info = IEEE80211_SKB_CB(skb);
1617
1618 ieee80211_tx_info_clear_status(info);
1619 for (i = 0; i < 4; i++) {
1620 struct ieee80211_tx_rate *r =
1621 &info->status.rates[i];
1622
1623 if (ts->ts_rate[i]) {
1624 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1625 r->count = ts->ts_retry[i];
1626 } else {
1627 r->idx = -1;
1628 r->count = 0;
1629 }
1630 }
1631
1632 /* count the successful attempt as well */
1633 info->status.rates[ts->ts_final_idx].count++;
1634
1635 if (unlikely(ts->ts_status)) {
1636 sc->stats.ack_fail++;
1637 if (ts->ts_status & AR5K_TXERR_FILT) {
1638 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1639 sc->stats.txerr_filt++;
1640 }
1641 if (ts->ts_status & AR5K_TXERR_XRETRY)
1642 sc->stats.txerr_retry++;
1643 if (ts->ts_status & AR5K_TXERR_FIFO)
1644 sc->stats.txerr_fifo++;
1645 } else {
1646 info->flags |= IEEE80211_TX_STAT_ACK;
1647 info->status.ack_signal = ts->ts_rssi;
1648 }
1649
1650 /*
1651 * Remove MAC header padding before giving the frame
1652 * back to mac80211.
1653 */
1654 ath5k_remove_padding(skb);
1655
1656 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1657 sc->stats.antenna_tx[ts->ts_antenna]++;
1658 else
1659 sc->stats.antenna_tx[0]++; /* invalid */
1660
1661 ieee80211_tx_status(sc->hw, skb);
1662}
8a63facc
BC		 1663
1664static void
1665ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1666{
8a63facc
BC		 1667 struct ath5k_tx_status ts = {};
1668 struct ath5k_buf *bf, *bf0;
1669 struct ath5k_desc *ds;
1670 struct sk_buff *skb;
1440401e 1671 int ret;
8127fbdc 1672
8a63facc
BC		 1673 spin_lock(&txq->lock);
1674 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1675
1676 txq->txq_poll_mark = false;
1677
1678 /* skb might already have been processed last time. */
1679 if (bf->skb != NULL) {
1680 ds = bf->desc;
1681
1682 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1683 if (unlikely(ret == -EINPROGRESS))
1684 break;
1685 else if (unlikely(ret)) {
1686 ATH5K_ERR(sc,
1687 "error %d while processing "
1688 "queue %u\n", ret, txq->qnum);
1689 break;
1690 }
1691
1692 skb = bf->skb;
1693 bf->skb = NULL;
aeae4ac9
FF		 1694
1695 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1696 DMA_TO_DEVICE);
23413296
BR		 1697 ath5k_tx_frame_completed(sc, skb, &ts);
1698 }
8127fbdc 1699
8a63facc
BC		 1700 /*
1701 * It's possible that the hardware can say the buffer is
1702 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1703 * host memory and moved on.
1704 * Always keep the last descriptor to avoid HW races...
8a63facc 1705 */
23413296
BR		 1706 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1707 spin_lock(&sc->txbuflock);
1708 list_move_tail(&bf->list, &sc->txbuf);
1709 sc->txbuf_len++;
1710 txq->txq_len--;
1711 spin_unlock(&sc->txbuflock);
8a63facc 1712 }
fa1c114f 1713 }
fa1c114f 1714 spin_unlock(&txq->lock);
4198a8d0 1715 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1716 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1717}
1718
1719static void
1720ath5k_tasklet_tx(unsigned long data)
1721{
8784d2ee 1722 int i;
fa1c114f
JS		 1723 struct ath5k_softc *sc = (void *)data;
1724
8784d2ee
BC		 1725 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1726 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1727 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1728}
1729
1730
fa1c114f
JS		 1731/*****************\
1732* Beacon handling *
1733\*****************/
1734
1735/*
1736 * Setup the beacon frame for transmit.
1737 */
1738static int
e039fa4a 1739ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1740{
1741 struct sk_buff *skb = bf->skb;
a888d52d 1742 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1743 struct ath5k_hw *ah = sc->ah;
1744 struct ath5k_desc *ds;
2bed03eb
NK		 1745 int ret = 0;
1746 u8 antenna;
fa1c114f 1747 u32 flags;
8127fbdc 1748 const int padsize = 0;
fa1c114f 1749
aeae4ac9
FF		 1750 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1751 DMA_TO_DEVICE);
fa1c114f
JS		 1752 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1753 "skbaddr %llx\n", skb, skb->data, skb->len,
1754 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1755
1756 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1757 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1758 return -EIO;
1759 }
1760
1761 ds = bf->desc;
2bed03eb 1762 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1763
1764 flags = AR5K_TXDESC_NOACK;
05c914fe 1765 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1766 ds->ds_link = bf->daddr; /* self-linked */
1767 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1768 } else
fa1c114f 1769 ds->ds_link = 0;
2bed03eb
NK		 1770
1771 /*
1772 * If we use multiple antennas on AP and use
1773 * the Sectored AP scenario, switch antenna every
1774 * 4 beacons to make sure everybody hears our AP.
1775 * When a client tries to associate, hw will keep
1776 * track of the tx antenna to be used for this client
1777 * automaticaly, based on ACKed packets.
1778 *
1779 * Note: AP still listens and transmits RTS on the
1780 * default antenna which is supposed to be an omni.
1781 *
1782 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1783 * multiple antennas (1 omni -- the default -- and 14
1784 * sectors), so if we choose to actually support this
1785 * mode, we need to allow the user to set how many antennas
1786 * we have and tweak the code below to send beacons
1787 * on all of them.
2bed03eb
NK		 1788 */
1789 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1790 antenna = sc->bsent & 4 ? 2 : 1;
1791
fa1c114f 1792
8f655dde
NK		 1793 /* FIXME: If we are in g mode and rate is a CCK rate
1794 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1795 * from tx power (value is in dB units already) */
fa1c114f 1796 ds->ds_data = bf->skbaddr;
281c56dd 1797 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1798 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1799 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1800 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1801 1, AR5K_TXKEYIX_INVALID,
400ec45a 1802 antenna, flags, 0, 0);
fa1c114f
JS		 1803 if (ret)
1804 goto err_unmap;
1805
1806 return 0;
1807err_unmap:
aeae4ac9 1808 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1809 return ret;
1810}
1811
8a63facc
BC		 1812/*
1813 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1814 * this is called only once at config_bss time, for AP we do it every
1815 * SWBA interrupt so that the TIM will reflect buffered frames.
1816 *
1817 * Called with the beacon lock.
1818 */
1819static int
1820ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1821{
1822 int ret;
1823 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1824 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1825 struct sk_buff *skb;
1826
1827 if (WARN_ON(!vif)) {
1828 ret = -EINVAL;
1829 goto out;
1830 }
1831
1832 skb = ieee80211_beacon_get(hw, vif);
1833
1834 if (!skb) {
1835 ret = -ENOMEM;
1836 goto out;
1837 }
1838
1839 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1840
b1ae1edf
BG		 1841 ath5k_txbuf_free_skb(sc, avf->bbuf);
1842 avf->bbuf->skb = skb;
1843 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1844 if (ret)
b1ae1edf 1845 avf->bbuf->skb = NULL;
8a63facc
BC		 1846out:
1847 return ret;
1848}
1849
fa1c114f
JS		 1850/*
1851 * Transmit a beacon frame at SWBA. Dynamic updates to the
1852 * frame contents are done as needed and the slot time is
1853 * also adjusted based on current state.
1854 *
5faaff74
BC		 1855 * This is called from software irq context (beacontq tasklets)
1856 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1857 */
1858static void
1859ath5k_beacon_send(struct ath5k_softc *sc)
1860{
fa1c114f 1861 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1862 struct ieee80211_vif *vif;
1863 struct ath5k_vif *avf;
1864 struct ath5k_buf *bf;
cec8db23 1865 struct sk_buff *skb;
fa1c114f 1866
be9b7259 1867 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1868
fa1c114f
JS		 1869 /*
1870 * Check if the previous beacon has gone out. If
a180a130 1871 * not, don't don't try to post another: skip this
fa1c114f
JS		 1872 * period and wait for the next. Missed beacons
1873 * indicate a problem and should not occur. If we
1874 * miss too many consecutive beacons reset the device.
1875 */
1876 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1877 sc->bmisscount++;
be9b7259 1878 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1879 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1880 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1881 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1882 "stuck beacon time (%u missed)\n",
1883 sc->bmisscount);
8d67a031
BR		 1884 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1885 "stuck beacon, resetting\n");
5faaff74 1886 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1887 }
1888 return;
1889 }
1890 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1891 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1892 "resume beacon xmit after %u misses\n",
1893 sc->bmisscount);
1894 sc->bmisscount = 0;
1895 }
1896
b1ae1edf
BG		 1897 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1898 u64 tsf = ath5k_hw_get_tsf64(ah);
1899 u32 tsftu = TSF_TO_TU(tsf);
1900 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1901 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1902 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1903 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1904 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1905 } else /* only one interface */
1906 vif = sc->bslot[0];
1907
1908 if (!vif)
1909 return;
1910
1911 avf = (void *)vif->drv_priv;
1912 bf = avf->bbuf;
1913 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1914 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1915 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1916 return;
1917 }
1918
fa1c114f
JS		 1919 /*
1920 * Stop any current dma and put the new frame on the queue.
1921 * This should never fail since we check above that no frames
1922 * are still pending on the queue.
1923 */
14fae2d4 1924 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1925 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1926 /* NB: hw still stops DMA, so proceed */
1927 }
fa1c114f 1928
1071db86
BC		 1929 /* refresh the beacon for AP mode */
1930 if (sc->opmode == NL80211_IFTYPE_AP)
b1ae1edf 1931 ath5k_beacon_update(sc->hw, vif);
1071db86 1932
c6e387a2
NK		 1933 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1934 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1935 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1936 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1937
b1ae1edf 1938 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1939 while (skb) {
1940 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1941 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1942 }
1943
fa1c114f
JS		 1944 sc->bsent++;
1945}
1946
9804b98d
BR		 1947/**
1948 * ath5k_beacon_update_timers - update beacon timers
1949 *
1950 * @sc: struct ath5k_softc pointer we are operating on
1951 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1952 * beacon timer update based on the current HW TSF.
1953 *
1954 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1955 * of a received beacon or the current local hardware TSF and write it to the
1956 * beacon timer registers.
1957 *
1958 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1959 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1960 * when we otherwise know we have to update the timers, but we keep it in this
1961 * function to have it all together in one place.
1962 */
fa1c114f 1963static void
9804b98d 1964ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1965{
1966 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1967 u32 nexttbtt, intval, hw_tu, bc_tu;
1968 u64 hw_tsf;
fa1c114f
JS		 1969
1970 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1971 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1972 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1973 if (intval < 15)
1974 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1975 intval);
1976 }
fa1c114f
JS		 1977 if (WARN_ON(!intval))
1978 return;
1979
9804b98d
BR		 1980 /* beacon TSF converted to TU */
1981 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1982
9804b98d
BR		 1983 /* current TSF converted to TU */
1984 hw_tsf = ath5k_hw_get_tsf64(ah);
1985 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1986
11f21df3
BR		 1987#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1988 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1989 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1990 * configuration we need to make sure it is bigger than that. */
1991
9804b98d
BR		 1992 if (bc_tsf == -1) {
1993 /*
1994 * no beacons received, called internally.
1995 * just need to refresh timers based on HW TSF.
1996 */
1997 nexttbtt = roundup(hw_tu + FUDGE, intval);
1998 } else if (bc_tsf == 0) {
1999 /*
2000 * no beacon received, probably called by ath5k_reset_tsf().
2001 * reset TSF to start with 0.
2002 */
2003 nexttbtt = intval;
2004 intval |= AR5K_BEACON_RESET_TSF;
2005 } else if (bc_tsf > hw_tsf) {
2006 /*
2007 * beacon received, SW merge happend but HW TSF not yet updated.
2008 * not possible to reconfigure timers yet, but next time we
2009 * receive a beacon with the same BSSID, the hardware will
2010 * automatically update the TSF and then we need to reconfigure
2011 * the timers.
2012 */
2013 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2014 "need to wait for HW TSF sync\n");
2015 return;
2016 } else {
2017 /*
2018 * most important case for beacon synchronization between STA.
2019 *
2020 * beacon received and HW TSF has been already updated by HW.
2021 * update next TBTT based on the TSF of the beacon, but make
2022 * sure it is ahead of our local TSF timer.
2023 */
2024 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2025 }
2026#undef FUDGE
fa1c114f 2027
036cd1ec
BR		 2028 sc->nexttbtt = nexttbtt;
2029
fa1c114f 2030 intval |= AR5K_BEACON_ENA;
fa1c114f 2031 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2032
2033 /*
2034 * debugging output last in order to preserve the time critical aspect
2035 * of this function
2036 */
2037 if (bc_tsf == -1)
2038 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2039 "reconfigured timers based on HW TSF\n");
2040 else if (bc_tsf == 0)
2041 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2042 "reset HW TSF and timers\n");
2043 else
2044 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2045 "updated timers based on beacon TSF\n");
2046
2047 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2048 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2049 (unsigned long long) bc_tsf,
2050 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2051 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2052 intval & AR5K_BEACON_PERIOD,
2053 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2054 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2055}
2056
036cd1ec
BR		 2057/**
2058 * ath5k_beacon_config - Configure the beacon queues and interrupts
2059 *
2060 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2061 *
036cd1ec 2062 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2063 * interrupts to detect TSF updates only.
fa1c114f
JS		 2064 */
2065static void
2066ath5k_beacon_config(struct ath5k_softc *sc)
2067{
2068 struct ath5k_hw *ah = sc->ah;
b5f03956 2069 unsigned long flags;
fa1c114f 2070
21800491 2071 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2072 sc->bmisscount = 0;
dc1968e7 2073 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2074
21800491 2075 if (sc->enable_beacon) {
fa1c114f 2076 /*
036cd1ec
BR		 2077 * In IBSS mode we use a self-linked tx descriptor and let the
2078 * hardware send the beacons automatically. We have to load it
fa1c114f 2079 * only once here.
036cd1ec 2080 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2081 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2082 */
2083 ath5k_beaconq_config(sc);
fa1c114f 2084
036cd1ec
BR		 2085 sc->imask |= AR5K_INT_SWBA;
2086
da966bca 2087 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2088 if (ath5k_hw_hasveol(ah))
da966bca 2089 ath5k_beacon_send(sc);
da966bca
JS		 2090 } else
2091 ath5k_beacon_update_timers(sc, -1);
21800491 2092 } else {
14fae2d4 2093 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2094 }
fa1c114f 2095
c6e387a2 2096 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2097 mmiowb();
2098 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2099}
2100
428cbd4f
NK		 2101static void ath5k_tasklet_beacon(unsigned long data)
2102{
2103 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2104
2105 /*
2106 * Software beacon alert--time to send a beacon.
2107 *
2108 * In IBSS mode we use this interrupt just to
2109 * keep track of the next TBTT (target beacon
2110 * transmission time) in order to detect wether
2111 * automatic TSF updates happened.
2112 */
2113 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2114 /* XXX: only if VEOL suppported */
2115 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2116 sc->nexttbtt += sc->bintval;
2117 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2118 "SWBA nexttbtt: %x hw_tu: %x "
2119 "TSF: %llx\n",
2120 sc->nexttbtt,
2121 TSF_TO_TU(tsf),
2122 (unsigned long long) tsf);
2123 } else {
2124 spin_lock(&sc->block);
2125 ath5k_beacon_send(sc);
2126 spin_unlock(&sc->block);
2127 }
2128}
2129
fa1c114f
JS		 2130
2131/********************\
2132* Interrupt handling *
2133\********************/
2134
6a8a3f6b
BR		 2135static void
2136ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2137{
2111ac0d
BR		 2138 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2139 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2140 /* run ANI only when full calibration is not active */
2141 ah->ah_cal_next_ani = jiffies +
2142 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2143 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2144
2145 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2146 ah->ah_cal_next_full = jiffies +
2147 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2148 tasklet_schedule(&ah->ah_sc->calib);
2149 }
2150 /* we could use SWI to generate enough interrupts to meet our
2151 * calibration interval requirements, if necessary:
2152 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2153}
2154
fa1c114f
JS		 2155static irqreturn_t
2156ath5k_intr(int irq, void *dev_id)
2157{
2158 struct ath5k_softc *sc = dev_id;
2159 struct ath5k_hw *ah = sc->ah;
2160 enum ath5k_int status;
2161 unsigned int counter = 1000;
2162
2163 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2164 !ath5k_hw_is_intr_pending(ah)))
2165 return IRQ_NONE;
2166
2167 do {
fa1c114f
JS		 2168 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2169 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2170 status, sc->imask);
fa1c114f
JS		 2171 if (unlikely(status & AR5K_INT_FATAL)) {
2172 /*
2173 * Fatal errors are unrecoverable.
2174 * Typically these are caused by DMA errors.
2175 */
8d67a031
BR		 2176 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2177 "fatal int, resetting\n");
5faaff74 2178 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2179 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2180 /*
2181 * Receive buffers are full. Either the bus is busy or
2182 * the CPU is not fast enough to process all received
2183 * frames.
2184 * Older chipsets need a reset to come out of this
2185 * condition, but we treat it as RX for newer chips.
2186 * We don't know exactly which versions need a reset -
2187 * this guess is copied from the HAL.
2188 */
2189 sc->stats.rxorn_intr++;
8d67a031
BR		 2190 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2191 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2192 "rx overrun, resetting\n");
5faaff74 2193 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2194 }
87d77c4e
BR		 2195 else
2196 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2197 } else {
2198 if (status & AR5K_INT_SWBA) {
56d2ac76 2199 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2200 }
2201 if (status & AR5K_INT_RXEOL) {
2202 /*
2203 * NB: the hardware should re-read the link when
2204 * RXE bit is written, but it doesn't work at
2205 * least on older hardware revs.
2206 */
b3f194e5 2207 sc->stats.rxeol_intr++;
fa1c114f
JS		 2208 }
2209 if (status & AR5K_INT_TXURN) {
2210 /* bump tx trigger level */
2211 ath5k_hw_update_tx_triglevel(ah, true);
2212 }
4c674c60 2213 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2214 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2215 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2216 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2217 tasklet_schedule(&sc->txtq);
2218 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2219 /* TODO */
fa1c114f
JS		 2220 }
2221 if (status & AR5K_INT_MIB) {
2111ac0d 2222 sc->stats.mib_intr++;
495391d7 2223 ath5k_hw_update_mib_counters(ah);
2111ac0d 2224 ath5k_ani_mib_intr(ah);
fa1c114f 2225 }
e6a3b616 2226 if (status & AR5K_INT_GPIO)
e6a3b616 2227 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2228
fa1c114f 2229 }
2516baa6 2230 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2231
2232 if (unlikely(!counter))
2233 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2234
6a8a3f6b 2235 ath5k_intr_calibration_poll(ah);
6e220662 2236
fa1c114f
JS		 2237 return IRQ_HANDLED;
2238}
2239
fa1c114f
JS		 2240/*
2241 * Periodically recalibrate the PHY to account
2242 * for temperature/environment changes.
2243 */
2244static void
6e220662 2245ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2246{
2247 struct ath5k_softc *sc = (void *)data;
2248 struct ath5k_hw *ah = sc->ah;
2249
6e220662 2250 /* Only full calibration for now */
e65e1d77 2251 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2252
fa1c114f 2253 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2254 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2255 sc->curchan->hw_value);
fa1c114f 2256
6f3b414a 2257 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2258 /*
2259 * Rfgain is out of bounds, reset the chip
2260 * to load new gain values.
2261 */
2262 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2263 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2264 }
2265 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2266 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2267 ieee80211_frequency_to_channel(
2268 sc->curchan->center_freq));
fa1c114f 2269
0e8e02dd 2270 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2271 * doesn't.
2272 * TODO: We should stop TX here, so that it doesn't interfere.
2273 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2274 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2275 ah->ah_cal_next_nf = jiffies +
2276 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2277 ath5k_hw_update_noise_floor(ah);
afe86286 2278 }
6e220662 2279
e65e1d77 2280 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2281}
2282
2283
2111ac0d
BR		 2284static void
2285ath5k_tasklet_ani(unsigned long data)
2286{
2287 struct ath5k_softc *sc = (void *)data;
2288 struct ath5k_hw *ah = sc->ah;
2289
2290 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2291 ath5k_ani_calibration(ah);
2292 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2293}
2294
2295
4edd761f
BR		 2296static void
2297ath5k_tx_complete_poll_work(struct work_struct *work)
2298{
2299 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2300 tx_complete_work.work);
2301 struct ath5k_txq *txq;
2302 int i;
2303 bool needreset = false;
2304
2305 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2306 if (sc->txqs[i].setup) {
2307 txq = &sc->txqs[i];
2308 spin_lock_bh(&txq->lock);
23413296 2309 if (txq->txq_len > 1) {
4edd761f
BR		 2310 if (txq->txq_poll_mark) {
2311 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2312 "TX queue stuck %d\n",
2313 txq->qnum);
2314 needreset = true;
923e5b3d 2315 txq->txq_stuck++;
4edd761f
BR		 2316 spin_unlock_bh(&txq->lock);
2317 break;
2318 } else {
2319 txq->txq_poll_mark = true;
2320 }
2321 }
2322 spin_unlock_bh(&txq->lock);
2323 }
2324 }
2325
2326 if (needreset) {
2327 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2328 "TX queues stuck, resetting\n");
8aec7af9 2329 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2330 }
2331
2332 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2333 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2334}
2335
2336
8a63facc
BC		 2337/*************************\
2338* Initialization routines *
2339\*************************/
fa1c114f
JS		 2340
2341static int
8a63facc 2342ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2343{
8a63facc 2344 struct ath5k_hw *ah = sc->ah;
cec8db23 2345
8a63facc
BC		 2346 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2347 test_bit(ATH_STAT_INVALID, sc->status));
2348
2349 /*
2350 * Shutdown the hardware and driver:
2351 * stop output from above
2352 * disable interrupts
2353 * turn off timers
2354 * turn off the radio
2355 * clear transmit machinery
2356 * clear receive machinery
2357 * drain and release tx queues
2358 * reclaim beacon resources
2359 * power down hardware
2360 *
2361 * Note that some of this work is not possible if the
2362 * hardware is gone (invalid).
2363 */
2364 ieee80211_stop_queues(sc->hw);
2365
2366 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2367 ath5k_led_off(sc);
2368 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2369 synchronize_irq(sc->irq);
8a63facc 2370 ath5k_rx_stop(sc);
80dac9ee
NK		 2371 ath5k_hw_dma_stop(ah);
2372 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2373 ath5k_hw_phy_disable(ah);
2374 }
2375
2376 return 0;
cec8db23
BC		 2377}
2378
8a63facc
BC		 2379static int
2380ath5k_init(struct ath5k_softc *sc)
fa1c114f 2381{
8a63facc
BC		 2382 struct ath5k_hw *ah = sc->ah;
2383 struct ath_common *common = ath5k_hw_common(ah);
2384 int ret, i;
fa1c114f 2385
8a63facc
BC		 2386 mutex_lock(&sc->lock);
2387
2388 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2389
fa1c114f 2390 /*
8a63facc
BC		 2391 * Stop anything previously setup. This is safe
2392 * no matter this is the first time through or not.
fa1c114f 2393 */
8a63facc 2394 ath5k_stop_locked(sc);
fa1c114f 2395
8a63facc
BC		 2396 /*
2397 * The basic interface to setting the hardware in a good
2398 * state is ``reset''. On return the hardware is known to
2399 * be powered up and with interrupts disabled. This must
2400 * be followed by initialization of the appropriate bits
2401 * and then setup of the interrupt mask.
2402 */
2403 sc->curchan = sc->hw->conf.channel;
2404 sc->curband = &sc->sbands[sc->curchan->band];
2405 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2406 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2407 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2408
8aec7af9 2409 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2410 if (ret)
2411 goto done;
fa1c114f 2412
8a63facc
BC		 2413 ath5k_rfkill_hw_start(ah);
2414
2415 /*
2416 * Reset the key cache since some parts do not reset the
2417 * contents on initial power up or resume from suspend.
2418 */
2419 for (i = 0; i < common->keymax; i++)
2420 ath_hw_keyreset(common, (u16) i);
2421
61cde037
NK		 2422 /* Use higher rates for acks instead of base
2423 * rate */
2424 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2425
2426 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2427 sc->bslot[i] = NULL;
2428
8a63facc
BC		 2429 ret = 0;
2430done:
2431 mmiowb();
2432 mutex_unlock(&sc->lock);
4edd761f
BR		 2433
2434 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2435 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2436
8a63facc
BC		 2437 return ret;
2438}
2439
2440static void stop_tasklets(struct ath5k_softc *sc)
2441{
2442 tasklet_kill(&sc->rxtq);
2443 tasklet_kill(&sc->txtq);
2444 tasklet_kill(&sc->calib);
2445 tasklet_kill(&sc->beacontq);
2446 tasklet_kill(&sc->ani_tasklet);
2447}
2448
2449/*
2450 * Stop the device, grabbing the top-level lock to protect
2451 * against concurrent entry through ath5k_init (which can happen
2452 * if another thread does a system call and the thread doing the
2453 * stop is preempted).
2454 */
2455static int
2456ath5k_stop_hw(struct ath5k_softc *sc)
2457{
2458 int ret;
2459
2460 mutex_lock(&sc->lock);
2461 ret = ath5k_stop_locked(sc);
2462 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2463 /*
2464 * Don't set the card in full sleep mode!
2465 *
2466 * a) When the device is in this state it must be carefully
2467 * woken up or references to registers in the PCI clock
2468 * domain may freeze the bus (and system). This varies
2469 * by chip and is mostly an issue with newer parts
2470 * (madwifi sources mentioned srev >= 0x78) that go to
2471 * sleep more quickly.
2472 *
2473 * b) On older chips full sleep results a weird behaviour
2474 * during wakeup. I tested various cards with srev < 0x78
2475 * and they don't wake up after module reload, a second
2476 * module reload is needed to bring the card up again.
2477 *
2478 * Until we figure out what's going on don't enable
2479 * full chip reset on any chip (this is what Legacy HAL
2480 * and Sam's HAL do anyway). Instead Perform a full reset
2481 * on the device (same as initial state after attach) and
2482 * leave it idle (keep MAC/BB on warm reset) */
2483 ret = ath5k_hw_on_hold(sc->ah);
2484
2485 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2486 "putting device to sleep\n");
fa1c114f
JS		 2487 }
2488
8a63facc
BC		 2489 mmiowb();
2490 mutex_unlock(&sc->lock);
2491
2492 stop_tasklets(sc);
2493
4edd761f
BR		 2494 cancel_delayed_work_sync(&sc->tx_complete_work);
2495
8a63facc
BC		 2496 ath5k_rfkill_hw_stop(sc->ah);
2497
2498 return ret;
fa1c114f
JS		 2499}
2500
209d889b
BC		 2501/*
2502 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2503 * and change to the given channel.
5faaff74
BC		 2504 *
2505 * This should be called with sc->lock.
209d889b 2506 */
fa1c114f 2507static int
8aec7af9
NK		 2508ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2509 bool skip_pcu)
fa1c114f 2510{
fa1c114f
JS		 2511 struct ath5k_hw *ah = sc->ah;
2512 int ret;
2513
2514 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2515
450464de 2516 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2517 synchronize_irq(sc->irq);
450464de
BC		 2518 stop_tasklets(sc);
2519
209d889b 2520 if (chan) {
80dac9ee 2521 ath5k_drain_tx_buffs(sc);
209d889b
BC		 2522
2523 sc->curchan = chan;
2524 sc->curband = &sc->sbands[chan->band];
d7dc1003 2525 }
8aec7af9
NK		 2526 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2527 skip_pcu);
d7dc1003 2528 if (ret) {
fa1c114f
JS		 2529 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2530 goto err;
2531 }
d7dc1003 2532
fa1c114f 2533 ret = ath5k_rx_start(sc);
d7dc1003 2534 if (ret) {
fa1c114f
JS		 2535 ATH5K_ERR(sc, "can't start recv logic\n");
2536 goto err;
2537 }
d7dc1003 2538
2111ac0d
BR		 2539 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2540
ac559526
BR		 2541 ah->ah_cal_next_full = jiffies;
2542 ah->ah_cal_next_ani = jiffies;
afe86286 2543 ah->ah_cal_next_nf = jiffies;
eef39bef 2544 ewma_init(&ah->ah_beacon_rssi_avg, 1000, 8);
afe86286 2545
fa1c114f 2546 /*
d7dc1003
JS		 2547 * Change channels and update the h/w rate map if we're switching;
2548 * e.g. 11a to 11b/g.
2549 *
2550 * We may be doing a reset in response to an ioctl that changes the
2551 * channel so update any state that might change as a result.
fa1c114f
JS		 2552 *
2553 * XXX needed?
2554 */
2555/* ath5k_chan_change(sc, c); */
fa1c114f 2556
d7dc1003
JS		 2557 ath5k_beacon_config(sc);
2558 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2559
397f385b
BR		 2560 ieee80211_wake_queues(sc->hw);
2561
fa1c114f
JS		 2562 return 0;
2563err:
2564 return ret;
2565}
2566
5faaff74
BC		 2567static void ath5k_reset_work(struct work_struct *work)
2568{
2569 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2570 reset_work);
2571
2572 mutex_lock(&sc->lock);
8aec7af9 2573 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2574 mutex_unlock(&sc->lock);
2575}
2576
8a63facc
BC		 2577static int
2578ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
fa1c114f
JS		 2579{
2580 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2581 struct ath5k_hw *ah = sc->ah;
2582 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2583 struct ath5k_txq *txq;
8a63facc 2584 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2585 int ret;
2586
8a63facc 2587 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
fa1c114f 2588
8a63facc
BC		 2589 /*
2590 * Check if the MAC has multi-rate retry support.
2591 * We do this by trying to setup a fake extended
2592 * descriptor. MACs that don't have support will
2593 * return false w/o doing anything. MACs that do
2594 * support it will return true w/o doing anything.
2595 */
2596 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2597
8a63facc
BC		 2598 if (ret < 0)
2599 goto err;
2600 if (ret > 0)
2601 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2602
8a63facc
BC		 2603 /*
2604 * Collect the channel list. The 802.11 layer
2605 * is resposible for filtering this list based
2606 * on settings like the phy mode and regulatory
2607 * domain restrictions.
2608 */
2609 ret = ath5k_setup_bands(hw);
2610 if (ret) {
2611 ATH5K_ERR(sc, "can't get channels\n");
2612 goto err;
2613 }
67d2e2df 2614
8a63facc
BC		 2615 /* NB: setup here so ath5k_rate_update is happy */
2616 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2617 ath5k_setcurmode(sc, AR5K_MODE_11A);
2618 else
2619 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2620
8a63facc
BC		 2621 /*
2622 * Allocate tx+rx descriptors and populate the lists.
2623 */
aeae4ac9 2624 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2625 if (ret) {
2626 ATH5K_ERR(sc, "can't allocate descriptors\n");
2627 goto err;
2628 }
fa1c114f 2629
8a63facc
BC		 2630 /*
2631 * Allocate hardware transmit queues: one queue for
2632 * beacon frames and one data queue for each QoS
2633 * priority. Note that hw functions handle resetting
2634 * these queues at the needed time.
2635 */
2636 ret = ath5k_beaconq_setup(ah);
2637 if (ret < 0) {
2638 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2639 goto err_desc;
2640 }
2641 sc->bhalq = ret;
2642 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2643 if (IS_ERR(sc->cabq)) {
2644 ATH5K_ERR(sc, "can't setup cab queue\n");
2645 ret = PTR_ERR(sc->cabq);
2646 goto err_bhal;
2647 }
fa1c114f 2648
925e0b06
BR		 2649 /* This order matches mac80211's queue priority, so we can
2650 * directly use the mac80211 queue number without any mapping */
2651 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2652 if (IS_ERR(txq)) {
2653 ATH5K_ERR(sc, "can't setup xmit queue\n");
2654 ret = PTR_ERR(txq);
2655 goto err_queues;
2656 }
2657 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2658 if (IS_ERR(txq)) {
8a63facc 2659 ATH5K_ERR(sc, "can't setup xmit queue\n");
925e0b06 2660 ret = PTR_ERR(txq);
8a63facc
BC		 2661 goto err_queues;
2662 }
925e0b06
BR		 2663 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2664 if (IS_ERR(txq)) {
2665 ATH5K_ERR(sc, "can't setup xmit queue\n");
2666 ret = PTR_ERR(txq);
2667 goto err_queues;
2668 }
2669 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2670 if (IS_ERR(txq)) {
2671 ATH5K_ERR(sc, "can't setup xmit queue\n");
2672 ret = PTR_ERR(txq);
2673 goto err_queues;
2674 }
2675 hw->queues = 4;
fa1c114f 2676
8a63facc
BC		 2677 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2678 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2679 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2680 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2681 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2682
8a63facc 2683 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2684 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2685
8a63facc
BC		 2686 ret = ath5k_eeprom_read_mac(ah, mac);
2687 if (ret) {
aeae4ac9 2688 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2689 goto err_queues;
e30eb4ab 2690 }
2bed03eb 2691
8a63facc 2692 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2693 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2694 /* All MAC address bits matter for ACKs */
62c58fb4 2695 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2696
2697 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2698 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2699 if (ret) {
2700 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2701 goto err_queues;
2702 }
2703
2704 ret = ieee80211_register_hw(hw);
2705 if (ret) {
2706 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2707 goto err_queues;
2708 }
2709
2710 if (!ath_is_world_regd(regulatory))
2711 regulatory_hint(hw->wiphy, regulatory->alpha2);
2712
2713 ath5k_init_leds(sc);
2714
2715 ath5k_sysfs_register(sc);
2716
2717 return 0;
2718err_queues:
2719 ath5k_txq_release(sc);
2720err_bhal:
2721 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2722err_desc:
aeae4ac9 2723 ath5k_desc_free(sc);
8a63facc
BC		 2724err:
2725 return ret;
2726}
2727
2728static void
2729ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2730{
2731 struct ath5k_softc *sc = hw->priv;
2732
2733 /*
2734 * NB: the order of these is important:
2735 * o call the 802.11 layer before detaching ath5k_hw to
2736 * ensure callbacks into the driver to delete global
2737 * key cache entries can be handled
2738 * o reclaim the tx queue data structures after calling
2739 * the 802.11 layer as we'll get called back to reclaim
2740 * node state and potentially want to use them
2741 * o to cleanup the tx queues the hal is called, so detach
2742 * it last
2743 * XXX: ??? detach ath5k_hw ???
2744 * Other than that, it's straightforward...
2745 */
2746 ieee80211_unregister_hw(hw);
aeae4ac9 2747 ath5k_desc_free(sc);
8a63facc
BC		 2748 ath5k_txq_release(sc);
2749 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2750 ath5k_unregister_leds(sc);
2751
2752 ath5k_sysfs_unregister(sc);
2753 /*
2754 * NB: can't reclaim these until after ieee80211_ifdetach
2755 * returns because we'll get called back to reclaim node
2756 * state and potentially want to use them.
2757 */
2758}
2759
2760/********************\
2761* Mac80211 functions *
2762\********************/
2763
2764static int
2765ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2766{
2767 struct ath5k_softc *sc = hw->priv;
925e0b06
BR		 2768 u16 qnum = skb_get_queue_mapping(skb);
2769
2770 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2771 dev_kfree_skb_any(skb);
2772 return 0;
2773 }
8a63facc 2774
925e0b06 2775 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
8a63facc
BC		 2776}
2777
2778static int ath5k_start(struct ieee80211_hw *hw)
2779{
2780 return ath5k_init(hw->priv);
2781}
2782
2783static void ath5k_stop(struct ieee80211_hw *hw)
2784{
2785 ath5k_stop_hw(hw->priv);
2786}
2787
2788static int ath5k_add_interface(struct ieee80211_hw *hw,
2789 struct ieee80211_vif *vif)
2790{
2791 struct ath5k_softc *sc = hw->priv;
2792 int ret;
b1ae1edf 2793 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 2794
2795 mutex_lock(&sc->lock);
b1ae1edf
BG		 2796
2797 if ((vif->type == NL80211_IFTYPE_AP ||
2798 vif->type == NL80211_IFTYPE_ADHOC)
2799 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
2800 ret = -ELNRNG;
8a63facc
BC		 2801 goto end;
2802 }
2803
b1ae1edf
BG		 2804 /* Don't allow other interfaces if one ad-hoc is configured.
2805 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2806 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2807 * for the IBSS, but this breaks with additional AP or STA interfaces
2808 * at the moment. */
2809 if (sc->num_adhoc_vifs ||
2810 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
2811 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
2812 ret = -ELNRNG;
2813 goto end;
2814 }
8a63facc
BC		 2815
2816 switch (vif->type) {
2817 case NL80211_IFTYPE_AP:
2818 case NL80211_IFTYPE_STATION:
2819 case NL80211_IFTYPE_ADHOC:
2820 case NL80211_IFTYPE_MESH_POINT:
b1ae1edf 2821 avf->opmode = vif->type;
8a63facc
BC		 2822 break;
2823 default:
2824 ret = -EOPNOTSUPP;
2825 goto end;
2826 }
2827
b1ae1edf
BG		 2828 sc->nvifs++;
2829 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
8a63facc 2830
b1ae1edf
BG		 2831 /* Assign the vap/adhoc to a beacon xmit slot. */
2832 if ((avf->opmode == NL80211_IFTYPE_AP) ||
2833 (avf->opmode == NL80211_IFTYPE_ADHOC)) {
2834 int slot;
2835
2836 WARN_ON(list_empty(&sc->bcbuf));
2837 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
2838 list);
2839 list_del(&avf->bbuf->list);
2840
2841 avf->bslot = 0;
2842 for (slot = 0; slot < ATH_BCBUF; slot++) {
2843 if (!sc->bslot[slot]) {
2844 avf->bslot = slot;
2845 break;
2846 }
2847 }
2848 BUG_ON(sc->bslot[avf->bslot] != NULL);
2849 sc->bslot[avf->bslot] = vif;
2850 if (avf->opmode == NL80211_IFTYPE_AP)
2851 sc->num_ap_vifs++;
2852 else
2853 sc->num_adhoc_vifs++;
2854 }
2855
b1ae1edf
BG		 2856 /* Any MAC address is fine, all others are included through the
2857 * filter.
2858 */
2859 memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
8a63facc 2860 ath5k_hw_set_lladdr(sc->ah, vif->addr);
b1ae1edf
BG		 2861
2862 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
2863
2864 ath5k_mode_setup(sc, vif);
8a63facc
BC		 2865
2866 ret = 0;
2867end:
2868 mutex_unlock(&sc->lock);
2869 return ret;
2870}
2871
2872static void
2873ath5k_remove_interface(struct ieee80211_hw *hw,
2874 struct ieee80211_vif *vif)
2875{
2876 struct ath5k_softc *sc = hw->priv;
b1ae1edf
BG		 2877 struct ath5k_vif *avf = (void *)vif->drv_priv;
2878 unsigned int i;
8a63facc
BC		 2879
2880 mutex_lock(&sc->lock);
b1ae1edf
BG		 2881 sc->nvifs--;
2882
2883 if (avf->bbuf) {
2884 ath5k_txbuf_free_skb(sc, avf->bbuf);
2885 list_add_tail(&avf->bbuf->list, &sc->bcbuf);
2886 for (i = 0; i < ATH_BCBUF; i++) {
2887 if (sc->bslot[i] == vif) {
2888 sc->bslot[i] = NULL;
2889 break;
2890 }
2891 }
2892 avf->bbuf = NULL;
2893 }
2894 if (avf->opmode == NL80211_IFTYPE_AP)
2895 sc->num_ap_vifs--;
2896 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
2897 sc->num_adhoc_vifs--;
8a63facc 2898
62c58fb4 2899 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2900 mutex_unlock(&sc->lock);
2901}
2902
2903/*
2904 * TODO: Phy disable/diversity etc
2905 */
2906static int
2907ath5k_config(struct ieee80211_hw *hw, u32 changed)
2908{
2909 struct ath5k_softc *sc = hw->priv;
2910 struct ath5k_hw *ah = sc->ah;
2911 struct ieee80211_conf *conf = &hw->conf;
2912 int ret = 0;
2913
2914 mutex_lock(&sc->lock);
2915
2916 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2917 ret = ath5k_chan_set(sc, conf->channel);
2918 if (ret < 0)
2919 goto unlock;
2920 }
2921
2922 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2923 (sc->power_level != conf->power_level)) {
a0823810
NK		 2924 sc->power_level = conf->power_level;
2925
2926 /* Half dB steps */
2927 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2928 }
fa1c114f 2929
2bed03eb
NK		 2930 /* TODO:
2931 * 1) Move this on config_interface and handle each case
2932 * separately eg. when we have only one STA vif, use
2933 * AR5K_ANTMODE_SINGLE_AP
2934 *
2935 * 2) Allow the user to change antenna mode eg. when only
2936 * one antenna is present
2937 *
2938 * 3) Allow the user to set default/tx antenna when possible
2939 *
2940 * 4) Default mode should handle 90% of the cases, together
2941 * with fixed a/b and single AP modes we should be able to
2942 * handle 99%. Sectored modes are extreme cases and i still
2943 * haven't found a usage for them. If we decide to support them,
2944 * then we must allow the user to set how many tx antennas we
2945 * have available
2946 */
caec9112 2947 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 2948
55aa4e0f 2949unlock:
be009370 2950 mutex_unlock(&sc->lock);
55aa4e0f 2951 return ret;
fa1c114f
JS		 2952}
2953
3ac64bee 2954static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 2955 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 2956{
2957 u32 mfilt[2], val;
3ac64bee 2958 u8 pos;
22bedad3 2959 struct netdev_hw_addr *ha;
3ac64bee
JB		 2960
2961 mfilt[0] = 0;
2962 mfilt[1] = 1;
2963
22bedad3 2964 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 2965 /* calculate XOR of eight 6-bit values */
22bedad3 2966 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 2967 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 2968 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 2969 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2970 pos &= 0x3f;
2971 mfilt[pos / 32] |= (1 << (pos % 32));
2972 /* XXX: we might be able to just do this instead,
2973 * but not sure, needs testing, if we do use this we'd
2974 * neet to inform below to not reset the mcast */
2975 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 2976 * ha->addr[5]); */
3ac64bee
JB		 2977 }
2978
2979 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2980}
2981
b1ae1edf
BG		 2982static bool ath_any_vif_assoc(struct ath5k_softc *sc)
2983{
2984 struct ath_vif_iter_data iter_data;
2985 iter_data.hw_macaddr = NULL;
2986 iter_data.any_assoc = false;
2987 iter_data.need_set_hw_addr = false;
2988 iter_data.found_active = true;
2989
2990 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
2991 &iter_data);
2992 return iter_data.any_assoc;
2993}
2994
fa1c114f
JS		 2995#define SUPPORTED_FIF_FLAGS \
2996 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2997 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2998 FIF_BCN_PRBRESP_PROMISC
2999/*
3000 * o always accept unicast, broadcast, and multicast traffic
3001 * o multicast traffic for all BSSIDs will be enabled if mac80211
3002 * says it should be
3003 * o maintain current state of phy ofdm or phy cck error reception.
3004 * If the hardware detects any of these type of errors then
3005 * ath5k_hw_get_rx_filter() will pass to us the respective
3006 * hardware filters to be able to receive these type of frames.
3007 * o probe request frames are accepted only when operating in
3008 * hostap, adhoc, or monitor modes
3009 * o enable promiscuous mode according to the interface state
3010 * o accept beacons:
3011 * - when operating in adhoc mode so the 802.11 layer creates
3012 * node table entries for peers,
3013 * - when operating in station mode for collecting rssi data when
3014 * the station is otherwise quiet, or
3015 * - when scanning
3016 */
3017static void ath5k_configure_filter(struct ieee80211_hw *hw,
3018 unsigned int changed_flags,
3019 unsigned int *new_flags,
3ac64bee 3020 u64 multicast)
fa1c114f
JS		 3021{
3022 struct ath5k_softc *sc = hw->priv;
3023 struct ath5k_hw *ah = sc->ah;
3ac64bee 3024 u32 mfilt[2], rfilt;
fa1c114f 3025
56d1de0a
BC		 3026 mutex_lock(&sc->lock);
3027
3ac64bee
JB		 3028 mfilt[0] = multicast;
3029 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3030
3031 /* Only deal with supported flags */
3032 changed_flags &= SUPPORTED_FIF_FLAGS;
3033 *new_flags &= SUPPORTED_FIF_FLAGS;
3034
3035 /* If HW detects any phy or radar errors, leave those filters on.
3036 * Also, always enable Unicast, Broadcasts and Multicast
3037 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3038 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3039 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3040 AR5K_RX_FILTER_MCAST);
3041
3042 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3043 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 3044 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3045 } else {
fa1c114f 3046 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3047 }
fa1c114f
JS		 3048 }
3049
6b5dcccb
BC		 3050 if (test_bit(ATH_STAT_PROMISC, sc->status))
3051 rfilt |= AR5K_RX_FILTER_PROM;
3052
fa1c114f
JS		 3053 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3054 if (*new_flags & FIF_ALLMULTI) {
3055 mfilt[0] = ~0;
3056 mfilt[1] = ~0;
fa1c114f
JS		 3057 }
3058
3059 /* This is the best we can do */
3060 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3061 rfilt |= AR5K_RX_FILTER_PHYERR;
3062
3063 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
30bf4169 3064 * and probes for any BSSID */
b1ae1edf 3065 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
30bf4169 3066 rfilt |= AR5K_RX_FILTER_BEACON;
fa1c114f
JS		 3067
3068 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3069 * set we should only pass on control frames for this
3070 * station. This needs testing. I believe right now this
3071 * enables *all* control frames, which is OK.. but
3072 * but we should see if we can improve on granularity */
3073 if (*new_flags & FIF_CONTROL)
3074 rfilt |= AR5K_RX_FILTER_CONTROL;
3075
3076 /* Additional settings per mode -- this is per ath5k */
3077
3078 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3079
56d1de0a
BC		 3080 switch (sc->opmode) {
3081 case NL80211_IFTYPE_MESH_POINT:
56d1de0a
BC		 3082 rfilt |= AR5K_RX_FILTER_CONTROL |
3083 AR5K_RX_FILTER_BEACON |
3084 AR5K_RX_FILTER_PROBEREQ |
3085 AR5K_RX_FILTER_PROM;
3086 break;
3087 case NL80211_IFTYPE_AP:
3088 case NL80211_IFTYPE_ADHOC:
3089 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3090 AR5K_RX_FILTER_BEACON;
3091 break;
3092 case NL80211_IFTYPE_STATION:
3093 if (sc->assoc)
3094 rfilt |= AR5K_RX_FILTER_BEACON;
3095 default:
3096 break;
3097 }
fa1c114f
JS		 3098
3099 /* Set filters */
0bbac08f 3100 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3101
3102 /* Set multicast bits */
3103 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
a180a130 3104 /* Set the cached hw filter flags, this will later actually
fa1c114f
JS		 3105 * be set in HW */
3106 sc->filter_flags = rfilt;
56d1de0a
BC		 3107
3108 mutex_unlock(&sc->lock);
fa1c114f
JS		 3109}
3110
3111static int
3112ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3113 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3114 struct ieee80211_key_conf *key)
fa1c114f
JS		 3115{
3116 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3117 struct ath5k_hw *ah = sc->ah;
3118 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3119 int ret = 0;
3120
9ad9a26e
BC		 3121 if (modparam_nohwcrypt)
3122 return -EOPNOTSUPP;
3123
97359d12
JB		 3124 switch (key->cipher) {
3125 case WLAN_CIPHER_SUITE_WEP40:
3126 case WLAN_CIPHER_SUITE_WEP104:
3127 case WLAN_CIPHER_SUITE_TKIP:
3f64b435 3128 break;
97359d12 3129 case WLAN_CIPHER_SUITE_CCMP:
781f3136 3130 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
1c818740 3131 break;
fa1c114f
JS		 3132 return -EOPNOTSUPP;
3133 default:
3134 WARN_ON(1);
3135 return -EINVAL;
3136 }
3137
3138 mutex_lock(&sc->lock);
3139
3140 switch (cmd) {
3141 case SET_KEY:
e0f8c2a9
BR		 3142 ret = ath_key_config(common, vif, sta, key);
3143 if (ret >= 0) {
3144 key->hw_key_idx = ret;
3145 /* push IV and Michael MIC generation to stack */
3146 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3147 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3148 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3149 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3150 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3151 ret = 0;
fa1c114f 3152 }
fa1c114f
JS		 3153 break;
3154 case DISABLE_KEY:
e0f8c2a9 3155 ath_key_delete(common, key);
fa1c114f
JS		 3156 break;
3157 default:
3158 ret = -EINVAL;
fa1c114f
JS		 3159 }
3160
8a63facc
BC		 3161 mmiowb();
3162 mutex_unlock(&sc->lock);
3163 return ret;
3164}
3165
3166static int
3167ath5k_get_stats(struct ieee80211_hw *hw,
3168 struct ieee80211_low_level_stats *stats)
3169{
3170 struct ath5k_softc *sc = hw->priv;
3171
3172 /* Force update */
3173 ath5k_hw_update_mib_counters(sc->ah);
3174
3175 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3176 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3177 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3178 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3179
3180 return 0;
3181}
3182
3183static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3184 struct survey_info *survey)
3185{
3186 struct ath5k_softc *sc = hw->priv;
3187 struct ieee80211_conf *conf = &hw->conf;
edb40a23
BR		 3188 struct ath_common *common = ath5k_hw_common(sc->ah);
3189 struct ath_cycle_counters *cc = &common->cc_survey;
3190 unsigned int div = common->clockrate * 1000;
8a63facc 3191
edb40a23 3192 if (idx != 0)
8a63facc
BC		 3193 return -ENOENT;
3194
3195 survey->channel = conf->channel;
3196 survey->filled = SURVEY_INFO_NOISE_DBM;
3197 survey->noise = sc->ah->ah_noise_floor;
3198
edb40a23
BR		 3199 spin_lock_bh(&common->cc_lock);
3200 ath_hw_cycle_counters_update(common);
3201 if (cc->cycles > 0) {
3202 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
3203 SURVEY_INFO_CHANNEL_TIME_BUSY |
3204 SURVEY_INFO_CHANNEL_TIME_RX |
3205 SURVEY_INFO_CHANNEL_TIME_TX;
3206 survey->channel_time += cc->cycles / div;
3207 survey->channel_time_busy += cc->rx_busy / div;
3208 survey->channel_time_rx += cc->rx_frame / div;
3209 survey->channel_time_tx += cc->tx_frame / div;
3210 }
3211 memset(cc, 0, sizeof(*cc));
3212 spin_unlock_bh(&common->cc_lock);
3213
8a63facc
BC		 3214 return 0;
3215}
3216
3217static u64
3218ath5k_get_tsf(struct ieee80211_hw *hw)
3219{
3220 struct ath5k_softc *sc = hw->priv;
3221
3222 return ath5k_hw_get_tsf64(sc->ah);
3223}
3224
3225static void
3226ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3227{
3228 struct ath5k_softc *sc = hw->priv;
3229
3230 ath5k_hw_set_tsf64(sc->ah, tsf);
3231}
3232
3233static void
3234ath5k_reset_tsf(struct ieee80211_hw *hw)
3235{
3236 struct ath5k_softc *sc = hw->priv;
3237
3238 /*
3239 * in IBSS mode we need to update the beacon timers too.
3240 * this will also reset the TSF if we call it with 0
3241 */
3242 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3243 ath5k_beacon_update_timers(sc, 0);
3244 else
3245 ath5k_hw_reset_tsf(sc->ah);
3246}
3247
3248static void
3249set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3250{
3251 struct ath5k_softc *sc = hw->priv;
3252 struct ath5k_hw *ah = sc->ah;
3253 u32 rfilt;
3254 rfilt = ath5k_hw_get_rx_filter(ah);
3255 if (enable)
3256 rfilt |= AR5K_RX_FILTER_BEACON;
3257 else
3258 rfilt &= ~AR5K_RX_FILTER_BEACON;
3259 ath5k_hw_set_rx_filter(ah, rfilt);
3260 sc->filter_flags = rfilt;
3261}
3262
3263static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3264 struct ieee80211_vif *vif,
3265 struct ieee80211_bss_conf *bss_conf,
3266 u32 changes)
3267{
b1ae1edf 3268 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 3269 struct ath5k_softc *sc = hw->priv;
3270 struct ath5k_hw *ah = sc->ah;
3271 struct ath_common *common = ath5k_hw_common(ah);
3272 unsigned long flags;
3273
3274 mutex_lock(&sc->lock);
8a63facc
BC		 3275
3276 if (changes & BSS_CHANGED_BSSID) {
3277 /* Cache for later use during resets */
3278 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3279 common->curaid = 0;
3280 ath5k_hw_set_bssid(ah);
3281 mmiowb();
3282 }
3283
3284 if (changes & BSS_CHANGED_BEACON_INT)
3285 sc->bintval = bss_conf->beacon_int;
3286
3287 if (changes & BSS_CHANGED_ASSOC) {
b1ae1edf
BG		 3288 avf->assoc = bss_conf->assoc;
3289 if (bss_conf->assoc)
3290 sc->assoc = bss_conf->assoc;
3291 else
3292 sc->assoc = ath_any_vif_assoc(sc);
3293
8a63facc
BC		 3294 if (sc->opmode == NL80211_IFTYPE_STATION)
3295 set_beacon_filter(hw, sc->assoc);
3296 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3297 AR5K_LED_ASSOC : AR5K_LED_INIT);
3298 if (bss_conf->assoc) {
3299 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3300 "Bss Info ASSOC %d, bssid: %pM\n",
3301 bss_conf->aid, common->curbssid);
3302 common->curaid = bss_conf->aid;
3303 ath5k_hw_set_bssid(ah);
3304 /* Once ANI is available you would start it here */
3305 }
3306 }
3307
3308 if (changes & BSS_CHANGED_BEACON) {
3309 spin_lock_irqsave(&sc->block, flags);
3310 ath5k_beacon_update(hw, vif);
3311 spin_unlock_irqrestore(&sc->block, flags);
3312 }
3313
3314 if (changes & BSS_CHANGED_BEACON_ENABLED)
3315 sc->enable_beacon = bss_conf->enable_beacon;
3316
3317 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3318 BSS_CHANGED_BEACON_INT))
3319 ath5k_beacon_config(sc);
3320
8a63facc
BC		 3321 mutex_unlock(&sc->lock);
3322}
3323
3324static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3325{
3326 struct ath5k_softc *sc = hw->priv;
3327 if (!sc->assoc)
3328 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3329}
3330
3331static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3332{
3333 struct ath5k_softc *sc = hw->priv;
3334 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3335 AR5K_LED_ASSOC : AR5K_LED_INIT);
3336}
3337
3338/**
3339 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3340 *
3341 * @hw: struct ieee80211_hw pointer
3342 * @coverage_class: IEEE 802.11 coverage class number
3343 *
3344 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3345 * coverage class. The values are persistent, they are restored after device
3346 * reset.
3347 */
3348static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3349{
3350 struct ath5k_softc *sc = hw->priv;
3351
3352 mutex_lock(&sc->lock);
3353 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3354 mutex_unlock(&sc->lock);
3355}
3356
e0b1cc52
BR		 3357static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3358 const struct ieee80211_tx_queue_params *params)
3359{
3360 struct ath5k_softc *sc = hw->priv;
3361 struct ath5k_hw *ah = sc->ah;
3362 struct ath5k_txq_info qi;
3363 int ret = 0;
3364
3365 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3366 return 0;
3367
3368 mutex_lock(&sc->lock);
3369
3370 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3371
3372 qi.tqi_aifs = params->aifs;
3373 qi.tqi_cw_min = params->cw_min;
3374 qi.tqi_cw_max = params->cw_max;
3375 qi.tqi_burst_time = params->txop;
3376
3377 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3378 "Configure tx [queue %d], "
3379 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3380 queue, params->aifs, params->cw_min,
3381 params->cw_max, params->txop);
3382
3383 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3384 ATH5K_ERR(sc,
3385 "Unable to update hardware queue %u!\n", queue);
3386 ret = -EIO;
3387 } else
3388 ath5k_hw_reset_tx_queue(ah, queue);
3389
3390 mutex_unlock(&sc->lock);
3391
3392 return ret;
3393}
3394
72a80110
BR		 3395static int ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
3396{
3397 struct ath5k_softc *sc = hw->priv;
3398
3399 if (tx_ant == 1 && rx_ant == 1)
3400 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
3401 else if (tx_ant == 2 && rx_ant == 2)
3402 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
3403 else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
3404 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
3405 else
3406 return -EINVAL;
3407 return 0;
3408}
3409
3410static int ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
3411{
3412 struct ath5k_softc *sc = hw->priv;
3413
3414 switch (sc->ah->ah_ant_mode) {
3415 case AR5K_ANTMODE_FIXED_A:
3416 *tx_ant = 1; *rx_ant = 1; break;
3417 case AR5K_ANTMODE_FIXED_B:
3418 *tx_ant = 2; *rx_ant = 2; break;
3419 case AR5K_ANTMODE_DEFAULT:
3420 *tx_ant = 3; *rx_ant = 3; break;
3421 }
3422 return 0;
3423}
3424
8a63facc
BC		 3425static const struct ieee80211_ops ath5k_hw_ops = {
3426 .tx = ath5k_tx,
3427 .start = ath5k_start,
3428 .stop = ath5k_stop,
3429 .add_interface = ath5k_add_interface,
3430 .remove_interface = ath5k_remove_interface,
3431 .config = ath5k_config,
3432 .prepare_multicast = ath5k_prepare_multicast,
3433 .configure_filter = ath5k_configure_filter,
3434 .set_key = ath5k_set_key,
3435 .get_stats = ath5k_get_stats,
3436 .get_survey = ath5k_get_survey,
e0b1cc52 3437 .conf_tx = ath5k_conf_tx,
8a63facc
BC		 3438 .get_tsf = ath5k_get_tsf,
3439 .set_tsf = ath5k_set_tsf,
3440 .reset_tsf = ath5k_reset_tsf,
3441 .bss_info_changed = ath5k_bss_info_changed,
3442 .sw_scan_start = ath5k_sw_scan_start,
3443 .sw_scan_complete = ath5k_sw_scan_complete,
3444 .set_coverage_class = ath5k_set_coverage_class,
72a80110
BR		 3445 .set_antenna = ath5k_set_antenna,
3446 .get_antenna = ath5k_get_antenna,
8a63facc
BC		 3447};
3448
3449/********************\
3450* PCI Initialization *
3451\********************/
3452
3453static int __devinit
3454ath5k_pci_probe(struct pci_dev *pdev,
3455 const struct pci_device_id *id)
3456{
3457 void __iomem *mem;
3458 struct ath5k_softc *sc;
3459 struct ath_common *common;
3460 struct ieee80211_hw *hw;
3461 int ret;
3462 u8 csz;
3463
3464 /*
3465 * L0s needs to be disabled on all ath5k cards.
3466 *
3467 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3468 * by default in the future in 2.6.36) this will also mean both L1 and
3469 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3470 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3471 * though but cannot currently undue the effect of a blacklist, for
3472 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3473 * the device link capability.
3474 *
3475 * It may be possible in the future to implement some PCI API to allow
3476 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3477 * best to accept that both L0s and L1 will be disabled completely for
3478 * distributions shipping with CONFIG_PCIEASPM rather than having this
3479 * issue present. Motivation for adding this new API will be to help
3480 * with power consumption for some of these devices.
3481 */
3482 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
3483
3484 ret = pci_enable_device(pdev);
3485 if (ret) {
3486 dev_err(&pdev->dev, "can't enable device\n");
3487 goto err;
3488 }
3489
3490 /* XXX 32-bit addressing only */
3491 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3492 if (ret) {
3493 dev_err(&pdev->dev, "32-bit DMA not available\n");
3494 goto err_dis;
3495 }
3496
3497 /*
3498 * Cache line size is used to size and align various
3499 * structures used to communicate with the hardware.
3500 */
3501 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
3502 if (csz == 0) {
3503 /*
3504 * Linux 2.4.18 (at least) writes the cache line size
3505 * register as a 16-bit wide register which is wrong.
3506 * We must have this setup properly for rx buffer
3507 * DMA to work so force a reasonable value here if it
3508 * comes up zero.
3509 */
3510 csz = L1_CACHE_BYTES >> 2;
3511 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
3512 }
3513 /*
3514 * The default setting of latency timer yields poor results,
3515 * set it to the value used by other systems. It may be worth
3516 * tweaking this setting more.
3517 */
3518 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
3519
3520 /* Enable bus mastering */
3521 pci_set_master(pdev);
3522
3523 /*
3524 * Disable the RETRY_TIMEOUT register (0x41) to keep
3525 * PCI Tx retries from interfering with C3 CPU state.
3526 */
3527 pci_write_config_byte(pdev, 0x41, 0);
3528
3529 ret = pci_request_region(pdev, 0, "ath5k");
3530 if (ret) {
3531 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
3532 goto err_dis;
3533 }
3534
3535 mem = pci_iomap(pdev, 0, 0);
3536 if (!mem) {
3537 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
3538 ret = -EIO;
3539 goto err_reg;
3540 }
3541
3542 /*
3543 * Allocate hw (mac80211 main struct)
3544 * and hw->priv (driver private data)
3545 */
3546 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
3547 if (hw == NULL) {
3548 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
3549 ret = -ENOMEM;
3550 goto err_map;
3551 }
3552
3553 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
3554
3555 /* Initialize driver private data */
3556 SET_IEEE80211_DEV(hw, &pdev->dev);
3557 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3558 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3559 IEEE80211_HW_SIGNAL_DBM;
3560
3561 hw->wiphy->interface_modes =
3562 BIT(NL80211_IFTYPE_AP) |
3563 BIT(NL80211_IFTYPE_STATION) |
3564 BIT(NL80211_IFTYPE_ADHOC) |
3565 BIT(NL80211_IFTYPE_MESH_POINT);
3566
3567 hw->extra_tx_headroom = 2;
3568 hw->channel_change_time = 5000;
3569 sc = hw->priv;
3570 sc->hw = hw;
3571 sc->pdev = pdev;
aeae4ac9
FF		 3572 sc->dev = &pdev->dev;
3573 sc->irq = pdev->irq;
8a63facc 3574
8a63facc
BC		 3575 /*
3576 * Mark the device as detached to avoid processing
3577 * interrupts until setup is complete.
3578 */
3579 __set_bit(ATH_STAT_INVALID, sc->status);
3580
3581 sc->iobase = mem; /* So we can unmap it on detach */
3582 sc->opmode = NL80211_IFTYPE_STATION;
3583 sc->bintval = 1000;
3584 mutex_init(&sc->lock);
3585 spin_lock_init(&sc->rxbuflock);
3586 spin_lock_init(&sc->txbuflock);
3587 spin_lock_init(&sc->block);
3588
3589 /* Set private data */
3590 pci_set_drvdata(pdev, sc);
3591
3592 /* Setup interrupt handler */
3593 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
3594 if (ret) {
3595 ATH5K_ERR(sc, "request_irq failed\n");
3596 goto err_free;
3597 }
3598
3599 /* If we passed the test, malloc an ath5k_hw struct */
3600 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
3601 if (!sc->ah) {
3602 ret = -ENOMEM;
3603 ATH5K_ERR(sc, "out of memory\n");
3604 goto err_irq;
3605 }
3606
3607 sc->ah->ah_sc = sc;
3608 sc->ah->ah_iobase = sc->iobase;
3609 common = ath5k_hw_common(sc->ah);
3610 common->ops = &ath5k_common_ops;
3611 common->ah = sc->ah;
3612 common->hw = hw;
3613 common->cachelsz = csz << 2; /* convert to bytes */
9192f715 3614 spin_lock_init(&common->cc_lock);
8a63facc
BC		 3615
3616 /* Initialize device */
3617 ret = ath5k_hw_attach(sc);
3618 if (ret) {
3619 goto err_free_ah;
3620 }
3621
3622 /* set up multi-rate retry capabilities */
3623 if (sc->ah->ah_version == AR5K_AR5212) {
3624 hw->max_rates = 4;
3625 hw->max_rate_tries = 11;
3626 }
3627
b1ae1edf
BG		 3628 hw->vif_data_size = sizeof(struct ath5k_vif);
3629
8a63facc
BC		 3630 /* Finish private driver data initialization */
3631 ret = ath5k_attach(pdev, hw);
3632 if (ret)
3633 goto err_ah;
3634
3635 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3636 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
3637 sc->ah->ah_mac_srev,
3638 sc->ah->ah_phy_revision);
3639
3640 if (!sc->ah->ah_single_chip) {
3641 /* Single chip radio (!RF5111) */
3642 if (sc->ah->ah_radio_5ghz_revision &&
3643 !sc->ah->ah_radio_2ghz_revision) {
3644 /* No 5GHz support -> report 2GHz radio */
3645 if (!test_bit(AR5K_MODE_11A,
3646 sc->ah->ah_capabilities.cap_mode)) {
3647 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3648 ath5k_chip_name(AR5K_VERSION_RAD,
3649 sc->ah->ah_radio_5ghz_revision),
3650 sc->ah->ah_radio_5ghz_revision);
3651 /* No 2GHz support (5110 and some
3652 * 5Ghz only cards) -> report 5Ghz radio */
3653 } else if (!test_bit(AR5K_MODE_11B,
3654 sc->ah->ah_capabilities.cap_mode)) {
3655 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3656 ath5k_chip_name(AR5K_VERSION_RAD,
3657 sc->ah->ah_radio_5ghz_revision),
3658 sc->ah->ah_radio_5ghz_revision);
3659 /* Multiband radio */
3660 } else {
3661 ATH5K_INFO(sc, "RF%s multiband radio found"
3662 " (0x%x)\n",
3663 ath5k_chip_name(AR5K_VERSION_RAD,
3664 sc->ah->ah_radio_5ghz_revision),
3665 sc->ah->ah_radio_5ghz_revision);
3666 }
3667 }
3668 /* Multi chip radio (RF5111 - RF2111) ->
3669 * report both 2GHz/5GHz radios */
3670 else if (sc->ah->ah_radio_5ghz_revision &&
3671 sc->ah->ah_radio_2ghz_revision){
3672 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3673 ath5k_chip_name(AR5K_VERSION_RAD,
3674 sc->ah->ah_radio_5ghz_revision),
3675 sc->ah->ah_radio_5ghz_revision);
3676 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3677 ath5k_chip_name(AR5K_VERSION_RAD,
3678 sc->ah->ah_radio_2ghz_revision),
3679 sc->ah->ah_radio_2ghz_revision);
3680 }
3681 }
3682
d84a35d1 3683 ath5k_debug_init_device(sc);
55ee82b5 3684
8a63facc
BC		 3685 /* ready to process interrupts */
3686 __clear_bit(ATH_STAT_INVALID, sc->status);
55ee82b5
HS		 3687
3688 return 0;
8a63facc
BC		 3689err_ah:
3690 ath5k_hw_detach(sc->ah);
3691err_free_ah:
3692 kfree(sc->ah);
3693err_irq:
3694 free_irq(pdev->irq, sc);
3695err_free:
3696 ieee80211_free_hw(hw);
3697err_map:
3698 pci_iounmap(pdev, mem);
3699err_reg:
3700 pci_release_region(pdev, 0);
3701err_dis:
3702 pci_disable_device(pdev);
3703err:
3704 return ret;
55ee82b5
HS		 3705}
3706
8a63facc
BC		 3707static void __devexit
3708ath5k_pci_remove(struct pci_dev *pdev)
fa1c114f 3709{
8a63facc 3710 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3711
8a63facc
BC		 3712 ath5k_debug_finish_device(sc);
3713 ath5k_detach(pdev, sc->hw);
3714 ath5k_hw_detach(sc->ah);
3715 kfree(sc->ah);
3716 free_irq(pdev->irq, sc);
3717 pci_iounmap(pdev, sc->iobase);
3718 pci_release_region(pdev, 0);
3719 pci_disable_device(pdev);
3720 ieee80211_free_hw(sc->hw);
fa1c114f
JS		 3721}
3722
8a63facc
BC		 3723#ifdef CONFIG_PM_SLEEP
3724static int ath5k_pci_suspend(struct device *dev)
3b5d665b 3725{
8a63facc 3726 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
3b5d665b 3727
8a63facc
BC		 3728 ath5k_led_off(sc);
3729 return 0;
3b5d665b
AF		 3730}
3731
8a63facc 3732static int ath5k_pci_resume(struct device *dev)
fa1c114f 3733{
8a63facc
BC		 3734 struct pci_dev *pdev = to_pci_dev(dev);
3735 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3736
9804b98d 3737 /*
8a63facc
BC		 3738 * Suspend/Resume resets the PCI configuration space, so we have to
3739 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3740 * PCI Tx retries from interfering with C3 CPU state
9804b98d 3741 */
8a63facc
BC		 3742 pci_write_config_byte(pdev, 0x41, 0);
3743
3744 ath5k_led_enable(sc);
3745 return 0;
fa1c114f
JS		 3746}
3747
8a63facc
BC		 3748static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
3749#define ATH5K_PM_OPS (&ath5k_pm_ops)
3750#else
3751#define ATH5K_PM_OPS NULL
3752#endif /* CONFIG_PM_SLEEP */
3753
3754static struct pci_driver ath5k_pci_driver = {
3755 .name = KBUILD_MODNAME,
3756 .id_table = ath5k_pci_id_table,
3757 .probe = ath5k_pci_probe,
3758 .remove = __devexit_p(ath5k_pci_remove),
3759 .driver.pm = ATH5K_PM_OPS,
3760};
3761
1071db86 3762/*
8a63facc 3763 * Module init/exit functions
1071db86 3764 */
8a63facc
BC		 3765static int __init
3766init_ath5k_pci(void)
fa1c114f 3767{
fa1c114f 3768 int ret;
57c4d7b4 3769
8a63facc
BC		 3770 ret = pci_register_driver(&ath5k_pci_driver);
3771 if (ret) {
3772 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
3773 return ret;
2d0ddec5
JB		 3774 }
3775
8a63facc 3776 return 0;
02969b38 3777}
f0f3d388 3778
8a63facc
BC		 3779static void __exit
3780exit_ath5k_pci(void)
f0f3d388 3781{
8a63facc 3782 pci_unregister_driver(&ath5k_pci_driver);
f0f3d388 3783}
6e08d228 3784
8a63facc
BC		 3785module_init(init_ath5k_pci);
3786module_exit(exit_ath5k_pci);
Linux kernel - Deliverables
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