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ath5k: send buffered frames after the beacon
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e 63static int modparam_nohwcrypt;
46802a4f 64module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 66
42639fcd 67static int modparam_all_channels;
46802a4f 68module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 69MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
fa1c114f
JS		 71
72/******************\
73* Internal defines *
74\******************/
75
76/* Module info */
77MODULE_AUTHOR("Jiri Slaby");
78MODULE_AUTHOR("Nick Kossifidis");
79MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 82MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 83
84
85/* Known PCI ids */
2c91108c 86static const struct pci_device_id ath5k_pci_id_table[] = {
fa1c114f
JS		 87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 105 { 0 }
106};
107MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109/* Known SREVs */
2c91108c 110static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147};
148
2c91108c 149static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189};
190
fa1c114f
JS		 191/*
192 * Prototypes - PCI stack related functions
193 */
194static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197#ifdef CONFIG_PM
198static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200static int ath5k_pci_resume(struct pci_dev *pdev);
201#else
202#define ath5k_pci_suspend NULL
203#define ath5k_pci_resume NULL
204#endif /* CONFIG_PM */
205
04a9e451 206static struct pci_driver ath5k_pci_driver = {
9764f3f9 207 .name = KBUILD_MODNAME,
fa1c114f
JS		 208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213};
214
215
216
217/*
218 * Prototypes - MAC 802.11 stack related functions
219 */
e039fa4a 220static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 221static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
209d889b 223static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 224static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 225static int ath5k_start(struct ieee80211_hw *hw);
226static void ath5k_stop(struct ieee80211_hw *hw);
227static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
e8975581 231static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
fa1c114f
JS		 232static void ath5k_configure_filter(struct ieee80211_hw *hw,
233 unsigned int changed_flags,
234 unsigned int *new_flags,
235 int mc_count, struct dev_mc_list *mclist);
236static int ath5k_set_key(struct ieee80211_hw *hw,
237 enum set_key_cmd cmd,
dc822b5d 238 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 239 struct ieee80211_key_conf *key);
240static int ath5k_get_stats(struct ieee80211_hw *hw,
241 struct ieee80211_low_level_stats *stats);
242static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
243 struct ieee80211_tx_queue_stats *stats);
244static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 245static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 246static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 247static int ath5k_beacon_update(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif);
02969b38
MX		 249static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif,
251 struct ieee80211_bss_conf *bss_conf,
252 u32 changes);
f0f3d388
BC		 253static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
254static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
fa1c114f 255
2c91108c 256static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 257 .tx = ath5k_tx,
258 .start = ath5k_start,
259 .stop = ath5k_stop,
260 .add_interface = ath5k_add_interface,
261 .remove_interface = ath5k_remove_interface,
262 .config = ath5k_config,
fa1c114f
JS		 263 .configure_filter = ath5k_configure_filter,
264 .set_key = ath5k_set_key,
265 .get_stats = ath5k_get_stats,
266 .conf_tx = NULL,
267 .get_tx_stats = ath5k_get_tx_stats,
268 .get_tsf = ath5k_get_tsf,
3b5d665b 269 .set_tsf = ath5k_set_tsf,
fa1c114f 270 .reset_tsf = ath5k_reset_tsf,
02969b38 271 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 272 .sw_scan_start = ath5k_sw_scan_start,
273 .sw_scan_complete = ath5k_sw_scan_complete,
fa1c114f
JS		 274};
275
276/*
277 * Prototypes - Internal functions
278 */
279/* Attach detach */
280static int ath5k_attach(struct pci_dev *pdev,
281 struct ieee80211_hw *hw);
282static void ath5k_detach(struct pci_dev *pdev,
283 struct ieee80211_hw *hw);
284/* Channel/mode setup */
285static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 286static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
287 struct ieee80211_channel *channels,
288 unsigned int mode,
289 unsigned int max);
63266a65 290static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 291static int ath5k_chan_set(struct ath5k_softc *sc,
292 struct ieee80211_channel *chan);
293static void ath5k_setcurmode(struct ath5k_softc *sc,
294 unsigned int mode);
295static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 296
fa1c114f
JS		 297/* Descriptor setup */
298static int ath5k_desc_alloc(struct ath5k_softc *sc,
299 struct pci_dev *pdev);
300static void ath5k_desc_free(struct ath5k_softc *sc,
301 struct pci_dev *pdev);
302/* Buffers setup */
303static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
304 struct ath5k_buf *bf);
305static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23
BC		 306 struct ath5k_buf *bf,
307 struct ath5k_txq *txq);
fa1c114f
JS		 308static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
309 struct ath5k_buf *bf)
310{
311 BUG_ON(!bf);
312 if (!bf->skb)
313 return;
314 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
315 PCI_DMA_TODEVICE);
00482973 316 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 317 bf->skb = NULL;
318}
319
a6c8d375
FF		 320static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
321 struct ath5k_buf *bf)
322{
323 BUG_ON(!bf);
324 if (!bf->skb)
325 return;
326 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
327 PCI_DMA_FROMDEVICE);
328 dev_kfree_skb_any(bf->skb);
329 bf->skb = NULL;
330}
331
332
fa1c114f
JS		 333/* Queues setup */
334static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
335 int qtype, int subtype);
336static int ath5k_beaconq_setup(struct ath5k_hw *ah);
337static int ath5k_beaconq_config(struct ath5k_softc *sc);
338static void ath5k_txq_drainq(struct ath5k_softc *sc,
339 struct ath5k_txq *txq);
340static void ath5k_txq_cleanup(struct ath5k_softc *sc);
341static void ath5k_txq_release(struct ath5k_softc *sc);
342/* Rx handling */
343static int ath5k_rx_start(struct ath5k_softc *sc);
344static void ath5k_rx_stop(struct ath5k_softc *sc);
345static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
346 struct ath5k_desc *ds,
b47f407b
BR		 347 struct sk_buff *skb,
348 struct ath5k_rx_status *rs);
fa1c114f
JS		 349static void ath5k_tasklet_rx(unsigned long data);
350/* Tx handling */
351static void ath5k_tx_processq(struct ath5k_softc *sc,
352 struct ath5k_txq *txq);
353static void ath5k_tasklet_tx(unsigned long data);
354/* Beacon handling */
355static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 356 struct ath5k_buf *bf);
fa1c114f
JS		 357static void ath5k_beacon_send(struct ath5k_softc *sc);
358static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 359static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 360static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 361
362static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
363{
364 u64 tsf = ath5k_hw_get_tsf64(ah);
365
366 if ((tsf & 0x7fff) < rstamp)
367 tsf -= 0x8000;
368
369 return (tsf & ~0x7fff) | rstamp;
370}
371
372/* Interrupt handling */
bb2becac 373static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 374static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 375static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 376static irqreturn_t ath5k_intr(int irq, void *dev_id);
377static void ath5k_tasklet_reset(unsigned long data);
378
379static void ath5k_calibrate(unsigned long data);
fa1c114f
JS		 380
381/*
382 * Module init/exit functions
383 */
384static int __init
385init_ath5k_pci(void)
386{
387 int ret;
388
389 ath5k_debug_init();
390
04a9e451 391 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 392 if (ret) {
393 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
394 return ret;
395 }
396
397 return 0;
398}
399
400static void __exit
401exit_ath5k_pci(void)
402{
04a9e451 403 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 404
405 ath5k_debug_finish();
406}
407
408module_init(init_ath5k_pci);
409module_exit(exit_ath5k_pci);
410
411
412/********************\
413* PCI Initialization *
414\********************/
415
416static const char *
417ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
418{
419 const char *name = "xxxxx";
420 unsigned int i;
421
422 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
423 if (srev_names[i].sr_type != type)
424 continue;
75d0edb8
NK		 425
426 if ((val & 0xf0) == srev_names[i].sr_val)
427 name = srev_names[i].sr_name;
428
429 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 430 name = srev_names[i].sr_name;
431 break;
432 }
433 }
434
435 return name;
436}
437
438static int __devinit
439ath5k_pci_probe(struct pci_dev *pdev,
440 const struct pci_device_id *id)
441{
442 void __iomem *mem;
443 struct ath5k_softc *sc;
444 struct ieee80211_hw *hw;
445 int ret;
446 u8 csz;
447
448 ret = pci_enable_device(pdev);
449 if (ret) {
450 dev_err(&pdev->dev, "can't enable device\n");
451 goto err;
452 }
453
454 /* XXX 32-bit addressing only */
284901a9 455 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 456 if (ret) {
457 dev_err(&pdev->dev, "32-bit DMA not available\n");
458 goto err_dis;
459 }
460
461 /*
462 * Cache line size is used to size and align various
463 * structures used to communicate with the hardware.
464 */
465 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
466 if (csz == 0) {
467 /*
468 * Linux 2.4.18 (at least) writes the cache line size
469 * register as a 16-bit wide register which is wrong.
470 * We must have this setup properly for rx buffer
471 * DMA to work so force a reasonable value here if it
472 * comes up zero.
473 */
474 csz = L1_CACHE_BYTES / sizeof(u32);
475 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
476 }
477 /*
478 * The default setting of latency timer yields poor results,
479 * set it to the value used by other systems. It may be worth
480 * tweaking this setting more.
481 */
482 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
483
484 /* Enable bus mastering */
485 pci_set_master(pdev);
486
487 /*
488 * Disable the RETRY_TIMEOUT register (0x41) to keep
489 * PCI Tx retries from interfering with C3 CPU state.
490 */
491 pci_write_config_byte(pdev, 0x41, 0);
492
493 ret = pci_request_region(pdev, 0, "ath5k");
494 if (ret) {
495 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
496 goto err_dis;
497 }
498
499 mem = pci_iomap(pdev, 0, 0);
500 if (!mem) {
501 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
502 ret = -EIO;
503 goto err_reg;
504 }
505
506 /*
507 * Allocate hw (mac80211 main struct)
508 * and hw->priv (driver private data)
509 */
510 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
511 if (hw == NULL) {
512 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
513 ret = -ENOMEM;
514 goto err_map;
515 }
516
517 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
518
519 /* Initialize driver private data */
520 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 521 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 522 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 523 IEEE80211_HW_SIGNAL_DBM |
524 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 525
526 hw->wiphy->interface_modes =
6f5f39c9 527 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 528 BIT(NL80211_IFTYPE_STATION) |
529 BIT(NL80211_IFTYPE_ADHOC) |
530 BIT(NL80211_IFTYPE_MESH_POINT);
531
fa1c114f
JS		 532 hw->extra_tx_headroom = 2;
533 hw->channel_change_time = 5000;
fa1c114f
JS		 534 sc = hw->priv;
535 sc->hw = hw;
536 sc->pdev = pdev;
537
538 ath5k_debug_init_device(sc);
539
540 /*
541 * Mark the device as detached to avoid processing
542 * interrupts until setup is complete.
543 */
544 __set_bit(ATH_STAT_INVALID, sc->status);
545
546 sc->iobase = mem; /* So we can unmap it on detach */
547 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 548 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 549 sc->bintval = 1000;
fa1c114f
JS		 550 mutex_init(&sc->lock);
551 spin_lock_init(&sc->rxbuflock);
552 spin_lock_init(&sc->txbuflock);
00482973 553 spin_lock_init(&sc->block);
fa1c114f
JS		 554
555 /* Set private data */
556 pci_set_drvdata(pdev, hw);
557
fa1c114f
JS		 558 /* Setup interrupt handler */
559 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
560 if (ret) {
561 ATH5K_ERR(sc, "request_irq failed\n");
562 goto err_free;
563 }
564
565 /* Initialize device */
566 sc->ah = ath5k_hw_attach(sc, id->driver_data);
567 if (IS_ERR(sc->ah)) {
568 ret = PTR_ERR(sc->ah);
569 goto err_irq;
570 }
571
2f7fe870
FF		 572 /* set up multi-rate retry capabilities */
573 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 574 hw->max_rates = 4;
575 hw->max_rate_tries = 11;
2f7fe870
FF		 576 }
577
fa1c114f
JS		 578 /* Finish private driver data initialization */
579 ret = ath5k_attach(pdev, hw);
580 if (ret)
581 goto err_ah;
582
583 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 584 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 585 sc->ah->ah_mac_srev,
586 sc->ah->ah_phy_revision);
587
400ec45a 588 if (!sc->ah->ah_single_chip) {
fa1c114f 589 /* Single chip radio (!RF5111) */
400ec45a
LR		 590 if (sc->ah->ah_radio_5ghz_revision &&
591 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 592 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 593 if (!test_bit(AR5K_MODE_11A,
594 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 595 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 596 ath5k_chip_name(AR5K_VERSION_RAD,
597 sc->ah->ah_radio_5ghz_revision),
598 sc->ah->ah_radio_5ghz_revision);
599 /* No 2GHz support (5110 and some
600 * 5Ghz only cards) -> report 5Ghz radio */
601 } else if (!test_bit(AR5K_MODE_11B,
602 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 603 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 604 ath5k_chip_name(AR5K_VERSION_RAD,
605 sc->ah->ah_radio_5ghz_revision),
606 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 607 /* Multiband radio */
608 } else {
609 ATH5K_INFO(sc, "RF%s multiband radio found"
610 " (0x%x)\n",
400ec45a
LR		 611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 614 }
615 }
400ec45a
LR		 616 /* Multi chip radio (RF5111 - RF2111) ->
617 * report both 2GHz/5GHz radios */
618 else if (sc->ah->ah_radio_5ghz_revision &&
619 sc->ah->ah_radio_2ghz_revision){
fa1c114f 620 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 621 ath5k_chip_name(AR5K_VERSION_RAD,
622 sc->ah->ah_radio_5ghz_revision),
623 sc->ah->ah_radio_5ghz_revision);
fa1c114f 624 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 625 ath5k_chip_name(AR5K_VERSION_RAD,
626 sc->ah->ah_radio_2ghz_revision),
627 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 628 }
629 }
630
631
632 /* ready to process interrupts */
633 __clear_bit(ATH_STAT_INVALID, sc->status);
634
635 return 0;
636err_ah:
637 ath5k_hw_detach(sc->ah);
638err_irq:
639 free_irq(pdev->irq, sc);
640err_free:
fa1c114f
JS		 641 ieee80211_free_hw(hw);
642err_map:
643 pci_iounmap(pdev, mem);
644err_reg:
645 pci_release_region(pdev, 0);
646err_dis:
647 pci_disable_device(pdev);
648err:
649 return ret;
650}
651
652static void __devexit
653ath5k_pci_remove(struct pci_dev *pdev)
654{
655 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
656 struct ath5k_softc *sc = hw->priv;
657
658 ath5k_debug_finish_device(sc);
659 ath5k_detach(pdev, hw);
660 ath5k_hw_detach(sc->ah);
661 free_irq(pdev->irq, sc);
fa1c114f
JS		 662 pci_iounmap(pdev, sc->iobase);
663 pci_release_region(pdev, 0);
664 pci_disable_device(pdev);
665 ieee80211_free_hw(hw);
666}
667
668#ifdef CONFIG_PM
669static int
670ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
671{
672 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
673 struct ath5k_softc *sc = hw->priv;
674
3a078876 675 ath5k_led_off(sc);
fa1c114f 676
3e4242b9 677 free_irq(pdev->irq, sc);
fa1c114f
JS		 678 pci_save_state(pdev);
679 pci_disable_device(pdev);
680 pci_set_power_state(pdev, PCI_D3hot);
681
682 return 0;
683}
684
685static int
686ath5k_pci_resume(struct pci_dev *pdev)
687{
688 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
689 struct ath5k_softc *sc = hw->priv;
bc1b32d6 690 int err;
fa1c114f 691
3e4242b9 692 pci_restore_state(pdev);
fa1c114f
JS		 693
694 err = pci_enable_device(pdev);
695 if (err)
696 return err;
697
8451d22d
JM		 698 /*
699 * Suspend/Resume resets the PCI configuration space, so we have to
700 * re-disable the RETRY_TIMEOUT register (0x41) to keep
701 * PCI Tx retries from interfering with C3 CPU state
702 */
703 pci_write_config_byte(pdev, 0x41, 0);
704
3e4242b9
JS		 705 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
706 if (err) {
707 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 708 goto err_no_irq;
3e4242b9
JS		 709 }
710
3a078876 711 ath5k_led_enable(sc);
fa1c114f 712 return 0;
bb2becac 713
37465c8a 714err_no_irq:
3e4242b9
JS		 715 pci_disable_device(pdev);
716 return err;
fa1c114f
JS		 717}
718#endif /* CONFIG_PM */
719
720
fa1c114f
JS		 721/***********************\
722* Driver Initialization *
723\***********************/
724
f769c36b
BC		 725static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
726{
727 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
728 struct ath5k_softc *sc = hw->priv;
729 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
730
731 return ath_reg_notifier_apply(wiphy, request, reg);
732}
733
fa1c114f
JS		 734static int
735ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
736{
737 struct ath5k_softc *sc = hw->priv;
738 struct ath5k_hw *ah = sc->ah;
0e149cf5 739 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 740 int ret;
741
742 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
743
744 /*
745 * Check if the MAC has multi-rate retry support.
746 * We do this by trying to setup a fake extended
747 * descriptor. MAC's that don't have support will
748 * return false w/o doing anything. MAC's that do
749 * support it will return true w/o doing anything.
750 */
c6e387a2 751 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 752 if (ret < 0)
753 goto err;
754 if (ret > 0)
fa1c114f
JS		 755 __set_bit(ATH_STAT_MRRETRY, sc->status);
756
fa1c114f
JS		 757 /*
758 * Collect the channel list. The 802.11 layer
759 * is resposible for filtering this list based
760 * on settings like the phy mode and regulatory
761 * domain restrictions.
762 */
63266a65 763 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 764 if (ret) {
765 ATH5K_ERR(sc, "can't get channels\n");
766 goto err;
767 }
768
769 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 770 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
771 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 772 else
d8ee398d 773 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 774
775 /*
776 * Allocate tx+rx descriptors and populate the lists.
777 */
778 ret = ath5k_desc_alloc(sc, pdev);
779 if (ret) {
780 ATH5K_ERR(sc, "can't allocate descriptors\n");
781 goto err;
782 }
783
784 /*
785 * Allocate hardware transmit queues: one queue for
786 * beacon frames and one data queue for each QoS
787 * priority. Note that hw functions handle reseting
788 * these queues at the needed time.
789 */
790 ret = ath5k_beaconq_setup(ah);
791 if (ret < 0) {
792 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
793 goto err_desc;
794 }
795 sc->bhalq = ret;
cec8db23
BC		 796 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
797 if (IS_ERR(sc->cabq)) {
798 ATH5K_ERR(sc, "can't setup cab queue\n");
799 ret = PTR_ERR(sc->cabq);
800 goto err_bhal;
801 }
fa1c114f
JS		 802
803 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
804 if (IS_ERR(sc->txq)) {
805 ATH5K_ERR(sc, "can't setup xmit queue\n");
806 ret = PTR_ERR(sc->txq);
cec8db23 807 goto err_queues;
fa1c114f
JS		 808 }
809
810 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
811 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
812 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
acf3c1a5 813 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 814 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 815
0e149cf5
BC		 816 ret = ath5k_eeprom_read_mac(ah, mac);
817 if (ret) {
818 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
819 sc->pdev->device);
820 goto err_queues;
821 }
822
fa1c114f
JS		 823 SET_IEEE80211_PERM_ADDR(hw, mac);
824 /* All MAC address bits matter for ACKs */
825 memset(sc->bssidmask, 0xff, ETH_ALEN);
826 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
827
f769c36b
BC		 828 ah->ah_regulatory.current_rd =
829 ah->ah_capabilities.cap_eeprom.ee_regdomain;
830 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
831 if (ret) {
832 ATH5K_ERR(sc, "can't initialize regulatory system\n");
833 goto err_queues;
834 }
835
fa1c114f
JS		 836 ret = ieee80211_register_hw(hw);
837 if (ret) {
838 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
839 goto err_queues;
840 }
841
f769c36b
BC		 842 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
843 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
844
3a078876
BC		 845 ath5k_init_leds(sc);
846
fa1c114f
JS		 847 return 0;
848err_queues:
849 ath5k_txq_release(sc);
850err_bhal:
851 ath5k_hw_release_tx_queue(ah, sc->bhalq);
852err_desc:
853 ath5k_desc_free(sc, pdev);
854err:
855 return ret;
856}
857
858static void
859ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
860{
861 struct ath5k_softc *sc = hw->priv;
862
863 /*
864 * NB: the order of these is important:
865 * o call the 802.11 layer before detaching ath5k_hw to
866 * insure callbacks into the driver to delete global
867 * key cache entries can be handled
868 * o reclaim the tx queue data structures after calling
869 * the 802.11 layer as we'll get called back to reclaim
870 * node state and potentially want to use them
871 * o to cleanup the tx queues the hal is called, so detach
872 * it last
873 * XXX: ??? detach ath5k_hw ???
874 * Other than that, it's straightforward...
875 */
876 ieee80211_unregister_hw(hw);
877 ath5k_desc_free(sc, pdev);
878 ath5k_txq_release(sc);
879 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 880 ath5k_unregister_leds(sc);
fa1c114f
JS		 881
882 /*
883 * NB: can't reclaim these until after ieee80211_ifdetach
884 * returns because we'll get called back to reclaim node
885 * state and potentially want to use them.
886 */
887}
888
889
890
891
892/********************\
893* Channel/mode setup *
894\********************/
895
896/*
897 * Convert IEEE channel number to MHz frequency.
898 */
899static inline short
900ath5k_ieee2mhz(short chan)
901{
902 if (chan <= 14 || chan >= 27)
903 return ieee80211chan2mhz(chan);
904 else
905 return 2212 + chan * 20;
906}
907
42639fcd
BC		 908/*
909 * Returns true for the channel numbers used without all_channels modparam.
910 */
911static bool ath5k_is_standard_channel(short chan)
912{
913 return ((chan <= 14) ||
914 /* UNII 1,2 */
915 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
916 /* midband */
917 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
918 /* UNII-3 */
919 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
920}
921
fa1c114f
JS		 922static unsigned int
923ath5k_copy_channels(struct ath5k_hw *ah,
924 struct ieee80211_channel *channels,
925 unsigned int mode,
926 unsigned int max)
927{
d8ee398d 928 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 929
930 if (!test_bit(mode, ah->ah_modes))
931 return 0;
932
fa1c114f 933 switch (mode) {
d8ee398d
LR		 934 case AR5K_MODE_11A:
935 case AR5K_MODE_11A_TURBO:
fa1c114f 936 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 937 size = 220 ;
fa1c114f
JS		 938 chfreq = CHANNEL_5GHZ;
939 break;
d8ee398d
LR		 940 case AR5K_MODE_11B:
941 case AR5K_MODE_11G:
942 case AR5K_MODE_11G_TURBO:
943 size = 26;
fa1c114f
JS		 944 chfreq = CHANNEL_2GHZ;
945 break;
946 default:
947 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
948 return 0;
949 }
950
951 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 952 ch = i + 1 ;
953 freq = ath5k_ieee2mhz(ch);
fa1c114f 954
d8ee398d
LR		 955 /* Check if channel is supported by the chipset */
956 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 957 continue;
958
42639fcd
BC		 959 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
960 continue;
961
d8ee398d
LR		 962 /* Write channel info and increment counter */
963 channels[count].center_freq = freq;
a3f4b914
LR		 964 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
965 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 966 switch (mode) {
967 case AR5K_MODE_11A:
968 case AR5K_MODE_11G:
969 channels[count].hw_value = chfreq | CHANNEL_OFDM;
970 break;
971 case AR5K_MODE_11A_TURBO:
972 case AR5K_MODE_11G_TURBO:
973 channels[count].hw_value = chfreq |
974 CHANNEL_OFDM | CHANNEL_TURBO;
975 break;
976 case AR5K_MODE_11B:
d8ee398d
LR		 977 channels[count].hw_value = CHANNEL_B;
978 }
fa1c114f 979
fa1c114f
JS		 980 count++;
981 max--;
982 }
983
984 return count;
985}
986
63266a65
BR		 987static void
988ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
989{
990 u8 i;
991
992 for (i = 0; i < AR5K_MAX_RATES; i++)
993 sc->rate_idx[b->band][i] = -1;
994
995 for (i = 0; i < b->n_bitrates; i++) {
996 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
997 if (b->bitrates[i].hw_value_short)
998 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
999 }
1000}
1001
d8ee398d 1002static int
63266a65 1003ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1004{
1005 struct ath5k_softc *sc = hw->priv;
d8ee398d 1006 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1007 struct ieee80211_supported_band *sband;
1008 int max_c, count_c = 0;
1009 int i;
fa1c114f 1010
d8ee398d 1011 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1012 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1013
1014 /* 2GHz band */
63266a65
BR		 1015 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1016 sband->band = IEEE80211_BAND_2GHZ;
1017 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1018
63266a65
BR		 1019 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1020 /* G mode */
1021 memcpy(sband->bitrates, &ath5k_rates[0],
1022 sizeof(struct ieee80211_rate) * 12);
1023 sband->n_bitrates = 12;
fa1c114f 1024
d8ee398d 1025 sband->channels = sc->channels;
d8ee398d 1026 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1027 AR5K_MODE_11G, max_c);
fa1c114f 1028
63266a65 1029 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1030 count_c = sband->n_channels;
63266a65
BR		 1031 max_c -= count_c;
1032 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1033 /* B mode */
1034 memcpy(sband->bitrates, &ath5k_rates[0],
1035 sizeof(struct ieee80211_rate) * 4);
1036 sband->n_bitrates = 4;
1037
1038 /* 5211 only supports B rates and uses 4bit rate codes
1039 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1040 * fix them up here:
1041 */
1042 if (ah->ah_version == AR5K_AR5211) {
1043 for (i = 0; i < 4; i++) {
1044 sband->bitrates[i].hw_value =
1045 sband->bitrates[i].hw_value & 0xF;
1046 sband->bitrates[i].hw_value_short =
1047 sband->bitrates[i].hw_value_short & 0xF;
1048 }
1049 }
fa1c114f 1050
63266a65
BR		 1051 sband->channels = sc->channels;
1052 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1053 AR5K_MODE_11B, max_c);
d8ee398d 1054
63266a65
BR		 1055 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1056 count_c = sband->n_channels;
d8ee398d 1057 max_c -= count_c;
fa1c114f 1058 }
63266a65 1059 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1060
63266a65 1061 /* 5GHz band, A mode */
400ec45a 1062 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1063 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1064 sband->band = IEEE80211_BAND_5GHZ;
1065 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1066
63266a65
BR		 1067 memcpy(sband->bitrates, &ath5k_rates[4],
1068 sizeof(struct ieee80211_rate) * 8);
1069 sband->n_bitrates = 8;
fa1c114f 1070
63266a65 1071 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1072 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1073 AR5K_MODE_11A, max_c);
1074
d8ee398d
LR		 1075 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1076 }
63266a65 1077 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1078
b446197c 1079 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1080
1081 return 0;
fa1c114f
JS		 1082}
1083
1084/*
1085 * Set/change channels. If the channel is really being changed,
1086 * it's done by reseting the chip. To accomplish this we must
1087 * first cleanup any pending DMA, then restart stuff after a la
1088 * ath5k_init.
be009370
BC		 1089 *
1090 * Called with sc->lock.
fa1c114f
JS		 1091 */
1092static int
1093ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1094{
d8ee398d
LR		 1095 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1096 sc->curchan->center_freq, chan->center_freq);
1097
1098 if (chan->center_freq != sc->curchan->center_freq ||
1099 chan->hw_value != sc->curchan->hw_value) {
1100
fa1c114f
JS		 1101 /*
1102 * To switch channels clear any pending DMA operations;
1103 * wait long enough for the RX fifo to drain, reset the
1104 * hardware at the new frequency, and then re-enable
1105 * the relevant bits of the h/w.
1106 */
209d889b 1107 return ath5k_reset(sc, chan);
fa1c114f
JS		 1108 }
1109
1110 return 0;
1111}
1112
1113static void
1114ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1115{
fa1c114f 1116 sc->curmode = mode;
d8ee398d 1117
400ec45a 1118 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1119 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1120 } else {
1121 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1122 }
fa1c114f
JS		 1123}
1124
1125static void
1126ath5k_mode_setup(struct ath5k_softc *sc)
1127{
1128 struct ath5k_hw *ah = sc->ah;
1129 u32 rfilt;
1130
1131 /* configure rx filter */
1132 rfilt = sc->filter_flags;
1133 ath5k_hw_set_rx_filter(ah, rfilt);
1134
1135 if (ath5k_hw_hasbssidmask(ah))
1136 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1137
1138 /* configure operational mode */
1139 ath5k_hw_set_opmode(ah);
1140
1141 ath5k_hw_set_mcast_filter(ah, 0, 0);
1142 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1143}
1144
d8ee398d 1145static inline int
63266a65
BR		 1146ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1147{
b7266047
BC		 1148 int rix;
1149
1150 /* return base rate on errors */
1151 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1152 "hw_rix out of bounds: %x\n", hw_rix))
1153 return 0;
1154
1155 rix = sc->rate_idx[sc->curband->band][hw_rix];
1156 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1157 rix = 0;
1158
1159 return rix;
d8ee398d
LR		 1160}
1161
fa1c114f
JS		 1162/***************\
1163* Buffers setup *
1164\***************/
1165
b6ea0356
BC		 1166static
1167struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1168{
1169 struct sk_buff *skb;
1170 unsigned int off;
1171
1172 /*
1173 * Allocate buffer with headroom_needed space for the
1174 * fake physical layer header at the start.
1175 */
1176 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1177
1178 if (!skb) {
1179 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1180 sc->rxbufsize + sc->cachelsz - 1);
1181 return NULL;
1182 }
1183 /*
1184 * Cache-line-align. This is important (for the
1185 * 5210 at least) as not doing so causes bogus data
1186 * in rx'd frames.
1187 */
1188 off = ((unsigned long)skb->data) % sc->cachelsz;
1189 if (off != 0)
1190 skb_reserve(skb, sc->cachelsz - off);
1191
1192 *skb_addr = pci_map_single(sc->pdev,
1193 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1194 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1195 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1196 dev_kfree_skb(skb);
1197 return NULL;
1198 }
1199 return skb;
1200}
1201
fa1c114f
JS		 1202static int
1203ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1204{
1205 struct ath5k_hw *ah = sc->ah;
1206 struct sk_buff *skb = bf->skb;
1207 struct ath5k_desc *ds;
1208
b6ea0356
BC		 1209 if (!skb) {
1210 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1211 if (!skb)
fa1c114f 1212 return -ENOMEM;
fa1c114f 1213 bf->skb = skb;
fa1c114f
JS		 1214 }
1215
1216 /*
1217 * Setup descriptors. For receive we always terminate
1218 * the descriptor list with a self-linked entry so we'll
1219 * not get overrun under high load (as can happen with a
1220 * 5212 when ANI processing enables PHY error frames).
1221 *
1222 * To insure the last descriptor is self-linked we create
1223 * each descriptor as self-linked and add it to the end. As
1224 * each additional descriptor is added the previous self-linked
1225 * entry is ``fixed'' naturally. This should be safe even
1226 * if DMA is happening. When processing RX interrupts we
1227 * never remove/process the last, self-linked, entry on the
1228 * descriptor list. This insures the hardware always has
1229 * someplace to write a new frame.
1230 */
1231 ds = bf->desc;
1232 ds->ds_link = bf->daddr; /* link to self */
1233 ds->ds_data = bf->skbaddr;
c6e387a2 1234 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1235 skb_tailroom(skb), /* buffer size */
1236 0);
1237
1238 if (sc->rxlink != NULL)
1239 *sc->rxlink = bf->daddr;
1240 sc->rxlink = &ds->ds_link;
1241 return 0;
1242}
1243
1244static int
cec8db23
BC		 1245ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1246 struct ath5k_txq *txq)
fa1c114f
JS		 1247{
1248 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1249 struct ath5k_desc *ds = bf->desc;
1250 struct sk_buff *skb = bf->skb;
a888d52d 1251 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1252 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1253 struct ieee80211_rate *rate;
1254 unsigned int mrr_rate[3], mrr_tries[3];
1255 int i, ret;
8902ff4e 1256 u16 hw_rate;
07c1e852
BC		 1257 u16 cts_rate = 0;
1258 u16 duration = 0;
8902ff4e 1259 u8 rc_flags;
fa1c114f
JS		 1260
1261 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1262
fa1c114f
JS		 1263 /* XXX endianness */
1264 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1265 PCI_DMA_TODEVICE);
1266
8902ff4e
BC		 1267 rate = ieee80211_get_tx_rate(sc->hw, info);
1268
e039fa4a 1269 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1270 flags |= AR5K_TXDESC_NOACK;
1271
8902ff4e
BC		 1272 rc_flags = info->control.rates[0].flags;
1273 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1274 rate->hw_value_short : rate->hw_value;
1275
281c56dd 1276 pktlen = skb->len;
fa1c114f 1277
8f655dde
NK		 1278 /* FIXME: If we are in g mode and rate is a CCK rate
1279 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1280 * from tx power (value is in dB units already) */
362695e1
BC		 1281 if (info->control.hw_key) {
1282 keyidx = info->control.hw_key->hw_key_idx;
1283 pktlen += info->control.hw_key->icv_len;
1284 }
07c1e852
BC		 1285 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1286 flags |= AR5K_TXDESC_RTSENA;
1287 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1288 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1289 sc->vif, pktlen, info));
1290 }
1291 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1292 flags |= AR5K_TXDESC_CTSENA;
1293 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1294 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1295 sc->vif, pktlen, info));
1296 }
fa1c114f
JS		 1297 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1298 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1299 (sc->power_level * 2),
8902ff4e 1300 hw_rate,
2bed03eb 1301 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1302 cts_rate, duration);
fa1c114f
JS		 1303 if (ret)
1304 goto err_unmap;
1305
2f7fe870
FF		 1306 memset(mrr_rate, 0, sizeof(mrr_rate));
1307 memset(mrr_tries, 0, sizeof(mrr_tries));
1308 for (i = 0; i < 3; i++) {
1309 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1310 if (!rate)
1311 break;
1312
1313 mrr_rate[i] = rate->hw_value;
e6a9854b 1314 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1315 }
1316
1317 ah->ah_setup_mrr_tx_desc(ah, ds,
1318 mrr_rate[0], mrr_tries[0],
1319 mrr_rate[1], mrr_tries[1],
1320 mrr_rate[2], mrr_tries[2]);
1321
fa1c114f
JS		 1322 ds->ds_link = 0;
1323 ds->ds_data = bf->skbaddr;
1324
1325 spin_lock_bh(&txq->lock);
1326 list_add_tail(&bf->list, &txq->q);
57ffc589 1327 sc->tx_stats[txq->qnum].len++;
fa1c114f 1328 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1329 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1330 else /* no, so only link it */
1331 *txq->link = bf->daddr;
1332
1333 txq->link = &ds->ds_link;
c6e387a2 1334 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1335 mmiowb();
fa1c114f
JS		 1336 spin_unlock_bh(&txq->lock);
1337
1338 return 0;
1339err_unmap:
1340 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1341 return ret;
1342}
1343
1344/*******************\
1345* Descriptors setup *
1346\*******************/
1347
1348static int
1349ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1350{
1351 struct ath5k_desc *ds;
1352 struct ath5k_buf *bf;
1353 dma_addr_t da;
1354 unsigned int i;
1355 int ret;
1356
1357 /* allocate descriptors */
1358 sc->desc_len = sizeof(struct ath5k_desc) *
1359 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1360 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1361 if (sc->desc == NULL) {
1362 ATH5K_ERR(sc, "can't allocate descriptors\n");
1363 ret = -ENOMEM;
1364 goto err;
1365 }
1366 ds = sc->desc;
1367 da = sc->desc_daddr;
1368 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1369 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1370
1371 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1372 sizeof(struct ath5k_buf), GFP_KERNEL);
1373 if (bf == NULL) {
1374 ATH5K_ERR(sc, "can't allocate bufptr\n");
1375 ret = -ENOMEM;
1376 goto err_free;
1377 }
1378 sc->bufptr = bf;
1379
1380 INIT_LIST_HEAD(&sc->rxbuf);
1381 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1382 bf->desc = ds;
1383 bf->daddr = da;
1384 list_add_tail(&bf->list, &sc->rxbuf);
1385 }
1386
1387 INIT_LIST_HEAD(&sc->txbuf);
1388 sc->txbuf_len = ATH_TXBUF;
1389 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1390 da += sizeof(*ds)) {
1391 bf->desc = ds;
1392 bf->daddr = da;
1393 list_add_tail(&bf->list, &sc->txbuf);
1394 }
1395
1396 /* beacon buffer */
1397 bf->desc = ds;
1398 bf->daddr = da;
1399 sc->bbuf = bf;
1400
1401 return 0;
1402err_free:
1403 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1404err:
1405 sc->desc = NULL;
1406 return ret;
1407}
1408
1409static void
1410ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1411{
1412 struct ath5k_buf *bf;
1413
1414 ath5k_txbuf_free(sc, sc->bbuf);
1415 list_for_each_entry(bf, &sc->txbuf, list)
1416 ath5k_txbuf_free(sc, bf);
1417 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1418 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1419
1420 /* Free memory associated with all descriptors */
1421 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1422
1423 kfree(sc->bufptr);
1424 sc->bufptr = NULL;
1425}
1426
1427
1428
1429
1430
1431/**************\
1432* Queues setup *
1433\**************/
1434
1435static struct ath5k_txq *
1436ath5k_txq_setup(struct ath5k_softc *sc,
1437 int qtype, int subtype)
1438{
1439 struct ath5k_hw *ah = sc->ah;
1440 struct ath5k_txq *txq;
1441 struct ath5k_txq_info qi = {
1442 .tqi_subtype = subtype,
1443 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1444 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1445 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1446 };
1447 int qnum;
1448
1449 /*
1450 * Enable interrupts only for EOL and DESC conditions.
1451 * We mark tx descriptors to receive a DESC interrupt
1452 * when a tx queue gets deep; otherwise waiting for the
1453 * EOL to reap descriptors. Note that this is done to
1454 * reduce interrupt load and this only defers reaping
1455 * descriptors, never transmitting frames. Aside from
1456 * reducing interrupts this also permits more concurrency.
1457 * The only potential downside is if the tx queue backs
1458 * up in which case the top half of the kernel may backup
1459 * due to a lack of tx descriptors.
1460 */
1461 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1462 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1463 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1464 if (qnum < 0) {
1465 /*
1466 * NB: don't print a message, this happens
1467 * normally on parts with too few tx queues
1468 */
1469 return ERR_PTR(qnum);
1470 }
1471 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1472 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1473 qnum, ARRAY_SIZE(sc->txqs));
1474 ath5k_hw_release_tx_queue(ah, qnum);
1475 return ERR_PTR(-EINVAL);
1476 }
1477 txq = &sc->txqs[qnum];
1478 if (!txq->setup) {
1479 txq->qnum = qnum;
1480 txq->link = NULL;
1481 INIT_LIST_HEAD(&txq->q);
1482 spin_lock_init(&txq->lock);
1483 txq->setup = true;
1484 }
1485 return &sc->txqs[qnum];
1486}
1487
1488static int
1489ath5k_beaconq_setup(struct ath5k_hw *ah)
1490{
1491 struct ath5k_txq_info qi = {
1492 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1493 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1494 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1495 /* NB: for dynamic turbo, don't enable any other interrupts */
1496 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1497 };
1498
1499 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1500}
1501
1502static int
1503ath5k_beaconq_config(struct ath5k_softc *sc)
1504{
1505 struct ath5k_hw *ah = sc->ah;
1506 struct ath5k_txq_info qi;
1507 int ret;
1508
1509 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1510 if (ret)
1511 return ret;
05c914fe
JB		 1512 if (sc->opmode == NL80211_IFTYPE_AP ||
1513 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1514 /*
1515 * Always burst out beacon and CAB traffic
1516 * (aifs = cwmin = cwmax = 0)
1517 */
1518 qi.tqi_aifs = 0;
1519 qi.tqi_cw_min = 0;
1520 qi.tqi_cw_max = 0;
05c914fe 1521 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1522 /*
1523 * Adhoc mode; backoff between 0 and (2 * cw_min).
1524 */
1525 qi.tqi_aifs = 0;
1526 qi.tqi_cw_min = 0;
1527 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1528 }
1529
6d91e1d8
BR		 1530 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1531 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1532 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1533
c6e387a2 1534 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1535 if (ret) {
1536 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1537 "hardware queue!\n", __func__);
1538 return ret;
1539 }
1540
1541 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1542}
1543
1544static void
1545ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1546{
1547 struct ath5k_buf *bf, *bf0;
1548
1549 /*
1550 * NB: this assumes output has been stopped and
1551 * we do not need to block ath5k_tx_tasklet
1552 */
1553 spin_lock_bh(&txq->lock);
1554 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1555 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1556
1557 ath5k_txbuf_free(sc, bf);
1558
1559 spin_lock_bh(&sc->txbuflock);
57ffc589 1560 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1561 list_move_tail(&bf->list, &sc->txbuf);
1562 sc->txbuf_len++;
1563 spin_unlock_bh(&sc->txbuflock);
1564 }
1565 txq->link = NULL;
1566 spin_unlock_bh(&txq->lock);
1567}
1568
1569/*
1570 * Drain the transmit queues and reclaim resources.
1571 */
1572static void
1573ath5k_txq_cleanup(struct ath5k_softc *sc)
1574{
1575 struct ath5k_hw *ah = sc->ah;
1576 unsigned int i;
1577
1578 /* XXX return value */
1579 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1580 /* don't touch the hardware if marked invalid */
1581 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1582 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1583 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1584 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1585 if (sc->txqs[i].setup) {
1586 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1587 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1588 "link %p\n",
1589 sc->txqs[i].qnum,
c6e387a2 1590 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1591 sc->txqs[i].qnum),
1592 sc->txqs[i].link);
1593 }
1594 }
36d6825b 1595 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1596
1597 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1598 if (sc->txqs[i].setup)
1599 ath5k_txq_drainq(sc, &sc->txqs[i]);
1600}
1601
1602static void
1603ath5k_txq_release(struct ath5k_softc *sc)
1604{
1605 struct ath5k_txq *txq = sc->txqs;
1606 unsigned int i;
1607
1608 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1609 if (txq->setup) {
1610 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1611 txq->setup = false;
1612 }
1613}
1614
1615
1616
1617
1618/*************\
1619* RX Handling *
1620\*************/
1621
1622/*
1623 * Enable the receive h/w following a reset.
1624 */
1625static int
1626ath5k_rx_start(struct ath5k_softc *sc)
1627{
1628 struct ath5k_hw *ah = sc->ah;
1629 struct ath5k_buf *bf;
1630 int ret;
1631
1632 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1633
1634 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1635 sc->cachelsz, sc->rxbufsize);
1636
fa1c114f 1637 spin_lock_bh(&sc->rxbuflock);
26925042 1638 sc->rxlink = NULL;
fa1c114f
JS		 1639 list_for_each_entry(bf, &sc->rxbuf, list) {
1640 ret = ath5k_rxbuf_setup(sc, bf);
1641 if (ret != 0) {
1642 spin_unlock_bh(&sc->rxbuflock);
1643 goto err;
1644 }
1645 }
1646 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1647 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1648 spin_unlock_bh(&sc->rxbuflock);
1649
c6e387a2 1650 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1651 ath5k_mode_setup(sc); /* set filters, etc. */
1652 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1653
1654 return 0;
1655err:
1656 return ret;
1657}
1658
1659/*
1660 * Disable the receive h/w in preparation for a reset.
1661 */
1662static void
1663ath5k_rx_stop(struct ath5k_softc *sc)
1664{
1665 struct ath5k_hw *ah = sc->ah;
1666
c6e387a2 1667 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1668 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1669 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1670
1671 ath5k_debug_printrxbuffs(sc, ah);
1672
1673 sc->rxlink = NULL; /* just in case */
1674}
1675
1676static unsigned int
1677ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1678 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1679{
1680 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1681 unsigned int keyix, hlen;
fa1c114f 1682
b47f407b
BR		 1683 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1684 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1685 return RX_FLAG_DECRYPTED;
1686
1687 /* Apparently when a default key is used to decrypt the packet
1688 the hw does not set the index used to decrypt. In such cases
1689 get the index from the packet. */
798ee985 1690 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1691 if (ieee80211_has_protected(hdr->frame_control) &&
1692 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1693 skb->len >= hlen + 4) {
fa1c114f
JS		 1694 keyix = skb->data[hlen + 3] >> 6;
1695
1696 if (test_bit(keyix, sc->keymap))
1697 return RX_FLAG_DECRYPTED;
1698 }
1699
1700 return 0;
1701}
1702
036cd1ec
BR		 1703
1704static void
6ba81c2c
BR		 1705ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1706 struct ieee80211_rx_status *rxs)
036cd1ec 1707{
6ba81c2c 1708 u64 tsf, bc_tstamp;
036cd1ec
BR		 1709 u32 hw_tu;
1710 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1711
24b56e70 1712 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1713 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1714 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1715 /*
6ba81c2c
BR		 1716 * Received an IBSS beacon with the same BSSID. Hardware *must*
1717 * have updated the local TSF. We have to work around various
1718 * hardware bugs, though...
036cd1ec 1719 */
6ba81c2c
BR		 1720 tsf = ath5k_hw_get_tsf64(sc->ah);
1721 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1722 hw_tu = TSF_TO_TU(tsf);
1723
1724 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1725 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1726 (unsigned long long)bc_tstamp,
1727 (unsigned long long)rxs->mactime,
1728 (unsigned long long)(rxs->mactime - bc_tstamp),
1729 (unsigned long long)tsf);
6ba81c2c
BR		 1730
1731 /*
1732 * Sometimes the HW will give us a wrong tstamp in the rx
1733 * status, causing the timestamp extension to go wrong.
1734 * (This seems to happen especially with beacon frames bigger
1735 * than 78 byte (incl. FCS))
1736 * But we know that the receive timestamp must be later than the
1737 * timestamp of the beacon since HW must have synced to that.
1738 *
1739 * NOTE: here we assume mactime to be after the frame was
1740 * received, not like mac80211 which defines it at the start.
1741 */
1742 if (bc_tstamp > rxs->mactime) {
036cd1ec 1743 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1744 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1745 (unsigned long long)rxs->mactime,
1746 (unsigned long long)tsf);
6ba81c2c 1747 rxs->mactime = tsf;
036cd1ec 1748 }
6ba81c2c
BR		 1749
1750 /*
1751 * Local TSF might have moved higher than our beacon timers,
1752 * in that case we have to update them to continue sending
1753 * beacons. This also takes care of synchronizing beacon sending
1754 * times with other stations.
1755 */
1756 if (hw_tu >= sc->nexttbtt)
1757 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1758 }
1759}
1760
fa1c114f
JS		 1761static void
1762ath5k_tasklet_rx(unsigned long data)
1763{
1764 struct ieee80211_rx_status rxs = {};
b47f407b 1765 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1766 struct sk_buff *skb, *next_skb;
1767 dma_addr_t next_skb_addr;
fa1c114f 1768 struct ath5k_softc *sc = (void *)data;
c57ca815 1769 struct ath5k_buf *bf;
fa1c114f 1770 struct ath5k_desc *ds;
fa1c114f
JS		 1771 int ret;
1772 int hdrlen;
0fe45b1d 1773 int padsize;
fa1c114f
JS		 1774
1775 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1776 if (list_empty(&sc->rxbuf)) {
1777 ATH5K_WARN(sc, "empty rx buf pool\n");
1778 goto unlock;
1779 }
fa1c114f 1780 do {
d6894b5b
BC		 1781 rxs.flag = 0;
1782
fa1c114f
JS		 1783 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1784 BUG_ON(bf->skb == NULL);
1785 skb = bf->skb;
1786 ds = bf->desc;
1787
c57ca815
BC		 1788 /* bail if HW is still using self-linked descriptor */
1789 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1790 break;
fa1c114f 1791
b47f407b 1792 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1793 if (unlikely(ret == -EINPROGRESS))
1794 break;
1795 else if (unlikely(ret)) {
1796 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1797 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1798 return;
1799 }
1800
b47f407b 1801 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1802 ATH5K_WARN(sc, "unsupported jumbo\n");
1803 goto next;
1804 }
1805
b47f407b
BR		 1806 if (unlikely(rs.rs_status)) {
1807 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1808 goto next;
b47f407b 1809 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1810 /*
1811 * Decrypt error. If the error occurred
1812 * because there was no hardware key, then
1813 * let the frame through so the upper layers
1814 * can process it. This is necessary for 5210
1815 * parts which have no way to setup a ``clear''
1816 * key cache entry.
1817 *
1818 * XXX do key cache faulting
1819 */
b47f407b
BR		 1820 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1821 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1822 goto accept;
1823 }
b47f407b 1824 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1825 rxs.flag |= RX_FLAG_MMIC_ERROR;
1826 goto accept;
1827 }
1828
1829 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1830 if ((rs.rs_status &
1831 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1832 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1833 goto next;
1834 }
1835accept:
b6ea0356
BC		 1836 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1837
1838 /*
1839 * If we can't replace bf->skb with a new skb under memory
1840 * pressure, just skip this packet
1841 */
1842 if (!next_skb)
1843 goto next;
1844
fa1c114f
JS		 1845 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1846 PCI_DMA_FROMDEVICE);
b47f407b 1847 skb_put(skb, rs.rs_datalen);
fa1c114f 1848
0fe45b1d
BP		 1849 /* The MAC header is padded to have 32-bit boundary if the
1850 * packet payload is non-zero. The general calculation for
1851 * padsize would take into account odd header lengths:
1852 * padsize = (4 - hdrlen % 4) % 4; However, since only
1853 * even-length headers are used, padding can only be 0 or 2
1854 * bytes and we can optimize this a bit. In addition, we must
1855 * not try to remove padding from short control frames that do
1856 * not have payload. */
fa1c114f 1857 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1858 padsize = ath5k_pad_size(hdrlen);
1859 if (padsize) {
0fe45b1d
BP		 1860 memmove(skb->data + padsize, skb->data, hdrlen);
1861 skb_pull(skb, padsize);
fa1c114f
JS		 1862 }
1863
c0e1899b
BR		 1864 /*
1865 * always extend the mac timestamp, since this information is
1866 * also needed for proper IBSS merging.
1867 *
1868 * XXX: it might be too late to do it here, since rs_tstamp is
1869 * 15bit only. that means TSF extension has to be done within
1870 * 32768usec (about 32ms). it might be necessary to move this to
1871 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1872 *
1873 * Unfortunately we don't know when the hardware takes the rx
1874 * timestamp (beginning of phy frame, data frame, end of rx?).
1875 * The only thing we know is that it is hardware specific...
1876 * On AR5213 it seems the rx timestamp is at the end of the
1877 * frame, but i'm not sure.
1878 *
1879 * NOTE: mac80211 defines mactime at the beginning of the first
1880 * data symbol. Since we don't have any time references it's
1881 * impossible to comply to that. This affects IBSS merge only
1882 * right now, so it's not too bad...
c0e1899b 1883 */
b47f407b 1884 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1885 rxs.flag |= RX_FLAG_TSFT;
1886
d8ee398d
LR		 1887 rxs.freq = sc->curchan->center_freq;
1888 rxs.band = sc->curband->band;
fa1c114f 1889
fa1c114f 1890 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1891 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1892
1893 /* An rssi of 35 indicates you should be able use
1894 * 54 Mbps reliably. A more elaborate scheme can be used
1895 * here but it requires a map of SNR/throughput for each
1896 * possible mode used */
1897 rxs.qual = rs.rs_rssi * 100 / 35;
1898
1899 /* rssi can be more than 35 though, anything above that
1900 * should be considered at 100% */
1901 if (rxs.qual > 100)
1902 rxs.qual = 100;
fa1c114f 1903
b47f407b
BR		 1904 rxs.antenna = rs.rs_antenna;
1905 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1906 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1907
06303352
BR		 1908 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1909 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1910 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1911
fa1c114f
JS		 1912 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1913
036cd1ec 1914 /* check beacons in IBSS mode */
05c914fe 1915 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1916 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1917
f1d58c25
JB		 1918 memcpy(IEEE80211_SKB_RXCB(skb), &rxs, sizeof(rxs));
1919 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 1920
1921 bf->skb = next_skb;
1922 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1923next:
1924 list_move_tail(&bf->list, &sc->rxbuf);
1925 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1926unlock:
fa1c114f
JS		 1927 spin_unlock(&sc->rxbuflock);
1928}
1929
1930
1931
1932
1933/*************\
1934* TX Handling *
1935\*************/
1936
1937static void
1938ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1939{
b47f407b 1940 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1941 struct ath5k_buf *bf, *bf0;
1942 struct ath5k_desc *ds;
1943 struct sk_buff *skb;
e039fa4a 1944 struct ieee80211_tx_info *info;
2f7fe870 1945 int i, ret;
fa1c114f
JS		 1946
1947 spin_lock(&txq->lock);
1948 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1949 ds = bf->desc;
1950
b47f407b 1951 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1952 if (unlikely(ret == -EINPROGRESS))
1953 break;
1954 else if (unlikely(ret)) {
1955 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1956 ret, txq->qnum);
1957 break;
1958 }
1959
1960 skb = bf->skb;
a888d52d 1961 info = IEEE80211_SKB_CB(skb);
fa1c114f 1962 bf->skb = NULL;
e039fa4a 1963
fa1c114f
JS		 1964 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1965 PCI_DMA_TODEVICE);
1966
e6a9854b 1967 ieee80211_tx_info_clear_status(info);
2f7fe870 1968 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1969 struct ieee80211_tx_rate *r =
1970 &info->status.rates[i];
2f7fe870
FF		 1971
1972 if (ts.ts_rate[i]) {
e6a9854b
JB		 1973 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1974 r->count = ts.ts_retry[i];
2f7fe870 1975 } else {
e6a9854b
JB		 1976 r->idx = -1;
1977 r->count = 0;
2f7fe870
FF		 1978 }
1979 }
1980
e6a9854b
JB		 1981 /* count the successful attempt as well */
1982 info->status.rates[ts.ts_final_idx].count++;
1983
b47f407b 1984 if (unlikely(ts.ts_status)) {
fa1c114f 1985 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1986 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1987 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1988 } else {
e039fa4a
JB		 1989 info->flags |= IEEE80211_TX_STAT_ACK;
1990 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1991 }
1992
e039fa4a 1993 ieee80211_tx_status(sc->hw, skb);
57ffc589 1994 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1995
1996 spin_lock(&sc->txbuflock);
57ffc589 1997 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1998 list_move_tail(&bf->list, &sc->txbuf);
1999 sc->txbuf_len++;
2000 spin_unlock(&sc->txbuflock);
2001 }
2002 if (likely(list_empty(&txq->q)))
2003 txq->link = NULL;
2004 spin_unlock(&txq->lock);
2005 if (sc->txbuf_len > ATH_TXBUF / 5)
2006 ieee80211_wake_queues(sc->hw);
2007}
2008
2009static void
2010ath5k_tasklet_tx(unsigned long data)
2011{
2012 struct ath5k_softc *sc = (void *)data;
2013
2014 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 2015}
2016
2017
fa1c114f
JS		 2018/*****************\
2019* Beacon handling *
2020\*****************/
2021
2022/*
2023 * Setup the beacon frame for transmit.
2024 */
2025static int
e039fa4a 2026ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2027{
2028 struct sk_buff *skb = bf->skb;
a888d52d 2029 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2030 struct ath5k_hw *ah = sc->ah;
2031 struct ath5k_desc *ds;
2bed03eb
NK		 2032 int ret = 0;
2033 u8 antenna;
fa1c114f
JS		 2034 u32 flags;
2035
2036 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2037 PCI_DMA_TODEVICE);
2038 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2039 "skbaddr %llx\n", skb, skb->data, skb->len,
2040 (unsigned long long)bf->skbaddr);
8d8bb39b 2041 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2042 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2043 return -EIO;
2044 }
2045
2046 ds = bf->desc;
2bed03eb 2047 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2048
2049 flags = AR5K_TXDESC_NOACK;
05c914fe 2050 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2051 ds->ds_link = bf->daddr; /* self-linked */
2052 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2053 } else
fa1c114f 2054 ds->ds_link = 0;
2bed03eb
NK		 2055
2056 /*
2057 * If we use multiple antennas on AP and use
2058 * the Sectored AP scenario, switch antenna every
2059 * 4 beacons to make sure everybody hears our AP.
2060 * When a client tries to associate, hw will keep
2061 * track of the tx antenna to be used for this client
2062 * automaticaly, based on ACKed packets.
2063 *
2064 * Note: AP still listens and transmits RTS on the
2065 * default antenna which is supposed to be an omni.
2066 *
2067 * Note2: On sectored scenarios it's possible to have
2068 * multiple antennas (1omni -the default- and 14 sectors)
2069 * so if we choose to actually support this mode we need
2070 * to allow user to set how many antennas we have and tweak
2071 * the code below to send beacons on all of them.
2072 */
2073 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2074 antenna = sc->bsent & 4 ? 2 : 1;
2075
fa1c114f 2076
8f655dde
NK		 2077 /* FIXME: If we are in g mode and rate is a CCK rate
2078 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2079 * from tx power (value is in dB units already) */
fa1c114f 2080 ds->ds_data = bf->skbaddr;
281c56dd 2081 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2082 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2083 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2084 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2085 1, AR5K_TXKEYIX_INVALID,
400ec45a 2086 antenna, flags, 0, 0);
fa1c114f
JS		 2087 if (ret)
2088 goto err_unmap;
2089
2090 return 0;
2091err_unmap:
2092 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2093 return ret;
2094}
2095
72828b1b
BC		 2096static void ath5k_beacon_disable(struct ath5k_softc *sc)
2097{
2098 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2099 ath5k_hw_set_imr(sc->ah, sc->imask);
2100 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2101}
2102
fa1c114f
JS		 2103/*
2104 * Transmit a beacon frame at SWBA. Dynamic updates to the
2105 * frame contents are done as needed and the slot time is
2106 * also adjusted based on current state.
2107 *
acf3c1a5
BC		 2108 * This is called from software irq context (beacontq or restq
2109 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2110 */
2111static void
2112ath5k_beacon_send(struct ath5k_softc *sc)
2113{
2114 struct ath5k_buf *bf = sc->bbuf;
2115 struct ath5k_hw *ah = sc->ah;
cec8db23 2116 struct sk_buff *skb;
fa1c114f 2117
be9b7259 2118 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2119
05c914fe
JB		 2120 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2121 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2122 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2123 return;
2124 }
2125 /*
2126 * Check if the previous beacon has gone out. If
2127 * not don't don't try to post another, skip this
2128 * period and wait for the next. Missed beacons
2129 * indicate a problem and should not occur. If we
2130 * miss too many consecutive beacons reset the device.
2131 */
2132 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2133 sc->bmisscount++;
be9b7259 2134 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2135 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2136 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2137 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2138 "stuck beacon time (%u missed)\n",
2139 sc->bmisscount);
2140 tasklet_schedule(&sc->restq);
2141 }
2142 return;
2143 }
2144 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2145 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2146 "resume beacon xmit after %u misses\n",
2147 sc->bmisscount);
2148 sc->bmisscount = 0;
2149 }
2150
2151 /*
2152 * Stop any current dma and put the new frame on the queue.
2153 * This should never fail since we check above that no frames
2154 * are still pending on the queue.
2155 */
2156 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2157 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2158 /* NB: hw still stops DMA, so proceed */
2159 }
fa1c114f 2160
1071db86
BC		 2161 /* refresh the beacon for AP mode */
2162 if (sc->opmode == NL80211_IFTYPE_AP)
2163 ath5k_beacon_update(sc->hw, sc->vif);
2164
c6e387a2
NK		 2165 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2166 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2167 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2168 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2169
cec8db23
BC		 2170 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2171 while (skb) {
2172 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2173 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2174 }
2175
fa1c114f
JS		 2176 sc->bsent++;
2177}
2178
2179
9804b98d
BR		 2180/**
2181 * ath5k_beacon_update_timers - update beacon timers
2182 *
2183 * @sc: struct ath5k_softc pointer we are operating on
2184 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2185 * beacon timer update based on the current HW TSF.
2186 *
2187 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2188 * of a received beacon or the current local hardware TSF and write it to the
2189 * beacon timer registers.
2190 *
2191 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2192 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2193 * when we otherwise know we have to update the timers, but we keep it in this
2194 * function to have it all together in one place.
2195 */
fa1c114f 2196static void
9804b98d 2197ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2198{
2199 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2200 u32 nexttbtt, intval, hw_tu, bc_tu;
2201 u64 hw_tsf;
fa1c114f
JS		 2202
2203 intval = sc->bintval & AR5K_BEACON_PERIOD;
2204 if (WARN_ON(!intval))
2205 return;
2206
9804b98d
BR		 2207 /* beacon TSF converted to TU */
2208 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2209
9804b98d
BR		 2210 /* current TSF converted to TU */
2211 hw_tsf = ath5k_hw_get_tsf64(ah);
2212 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2213
9804b98d
BR		 2214#define FUDGE 3
2215 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2216 if (bc_tsf == -1) {
2217 /*
2218 * no beacons received, called internally.
2219 * just need to refresh timers based on HW TSF.
2220 */
2221 nexttbtt = roundup(hw_tu + FUDGE, intval);
2222 } else if (bc_tsf == 0) {
2223 /*
2224 * no beacon received, probably called by ath5k_reset_tsf().
2225 * reset TSF to start with 0.
2226 */
2227 nexttbtt = intval;
2228 intval |= AR5K_BEACON_RESET_TSF;
2229 } else if (bc_tsf > hw_tsf) {
2230 /*
2231 * beacon received, SW merge happend but HW TSF not yet updated.
2232 * not possible to reconfigure timers yet, but next time we
2233 * receive a beacon with the same BSSID, the hardware will
2234 * automatically update the TSF and then we need to reconfigure
2235 * the timers.
2236 */
2237 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2238 "need to wait for HW TSF sync\n");
2239 return;
2240 } else {
2241 /*
2242 * most important case for beacon synchronization between STA.
2243 *
2244 * beacon received and HW TSF has been already updated by HW.
2245 * update next TBTT based on the TSF of the beacon, but make
2246 * sure it is ahead of our local TSF timer.
2247 */
2248 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2249 }
2250#undef FUDGE
fa1c114f 2251
036cd1ec
BR		 2252 sc->nexttbtt = nexttbtt;
2253
fa1c114f 2254 intval |= AR5K_BEACON_ENA;
fa1c114f 2255 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2256
2257 /*
2258 * debugging output last in order to preserve the time critical aspect
2259 * of this function
2260 */
2261 if (bc_tsf == -1)
2262 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2263 "reconfigured timers based on HW TSF\n");
2264 else if (bc_tsf == 0)
2265 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2266 "reset HW TSF and timers\n");
2267 else
2268 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2269 "updated timers based on beacon TSF\n");
2270
2271 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2272 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2273 (unsigned long long) bc_tsf,
2274 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2275 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2276 intval & AR5K_BEACON_PERIOD,
2277 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2278 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2279}
2280
2281
036cd1ec
BR		 2282/**
2283 * ath5k_beacon_config - Configure the beacon queues and interrupts
2284 *
2285 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2286 *
036cd1ec 2287 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2288 * interrupts to detect TSF updates only.
fa1c114f
JS		 2289 */
2290static void
2291ath5k_beacon_config(struct ath5k_softc *sc)
2292{
2293 struct ath5k_hw *ah = sc->ah;
b5f03956 2294 unsigned long flags;
fa1c114f 2295
c6e387a2 2296 ath5k_hw_set_imr(ah, 0);
fa1c114f 2297 sc->bmisscount = 0;
dc1968e7 2298 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2299
1e3e6e8f 2300 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2301 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2302 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2303 /*
036cd1ec
BR		 2304 * In IBSS mode we use a self-linked tx descriptor and let the
2305 * hardware send the beacons automatically. We have to load it
fa1c114f 2306 * only once here.
036cd1ec 2307 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2308 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2309 */
2310 ath5k_beaconq_config(sc);
fa1c114f 2311
036cd1ec
BR		 2312 sc->imask |= AR5K_INT_SWBA;
2313
da966bca
JS		 2314 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2315 if (ath5k_hw_hasveol(ah)) {
b5f03956 2316 spin_lock_irqsave(&sc->block, flags);
da966bca 2317 ath5k_beacon_send(sc);
b5f03956 2318 spin_unlock_irqrestore(&sc->block, flags);
da966bca
JS		 2319 }
2320 } else
2321 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2322 }
fa1c114f 2323
c6e387a2 2324 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2325}
2326
428cbd4f
NK		 2327static void ath5k_tasklet_beacon(unsigned long data)
2328{
2329 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2330
2331 /*
2332 * Software beacon alert--time to send a beacon.
2333 *
2334 * In IBSS mode we use this interrupt just to
2335 * keep track of the next TBTT (target beacon
2336 * transmission time) in order to detect wether
2337 * automatic TSF updates happened.
2338 */
2339 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2340 /* XXX: only if VEOL suppported */
2341 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2342 sc->nexttbtt += sc->bintval;
2343 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2344 "SWBA nexttbtt: %x hw_tu: %x "
2345 "TSF: %llx\n",
2346 sc->nexttbtt,
2347 TSF_TO_TU(tsf),
2348 (unsigned long long) tsf);
2349 } else {
2350 spin_lock(&sc->block);
2351 ath5k_beacon_send(sc);
2352 spin_unlock(&sc->block);
2353 }
2354}
2355
fa1c114f
JS		 2356
2357/********************\
2358* Interrupt handling *
2359\********************/
2360
2361static int
bb2becac 2362ath5k_init(struct ath5k_softc *sc)
fa1c114f 2363{
bc1b32d6
EO		 2364 struct ath5k_hw *ah = sc->ah;
2365 int ret, i;
fa1c114f
JS		 2366
2367 mutex_lock(&sc->lock);
2368
2369 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2370
2371 /*
2372 * Stop anything previously setup. This is safe
2373 * no matter this is the first time through or not.
2374 */
2375 ath5k_stop_locked(sc);
2376
2377 /*
2378 * The basic interface to setting the hardware in a good
2379 * state is ``reset''. On return the hardware is known to
2380 * be powered up and with interrupts disabled. This must
2381 * be followed by initialization of the appropriate bits
2382 * and then setup of the interrupt mask.
2383 */
d8ee398d
LR		 2384 sc->curchan = sc->hw->conf.channel;
2385 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2386 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2387 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
9ca9fb8a 2388 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
209d889b 2389 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2390 if (ret)
2391 goto done;
fa1c114f 2392
e6a3b616
TD		 2393 ath5k_rfkill_hw_start(ah);
2394
bc1b32d6
EO		 2395 /*
2396 * Reset the key cache since some parts do not reset the
2397 * contents on initial power up or resume from suspend.
2398 */
2399 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2400 ath5k_hw_reset_key(ah, i);
2401
fa1c114f 2402 /* Set ack to be sent at low bit-rates */
bc1b32d6 2403 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2404
2405 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2406 msecs_to_jiffies(ath5k_calinterval * 1000)));
2407
2408 ret = 0;
2409done:
274c7c36 2410 mmiowb();
fa1c114f
JS		 2411 mutex_unlock(&sc->lock);
2412 return ret;
2413}
2414
2415static int
2416ath5k_stop_locked(struct ath5k_softc *sc)
2417{
2418 struct ath5k_hw *ah = sc->ah;
2419
2420 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2421 test_bit(ATH_STAT_INVALID, sc->status));
2422
2423 /*
2424 * Shutdown the hardware and driver:
2425 * stop output from above
2426 * disable interrupts
2427 * turn off timers
2428 * turn off the radio
2429 * clear transmit machinery
2430 * clear receive machinery
2431 * drain and release tx queues
2432 * reclaim beacon resources
2433 * power down hardware
2434 *
2435 * Note that some of this work is not possible if the
2436 * hardware is gone (invalid).
2437 */
2438 ieee80211_stop_queues(sc->hw);
2439
2440 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2441 ath5k_led_off(sc);
c6e387a2 2442 ath5k_hw_set_imr(ah, 0);
274c7c36 2443 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2444 }
2445 ath5k_txq_cleanup(sc);
2446 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2447 ath5k_rx_stop(sc);
2448 ath5k_hw_phy_disable(ah);
2449 } else
2450 sc->rxlink = NULL;
2451
2452 return 0;
2453}
2454
2455/*
2456 * Stop the device, grabbing the top-level lock to protect
2457 * against concurrent entry through ath5k_init (which can happen
2458 * if another thread does a system call and the thread doing the
2459 * stop is preempted).
2460 */
2461static int
bb2becac 2462ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2463{
2464 int ret;
2465
2466 mutex_lock(&sc->lock);
2467 ret = ath5k_stop_locked(sc);
2468 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2469 /*
2470 * Set the chip in full sleep mode. Note that we are
2471 * careful to do this only when bringing the interface
2472 * completely to a stop. When the chip is in this state
2473 * it must be carefully woken up or references to
2474 * registers in the PCI clock domain may freeze the bus
2475 * (and system). This varies by chip and is mostly an
2476 * issue with newer parts that go to sleep more quickly.
2477 */
2478 if (sc->ah->ah_mac_srev >= 0x78) {
2479 /*
2480 * XXX
2481 * don't put newer MAC revisions > 7.8 to sleep because
2482 * of the above mentioned problems
2483 */
2484 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2485 "not putting device to sleep\n");
2486 } else {
2487 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2488 "putting device to full sleep\n");
2489 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2490 }
2491 }
2492 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2493
274c7c36 2494 mmiowb();
fa1c114f
JS		 2495 mutex_unlock(&sc->lock);
2496
2497 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2498 tasklet_kill(&sc->rxtq);
2499 tasklet_kill(&sc->txtq);
2500 tasklet_kill(&sc->restq);
acf3c1a5 2501 tasklet_kill(&sc->beacontq);
fa1c114f 2502
e6a3b616
TD		 2503 ath5k_rfkill_hw_stop(sc->ah);
2504
fa1c114f
JS		 2505 return ret;
2506}
2507
2508static irqreturn_t
2509ath5k_intr(int irq, void *dev_id)
2510{
2511 struct ath5k_softc *sc = dev_id;
2512 struct ath5k_hw *ah = sc->ah;
2513 enum ath5k_int status;
2514 unsigned int counter = 1000;
2515
2516 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2517 !ath5k_hw_is_intr_pending(ah)))
2518 return IRQ_NONE;
2519
2520 do {
fa1c114f
JS		 2521 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2522 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2523 status, sc->imask);
fa1c114f
JS		 2524 if (unlikely(status & AR5K_INT_FATAL)) {
2525 /*
2526 * Fatal errors are unrecoverable.
2527 * Typically these are caused by DMA errors.
2528 */
2529 tasklet_schedule(&sc->restq);
2530 } else if (unlikely(status & AR5K_INT_RXORN)) {
2531 tasklet_schedule(&sc->restq);
2532 } else {
2533 if (status & AR5K_INT_SWBA) {
56d2ac76 2534 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2535 }
2536 if (status & AR5K_INT_RXEOL) {
2537 /*
2538 * NB: the hardware should re-read the link when
2539 * RXE bit is written, but it doesn't work at
2540 * least on older hardware revs.
2541 */
2542 sc->rxlink = NULL;
2543 }
2544 if (status & AR5K_INT_TXURN) {
2545 /* bump tx trigger level */
2546 ath5k_hw_update_tx_triglevel(ah, true);
2547 }
4c674c60 2548 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2549 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2550 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2551 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2552 tasklet_schedule(&sc->txtq);
2553 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2554 /* TODO */
fa1c114f
JS		 2555 }
2556 if (status & AR5K_INT_MIB) {
194828a2
NK		 2557 /*
2558 * These stats are also used for ANI i think
2559 * so how about updating them more often ?
2560 */
2561 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f 2562 }
e6a3b616 2563 if (status & AR5K_INT_GPIO)
e6a3b616 2564 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2565
fa1c114f 2566 }
2516baa6 2567 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2568
2569 if (unlikely(!counter))
2570 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2571
2572 return IRQ_HANDLED;
2573}
2574
2575static void
2576ath5k_tasklet_reset(unsigned long data)
2577{
2578 struct ath5k_softc *sc = (void *)data;
2579
d7dc1003 2580 ath5k_reset_wake(sc);
fa1c114f
JS		 2581}
2582
2583/*
2584 * Periodically recalibrate the PHY to account
2585 * for temperature/environment changes.
2586 */
2587static void
2588ath5k_calibrate(unsigned long data)
2589{
2590 struct ath5k_softc *sc = (void *)data;
2591 struct ath5k_hw *ah = sc->ah;
2592
2593 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2594 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2595 sc->curchan->hw_value);
fa1c114f 2596
6f3b414a 2597 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2598 /*
2599 * Rfgain is out of bounds, reset the chip
2600 * to load new gain values.
2601 */
2602 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2603 ath5k_reset_wake(sc);
fa1c114f
JS		 2604 }
2605 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2606 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2607 ieee80211_frequency_to_channel(
2608 sc->curchan->center_freq));
fa1c114f
JS		 2609
2610 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2611 msecs_to_jiffies(ath5k_calinterval * 1000)));
2612}
2613
2614
fa1c114f
JS		 2615/********************\
2616* Mac80211 functions *
2617\********************/
2618
2619static int
e039fa4a 2620ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2621{
2622 struct ath5k_softc *sc = hw->priv;
2623
2624 return ath5k_tx_queue(hw, skb, sc->txq);
2625}
2626
2627static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2628 struct ath5k_txq *txq)
fa1c114f
JS		 2629{
2630 struct ath5k_softc *sc = hw->priv;
2631 struct ath5k_buf *bf;
2632 unsigned long flags;
2633 int hdrlen;
0fe45b1d 2634 int padsize;
fa1c114f
JS		 2635
2636 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2637
05c914fe 2638 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2639 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2640
2641 /*
2642 * the hardware expects the header padded to 4 byte boundaries
2643 * if this is not the case we add the padding after the header
2644 */
2645 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2646 padsize = ath5k_pad_size(hdrlen);
2647 if (padsize) {
0fe45b1d
BP		 2648
2649 if (skb_headroom(skb) < padsize) {
fa1c114f 2650 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2651 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2652 goto drop_packet;
fa1c114f 2653 }
0fe45b1d
BP		 2654 skb_push(skb, padsize);
2655 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2656 }
2657
fa1c114f
JS		 2658 spin_lock_irqsave(&sc->txbuflock, flags);
2659 if (list_empty(&sc->txbuf)) {
2660 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2661 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2662 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2663 goto drop_packet;
fa1c114f
JS		 2664 }
2665 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2666 list_del(&bf->list);
2667 sc->txbuf_len--;
2668 if (list_empty(&sc->txbuf))
2669 ieee80211_stop_queues(hw);
2670 spin_unlock_irqrestore(&sc->txbuflock, flags);
2671
2672 bf->skb = skb;
2673
cec8db23 2674 if (ath5k_txbuf_setup(sc, bf, txq)) {
fa1c114f
JS		 2675 bf->skb = NULL;
2676 spin_lock_irqsave(&sc->txbuflock, flags);
2677 list_add_tail(&bf->list, &sc->txbuf);
2678 sc->txbuf_len++;
2679 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2680 goto drop_packet;
fa1c114f 2681 }
5a0fe8ac 2682 return NETDEV_TX_OK;
fa1c114f 2683
5a0fe8ac
BC		 2684drop_packet:
2685 dev_kfree_skb_any(skb);
71ef99c8 2686 return NETDEV_TX_OK;
fa1c114f
JS		 2687}
2688
209d889b
BC		 2689/*
2690 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2691 * and change to the given channel.
2692 */
fa1c114f 2693static int
209d889b 2694ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2695{
fa1c114f
JS		 2696 struct ath5k_hw *ah = sc->ah;
2697 int ret;
2698
2699 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2700
209d889b 2701 if (chan) {
c6e387a2 2702 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2703 ath5k_txq_cleanup(sc);
2704 ath5k_rx_stop(sc);
209d889b
BC		 2705
2706 sc->curchan = chan;
2707 sc->curband = &sc->sbands[chan->band];
d7dc1003 2708 }
fa1c114f 2709 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2710 if (ret) {
fa1c114f
JS		 2711 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2712 goto err;
2713 }
d7dc1003 2714
fa1c114f 2715 ret = ath5k_rx_start(sc);
d7dc1003 2716 if (ret) {
fa1c114f
JS		 2717 ATH5K_ERR(sc, "can't start recv logic\n");
2718 goto err;
2719 }
d7dc1003 2720
fa1c114f 2721 /*
d7dc1003
JS		 2722 * Change channels and update the h/w rate map if we're switching;
2723 * e.g. 11a to 11b/g.
2724 *
2725 * We may be doing a reset in response to an ioctl that changes the
2726 * channel so update any state that might change as a result.
fa1c114f
JS		 2727 *
2728 * XXX needed?
2729 */
2730/* ath5k_chan_change(sc, c); */
fa1c114f 2731
d7dc1003
JS		 2732 ath5k_beacon_config(sc);
2733 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2734
2735 return 0;
2736err:
2737 return ret;
2738}
2739
d7dc1003
JS		 2740static int
2741ath5k_reset_wake(struct ath5k_softc *sc)
2742{
2743 int ret;
2744
209d889b 2745 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2746 if (!ret)
2747 ieee80211_wake_queues(sc->hw);
2748
2749 return ret;
2750}
2751
fa1c114f
JS		 2752static int ath5k_start(struct ieee80211_hw *hw)
2753{
bb2becac 2754 return ath5k_init(hw->priv);
fa1c114f
JS		 2755}
2756
2757static void ath5k_stop(struct ieee80211_hw *hw)
2758{
bb2becac 2759 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2760}
2761
2762static int ath5k_add_interface(struct ieee80211_hw *hw,
2763 struct ieee80211_if_init_conf *conf)
2764{
2765 struct ath5k_softc *sc = hw->priv;
2766 int ret;
2767
2768 mutex_lock(&sc->lock);
32bfd35d 2769 if (sc->vif) {
fa1c114f
JS		 2770 ret = 0;
2771 goto end;
2772 }
2773
32bfd35d 2774 sc->vif = conf->vif;
fa1c114f
JS		 2775
2776 switch (conf->type) {
da966bca 2777 case NL80211_IFTYPE_AP:
05c914fe
JB		 2778 case NL80211_IFTYPE_STATION:
2779 case NL80211_IFTYPE_ADHOC:
b706e65b 2780 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2781 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2782 sc->opmode = conf->type;
2783 break;
2784 default:
2785 ret = -EOPNOTSUPP;
2786 goto end;
2787 }
67d2e2df 2788
0e149cf5 2789 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2790
fa1c114f
JS		 2791 ret = 0;
2792end:
2793 mutex_unlock(&sc->lock);
2794 return ret;
2795}
2796
2797static void
2798ath5k_remove_interface(struct ieee80211_hw *hw,
2799 struct ieee80211_if_init_conf *conf)
2800{
2801 struct ath5k_softc *sc = hw->priv;
0e149cf5 2802 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2803
2804 mutex_lock(&sc->lock);
32bfd35d 2805 if (sc->vif != conf->vif)
fa1c114f
JS		 2806 goto end;
2807
0e149cf5 2808 ath5k_hw_set_lladdr(sc->ah, mac);
72828b1b 2809 ath5k_beacon_disable(sc);
32bfd35d 2810 sc->vif = NULL;
fa1c114f
JS		 2811end:
2812 mutex_unlock(&sc->lock);
2813}
2814
d8ee398d
LR		 2815/*
2816 * TODO: Phy disable/diversity etc
2817 */
fa1c114f 2818static int
e8975581 2819ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2820{
2821 struct ath5k_softc *sc = hw->priv;
a0823810 2822 struct ath5k_hw *ah = sc->ah;
e8975581 2823 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 2824 int ret = 0;
be009370
BC		 2825
2826 mutex_lock(&sc->lock);
fa1c114f 2827
2bed03eb
NK		 2828 ret = ath5k_chan_set(sc, conf->channel);
2829 if (ret < 0)
55aa4e0f 2830 goto unlock;
2bed03eb 2831
a0823810
NK		 2832 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2833 (sc->power_level != conf->power_level)) {
2834 sc->power_level = conf->power_level;
2835
2836 /* Half dB steps */
2837 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2838 }
fa1c114f 2839
2bed03eb
NK		 2840 /* TODO:
2841 * 1) Move this on config_interface and handle each case
2842 * separately eg. when we have only one STA vif, use
2843 * AR5K_ANTMODE_SINGLE_AP
2844 *
2845 * 2) Allow the user to change antenna mode eg. when only
2846 * one antenna is present
2847 *
2848 * 3) Allow the user to set default/tx antenna when possible
2849 *
2850 * 4) Default mode should handle 90% of the cases, together
2851 * with fixed a/b and single AP modes we should be able to
2852 * handle 99%. Sectored modes are extreme cases and i still
2853 * haven't found a usage for them. If we decide to support them,
2854 * then we must allow the user to set how many tx antennas we
2855 * have available
2856 */
2857 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
be009370 2858
55aa4e0f 2859unlock:
be009370 2860 mutex_unlock(&sc->lock);
55aa4e0f 2861 return ret;
fa1c114f
JS		 2862}
2863
fa1c114f
JS		 2864#define SUPPORTED_FIF_FLAGS \
2865 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2866 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2867 FIF_BCN_PRBRESP_PROMISC
2868/*
2869 * o always accept unicast, broadcast, and multicast traffic
2870 * o multicast traffic for all BSSIDs will be enabled if mac80211
2871 * says it should be
2872 * o maintain current state of phy ofdm or phy cck error reception.
2873 * If the hardware detects any of these type of errors then
2874 * ath5k_hw_get_rx_filter() will pass to us the respective
2875 * hardware filters to be able to receive these type of frames.
2876 * o probe request frames are accepted only when operating in
2877 * hostap, adhoc, or monitor modes
2878 * o enable promiscuous mode according to the interface state
2879 * o accept beacons:
2880 * - when operating in adhoc mode so the 802.11 layer creates
2881 * node table entries for peers,
2882 * - when operating in station mode for collecting rssi data when
2883 * the station is otherwise quiet, or
2884 * - when scanning
2885 */
2886static void ath5k_configure_filter(struct ieee80211_hw *hw,
2887 unsigned int changed_flags,
2888 unsigned int *new_flags,
2889 int mc_count, struct dev_mc_list *mclist)
2890{
2891 struct ath5k_softc *sc = hw->priv;
2892 struct ath5k_hw *ah = sc->ah;
2893 u32 mfilt[2], val, rfilt;
2894 u8 pos;
2895 int i;
2896
2897 mfilt[0] = 0;
2898 mfilt[1] = 0;
2899
2900 /* Only deal with supported flags */
2901 changed_flags &= SUPPORTED_FIF_FLAGS;
2902 *new_flags &= SUPPORTED_FIF_FLAGS;
2903
2904 /* If HW detects any phy or radar errors, leave those filters on.
2905 * Also, always enable Unicast, Broadcasts and Multicast
2906 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2907 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2908 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2909 AR5K_RX_FILTER_MCAST);
2910
2911 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2912 if (*new_flags & FIF_PROMISC_IN_BSS) {
2913 rfilt |= AR5K_RX_FILTER_PROM;
2914 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2915 } else {
fa1c114f 2916 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2917 }
fa1c114f
JS		 2918 }
2919
2920 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2921 if (*new_flags & FIF_ALLMULTI) {
2922 mfilt[0] = ~0;
2923 mfilt[1] = ~0;
2924 } else {
2925 for (i = 0; i < mc_count; i++) {
2926 if (!mclist)
2927 break;
2928 /* calculate XOR of eight 6-bit values */
533dd1b0 2929 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2930 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2931 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2932 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2933 pos &= 0x3f;
2934 mfilt[pos / 32] |= (1 << (pos % 32));
2935 /* XXX: we might be able to just do this instead,
2936 * but not sure, needs testing, if we do use this we'd
2937 * neet to inform below to not reset the mcast */
2938 /* ath5k_hw_set_mcast_filterindex(ah,
2939 * mclist->dmi_addr[5]); */
2940 mclist = mclist->next;
2941 }
2942 }
2943
2944 /* This is the best we can do */
2945 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2946 rfilt |= AR5K_RX_FILTER_PHYERR;
2947
2948 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2949 * and probes for any BSSID, this needs testing */
2950 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2951 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2952
2953 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2954 * set we should only pass on control frames for this
2955 * station. This needs testing. I believe right now this
2956 * enables *all* control frames, which is OK.. but
2957 * but we should see if we can improve on granularity */
2958 if (*new_flags & FIF_CONTROL)
2959 rfilt |= AR5K_RX_FILTER_CONTROL;
2960
2961 /* Additional settings per mode -- this is per ath5k */
2962
2963 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2964
05c914fe 2965 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2966 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2967 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2968 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2969 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2970 if (sc->opmode != NL80211_IFTYPE_AP &&
2971 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2972 test_bit(ATH_STAT_PROMISC, sc->status))
2973 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2974 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2975 sc->opmode == NL80211_IFTYPE_ADHOC ||
2976 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2977 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2978 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2979 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2980 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2981
2982 /* Set filters */
0bbac08f 2983 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2984
2985 /* Set multicast bits */
2986 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2987 /* Set the cached hw filter flags, this will alter actually
2988 * be set in HW */
2989 sc->filter_flags = rfilt;
2990}
2991
2992static int
2993ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2994 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2995 struct ieee80211_key_conf *key)
fa1c114f
JS		 2996{
2997 struct ath5k_softc *sc = hw->priv;
2998 int ret = 0;
2999
9ad9a26e
BC		 3000 if (modparam_nohwcrypt)
3001 return -EOPNOTSUPP;
3002
0bbac08f 3003 switch (key->alg) {
fa1c114f 3004 case ALG_WEP:
fa1c114f 3005 case ALG_TKIP:
3f64b435 3006 break;
fa1c114f
JS		 3007 case ALG_CCMP:
3008 return -EOPNOTSUPP;
3009 default:
3010 WARN_ON(1);
3011 return -EINVAL;
3012 }
3013
3014 mutex_lock(&sc->lock);
3015
3016 switch (cmd) {
3017 case SET_KEY:
dc822b5d
JB		 3018 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3019 sta ? sta->addr : NULL);
fa1c114f
JS		 3020 if (ret) {
3021 ATH5K_ERR(sc, "can't set the key\n");
3022 goto unlock;
3023 }
3024 __set_bit(key->keyidx, sc->keymap);
3025 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3026 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3027 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3028 break;
3029 case DISABLE_KEY:
3030 ath5k_hw_reset_key(sc->ah, key->keyidx);
3031 __clear_bit(key->keyidx, sc->keymap);
3032 break;
3033 default:
3034 ret = -EINVAL;
3035 goto unlock;
3036 }
3037
3038unlock:
274c7c36 3039 mmiowb();
fa1c114f
JS		 3040 mutex_unlock(&sc->lock);
3041 return ret;
3042}
3043
3044static int
3045ath5k_get_stats(struct ieee80211_hw *hw,
3046 struct ieee80211_low_level_stats *stats)
3047{
3048 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3049 struct ath5k_hw *ah = sc->ah;
3050
3051 /* Force update */
3052 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3053
3054 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3055
3056 return 0;
3057}
3058
3059static int
3060ath5k_get_tx_stats(struct ieee80211_hw *hw,
3061 struct ieee80211_tx_queue_stats *stats)
3062{
3063 struct ath5k_softc *sc = hw->priv;
3064
3065 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3066
3067 return 0;
3068}
3069
3070static u64
3071ath5k_get_tsf(struct ieee80211_hw *hw)
3072{
3073 struct ath5k_softc *sc = hw->priv;
3074
3075 return ath5k_hw_get_tsf64(sc->ah);
3076}
3077
3b5d665b
AF		 3078static void
3079ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3080{
3081 struct ath5k_softc *sc = hw->priv;
3082
3083 ath5k_hw_set_tsf64(sc->ah, tsf);
3084}
3085
fa1c114f
JS		 3086static void
3087ath5k_reset_tsf(struct ieee80211_hw *hw)
3088{
3089 struct ath5k_softc *sc = hw->priv;
3090
9804b98d
BR		 3091 /*
3092 * in IBSS mode we need to update the beacon timers too.
3093 * this will also reset the TSF if we call it with 0
3094 */
05c914fe 3095 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3096 ath5k_beacon_update_timers(sc, 0);
3097 else
3098 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3099}
3100
1071db86
BC		 3101/*
3102 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3103 * this is called only once at config_bss time, for AP we do it every
3104 * SWBA interrupt so that the TIM will reflect buffered frames.
3105 *
3106 * Called with the beacon lock.
3107 */
fa1c114f 3108static int
1071db86 3109ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3110{
fa1c114f 3111 int ret;
1071db86 3112 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3113 struct sk_buff *skb;
3114
3115 if (WARN_ON(!vif)) {
3116 ret = -EINVAL;
3117 goto out;
3118 }
3119
3120 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3121
3122 if (!skb) {
3123 ret = -ENOMEM;
3124 goto out;
3125 }
fa1c114f
JS		 3126
3127 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3128
fa1c114f
JS		 3129 ath5k_txbuf_free(sc, sc->bbuf);
3130 sc->bbuf->skb = skb;
e039fa4a 3131 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3132 if (ret)
3133 sc->bbuf->skb = NULL;
1071db86
BC		 3134out:
3135 return ret;
3136}
3137
3138/*
3139 * Update the beacon and reconfigure the beacon queues.
3140 */
3141static void
3142ath5k_beacon_reconfig(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3143{
3144 int ret;
3145 unsigned long flags;
3146 struct ath5k_softc *sc = hw->priv;
3147
3148 spin_lock_irqsave(&sc->block, flags);
3149 ret = ath5k_beacon_update(hw, vif);
00482973 3150 spin_unlock_irqrestore(&sc->block, flags);
1071db86 3151 if (ret == 0) {
fa1c114f 3152 ath5k_beacon_config(sc);
274c7c36
JS		 3153 mmiowb();
3154 }
fa1c114f 3155}
1071db86 3156
02969b38
MX		 3157static void
3158set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3159{
3160 struct ath5k_softc *sc = hw->priv;
3161 struct ath5k_hw *ah = sc->ah;
3162 u32 rfilt;
3163 rfilt = ath5k_hw_get_rx_filter(ah);
3164 if (enable)
3165 rfilt |= AR5K_RX_FILTER_BEACON;
3166 else
3167 rfilt &= ~AR5K_RX_FILTER_BEACON;
3168 ath5k_hw_set_rx_filter(ah, rfilt);
3169 sc->filter_flags = rfilt;
3170}
fa1c114f 3171
02969b38
MX		 3172static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3173 struct ieee80211_vif *vif,
3174 struct ieee80211_bss_conf *bss_conf,
3175 u32 changes)
3176{
3177 struct ath5k_softc *sc = hw->priv;
2d0ddec5
JB		 3178 struct ath5k_hw *ah = sc->ah;
3179
3180 mutex_lock(&sc->lock);
3181 if (WARN_ON(sc->vif != vif))
3182 goto unlock;
3183
3184 if (changes & BSS_CHANGED_BSSID) {
3185 /* Cache for later use during resets */
3186 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3187 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3188 * a clean way of letting us retrieve this yet. */
3189 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3190 mmiowb();
3191 }
57c4d7b4
JB		 3192
3193 if (changes & BSS_CHANGED_BEACON_INT)
3194 sc->bintval = bss_conf->beacon_int;
3195
02969b38 3196 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3197 sc->assoc = bss_conf->assoc;
3198 if (sc->opmode == NL80211_IFTYPE_STATION)
3199 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3200 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3201 AR5K_LED_ASSOC : AR5K_LED_INIT);
02969b38 3202 }
2d0ddec5
JB		 3203
3204 if (changes & BSS_CHANGED_BEACON &&
3205 (vif->type == NL80211_IFTYPE_ADHOC ||
3206 vif->type == NL80211_IFTYPE_MESH_POINT ||
3207 vif->type == NL80211_IFTYPE_AP)) {
1071db86 3208 ath5k_beacon_reconfig(hw, vif);
2d0ddec5
JB		 3209 }
3210
3211 unlock:
3212 mutex_unlock(&sc->lock);
02969b38 3213}
f0f3d388
BC		 3214
3215static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3216{
3217 struct ath5k_softc *sc = hw->priv;
3218 if (!sc->assoc)
3219 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3220}
3221
3222static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3223{
3224 struct ath5k_softc *sc = hw->priv;
3225 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3226 AR5K_LED_ASSOC : AR5K_LED_INIT);
3227}
Linux kernel - Deliverables
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