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fa1c114f JS |
1 | /*- |
2 | * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting | |
3 | * Copyright (c) 2004-2005 Atheros Communications, Inc. | |
4 | * Copyright (c) 2006 Devicescape Software, Inc. | |
5 | * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> | |
6 | * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> | |
7 | * | |
8 | * All rights reserved. | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer, | |
15 | * without modification. | |
16 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
17 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any | |
18 | * redistribution must be conditioned upon including a substantially | |
19 | * similar Disclaimer requirement for further binary redistribution. | |
20 | * 3. Neither the names of the above-listed copyright holders nor the names | |
21 | * of any contributors may be used to endorse or promote products derived | |
22 | * from this software without specific prior written permission. | |
23 | * | |
24 | * Alternatively, this software may be distributed under the terms of the | |
25 | * GNU General Public License ("GPL") version 2 as published by the Free | |
26 | * Software Foundation. | |
27 | * | |
28 | * NO WARRANTY | |
29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
30 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
31 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY | |
32 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL | |
33 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, | |
34 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
35 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
36 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER | |
37 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
38 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
39 | * THE POSSIBILITY OF SUCH DAMAGES. | |
40 | * | |
41 | */ | |
42 | ||
fa1c114f JS |
43 | #include <linux/module.h> |
44 | #include <linux/delay.h> | |
274c7c36 | 45 | #include <linux/hardirq.h> |
fa1c114f | 46 | #include <linux/if.h> |
274c7c36 | 47 | #include <linux/io.h> |
fa1c114f JS |
48 | #include <linux/netdevice.h> |
49 | #include <linux/cache.h> | |
fa1c114f JS |
50 | #include <linux/ethtool.h> |
51 | #include <linux/uaccess.h> | |
5a0e3ad6 | 52 | #include <linux/slab.h> |
b1ae1edf | 53 | #include <linux/etherdevice.h> |
fa1c114f JS |
54 | |
55 | #include <net/ieee80211_radiotap.h> | |
56 | ||
57 | #include <asm/unaligned.h> | |
58 | ||
59 | #include "base.h" | |
60 | #include "reg.h" | |
61 | #include "debug.h" | |
2111ac0d | 62 | #include "ani.h" |
fa1c114f | 63 | |
18cb6e32 JL |
64 | int ath5k_modparam_nohwcrypt; |
65 | module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); | |
9ad9a26e | 66 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); |
fa1c114f | 67 | |
42639fcd | 68 | static int modparam_all_channels; |
46802a4f | 69 | module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); |
42639fcd BC |
70 | MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); |
71 | ||
fa1c114f JS |
72 | /* Module info */ |
73 | MODULE_AUTHOR("Jiri Slaby"); | |
74 | MODULE_AUTHOR("Nick Kossifidis"); | |
75 | MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); | |
76 | MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); | |
77 | MODULE_LICENSE("Dual BSD/GPL"); | |
fa1c114f | 78 | |
132b1c3e | 79 | static int ath5k_init(struct ieee80211_hw *hw); |
8aec7af9 NK |
80 | static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, |
81 | bool skip_pcu); | |
cd2c5486 BR |
82 | int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif); |
83 | void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); | |
fa1c114f | 84 | |
fa1c114f | 85 | /* Known SREVs */ |
2c91108c | 86 | static const struct ath5k_srev_name srev_names[] = { |
a0b907ee FF |
87 | #ifdef CONFIG_ATHEROS_AR231X |
88 | { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, | |
89 | { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, | |
90 | { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, | |
91 | { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, | |
92 | { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, | |
93 | { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, | |
94 | { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, | |
95 | #else | |
1bef016a NK |
96 | { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, |
97 | { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, | |
98 | { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, | |
99 | { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, | |
100 | { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, | |
101 | { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, | |
102 | { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, | |
103 | { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, | |
104 | { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, | |
105 | { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, | |
106 | { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, | |
107 | { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, | |
108 | { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, | |
109 | { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, | |
110 | { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, | |
111 | { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, | |
112 | { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, | |
113 | { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, | |
a0b907ee | 114 | #endif |
1bef016a | 115 | { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, |
fa1c114f JS |
116 | { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, |
117 | { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, | |
1bef016a | 118 | { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, |
fa1c114f JS |
119 | { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, |
120 | { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, | |
121 | { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, | |
1bef016a | 122 | { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, |
fa1c114f JS |
123 | { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, |
124 | { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, | |
1bef016a NK |
125 | { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, |
126 | { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, | |
127 | { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, | |
1bef016a | 128 | { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, |
fa1c114f | 129 | { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, |
a0b907ee FF |
130 | #ifdef CONFIG_ATHEROS_AR231X |
131 | { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, | |
132 | { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, | |
133 | #endif | |
fa1c114f JS |
134 | { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, |
135 | }; | |
136 | ||
2c91108c | 137 | static const struct ieee80211_rate ath5k_rates[] = { |
63266a65 BR |
138 | { .bitrate = 10, |
139 | .hw_value = ATH5K_RATE_CODE_1M, }, | |
140 | { .bitrate = 20, | |
141 | .hw_value = ATH5K_RATE_CODE_2M, | |
142 | .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, | |
143 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
144 | { .bitrate = 55, | |
145 | .hw_value = ATH5K_RATE_CODE_5_5M, | |
146 | .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, | |
147 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
148 | { .bitrate = 110, | |
149 | .hw_value = ATH5K_RATE_CODE_11M, | |
150 | .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, | |
151 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
152 | { .bitrate = 60, | |
153 | .hw_value = ATH5K_RATE_CODE_6M, | |
154 | .flags = 0 }, | |
155 | { .bitrate = 90, | |
156 | .hw_value = ATH5K_RATE_CODE_9M, | |
157 | .flags = 0 }, | |
158 | { .bitrate = 120, | |
159 | .hw_value = ATH5K_RATE_CODE_12M, | |
160 | .flags = 0 }, | |
161 | { .bitrate = 180, | |
162 | .hw_value = ATH5K_RATE_CODE_18M, | |
163 | .flags = 0 }, | |
164 | { .bitrate = 240, | |
165 | .hw_value = ATH5K_RATE_CODE_24M, | |
166 | .flags = 0 }, | |
167 | { .bitrate = 360, | |
168 | .hw_value = ATH5K_RATE_CODE_36M, | |
169 | .flags = 0 }, | |
170 | { .bitrate = 480, | |
171 | .hw_value = ATH5K_RATE_CODE_48M, | |
172 | .flags = 0 }, | |
173 | { .bitrate = 540, | |
174 | .hw_value = ATH5K_RATE_CODE_54M, | |
175 | .flags = 0 }, | |
176 | /* XR missing */ | |
177 | }; | |
178 | ||
fa1c114f JS |
179 | static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) |
180 | { | |
181 | u64 tsf = ath5k_hw_get_tsf64(ah); | |
182 | ||
183 | if ((tsf & 0x7fff) < rstamp) | |
184 | tsf -= 0x8000; | |
185 | ||
186 | return (tsf & ~0x7fff) | rstamp; | |
187 | } | |
188 | ||
e5b046d8 | 189 | const char * |
fa1c114f JS |
190 | ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) |
191 | { | |
192 | const char *name = "xxxxx"; | |
193 | unsigned int i; | |
194 | ||
195 | for (i = 0; i < ARRAY_SIZE(srev_names); i++) { | |
196 | if (srev_names[i].sr_type != type) | |
197 | continue; | |
75d0edb8 NK |
198 | |
199 | if ((val & 0xf0) == srev_names[i].sr_val) | |
200 | name = srev_names[i].sr_name; | |
201 | ||
202 | if ((val & 0xff) == srev_names[i].sr_val) { | |
fa1c114f JS |
203 | name = srev_names[i].sr_name; |
204 | break; | |
205 | } | |
206 | } | |
207 | ||
208 | return name; | |
209 | } | |
e5aa8474 LR |
210 | static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) |
211 | { | |
212 | struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; | |
213 | return ath5k_hw_reg_read(ah, reg_offset); | |
214 | } | |
215 | ||
216 | static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
217 | { | |
218 | struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; | |
219 | ath5k_hw_reg_write(ah, val, reg_offset); | |
220 | } | |
221 | ||
222 | static const struct ath_ops ath5k_common_ops = { | |
223 | .read = ath5k_ioread32, | |
224 | .write = ath5k_iowrite32, | |
225 | }; | |
fa1c114f | 226 | |
8a63facc BC |
227 | /***********************\ |
228 | * Driver Initialization * | |
229 | \***********************/ | |
230 | ||
231 | static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) | |
fa1c114f | 232 | { |
8a63facc BC |
233 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); |
234 | struct ath5k_softc *sc = hw->priv; | |
235 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); | |
fa1c114f | 236 | |
8a63facc BC |
237 | return ath_reg_notifier_apply(wiphy, request, regulatory); |
238 | } | |
6ccf15a1 | 239 | |
8a63facc BC |
240 | /********************\ |
241 | * Channel/mode setup * | |
242 | \********************/ | |
fa1c114f | 243 | |
8a63facc BC |
244 | /* |
245 | * Returns true for the channel numbers used without all_channels modparam. | |
246 | */ | |
410e6120 | 247 | static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) |
8a63facc | 248 | { |
410e6120 BR |
249 | if (band == IEEE80211_BAND_2GHZ && chan <= 14) |
250 | return true; | |
251 | ||
252 | return /* UNII 1,2 */ | |
253 | (((chan & 3) == 0 && chan >= 36 && chan <= 64) || | |
8a63facc BC |
254 | /* midband */ |
255 | ((chan & 3) == 0 && chan >= 100 && chan <= 140) || | |
256 | /* UNII-3 */ | |
410e6120 BR |
257 | ((chan & 3) == 1 && chan >= 149 && chan <= 165) || |
258 | /* 802.11j 5.030-5.080 GHz (20MHz) */ | |
259 | (chan == 8 || chan == 12 || chan == 16) || | |
260 | /* 802.11j 4.9GHz (20MHz) */ | |
261 | (chan == 184 || chan == 188 || chan == 192 || chan == 196)); | |
8a63facc | 262 | } |
fa1c114f | 263 | |
8a63facc | 264 | static unsigned int |
08105690 | 265 | ath5k_setup_channels(struct ath5k_hw *ah, |
8a63facc BC |
266 | struct ieee80211_channel *channels, |
267 | unsigned int mode, | |
268 | unsigned int max) | |
269 | { | |
270 | unsigned int i, count, size, chfreq, freq, ch; | |
90c02d72 | 271 | enum ieee80211_band band; |
fa1c114f | 272 | |
8a63facc BC |
273 | if (!test_bit(mode, ah->ah_modes)) |
274 | return 0; | |
fa1c114f | 275 | |
8a63facc BC |
276 | switch (mode) { |
277 | case AR5K_MODE_11A: | |
8a63facc BC |
278 | /* 1..220, but 2GHz frequencies are filtered by check_channel */ |
279 | size = 220 ; | |
280 | chfreq = CHANNEL_5GHZ; | |
90c02d72 | 281 | band = IEEE80211_BAND_5GHZ; |
8a63facc BC |
282 | break; |
283 | case AR5K_MODE_11B: | |
284 | case AR5K_MODE_11G: | |
8a63facc BC |
285 | size = 26; |
286 | chfreq = CHANNEL_2GHZ; | |
90c02d72 | 287 | band = IEEE80211_BAND_2GHZ; |
8a63facc BC |
288 | break; |
289 | default: | |
290 | ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); | |
291 | return 0; | |
fa1c114f JS |
292 | } |
293 | ||
8a63facc BC |
294 | for (i = 0, count = 0; i < size && max > 0; i++) { |
295 | ch = i + 1 ; | |
90c02d72 BR |
296 | freq = ieee80211_channel_to_frequency(ch, band); |
297 | ||
298 | if (freq == 0) /* mapping failed - not a standard channel */ | |
299 | continue; | |
fa1c114f | 300 | |
8a63facc BC |
301 | /* Check if channel is supported by the chipset */ |
302 | if (!ath5k_channel_ok(ah, freq, chfreq)) | |
303 | continue; | |
f59ac048 | 304 | |
410e6120 BR |
305 | if (!modparam_all_channels && |
306 | !ath5k_is_standard_channel(ch, band)) | |
8a63facc | 307 | continue; |
f59ac048 | 308 | |
8a63facc BC |
309 | /* Write channel info and increment counter */ |
310 | channels[count].center_freq = freq; | |
90c02d72 | 311 | channels[count].band = band; |
8a63facc BC |
312 | switch (mode) { |
313 | case AR5K_MODE_11A: | |
314 | case AR5K_MODE_11G: | |
315 | channels[count].hw_value = chfreq | CHANNEL_OFDM; | |
316 | break; | |
8a63facc BC |
317 | case AR5K_MODE_11B: |
318 | channels[count].hw_value = CHANNEL_B; | |
319 | } | |
fa1c114f | 320 | |
8a63facc BC |
321 | count++; |
322 | max--; | |
323 | } | |
fa1c114f | 324 | |
8a63facc BC |
325 | return count; |
326 | } | |
fa1c114f | 327 | |
8a63facc BC |
328 | static void |
329 | ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) | |
330 | { | |
331 | u8 i; | |
fa1c114f | 332 | |
8a63facc BC |
333 | for (i = 0; i < AR5K_MAX_RATES; i++) |
334 | sc->rate_idx[b->band][i] = -1; | |
fa1c114f | 335 | |
8a63facc BC |
336 | for (i = 0; i < b->n_bitrates; i++) { |
337 | sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; | |
338 | if (b->bitrates[i].hw_value_short) | |
339 | sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; | |
fa1c114f | 340 | } |
8a63facc | 341 | } |
fa1c114f | 342 | |
8a63facc BC |
343 | static int |
344 | ath5k_setup_bands(struct ieee80211_hw *hw) | |
345 | { | |
346 | struct ath5k_softc *sc = hw->priv; | |
347 | struct ath5k_hw *ah = sc->ah; | |
348 | struct ieee80211_supported_band *sband; | |
349 | int max_c, count_c = 0; | |
350 | int i; | |
fa1c114f | 351 | |
8a63facc BC |
352 | BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); |
353 | max_c = ARRAY_SIZE(sc->channels); | |
db719718 | 354 | |
8a63facc BC |
355 | /* 2GHz band */ |
356 | sband = &sc->sbands[IEEE80211_BAND_2GHZ]; | |
357 | sband->band = IEEE80211_BAND_2GHZ; | |
358 | sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; | |
9adca126 | 359 | |
8a63facc BC |
360 | if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { |
361 | /* G mode */ | |
362 | memcpy(sband->bitrates, &ath5k_rates[0], | |
363 | sizeof(struct ieee80211_rate) * 12); | |
364 | sband->n_bitrates = 12; | |
2f7fe870 | 365 | |
8a63facc | 366 | sband->channels = sc->channels; |
08105690 | 367 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 368 | AR5K_MODE_11G, max_c); |
fa1c114f | 369 | |
8a63facc BC |
370 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
371 | count_c = sband->n_channels; | |
372 | max_c -= count_c; | |
373 | } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { | |
374 | /* B mode */ | |
375 | memcpy(sband->bitrates, &ath5k_rates[0], | |
376 | sizeof(struct ieee80211_rate) * 4); | |
377 | sband->n_bitrates = 4; | |
fa1c114f | 378 | |
8a63facc BC |
379 | /* 5211 only supports B rates and uses 4bit rate codes |
380 | * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) | |
381 | * fix them up here: | |
382 | */ | |
383 | if (ah->ah_version == AR5K_AR5211) { | |
384 | for (i = 0; i < 4; i++) { | |
385 | sband->bitrates[i].hw_value = | |
386 | sband->bitrates[i].hw_value & 0xF; | |
387 | sband->bitrates[i].hw_value_short = | |
388 | sband->bitrates[i].hw_value_short & 0xF; | |
fa1c114f JS |
389 | } |
390 | } | |
fa1c114f | 391 | |
8a63facc | 392 | sband->channels = sc->channels; |
08105690 | 393 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 394 | AR5K_MODE_11B, max_c); |
fa1c114f | 395 | |
8a63facc BC |
396 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
397 | count_c = sband->n_channels; | |
398 | max_c -= count_c; | |
399 | } | |
400 | ath5k_setup_rate_idx(sc, sband); | |
fa1c114f | 401 | |
8a63facc BC |
402 | /* 5GHz band, A mode */ |
403 | if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { | |
404 | sband = &sc->sbands[IEEE80211_BAND_5GHZ]; | |
405 | sband->band = IEEE80211_BAND_5GHZ; | |
406 | sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; | |
fa1c114f | 407 | |
8a63facc BC |
408 | memcpy(sband->bitrates, &ath5k_rates[4], |
409 | sizeof(struct ieee80211_rate) * 8); | |
410 | sband->n_bitrates = 8; | |
fa1c114f | 411 | |
8a63facc | 412 | sband->channels = &sc->channels[count_c]; |
08105690 | 413 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 414 | AR5K_MODE_11A, max_c); |
fa1c114f | 415 | |
8a63facc BC |
416 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; |
417 | } | |
418 | ath5k_setup_rate_idx(sc, sband); | |
419 | ||
420 | ath5k_debug_dump_bands(sc); | |
fa1c114f | 421 | |
fa1c114f JS |
422 | return 0; |
423 | } | |
424 | ||
8a63facc BC |
425 | /* |
426 | * Set/change channels. We always reset the chip. | |
427 | * To accomplish this we must first cleanup any pending DMA, | |
428 | * then restart stuff after a la ath5k_init. | |
429 | * | |
430 | * Called with sc->lock. | |
431 | */ | |
cd2c5486 | 432 | int |
8a63facc BC |
433 | ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) |
434 | { | |
435 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
436 | "channel set, resetting (%u -> %u MHz)\n", | |
437 | sc->curchan->center_freq, chan->center_freq); | |
438 | ||
8451d22d | 439 | /* |
8a63facc BC |
440 | * To switch channels clear any pending DMA operations; |
441 | * wait long enough for the RX fifo to drain, reset the | |
442 | * hardware at the new frequency, and then re-enable | |
443 | * the relevant bits of the h/w. | |
8451d22d | 444 | */ |
8aec7af9 | 445 | return ath5k_reset(sc, chan, true); |
fa1c114f | 446 | } |
fa1c114f | 447 | |
b1ae1edf BG |
448 | struct ath_vif_iter_data { |
449 | const u8 *hw_macaddr; | |
450 | u8 mask[ETH_ALEN]; | |
451 | u8 active_mac[ETH_ALEN]; /* first active MAC */ | |
452 | bool need_set_hw_addr; | |
453 | bool found_active; | |
454 | bool any_assoc; | |
62c58fb4 | 455 | enum nl80211_iftype opmode; |
b1ae1edf BG |
456 | }; |
457 | ||
458 | static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
459 | { | |
460 | struct ath_vif_iter_data *iter_data = data; | |
461 | int i; | |
62c58fb4 | 462 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
b1ae1edf BG |
463 | |
464 | if (iter_data->hw_macaddr) | |
465 | for (i = 0; i < ETH_ALEN; i++) | |
466 | iter_data->mask[i] &= | |
467 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
468 | ||
469 | if (!iter_data->found_active) { | |
470 | iter_data->found_active = true; | |
471 | memcpy(iter_data->active_mac, mac, ETH_ALEN); | |
472 | } | |
473 | ||
474 | if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) | |
475 | if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0) | |
476 | iter_data->need_set_hw_addr = false; | |
477 | ||
478 | if (!iter_data->any_assoc) { | |
b1ae1edf BG |
479 | if (avf->assoc) |
480 | iter_data->any_assoc = true; | |
481 | } | |
62c58fb4 BG |
482 | |
483 | /* Calculate combined mode - when APs are active, operate in AP mode. | |
484 | * Otherwise use the mode of the new interface. This can currently | |
485 | * only deal with combinations of APs and STAs. Only one ad-hoc | |
7afbb2f0 | 486 | * interfaces is allowed. |
62c58fb4 BG |
487 | */ |
488 | if (avf->opmode == NL80211_IFTYPE_AP) | |
489 | iter_data->opmode = NL80211_IFTYPE_AP; | |
490 | else | |
491 | if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) | |
492 | iter_data->opmode = avf->opmode; | |
b1ae1edf BG |
493 | } |
494 | ||
cd2c5486 BR |
495 | void |
496 | ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, | |
497 | struct ieee80211_vif *vif) | |
b1ae1edf BG |
498 | { |
499 | struct ath_common *common = ath5k_hw_common(sc->ah); | |
500 | struct ath_vif_iter_data iter_data; | |
501 | ||
502 | /* | |
503 | * Use the hardware MAC address as reference, the hardware uses it | |
504 | * together with the BSSID mask when matching addresses. | |
505 | */ | |
506 | iter_data.hw_macaddr = common->macaddr; | |
507 | memset(&iter_data.mask, 0xff, ETH_ALEN); | |
508 | iter_data.found_active = false; | |
509 | iter_data.need_set_hw_addr = true; | |
62c58fb4 | 510 | iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; |
b1ae1edf BG |
511 | |
512 | if (vif) | |
513 | ath_vif_iter(&iter_data, vif->addr, vif); | |
514 | ||
515 | /* Get list of all active MAC addresses */ | |
516 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter, | |
517 | &iter_data); | |
518 | memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN); | |
519 | ||
62c58fb4 BG |
520 | sc->opmode = iter_data.opmode; |
521 | if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED) | |
522 | /* Nothing active, default to station mode */ | |
523 | sc->opmode = NL80211_IFTYPE_STATION; | |
524 | ||
7afbb2f0 BG |
525 | ath5k_hw_set_opmode(sc->ah, sc->opmode); |
526 | ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", | |
527 | sc->opmode, ath_opmode_to_string(sc->opmode)); | |
62c58fb4 | 528 | |
b1ae1edf BG |
529 | if (iter_data.need_set_hw_addr && iter_data.found_active) |
530 | ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac); | |
531 | ||
62c58fb4 BG |
532 | if (ath5k_hw_hasbssidmask(sc->ah)) |
533 | ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); | |
b1ae1edf BG |
534 | } |
535 | ||
cd2c5486 | 536 | void |
b1ae1edf | 537 | ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif) |
fa1c114f | 538 | { |
fa1c114f | 539 | struct ath5k_hw *ah = sc->ah; |
8a63facc | 540 | u32 rfilt; |
fa1c114f | 541 | |
8a63facc BC |
542 | /* configure rx filter */ |
543 | rfilt = sc->filter_flags; | |
544 | ath5k_hw_set_rx_filter(ah, rfilt); | |
8a63facc | 545 | ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); |
62c58fb4 BG |
546 | |
547 | ath5k_update_bssid_mask_and_opmode(sc, vif); | |
8a63facc | 548 | } |
fa1c114f | 549 | |
8a63facc BC |
550 | static inline int |
551 | ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) | |
552 | { | |
553 | int rix; | |
fa1c114f | 554 | |
8a63facc BC |
555 | /* return base rate on errors */ |
556 | if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, | |
557 | "hw_rix out of bounds: %x\n", hw_rix)) | |
558 | return 0; | |
559 | ||
930a7622 | 560 | rix = sc->rate_idx[sc->curchan->band][hw_rix]; |
8a63facc BC |
561 | if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) |
562 | rix = 0; | |
563 | ||
564 | return rix; | |
565 | } | |
566 | ||
567 | /***************\ | |
568 | * Buffers setup * | |
569 | \***************/ | |
570 | ||
571 | static | |
572 | struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) | |
573 | { | |
574 | struct ath_common *common = ath5k_hw_common(sc->ah); | |
575 | struct sk_buff *skb; | |
fa1c114f JS |
576 | |
577 | /* | |
8a63facc BC |
578 | * Allocate buffer with headroom_needed space for the |
579 | * fake physical layer header at the start. | |
fa1c114f | 580 | */ |
8a63facc BC |
581 | skb = ath_rxbuf_alloc(common, |
582 | common->rx_bufsize, | |
583 | GFP_ATOMIC); | |
fa1c114f | 584 | |
8a63facc BC |
585 | if (!skb) { |
586 | ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", | |
587 | common->rx_bufsize); | |
588 | return NULL; | |
fa1c114f JS |
589 | } |
590 | ||
aeae4ac9 | 591 | *skb_addr = dma_map_single(sc->dev, |
8a63facc | 592 | skb->data, common->rx_bufsize, |
aeae4ac9 FF |
593 | DMA_FROM_DEVICE); |
594 | ||
595 | if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) { | |
8a63facc BC |
596 | ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); |
597 | dev_kfree_skb(skb); | |
598 | return NULL; | |
0e149cf5 | 599 | } |
8a63facc BC |
600 | return skb; |
601 | } | |
0e149cf5 | 602 | |
8a63facc BC |
603 | static int |
604 | ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) | |
605 | { | |
606 | struct ath5k_hw *ah = sc->ah; | |
607 | struct sk_buff *skb = bf->skb; | |
608 | struct ath5k_desc *ds; | |
609 | int ret; | |
fa1c114f | 610 | |
8a63facc BC |
611 | if (!skb) { |
612 | skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); | |
613 | if (!skb) | |
614 | return -ENOMEM; | |
615 | bf->skb = skb; | |
f769c36b BC |
616 | } |
617 | ||
8a63facc BC |
618 | /* |
619 | * Setup descriptors. For receive we always terminate | |
620 | * the descriptor list with a self-linked entry so we'll | |
621 | * not get overrun under high load (as can happen with a | |
622 | * 5212 when ANI processing enables PHY error frames). | |
623 | * | |
624 | * To ensure the last descriptor is self-linked we create | |
625 | * each descriptor as self-linked and add it to the end. As | |
626 | * each additional descriptor is added the previous self-linked | |
627 | * entry is "fixed" naturally. This should be safe even | |
628 | * if DMA is happening. When processing RX interrupts we | |
629 | * never remove/process the last, self-linked, entry on the | |
630 | * descriptor list. This ensures the hardware always has | |
631 | * someplace to write a new frame. | |
632 | */ | |
633 | ds = bf->desc; | |
634 | ds->ds_link = bf->daddr; /* link to self */ | |
635 | ds->ds_data = bf->skbaddr; | |
636 | ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); | |
fa1c114f | 637 | if (ret) { |
8a63facc BC |
638 | ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__); |
639 | return ret; | |
fa1c114f JS |
640 | } |
641 | ||
8a63facc BC |
642 | if (sc->rxlink != NULL) |
643 | *sc->rxlink = bf->daddr; | |
644 | sc->rxlink = &ds->ds_link; | |
fa1c114f | 645 | return 0; |
fa1c114f JS |
646 | } |
647 | ||
8a63facc | 648 | static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
fa1c114f | 649 | { |
8a63facc BC |
650 | struct ieee80211_hdr *hdr; |
651 | enum ath5k_pkt_type htype; | |
652 | __le16 fc; | |
fa1c114f | 653 | |
8a63facc BC |
654 | hdr = (struct ieee80211_hdr *)skb->data; |
655 | fc = hdr->frame_control; | |
fa1c114f | 656 | |
8a63facc BC |
657 | if (ieee80211_is_beacon(fc)) |
658 | htype = AR5K_PKT_TYPE_BEACON; | |
659 | else if (ieee80211_is_probe_resp(fc)) | |
660 | htype = AR5K_PKT_TYPE_PROBE_RESP; | |
661 | else if (ieee80211_is_atim(fc)) | |
662 | htype = AR5K_PKT_TYPE_ATIM; | |
663 | else if (ieee80211_is_pspoll(fc)) | |
664 | htype = AR5K_PKT_TYPE_PSPOLL; | |
fa1c114f | 665 | else |
8a63facc | 666 | htype = AR5K_PKT_TYPE_NORMAL; |
fa1c114f | 667 | |
8a63facc | 668 | return htype; |
42639fcd BC |
669 | } |
670 | ||
8a63facc BC |
671 | static int |
672 | ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, | |
673 | struct ath5k_txq *txq, int padsize) | |
fa1c114f | 674 | { |
8a63facc BC |
675 | struct ath5k_hw *ah = sc->ah; |
676 | struct ath5k_desc *ds = bf->desc; | |
677 | struct sk_buff *skb = bf->skb; | |
678 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
679 | unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; | |
680 | struct ieee80211_rate *rate; | |
681 | unsigned int mrr_rate[3], mrr_tries[3]; | |
682 | int i, ret; | |
683 | u16 hw_rate; | |
684 | u16 cts_rate = 0; | |
685 | u16 duration = 0; | |
686 | u8 rc_flags; | |
fa1c114f | 687 | |
8a63facc | 688 | flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; |
fa1c114f | 689 | |
8a63facc | 690 | /* XXX endianness */ |
aeae4ac9 FF |
691 | bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, |
692 | DMA_TO_DEVICE); | |
fa1c114f | 693 | |
8a63facc | 694 | rate = ieee80211_get_tx_rate(sc->hw, info); |
29ad2fac JL |
695 | if (!rate) { |
696 | ret = -EINVAL; | |
697 | goto err_unmap; | |
698 | } | |
fa1c114f | 699 | |
8a63facc BC |
700 | if (info->flags & IEEE80211_TX_CTL_NO_ACK) |
701 | flags |= AR5K_TXDESC_NOACK; | |
fa1c114f | 702 | |
8a63facc BC |
703 | rc_flags = info->control.rates[0].flags; |
704 | hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? | |
705 | rate->hw_value_short : rate->hw_value; | |
42639fcd | 706 | |
8a63facc BC |
707 | pktlen = skb->len; |
708 | ||
709 | /* FIXME: If we are in g mode and rate is a CCK rate | |
710 | * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta | |
711 | * from tx power (value is in dB units already) */ | |
712 | if (info->control.hw_key) { | |
713 | keyidx = info->control.hw_key->hw_key_idx; | |
714 | pktlen += info->control.hw_key->icv_len; | |
715 | } | |
716 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
717 | flags |= AR5K_TXDESC_RTSENA; | |
718 | cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; | |
719 | duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, | |
b1ae1edf | 720 | info->control.vif, pktlen, info)); |
8a63facc BC |
721 | } |
722 | if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
723 | flags |= AR5K_TXDESC_CTSENA; | |
724 | cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; | |
725 | duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, | |
b1ae1edf | 726 | info->control.vif, pktlen, info)); |
8a63facc BC |
727 | } |
728 | ret = ah->ah_setup_tx_desc(ah, ds, pktlen, | |
729 | ieee80211_get_hdrlen_from_skb(skb), padsize, | |
730 | get_hw_packet_type(skb), | |
731 | (sc->power_level * 2), | |
732 | hw_rate, | |
733 | info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, | |
734 | cts_rate, duration); | |
735 | if (ret) | |
736 | goto err_unmap; | |
737 | ||
738 | memset(mrr_rate, 0, sizeof(mrr_rate)); | |
739 | memset(mrr_tries, 0, sizeof(mrr_tries)); | |
740 | for (i = 0; i < 3; i++) { | |
741 | rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); | |
742 | if (!rate) | |
400ec45a | 743 | break; |
fa1c114f | 744 | |
8a63facc BC |
745 | mrr_rate[i] = rate->hw_value; |
746 | mrr_tries[i] = info->control.rates[i + 1].count; | |
fa1c114f JS |
747 | } |
748 | ||
8a63facc BC |
749 | ath5k_hw_setup_mrr_tx_desc(ah, ds, |
750 | mrr_rate[0], mrr_tries[0], | |
751 | mrr_rate[1], mrr_tries[1], | |
752 | mrr_rate[2], mrr_tries[2]); | |
fa1c114f | 753 | |
8a63facc BC |
754 | ds->ds_link = 0; |
755 | ds->ds_data = bf->skbaddr; | |
63266a65 | 756 | |
8a63facc BC |
757 | spin_lock_bh(&txq->lock); |
758 | list_add_tail(&bf->list, &txq->q); | |
925e0b06 | 759 | txq->txq_len++; |
8a63facc BC |
760 | if (txq->link == NULL) /* is this first packet? */ |
761 | ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); | |
762 | else /* no, so only link it */ | |
763 | *txq->link = bf->daddr; | |
63266a65 | 764 | |
8a63facc BC |
765 | txq->link = &ds->ds_link; |
766 | ath5k_hw_start_tx_dma(ah, txq->qnum); | |
767 | mmiowb(); | |
768 | spin_unlock_bh(&txq->lock); | |
769 | ||
770 | return 0; | |
771 | err_unmap: | |
aeae4ac9 | 772 | dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); |
8a63facc | 773 | return ret; |
63266a65 BR |
774 | } |
775 | ||
8a63facc BC |
776 | /*******************\ |
777 | * Descriptors setup * | |
778 | \*******************/ | |
779 | ||
d8ee398d | 780 | static int |
aeae4ac9 | 781 | ath5k_desc_alloc(struct ath5k_softc *sc) |
fa1c114f | 782 | { |
8a63facc BC |
783 | struct ath5k_desc *ds; |
784 | struct ath5k_buf *bf; | |
785 | dma_addr_t da; | |
786 | unsigned int i; | |
787 | int ret; | |
d8ee398d | 788 | |
8a63facc BC |
789 | /* allocate descriptors */ |
790 | sc->desc_len = sizeof(struct ath5k_desc) * | |
791 | (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); | |
aeae4ac9 FF |
792 | |
793 | sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len, | |
794 | &sc->desc_daddr, GFP_KERNEL); | |
8a63facc BC |
795 | if (sc->desc == NULL) { |
796 | ATH5K_ERR(sc, "can't allocate descriptors\n"); | |
797 | ret = -ENOMEM; | |
798 | goto err; | |
799 | } | |
800 | ds = sc->desc; | |
801 | da = sc->desc_daddr; | |
802 | ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", | |
803 | ds, sc->desc_len, (unsigned long long)sc->desc_daddr); | |
fa1c114f | 804 | |
8a63facc BC |
805 | bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, |
806 | sizeof(struct ath5k_buf), GFP_KERNEL); | |
807 | if (bf == NULL) { | |
808 | ATH5K_ERR(sc, "can't allocate bufptr\n"); | |
809 | ret = -ENOMEM; | |
810 | goto err_free; | |
811 | } | |
812 | sc->bufptr = bf; | |
fa1c114f | 813 | |
8a63facc BC |
814 | INIT_LIST_HEAD(&sc->rxbuf); |
815 | for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { | |
816 | bf->desc = ds; | |
817 | bf->daddr = da; | |
818 | list_add_tail(&bf->list, &sc->rxbuf); | |
819 | } | |
d8ee398d | 820 | |
8a63facc BC |
821 | INIT_LIST_HEAD(&sc->txbuf); |
822 | sc->txbuf_len = ATH_TXBUF; | |
823 | for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, | |
824 | da += sizeof(*ds)) { | |
825 | bf->desc = ds; | |
826 | bf->daddr = da; | |
827 | list_add_tail(&bf->list, &sc->txbuf); | |
fa1c114f JS |
828 | } |
829 | ||
b1ae1edf BG |
830 | /* beacon buffers */ |
831 | INIT_LIST_HEAD(&sc->bcbuf); | |
832 | for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { | |
833 | bf->desc = ds; | |
834 | bf->daddr = da; | |
835 | list_add_tail(&bf->list, &sc->bcbuf); | |
836 | } | |
fa1c114f | 837 | |
8a63facc BC |
838 | return 0; |
839 | err_free: | |
aeae4ac9 | 840 | dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); |
8a63facc BC |
841 | err: |
842 | sc->desc = NULL; | |
843 | return ret; | |
844 | } | |
fa1c114f | 845 | |
cd2c5486 BR |
846 | void |
847 | ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) | |
848 | { | |
849 | BUG_ON(!bf); | |
850 | if (!bf->skb) | |
851 | return; | |
852 | dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len, | |
853 | DMA_TO_DEVICE); | |
854 | dev_kfree_skb_any(bf->skb); | |
855 | bf->skb = NULL; | |
856 | bf->skbaddr = 0; | |
857 | bf->desc->ds_data = 0; | |
858 | } | |
859 | ||
860 | void | |
861 | ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) | |
862 | { | |
863 | struct ath5k_hw *ah = sc->ah; | |
864 | struct ath_common *common = ath5k_hw_common(ah); | |
865 | ||
866 | BUG_ON(!bf); | |
867 | if (!bf->skb) | |
868 | return; | |
869 | dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize, | |
870 | DMA_FROM_DEVICE); | |
871 | dev_kfree_skb_any(bf->skb); | |
872 | bf->skb = NULL; | |
873 | bf->skbaddr = 0; | |
874 | bf->desc->ds_data = 0; | |
875 | } | |
876 | ||
8a63facc | 877 | static void |
aeae4ac9 | 878 | ath5k_desc_free(struct ath5k_softc *sc) |
8a63facc BC |
879 | { |
880 | struct ath5k_buf *bf; | |
d8ee398d | 881 | |
8a63facc BC |
882 | list_for_each_entry(bf, &sc->txbuf, list) |
883 | ath5k_txbuf_free_skb(sc, bf); | |
884 | list_for_each_entry(bf, &sc->rxbuf, list) | |
885 | ath5k_rxbuf_free_skb(sc, bf); | |
b1ae1edf BG |
886 | list_for_each_entry(bf, &sc->bcbuf, list) |
887 | ath5k_txbuf_free_skb(sc, bf); | |
d8ee398d | 888 | |
8a63facc | 889 | /* Free memory associated with all descriptors */ |
aeae4ac9 | 890 | dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); |
8a63facc BC |
891 | sc->desc = NULL; |
892 | sc->desc_daddr = 0; | |
d8ee398d | 893 | |
8a63facc BC |
894 | kfree(sc->bufptr); |
895 | sc->bufptr = NULL; | |
fa1c114f JS |
896 | } |
897 | ||
8a63facc BC |
898 | |
899 | /**************\ | |
900 | * Queues setup * | |
901 | \**************/ | |
902 | ||
903 | static struct ath5k_txq * | |
904 | ath5k_txq_setup(struct ath5k_softc *sc, | |
905 | int qtype, int subtype) | |
fa1c114f | 906 | { |
8a63facc BC |
907 | struct ath5k_hw *ah = sc->ah; |
908 | struct ath5k_txq *txq; | |
909 | struct ath5k_txq_info qi = { | |
910 | .tqi_subtype = subtype, | |
de8af455 BR |
911 | /* XXX: default values not correct for B and XR channels, |
912 | * but who cares? */ | |
913 | .tqi_aifs = AR5K_TUNE_AIFS, | |
914 | .tqi_cw_min = AR5K_TUNE_CWMIN, | |
915 | .tqi_cw_max = AR5K_TUNE_CWMAX | |
8a63facc BC |
916 | }; |
917 | int qnum; | |
d8ee398d | 918 | |
e30eb4ab | 919 | /* |
8a63facc BC |
920 | * Enable interrupts only for EOL and DESC conditions. |
921 | * We mark tx descriptors to receive a DESC interrupt | |
922 | * when a tx queue gets deep; otherwise we wait for the | |
923 | * EOL to reap descriptors. Note that this is done to | |
924 | * reduce interrupt load and this only defers reaping | |
925 | * descriptors, never transmitting frames. Aside from | |
926 | * reducing interrupts this also permits more concurrency. | |
927 | * The only potential downside is if the tx queue backs | |
928 | * up in which case the top half of the kernel may backup | |
929 | * due to a lack of tx descriptors. | |
e30eb4ab | 930 | */ |
8a63facc BC |
931 | qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | |
932 | AR5K_TXQ_FLAG_TXDESCINT_ENABLE; | |
933 | qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); | |
934 | if (qnum < 0) { | |
935 | /* | |
936 | * NB: don't print a message, this happens | |
937 | * normally on parts with too few tx queues | |
938 | */ | |
939 | return ERR_PTR(qnum); | |
940 | } | |
941 | if (qnum >= ARRAY_SIZE(sc->txqs)) { | |
942 | ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", | |
943 | qnum, ARRAY_SIZE(sc->txqs)); | |
944 | ath5k_hw_release_tx_queue(ah, qnum); | |
945 | return ERR_PTR(-EINVAL); | |
946 | } | |
947 | txq = &sc->txqs[qnum]; | |
948 | if (!txq->setup) { | |
949 | txq->qnum = qnum; | |
950 | txq->link = NULL; | |
951 | INIT_LIST_HEAD(&txq->q); | |
952 | spin_lock_init(&txq->lock); | |
953 | txq->setup = true; | |
925e0b06 | 954 | txq->txq_len = 0; |
4edd761f | 955 | txq->txq_poll_mark = false; |
923e5b3d | 956 | txq->txq_stuck = 0; |
8a63facc BC |
957 | } |
958 | return &sc->txqs[qnum]; | |
fa1c114f JS |
959 | } |
960 | ||
8a63facc BC |
961 | static int |
962 | ath5k_beaconq_setup(struct ath5k_hw *ah) | |
fa1c114f | 963 | { |
8a63facc | 964 | struct ath5k_txq_info qi = { |
de8af455 BR |
965 | /* XXX: default values not correct for B and XR channels, |
966 | * but who cares? */ | |
967 | .tqi_aifs = AR5K_TUNE_AIFS, | |
968 | .tqi_cw_min = AR5K_TUNE_CWMIN, | |
969 | .tqi_cw_max = AR5K_TUNE_CWMAX, | |
8a63facc BC |
970 | /* NB: for dynamic turbo, don't enable any other interrupts */ |
971 | .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE | |
972 | }; | |
d8ee398d | 973 | |
8a63facc | 974 | return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); |
fa1c114f JS |
975 | } |
976 | ||
8a63facc BC |
977 | static int |
978 | ath5k_beaconq_config(struct ath5k_softc *sc) | |
fa1c114f JS |
979 | { |
980 | struct ath5k_hw *ah = sc->ah; | |
8a63facc BC |
981 | struct ath5k_txq_info qi; |
982 | int ret; | |
fa1c114f | 983 | |
8a63facc BC |
984 | ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); |
985 | if (ret) | |
986 | goto err; | |
fa1c114f | 987 | |
8a63facc BC |
988 | if (sc->opmode == NL80211_IFTYPE_AP || |
989 | sc->opmode == NL80211_IFTYPE_MESH_POINT) { | |
990 | /* | |
991 | * Always burst out beacon and CAB traffic | |
992 | * (aifs = cwmin = cwmax = 0) | |
993 | */ | |
994 | qi.tqi_aifs = 0; | |
995 | qi.tqi_cw_min = 0; | |
996 | qi.tqi_cw_max = 0; | |
997 | } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { | |
998 | /* | |
999 | * Adhoc mode; backoff between 0 and (2 * cw_min). | |
1000 | */ | |
1001 | qi.tqi_aifs = 0; | |
1002 | qi.tqi_cw_min = 0; | |
de8af455 | 1003 | qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; |
8a63facc | 1004 | } |
fa1c114f | 1005 | |
8a63facc BC |
1006 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
1007 | "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", | |
1008 | qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); | |
fa1c114f | 1009 | |
8a63facc BC |
1010 | ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); |
1011 | if (ret) { | |
1012 | ATH5K_ERR(sc, "%s: unable to update parameters for beacon " | |
1013 | "hardware queue!\n", __func__); | |
1014 | goto err; | |
1015 | } | |
1016 | ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */ | |
1017 | if (ret) | |
1018 | goto err; | |
b7266047 | 1019 | |
8a63facc BC |
1020 | /* reconfigure cabq with ready time to 80% of beacon_interval */ |
1021 | ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); | |
1022 | if (ret) | |
1023 | goto err; | |
b7266047 | 1024 | |
8a63facc BC |
1025 | qi.tqi_ready_time = (sc->bintval * 80) / 100; |
1026 | ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); | |
1027 | if (ret) | |
1028 | goto err; | |
b7266047 | 1029 | |
8a63facc BC |
1030 | ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); |
1031 | err: | |
1032 | return ret; | |
d8ee398d LR |
1033 | } |
1034 | ||
80dac9ee NK |
1035 | /** |
1036 | * ath5k_drain_tx_buffs - Empty tx buffers | |
1037 | * | |
1038 | * @sc The &struct ath5k_softc | |
1039 | * | |
1040 | * Empty tx buffers from all queues in preparation | |
1041 | * of a reset or during shutdown. | |
1042 | * | |
1043 | * NB: this assumes output has been stopped and | |
1044 | * we do not need to block ath5k_tx_tasklet | |
1045 | */ | |
8a63facc | 1046 | static void |
80dac9ee | 1047 | ath5k_drain_tx_buffs(struct ath5k_softc *sc) |
8a63facc | 1048 | { |
80dac9ee | 1049 | struct ath5k_txq *txq; |
8a63facc | 1050 | struct ath5k_buf *bf, *bf0; |
80dac9ee | 1051 | int i; |
b6ea0356 | 1052 | |
80dac9ee NK |
1053 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { |
1054 | if (sc->txqs[i].setup) { | |
1055 | txq = &sc->txqs[i]; | |
1056 | spin_lock_bh(&txq->lock); | |
1057 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
1058 | ath5k_debug_printtxbuf(sc, bf); | |
b6ea0356 | 1059 | |
80dac9ee | 1060 | ath5k_txbuf_free_skb(sc, bf); |
fa1c114f | 1061 | |
80dac9ee NK |
1062 | spin_lock_bh(&sc->txbuflock); |
1063 | list_move_tail(&bf->list, &sc->txbuf); | |
1064 | sc->txbuf_len++; | |
1065 | txq->txq_len--; | |
1066 | spin_unlock_bh(&sc->txbuflock); | |
8a63facc | 1067 | } |
80dac9ee NK |
1068 | txq->link = NULL; |
1069 | txq->txq_poll_mark = false; | |
1070 | spin_unlock_bh(&txq->lock); | |
1071 | } | |
0452d4a5 | 1072 | } |
fa1c114f JS |
1073 | } |
1074 | ||
8a63facc BC |
1075 | static void |
1076 | ath5k_txq_release(struct ath5k_softc *sc) | |
2ac2927a | 1077 | { |
8a63facc BC |
1078 | struct ath5k_txq *txq = sc->txqs; |
1079 | unsigned int i; | |
2ac2927a | 1080 | |
8a63facc BC |
1081 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) |
1082 | if (txq->setup) { | |
1083 | ath5k_hw_release_tx_queue(sc->ah, txq->qnum); | |
1084 | txq->setup = false; | |
1085 | } | |
1086 | } | |
2ac2927a | 1087 | |
2ac2927a | 1088 | |
8a63facc BC |
1089 | /*************\ |
1090 | * RX Handling * | |
1091 | \*************/ | |
2ac2927a | 1092 | |
8a63facc BC |
1093 | /* |
1094 | * Enable the receive h/w following a reset. | |
1095 | */ | |
fa1c114f | 1096 | static int |
8a63facc | 1097 | ath5k_rx_start(struct ath5k_softc *sc) |
fa1c114f JS |
1098 | { |
1099 | struct ath5k_hw *ah = sc->ah; | |
8a63facc BC |
1100 | struct ath_common *common = ath5k_hw_common(ah); |
1101 | struct ath5k_buf *bf; | |
1102 | int ret; | |
fa1c114f | 1103 | |
8a63facc | 1104 | common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); |
fa1c114f | 1105 | |
8a63facc BC |
1106 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", |
1107 | common->cachelsz, common->rx_bufsize); | |
2f7fe870 | 1108 | |
8a63facc BC |
1109 | spin_lock_bh(&sc->rxbuflock); |
1110 | sc->rxlink = NULL; | |
1111 | list_for_each_entry(bf, &sc->rxbuf, list) { | |
1112 | ret = ath5k_rxbuf_setup(sc, bf); | |
1113 | if (ret != 0) { | |
1114 | spin_unlock_bh(&sc->rxbuflock); | |
1115 | goto err; | |
1116 | } | |
2f7fe870 | 1117 | } |
8a63facc BC |
1118 | bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); |
1119 | ath5k_hw_set_rxdp(ah, bf->daddr); | |
1120 | spin_unlock_bh(&sc->rxbuflock); | |
2f7fe870 | 1121 | |
8a63facc | 1122 | ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ |
b1ae1edf | 1123 | ath5k_mode_setup(sc, NULL); /* set filters, etc. */ |
8a63facc | 1124 | ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ |
fa1c114f JS |
1125 | |
1126 | return 0; | |
8a63facc | 1127 | err: |
fa1c114f JS |
1128 | return ret; |
1129 | } | |
1130 | ||
8a63facc | 1131 | /* |
80dac9ee NK |
1132 | * Disable the receive logic on PCU (DRU) |
1133 | * In preparation for a shutdown. | |
1134 | * | |
1135 | * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop | |
1136 | * does. | |
8a63facc BC |
1137 | */ |
1138 | static void | |
1139 | ath5k_rx_stop(struct ath5k_softc *sc) | |
fa1c114f | 1140 | { |
8a63facc | 1141 | struct ath5k_hw *ah = sc->ah; |
fa1c114f | 1142 | |
8a63facc | 1143 | ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ |
80dac9ee | 1144 | ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ |
fa1c114f | 1145 | |
8a63facc BC |
1146 | ath5k_debug_printrxbuffs(sc, ah); |
1147 | } | |
fa1c114f | 1148 | |
8a63facc BC |
1149 | static unsigned int |
1150 | ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb, | |
1151 | struct ath5k_rx_status *rs) | |
1152 | { | |
1153 | struct ath5k_hw *ah = sc->ah; | |
1154 | struct ath_common *common = ath5k_hw_common(ah); | |
1155 | struct ieee80211_hdr *hdr = (void *)skb->data; | |
1156 | unsigned int keyix, hlen; | |
fa1c114f | 1157 | |
8a63facc BC |
1158 | if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && |
1159 | rs->rs_keyix != AR5K_RXKEYIX_INVALID) | |
1160 | return RX_FLAG_DECRYPTED; | |
fa1c114f | 1161 | |
8a63facc BC |
1162 | /* Apparently when a default key is used to decrypt the packet |
1163 | the hw does not set the index used to decrypt. In such cases | |
1164 | get the index from the packet. */ | |
1165 | hlen = ieee80211_hdrlen(hdr->frame_control); | |
1166 | if (ieee80211_has_protected(hdr->frame_control) && | |
1167 | !(rs->rs_status & AR5K_RXERR_DECRYPT) && | |
1168 | skb->len >= hlen + 4) { | |
1169 | keyix = skb->data[hlen + 3] >> 6; | |
1170 | ||
1171 | if (test_bit(keyix, common->keymap)) | |
1172 | return RX_FLAG_DECRYPTED; | |
1173 | } | |
fa1c114f JS |
1174 | |
1175 | return 0; | |
fa1c114f JS |
1176 | } |
1177 | ||
8a63facc | 1178 | |
fa1c114f | 1179 | static void |
8a63facc BC |
1180 | ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, |
1181 | struct ieee80211_rx_status *rxs) | |
fa1c114f | 1182 | { |
8a63facc BC |
1183 | struct ath_common *common = ath5k_hw_common(sc->ah); |
1184 | u64 tsf, bc_tstamp; | |
1185 | u32 hw_tu; | |
1186 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; | |
fa1c114f | 1187 | |
8a63facc BC |
1188 | if (ieee80211_is_beacon(mgmt->frame_control) && |
1189 | le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && | |
1190 | memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { | |
1191 | /* | |
1192 | * Received an IBSS beacon with the same BSSID. Hardware *must* | |
1193 | * have updated the local TSF. We have to work around various | |
1194 | * hardware bugs, though... | |
1195 | */ | |
1196 | tsf = ath5k_hw_get_tsf64(sc->ah); | |
1197 | bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); | |
1198 | hw_tu = TSF_TO_TU(tsf); | |
fa1c114f | 1199 | |
8a63facc BC |
1200 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, |
1201 | "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", | |
1202 | (unsigned long long)bc_tstamp, | |
1203 | (unsigned long long)rxs->mactime, | |
1204 | (unsigned long long)(rxs->mactime - bc_tstamp), | |
1205 | (unsigned long long)tsf); | |
fa1c114f | 1206 | |
8a63facc BC |
1207 | /* |
1208 | * Sometimes the HW will give us a wrong tstamp in the rx | |
1209 | * status, causing the timestamp extension to go wrong. | |
1210 | * (This seems to happen especially with beacon frames bigger | |
1211 | * than 78 byte (incl. FCS)) | |
1212 | * But we know that the receive timestamp must be later than the | |
1213 | * timestamp of the beacon since HW must have synced to that. | |
1214 | * | |
1215 | * NOTE: here we assume mactime to be after the frame was | |
1216 | * received, not like mac80211 which defines it at the start. | |
1217 | */ | |
1218 | if (bc_tstamp > rxs->mactime) { | |
1219 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
1220 | "fixing mactime from %llx to %llx\n", | |
1221 | (unsigned long long)rxs->mactime, | |
1222 | (unsigned long long)tsf); | |
1223 | rxs->mactime = tsf; | |
1224 | } | |
fa1c114f | 1225 | |
8a63facc BC |
1226 | /* |
1227 | * Local TSF might have moved higher than our beacon timers, | |
1228 | * in that case we have to update them to continue sending | |
1229 | * beacons. This also takes care of synchronizing beacon sending | |
1230 | * times with other stations. | |
1231 | */ | |
1232 | if (hw_tu >= sc->nexttbtt) | |
1233 | ath5k_beacon_update_timers(sc, bc_tstamp); | |
7f896126 BR |
1234 | |
1235 | /* Check if the beacon timers are still correct, because a TSF | |
1236 | * update might have created a window between them - for a | |
1237 | * longer description see the comment of this function: */ | |
1238 | if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) { | |
1239 | ath5k_beacon_update_timers(sc, bc_tstamp); | |
1240 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
1241 | "fixed beacon timers after beacon receive\n"); | |
1242 | } | |
8a63facc BC |
1243 | } |
1244 | } | |
fa1c114f | 1245 | |
8a63facc BC |
1246 | static void |
1247 | ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi) | |
1248 | { | |
1249 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; | |
1250 | struct ath5k_hw *ah = sc->ah; | |
1251 | struct ath_common *common = ath5k_hw_common(ah); | |
fa1c114f | 1252 | |
8a63facc BC |
1253 | /* only beacons from our BSSID */ |
1254 | if (!ieee80211_is_beacon(mgmt->frame_control) || | |
1255 | memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0) | |
1256 | return; | |
fa1c114f | 1257 | |
eef39bef | 1258 | ewma_add(&ah->ah_beacon_rssi_avg, rssi); |
fa1c114f | 1259 | |
8a63facc BC |
1260 | /* in IBSS mode we should keep RSSI statistics per neighbour */ |
1261 | /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ | |
1262 | } | |
fa1c114f | 1263 | |
8a63facc BC |
1264 | /* |
1265 | * Compute padding position. skb must contain an IEEE 802.11 frame | |
1266 | */ | |
1267 | static int ath5k_common_padpos(struct sk_buff *skb) | |
fa1c114f | 1268 | { |
8a63facc BC |
1269 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
1270 | __le16 frame_control = hdr->frame_control; | |
1271 | int padpos = 24; | |
fa1c114f | 1272 | |
8a63facc BC |
1273 | if (ieee80211_has_a4(frame_control)) { |
1274 | padpos += ETH_ALEN; | |
fa1c114f | 1275 | } |
8a63facc BC |
1276 | if (ieee80211_is_data_qos(frame_control)) { |
1277 | padpos += IEEE80211_QOS_CTL_LEN; | |
fa1c114f | 1278 | } |
8a63facc BC |
1279 | |
1280 | return padpos; | |
fa1c114f JS |
1281 | } |
1282 | ||
8a63facc BC |
1283 | /* |
1284 | * This function expects an 802.11 frame and returns the number of | |
1285 | * bytes added, or -1 if we don't have enough header room. | |
1286 | */ | |
1287 | static int ath5k_add_padding(struct sk_buff *skb) | |
fa1c114f | 1288 | { |
8a63facc BC |
1289 | int padpos = ath5k_common_padpos(skb); |
1290 | int padsize = padpos & 3; | |
fa1c114f | 1291 | |
8a63facc | 1292 | if (padsize && skb->len>padpos) { |
fa1c114f | 1293 | |
8a63facc BC |
1294 | if (skb_headroom(skb) < padsize) |
1295 | return -1; | |
fa1c114f | 1296 | |
8a63facc BC |
1297 | skb_push(skb, padsize); |
1298 | memmove(skb->data, skb->data+padsize, padpos); | |
1299 | return padsize; | |
1300 | } | |
a951ae21 | 1301 | |
8a63facc BC |
1302 | return 0; |
1303 | } | |
fa1c114f | 1304 | |
8a63facc BC |
1305 | /* |
1306 | * The MAC header is padded to have 32-bit boundary if the | |
1307 | * packet payload is non-zero. The general calculation for | |
1308 | * padsize would take into account odd header lengths: | |
1309 | * padsize = 4 - (hdrlen & 3); however, since only | |
1310 | * even-length headers are used, padding can only be 0 or 2 | |
1311 | * bytes and we can optimize this a bit. We must not try to | |
1312 | * remove padding from short control frames that do not have a | |
1313 | * payload. | |
1314 | * | |
1315 | * This function expects an 802.11 frame and returns the number of | |
1316 | * bytes removed. | |
1317 | */ | |
1318 | static int ath5k_remove_padding(struct sk_buff *skb) | |
1319 | { | |
1320 | int padpos = ath5k_common_padpos(skb); | |
1321 | int padsize = padpos & 3; | |
6d91e1d8 | 1322 | |
8a63facc BC |
1323 | if (padsize && skb->len>=padpos+padsize) { |
1324 | memmove(skb->data + padsize, skb->data, padpos); | |
1325 | skb_pull(skb, padsize); | |
1326 | return padsize; | |
fa1c114f | 1327 | } |
a951ae21 | 1328 | |
8a63facc | 1329 | return 0; |
fa1c114f JS |
1330 | } |
1331 | ||
1332 | static void | |
8a63facc BC |
1333 | ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb, |
1334 | struct ath5k_rx_status *rs) | |
fa1c114f | 1335 | { |
8a63facc BC |
1336 | struct ieee80211_rx_status *rxs; |
1337 | ||
1338 | ath5k_remove_padding(skb); | |
1339 | ||
1340 | rxs = IEEE80211_SKB_RXCB(skb); | |
1341 | ||
1342 | rxs->flag = 0; | |
1343 | if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) | |
1344 | rxs->flag |= RX_FLAG_MMIC_ERROR; | |
fa1c114f JS |
1345 | |
1346 | /* | |
8a63facc BC |
1347 | * always extend the mac timestamp, since this information is |
1348 | * also needed for proper IBSS merging. | |
1349 | * | |
1350 | * XXX: it might be too late to do it here, since rs_tstamp is | |
1351 | * 15bit only. that means TSF extension has to be done within | |
1352 | * 32768usec (about 32ms). it might be necessary to move this to | |
1353 | * the interrupt handler, like it is done in madwifi. | |
1354 | * | |
1355 | * Unfortunately we don't know when the hardware takes the rx | |
1356 | * timestamp (beginning of phy frame, data frame, end of rx?). | |
1357 | * The only thing we know is that it is hardware specific... | |
1358 | * On AR5213 it seems the rx timestamp is at the end of the | |
1359 | * frame, but i'm not sure. | |
1360 | * | |
1361 | * NOTE: mac80211 defines mactime at the beginning of the first | |
1362 | * data symbol. Since we don't have any time references it's | |
1363 | * impossible to comply to that. This affects IBSS merge only | |
1364 | * right now, so it's not too bad... | |
fa1c114f | 1365 | */ |
8a63facc BC |
1366 | rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp); |
1367 | rxs->flag |= RX_FLAG_TSFT; | |
fa1c114f | 1368 | |
8a63facc | 1369 | rxs->freq = sc->curchan->center_freq; |
930a7622 | 1370 | rxs->band = sc->curchan->band; |
fa1c114f | 1371 | |
8a63facc | 1372 | rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi; |
fa1c114f | 1373 | |
8a63facc | 1374 | rxs->antenna = rs->rs_antenna; |
fa1c114f | 1375 | |
8a63facc BC |
1376 | if (rs->rs_antenna > 0 && rs->rs_antenna < 5) |
1377 | sc->stats.antenna_rx[rs->rs_antenna]++; | |
1378 | else | |
1379 | sc->stats.antenna_rx[0]++; /* invalid */ | |
fa1c114f | 1380 | |
8a63facc BC |
1381 | rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate); |
1382 | rxs->flag |= ath5k_rx_decrypted(sc, skb, rs); | |
fa1c114f | 1383 | |
8a63facc | 1384 | if (rxs->rate_idx >= 0 && rs->rs_rate == |
930a7622 | 1385 | sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short) |
8a63facc | 1386 | rxs->flag |= RX_FLAG_SHORTPRE; |
fa1c114f | 1387 | |
8a63facc | 1388 | ath5k_debug_dump_skb(sc, skb, "RX ", 0); |
fa1c114f | 1389 | |
8a63facc | 1390 | ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi); |
fa1c114f | 1391 | |
8a63facc BC |
1392 | /* check beacons in IBSS mode */ |
1393 | if (sc->opmode == NL80211_IFTYPE_ADHOC) | |
1394 | ath5k_check_ibss_tsf(sc, skb, rxs); | |
fa1c114f | 1395 | |
8a63facc BC |
1396 | ieee80211_rx(sc->hw, skb); |
1397 | } | |
fa1c114f | 1398 | |
8a63facc BC |
1399 | /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? |
1400 | * | |
1401 | * Check if we want to further process this frame or not. Also update | |
1402 | * statistics. Return true if we want this frame, false if not. | |
fa1c114f | 1403 | */ |
8a63facc BC |
1404 | static bool |
1405 | ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs) | |
fa1c114f | 1406 | { |
8a63facc | 1407 | sc->stats.rx_all_count++; |
b72acddb | 1408 | sc->stats.rx_bytes_count += rs->rs_datalen; |
fa1c114f | 1409 | |
8a63facc BC |
1410 | if (unlikely(rs->rs_status)) { |
1411 | if (rs->rs_status & AR5K_RXERR_CRC) | |
1412 | sc->stats.rxerr_crc++; | |
1413 | if (rs->rs_status & AR5K_RXERR_FIFO) | |
1414 | sc->stats.rxerr_fifo++; | |
1415 | if (rs->rs_status & AR5K_RXERR_PHY) { | |
1416 | sc->stats.rxerr_phy++; | |
1417 | if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) | |
1418 | sc->stats.rxerr_phy_code[rs->rs_phyerr]++; | |
1419 | return false; | |
1420 | } | |
1421 | if (rs->rs_status & AR5K_RXERR_DECRYPT) { | |
1422 | /* | |
1423 | * Decrypt error. If the error occurred | |
1424 | * because there was no hardware key, then | |
1425 | * let the frame through so the upper layers | |
1426 | * can process it. This is necessary for 5210 | |
1427 | * parts which have no way to setup a ``clear'' | |
1428 | * key cache entry. | |
1429 | * | |
1430 | * XXX do key cache faulting | |
1431 | */ | |
1432 | sc->stats.rxerr_decrypt++; | |
1433 | if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && | |
1434 | !(rs->rs_status & AR5K_RXERR_CRC)) | |
1435 | return true; | |
1436 | } | |
1437 | if (rs->rs_status & AR5K_RXERR_MIC) { | |
1438 | sc->stats.rxerr_mic++; | |
1439 | return true; | |
fa1c114f | 1440 | } |
fa1c114f | 1441 | |
8a63facc BC |
1442 | /* reject any frames with non-crypto errors */ |
1443 | if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) | |
1444 | return false; | |
1445 | } | |
fa1c114f | 1446 | |
8a63facc BC |
1447 | if (unlikely(rs->rs_more)) { |
1448 | sc->stats.rxerr_jumbo++; | |
1449 | return false; | |
1450 | } | |
1451 | return true; | |
fa1c114f JS |
1452 | } |
1453 | ||
fa1c114f | 1454 | static void |
8a63facc | 1455 | ath5k_tasklet_rx(unsigned long data) |
fa1c114f | 1456 | { |
8a63facc BC |
1457 | struct ath5k_rx_status rs = {}; |
1458 | struct sk_buff *skb, *next_skb; | |
1459 | dma_addr_t next_skb_addr; | |
1460 | struct ath5k_softc *sc = (void *)data; | |
dc1e001b LR |
1461 | struct ath5k_hw *ah = sc->ah; |
1462 | struct ath_common *common = ath5k_hw_common(ah); | |
8a63facc BC |
1463 | struct ath5k_buf *bf; |
1464 | struct ath5k_desc *ds; | |
1465 | int ret; | |
fa1c114f | 1466 | |
8a63facc BC |
1467 | spin_lock(&sc->rxbuflock); |
1468 | if (list_empty(&sc->rxbuf)) { | |
1469 | ATH5K_WARN(sc, "empty rx buf pool\n"); | |
1470 | goto unlock; | |
1471 | } | |
1472 | do { | |
1473 | bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); | |
1474 | BUG_ON(bf->skb == NULL); | |
1475 | skb = bf->skb; | |
1476 | ds = bf->desc; | |
fa1c114f | 1477 | |
8a63facc BC |
1478 | /* bail if HW is still using self-linked descriptor */ |
1479 | if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) | |
1480 | break; | |
fa1c114f | 1481 | |
8a63facc BC |
1482 | ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); |
1483 | if (unlikely(ret == -EINPROGRESS)) | |
1484 | break; | |
1485 | else if (unlikely(ret)) { | |
1486 | ATH5K_ERR(sc, "error in processing rx descriptor\n"); | |
1487 | sc->stats.rxerr_proc++; | |
1488 | break; | |
1489 | } | |
fa1c114f | 1490 | |
8a63facc BC |
1491 | if (ath5k_receive_frame_ok(sc, &rs)) { |
1492 | next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); | |
fa1c114f | 1493 | |
8a63facc BC |
1494 | /* |
1495 | * If we can't replace bf->skb with a new skb under | |
1496 | * memory pressure, just skip this packet | |
1497 | */ | |
1498 | if (!next_skb) | |
1499 | goto next; | |
036cd1ec | 1500 | |
aeae4ac9 | 1501 | dma_unmap_single(sc->dev, bf->skbaddr, |
8a63facc | 1502 | common->rx_bufsize, |
aeae4ac9 | 1503 | DMA_FROM_DEVICE); |
036cd1ec | 1504 | |
8a63facc | 1505 | skb_put(skb, rs.rs_datalen); |
6ba81c2c | 1506 | |
8a63facc | 1507 | ath5k_receive_frame(sc, skb, &rs); |
6ba81c2c | 1508 | |
8a63facc BC |
1509 | bf->skb = next_skb; |
1510 | bf->skbaddr = next_skb_addr; | |
036cd1ec | 1511 | } |
8a63facc BC |
1512 | next: |
1513 | list_move_tail(&bf->list, &sc->rxbuf); | |
1514 | } while (ath5k_rxbuf_setup(sc, bf) == 0); | |
1515 | unlock: | |
1516 | spin_unlock(&sc->rxbuflock); | |
036cd1ec BR |
1517 | } |
1518 | ||
b4ea449d | 1519 | |
8a63facc BC |
1520 | /*************\ |
1521 | * TX Handling * | |
1522 | \*************/ | |
b4ea449d | 1523 | |
cd2c5486 BR |
1524 | int |
1525 | ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, | |
1526 | struct ath5k_txq *txq) | |
8a63facc BC |
1527 | { |
1528 | struct ath5k_softc *sc = hw->priv; | |
1529 | struct ath5k_buf *bf; | |
1530 | unsigned long flags; | |
1531 | int padsize; | |
b4ea449d | 1532 | |
8a63facc | 1533 | ath5k_debug_dump_skb(sc, skb, "TX ", 1); |
b4ea449d | 1534 | |
8a63facc BC |
1535 | /* |
1536 | * The hardware expects the header padded to 4 byte boundaries. | |
1537 | * If this is not the case, we add the padding after the header. | |
1538 | */ | |
1539 | padsize = ath5k_add_padding(skb); | |
1540 | if (padsize < 0) { | |
1541 | ATH5K_ERR(sc, "tx hdrlen not %%4: not enough" | |
1542 | " headroom to pad"); | |
1543 | goto drop_packet; | |
1544 | } | |
8127fbdc | 1545 | |
925e0b06 BR |
1546 | if (txq->txq_len >= ATH5K_TXQ_LEN_MAX) |
1547 | ieee80211_stop_queue(hw, txq->qnum); | |
1548 | ||
8a63facc BC |
1549 | spin_lock_irqsave(&sc->txbuflock, flags); |
1550 | if (list_empty(&sc->txbuf)) { | |
1551 | ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); | |
1552 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
651d9375 | 1553 | ieee80211_stop_queues(hw); |
8a63facc | 1554 | goto drop_packet; |
8127fbdc | 1555 | } |
8a63facc BC |
1556 | bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); |
1557 | list_del(&bf->list); | |
1558 | sc->txbuf_len--; | |
1559 | if (list_empty(&sc->txbuf)) | |
1560 | ieee80211_stop_queues(hw); | |
1561 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
1562 | ||
1563 | bf->skb = skb; | |
1564 | ||
1565 | if (ath5k_txbuf_setup(sc, bf, txq, padsize)) { | |
1566 | bf->skb = NULL; | |
1567 | spin_lock_irqsave(&sc->txbuflock, flags); | |
1568 | list_add_tail(&bf->list, &sc->txbuf); | |
1569 | sc->txbuf_len++; | |
1570 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
1571 | goto drop_packet; | |
8127fbdc | 1572 | } |
8a63facc | 1573 | return NETDEV_TX_OK; |
8127fbdc | 1574 | |
8a63facc BC |
1575 | drop_packet: |
1576 | dev_kfree_skb_any(skb); | |
1577 | return NETDEV_TX_OK; | |
8127fbdc BP |
1578 | } |
1579 | ||
1440401e BR |
1580 | static void |
1581 | ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb, | |
1582 | struct ath5k_tx_status *ts) | |
1583 | { | |
1584 | struct ieee80211_tx_info *info; | |
1585 | int i; | |
1586 | ||
1587 | sc->stats.tx_all_count++; | |
b72acddb | 1588 | sc->stats.tx_bytes_count += skb->len; |
1440401e BR |
1589 | info = IEEE80211_SKB_CB(skb); |
1590 | ||
1591 | ieee80211_tx_info_clear_status(info); | |
1592 | for (i = 0; i < 4; i++) { | |
1593 | struct ieee80211_tx_rate *r = | |
1594 | &info->status.rates[i]; | |
1595 | ||
1596 | if (ts->ts_rate[i]) { | |
1597 | r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]); | |
1598 | r->count = ts->ts_retry[i]; | |
1599 | } else { | |
1600 | r->idx = -1; | |
1601 | r->count = 0; | |
1602 | } | |
1603 | } | |
1604 | ||
1605 | /* count the successful attempt as well */ | |
1606 | info->status.rates[ts->ts_final_idx].count++; | |
1607 | ||
1608 | if (unlikely(ts->ts_status)) { | |
1609 | sc->stats.ack_fail++; | |
1610 | if (ts->ts_status & AR5K_TXERR_FILT) { | |
1611 | info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
1612 | sc->stats.txerr_filt++; | |
1613 | } | |
1614 | if (ts->ts_status & AR5K_TXERR_XRETRY) | |
1615 | sc->stats.txerr_retry++; | |
1616 | if (ts->ts_status & AR5K_TXERR_FIFO) | |
1617 | sc->stats.txerr_fifo++; | |
1618 | } else { | |
1619 | info->flags |= IEEE80211_TX_STAT_ACK; | |
1620 | info->status.ack_signal = ts->ts_rssi; | |
1621 | } | |
1622 | ||
1623 | /* | |
1624 | * Remove MAC header padding before giving the frame | |
1625 | * back to mac80211. | |
1626 | */ | |
1627 | ath5k_remove_padding(skb); | |
1628 | ||
1629 | if (ts->ts_antenna > 0 && ts->ts_antenna < 5) | |
1630 | sc->stats.antenna_tx[ts->ts_antenna]++; | |
1631 | else | |
1632 | sc->stats.antenna_tx[0]++; /* invalid */ | |
1633 | ||
1634 | ieee80211_tx_status(sc->hw, skb); | |
1635 | } | |
8a63facc BC |
1636 | |
1637 | static void | |
1638 | ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) | |
8127fbdc | 1639 | { |
8a63facc BC |
1640 | struct ath5k_tx_status ts = {}; |
1641 | struct ath5k_buf *bf, *bf0; | |
1642 | struct ath5k_desc *ds; | |
1643 | struct sk_buff *skb; | |
1440401e | 1644 | int ret; |
8127fbdc | 1645 | |
8a63facc BC |
1646 | spin_lock(&txq->lock); |
1647 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
23413296 BR |
1648 | |
1649 | txq->txq_poll_mark = false; | |
1650 | ||
1651 | /* skb might already have been processed last time. */ | |
1652 | if (bf->skb != NULL) { | |
1653 | ds = bf->desc; | |
1654 | ||
1655 | ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); | |
1656 | if (unlikely(ret == -EINPROGRESS)) | |
1657 | break; | |
1658 | else if (unlikely(ret)) { | |
1659 | ATH5K_ERR(sc, | |
1660 | "error %d while processing " | |
1661 | "queue %u\n", ret, txq->qnum); | |
1662 | break; | |
1663 | } | |
1664 | ||
1665 | skb = bf->skb; | |
1666 | bf->skb = NULL; | |
aeae4ac9 FF |
1667 | |
1668 | dma_unmap_single(sc->dev, bf->skbaddr, skb->len, | |
1669 | DMA_TO_DEVICE); | |
23413296 BR |
1670 | ath5k_tx_frame_completed(sc, skb, &ts); |
1671 | } | |
8127fbdc | 1672 | |
8a63facc BC |
1673 | /* |
1674 | * It's possible that the hardware can say the buffer is | |
1675 | * completed when it hasn't yet loaded the ds_link from | |
23413296 BR |
1676 | * host memory and moved on. |
1677 | * Always keep the last descriptor to avoid HW races... | |
8a63facc | 1678 | */ |
23413296 BR |
1679 | if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) { |
1680 | spin_lock(&sc->txbuflock); | |
1681 | list_move_tail(&bf->list, &sc->txbuf); | |
1682 | sc->txbuf_len++; | |
1683 | txq->txq_len--; | |
1684 | spin_unlock(&sc->txbuflock); | |
8a63facc | 1685 | } |
fa1c114f | 1686 | } |
fa1c114f | 1687 | spin_unlock(&txq->lock); |
4198a8d0 | 1688 | if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) |
925e0b06 | 1689 | ieee80211_wake_queue(sc->hw, txq->qnum); |
fa1c114f JS |
1690 | } |
1691 | ||
1692 | static void | |
1693 | ath5k_tasklet_tx(unsigned long data) | |
1694 | { | |
8784d2ee | 1695 | int i; |
fa1c114f JS |
1696 | struct ath5k_softc *sc = (void *)data; |
1697 | ||
8784d2ee BC |
1698 | for (i=0; i < AR5K_NUM_TX_QUEUES; i++) |
1699 | if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) | |
1700 | ath5k_tx_processq(sc, &sc->txqs[i]); | |
fa1c114f JS |
1701 | } |
1702 | ||
1703 | ||
fa1c114f JS |
1704 | /*****************\ |
1705 | * Beacon handling * | |
1706 | \*****************/ | |
1707 | ||
1708 | /* | |
1709 | * Setup the beacon frame for transmit. | |
1710 | */ | |
1711 | static int | |
e039fa4a | 1712 | ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) |
fa1c114f JS |
1713 | { |
1714 | struct sk_buff *skb = bf->skb; | |
a888d52d | 1715 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
fa1c114f JS |
1716 | struct ath5k_hw *ah = sc->ah; |
1717 | struct ath5k_desc *ds; | |
2bed03eb NK |
1718 | int ret = 0; |
1719 | u8 antenna; | |
fa1c114f | 1720 | u32 flags; |
8127fbdc | 1721 | const int padsize = 0; |
fa1c114f | 1722 | |
aeae4ac9 FF |
1723 | bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, |
1724 | DMA_TO_DEVICE); | |
fa1c114f JS |
1725 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " |
1726 | "skbaddr %llx\n", skb, skb->data, skb->len, | |
1727 | (unsigned long long)bf->skbaddr); | |
aeae4ac9 FF |
1728 | |
1729 | if (dma_mapping_error(sc->dev, bf->skbaddr)) { | |
fa1c114f JS |
1730 | ATH5K_ERR(sc, "beacon DMA mapping failed\n"); |
1731 | return -EIO; | |
1732 | } | |
1733 | ||
1734 | ds = bf->desc; | |
2bed03eb | 1735 | antenna = ah->ah_tx_ant; |
fa1c114f JS |
1736 | |
1737 | flags = AR5K_TXDESC_NOACK; | |
05c914fe | 1738 | if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { |
fa1c114f JS |
1739 | ds->ds_link = bf->daddr; /* self-linked */ |
1740 | flags |= AR5K_TXDESC_VEOL; | |
2bed03eb | 1741 | } else |
fa1c114f | 1742 | ds->ds_link = 0; |
2bed03eb NK |
1743 | |
1744 | /* | |
1745 | * If we use multiple antennas on AP and use | |
1746 | * the Sectored AP scenario, switch antenna every | |
1747 | * 4 beacons to make sure everybody hears our AP. | |
1748 | * When a client tries to associate, hw will keep | |
1749 | * track of the tx antenna to be used for this client | |
1750 | * automaticaly, based on ACKed packets. | |
1751 | * | |
1752 | * Note: AP still listens and transmits RTS on the | |
1753 | * default antenna which is supposed to be an omni. | |
1754 | * | |
1755 | * Note2: On sectored scenarios it's possible to have | |
a180a130 BC |
1756 | * multiple antennas (1 omni -- the default -- and 14 |
1757 | * sectors), so if we choose to actually support this | |
1758 | * mode, we need to allow the user to set how many antennas | |
1759 | * we have and tweak the code below to send beacons | |
1760 | * on all of them. | |
2bed03eb NK |
1761 | */ |
1762 | if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) | |
1763 | antenna = sc->bsent & 4 ? 2 : 1; | |
1764 | ||
fa1c114f | 1765 | |
8f655dde NK |
1766 | /* FIXME: If we are in g mode and rate is a CCK rate |
1767 | * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta | |
1768 | * from tx power (value is in dB units already) */ | |
fa1c114f | 1769 | ds->ds_data = bf->skbaddr; |
281c56dd | 1770 | ret = ah->ah_setup_tx_desc(ah, ds, skb->len, |
8127fbdc | 1771 | ieee80211_get_hdrlen_from_skb(skb), padsize, |
400ec45a | 1772 | AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), |
e039fa4a | 1773 | ieee80211_get_tx_rate(sc->hw, info)->hw_value, |
2e92e6f2 | 1774 | 1, AR5K_TXKEYIX_INVALID, |
400ec45a | 1775 | antenna, flags, 0, 0); |
fa1c114f JS |
1776 | if (ret) |
1777 | goto err_unmap; | |
1778 | ||
1779 | return 0; | |
1780 | err_unmap: | |
aeae4ac9 | 1781 | dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); |
fa1c114f JS |
1782 | return ret; |
1783 | } | |
1784 | ||
8a63facc BC |
1785 | /* |
1786 | * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, | |
1787 | * this is called only once at config_bss time, for AP we do it every | |
1788 | * SWBA interrupt so that the TIM will reflect buffered frames. | |
1789 | * | |
1790 | * Called with the beacon lock. | |
1791 | */ | |
cd2c5486 | 1792 | int |
8a63facc BC |
1793 | ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
1794 | { | |
1795 | int ret; | |
1796 | struct ath5k_softc *sc = hw->priv; | |
b1ae1edf | 1797 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
8a63facc BC |
1798 | struct sk_buff *skb; |
1799 | ||
1800 | if (WARN_ON(!vif)) { | |
1801 | ret = -EINVAL; | |
1802 | goto out; | |
1803 | } | |
1804 | ||
1805 | skb = ieee80211_beacon_get(hw, vif); | |
1806 | ||
1807 | if (!skb) { | |
1808 | ret = -ENOMEM; | |
1809 | goto out; | |
1810 | } | |
1811 | ||
1812 | ath5k_debug_dump_skb(sc, skb, "BC ", 1); | |
1813 | ||
b1ae1edf BG |
1814 | ath5k_txbuf_free_skb(sc, avf->bbuf); |
1815 | avf->bbuf->skb = skb; | |
1816 | ret = ath5k_beacon_setup(sc, avf->bbuf); | |
8a63facc | 1817 | if (ret) |
b1ae1edf | 1818 | avf->bbuf->skb = NULL; |
8a63facc BC |
1819 | out: |
1820 | return ret; | |
1821 | } | |
1822 | ||
fa1c114f JS |
1823 | /* |
1824 | * Transmit a beacon frame at SWBA. Dynamic updates to the | |
1825 | * frame contents are done as needed and the slot time is | |
1826 | * also adjusted based on current state. | |
1827 | * | |
5faaff74 BC |
1828 | * This is called from software irq context (beacontq tasklets) |
1829 | * or user context from ath5k_beacon_config. | |
fa1c114f JS |
1830 | */ |
1831 | static void | |
1832 | ath5k_beacon_send(struct ath5k_softc *sc) | |
1833 | { | |
fa1c114f | 1834 | struct ath5k_hw *ah = sc->ah; |
b1ae1edf BG |
1835 | struct ieee80211_vif *vif; |
1836 | struct ath5k_vif *avf; | |
1837 | struct ath5k_buf *bf; | |
cec8db23 | 1838 | struct sk_buff *skb; |
fa1c114f | 1839 | |
be9b7259 | 1840 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); |
fa1c114f | 1841 | |
fa1c114f JS |
1842 | /* |
1843 | * Check if the previous beacon has gone out. If | |
a180a130 | 1844 | * not, don't don't try to post another: skip this |
fa1c114f JS |
1845 | * period and wait for the next. Missed beacons |
1846 | * indicate a problem and should not occur. If we | |
1847 | * miss too many consecutive beacons reset the device. | |
1848 | */ | |
1849 | if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { | |
1850 | sc->bmisscount++; | |
be9b7259 | 1851 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f | 1852 | "missed %u consecutive beacons\n", sc->bmisscount); |
428cbd4f | 1853 | if (sc->bmisscount > 10) { /* NB: 10 is a guess */ |
be9b7259 | 1854 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f JS |
1855 | "stuck beacon time (%u missed)\n", |
1856 | sc->bmisscount); | |
8d67a031 BR |
1857 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, |
1858 | "stuck beacon, resetting\n"); | |
5faaff74 | 1859 | ieee80211_queue_work(sc->hw, &sc->reset_work); |
fa1c114f JS |
1860 | } |
1861 | return; | |
1862 | } | |
1863 | if (unlikely(sc->bmisscount != 0)) { | |
be9b7259 | 1864 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f JS |
1865 | "resume beacon xmit after %u misses\n", |
1866 | sc->bmisscount); | |
1867 | sc->bmisscount = 0; | |
1868 | } | |
1869 | ||
b93996cf JC |
1870 | if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) || |
1871 | sc->opmode == NL80211_IFTYPE_MESH_POINT) { | |
b1ae1edf BG |
1872 | u64 tsf = ath5k_hw_get_tsf64(ah); |
1873 | u32 tsftu = TSF_TO_TU(tsf); | |
1874 | int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; | |
1875 | vif = sc->bslot[(slot + 1) % ATH_BCBUF]; | |
1876 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, | |
1877 | "tsf %llx tsftu %x intval %u slot %u vif %p\n", | |
1878 | (unsigned long long)tsf, tsftu, sc->bintval, slot, vif); | |
1879 | } else /* only one interface */ | |
1880 | vif = sc->bslot[0]; | |
1881 | ||
1882 | if (!vif) | |
1883 | return; | |
1884 | ||
1885 | avf = (void *)vif->drv_priv; | |
1886 | bf = avf->bbuf; | |
1887 | if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || | |
1888 | sc->opmode == NL80211_IFTYPE_MONITOR)) { | |
1889 | ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); | |
1890 | return; | |
1891 | } | |
1892 | ||
fa1c114f JS |
1893 | /* |
1894 | * Stop any current dma and put the new frame on the queue. | |
1895 | * This should never fail since we check above that no frames | |
1896 | * are still pending on the queue. | |
1897 | */ | |
14fae2d4 | 1898 | if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) { |
428cbd4f | 1899 | ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); |
fa1c114f JS |
1900 | /* NB: hw still stops DMA, so proceed */ |
1901 | } | |
fa1c114f | 1902 | |
d82b577b JC |
1903 | /* refresh the beacon for AP or MESH mode */ |
1904 | if (sc->opmode == NL80211_IFTYPE_AP || | |
1905 | sc->opmode == NL80211_IFTYPE_MESH_POINT) | |
b1ae1edf | 1906 | ath5k_beacon_update(sc->hw, vif); |
1071db86 | 1907 | |
c6e387a2 NK |
1908 | ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); |
1909 | ath5k_hw_start_tx_dma(ah, sc->bhalq); | |
be9b7259 | 1910 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", |
fa1c114f JS |
1911 | sc->bhalq, (unsigned long long)bf->daddr, bf->desc); |
1912 | ||
b1ae1edf | 1913 | skb = ieee80211_get_buffered_bc(sc->hw, vif); |
cec8db23 BC |
1914 | while (skb) { |
1915 | ath5k_tx_queue(sc->hw, skb, sc->cabq); | |
b1ae1edf | 1916 | skb = ieee80211_get_buffered_bc(sc->hw, vif); |
cec8db23 BC |
1917 | } |
1918 | ||
fa1c114f JS |
1919 | sc->bsent++; |
1920 | } | |
1921 | ||
9804b98d BR |
1922 | /** |
1923 | * ath5k_beacon_update_timers - update beacon timers | |
1924 | * | |
1925 | * @sc: struct ath5k_softc pointer we are operating on | |
1926 | * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a | |
1927 | * beacon timer update based on the current HW TSF. | |
1928 | * | |
1929 | * Calculate the next target beacon transmit time (TBTT) based on the timestamp | |
1930 | * of a received beacon or the current local hardware TSF and write it to the | |
1931 | * beacon timer registers. | |
1932 | * | |
1933 | * This is called in a variety of situations, e.g. when a beacon is received, | |
6ba81c2c | 1934 | * when a TSF update has been detected, but also when an new IBSS is created or |
9804b98d BR |
1935 | * when we otherwise know we have to update the timers, but we keep it in this |
1936 | * function to have it all together in one place. | |
1937 | */ | |
cd2c5486 | 1938 | void |
9804b98d | 1939 | ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) |
fa1c114f JS |
1940 | { |
1941 | struct ath5k_hw *ah = sc->ah; | |
9804b98d BR |
1942 | u32 nexttbtt, intval, hw_tu, bc_tu; |
1943 | u64 hw_tsf; | |
fa1c114f JS |
1944 | |
1945 | intval = sc->bintval & AR5K_BEACON_PERIOD; | |
b1ae1edf BG |
1946 | if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { |
1947 | intval /= ATH_BCBUF; /* staggered multi-bss beacons */ | |
1948 | if (intval < 15) | |
1949 | ATH5K_WARN(sc, "intval %u is too low, min 15\n", | |
1950 | intval); | |
1951 | } | |
fa1c114f JS |
1952 | if (WARN_ON(!intval)) |
1953 | return; | |
1954 | ||
9804b98d BR |
1955 | /* beacon TSF converted to TU */ |
1956 | bc_tu = TSF_TO_TU(bc_tsf); | |
fa1c114f | 1957 | |
9804b98d BR |
1958 | /* current TSF converted to TU */ |
1959 | hw_tsf = ath5k_hw_get_tsf64(ah); | |
1960 | hw_tu = TSF_TO_TU(hw_tsf); | |
fa1c114f | 1961 | |
11f21df3 BR |
1962 | #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3 |
1963 | /* We use FUDGE to make sure the next TBTT is ahead of the current TU. | |
1964 | * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer | |
1965 | * configuration we need to make sure it is bigger than that. */ | |
1966 | ||
9804b98d BR |
1967 | if (bc_tsf == -1) { |
1968 | /* | |
1969 | * no beacons received, called internally. | |
1970 | * just need to refresh timers based on HW TSF. | |
1971 | */ | |
1972 | nexttbtt = roundup(hw_tu + FUDGE, intval); | |
1973 | } else if (bc_tsf == 0) { | |
1974 | /* | |
1975 | * no beacon received, probably called by ath5k_reset_tsf(). | |
1976 | * reset TSF to start with 0. | |
1977 | */ | |
1978 | nexttbtt = intval; | |
1979 | intval |= AR5K_BEACON_RESET_TSF; | |
1980 | } else if (bc_tsf > hw_tsf) { | |
1981 | /* | |
1982 | * beacon received, SW merge happend but HW TSF not yet updated. | |
1983 | * not possible to reconfigure timers yet, but next time we | |
1984 | * receive a beacon with the same BSSID, the hardware will | |
1985 | * automatically update the TSF and then we need to reconfigure | |
1986 | * the timers. | |
1987 | */ | |
1988 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
1989 | "need to wait for HW TSF sync\n"); | |
1990 | return; | |
1991 | } else { | |
1992 | /* | |
1993 | * most important case for beacon synchronization between STA. | |
1994 | * | |
1995 | * beacon received and HW TSF has been already updated by HW. | |
1996 | * update next TBTT based on the TSF of the beacon, but make | |
1997 | * sure it is ahead of our local TSF timer. | |
1998 | */ | |
1999 | nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); | |
2000 | } | |
2001 | #undef FUDGE | |
fa1c114f | 2002 | |
036cd1ec BR |
2003 | sc->nexttbtt = nexttbtt; |
2004 | ||
fa1c114f | 2005 | intval |= AR5K_BEACON_ENA; |
fa1c114f | 2006 | ath5k_hw_init_beacon(ah, nexttbtt, intval); |
9804b98d BR |
2007 | |
2008 | /* | |
2009 | * debugging output last in order to preserve the time critical aspect | |
2010 | * of this function | |
2011 | */ | |
2012 | if (bc_tsf == -1) | |
2013 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2014 | "reconfigured timers based on HW TSF\n"); | |
2015 | else if (bc_tsf == 0) | |
2016 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2017 | "reset HW TSF and timers\n"); | |
2018 | else | |
2019 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2020 | "updated timers based on beacon TSF\n"); | |
2021 | ||
2022 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
04f93a87 DM |
2023 | "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", |
2024 | (unsigned long long) bc_tsf, | |
2025 | (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); | |
9804b98d BR |
2026 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", |
2027 | intval & AR5K_BEACON_PERIOD, | |
2028 | intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", | |
2029 | intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); | |
fa1c114f JS |
2030 | } |
2031 | ||
036cd1ec BR |
2032 | /** |
2033 | * ath5k_beacon_config - Configure the beacon queues and interrupts | |
2034 | * | |
2035 | * @sc: struct ath5k_softc pointer we are operating on | |
fa1c114f | 2036 | * |
036cd1ec | 2037 | * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA |
6ba81c2c | 2038 | * interrupts to detect TSF updates only. |
fa1c114f | 2039 | */ |
cd2c5486 | 2040 | void |
fa1c114f JS |
2041 | ath5k_beacon_config(struct ath5k_softc *sc) |
2042 | { | |
2043 | struct ath5k_hw *ah = sc->ah; | |
b5f03956 | 2044 | unsigned long flags; |
fa1c114f | 2045 | |
21800491 | 2046 | spin_lock_irqsave(&sc->block, flags); |
fa1c114f | 2047 | sc->bmisscount = 0; |
dc1968e7 | 2048 | sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); |
fa1c114f | 2049 | |
21800491 | 2050 | if (sc->enable_beacon) { |
fa1c114f | 2051 | /* |
036cd1ec BR |
2052 | * In IBSS mode we use a self-linked tx descriptor and let the |
2053 | * hardware send the beacons automatically. We have to load it | |
fa1c114f | 2054 | * only once here. |
036cd1ec | 2055 | * We use the SWBA interrupt only to keep track of the beacon |
6ba81c2c | 2056 | * timers in order to detect automatic TSF updates. |
fa1c114f JS |
2057 | */ |
2058 | ath5k_beaconq_config(sc); | |
fa1c114f | 2059 | |
036cd1ec BR |
2060 | sc->imask |= AR5K_INT_SWBA; |
2061 | ||
da966bca | 2062 | if (sc->opmode == NL80211_IFTYPE_ADHOC) { |
21800491 | 2063 | if (ath5k_hw_hasveol(ah)) |
da966bca | 2064 | ath5k_beacon_send(sc); |
da966bca JS |
2065 | } else |
2066 | ath5k_beacon_update_timers(sc, -1); | |
21800491 | 2067 | } else { |
14fae2d4 | 2068 | ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq); |
fa1c114f | 2069 | } |
fa1c114f | 2070 | |
c6e387a2 | 2071 | ath5k_hw_set_imr(ah, sc->imask); |
21800491 BC |
2072 | mmiowb(); |
2073 | spin_unlock_irqrestore(&sc->block, flags); | |
fa1c114f JS |
2074 | } |
2075 | ||
428cbd4f NK |
2076 | static void ath5k_tasklet_beacon(unsigned long data) |
2077 | { | |
2078 | struct ath5k_softc *sc = (struct ath5k_softc *) data; | |
2079 | ||
2080 | /* | |
2081 | * Software beacon alert--time to send a beacon. | |
2082 | * | |
2083 | * In IBSS mode we use this interrupt just to | |
2084 | * keep track of the next TBTT (target beacon | |
2085 | * transmission time) in order to detect wether | |
2086 | * automatic TSF updates happened. | |
2087 | */ | |
2088 | if (sc->opmode == NL80211_IFTYPE_ADHOC) { | |
2089 | /* XXX: only if VEOL suppported */ | |
2090 | u64 tsf = ath5k_hw_get_tsf64(sc->ah); | |
2091 | sc->nexttbtt += sc->bintval; | |
2092 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, | |
2093 | "SWBA nexttbtt: %x hw_tu: %x " | |
2094 | "TSF: %llx\n", | |
2095 | sc->nexttbtt, | |
2096 | TSF_TO_TU(tsf), | |
2097 | (unsigned long long) tsf); | |
2098 | } else { | |
2099 | spin_lock(&sc->block); | |
2100 | ath5k_beacon_send(sc); | |
2101 | spin_unlock(&sc->block); | |
2102 | } | |
2103 | } | |
2104 | ||
fa1c114f JS |
2105 | |
2106 | /********************\ | |
2107 | * Interrupt handling * | |
2108 | \********************/ | |
2109 | ||
6a8a3f6b BR |
2110 | static void |
2111 | ath5k_intr_calibration_poll(struct ath5k_hw *ah) | |
2112 | { | |
2111ac0d BR |
2113 | if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && |
2114 | !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) { | |
2115 | /* run ANI only when full calibration is not active */ | |
2116 | ah->ah_cal_next_ani = jiffies + | |
2117 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); | |
2118 | tasklet_schedule(&ah->ah_sc->ani_tasklet); | |
2119 | ||
2120 | } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { | |
6a8a3f6b BR |
2121 | ah->ah_cal_next_full = jiffies + |
2122 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); | |
2123 | tasklet_schedule(&ah->ah_sc->calib); | |
2124 | } | |
2125 | /* we could use SWI to generate enough interrupts to meet our | |
2126 | * calibration interval requirements, if necessary: | |
2127 | * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ | |
2128 | } | |
2129 | ||
132b1c3e | 2130 | irqreturn_t |
fa1c114f JS |
2131 | ath5k_intr(int irq, void *dev_id) |
2132 | { | |
2133 | struct ath5k_softc *sc = dev_id; | |
2134 | struct ath5k_hw *ah = sc->ah; | |
2135 | enum ath5k_int status; | |
2136 | unsigned int counter = 1000; | |
2137 | ||
2138 | if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || | |
4cebb34c FF |
2139 | ((ath5k_get_bus_type(ah) != ATH_AHB) && |
2140 | !ath5k_hw_is_intr_pending(ah)))) | |
fa1c114f JS |
2141 | return IRQ_NONE; |
2142 | ||
2143 | do { | |
fa1c114f JS |
2144 | ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ |
2145 | ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", | |
2146 | status, sc->imask); | |
fa1c114f JS |
2147 | if (unlikely(status & AR5K_INT_FATAL)) { |
2148 | /* | |
2149 | * Fatal errors are unrecoverable. | |
2150 | * Typically these are caused by DMA errors. | |
2151 | */ | |
8d67a031 BR |
2152 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, |
2153 | "fatal int, resetting\n"); | |
5faaff74 | 2154 | ieee80211_queue_work(sc->hw, &sc->reset_work); |
fa1c114f | 2155 | } else if (unlikely(status & AR5K_INT_RXORN)) { |
87d77c4e BR |
2156 | /* |
2157 | * Receive buffers are full. Either the bus is busy or | |
2158 | * the CPU is not fast enough to process all received | |
2159 | * frames. | |
2160 | * Older chipsets need a reset to come out of this | |
2161 | * condition, but we treat it as RX for newer chips. | |
2162 | * We don't know exactly which versions need a reset - | |
2163 | * this guess is copied from the HAL. | |
2164 | */ | |
2165 | sc->stats.rxorn_intr++; | |
8d67a031 BR |
2166 | if (ah->ah_mac_srev < AR5K_SREV_AR5212) { |
2167 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
2168 | "rx overrun, resetting\n"); | |
5faaff74 | 2169 | ieee80211_queue_work(sc->hw, &sc->reset_work); |
8d67a031 | 2170 | } |
87d77c4e BR |
2171 | else |
2172 | tasklet_schedule(&sc->rxtq); | |
fa1c114f JS |
2173 | } else { |
2174 | if (status & AR5K_INT_SWBA) { | |
56d2ac76 | 2175 | tasklet_hi_schedule(&sc->beacontq); |
fa1c114f JS |
2176 | } |
2177 | if (status & AR5K_INT_RXEOL) { | |
2178 | /* | |
2179 | * NB: the hardware should re-read the link when | |
2180 | * RXE bit is written, but it doesn't work at | |
2181 | * least on older hardware revs. | |
2182 | */ | |
b3f194e5 | 2183 | sc->stats.rxeol_intr++; |
fa1c114f JS |
2184 | } |
2185 | if (status & AR5K_INT_TXURN) { | |
2186 | /* bump tx trigger level */ | |
2187 | ath5k_hw_update_tx_triglevel(ah, true); | |
2188 | } | |
4c674c60 | 2189 | if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) |
fa1c114f | 2190 | tasklet_schedule(&sc->rxtq); |
4c674c60 NK |
2191 | if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC |
2192 | | AR5K_INT_TXERR | AR5K_INT_TXEOL)) | |
fa1c114f JS |
2193 | tasklet_schedule(&sc->txtq); |
2194 | if (status & AR5K_INT_BMISS) { | |
1e3e6e8f | 2195 | /* TODO */ |
fa1c114f JS |
2196 | } |
2197 | if (status & AR5K_INT_MIB) { | |
2111ac0d | 2198 | sc->stats.mib_intr++; |
495391d7 | 2199 | ath5k_hw_update_mib_counters(ah); |
2111ac0d | 2200 | ath5k_ani_mib_intr(ah); |
fa1c114f | 2201 | } |
e6a3b616 | 2202 | if (status & AR5K_INT_GPIO) |
e6a3b616 | 2203 | tasklet_schedule(&sc->rf_kill.toggleq); |
a6ae0716 | 2204 | |
fa1c114f | 2205 | } |
4cebb34c FF |
2206 | |
2207 | if (ath5k_get_bus_type(ah) == ATH_AHB) | |
2208 | break; | |
2209 | ||
2516baa6 | 2210 | } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); |
fa1c114f JS |
2211 | |
2212 | if (unlikely(!counter)) | |
2213 | ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); | |
2214 | ||
6a8a3f6b | 2215 | ath5k_intr_calibration_poll(ah); |
6e220662 | 2216 | |
fa1c114f JS |
2217 | return IRQ_HANDLED; |
2218 | } | |
2219 | ||
fa1c114f JS |
2220 | /* |
2221 | * Periodically recalibrate the PHY to account | |
2222 | * for temperature/environment changes. | |
2223 | */ | |
2224 | static void | |
6e220662 | 2225 | ath5k_tasklet_calibrate(unsigned long data) |
fa1c114f JS |
2226 | { |
2227 | struct ath5k_softc *sc = (void *)data; | |
2228 | struct ath5k_hw *ah = sc->ah; | |
2229 | ||
6e220662 | 2230 | /* Only full calibration for now */ |
e65e1d77 | 2231 | ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; |
6e220662 | 2232 | |
fa1c114f | 2233 | ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", |
400ec45a LR |
2234 | ieee80211_frequency_to_channel(sc->curchan->center_freq), |
2235 | sc->curchan->hw_value); | |
fa1c114f | 2236 | |
6f3b414a | 2237 | if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { |
fa1c114f JS |
2238 | /* |
2239 | * Rfgain is out of bounds, reset the chip | |
2240 | * to load new gain values. | |
2241 | */ | |
2242 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); | |
5faaff74 | 2243 | ieee80211_queue_work(sc->hw, &sc->reset_work); |
fa1c114f JS |
2244 | } |
2245 | if (ath5k_hw_phy_calibrate(ah, sc->curchan)) | |
2246 | ATH5K_ERR(sc, "calibration of channel %u failed\n", | |
400ec45a LR |
2247 | ieee80211_frequency_to_channel( |
2248 | sc->curchan->center_freq)); | |
fa1c114f | 2249 | |
0e8e02dd | 2250 | /* Noise floor calibration interrupts rx/tx path while I/Q calibration |
651d9375 BR |
2251 | * doesn't. |
2252 | * TODO: We should stop TX here, so that it doesn't interfere. | |
2253 | * Note that stopping the queues is not enough to stop TX! */ | |
afe86286 BR |
2254 | if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) { |
2255 | ah->ah_cal_next_nf = jiffies + | |
2256 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF); | |
afe86286 | 2257 | ath5k_hw_update_noise_floor(ah); |
afe86286 | 2258 | } |
6e220662 | 2259 | |
e65e1d77 | 2260 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; |
fa1c114f JS |
2261 | } |
2262 | ||
2263 | ||
2111ac0d BR |
2264 | static void |
2265 | ath5k_tasklet_ani(unsigned long data) | |
2266 | { | |
2267 | struct ath5k_softc *sc = (void *)data; | |
2268 | struct ath5k_hw *ah = sc->ah; | |
2269 | ||
2270 | ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; | |
2271 | ath5k_ani_calibration(ah); | |
2272 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; | |
fa1c114f JS |
2273 | } |
2274 | ||
2275 | ||
4edd761f BR |
2276 | static void |
2277 | ath5k_tx_complete_poll_work(struct work_struct *work) | |
2278 | { | |
2279 | struct ath5k_softc *sc = container_of(work, struct ath5k_softc, | |
2280 | tx_complete_work.work); | |
2281 | struct ath5k_txq *txq; | |
2282 | int i; | |
2283 | bool needreset = false; | |
2284 | ||
2285 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { | |
2286 | if (sc->txqs[i].setup) { | |
2287 | txq = &sc->txqs[i]; | |
2288 | spin_lock_bh(&txq->lock); | |
23413296 | 2289 | if (txq->txq_len > 1) { |
4edd761f BR |
2290 | if (txq->txq_poll_mark) { |
2291 | ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, | |
2292 | "TX queue stuck %d\n", | |
2293 | txq->qnum); | |
2294 | needreset = true; | |
923e5b3d | 2295 | txq->txq_stuck++; |
4edd761f BR |
2296 | spin_unlock_bh(&txq->lock); |
2297 | break; | |
2298 | } else { | |
2299 | txq->txq_poll_mark = true; | |
2300 | } | |
2301 | } | |
2302 | spin_unlock_bh(&txq->lock); | |
2303 | } | |
2304 | } | |
2305 | ||
2306 | if (needreset) { | |
2307 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
2308 | "TX queues stuck, resetting\n"); | |
8aec7af9 | 2309 | ath5k_reset(sc, NULL, true); |
4edd761f BR |
2310 | } |
2311 | ||
2312 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, | |
2313 | msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); | |
2314 | } | |
2315 | ||
2316 | ||
8a63facc BC |
2317 | /*************************\ |
2318 | * Initialization routines * | |
2319 | \*************************/ | |
fa1c114f | 2320 | |
132b1c3e FF |
2321 | int |
2322 | ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops) | |
2323 | { | |
2324 | struct ieee80211_hw *hw = sc->hw; | |
2325 | struct ath_common *common; | |
2326 | int ret; | |
2327 | int csz; | |
2328 | ||
2329 | /* Initialize driver private data */ | |
2330 | SET_IEEE80211_DEV(hw, sc->dev); | |
2331 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | | |
b9e61f11 NK |
2332 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
2333 | IEEE80211_HW_SIGNAL_DBM | | |
2334 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
132b1c3e FF |
2335 | |
2336 | hw->wiphy->interface_modes = | |
2337 | BIT(NL80211_IFTYPE_AP) | | |
2338 | BIT(NL80211_IFTYPE_STATION) | | |
2339 | BIT(NL80211_IFTYPE_ADHOC) | | |
2340 | BIT(NL80211_IFTYPE_MESH_POINT); | |
2341 | ||
3de135db BR |
2342 | /* both antennas can be configured as RX or TX */ |
2343 | hw->wiphy->available_antennas_tx = 0x3; | |
2344 | hw->wiphy->available_antennas_rx = 0x3; | |
2345 | ||
132b1c3e FF |
2346 | hw->extra_tx_headroom = 2; |
2347 | hw->channel_change_time = 5000; | |
2348 | ||
2349 | /* | |
2350 | * Mark the device as detached to avoid processing | |
2351 | * interrupts until setup is complete. | |
2352 | */ | |
2353 | __set_bit(ATH_STAT_INVALID, sc->status); | |
2354 | ||
2355 | sc->opmode = NL80211_IFTYPE_STATION; | |
2356 | sc->bintval = 1000; | |
2357 | mutex_init(&sc->lock); | |
2358 | spin_lock_init(&sc->rxbuflock); | |
2359 | spin_lock_init(&sc->txbuflock); | |
2360 | spin_lock_init(&sc->block); | |
2361 | ||
2362 | ||
2363 | /* Setup interrupt handler */ | |
2364 | ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc); | |
2365 | if (ret) { | |
2366 | ATH5K_ERR(sc, "request_irq failed\n"); | |
2367 | goto err; | |
2368 | } | |
2369 | ||
2370 | /* If we passed the test, malloc an ath5k_hw struct */ | |
2371 | sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); | |
2372 | if (!sc->ah) { | |
2373 | ret = -ENOMEM; | |
2374 | ATH5K_ERR(sc, "out of memory\n"); | |
2375 | goto err_irq; | |
2376 | } | |
2377 | ||
2378 | sc->ah->ah_sc = sc; | |
2379 | sc->ah->ah_iobase = sc->iobase; | |
2380 | common = ath5k_hw_common(sc->ah); | |
2381 | common->ops = &ath5k_common_ops; | |
2382 | common->bus_ops = bus_ops; | |
2383 | common->ah = sc->ah; | |
2384 | common->hw = hw; | |
2385 | common->priv = sc; | |
2386 | ||
2387 | /* | |
2388 | * Cache line size is used to size and align various | |
2389 | * structures used to communicate with the hardware. | |
2390 | */ | |
2391 | ath5k_read_cachesize(common, &csz); | |
2392 | common->cachelsz = csz << 2; /* convert to bytes */ | |
2393 | ||
2394 | spin_lock_init(&common->cc_lock); | |
2395 | ||
2396 | /* Initialize device */ | |
2397 | ret = ath5k_hw_init(sc); | |
2398 | if (ret) | |
2399 | goto err_free_ah; | |
2400 | ||
2401 | /* set up multi-rate retry capabilities */ | |
2402 | if (sc->ah->ah_version == AR5K_AR5212) { | |
2403 | hw->max_rates = 4; | |
2404 | hw->max_rate_tries = 11; | |
2405 | } | |
2406 | ||
2407 | hw->vif_data_size = sizeof(struct ath5k_vif); | |
2408 | ||
2409 | /* Finish private driver data initialization */ | |
2410 | ret = ath5k_init(hw); | |
2411 | if (ret) | |
2412 | goto err_ah; | |
2413 | ||
2414 | ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", | |
2415 | ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), | |
2416 | sc->ah->ah_mac_srev, | |
2417 | sc->ah->ah_phy_revision); | |
2418 | ||
2419 | if (!sc->ah->ah_single_chip) { | |
2420 | /* Single chip radio (!RF5111) */ | |
2421 | if (sc->ah->ah_radio_5ghz_revision && | |
2422 | !sc->ah->ah_radio_2ghz_revision) { | |
2423 | /* No 5GHz support -> report 2GHz radio */ | |
2424 | if (!test_bit(AR5K_MODE_11A, | |
2425 | sc->ah->ah_capabilities.cap_mode)) { | |
2426 | ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", | |
2427 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2428 | sc->ah->ah_radio_5ghz_revision), | |
2429 | sc->ah->ah_radio_5ghz_revision); | |
2430 | /* No 2GHz support (5110 and some | |
2431 | * 5Ghz only cards) -> report 5Ghz radio */ | |
2432 | } else if (!test_bit(AR5K_MODE_11B, | |
2433 | sc->ah->ah_capabilities.cap_mode)) { | |
2434 | ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", | |
2435 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2436 | sc->ah->ah_radio_5ghz_revision), | |
2437 | sc->ah->ah_radio_5ghz_revision); | |
2438 | /* Multiband radio */ | |
2439 | } else { | |
2440 | ATH5K_INFO(sc, "RF%s multiband radio found" | |
2441 | " (0x%x)\n", | |
2442 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2443 | sc->ah->ah_radio_5ghz_revision), | |
2444 | sc->ah->ah_radio_5ghz_revision); | |
2445 | } | |
2446 | } | |
2447 | /* Multi chip radio (RF5111 - RF2111) -> | |
2448 | * report both 2GHz/5GHz radios */ | |
2449 | else if (sc->ah->ah_radio_5ghz_revision && | |
2450 | sc->ah->ah_radio_2ghz_revision){ | |
2451 | ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", | |
2452 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2453 | sc->ah->ah_radio_5ghz_revision), | |
2454 | sc->ah->ah_radio_5ghz_revision); | |
2455 | ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", | |
2456 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2457 | sc->ah->ah_radio_2ghz_revision), | |
2458 | sc->ah->ah_radio_2ghz_revision); | |
2459 | } | |
2460 | } | |
2461 | ||
2462 | ath5k_debug_init_device(sc); | |
2463 | ||
2464 | /* ready to process interrupts */ | |
2465 | __clear_bit(ATH_STAT_INVALID, sc->status); | |
2466 | ||
2467 | return 0; | |
2468 | err_ah: | |
2469 | ath5k_hw_deinit(sc->ah); | |
2470 | err_free_ah: | |
2471 | kfree(sc->ah); | |
2472 | err_irq: | |
2473 | free_irq(sc->irq, sc); | |
2474 | err: | |
2475 | return ret; | |
2476 | } | |
2477 | ||
fa1c114f | 2478 | static int |
8a63facc | 2479 | ath5k_stop_locked(struct ath5k_softc *sc) |
cec8db23 | 2480 | { |
8a63facc | 2481 | struct ath5k_hw *ah = sc->ah; |
cec8db23 | 2482 | |
8a63facc BC |
2483 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", |
2484 | test_bit(ATH_STAT_INVALID, sc->status)); | |
2485 | ||
2486 | /* | |
2487 | * Shutdown the hardware and driver: | |
2488 | * stop output from above | |
2489 | * disable interrupts | |
2490 | * turn off timers | |
2491 | * turn off the radio | |
2492 | * clear transmit machinery | |
2493 | * clear receive machinery | |
2494 | * drain and release tx queues | |
2495 | * reclaim beacon resources | |
2496 | * power down hardware | |
2497 | * | |
2498 | * Note that some of this work is not possible if the | |
2499 | * hardware is gone (invalid). | |
2500 | */ | |
2501 | ieee80211_stop_queues(sc->hw); | |
2502 | ||
2503 | if (!test_bit(ATH_STAT_INVALID, sc->status)) { | |
2504 | ath5k_led_off(sc); | |
2505 | ath5k_hw_set_imr(ah, 0); | |
aeae4ac9 | 2506 | synchronize_irq(sc->irq); |
8a63facc | 2507 | ath5k_rx_stop(sc); |
80dac9ee NK |
2508 | ath5k_hw_dma_stop(ah); |
2509 | ath5k_drain_tx_buffs(sc); | |
8a63facc BC |
2510 | ath5k_hw_phy_disable(ah); |
2511 | } | |
2512 | ||
2513 | return 0; | |
cec8db23 BC |
2514 | } |
2515 | ||
cd2c5486 | 2516 | int |
132b1c3e | 2517 | ath5k_init_hw(struct ath5k_softc *sc) |
fa1c114f | 2518 | { |
8a63facc BC |
2519 | struct ath5k_hw *ah = sc->ah; |
2520 | struct ath_common *common = ath5k_hw_common(ah); | |
2521 | int ret, i; | |
fa1c114f | 2522 | |
8a63facc BC |
2523 | mutex_lock(&sc->lock); |
2524 | ||
2525 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); | |
fa1c114f | 2526 | |
fa1c114f | 2527 | /* |
8a63facc BC |
2528 | * Stop anything previously setup. This is safe |
2529 | * no matter this is the first time through or not. | |
fa1c114f | 2530 | */ |
8a63facc | 2531 | ath5k_stop_locked(sc); |
fa1c114f | 2532 | |
8a63facc BC |
2533 | /* |
2534 | * The basic interface to setting the hardware in a good | |
2535 | * state is ``reset''. On return the hardware is known to | |
2536 | * be powered up and with interrupts disabled. This must | |
2537 | * be followed by initialization of the appropriate bits | |
2538 | * and then setup of the interrupt mask. | |
2539 | */ | |
2540 | sc->curchan = sc->hw->conf.channel; | |
8a63facc BC |
2541 | sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | |
2542 | AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | | |
2543 | AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; | |
fa1c114f | 2544 | |
8aec7af9 | 2545 | ret = ath5k_reset(sc, NULL, false); |
8a63facc BC |
2546 | if (ret) |
2547 | goto done; | |
fa1c114f | 2548 | |
8a63facc BC |
2549 | ath5k_rfkill_hw_start(ah); |
2550 | ||
2551 | /* | |
2552 | * Reset the key cache since some parts do not reset the | |
2553 | * contents on initial power up or resume from suspend. | |
2554 | */ | |
2555 | for (i = 0; i < common->keymax; i++) | |
2556 | ath_hw_keyreset(common, (u16) i); | |
2557 | ||
61cde037 NK |
2558 | /* Use higher rates for acks instead of base |
2559 | * rate */ | |
2560 | ah->ah_ack_bitrate_high = true; | |
b1ae1edf BG |
2561 | |
2562 | for (i = 0; i < ARRAY_SIZE(sc->bslot); i++) | |
2563 | sc->bslot[i] = NULL; | |
2564 | ||
8a63facc BC |
2565 | ret = 0; |
2566 | done: | |
2567 | mmiowb(); | |
2568 | mutex_unlock(&sc->lock); | |
4edd761f BR |
2569 | |
2570 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, | |
2571 | msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); | |
2572 | ||
8a63facc BC |
2573 | return ret; |
2574 | } | |
2575 | ||
2576 | static void stop_tasklets(struct ath5k_softc *sc) | |
2577 | { | |
2578 | tasklet_kill(&sc->rxtq); | |
2579 | tasklet_kill(&sc->txtq); | |
2580 | tasklet_kill(&sc->calib); | |
2581 | tasklet_kill(&sc->beacontq); | |
2582 | tasklet_kill(&sc->ani_tasklet); | |
2583 | } | |
2584 | ||
2585 | /* | |
2586 | * Stop the device, grabbing the top-level lock to protect | |
2587 | * against concurrent entry through ath5k_init (which can happen | |
2588 | * if another thread does a system call and the thread doing the | |
2589 | * stop is preempted). | |
2590 | */ | |
cd2c5486 | 2591 | int |
8a63facc BC |
2592 | ath5k_stop_hw(struct ath5k_softc *sc) |
2593 | { | |
2594 | int ret; | |
2595 | ||
2596 | mutex_lock(&sc->lock); | |
2597 | ret = ath5k_stop_locked(sc); | |
2598 | if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { | |
2599 | /* | |
2600 | * Don't set the card in full sleep mode! | |
2601 | * | |
2602 | * a) When the device is in this state it must be carefully | |
2603 | * woken up or references to registers in the PCI clock | |
2604 | * domain may freeze the bus (and system). This varies | |
2605 | * by chip and is mostly an issue with newer parts | |
2606 | * (madwifi sources mentioned srev >= 0x78) that go to | |
2607 | * sleep more quickly. | |
2608 | * | |
2609 | * b) On older chips full sleep results a weird behaviour | |
2610 | * during wakeup. I tested various cards with srev < 0x78 | |
2611 | * and they don't wake up after module reload, a second | |
2612 | * module reload is needed to bring the card up again. | |
2613 | * | |
2614 | * Until we figure out what's going on don't enable | |
2615 | * full chip reset on any chip (this is what Legacy HAL | |
2616 | * and Sam's HAL do anyway). Instead Perform a full reset | |
2617 | * on the device (same as initial state after attach) and | |
2618 | * leave it idle (keep MAC/BB on warm reset) */ | |
2619 | ret = ath5k_hw_on_hold(sc->ah); | |
2620 | ||
2621 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
2622 | "putting device to sleep\n"); | |
fa1c114f JS |
2623 | } |
2624 | ||
8a63facc BC |
2625 | mmiowb(); |
2626 | mutex_unlock(&sc->lock); | |
2627 | ||
2628 | stop_tasklets(sc); | |
2629 | ||
4edd761f BR |
2630 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2631 | ||
8a63facc BC |
2632 | ath5k_rfkill_hw_stop(sc->ah); |
2633 | ||
2634 | return ret; | |
fa1c114f JS |
2635 | } |
2636 | ||
209d889b BC |
2637 | /* |
2638 | * Reset the hardware. If chan is not NULL, then also pause rx/tx | |
2639 | * and change to the given channel. | |
5faaff74 BC |
2640 | * |
2641 | * This should be called with sc->lock. | |
209d889b | 2642 | */ |
fa1c114f | 2643 | static int |
8aec7af9 NK |
2644 | ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, |
2645 | bool skip_pcu) | |
fa1c114f | 2646 | { |
fa1c114f | 2647 | struct ath5k_hw *ah = sc->ah; |
f15a4bb2 | 2648 | struct ath_common *common = ath5k_hw_common(ah); |
344b54b9 | 2649 | int ret, ani_mode; |
fa1c114f JS |
2650 | |
2651 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); | |
fa1c114f | 2652 | |
450464de | 2653 | ath5k_hw_set_imr(ah, 0); |
aeae4ac9 | 2654 | synchronize_irq(sc->irq); |
450464de BC |
2655 | stop_tasklets(sc); |
2656 | ||
344b54b9 NK |
2657 | /* Save ani mode and disable ANI durring |
2658 | * reset. If we don't we might get false | |
2659 | * PHY error interrupts. */ | |
2660 | ani_mode = ah->ah_sc->ani_state.ani_mode; | |
2661 | ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); | |
2662 | ||
19252ecb NK |
2663 | /* We are going to empty hw queues |
2664 | * so we should also free any remaining | |
2665 | * tx buffers */ | |
2666 | ath5k_drain_tx_buffs(sc); | |
930a7622 | 2667 | if (chan) |
209d889b | 2668 | sc->curchan = chan; |
8aec7af9 NK |
2669 | ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL, |
2670 | skip_pcu); | |
d7dc1003 | 2671 | if (ret) { |
fa1c114f JS |
2672 | ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); |
2673 | goto err; | |
2674 | } | |
d7dc1003 | 2675 | |
fa1c114f | 2676 | ret = ath5k_rx_start(sc); |
d7dc1003 | 2677 | if (ret) { |
fa1c114f JS |
2678 | ATH5K_ERR(sc, "can't start recv logic\n"); |
2679 | goto err; | |
2680 | } | |
d7dc1003 | 2681 | |
344b54b9 | 2682 | ath5k_ani_init(ah, ani_mode); |
2111ac0d | 2683 | |
ac559526 BR |
2684 | ah->ah_cal_next_full = jiffies; |
2685 | ah->ah_cal_next_ani = jiffies; | |
afe86286 | 2686 | ah->ah_cal_next_nf = jiffies; |
5dcc03fe | 2687 | ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); |
afe86286 | 2688 | |
f15a4bb2 BR |
2689 | /* clear survey data and cycle counters */ |
2690 | memset(&sc->survey, 0, sizeof(sc->survey)); | |
bb007554 | 2691 | spin_lock_bh(&common->cc_lock); |
f15a4bb2 BR |
2692 | ath_hw_cycle_counters_update(common); |
2693 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
2694 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); | |
bb007554 | 2695 | spin_unlock_bh(&common->cc_lock); |
f15a4bb2 | 2696 | |
fa1c114f | 2697 | /* |
d7dc1003 JS |
2698 | * Change channels and update the h/w rate map if we're switching; |
2699 | * e.g. 11a to 11b/g. | |
2700 | * | |
2701 | * We may be doing a reset in response to an ioctl that changes the | |
2702 | * channel so update any state that might change as a result. | |
fa1c114f JS |
2703 | * |
2704 | * XXX needed? | |
2705 | */ | |
2706 | /* ath5k_chan_change(sc, c); */ | |
fa1c114f | 2707 | |
d7dc1003 JS |
2708 | ath5k_beacon_config(sc); |
2709 | /* intrs are enabled by ath5k_beacon_config */ | |
fa1c114f | 2710 | |
397f385b BR |
2711 | ieee80211_wake_queues(sc->hw); |
2712 | ||
fa1c114f JS |
2713 | return 0; |
2714 | err: | |
2715 | return ret; | |
2716 | } | |
2717 | ||
5faaff74 BC |
2718 | static void ath5k_reset_work(struct work_struct *work) |
2719 | { | |
2720 | struct ath5k_softc *sc = container_of(work, struct ath5k_softc, | |
2721 | reset_work); | |
2722 | ||
2723 | mutex_lock(&sc->lock); | |
8aec7af9 | 2724 | ath5k_reset(sc, NULL, true); |
5faaff74 BC |
2725 | mutex_unlock(&sc->lock); |
2726 | } | |
2727 | ||
8a63facc | 2728 | static int |
132b1c3e | 2729 | ath5k_init(struct ieee80211_hw *hw) |
fa1c114f | 2730 | { |
132b1c3e | 2731 | |
fa1c114f | 2732 | struct ath5k_softc *sc = hw->priv; |
8a63facc BC |
2733 | struct ath5k_hw *ah = sc->ah; |
2734 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); | |
925e0b06 | 2735 | struct ath5k_txq *txq; |
8a63facc | 2736 | u8 mac[ETH_ALEN] = {}; |
fa1c114f JS |
2737 | int ret; |
2738 | ||
fa1c114f | 2739 | |
8a63facc BC |
2740 | /* |
2741 | * Check if the MAC has multi-rate retry support. | |
2742 | * We do this by trying to setup a fake extended | |
2743 | * descriptor. MACs that don't have support will | |
2744 | * return false w/o doing anything. MACs that do | |
2745 | * support it will return true w/o doing anything. | |
2746 | */ | |
2747 | ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); | |
67d2e2df | 2748 | |
8a63facc BC |
2749 | if (ret < 0) |
2750 | goto err; | |
2751 | if (ret > 0) | |
2752 | __set_bit(ATH_STAT_MRRETRY, sc->status); | |
ccfe5552 | 2753 | |
8a63facc BC |
2754 | /* |
2755 | * Collect the channel list. The 802.11 layer | |
2756 | * is resposible for filtering this list based | |
2757 | * on settings like the phy mode and regulatory | |
2758 | * domain restrictions. | |
2759 | */ | |
2760 | ret = ath5k_setup_bands(hw); | |
2761 | if (ret) { | |
2762 | ATH5K_ERR(sc, "can't get channels\n"); | |
2763 | goto err; | |
2764 | } | |
67d2e2df | 2765 | |
8a63facc BC |
2766 | /* |
2767 | * Allocate tx+rx descriptors and populate the lists. | |
2768 | */ | |
aeae4ac9 | 2769 | ret = ath5k_desc_alloc(sc); |
8a63facc BC |
2770 | if (ret) { |
2771 | ATH5K_ERR(sc, "can't allocate descriptors\n"); | |
2772 | goto err; | |
2773 | } | |
fa1c114f | 2774 | |
8a63facc BC |
2775 | /* |
2776 | * Allocate hardware transmit queues: one queue for | |
2777 | * beacon frames and one data queue for each QoS | |
2778 | * priority. Note that hw functions handle resetting | |
2779 | * these queues at the needed time. | |
2780 | */ | |
2781 | ret = ath5k_beaconq_setup(ah); | |
2782 | if (ret < 0) { | |
2783 | ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); | |
2784 | goto err_desc; | |
2785 | } | |
2786 | sc->bhalq = ret; | |
2787 | sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); | |
2788 | if (IS_ERR(sc->cabq)) { | |
2789 | ATH5K_ERR(sc, "can't setup cab queue\n"); | |
2790 | ret = PTR_ERR(sc->cabq); | |
2791 | goto err_bhal; | |
2792 | } | |
fa1c114f | 2793 | |
22d8d9f8 BR |
2794 | /* 5211 and 5212 usually support 10 queues but we better rely on the |
2795 | * capability information */ | |
2796 | if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { | |
2797 | /* This order matches mac80211's queue priority, so we can | |
2798 | * directly use the mac80211 queue number without any mapping */ | |
2799 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); | |
2800 | if (IS_ERR(txq)) { | |
2801 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
2802 | ret = PTR_ERR(txq); | |
2803 | goto err_queues; | |
2804 | } | |
2805 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); | |
2806 | if (IS_ERR(txq)) { | |
2807 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
2808 | ret = PTR_ERR(txq); | |
2809 | goto err_queues; | |
2810 | } | |
2811 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); | |
2812 | if (IS_ERR(txq)) { | |
2813 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
2814 | ret = PTR_ERR(txq); | |
2815 | goto err_queues; | |
2816 | } | |
2817 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); | |
2818 | if (IS_ERR(txq)) { | |
2819 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
2820 | ret = PTR_ERR(txq); | |
2821 | goto err_queues; | |
2822 | } | |
2823 | hw->queues = 4; | |
2824 | } else { | |
2825 | /* older hardware (5210) can only support one data queue */ | |
2826 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); | |
2827 | if (IS_ERR(txq)) { | |
2828 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
2829 | ret = PTR_ERR(txq); | |
2830 | goto err_queues; | |
2831 | } | |
2832 | hw->queues = 1; | |
2833 | } | |
fa1c114f | 2834 | |
8a63facc BC |
2835 | tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); |
2836 | tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); | |
2837 | tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); | |
2838 | tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); | |
2839 | tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc); | |
be009370 | 2840 | |
8a63facc | 2841 | INIT_WORK(&sc->reset_work, ath5k_reset_work); |
4edd761f | 2842 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work); |
fa1c114f | 2843 | |
8a63facc BC |
2844 | ret = ath5k_eeprom_read_mac(ah, mac); |
2845 | if (ret) { | |
aeae4ac9 | 2846 | ATH5K_ERR(sc, "unable to read address from EEPROM\n"); |
8a63facc | 2847 | goto err_queues; |
e30eb4ab | 2848 | } |
2bed03eb | 2849 | |
8a63facc | 2850 | SET_IEEE80211_PERM_ADDR(hw, mac); |
b1ae1edf | 2851 | memcpy(&sc->lladdr, mac, ETH_ALEN); |
8a63facc | 2852 | /* All MAC address bits matter for ACKs */ |
62c58fb4 | 2853 | ath5k_update_bssid_mask_and_opmode(sc, NULL); |
8a63facc BC |
2854 | |
2855 | regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; | |
2856 | ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); | |
2857 | if (ret) { | |
2858 | ATH5K_ERR(sc, "can't initialize regulatory system\n"); | |
2859 | goto err_queues; | |
2860 | } | |
2861 | ||
2862 | ret = ieee80211_register_hw(hw); | |
2863 | if (ret) { | |
2864 | ATH5K_ERR(sc, "can't register ieee80211 hw\n"); | |
2865 | goto err_queues; | |
2866 | } | |
2867 | ||
2868 | if (!ath_is_world_regd(regulatory)) | |
2869 | regulatory_hint(hw->wiphy, regulatory->alpha2); | |
2870 | ||
2871 | ath5k_init_leds(sc); | |
2872 | ||
2873 | ath5k_sysfs_register(sc); | |
2874 | ||
2875 | return 0; | |
2876 | err_queues: | |
2877 | ath5k_txq_release(sc); | |
2878 | err_bhal: | |
2879 | ath5k_hw_release_tx_queue(ah, sc->bhalq); | |
2880 | err_desc: | |
aeae4ac9 | 2881 | ath5k_desc_free(sc); |
8a63facc BC |
2882 | err: |
2883 | return ret; | |
2884 | } | |
2885 | ||
132b1c3e FF |
2886 | void |
2887 | ath5k_deinit_softc(struct ath5k_softc *sc) | |
8a63facc | 2888 | { |
132b1c3e | 2889 | struct ieee80211_hw *hw = sc->hw; |
8a63facc BC |
2890 | |
2891 | /* | |
2892 | * NB: the order of these is important: | |
2893 | * o call the 802.11 layer before detaching ath5k_hw to | |
2894 | * ensure callbacks into the driver to delete global | |
2895 | * key cache entries can be handled | |
2896 | * o reclaim the tx queue data structures after calling | |
2897 | * the 802.11 layer as we'll get called back to reclaim | |
2898 | * node state and potentially want to use them | |
2899 | * o to cleanup the tx queues the hal is called, so detach | |
2900 | * it last | |
2901 | * XXX: ??? detach ath5k_hw ??? | |
2902 | * Other than that, it's straightforward... | |
2903 | */ | |
132b1c3e | 2904 | ath5k_debug_finish_device(sc); |
8a63facc | 2905 | ieee80211_unregister_hw(hw); |
aeae4ac9 | 2906 | ath5k_desc_free(sc); |
8a63facc BC |
2907 | ath5k_txq_release(sc); |
2908 | ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); | |
2909 | ath5k_unregister_leds(sc); | |
2910 | ||
2911 | ath5k_sysfs_unregister(sc); | |
2912 | /* | |
2913 | * NB: can't reclaim these until after ieee80211_ifdetach | |
2914 | * returns because we'll get called back to reclaim node | |
2915 | * state and potentially want to use them. | |
2916 | */ | |
132b1c3e FF |
2917 | ath5k_hw_deinit(sc->ah); |
2918 | free_irq(sc->irq, sc); | |
8a63facc BC |
2919 | } |
2920 | ||
cd2c5486 BR |
2921 | bool |
2922 | ath_any_vif_assoc(struct ath5k_softc *sc) | |
b1ae1edf BG |
2923 | { |
2924 | struct ath_vif_iter_data iter_data; | |
2925 | iter_data.hw_macaddr = NULL; | |
2926 | iter_data.any_assoc = false; | |
2927 | iter_data.need_set_hw_addr = false; | |
2928 | iter_data.found_active = true; | |
2929 | ||
2930 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter, | |
2931 | &iter_data); | |
2932 | return iter_data.any_assoc; | |
2933 | } | |
2934 | ||
cd2c5486 | 2935 | void |
8a63facc BC |
2936 | set_beacon_filter(struct ieee80211_hw *hw, bool enable) |
2937 | { | |
2938 | struct ath5k_softc *sc = hw->priv; | |
2939 | struct ath5k_hw *ah = sc->ah; | |
2940 | u32 rfilt; | |
2941 | rfilt = ath5k_hw_get_rx_filter(ah); | |
2942 | if (enable) | |
2943 | rfilt |= AR5K_RX_FILTER_BEACON; | |
2944 | else | |
2945 | rfilt &= ~AR5K_RX_FILTER_BEACON; | |
2946 | ath5k_hw_set_rx_filter(ah, rfilt); | |
2947 | sc->filter_flags = rfilt; | |
2948 | } |