[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / pci.c

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
#include <linux/pci.h>
#include <linux/pci-aspm.h>
#include <linux/etherdevice.h>
#include <linux/module.h>
#include "../ath.h"
#include "ath5k.h"
#include "debug.h"
#include "base.h"
#include "reg.h"

/* Known PCI ids */
static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
	{ PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
	{ PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
	{ PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
	{ PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
	{ PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
	{ PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
	{ PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
	{ PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
	{ PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
	{ PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
	{ PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
	{ PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);

/* return bus cachesize in 4B word units */
static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
{
	struct ath5k_hw *ah = (struct ath5k_hw *) common->priv;
	u8 u8tmp;

	pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unpleasant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = L1_CACHE_BYTES >> 2;   /* Use the default size */
}

/*
 * Read from eeprom
 */
static bool
ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
{
	struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
	u32 status, timeout;

	/*
	 * Initialize EEPROM access
	 */
	if (ah->ah_version == AR5K_AR5210) {
		AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
		(void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
	} else {
		ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
		AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
				AR5K_EEPROM_CMD_READ);
	}

	for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
		status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
		if (status & AR5K_EEPROM_STAT_RDDONE) {
			if (status & AR5K_EEPROM_STAT_RDERR)
				return false;
			*data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
					0xffff);
			return true;
		}
		udelay(15);
	}

	return false;
}

int ath5k_hw_read_srev(struct ath5k_hw *ah)
{
	ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
	return 0;
}

/*
 * Read the MAC address from eeprom or platform_data
 */
static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
{
	u8 mac_d[ETH_ALEN] = {};
	u32 total, offset;
	u16 data;
	int octet;

	AR5K_EEPROM_READ(0x20, data);

	for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
		AR5K_EEPROM_READ(offset, data);

		total += data;
		mac_d[octet + 1] = data & 0xff;
		mac_d[octet] = data >> 8;
		octet += 2;
	}

	if (!total || total == 3 * 0xffff)
		return -EINVAL;

	memcpy(mac, mac_d, ETH_ALEN);

	return 0;
}


/* Common ath_bus_opts structure */
static const struct ath_bus_ops ath_pci_bus_ops = {
	.ath_bus_type = ATH_PCI,
	.read_cachesize = ath5k_pci_read_cachesize,
	.eeprom_read = ath5k_pci_eeprom_read,
	.eeprom_read_mac = ath5k_pci_eeprom_read_mac,
};

/********************\
* PCI Initialization *
\********************/

static int __devinit
ath5k_pci_probe(struct pci_dev *pdev,
		const struct pci_device_id *id)
{
	void __iomem *mem;
	struct ath5k_hw *ah;
	struct ieee80211_hw *hw;
	int ret;
	u8 csz;

	/*
	 * L0s needs to be disabled on all ath5k cards.
	 *
	 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
	 * by default in the future in 2.6.36) this will also mean both L1 and
	 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
	 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
	 * though but cannot currently undue the effect of a blacklist, for
	 * details you can read pcie_aspm_sanity_check() and see how it adjusts
	 * the device link capability.
	 *
	 * It may be possible in the future to implement some PCI API to allow
	 * drivers to override blacklists for pre 1.1 PCIe but for now it is
	 * best to accept that both L0s and L1 will be disabled completely for
	 * distributions shipping with CONFIG_PCIEASPM rather than having this
	 * issue present. Motivation for adding this new API will be to help
	 * with power consumption for some of these devices.
	 */
	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);

	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "can't enable device\n");
		goto err;
	}

	/* XXX 32-bit addressing only */
	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		dev_err(&pdev->dev, "32-bit DMA not available\n");
		goto err_dis;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES >> 2;
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems.  It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	/* Enable bus mastering */
	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_write_config_byte(pdev, 0x41, 0);

	ret = pci_request_region(pdev, 0, "ath5k");
	if (ret) {
		dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
		goto err_dis;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
		dev_err(&pdev->dev, "cannot remap PCI memory region\n");
		ret = -EIO;
		goto err_reg;
	}

	/*
	 * Allocate hw (mac80211 main struct)
	 * and hw->priv (driver private data)
	 */
	hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops);
	if (hw == NULL) {
		dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
		ret = -ENOMEM;
		goto err_map;
	}

	dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));

	ah = hw->priv;
	ah->hw = hw;
	ah->pdev = pdev;
	ah->dev = &pdev->dev;
	ah->irq = pdev->irq;
	ah->devid = id->device;
	ah->iobase = mem; /* So we can unmap it on detach */

	/* Initialize */
	ret = ath5k_init_ah(ah, &ath_pci_bus_ops);
	if (ret)
		goto err_free;

	/* Set private data */
	pci_set_drvdata(pdev, hw);

	return 0;
err_free:
	ieee80211_free_hw(hw);
err_map:
	pci_iounmap(pdev, mem);
err_reg:
	pci_release_region(pdev, 0);
err_dis:
	pci_disable_device(pdev);
err:
	return ret;
}

static void __devexit
ath5k_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath5k_hw *ah = hw->priv;

	ath5k_deinit_ah(ah);
	pci_iounmap(pdev, ah->iobase);
	pci_release_region(pdev, 0);
	pci_disable_device(pdev);
	ieee80211_free_hw(hw);
}

#ifdef CONFIG_PM_SLEEP
static int ath5k_pci_suspend(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath5k_hw *ah = hw->priv;

	ath5k_led_off(ah);
	return 0;
}

static int ath5k_pci_resume(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath5k_hw *ah = hw->priv;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_write_config_byte(pdev, 0x41, 0);

	ath5k_led_enable(ah);
	return 0;
}

static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
#define ATH5K_PM_OPS	(&ath5k_pm_ops)
#else
#define ATH5K_PM_OPS	NULL
#endif /* CONFIG_PM_SLEEP */

static struct pci_driver ath5k_pci_driver = {
	.name		= KBUILD_MODNAME,
	.id_table	= ath5k_pci_id_table,
	.probe		= ath5k_pci_probe,
	.remove		= __devexit_p(ath5k_pci_remove),
	.driver.pm	= ATH5K_PM_OPS,
};

/*
 * Module init/exit functions
 */
static int __init
init_ath5k_pci(void)
{
	int ret;

	ret = pci_register_driver(&ath5k_pci_driver);
	if (ret) {
		printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
		return ret;
	}

	return 0;
}

static void __exit
exit_ath5k_pci(void)
{
	pci_unregister_driver(&ath5k_pci_driver);
}

module_init(init_ath5k_pci);
module_exit(exit_ath5k_pci);
Commit	Line	Data
e5b046d8 FF	1	/*
	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/nl80211.h>
	18	#include <linux/pci.h>
	19	#include <linux/pci-aspm.h>
fa9bfd61	20	#include <linux/etherdevice.h>
9d9779e7	21	#include <linux/module.h>
e5b046d8 FF	22	#include "../ath.h"
	23	#include "ath5k.h"
	24	#include "debug.h"
	25	#include "base.h"
	26	#include "reg.h"
	27
	28	/* Known PCI ids */
	29	static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
	30	{ PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
	31	{ PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
	32	{ PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
	33	{ PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
	34	{ PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
	35	{ PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
	36	{ PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
	37	{ PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
6a2a0e73 PR	38	{ PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */
	39	{ PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */
	40	{ PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */
	41	{ PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */
	42	{ PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */
	43	{ PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */
e5b046d8 FF	44	{ PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
	45	{ PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
	46	{ PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
	47	{ PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
	48	{ 0 }
	49	};
b7ee1d01	50	MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
e5b046d8 FF	51
	52	/* return bus cachesize in 4B word units */
	53	static void ath5k_pci_read_cachesize(struct ath_common common, int csz)
	54	{
e0d687bd	55	struct ath5k_hw ah = (struct ath5k_hw ) common->priv;
e5b046d8 FF	56	u8 u8tmp;
e5b046d8 FF	57
e0d687bd	58	pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
e5b046d8 FF	59	*csz = (int)u8tmp;
	60
	61	/*
25985edc	62	* This check was put in to avoid "unpleasant" consequences if
e5b046d8 FF	63	* the bootrom has not fully initialized all PCI devices.
	64	* Sometimes the cache line size register is not set
	65	*/
	66
	67	if (*csz == 0)
	68	csz = L1_CACHE_BYTES >> 2; / Use the default size */
	69	}
	70
4aa5d783 FF	71	/*
	72	* Read from eeprom
	73	*/
fda9b7af WD	74	static bool
fda9b7af WD	75	ath5k_pci_eeprom_read(struct ath_common common, u32 offset, u16 data)
4aa5d783 FF	76	{
	77	struct ath5k_hw ah = (struct ath5k_hw ) common->ah;
	78	u32 status, timeout;
	79
	80	/*
	81	* Initialize EEPROM access
	82	*/
	83	if (ah->ah_version == AR5K_AR5210) {
	84	AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
	85	(void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
	86	} else {
	87	ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
	88	AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
	89	AR5K_EEPROM_CMD_READ);
	90	}
	91
	92	for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
	93	status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
	94	if (status & AR5K_EEPROM_STAT_RDDONE) {
	95	if (status & AR5K_EEPROM_STAT_RDERR)
fda9b7af	96	return false;
4aa5d783 FF	97	*data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
4aa5d783 FF	98	0xffff);
fda9b7af	99	return true;
4aa5d783 FF	100	}
	101	udelay(15);
	102	}
	103
fda9b7af	104	return false;
4aa5d783 FF	105	}
4aa5d783 FF	106
e7aecd32 FF	107	int ath5k_hw_read_srev(struct ath5k_hw *ah)
	108	{
	109	ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
	110	return 0;
	111	}
	112
fa9bfd61 FF	113	/*
	114	* Read the MAC address from eeprom or platform_data
	115	*/
	116	static int ath5k_pci_eeprom_read_mac(struct ath5k_hw ah, u8 mac)
	117	{
	118	u8 mac_d[ETH_ALEN] = {};
	119	u32 total, offset;
	120	u16 data;
	121	int octet;
	122
	123	AR5K_EEPROM_READ(0x20, data);
	124
	125	for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
	126	AR5K_EEPROM_READ(offset, data);
	127
	128	total += data;
	129	mac_d[octet + 1] = data & 0xff;
	130	mac_d[octet] = data >> 8;
	131	octet += 2;
	132	}
	133
	134	if (!total \|\| total == 3 * 0xffff)
	135	return -EINVAL;
	136
	137	memcpy(mac, mac_d, ETH_ALEN);
	138
	139	return 0;
	140	}
	141
	142
e5b046d8 FF	143	/* Common ath_bus_opts structure */
	144	static const struct ath_bus_ops ath_pci_bus_ops = {
	145	.ath_bus_type = ATH_PCI,
	146	.read_cachesize = ath5k_pci_read_cachesize,
4aa5d783	147	.eeprom_read = ath5k_pci_eeprom_read,
fa9bfd61	148	.eeprom_read_mac = ath5k_pci_eeprom_read_mac,
e5b046d8 FF	149	};
	150
	151	/********************\
	152	* PCI Initialization *
	153	\********************/
	154
	155	static int __devinit
	156	ath5k_pci_probe(struct pci_dev *pdev,
	157	const struct pci_device_id *id)
	158	{
	159	void __iomem *mem;
e0d687bd	160	struct ath5k_hw *ah;
e5b046d8 FF	161	struct ieee80211_hw *hw;
	162	int ret;
	163	u8 csz;
	164
	165	/*
	166	* L0s needs to be disabled on all ath5k cards.
	167	*
	168	* For distributions shipping with CONFIG_PCIEASPM (this will be enabled
	169	* by default in the future in 2.6.36) this will also mean both L1 and
	170	* L0s will be disabled when a pre 1.1 PCIe device is detected. We do
	171	* know L1 works correctly even for all ath5k pre 1.1 PCIe devices
	172	* though but cannot currently undue the effect of a blacklist, for
	173	* details you can read pcie_aspm_sanity_check() and see how it adjusts
	174	* the device link capability.
	175	*
	176	* It may be possible in the future to implement some PCI API to allow
	177	* drivers to override blacklists for pre 1.1 PCIe but for now it is
	178	* best to accept that both L0s and L1 will be disabled completely for
	179	* distributions shipping with CONFIG_PCIEASPM rather than having this
	180	* issue present. Motivation for adding this new API will be to help
	181	* with power consumption for some of these devices.
	182	*/
	183	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
	184
	185	ret = pci_enable_device(pdev);
	186	if (ret) {
	187	dev_err(&pdev->dev, "can't enable device\n");
	188	goto err;
	189	}
	190
	191	/* XXX 32-bit addressing only */
	192	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	193	if (ret) {
	194	dev_err(&pdev->dev, "32-bit DMA not available\n");
	195	goto err_dis;
	196	}
	197
	198	/*
	199	* Cache line size is used to size and align various
	200	* structures used to communicate with the hardware.
	201	*/
	202	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	203	if (csz == 0) {
	204	/*
	205	* Linux 2.4.18 (at least) writes the cache line size
	206	* register as a 16-bit wide register which is wrong.
	207	* We must have this setup properly for rx buffer
	208	* DMA to work so force a reasonable value here if it
	209	* comes up zero.
	210	*/
	211	csz = L1_CACHE_BYTES >> 2;
	212	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	213	}
	214	/*
	215	* The default setting of latency timer yields poor results,
	216	* set it to the value used by other systems. It may be worth
	217	* tweaking this setting more.
	218	*/
	219	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	220
	221	/* Enable bus mastering */
	222	pci_set_master(pdev);
	223
	224	/*
225	* Disable the RETRY_TIMEOUT register (0x41) to keep
226	* PCI Tx retries from interfering with C3 CPU state.
227	*/
228	pci_write_config_byte(pdev, 0x41, 0);
229
230	ret = pci_request_region(pdev, 0, "ath5k");
231	if (ret) {
232	dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
233	goto err_dis;
234	}
235
236	mem = pci_iomap(pdev, 0, 0);
237	if (!mem) {
e4bbf2f5	238	dev_err(&pdev->dev, "cannot remap PCI memory region\n");
e5b046d8 FF	239	ret = -EIO;
	240	goto err_reg;
	241	}
	242
	243	/*
	244	* Allocate hw (mac80211 main struct)
	245	* and hw->priv (driver private data)
	246	*/
e0d687bd	247	hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops);
e5b046d8 FF	248	if (hw == NULL) {
	249	dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
	250	ret = -ENOMEM;
	251	goto err_map;
	252	}
	253
	254	dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
	255
e0d687bd PR	256	ah = hw->priv;
	257	ah->hw = hw;
	258	ah->pdev = pdev;
	259	ah->dev = &pdev->dev;
	260	ah->irq = pdev->irq;
	261	ah->devid = id->device;
	262	ah->iobase = mem; /* So we can unmap it on detach */
e5b046d8 FF	263
e5b046d8 FF	264	/* Initialize */
bb1f3ad9	265	ret = ath5k_init_ah(ah, &ath_pci_bus_ops);
e5b046d8 FF	266	if (ret)
	267	goto err_free;
	268
	269	/* Set private data */
	270	pci_set_drvdata(pdev, hw);
	271
	272	return 0;
	273	err_free:
	274	ieee80211_free_hw(hw);
	275	err_map:
	276	pci_iounmap(pdev, mem);
	277	err_reg:
	278	pci_release_region(pdev, 0);
	279	err_dis:
	280	pci_disable_device(pdev);
	281	err:
	282	return ret;
	283	}
	284
	285	static void __devexit
	286	ath5k_pci_remove(struct pci_dev *pdev)
	287	{
	288	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
e0d687bd	289	struct ath5k_hw *ah = hw->priv;
e5b046d8	290
bb1f3ad9	291	ath5k_deinit_ah(ah);
e0d687bd	292	pci_iounmap(pdev, ah->iobase);
e5b046d8 FF	293	pci_release_region(pdev, 0);
	294	pci_disable_device(pdev);
	295	ieee80211_free_hw(hw);
	296	}
	297
	298	#ifdef CONFIG_PM_SLEEP
	299	static int ath5k_pci_suspend(struct device *dev)
	300	{
37000b30 PR	301	struct pci_dev *pdev = to_pci_dev(dev);
37000b30 PR	302	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
e0d687bd	303	struct ath5k_hw *ah = hw->priv;
e5b046d8	304
e0d687bd	305	ath5k_led_off(ah);
e5b046d8 FF	306	return 0;
	307	}
	308
	309	static int ath5k_pci_resume(struct device *dev)
	310	{
	311	struct pci_dev *pdev = to_pci_dev(dev);
37000b30	312	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
e0d687bd	313	struct ath5k_hw *ah = hw->priv;
e5b046d8 FF	314
	315	/*
	316	* Suspend/Resume resets the PCI configuration space, so we have to
	317	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	318	* PCI Tx retries from interfering with C3 CPU state
	319	*/
	320	pci_write_config_byte(pdev, 0x41, 0);
	321
e0d687bd	322	ath5k_led_enable(ah);
e5b046d8 FF	323	return 0;
	324	}
	325
	326	static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
	327	#define ATH5K_PM_OPS (&ath5k_pm_ops)
	328	#else
	329	#define ATH5K_PM_OPS NULL
	330	#endif /* CONFIG_PM_SLEEP */
	331
	332	static struct pci_driver ath5k_pci_driver = {
	333	.name = KBUILD_MODNAME,
	334	.id_table = ath5k_pci_id_table,
	335	.probe = ath5k_pci_probe,
	336	.remove = __devexit_p(ath5k_pci_remove),
	337	.driver.pm = ATH5K_PM_OPS,
	338	};
	339
	340	/*
	341	* Module init/exit functions
	342	*/
	343	static int __init
	344	init_ath5k_pci(void)
	345	{
	346	int ret;
	347
	348	ret = pci_register_driver(&ath5k_pci_driver);
	349	if (ret) {
	350	printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
	351	return ret;
	352	}
	353
	354	return 0;
	355	}
	356
	357	static void __exit
	358	exit_ath5k_pci(void)
	359	{
	360	pci_unregister_driver(&ath5k_pci_driver);
	361	}
	362
	363	module_init(init_ath5k_pci);
	364	module_exit(exit_ath5k_pci);