[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / pci.c

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/nl80211.h>
#include <linux/pci.h>
#include <linux/pci-aspm.h>
#include <linux/etherdevice.h>
#include <linux/module.h>
#include "../ath.h"
#include "ath5k.h"
#include "debug.h"
#include "base.h"
#include "reg.h"

/* Known PCI ids */
static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
	{ PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
	{ PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
	{ PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
	{ PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
	{ PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
	{ PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
	{ PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
	{ PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
	{ PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */
	{ PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
	{ PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
	{ PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
	{ PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
	{ PCI_VDEVICE(ATHEROS, 0xff1b) }, /* AR5BXB63 */
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);

/* return bus cachesize in 4B word units */
static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
{
	struct ath5k_hw *ah = (struct ath5k_hw *) common->priv;
	u8 u8tmp;

	pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unpleasant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = L1_CACHE_BYTES >> 2;   /* Use the default size */
}

/*
 * Read from eeprom
 */
static bool
ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
{
	struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
	u32 status, timeout;

	/*
	 * Initialize EEPROM access
	 */
	if (ah->ah_version == AR5K_AR5210) {
		AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
		(void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
	} else {
		ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
		AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
				AR5K_EEPROM_CMD_READ);
	}

	for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
		status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
		if (status & AR5K_EEPROM_STAT_RDDONE) {
			if (status & AR5K_EEPROM_STAT_RDERR)
				return false;
			*data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
					0xffff);
			return true;
		}
		usleep_range(15, 20);
	}

	return false;
}

int ath5k_hw_read_srev(struct ath5k_hw *ah)
{
	ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
	return 0;
}

/*
 * Read the MAC address from eeprom or platform_data
 */
static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
{
	u8 mac_d[ETH_ALEN] = {};
	u32 total, offset;
	u16 data;
	int octet;

	AR5K_EEPROM_READ(0x20, data);

	for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
		AR5K_EEPROM_READ(offset, data);

		total += data;
		mac_d[octet + 1] = data & 0xff;
		mac_d[octet] = data >> 8;
		octet += 2;
	}

	if (!total || total == 3 * 0xffff)
		return -EINVAL;

	memcpy(mac, mac_d, ETH_ALEN);

	return 0;
}


/* Common ath_bus_opts structure */
static const struct ath_bus_ops ath_pci_bus_ops = {
	.ath_bus_type = ATH_PCI,
	.read_cachesize = ath5k_pci_read_cachesize,
	.eeprom_read = ath5k_pci_eeprom_read,
	.eeprom_read_mac = ath5k_pci_eeprom_read_mac,
};

/********************\
* PCI Initialization *
\********************/

static int __devinit
ath5k_pci_probe(struct pci_dev *pdev,
		const struct pci_device_id *id)
{
	void __iomem *mem;
	struct ath5k_hw *ah;
	struct ieee80211_hw *hw;
	int ret;
	u8 csz;

	/*
	 * L0s needs to be disabled on all ath5k cards.
	 *
	 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
	 * by default in the future in 2.6.36) this will also mean both L1 and
	 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
	 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
	 * though but cannot currently undue the effect of a blacklist, for
	 * details you can read pcie_aspm_sanity_check() and see how it adjusts
	 * the device link capability.
	 *
	 * It may be possible in the future to implement some PCI API to allow
	 * drivers to override blacklists for pre 1.1 PCIe but for now it is
	 * best to accept that both L0s and L1 will be disabled completely for
	 * distributions shipping with CONFIG_PCIEASPM rather than having this
	 * issue present. Motivation for adding this new API will be to help
	 * with power consumption for some of these devices.
	 */
	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);

	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "can't enable device\n");
		goto err;
	}

	/* XXX 32-bit addressing only */
	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		dev_err(&pdev->dev, "32-bit DMA not available\n");
		goto err_dis;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES >> 2;
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems.  It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	/* Enable bus mastering */
	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_write_config_byte(pdev, 0x41, 0);

	ret = pci_request_region(pdev, 0, "ath5k");
	if (ret) {
		dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
		goto err_dis;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
		dev_err(&pdev->dev, "cannot remap PCI memory region\n");
		ret = -EIO;
		goto err_reg;
	}

	/*
	 * Allocate hw (mac80211 main struct)
	 * and hw->priv (driver private data)
	 */
	hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops);
	if (hw == NULL) {
		dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
		ret = -ENOMEM;
		goto err_map;
	}

	dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));

	ah = hw->priv;
	ah->hw = hw;
	ah->pdev = pdev;
	ah->dev = &pdev->dev;
	ah->irq = pdev->irq;
	ah->devid = id->device;
	ah->iobase = mem; /* So we can unmap it on detach */

	/* Initialize */
	ret = ath5k_init_ah(ah, &ath_pci_bus_ops);
	if (ret)
		goto err_free;

	/* Set private data */
	pci_set_drvdata(pdev, hw);

	return 0;
err_free:
	ieee80211_free_hw(hw);
err_map:
	pci_iounmap(pdev, mem);
err_reg:
	pci_release_region(pdev, 0);
err_dis:
	pci_disable_device(pdev);
err:
	return ret;
}

static void __devexit
ath5k_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath5k_hw *ah = hw->priv;

	ath5k_deinit_ah(ah);
	pci_iounmap(pdev, ah->iobase);
	pci_release_region(pdev, 0);
	pci_disable_device(pdev);
	ieee80211_free_hw(hw);
}

#ifdef CONFIG_PM_SLEEP
static int ath5k_pci_suspend(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath5k_hw *ah = hw->priv;

	ath5k_led_off(ah);
	return 0;
}

static int ath5k_pci_resume(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath5k_hw *ah = hw->priv;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_write_config_byte(pdev, 0x41, 0);

	ath5k_led_enable(ah);
	return 0;
}

static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
#define ATH5K_PM_OPS	(&ath5k_pm_ops)
#else
#define ATH5K_PM_OPS	NULL
#endif /* CONFIG_PM_SLEEP */

static struct pci_driver ath5k_pci_driver = {
	.name		= KBUILD_MODNAME,
	.id_table	= ath5k_pci_id_table,
	.probe		= ath5k_pci_probe,
	.remove		= __devexit_p(ath5k_pci_remove),
	.driver.pm	= ATH5K_PM_OPS,
};

module_pci_driver(ath5k_pci_driver);
Commit	Line	Data
e5b046d8 FF	1	/*
	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
516304b0 JP	17	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
516304b0 JP	18
e5b046d8 FF	19	#include <linux/nl80211.h>
	20	#include <linux/pci.h>
	21	#include <linux/pci-aspm.h>
fa9bfd61	22	#include <linux/etherdevice.h>
9d9779e7	23	#include <linux/module.h>
e5b046d8 FF	24	#include "../ath.h"
	25	#include "ath5k.h"
	26	#include "debug.h"
	27	#include "base.h"
	28	#include "reg.h"
	29
	30	/* Known PCI ids */
	31	static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
	32	{ PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
	33	{ PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
	34	{ PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
	35	{ PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
	36	{ PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
	37	{ PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
	38	{ PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
	39	{ PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
6a2a0e73 PR	40	{ PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */
	41	{ PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */
	42	{ PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */
	43	{ PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */
	44	{ PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */
	45	{ PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */
e5b046d8 FF	46	{ PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
	47	{ PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
	48	{ PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
	49	{ PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
88642088	50	{ PCI_VDEVICE(ATHEROS, 0xff1b) }, /* AR5BXB63 */
e5b046d8 FF	51	{ 0 }
e5b046d8 FF	52	};
b7ee1d01	53	MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
e5b046d8 FF	54
	55	/* return bus cachesize in 4B word units */
	56	static void ath5k_pci_read_cachesize(struct ath_common common, int csz)
	57	{
e0d687bd	58	struct ath5k_hw ah = (struct ath5k_hw ) common->priv;
e5b046d8 FF	59	u8 u8tmp;
e5b046d8 FF	60
e0d687bd	61	pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
e5b046d8 FF	62	*csz = (int)u8tmp;
	63
	64	/*
25985edc	65	* This check was put in to avoid "unpleasant" consequences if
e5b046d8 FF	66	* the bootrom has not fully initialized all PCI devices.
	67	* Sometimes the cache line size register is not set
	68	*/
	69
	70	if (*csz == 0)
	71	csz = L1_CACHE_BYTES >> 2; / Use the default size */
	72	}
	73
4aa5d783 FF	74	/*
	75	* Read from eeprom
	76	*/
fda9b7af WD	77	static bool
fda9b7af WD	78	ath5k_pci_eeprom_read(struct ath_common common, u32 offset, u16 data)
4aa5d783 FF	79	{
	80	struct ath5k_hw ah = (struct ath5k_hw ) common->ah;
	81	u32 status, timeout;
	82
	83	/*
	84	* Initialize EEPROM access
	85	*/
	86	if (ah->ah_version == AR5K_AR5210) {
	87	AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
	88	(void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
	89	} else {
	90	ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
	91	AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
	92	AR5K_EEPROM_CMD_READ);
	93	}
	94
	95	for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
	96	status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
	97	if (status & AR5K_EEPROM_STAT_RDDONE) {
	98	if (status & AR5K_EEPROM_STAT_RDERR)
fda9b7af	99	return false;
4aa5d783 FF	100	*data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
4aa5d783 FF	101	0xffff);
fda9b7af	102	return true;
4aa5d783	103	}
1846ac3d	104	usleep_range(15, 20);
4aa5d783 FF	105	}
4aa5d783 FF	106
fda9b7af	107	return false;
4aa5d783 FF	108	}
4aa5d783 FF	109
e7aecd32 FF	110	int ath5k_hw_read_srev(struct ath5k_hw *ah)
	111	{
	112	ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
	113	return 0;
	114	}
	115
fa9bfd61 FF	116	/*
	117	* Read the MAC address from eeprom or platform_data
	118	*/
	119	static int ath5k_pci_eeprom_read_mac(struct ath5k_hw ah, u8 mac)
	120	{
	121	u8 mac_d[ETH_ALEN] = {};
	122	u32 total, offset;
	123	u16 data;
	124	int octet;
	125
	126	AR5K_EEPROM_READ(0x20, data);
	127
	128	for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
	129	AR5K_EEPROM_READ(offset, data);
	130
	131	total += data;
	132	mac_d[octet + 1] = data & 0xff;
	133	mac_d[octet] = data >> 8;
	134	octet += 2;
	135	}
	136
	137	if (!total \|\| total == 3 * 0xffff)
	138	return -EINVAL;
	139
	140	memcpy(mac, mac_d, ETH_ALEN);
	141
	142	return 0;
	143	}
	144
	145
e5b046d8 FF	146	/* Common ath_bus_opts structure */
	147	static const struct ath_bus_ops ath_pci_bus_ops = {
	148	.ath_bus_type = ATH_PCI,
	149	.read_cachesize = ath5k_pci_read_cachesize,
4aa5d783	150	.eeprom_read = ath5k_pci_eeprom_read,
fa9bfd61	151	.eeprom_read_mac = ath5k_pci_eeprom_read_mac,
e5b046d8 FF	152	};
	153
	154	/********************\
	155	* PCI Initialization *
	156	\********************/
	157
	158	static int __devinit
	159	ath5k_pci_probe(struct pci_dev *pdev,
	160	const struct pci_device_id *id)
	161	{
	162	void __iomem *mem;
e0d687bd	163	struct ath5k_hw *ah;
e5b046d8 FF	164	struct ieee80211_hw *hw;
	165	int ret;
	166	u8 csz;
	167
	168	/*
	169	* L0s needs to be disabled on all ath5k cards.
	170	*
	171	* For distributions shipping with CONFIG_PCIEASPM (this will be enabled
	172	* by default in the future in 2.6.36) this will also mean both L1 and
	173	* L0s will be disabled when a pre 1.1 PCIe device is detected. We do
	174	* know L1 works correctly even for all ath5k pre 1.1 PCIe devices
	175	* though but cannot currently undue the effect of a blacklist, for
	176	* details you can read pcie_aspm_sanity_check() and see how it adjusts
	177	* the device link capability.
	178	*
	179	* It may be possible in the future to implement some PCI API to allow
	180	* drivers to override blacklists for pre 1.1 PCIe but for now it is
	181	* best to accept that both L0s and L1 will be disabled completely for
	182	* distributions shipping with CONFIG_PCIEASPM rather than having this
	183	* issue present. Motivation for adding this new API will be to help
	184	* with power consumption for some of these devices.
	185	*/
	186	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
	187
	188	ret = pci_enable_device(pdev);
	189	if (ret) {
	190	dev_err(&pdev->dev, "can't enable device\n");
	191	goto err;
	192	}
	193
	194	/* XXX 32-bit addressing only */
	195	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	196	if (ret) {
	197	dev_err(&pdev->dev, "32-bit DMA not available\n");
	198	goto err_dis;
	199	}
	200
	201	/*
	202	* Cache line size is used to size and align various
	203	* structures used to communicate with the hardware.
	204	*/
	205	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	206	if (csz == 0) {
	207	/*
	208	* Linux 2.4.18 (at least) writes the cache line size
	209	* register as a 16-bit wide register which is wrong.
	210	* We must have this setup properly for rx buffer
	211	* DMA to work so force a reasonable value here if it
	212	* comes up zero.
	213	*/
	214	csz = L1_CACHE_BYTES >> 2;
	215	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	216	}
	217	/*
	218	* The default setting of latency timer yields poor results,
	219	* set it to the value used by other systems. It may be worth
	220	* tweaking this setting more.
	221	*/
	222	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	223
	224	/* Enable bus mastering */
	225	pci_set_master(pdev);
	226
	227	/*
228	* Disable the RETRY_TIMEOUT register (0x41) to keep
229	* PCI Tx retries from interfering with C3 CPU state.
230	*/
231	pci_write_config_byte(pdev, 0x41, 0);
232
233	ret = pci_request_region(pdev, 0, "ath5k");
234	if (ret) {
235	dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
236	goto err_dis;
237	}
238
239	mem = pci_iomap(pdev, 0, 0);
240	if (!mem) {
e4bbf2f5	241	dev_err(&pdev->dev, "cannot remap PCI memory region\n");
e5b046d8 FF	242	ret = -EIO;
	243	goto err_reg;
	244	}
	245
	246	/*
	247	* Allocate hw (mac80211 main struct)
	248	* and hw->priv (driver private data)
	249	*/
e0d687bd	250	hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops);
e5b046d8 FF	251	if (hw == NULL) {
	252	dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
	253	ret = -ENOMEM;
	254	goto err_map;
	255	}
	256
	257	dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
	258
e0d687bd PR	259	ah = hw->priv;
	260	ah->hw = hw;
	261	ah->pdev = pdev;
	262	ah->dev = &pdev->dev;
	263	ah->irq = pdev->irq;
	264	ah->devid = id->device;
	265	ah->iobase = mem; /* So we can unmap it on detach */
e5b046d8 FF	266
e5b046d8 FF	267	/* Initialize */
bb1f3ad9	268	ret = ath5k_init_ah(ah, &ath_pci_bus_ops);
e5b046d8 FF	269	if (ret)
	270	goto err_free;
	271
	272	/* Set private data */
	273	pci_set_drvdata(pdev, hw);
	274
	275	return 0;
	276	err_free:
	277	ieee80211_free_hw(hw);
	278	err_map:
	279	pci_iounmap(pdev, mem);
	280	err_reg:
	281	pci_release_region(pdev, 0);
	282	err_dis:
	283	pci_disable_device(pdev);
	284	err:
	285	return ret;
	286	}
	287
	288	static void __devexit
	289	ath5k_pci_remove(struct pci_dev *pdev)
	290	{
	291	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
e0d687bd	292	struct ath5k_hw *ah = hw->priv;
e5b046d8	293
bb1f3ad9	294	ath5k_deinit_ah(ah);
e0d687bd	295	pci_iounmap(pdev, ah->iobase);
e5b046d8 FF	296	pci_release_region(pdev, 0);
	297	pci_disable_device(pdev);
	298	ieee80211_free_hw(hw);
	299	}
	300
	301	#ifdef CONFIG_PM_SLEEP
	302	static int ath5k_pci_suspend(struct device *dev)
	303	{
37000b30 PR	304	struct pci_dev *pdev = to_pci_dev(dev);
37000b30 PR	305	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
e0d687bd	306	struct ath5k_hw *ah = hw->priv;
e5b046d8	307
e0d687bd	308	ath5k_led_off(ah);
e5b046d8 FF	309	return 0;
	310	}
	311
	312	static int ath5k_pci_resume(struct device *dev)
	313	{
	314	struct pci_dev *pdev = to_pci_dev(dev);
37000b30	315	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
e0d687bd	316	struct ath5k_hw *ah = hw->priv;
e5b046d8 FF	317
	318	/*
	319	* Suspend/Resume resets the PCI configuration space, so we have to
	320	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	321	* PCI Tx retries from interfering with C3 CPU state
	322	*/
	323	pci_write_config_byte(pdev, 0x41, 0);
	324
e0d687bd	325	ath5k_led_enable(ah);
e5b046d8 FF	326	return 0;
	327	}
	328
	329	static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
	330	#define ATH5K_PM_OPS (&ath5k_pm_ops)
	331	#else
	332	#define ATH5K_PM_OPS NULL
	333	#endif /* CONFIG_PM_SLEEP */
	334
	335	static struct pci_driver ath5k_pci_driver = {
	336	.name = KBUILD_MODNAME,
	337	.id_table = ath5k_pci_id_table,
	338	.probe = ath5k_pci_probe,
	339	.remove = __devexit_p(ath5k_pci_remove),
	340	.driver.pm = ATH5K_PM_OPS,
	341	};
	342
5b0a3b7e	343	module_pci_driver(ath5k_pci_driver);