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c6e387a2 NK |
1 | /* |
2 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> | |
3 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> | |
4 | * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> | |
5 | * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> | |
6 | * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> | |
7 | * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> | |
8 | * | |
9 | * Permission to use, copy, modify, and distribute this software for any | |
10 | * purpose with or without fee is hereby granted, provided that the above | |
11 | * copyright notice and this permission notice appear in all copies. | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
20 | * | |
21 | */ | |
22 | ||
23 | /*********************************\ | |
24 | * Protocol Control Unit Functions * | |
25 | \*********************************/ | |
26 | ||
bcd8f54a LR |
27 | #include <asm/unaligned.h> |
28 | ||
c6e387a2 NK |
29 | #include "ath5k.h" |
30 | #include "reg.h" | |
31 | #include "debug.h" | |
32 | #include "base.h" | |
33 | ||
61cde037 | 34 | /* |
6a2a0e73 | 35 | * AR5212+ can use higher rates for ack transmission |
61cde037 NK |
36 | * based on current tx rate instead of the base rate. |
37 | * It does this to better utilize channel usage. | |
38 | * This is a mapping between G rates (that cover both | |
39 | * CCK and OFDM) and ack rates that we use when setting | |
40 | * rate -> duration table. This mapping is hw-based so | |
41 | * don't change anything. | |
42 | * | |
43 | * To enable this functionality we must set | |
44 | * ah->ah_ack_bitrate_high to true else base rate is | |
45 | * used (1Mb for CCK, 6Mb for OFDM). | |
46 | */ | |
47 | static const unsigned int ack_rates_high[] = | |
48 | /* Tx -> ACK */ | |
49 | /* 1Mb -> 1Mb */ { 0, | |
50 | /* 2MB -> 2Mb */ 1, | |
51 | /* 5.5Mb -> 2Mb */ 1, | |
52 | /* 11Mb -> 2Mb */ 1, | |
53 | /* 6Mb -> 6Mb */ 4, | |
54 | /* 9Mb -> 6Mb */ 4, | |
55 | /* 12Mb -> 12Mb */ 6, | |
56 | /* 18Mb -> 12Mb */ 6, | |
57 | /* 24Mb -> 24Mb */ 8, | |
58 | /* 36Mb -> 24Mb */ 8, | |
59 | /* 48Mb -> 24Mb */ 8, | |
60 | /* 54Mb -> 24Mb */ 8 }; | |
61 | ||
c6e387a2 | 62 | /*******************\ |
9320b5c4 | 63 | * Helper functions * |
c6e387a2 NK |
64 | \*******************/ |
65 | ||
61cde037 NK |
66 | /** |
67 | * ath5k_hw_get_frame_duration - Get tx time of a frame | |
68 | * | |
69 | * @ah: The &struct ath5k_hw | |
70 | * @len: Frame's length in bytes | |
71 | * @rate: The @struct ieee80211_rate | |
72 | * | |
73 | * Calculate tx duration of a frame given it's rate and length | |
74 | * It extends ieee80211_generic_frame_duration for non standard | |
75 | * bwmodes. | |
76 | */ | |
77 | int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, | |
a27049e2 | 78 | int len, struct ieee80211_rate *rate, bool shortpre) |
61cde037 NK |
79 | { |
80 | struct ath5k_softc *sc = ah->ah_sc; | |
81 | int sifs, preamble, plcp_bits, sym_time; | |
82 | int bitrate, bits, symbols, symbol_bits; | |
83 | int dur; | |
84 | ||
85 | /* Fallback */ | |
86 | if (!ah->ah_bwmode) { | |
a27049e2 FF |
87 | __le16 raw_dur = ieee80211_generic_frame_duration(sc->hw, |
88 | NULL, len, rate); | |
89 | ||
90 | /* subtract difference between long and short preamble */ | |
91 | dur = le16_to_cpu(raw_dur); | |
92 | if (shortpre) | |
93 | dur -= 96; | |
94 | ||
95 | return dur; | |
61cde037 NK |
96 | } |
97 | ||
98 | bitrate = rate->bitrate; | |
99 | preamble = AR5K_INIT_OFDM_PREAMPLE_TIME; | |
100 | plcp_bits = AR5K_INIT_OFDM_PLCP_BITS; | |
101 | sym_time = AR5K_INIT_OFDM_SYMBOL_TIME; | |
102 | ||
103 | switch (ah->ah_bwmode) { | |
104 | case AR5K_BWMODE_40MHZ: | |
105 | sifs = AR5K_INIT_SIFS_TURBO; | |
106 | preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN; | |
107 | break; | |
108 | case AR5K_BWMODE_10MHZ: | |
109 | sifs = AR5K_INIT_SIFS_HALF_RATE; | |
110 | preamble *= 2; | |
111 | sym_time *= 2; | |
112 | break; | |
113 | case AR5K_BWMODE_5MHZ: | |
114 | sifs = AR5K_INIT_SIFS_QUARTER_RATE; | |
115 | preamble *= 4; | |
116 | sym_time *= 4; | |
117 | break; | |
118 | default: | |
119 | sifs = AR5K_INIT_SIFS_DEFAULT_BG; | |
120 | break; | |
121 | } | |
122 | ||
123 | bits = plcp_bits + (len << 3); | |
124 | /* Bit rate is in 100Kbits */ | |
125 | symbol_bits = bitrate * sym_time; | |
126 | symbols = DIV_ROUND_UP(bits * 10, symbol_bits); | |
127 | ||
128 | dur = sifs + preamble + (sym_time * symbols); | |
129 | ||
130 | return dur; | |
131 | } | |
132 | ||
c6e387a2 | 133 | /** |
9320b5c4 | 134 | * ath5k_hw_get_default_slottime - Get the default slot time for current mode |
c6e387a2 NK |
135 | * |
136 | * @ah: The &struct ath5k_hw | |
c6e387a2 | 137 | */ |
71ba1c30 | 138 | unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah) |
c6e387a2 | 139 | { |
9320b5c4 | 140 | struct ieee80211_channel *channel = ah->ah_current_channel; |
3017fcab | 141 | unsigned int slot_time; |
c6e387a2 | 142 | |
3017fcab NK |
143 | switch (ah->ah_bwmode) { |
144 | case AR5K_BWMODE_40MHZ: | |
145 | slot_time = AR5K_INIT_SLOT_TIME_TURBO; | |
146 | break; | |
147 | case AR5K_BWMODE_10MHZ: | |
148 | slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE; | |
149 | break; | |
150 | case AR5K_BWMODE_5MHZ: | |
151 | slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE; | |
152 | break; | |
153 | case AR5K_BWMODE_DEFAULT: | |
3017fcab | 154 | default: |
b1ad1b6f FF |
155 | slot_time = AR5K_INIT_SLOT_TIME_DEFAULT; |
156 | if ((channel->hw_value & CHANNEL_CCK) && !ah->ah_short_slot) | |
3017fcab NK |
157 | slot_time = AR5K_INIT_SLOT_TIME_B; |
158 | break; | |
159 | } | |
c6e387a2 | 160 | |
3017fcab | 161 | return slot_time; |
9320b5c4 | 162 | } |
c6e387a2 | 163 | |
9320b5c4 NK |
164 | /** |
165 | * ath5k_hw_get_default_sifs - Get the default SIFS for current mode | |
166 | * | |
167 | * @ah: The &struct ath5k_hw | |
168 | */ | |
3017fcab | 169 | unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah) |
9320b5c4 NK |
170 | { |
171 | struct ieee80211_channel *channel = ah->ah_current_channel; | |
3017fcab | 172 | unsigned int sifs; |
c6e387a2 | 173 | |
3017fcab NK |
174 | switch (ah->ah_bwmode) { |
175 | case AR5K_BWMODE_40MHZ: | |
176 | sifs = AR5K_INIT_SIFS_TURBO; | |
177 | break; | |
178 | case AR5K_BWMODE_10MHZ: | |
179 | sifs = AR5K_INIT_SIFS_HALF_RATE; | |
180 | break; | |
181 | case AR5K_BWMODE_5MHZ: | |
182 | sifs = AR5K_INIT_SIFS_QUARTER_RATE; | |
183 | break; | |
184 | case AR5K_BWMODE_DEFAULT: | |
185 | sifs = AR5K_INIT_SIFS_DEFAULT_BG; | |
186 | default: | |
187 | if (channel->hw_value & CHANNEL_5GHZ) | |
188 | sifs = AR5K_INIT_SIFS_DEFAULT_A; | |
189 | break; | |
190 | } | |
c6e387a2 | 191 | |
3017fcab | 192 | return sifs; |
c6e387a2 NK |
193 | } |
194 | ||
195 | /** | |
9320b5c4 | 196 | * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics) |
c6e387a2 NK |
197 | * |
198 | * @ah: The &struct ath5k_hw | |
c6e387a2 | 199 | * |
495391d7 BR |
200 | * Reads MIB counters from PCU and updates sw statistics. Is called after a |
201 | * MIB interrupt, because one of these counters might have reached their maximum | |
202 | * and triggered the MIB interrupt, to let us read and clear the counter. | |
203 | * | |
204 | * Is called in interrupt context! | |
c6e387a2 | 205 | */ |
495391d7 | 206 | void ath5k_hw_update_mib_counters(struct ath5k_hw *ah) |
c6e387a2 | 207 | { |
495391d7 | 208 | struct ath5k_statistics *stats = &ah->ah_sc->stats; |
c6e387a2 NK |
209 | |
210 | /* Read-And-Clear */ | |
495391d7 BR |
211 | stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); |
212 | stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); | |
213 | stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); | |
214 | stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); | |
215 | stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); | |
c6e387a2 NK |
216 | } |
217 | ||
c6e387a2 NK |
218 | |
219 | /******************\ | |
220 | * ACK/CTS Timeouts * | |
221 | \******************/ | |
222 | ||
9320b5c4 NK |
223 | /** |
224 | * ath5k_hw_write_rate_duration - fill rate code to duration table | |
225 | * | |
226 | * @ah: the &struct ath5k_hw | |
227 | * @mode: one of enum ath5k_driver_mode | |
228 | * | |
229 | * Write the rate code to duration table upon hw reset. This is a helper for | |
61cde037 | 230 | * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on |
9320b5c4 NK |
231 | * the hardware, based on current mode, for each rate. The rates which are |
232 | * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have | |
233 | * different rate code so we write their value twice (one for long preamble | |
234 | * and one for short). | |
235 | * | |
236 | * Note: Band doesn't matter here, if we set the values for OFDM it works | |
237 | * on both a and g modes. So all we have to do is set values for all g rates | |
61cde037 NK |
238 | * that include all OFDM and CCK rates. |
239 | * | |
9320b5c4 | 240 | */ |
61cde037 | 241 | static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah) |
9320b5c4 NK |
242 | { |
243 | struct ath5k_softc *sc = ah->ah_sc; | |
244 | struct ieee80211_rate *rate; | |
245 | unsigned int i; | |
61cde037 NK |
246 | /* 802.11g covers both OFDM and CCK */ |
247 | u8 band = IEEE80211_BAND_2GHZ; | |
9320b5c4 NK |
248 | |
249 | /* Write rate duration table */ | |
61cde037 | 250 | for (i = 0; i < sc->sbands[band].n_bitrates; i++) { |
9320b5c4 NK |
251 | u32 reg; |
252 | u16 tx_time; | |
253 | ||
61cde037 NK |
254 | if (ah->ah_ack_bitrate_high) |
255 | rate = &sc->sbands[band].bitrates[ack_rates_high[i]]; | |
256 | /* CCK -> 1Mb */ | |
257 | else if (i < 4) | |
258 | rate = &sc->sbands[band].bitrates[0]; | |
259 | /* OFDM -> 6Mb */ | |
260 | else | |
261 | rate = &sc->sbands[band].bitrates[4]; | |
9320b5c4 NK |
262 | |
263 | /* Set ACK timeout */ | |
264 | reg = AR5K_RATE_DUR(rate->hw_value); | |
265 | ||
266 | /* An ACK frame consists of 10 bytes. If you add the FCS, | |
267 | * which ieee80211_generic_frame_duration() adds, | |
268 | * its 14 bytes. Note we use the control rate and not the | |
269 | * actual rate for this rate. See mac80211 tx.c | |
270 | * ieee80211_duration() for a brief description of | |
271 | * what rate we should choose to TX ACKs. */ | |
a27049e2 | 272 | tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false); |
61cde037 | 273 | |
9320b5c4 NK |
274 | ath5k_hw_reg_write(ah, tx_time, reg); |
275 | ||
276 | if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) | |
277 | continue; | |
278 | ||
a27049e2 | 279 | tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, true); |
9320b5c4 NK |
280 | ath5k_hw_reg_write(ah, tx_time, |
281 | reg + (AR5K_SET_SHORT_PREAMBLE << 2)); | |
282 | } | |
283 | } | |
284 | ||
c6e387a2 NK |
285 | /** |
286 | * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU | |
287 | * | |
288 | * @ah: The &struct ath5k_hw | |
289 | * @timeout: Timeout in usec | |
290 | */ | |
626ede6b | 291 | static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) |
c6e387a2 | 292 | { |
3578e6eb LT |
293 | if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) |
294 | <= timeout) | |
c6e387a2 NK |
295 | return -EINVAL; |
296 | ||
297 | AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, | |
3578e6eb | 298 | ath5k_hw_htoclock(ah, timeout)); |
c6e387a2 NK |
299 | |
300 | return 0; | |
301 | } | |
302 | ||
c6e387a2 NK |
303 | /** |
304 | * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU | |
305 | * | |
306 | * @ah: The &struct ath5k_hw | |
307 | * @timeout: Timeout in usec | |
308 | */ | |
626ede6b | 309 | static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) |
c6e387a2 | 310 | { |
3578e6eb LT |
311 | if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) |
312 | <= timeout) | |
c6e387a2 NK |
313 | return -EINVAL; |
314 | ||
315 | AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, | |
3578e6eb | 316 | ath5k_hw_htoclock(ah, timeout)); |
c6e387a2 NK |
317 | |
318 | return 0; | |
319 | } | |
320 | ||
6e08d228 | 321 | |
9320b5c4 NK |
322 | /*******************\ |
323 | * RX filter Control * | |
324 | \*******************/ | |
6e08d228 | 325 | |
c6e387a2 NK |
326 | /** |
327 | * ath5k_hw_set_lladdr - Set station id | |
328 | * | |
329 | * @ah: The &struct ath5k_hw | |
330 | * @mac: The card's mac address | |
331 | * | |
332 | * Set station id on hw using the provided mac address | |
333 | */ | |
334 | int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) | |
335 | { | |
954fecea | 336 | struct ath_common *common = ath5k_hw_common(ah); |
c6e387a2 | 337 | u32 low_id, high_id; |
f6bac3ea | 338 | u32 pcu_reg; |
c6e387a2 | 339 | |
c6e387a2 | 340 | /* Set new station ID */ |
954fecea | 341 | memcpy(common->macaddr, mac, ETH_ALEN); |
c6e387a2 | 342 | |
f6bac3ea BC |
343 | pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; |
344 | ||
bcd8f54a LR |
345 | low_id = get_unaligned_le32(mac); |
346 | high_id = get_unaligned_le16(mac + 4); | |
c6e387a2 NK |
347 | |
348 | ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); | |
f6bac3ea | 349 | ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); |
c6e387a2 NK |
350 | |
351 | return 0; | |
352 | } | |
353 | ||
354 | /** | |
418de6d9 | 355 | * ath5k_hw_set_bssid - Set current BSSID on hw |
c6e387a2 NK |
356 | * |
357 | * @ah: The &struct ath5k_hw | |
c6e387a2 | 358 | * |
418de6d9 NK |
359 | * Sets the current BSSID and BSSID mask we have from the |
360 | * common struct into the hardware | |
c6e387a2 | 361 | */ |
418de6d9 | 362 | void ath5k_hw_set_bssid(struct ath5k_hw *ah) |
c6e387a2 | 363 | { |
954fecea | 364 | struct ath_common *common = ath5k_hw_common(ah); |
c6e387a2 NK |
365 | u16 tim_offset = 0; |
366 | ||
367 | /* | |
418de6d9 | 368 | * Set BSSID mask on 5212 |
c6e387a2 | 369 | */ |
a72d57a8 LR |
370 | if (ah->ah_version == AR5K_AR5212) |
371 | ath_hw_setbssidmask(common); | |
c6e387a2 NK |
372 | |
373 | /* | |
418de6d9 | 374 | * Set BSSID |
c6e387a2 | 375 | */ |
abba0686 LR |
376 | ath5k_hw_reg_write(ah, |
377 | get_unaligned_le32(common->curbssid), | |
a3f86bff | 378 | AR5K_BSS_ID0); |
abba0686 LR |
379 | ath5k_hw_reg_write(ah, |
380 | get_unaligned_le16(common->curbssid + 4) | | |
381 | ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), | |
a3f86bff | 382 | AR5K_BSS_ID1); |
c6e387a2 | 383 | |
be5d6b75 | 384 | if (common->curaid == 0) { |
c6e387a2 NK |
385 | ath5k_hw_disable_pspoll(ah); |
386 | return; | |
387 | } | |
388 | ||
389 | AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, | |
abba0686 | 390 | tim_offset ? tim_offset + 4 : 0); |
c6e387a2 NK |
391 | |
392 | ath5k_hw_enable_pspoll(ah, NULL, 0); | |
393 | } | |
394 | ||
13b81559 | 395 | void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) |
c6e387a2 | 396 | { |
954fecea | 397 | struct ath_common *common = ath5k_hw_common(ah); |
c6e387a2 | 398 | |
f07a6c49 NK |
399 | /* Cache bssid mask so that we can restore it |
400 | * on reset */ | |
954fecea | 401 | memcpy(common->bssidmask, mask, ETH_ALEN); |
13b81559 LR |
402 | if (ah->ah_version == AR5K_AR5212) |
403 | ath_hw_setbssidmask(common); | |
c6e387a2 NK |
404 | } |
405 | ||
c6e387a2 NK |
406 | /* |
407 | * Set multicast filter | |
408 | */ | |
409 | void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) | |
410 | { | |
c6e387a2 NK |
411 | ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); |
412 | ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); | |
413 | } | |
414 | ||
c6e387a2 NK |
415 | /** |
416 | * ath5k_hw_get_rx_filter - Get current rx filter | |
417 | * | |
418 | * @ah: The &struct ath5k_hw | |
419 | * | |
420 | * Returns the RX filter by reading rx filter and | |
421 | * phy error filter registers. RX filter is used | |
422 | * to set the allowed frame types that PCU will accept | |
423 | * and pass to the driver. For a list of frame types | |
424 | * check out reg.h. | |
425 | */ | |
426 | u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) | |
427 | { | |
428 | u32 data, filter = 0; | |
429 | ||
c6e387a2 NK |
430 | filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); |
431 | ||
432 | /*Radar detection for 5212*/ | |
433 | if (ah->ah_version == AR5K_AR5212) { | |
434 | data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); | |
435 | ||
436 | if (data & AR5K_PHY_ERR_FIL_RADAR) | |
437 | filter |= AR5K_RX_FILTER_RADARERR; | |
438 | if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) | |
439 | filter |= AR5K_RX_FILTER_PHYERR; | |
440 | } | |
441 | ||
442 | return filter; | |
443 | } | |
444 | ||
445 | /** | |
446 | * ath5k_hw_set_rx_filter - Set rx filter | |
447 | * | |
448 | * @ah: The &struct ath5k_hw | |
449 | * @filter: RX filter mask (see reg.h) | |
450 | * | |
451 | * Sets RX filter register and also handles PHY error filter | |
452 | * register on 5212 and newer chips so that we have proper PHY | |
453 | * error reporting. | |
454 | */ | |
455 | void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) | |
456 | { | |
457 | u32 data = 0; | |
458 | ||
c6e387a2 NK |
459 | /* Set PHY error filter register on 5212*/ |
460 | if (ah->ah_version == AR5K_AR5212) { | |
461 | if (filter & AR5K_RX_FILTER_RADARERR) | |
462 | data |= AR5K_PHY_ERR_FIL_RADAR; | |
463 | if (filter & AR5K_RX_FILTER_PHYERR) | |
464 | data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; | |
465 | } | |
466 | ||
467 | /* | |
25985edc | 468 | * The AR5210 uses promiscuous mode to detect radar activity |
c6e387a2 NK |
469 | */ |
470 | if (ah->ah_version == AR5K_AR5210 && | |
471 | (filter & AR5K_RX_FILTER_RADARERR)) { | |
472 | filter &= ~AR5K_RX_FILTER_RADARERR; | |
473 | filter |= AR5K_RX_FILTER_PROM; | |
474 | } | |
475 | ||
f07a6c49 | 476 | /*Zero length DMA (phy error reporting) */ |
c6e387a2 NK |
477 | if (data) |
478 | AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); | |
479 | else | |
480 | AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); | |
481 | ||
482 | /*Write RX Filter register*/ | |
483 | ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); | |
484 | ||
485 | /*Write PHY error filter register on 5212*/ | |
486 | if (ah->ah_version == AR5K_AR5212) | |
487 | ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); | |
488 | ||
489 | } | |
490 | ||
491 | ||
492 | /****************\ | |
493 | * Beacon control * | |
494 | \****************/ | |
495 | ||
1c0fc65e BP |
496 | #define ATH5K_MAX_TSF_READ 10 |
497 | ||
c6e387a2 NK |
498 | /** |
499 | * ath5k_hw_get_tsf64 - Get the full 64bit TSF | |
500 | * | |
501 | * @ah: The &struct ath5k_hw | |
502 | * | |
503 | * Returns the current TSF | |
504 | */ | |
505 | u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) | |
506 | { | |
1c0fc65e BP |
507 | u32 tsf_lower, tsf_upper1, tsf_upper2; |
508 | int i; | |
28df897a BR |
509 | unsigned long flags; |
510 | ||
511 | /* This code is time critical - we don't want to be interrupted here */ | |
512 | local_irq_save(flags); | |
1c0fc65e BP |
513 | |
514 | /* | |
515 | * While reading TSF upper and then lower part, the clock is still | |
516 | * counting (or jumping in case of IBSS merge) so we might get | |
517 | * inconsistent values. To avoid this, we read the upper part again | |
518 | * and check it has not been changed. We make the hypothesis that a | |
519 | * maximum of 3 changes can happens in a row (we use 10 as a safe | |
520 | * value). | |
521 | * | |
522 | * Impact on performance is pretty small, since in most cases, only | |
523 | * 3 register reads are needed. | |
524 | */ | |
525 | ||
526 | tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); | |
527 | for (i = 0; i < ATH5K_MAX_TSF_READ; i++) { | |
528 | tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); | |
529 | tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); | |
530 | if (tsf_upper2 == tsf_upper1) | |
531 | break; | |
532 | tsf_upper1 = tsf_upper2; | |
533 | } | |
534 | ||
28df897a BR |
535 | local_irq_restore(flags); |
536 | ||
e4bbf2f5 | 537 | WARN_ON(i == ATH5K_MAX_TSF_READ); |
1c0fc65e | 538 | |
fdd55d14 | 539 | return ((u64)tsf_upper1 << 32) | tsf_lower; |
c6e387a2 NK |
540 | } |
541 | ||
8cab7581 AF |
542 | /** |
543 | * ath5k_hw_set_tsf64 - Set a new 64bit TSF | |
544 | * | |
545 | * @ah: The &struct ath5k_hw | |
546 | * @tsf64: The new 64bit TSF | |
547 | * | |
548 | * Sets the new TSF | |
549 | */ | |
550 | void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) | |
551 | { | |
8cab7581 | 552 | ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); |
0ad65bd7 | 553 | ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); |
8cab7581 AF |
554 | } |
555 | ||
c6e387a2 NK |
556 | /** |
557 | * ath5k_hw_reset_tsf - Force a TSF reset | |
558 | * | |
559 | * @ah: The &struct ath5k_hw | |
560 | * | |
561 | * Forces a TSF reset on PCU | |
562 | */ | |
563 | void ath5k_hw_reset_tsf(struct ath5k_hw *ah) | |
564 | { | |
14be9947 BC |
565 | u32 val; |
566 | ||
14be9947 BC |
567 | val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; |
568 | ||
569 | /* | |
570 | * Each write to the RESET_TSF bit toggles a hardware internal | |
571 | * signal to reset TSF, but if left high it will cause a TSF reset | |
572 | * on the next chip reset as well. Thus we always write the value | |
573 | * twice to clear the signal. | |
574 | */ | |
575 | ath5k_hw_reg_write(ah, val, AR5K_BEACON); | |
576 | ath5k_hw_reg_write(ah, val, AR5K_BEACON); | |
c6e387a2 NK |
577 | } |
578 | ||
579 | /* | |
580 | * Initialize beacon timers | |
581 | */ | |
582 | void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) | |
583 | { | |
584 | u32 timer1, timer2, timer3; | |
585 | ||
c6e387a2 NK |
586 | /* |
587 | * Set the additional timers by mode | |
588 | */ | |
ccfe5552 | 589 | switch (ah->ah_sc->opmode) { |
f07a6c49 | 590 | case NL80211_IFTYPE_MONITOR: |
05c914fe | 591 | case NL80211_IFTYPE_STATION: |
f07a6c49 NK |
592 | /* In STA mode timer1 is used as next wakeup |
593 | * timer and timer2 as next CFP duration start | |
594 | * timer. Both in 1/8TUs. */ | |
595 | /* TODO: PCF handling */ | |
c6e387a2 NK |
596 | if (ah->ah_version == AR5K_AR5210) { |
597 | timer1 = 0xffffffff; | |
598 | timer2 = 0xffffffff; | |
599 | } else { | |
600 | timer1 = 0x0000ffff; | |
601 | timer2 = 0x0007ffff; | |
602 | } | |
f07a6c49 NK |
603 | /* Mark associated AP as PCF incapable for now */ |
604 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); | |
c6e387a2 | 605 | break; |
f07a6c49 NK |
606 | case NL80211_IFTYPE_ADHOC: |
607 | AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); | |
c6e387a2 | 608 | default: |
f07a6c49 NK |
609 | /* On non-STA modes timer1 is used as next DMA |
610 | * beacon alert (DBA) timer and timer2 as next | |
611 | * software beacon alert. Both in 1/8TUs. */ | |
c6e387a2 NK |
612 | timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; |
613 | timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; | |
f07a6c49 | 614 | break; |
c6e387a2 NK |
615 | } |
616 | ||
f07a6c49 NK |
617 | /* Timer3 marks the end of our ATIM window |
618 | * a zero length window is not allowed because | |
619 | * we 'll get no beacons */ | |
4a79f2c5 | 620 | timer3 = next_beacon + 1; |
c6e387a2 NK |
621 | |
622 | /* | |
623 | * Set the beacon register and enable all timers. | |
c6e387a2 | 624 | */ |
35edf8aa | 625 | /* When in AP or Mesh Point mode zero timer0 to start TSF */ |
ccfe5552 BR |
626 | if (ah->ah_sc->opmode == NL80211_IFTYPE_AP || |
627 | ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT) | |
f07a6c49 | 628 | ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); |
428cbd4f NK |
629 | |
630 | ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); | |
c6e387a2 NK |
631 | ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); |
632 | ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); | |
633 | ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); | |
634 | ||
f07a6c49 NK |
635 | /* Force a TSF reset if requested and enable beacons */ |
636 | if (interval & AR5K_BEACON_RESET_TSF) | |
637 | ath5k_hw_reset_tsf(ah); | |
638 | ||
c6e387a2 | 639 | ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | |
f07a6c49 NK |
640 | AR5K_BEACON_ENABLE), |
641 | AR5K_BEACON); | |
642 | ||
643 | /* Flush any pending BMISS interrupts on ISR by | |
644 | * performing a clear-on-write operation on PISR | |
645 | * register for the BMISS bit (writing a bit on | |
6a2a0e73 PR |
646 | * ISR toggles a reset for that bit and leaves |
647 | * the remaining bits intact) */ | |
f07a6c49 NK |
648 | if (ah->ah_version == AR5K_AR5210) |
649 | ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); | |
650 | else | |
651 | ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); | |
652 | ||
6a2a0e73 | 653 | /* TODO: Set enhanced sleep registers on AR5212 |
f07a6c49 NK |
654 | * based on vif->bss_conf params, until then |
655 | * disable power save reporting.*/ | |
656 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); | |
657 | ||
c6e387a2 NK |
658 | } |
659 | ||
7f896126 BR |
660 | /** |
661 | * ath5k_check_timer_win - Check if timer B is timer A + window | |
662 | * | |
663 | * @a: timer a (before b) | |
664 | * @b: timer b (after a) | |
665 | * @window: difference between a and b | |
666 | * @intval: timers are increased by this interval | |
667 | * | |
668 | * This helper function checks if timer B is timer A + window and covers | |
669 | * cases where timer A or B might have already been updated or wrapped | |
670 | * around (Timers are 16 bit). | |
671 | * | |
672 | * Returns true if O.K. | |
673 | */ | |
674 | static inline bool | |
675 | ath5k_check_timer_win(int a, int b, int window, int intval) | |
676 | { | |
677 | /* | |
678 | * 1.) usually B should be A + window | |
679 | * 2.) A already updated, B not updated yet | |
680 | * 3.) A already updated and has wrapped around | |
681 | * 4.) B has wrapped around | |
682 | */ | |
683 | if ((b - a == window) || /* 1.) */ | |
684 | (a - b == intval - window) || /* 2.) */ | |
685 | ((a | 0x10000) - b == intval - window) || /* 3.) */ | |
686 | ((b | 0x10000) - a == window)) /* 4.) */ | |
687 | return true; /* O.K. */ | |
688 | return false; | |
689 | } | |
690 | ||
691 | /** | |
692 | * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct | |
693 | * | |
694 | * @ah: The &struct ath5k_hw | |
695 | * @intval: beacon interval | |
696 | * | |
697 | * This is a workaround for IBSS mode: | |
698 | * | |
699 | * The need for this function arises from the fact that we have 4 separate | |
700 | * HW timer registers (TIMER0 - TIMER3), which are closely related to the | |
701 | * next beacon target time (NBTT), and that the HW updates these timers | |
25985edc LDM |
702 | * separately based on the current TSF value. The hardware increments each |
703 | * timer by the beacon interval, when the local TSF converted to TU is equal | |
7f896126 BR |
704 | * to the value stored in the timer. |
705 | * | |
706 | * The reception of a beacon with the same BSSID can update the local HW TSF | |
707 | * at any time - this is something we can't avoid. If the TSF jumps to a | |
708 | * time which is later than the time stored in a timer, this timer will not | |
709 | * be updated until the TSF in TU wraps around at 16 bit (the size of the | |
710 | * timers) and reaches the time which is stored in the timer. | |
711 | * | |
712 | * The problem is that these timers are closely related to TIMER0 (NBTT) and | |
713 | * that they define a time "window". When the TSF jumps between two timers | |
714 | * (e.g. ATIM and NBTT), the one in the past will be left behind (not | |
715 | * updated), while the one in the future will be updated every beacon | |
716 | * interval. This causes the window to get larger, until the TSF wraps | |
717 | * around as described above and the timer which was left behind gets | |
718 | * updated again. But - because the beacon interval is usually not an exact | |
719 | * divisor of the size of the timers (16 bit), an unwanted "window" between | |
720 | * these timers has developed! | |
721 | * | |
722 | * This is especially important with the ATIM window, because during | |
723 | * the ATIM window only ATIM frames and no data frames are allowed to be | |
724 | * sent, which creates transmission pauses after each beacon. This symptom | |
725 | * has been described as "ramping ping" because ping times increase linearly | |
726 | * for some time and then drop down again. A wrong window on the DMA beacon | |
727 | * timer has the same effect, so we check for these two conditions. | |
728 | * | |
729 | * Returns true if O.K. | |
730 | */ | |
731 | bool | |
732 | ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) | |
733 | { | |
734 | unsigned int nbtt, atim, dma; | |
735 | ||
736 | nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); | |
737 | atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); | |
738 | dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; | |
739 | ||
740 | /* NOTE: SWBA is different. Having a wrong window there does not | |
6a2a0e73 | 741 | * stop us from sending data and this condition is caught by |
7f896126 BR |
742 | * other means (SWBA interrupt) */ |
743 | ||
744 | if (ath5k_check_timer_win(nbtt, atim, 1, intval) && | |
745 | ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP, | |
746 | intval)) | |
747 | return true; /* O.K. */ | |
748 | return false; | |
749 | } | |
750 | ||
6e08d228 LT |
751 | /** |
752 | * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class | |
753 | * | |
754 | * @ah: The &struct ath5k_hw | |
755 | * @coverage_class: IEEE 802.11 coverage class number | |
756 | * | |
eeb8832b | 757 | * Sets IFS intervals and ACK/CTS timeouts for given coverage class. |
6e08d228 LT |
758 | */ |
759 | void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) | |
760 | { | |
761 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ | |
762 | int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; | |
763 | int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; | |
764 | int cts_timeout = ack_timeout; | |
765 | ||
eeb8832b | 766 | ath5k_hw_set_ifs_intervals(ah, slot_time); |
6e08d228 LT |
767 | ath5k_hw_set_ack_timeout(ah, ack_timeout); |
768 | ath5k_hw_set_cts_timeout(ah, cts_timeout); | |
769 | ||
770 | ah->ah_coverage_class = coverage_class; | |
771 | } | |
9320b5c4 NK |
772 | |
773 | /***************************\ | |
774 | * Init/Start/Stop functions * | |
775 | \***************************/ | |
776 | ||
777 | /** | |
778 | * ath5k_hw_start_rx_pcu - Start RX engine | |
779 | * | |
780 | * @ah: The &struct ath5k_hw | |
781 | * | |
782 | * Starts RX engine on PCU so that hw can process RXed frames | |
783 | * (ACK etc). | |
784 | * | |
785 | * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma | |
786 | */ | |
787 | void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) | |
788 | { | |
789 | AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); | |
790 | } | |
791 | ||
792 | /** | |
793 | * at5k_hw_stop_rx_pcu - Stop RX engine | |
794 | * | |
795 | * @ah: The &struct ath5k_hw | |
796 | * | |
797 | * Stops RX engine on PCU | |
798 | */ | |
799 | void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) | |
800 | { | |
801 | AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); | |
802 | } | |
803 | ||
804 | /** | |
805 | * ath5k_hw_set_opmode - Set PCU operating mode | |
806 | * | |
807 | * @ah: The &struct ath5k_hw | |
808 | * @op_mode: &enum nl80211_iftype operating mode | |
809 | * | |
810 | * Configure PCU for the various operating modes (AP/STA etc) | |
811 | */ | |
812 | int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) | |
813 | { | |
814 | struct ath_common *common = ath5k_hw_common(ah); | |
815 | u32 pcu_reg, beacon_reg, low_id, high_id; | |
816 | ||
817 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); | |
818 | ||
819 | /* Preserve rest settings */ | |
820 | pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; | |
821 | pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP | |
822 | | AR5K_STA_ID1_KEYSRCH_MODE | |
823 | | (ah->ah_version == AR5K_AR5210 ? | |
824 | (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); | |
825 | ||
826 | beacon_reg = 0; | |
827 | ||
828 | switch (op_mode) { | |
829 | case NL80211_IFTYPE_ADHOC: | |
830 | pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; | |
831 | beacon_reg |= AR5K_BCR_ADHOC; | |
832 | if (ah->ah_version == AR5K_AR5210) | |
833 | pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; | |
834 | else | |
835 | AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); | |
836 | break; | |
837 | ||
838 | case NL80211_IFTYPE_AP: | |
839 | case NL80211_IFTYPE_MESH_POINT: | |
840 | pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; | |
841 | beacon_reg |= AR5K_BCR_AP; | |
842 | if (ah->ah_version == AR5K_AR5210) | |
843 | pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; | |
844 | else | |
845 | AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); | |
846 | break; | |
847 | ||
848 | case NL80211_IFTYPE_STATION: | |
849 | pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE | |
850 | | (ah->ah_version == AR5K_AR5210 ? | |
851 | AR5K_STA_ID1_PWR_SV : 0); | |
852 | case NL80211_IFTYPE_MONITOR: | |
853 | pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE | |
854 | | (ah->ah_version == AR5K_AR5210 ? | |
855 | AR5K_STA_ID1_NO_PSPOLL : 0); | |
856 | break; | |
857 | ||
858 | default: | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
862 | /* | |
863 | * Set PCU registers | |
864 | */ | |
865 | low_id = get_unaligned_le32(common->macaddr); | |
866 | high_id = get_unaligned_le16(common->macaddr + 4); | |
867 | ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); | |
868 | ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); | |
869 | ||
870 | /* | |
871 | * Set Beacon Control Register on 5210 | |
872 | */ | |
873 | if (ah->ah_version == AR5K_AR5210) | |
874 | ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); | |
875 | ||
876 | return 0; | |
877 | } | |
878 | ||
879 | void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, | |
880 | u8 mode) | |
881 | { | |
882 | /* Set bssid and bssid mask */ | |
883 | ath5k_hw_set_bssid(ah); | |
884 | ||
885 | /* Set PCU config */ | |
886 | ath5k_hw_set_opmode(ah, op_mode); | |
887 | ||
888 | /* Write rate duration table only on AR5212 and if | |
889 | * virtual interface has already been brought up | |
890 | * XXX: rethink this after new mode changes to | |
891 | * mac80211 are integrated */ | |
892 | if (ah->ah_version == AR5K_AR5212 && | |
893 | ah->ah_sc->nvifs) | |
61cde037 | 894 | ath5k_hw_write_rate_duration(ah); |
9320b5c4 NK |
895 | |
896 | /* Set RSSI/BRSSI thresholds | |
897 | * | |
898 | * Note: If we decide to set this value | |
6a2a0e73 | 899 | * dynamically, have in mind that when AR5K_RSSI_THR |
9320b5c4 NK |
900 | * register is read it might return 0x40 if we haven't |
901 | * wrote anything to it plus BMISS RSSI threshold is zeroed. | |
902 | * So doing a save/restore procedure here isn't the right | |
903 | * choice. Instead store it on ath5k_hw */ | |
904 | ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | | |
905 | AR5K_TUNE_BMISS_THRES << | |
906 | AR5K_RSSI_THR_BMISS_S), | |
907 | AR5K_RSSI_THR); | |
908 | ||
909 | /* MIC QoS support */ | |
910 | if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { | |
911 | ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); | |
912 | ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); | |
913 | } | |
914 | ||
915 | /* QoS NOACK Policy */ | |
916 | if (ah->ah_version == AR5K_AR5212) { | |
917 | ath5k_hw_reg_write(ah, | |
918 | AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | | |
919 | AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | | |
920 | AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), | |
921 | AR5K_QOS_NOACK); | |
922 | } | |
923 | ||
924 | /* Restore slot time and ACK timeouts */ | |
925 | if (ah->ah_coverage_class > 0) | |
926 | ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); | |
927 | ||
61cde037 NK |
928 | /* Set ACK bitrate mode (see ack_rates_high) */ |
929 | if (ah->ah_version == AR5K_AR5212) { | |
930 | u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; | |
931 | if (ah->ah_ack_bitrate_high) | |
932 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); | |
933 | else | |
934 | AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); | |
935 | } | |
9320b5c4 NK |
936 | return; |
937 | } |