[deliverable/linux.git] / drivers / net / wireless / ath / ath6kl / hif.h

/*
 * Copyright (c) 2004-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef HIF_H
#define HIF_H

#include "common.h"
#include "core.h"

#include <linux/scatterlist.h>

#define BUS_REQUEST_MAX_NUM                64
#define HIF_MBOX_BLOCK_SIZE                128
#define HIF_MBOX0_BLOCK_SIZE               1

#define HIF_DMA_BUFFER_SIZE (32 * 1024)
#define CMD53_FIXED_ADDRESS 1
#define CMD53_INCR_ADDRESS  2

#define MAX_SCATTER_REQUESTS             4
#define MAX_SCATTER_ENTRIES_PER_REQ      16
#define MAX_SCATTER_REQ_TRANSFER_SIZE    (32 * 1024)

#define MANUFACTURER_ID_AR6003_BASE        0x300
    /* SDIO manufacturer ID and Codes */
#define MANUFACTURER_ID_ATH6KL_BASE_MASK     0xFF00
#define MANUFACTURER_CODE                  0x271	/* Atheros */

/* Mailbox address in SDIO address space */
#define HIF_MBOX_BASE_ADDR                 0x800
#define HIF_MBOX_WIDTH                     0x800

#define HIF_MBOX_END_ADDR  (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1)

/* version 1 of the chip has only a 12K extended mbox range */
#define HIF_MBOX0_EXT_BASE_ADDR  0x4000
#define HIF_MBOX0_EXT_WIDTH      (12*1024)

/* GMBOX addresses */
#define HIF_GMBOX_BASE_ADDR                0x7000
#define HIF_GMBOX_WIDTH                    0x4000

/* interrupt mode register */
#define CCCR_SDIO_IRQ_MODE_REG         0xF0

/* mode to enable special 4-bit interrupt assertion without clock */
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ   (1 << 0)

struct bus_request {
	struct list_head list;

	/* request data */
	u32 address;

	u8 *buffer;
	u32 length;
	u32 request;
	struct htc_packet *packet;
	int status;

	/* this is a scatter request */
	struct hif_scatter_req *scat_req;
};

/* direction of transfer (read/write) */
#define HIF_READ                    0x00000001
#define HIF_WRITE                   0x00000002
#define HIF_DIR_MASK                (HIF_READ | HIF_WRITE)

/*
 *     emode - This indicates the whether the command is to be executed in a
 *             blocking or non-blocking fashion (HIF_SYNCHRONOUS/
 *             HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
 *             implemented using the asynchronous mode allowing the the bus
 *             driver to indicate the completion of operation through the
 *             registered callback routine. The requirement primarily comes
 *             from the contexts these operations get called from (a driver's
 *             transmit context or the ISR context in case of receive).
 *             Support for both of these modes is essential.
 */
#define HIF_SYNCHRONOUS             0x00000010
#define HIF_ASYNCHRONOUS            0x00000020
#define HIF_EMODE_MASK              (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)

/*
 *     dmode - An interface may support different kinds of commands based on
 *             the tradeoff between the amount of data it can carry and the
 *             setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
 *             HIF_BLOCK_BASIS). In case of latter, the data is rounded off
 *             to the nearest block size by padding. The size of the block is
 *             configurable at compile time using the HIF_BLOCK_SIZE and is
 *             negotiated with the target during initialization after the
 *             ATH6KL interrupts are enabled.
 */
#define HIF_BYTE_BASIS              0x00000040
#define HIF_BLOCK_BASIS             0x00000080
#define HIF_DMODE_MASK              (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)

/*
 *     amode - This indicates if the address has to be incremented on ATH6KL
 *             after every read/write operation (HIF?FIXED_ADDRESS/
 *             HIF_INCREMENTAL_ADDRESS).
 */
#define HIF_FIXED_ADDRESS           0x00000100
#define HIF_INCREMENTAL_ADDRESS     0x00000200
#define HIF_AMODE_MASK		  (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)

#define HIF_WR_ASYNC_BYTE_INC					\
	(HIF_WRITE | HIF_ASYNCHRONOUS |				\
	 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)

#define HIF_WR_ASYNC_BLOCK_INC					\
	(HIF_WRITE | HIF_ASYNCHRONOUS |				\
	 HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)

#define HIF_WR_SYNC_BYTE_FIX					\
	(HIF_WRITE | HIF_SYNCHRONOUS |				\
	 HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)

#define HIF_WR_SYNC_BYTE_INC					\
	(HIF_WRITE | HIF_SYNCHRONOUS |				\
	 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)

#define HIF_WR_SYNC_BLOCK_INC					\
	(HIF_WRITE | HIF_SYNCHRONOUS |				\
	 HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)

#define HIF_RD_SYNC_BYTE_INC						\
	(HIF_READ | HIF_SYNCHRONOUS |					\
	 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)

#define HIF_RD_SYNC_BYTE_FIX						\
	(HIF_READ | HIF_SYNCHRONOUS |					\
	 HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)

#define HIF_RD_ASYNC_BLOCK_FIX						\
	(HIF_READ | HIF_ASYNCHRONOUS |					\
	 HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)

#define HIF_RD_SYNC_BLOCK_FIX						\
	(HIF_READ | HIF_SYNCHRONOUS |					\
	 HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)

struct hif_scatter_item {
	u8 *buf;
	int len;
	struct htc_packet *packet;
};

struct hif_scatter_req {
	struct list_head list;
	/* address for the read/write operation */
	u32 addr;

	/* request flags */
	u32 req;

	/* total length of entire transfer */
	u32 len;

	bool virt_scat;

	void (*complete) (struct htc_target *, struct hif_scatter_req *);
	int status;
	int scat_entries;

	struct bus_request *busrequest;
	struct scatterlist *sgentries;

	/* bounce buffer for upper layers to copy to/from */
	u8 *virt_dma_buf;

	struct hif_scatter_item scat_list[1];
};

struct hif_dev_scat_sup_info {
	int max_scat_entries;
	int max_xfer_szper_scatreq;
};

struct ath6kl_hif_ops {
	int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf,
			       u32 len, u32 request);
	int (*write_async)(struct ath6kl *ar, u32 address, u8 *buffer,
			   u32 length, u32 request, struct htc_packet *packet);

	void (*irq_enable)(struct ath6kl *ar);
	void (*irq_disable)(struct ath6kl *ar);

	struct hif_scatter_req *(*scatter_req_get)(struct ath6kl *ar);
	void (*scatter_req_add)(struct ath6kl *ar,
				struct hif_scatter_req *s_req);
	int (*enable_scatter)(struct ath6kl *ar,
			      struct hif_dev_scat_sup_info *info);
	int (*scat_req_rw) (struct ath6kl *ar,
			    struct hif_scatter_req *scat_req);
	void (*cleanup_scatter)(struct ath6kl *ar);
};

#endif
Commit	Line	Data
bdcd8170 KV	1	/*
	2	* Copyright (c) 2004-2011 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef HIF_H
	18	#define HIF_H
	19
	20	#include "common.h"
	21	#include "core.h"
	22
	23	#include <linux/scatterlist.h>
	24
	25	#define BUS_REQUEST_MAX_NUM 64
	26	#define HIF_MBOX_BLOCK_SIZE 128
	27	#define HIF_MBOX0_BLOCK_SIZE 1
	28
	29	#define HIF_DMA_BUFFER_SIZE (32 * 1024)
	30	#define CMD53_FIXED_ADDRESS 1
	31	#define CMD53_INCR_ADDRESS 2
	32
	33	#define MAX_SCATTER_REQUESTS 4
	34	#define MAX_SCATTER_ENTRIES_PER_REQ 16
	35	#define MAX_SCATTER_REQ_TRANSFER_SIZE (32 * 1024)
	36
	37	#define MANUFACTURER_ID_AR6003_BASE 0x300
	38	/* SDIO manufacturer ID and Codes */
	39	#define MANUFACTURER_ID_ATH6KL_BASE_MASK 0xFF00
	40	#define MANUFACTURER_CODE 0x271 /* Atheros */
	41
	42	/* Mailbox address in SDIO address space */
	43	#define HIF_MBOX_BASE_ADDR 0x800
	44	#define HIF_MBOX_WIDTH 0x800
	45
	46	#define HIF_MBOX_END_ADDR (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1)
	47
	48	/* version 1 of the chip has only a 12K extended mbox range */
	49	#define HIF_MBOX0_EXT_BASE_ADDR 0x4000
	50	#define HIF_MBOX0_EXT_WIDTH (12*1024)
	51
	52	/* GMBOX addresses */
	53	#define HIF_GMBOX_BASE_ADDR 0x7000
	54	#define HIF_GMBOX_WIDTH 0x4000
	55
	56	/* interrupt mode register */
	57	#define CCCR_SDIO_IRQ_MODE_REG 0xF0
	58
	59	/* mode to enable special 4-bit interrupt assertion without clock */
	60	#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0)
	61
	62	struct bus_request {
	63	struct list_head list;
	64
65	/* request data */
66	u32 address;
67
68	u8 *buffer;
69	u32 length;
70	u32 request;
71	struct htc_packet *packet;
72	int status;
73
74	/* this is a scatter request */
75	struct hif_scatter_req *scat_req;
76	};
77
78	/* direction of transfer (read/write) */
79	#define HIF_READ 0x00000001
80	#define HIF_WRITE 0x00000002
81	#define HIF_DIR_MASK (HIF_READ \| HIF_WRITE)
82
83	/*
84	* emode - This indicates the whether the command is to be executed in a
85	* blocking or non-blocking fashion (HIF_SYNCHRONOUS/
86	* HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
87	* implemented using the asynchronous mode allowing the the bus
88	* driver to indicate the completion of operation through the
89	* registered callback routine. The requirement primarily comes
90	* from the contexts these operations get called from (a driver's
91	* transmit context or the ISR context in case of receive).
92	* Support for both of these modes is essential.
93	*/
94	#define HIF_SYNCHRONOUS 0x00000010
95	#define HIF_ASYNCHRONOUS 0x00000020
96	#define HIF_EMODE_MASK (HIF_SYNCHRONOUS \| HIF_ASYNCHRONOUS)
97
98	/*
99	* dmode - An interface may support different kinds of commands based on
100	* the tradeoff between the amount of data it can carry and the
101	* setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
102	* HIF_BLOCK_BASIS). In case of latter, the data is rounded off
103	* to the nearest block size by padding. The size of the block is
104	* configurable at compile time using the HIF_BLOCK_SIZE and is
105	* negotiated with the target during initialization after the
106	* ATH6KL interrupts are enabled.
107	*/
108	#define HIF_BYTE_BASIS 0x00000040
109	#define HIF_BLOCK_BASIS 0x00000080
110	#define HIF_DMODE_MASK (HIF_BYTE_BASIS \| HIF_BLOCK_BASIS)
111
112	/*
113	* amode - This indicates if the address has to be incremented on ATH6KL
114	* after every read/write operation (HIF?FIXED_ADDRESS/
115	* HIF_INCREMENTAL_ADDRESS).
116	*/
117	#define HIF_FIXED_ADDRESS 0x00000100
118	#define HIF_INCREMENTAL_ADDRESS 0x00000200
119	#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS \| HIF_INCREMENTAL_ADDRESS)
120
121	#define HIF_WR_ASYNC_BYTE_INC \
122	(HIF_WRITE \| HIF_ASYNCHRONOUS \| \
123	HIF_BYTE_BASIS \| HIF_INCREMENTAL_ADDRESS)
124
125	#define HIF_WR_ASYNC_BLOCK_INC \
126	(HIF_WRITE \| HIF_ASYNCHRONOUS \| \
127	HIF_BLOCK_BASIS \| HIF_INCREMENTAL_ADDRESS)
128
129	#define HIF_WR_SYNC_BYTE_FIX \
130	(HIF_WRITE \| HIF_SYNCHRONOUS \| \
131	HIF_BYTE_BASIS \| HIF_FIXED_ADDRESS)
132
133	#define HIF_WR_SYNC_BYTE_INC \
134	(HIF_WRITE \| HIF_SYNCHRONOUS \| \
135	HIF_BYTE_BASIS \| HIF_INCREMENTAL_ADDRESS)
136
137	#define HIF_WR_SYNC_BLOCK_INC \
138	(HIF_WRITE \| HIF_SYNCHRONOUS \| \
139	HIF_BLOCK_BASIS \| HIF_INCREMENTAL_ADDRESS)
140
141	#define HIF_RD_SYNC_BYTE_INC \
142	(HIF_READ \| HIF_SYNCHRONOUS \| \
143	HIF_BYTE_BASIS \| HIF_INCREMENTAL_ADDRESS)
144
145	#define HIF_RD_SYNC_BYTE_FIX \
146	(HIF_READ \| HIF_SYNCHRONOUS \| \
147	HIF_BYTE_BASIS \| HIF_FIXED_ADDRESS)
148
149	#define HIF_RD_ASYNC_BLOCK_FIX \
150	(HIF_READ \| HIF_ASYNCHRONOUS \| \
151	HIF_BLOCK_BASIS \| HIF_FIXED_ADDRESS)
152
153	#define HIF_RD_SYNC_BLOCK_FIX \
154	(HIF_READ \| HIF_SYNCHRONOUS \| \
155	HIF_BLOCK_BASIS \| HIF_FIXED_ADDRESS)
156
157	struct hif_scatter_item {
158	u8 *buf;
159	int len;
160	struct htc_packet *packet;
161	};
162
163	struct hif_scatter_req {
164	struct list_head list;
165	/* address for the read/write operation */
166	u32 addr;
167
168	/* request flags */
169	u32 req;
170
171	/* total length of entire transfer */
172	u32 len;
173
4a005c3e VT	174	bool virt_scat;
4a005c3e VT	175
e041c7f9	176	void (complete) (struct htc_target , struct hif_scatter_req *);
bdcd8170	177	int status;
bdcd8170 KV	178	int scat_entries;
bdcd8170 KV	179
d4df7890 VT	180	struct bus_request *busrequest;
d4df7890 VT	181	struct scatterlist *sgentries;
bdcd8170 KV	182
	183	/* bounce buffer for upper layers to copy to/from */
	184	u8 *virt_dma_buf;
	185
	186	struct hif_scatter_item scat_list[1];
	187	};
	188
	189	struct hif_dev_scat_sup_info {
bdcd8170 KV	190	int max_scat_entries;
	191	int max_xfer_szper_scatreq;
	192	};
	193
bdcd8170 KV	194	struct ath6kl_hif_ops {
	195	int (read_write_sync)(struct ath6kl ar, u32 addr, u8 *buf,
	196	u32 len, u32 request);
	197	int (write_async)(struct ath6kl ar, u32 address, u8 *buffer,
	198	u32 length, u32 request, struct htc_packet *packet);
	199
	200	void (irq_enable)(struct ath6kl ar);
	201	void (irq_disable)(struct ath6kl ar);
	202
	203	struct hif_scatter_req (scatter_req_get)(struct ath6kl *ar);
	204	void (scatter_req_add)(struct ath6kl ar,
	205	struct hif_scatter_req *s_req);
	206	int (enable_scatter)(struct ath6kl ar,
	207	struct hif_dev_scat_sup_info *info);
f74a7361 VT	208	int (scat_req_rw) (struct ath6kl ar,
f74a7361 VT	209	struct hif_scatter_req *scat_req);
bdcd8170 KV	210	void (cleanup_scatter)(struct ath6kl ar);
	211	};
	212
	213	#endif